# instructions

platform: x86
mnem: CVTPD2PS
description:
CVTPD2PS - Convert Packed Double-Precision FP Values to Packed Single-Precision FP Values:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                               
| 66 0F 5A /r CVTPD2PS xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert two packed double-precision       
|                                        |      |               |                   | floatingpoint values in xmm2/m128 to      
|                                        |      |               |                   | two packed single-precision floating-point
|                                        |      |               |                   | values in xmm1.                           
| VEX.128.66.0F.WIG 5A /r VCVTPD2PS xmm1,| RM   | V/V           | AVX               | Convert two packed double-precision       
| xmm2/m128                              |      |               |                   | floatingpoint values in xmm2/mem to       
|                                        |      |               |                   | two singleprecision floating-point values 
|                                        |      |               |                   | in xmm1.                                  
| VEX.256.66.0F.WIG 5A /r VCVTPD2PS xmm1,| RM   | V/V           | AVX               | Convert four packed double-precision      
| ymm2/m256                              |      |               |                   | floatingpoint values in ymm2/mem to       
|                                        |      |               |                   | four singleprecision floating-point       
|                                        |      |               |                   | values in xmm1.                           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed double-precision floating-point values in the source operand
(second operand) to two packed single-precision floating-point values in the
destination operand (first operand). When a conversion is inexact, the value
returned is rounded according to the rounding control bits in the MXCSR register.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. Bits[127:64] of the destination XMM register are zeroed. However,
the upper bits (VLMAX-1:128) of the corresponding YMM register destination are
unmodified. VEX.128 encoded version: The source operand is an XMM register or
128- bit memory location. The destination operation is a YMM register. The upper
bits (VLMAX-1:64) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is an XMM register. The upper bits (255:128)
of the corresponding YMM register destination are zeroed. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD.

| SRC DEST| X3 Figure 3-12.| X2 0 VCVTPD2PS (VEX.256 encoded version)| X1 X2| X0 X0
Operation:

CVTPD2PS (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[127:64] <- 0
DEST[VLMAX-1:128] (unmodified)
VCVTPD2PS (VEX.128 encoded version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[VLMAX-1:64] <- 0
VCVTPD2PS (VEX.256 encoded version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[95:64] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])
DEST[127:96] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)
DEST[255:128]<- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPD2PS:| __m128 _mm_cvtpd_ps(__m128d a)    
| CVTPD2PS:| __m256 _mm256_cvtpd_ps (__m256d a)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTPI2PD
description:
CVTPI2PD - Convert Packed Dword Integers to Packed Double-Precision FP Values:
| Opcode/Instruction               | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 66 0F 2A /r CVTPI2PD xmm, mm/m64*| RM   | Valid      | Valid          | Convert two packed signed doubleword  
|                                  |      |            |                | integers from mm/mem64 to two packed  
|                                  |      |            |                | double-precision floating-point values
|                                  |      |            |                | in xmm.                               
Notes: *Operation is different for different operand sets; see the Description
section.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed signed doubleword integers in the source operand (second
operand) to two packed doubleprecision floating-point values in the destination
operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand is an XMM register. In addition, depending on the operand
configuration:

 - For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX
technology operation (that is, the x87 FPU top-of-stack pointer is set to 0
and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed
while an x87 FPU floating-point exception is pending, the exception is handled
before the CVTPI2PD instruction is executed.
 - For operands xmm, m64: the instruction does not cause a transition to MMX technology
and does not take x87 FPU exceptions.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPI2PD:| __m128d _mm_cvtpi32_pd(__m64 a)

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Table 22-6, “Exception Conditions for Legacy SIMD/MMX Instructions with
XMM and without FP Exception,” in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3B.


platform: x86
mnem: CVTPI2PS
description:
CVTPI2PS - Convert Packed Dword Integers to Packed Single-Precision FP Values:
| Opcode/Instruction           | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 0F 2A /r CVTPI2PS xmm, mm/m64| RM   | Valid      | Valid          | Convert two signed doubleword integers
|                              |      |            |                | from mm/m64 to two single-precision   
|                              |      |            |                | floating-point values in xmm.         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed signed doubleword integers in the source operand (second
operand) to two packed singleprecision floating-point values in the destination
operand (first operand).

The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand is an XMM register. The results are stored in the low
quadword of the destination operand, and the high quadword remains unchanged.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register.

This instruction causes a transition from x87 FPU to MMX technology operation
(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word
is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPI2PS
instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
(* High quadword of destination unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPI2PS:| __m128 _mm_cvtpi32_ps(__m128 a, __m64
|          | b)                                   

SIMD Floating-Point Exceptions:
Precision.


Other Exceptions:
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with
XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B.


platform: x86
mnem: CVTPS2DQ
description:
CVTPS2DQ - Convert Packed Single-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                              
| 66 0F 5B /r CVTPS2DQ xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert four packed single-precision     
|                                        |      |               |                   | floatingpoint values from xmm2/m128      
|                                        |      |               |                   | to four packed signed doubleword integers
|                                        |      |               |                   | in xmm1.                                 
| VEX.128.66.0F.WIG 5B /r VCVTPS2DQ xmm1,| RM   | V/V           | AVX               | Convert four packed single precision     
| xmm2/m128                              |      |               |                   | floatingpoint values from xmm2/mem to    
|                                        |      |               |                   | four packed signed doubleword values     
|                                        |      |               |                   | in xmm1.                                 
| VEX.256.66.0F.WIG 5B /r VCVTPS2DQ ymm1,| RM   | V/V           | AVX               | Convert eight packed single precision    
| ymm2/m256                              |      |               |                   | floatingpoint values from ymm2/mem to    
|                                        |      |               |                   | eight packed signed doubleword values    
|                                        |      |               |                   | in ymm1.                                 

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts four or eight packed single-precision floating-point values in the
source operand to four or eight signed doubleword integers in the destination
operand.

When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (80000000H)
is returned.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 128- bit memory location. The destination operation is a YMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is a YMM register. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD.

Operation:

CVTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[VLMAX-1:128] (unmodified)
VCVTPS2DQ (VEX.128 encoded version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[VLMAX-1:128] <- 0
VCVTPS2DQ (VEX.256 encoded version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)
DEST[159:128] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])
DEST[191:160] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])
DEST[223:192] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])
DEST[255:224] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPS2DQ: | __m128i _mm_cvtps_epi32(__m128 a)  
| VCVTPS2DQ:| __ m256i _mm256_cvtps_epi32 (__m256
|           | a)                                 

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTPS2PD
description:
CVTPS2PD - Convert Packed Single-Precision FP Values to Packed Double-Precision FP Values:
| Opcode/Instruction                  | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 0F 5A /r CVTPS2PD xmm1, xmm2/m64    | RM   | V/V           | SSE2              | Convert two packed single-precision        
|                                     |      |               |                   | floatingpoint values in xmm2/m64 to        
|                                     |      |               |                   | two packed double-precision floating-point 
|                                     |      |               |                   | values in xmm1.                            
| VEX.128.0F.WIG 5A /r VCVTPS2PD xmm1,| RM   | V/V           | AVX               | Convert two packed single-precision        
| xmm2/m64                            |      |               |                   | floatingpoint values in xmm2/mem to        
|                                     |      |               |                   | two packed double-precision floating-point 
|                                     |      |               |                   | values in xmm1.                            
| VEX.256.0F.WIG 5A /r VCVTPS2PD ymm1,| RM   | V/V           | AVX               | Convert four packed single-precision       
| xmm2/m128                           |      |               |                   | floatingpoint values in xmm2/mem to        
|                                     |      |               |                   | four packed double-precision floating-point
|                                     |      |               |                   | values in ymm1.                            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two or four packed single-precision floating-point values in the source
operand (second operand) to two or four packed double-precision floating-point
values in the destination operand (first operand).

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 64- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 64- bit memory location. The destination operation is a YMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory
location. The destination operation is a YMM register. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD.

| SRC X3| X3 X2| X2 X1| X1| X0 X0
DEST

| Figure 3-13.| CVTPS2PD (VEX.256 encoded version)
Operation:

CVTPS2PD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[VLMAX-1:128] (unmodified)
VCVTPS2PD (VEX.128 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[VLMAX-1:128] <- 0
VCVTPS2PD (VEX.256 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPS2PD: | __m128d _mm_cvtps_pd(__m128 a)    
| VCVTPS2PD:| __m256d _mm256_cvtps_pd (__m128 a)

SIMD Floating-Point Exceptions:
Invalid, Denormal.


Other Exceptions:
See Exceptions Type 3; additionally

#UDIf VEX.vvvv != 1111B.


platform: x86
mnem: CVTPS2PI
description:
CVTPS2PI - Convert Packed Single-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction           | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 2D /r CVTPS2PI mm, xmm/m64| RM   | Valid      | Valid          | Convert two packed single-precision  
|                              |      |            |                | floatingpoint values from xmm/m64 to 
|                              |      |            |                | two packed signed doubleword integers
|                              |      |            |                | in mm.                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed single-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an MMX technology register. When the source operand is
an XMM register, the two single-precision floating-point values are contained
in the low quadword of the register. When a conversion is inexact, the value
returned is rounded according to the rounding control bits in the MXCSR register.
If a converted result is larger than the maximum signed doubleword integer,
the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value (80000000H) is returned.

CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that
is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is
set to all 0s [valid]). If this instruction is executed while an x87 FPU floatingpoint
exception is pending, the exception is handled before the CVTPS2PI instruction
is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPS2PI:| __m64 _mm_cvtps_pi32(__m128 a)

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with
XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B.


platform: x86
mnem: CVTSD2SI
description:
CVTSD2SI - Convert Scalar Double-Precision FP Value to Integer:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F2 0F 2D /r CVTSD2SI r32, xmm/m64      | RM   | V/V           | SSE2              | Convert one double-precision floating-point 
|                                        |      |               |                   | value from xmm/m64 to one signed doubleword 
|                                        |      |               |                   | integer r32.                                
| F2 REX.W 0F 2D /r CVTSD2SI r64, xmm/m64| RM   | V/N.E.        | SSE2              | Convert one double-precision floating-point 
|                                        |      |               |                   | value from xmm/m64 to one signed quadword   
|                                        |      |               |                   | integer sign-extended into r64.             
| VEX.LIG.F2.0F.W0 2D /r VCVTSD2SI r32,  | RM   | V/V           | AVX               | Convert one double precision floating-point 
| xmm1/m64                               |      |               |                   | value from xmm1/m64 to one signed doubleword
|                                        |      |               |                   | integer r32.                                
| VEX.LIG.F2.0F.W1 2D /r VCVTSD2SI r64,  | RM   | V/N.E.1       | AVX               | Convert one double precision floating-point 
| xmm1/m64                               |      |               |                   | value from xmm1/m64 to one signed quadword  
|                                        |      |               |                   | integer sign-extended into r64.             
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts a double-precision floating-point value in the source operand (second
operand) to a signed doubleword integer in the destination operand (first operand).
The source operand can be an XMM register or a 64-bit memory location. The destination
operand is a general-purpose register. When the source operand is an XMM register,
the double-precision floating-point value is contained in the low quadword of
the register.

When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (80000000H)
is returned.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operation. See the summary chart at the beginning of this
section for encoding data and limits. Legacy SSE instructions: Use of the REX.W
prefix promotes the instruction to 64-bit operation. See the summary chart at
the beginning of this section for encoding data and limits. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

Operation:

IF 64-Bit Mode and OperandSize = 64
  THEN
     DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer64(SRC[63:0]);
  ELSE
     DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_cvtsd_si32(__m128d a) __int64 _mm_cvtsd_si64(__m128d a)


SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTSD2SS
description:
CVTSD2SS - Convert Scalar Double-Precision FP Value to Scalar Single-Precision FP Value:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F2 0F 5A /r CVTSD2SS xmm1, xmm2/m64  | RM   | V/V           | SSE2              | Convert one double-precision floating-point
|                                      |      |               |                   | value in xmm2/m64 to one single-precision  
|                                      |      |               |                   | floating-point value in xmm1.              
| VEX.NDS.LIG.F2.0F.WIG 5A /r VCVTSD2SS| RVM  | V/V           | AVX               | Convert one double-precision floating-point
| xmm1,xmm2, xmm3/m64                  |      |               |                   | value in xmm3/m64 to one single-precision  
|                                      |      |               |                   | floating-point value and merge with        
|                                      |      |               |                   | high bits in xmm2.                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts a double-precision floating-point value in the source operand (second
operand) to a single-precision floating-point value in the destination operand
(first operand).

The source operand can be an XMM register or a 64-bit memory location. The destination
operand is an XMM register. When the source operand is an XMM register, the
double-precision floating-point value is contained in the low quadword of the
register. The result is stored in the low doubleword of the destination operand,
and the upper 3 doublewords are left unchanged. When the conversion is inexact,
the value returned is rounded according to the rounding control bits in the
MXCSR register.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The destination and first
source operand are the same. Bits (VLMAX-1:32) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: Bits (127:64) of the XMM
register destination are copied from corresponding bits in the first source
operand. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

CVTSD2SS (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);
(* DEST[VLMAX-1:32] Unmodified *)
VCVTSD2SS (VEX.128 encoded version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTSD2SS:| __m128 _mm_cvtsd_ss(__m128 a, __m128d
|          | b)                                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CVTSI2SD
description:
CVTSI2SD - Convert Dword Integer to Scalar Double-Precision FP Value:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                      
| F2 0F 2A /r CVTSI2SD xmm, r/m32      | RM   | V/V           | SSE2              | Convert one signed doubleword integer            
|                                      |      |               |                   | from r/m32 to one double-precision floating-point
|                                      |      |               |                   | value in xmm.                                    
| F2 REX.W 0F 2A /r CVTSI2SD xmm, r/m64| RM   | V/N.E.        | SSE2              | Convert one signed quadword integer              
|                                      |      |               |                   | from r/m64 to one double-precision floating-point
|                                      |      |               |                   | value in xmm.                                    
| VEX.NDS.LIG.F2.0F.W0 2A /r VCVTSI2SD | RVM  | V/V           | AVX               | Convert one signed doubleword integer            
| xmm1, xmm2, r/m32                    |      |               |                   | from r/m32 to one double-precision floating-point
|                                      |      |               |                   | value in xmm1.                                   
| VEX.NDS.LIG.F2.0F.W1 2A /r VCVTSI2SD | RVM  | V/N.E.1       | AVX               | Convert one signed quadword integer              
| xmm1, xmm2, r/m64                    |      |               |                   | from r/m64 to one double-precision floating-point
|                                      |      |               |                   | value in xmm1.                                   
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts a signed doubleword integer (or signed quadword integer if operand
size is 64 bits) in the second source operand to a double-precision floating-point
value in the destination operand. The result is stored in the low quadword of
the destination operand, and the high quadword left unchanged. When conversion
is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register. Legacy SSE instructions: Use of the REX.W prefix
promotes the instruction to 64-bit operands. See the summary chart at the beginning
of this section for encoding data and limits. The second source operand can
be a general-purpose register or a 32/64-bit memory location. The first source
and destination operands are XMM registers. 128-bit Legacy SSE version: The
destination and first source operand are the same. Bits (VLMAX-1:64) of the
corresponding YMM destination register remain unchanged. VEX.128 encoded version:
Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.

Operation:

CVTSI2SD
IF 64-Bit Mode And OperandSize = 64
THEN
  DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);
ELSE
  DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[VLMAX-1:64] (Unmodified)
VCVTSI2SD
IF 64-Bit Mode And OperandSize = 64
THEN
  DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
  DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTSI2SD:| __m128d _mm_cvtsi32_sd(__m128d a, int    
|          | b)                                       
| CVTSI2SD:| __m128d _mm_cvtsi64_sd(__m128d a, __int64
|          | b)                                       

SIMD Floating-Point Exceptions:
Precision.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CVTSI2SS
description:
CVTSI2SS - Convert Dword Integer to Scalar Single-Precision FP Value:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                      
| F3 0F 2A /r CVTSI2SS xmm, r/m32      | RM   | V/V           | SSE               | Convert one signed doubleword integer            
|                                      |      |               |                   | from r/m32 to one single-precision floating-point
|                                      |      |               |                   | value in xmm.                                    
| F3 REX.W 0F 2A /r CVTSI2SS xmm, r/m64| RM   | V/N.E.        | SSE               | Convert one signed quadword integer              
|                                      |      |               |                   | from r/m64 to one single-precision floating-point
|                                      |      |               |                   | value in xmm.                                    
| VEX.NDS.LIG.F3.0F.W0 2A /r VCVTSI2SS | RVM  | V/V           | AVX               | Convert one signed doubleword integer            
| xmm1, xmm2, r/m32                    |      |               |                   | from r/m32 to one single-precision floating-point
|                                      |      |               |                   | value in xmm1.                                   
| VEX.NDS.LIG.F3.0F.W1 2A /r VCVTSI2SS | RVM  | V/N.E.1       | AVX               | Convert one signed quadword integer              
| xmm1, xmm2, r/m64                    |      |               |                   | from r/m64 to one single-precision floating-point
|                                      |      |               |                   | value in xmm1.                                   
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts a signed doubleword integer (or signed quadword integer if operand
size is 64 bits) in the source operand (second operand) to a single-precision
floating-point value in the destination operand (first operand). The source
operand can be a general-purpose register or a memory location. The destination
operand is an XMM register. The result is stored in the low doubleword of the
destination operand, and the upper three doublewords are left unchanged. When
a conversion is inexact, the value returned is rounded according to the rounding
control bits in the MXCSR register.

Legacy SSE instructions: In 64-bit mode, the instruction can access additional
registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W
prefix promotes the instruction to 64-bit operands. See the summary chart at
the beginning of this section for encoding data and limits.

128-bit Legacy SSE version: The destination and first source operand are the
same. Bits (VLMAX-1:32) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: Bits (127:32) of the XMM register destination
are copied from corresponding bits in the first source operand. Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

Operation:

CVTSI2SS (128-bit Legacy SSE version)
IF 64-Bit Mode And OperandSize = 64
THEN
  DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
  DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[VLMAX-1:32] (Unmodified)
VCVTSI2SS (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
  DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
  DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTSI2SS:| __m128| _mm_cvtsi32_ss(__m128| a, int b)    
| CVTSI2SS:| __m128| _mm_cvtsi64_ss(__m128| a, __int64 b)

SIMD Floating-Point Exceptions:
Precision.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CVTSS2SD
description:
CVTSS2SD - Convert Scalar Single-Precision FP Value to Scalar Double-Precision FP Value:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32  | RM   | V/V           | SSE2              | Convert one single-precision floating-point
|                                      |      |               |                   | value in xmm2/m32 to one double-precision  
|                                      |      |               |                   | floating-point value in xmm1.              
| VEX.NDS.LIG.F3.0F.WIG 5A /r VCVTSS2SD| RVM  | V/V           | AVX               | Convert one single-precision floating-point
| xmm1, xmm2, xmm3/m32                 |      |               |                   | value in xmm3/m32 to one double-precision  
|                                      |      |               |                   | floating-point value and merge with        
|                                      |      |               |                   | high bits of xmm2.                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts a single-precision floating-point value in the source operand (second
operand) to a double-precision floating-point value in the destination operand
(first operand). The source operand can be an XMM register or a 32bit memory
location. The destination operand is an XMM register. When the source operand
is an XMM register, the single-precision floating-point value is contained in
the low doubleword of the register. The result is stored in the low quadword
of the destination operand, and the high quadword is left unchanged.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The destination and first
source operand are the same. Bits (VLMAX-1:64) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: Bits (127:64) of the XMM
register destination are copied from corresponding bits in the first source
operand. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

CVTSS2SD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[VLMAX-1:64] (Unmodified)
VCVTSS2SD (VEX.128 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTSS2SD:| __m128d _mm_cvtss_sd(__m128d a, __m128
|          | b)                                    

SIMD Floating-Point Exceptions:
Invalid, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CVTSS2SI
description:
CVTSS2SI - Convert Scalar Single-Precision FP Value to Dword Integer:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F3 0F 2D /r CVTSS2SI r32, xmm/m32      | RM   | V/V           | SSE               | Convert one single-precision floating-point 
|                                        |      |               |                   | value from xmm/m32 to one signed doubleword 
|                                        |      |               |                   | integer in r32.                             
| F3 REX.W 0F 2D /r CVTSS2SI r64, xmm/m32| RM   | V/N.E.        | SSE               | Convert one single-precision floating-point 
|                                        |      |               |                   | value from xmm/m32 to one signed quadword   
|                                        |      |               |                   | integer in r64.                             
| VEX.LIG.F3.0F.W0 2D /r VCVTSS2SI r32,  | RM   | V/V           | AVX               | Convert one single-precision floating-point 
| xmm1/m32                               |      |               |                   | value from xmm1/m32 to one signed doubleword
|                                        |      |               |                   | integer in r32.                             
| VEX.LIG.F3.0F.W1 2D /r VCVTSS2SI r64,  | RM   | V/N.E.1       | AVX               | Convert one single-precision floating-point 
| xmm1/m32                               |      |               |                   | value from xmm1/m32 to one signed quadword  
|                                        |      |               |                   | integer in r64.                             
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts a single-precision floating-point value in the source operand (second
operand) to a signed doubleword integer (or signed quadword integer if operand
size is 64 bits) in the destination operand (first operand). The source operand
can be an XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-point
value is contained in the low doubleword of the register.

When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (80000000H)
is returned.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. Use of the REX.W prefix promotes the
instruction to 64-bit operands. See the summary chart at the beginning of this
section for encoding data and limits. Legacy SSE instructions: In 64-bit mode,
Use of the REX.W prefix promotes the instruction to 64-bit operands. See the
summary chart at the beginning of this section for encoding data and limits.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise
instructions will #UD.

Operation:

IF 64-bit Mode and OperandSize = 64
  THEN
     DEST[64:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
  ELSE
     DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_cvtss_si32(__m128d a) __int64 _mm_cvtss_si64(__m128d a)


SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTTPD2DQ
description:
CVTTPD2DQ - Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                             
| 66 0F E6 /r CVTTPD2DQ xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert two packed double-precision     
|                                         |      |               |                   | floatingpoint values from xmm2/m128     
|                                         |      |               |                   | to two packed signed doubleword integers
|                                         |      |               |                   | in xmm1 using truncation.               
| VEX.128.66.0F.WIG E6 /r VCVTTPD2DQ xmm1,| RM   | V/V           | AVX               | Convert two packed double-precision     
| xmm2/m128                               |      |               |                   | floatingpoint values in xmm2/mem to     
|                                         |      |               |                   | two signed doubleword integers in xmm1  
|                                         |      |               |                   | using truncation.                       
| VEX.256.66.0F.WIG E6 /r VCVTTPD2DQ xmm1,| RM   | V/V           | AVX               | Convert four packed double-precision    
| ymm2/m256                               |      |               |                   | floatingpoint values in ymm2/mem to     
|                                         |      |               |                   | four signed doubleword integers in xmm1 
|                                         |      |               |                   | using truncation.                       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two or four packed double-precision floating-point values in the source
operand (second operand) to two or four packed signed doubleword integers in
the destination operand (first operand). When a conversion is inexact, a truncated
(round toward zero) value is returned.If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is
returned.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 128- bit memory location. The destination operation is a YMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is an XMM register. The upper bits (255:128)
of the corresponding YMM register destination are zeroed. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

| SRC DEST| X3 Figure 3-14.| X2 0 VCVTTPD2DQ (VEX.256 encoded version)| X1 X2| X0 X0
Operation:

CVTTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[127:64] <- 0
DEST[VLMAX-1:128] (unmodified)
VCVTTPD2DQ (VEX.128 encoded version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[VLMAX-1:64] <- 0
VCVTTPD2DQ (VEX.256 encoded version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[95:64] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])
DEST[127:96] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)
DEST[255:128]<- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTTPD2DQ: | __m128i _mm_cvttpd_epi32(__m128d a) 
| VCVTTPD2DQ:| __m128i _mm256_cvttpd_epi32 (__m256d
|            | src)                                

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTTPD2PI
description:
CVTTPD2PI - Convert with Truncation Packed Double-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction                | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 66 0F 2C /r CVTTPD2PI mm, xmm/m128| RM   | Valid      | Valid          | Convert two packer double-precision  
|                                   |      |            |                | floatingpoint values from xmm/m128 to
|                                   |      |            |                | two packed signed doubleword integers
|                                   |      |            |                | in mm using truncation.              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed double-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand). The source operand can be an XMM register or a 128-bit
memory location. The destination operand is an MMX technology register.

When a conversion is inexact, a truncated (round toward zero) result is returned.
If a converted result is larger than the maximum signed doubleword integer,
the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation
(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word
is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPD2PI
instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32_
          Truncate(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTTPD1PI:| __m64 _mm_cvttpd_pi32(__m128d a)

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Mode Exceptions:
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with
FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3B.


platform: x86
mnem: CVTTPS2DQ
description:
CVTTPS2DQ - Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| F3 0F 5B /r CVTTPS2DQ xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert four single-precision floating-point 
|                                         |      |               |                   | values from xmm2/m128 to four signed         
|                                         |      |               |                   | doubleword integers in xmm1 using truncation.
| VEX.128.F3.0F.WIG 5B /r VCVTTPS2DQ xmm1,| RM   | V/V           | AVX               | Convert four packed single precision         
| xmm2/m128                               |      |               |                   | floatingpoint values from xmm2/mem to        
|                                         |      |               |                   | four packed signed doubleword values         
|                                         |      |               |                   | in xmm1 using truncation.                    
| VEX.256.F3.0F.WIG 5B /r VCVTTPS2DQ ymm1,| RM   | V/V           | AVX               | Convert eight packed single precision        
| ymm2/m256                               |      |               |                   | floatingpoint values from ymm2/mem to        
|                                         |      |               |                   | eight packed signed doubleword values        
|                                         |      |               |                   | in ymm1 using truncation.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts four or eight packed single-precision floating-point values in the
source operand to four or eight signed doubleword integers in the destination
operand. When a conversion is inexact, a truncated (round toward zero) value
is returned.If a converted result is larger than the maximum signed doubleword
integer, the floating-point invalid exception is raised, and if this exception
is masked, the indefinite integer value (80000000H) is returned.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 128- bit memory location. The destination operation is a YMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is a YMM register. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD.

Operation:

CVTTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[VLMAX-1:128] (unmodified)
VCVTTPS2DQ (VEX.128 encoded version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[VLMAX-1:128] <- 0
VCVTTPS2DQ (VEX.256 encoded version)
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)
DEST[159:128] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])
DEST[191:160] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])
DEST[223:192] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])
DEST[255:224] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTTPS2DQ: | __m128i _mm_cvttps_epi32(__m128 a) 
| VCVTTPS2DQ:| __m256i _mm256_cvttps_epi32 (__m256
|            | a)                                 

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTTPS2PI
description:
CVTTPS2PI - Convert with Truncation Packed Single-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction            | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                 
| 0F 2C /r CVTTPS2PI mm, xmm/m64| RM   | Valid      | Valid          | Convert two single-precision floating-point 
|                               |      |            |                | values from xmm/m64 to two signed doubleword
|                               |      |            |                | signed integers in mm using truncation.     

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed single-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand). The source operand can be an XMM register or a 64-bit
memory location. The destination operand is an MMX technology register. When
the source operand is an XMM register, the two single-precision floating-point
values are contained in the low quadword of the register.

When a conversion is inexact, a truncated (round toward zero) result is returned.
If a converted result is larger than the maximum signed doubleword integer,
the floating-point invalid exception is raised, and if this exception is masked,
the indefinite integer value (80000000H) is returned.

This instruction causes a transition from x87 FPU to MMX technology operation
(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word
is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPS2PI
instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTTPS2PI:| __m64 _mm_cvttps_pi32(__m128 a)

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Table 22-5, “Exception Conditions for Legacy SIMD/MMX Instructions with
XMM and FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B.


platform: x86
mnem: CVTTSD2SI
description:
CVTTSD2SI - Convert with Truncation Scalar Double-Precision FP Value to Signed Integer:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F2 0F 2C /r CVTTSD2SI r32, xmm/m64      | RM   | V/V           | SSE2              | Convert one double-precision floating-point 
|                                         |      |               |                   | value from xmm/m64 to one signed doubleword 
|                                         |      |               |                   | integer in r32 using truncation.            
| F2 REX.W 0F 2C /r CVTTSD2SI r64, xmm/m64| RM   | V/N.E.        | SSE2              | Convert one double precision floating-point 
|                                         |      |               |                   | value from xmm/m64 to one signedquadword    
|                                         |      |               |                   | integer in r64 using truncation.            
| VEX.LIG.F2.0F.W0 2C /r VCVTTSD2SI r32,  | RM   | V/V           | AVX               | Convert one double-precision floating-point 
| xmm1/m64                                |      |               |                   | value from xmm1/m64 to one signed doubleword
|                                         |      |               |                   | integer in r32 using truncation.            
| VEX.LIG.F2.0F.W1 2C /r VCVTTSD2SI r64,  | RM   | V/N.E.1       | AVX               | Convert one double precision floating-point 
| xmm1/m64                                |      |               |                   | value from xmm1/m64 to one signed quadword  
|                                         |      |               |                   | integer in r64 using truncation.            
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts a double-precision floating-point value in the source operand (second
operand) to a signed doubleword integer (or signed quadword integer if operand
size is 64 bits) in the destination operand (first operand). The source operand
can be an XMM register or a 64-bit memory location. The destination operand
is a general purpose register. When the source operand is an XMM register, the
double-precision floating-point value is contained in the low quadword of the
register. When a conversion is inexact, a truncated (round toward zero) result
is returned. If a converted result is larger than the maximum signed doubleword
integer, the floating point invalid exception is raised. If this exception is
masked, the indefinite integer value (80000000H) is returned. Legacy SSE instructions:
In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation.
See the summary chart at the beginning of this section for encoding data and
limits. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b,
otherwise instructions will #UD.

Operation:

IF 64-Bit Mode and OperandSize = 64
  THEN
     DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_
              Integer64_Truncate(SRC[63:0]);
  ELSE
     DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_
             Integer32_Truncate(SRC[63:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_cvttsd_si32(__m128d a) __int64 _mm_cvttsd_si64(__m128d a)


SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTTSS2SI
description:
CVTTSS2SI - Convert with Truncation Scalar Single-Precision FP Value to Dword Integer:
| Opcode/Instruction                      | Op/ En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F3 0F 2C /r CVTTSS2SI r32, xmm/m32      | RM    | V/V           | SSE               | Convert one single-precision floating-point 
|                                         |       |               |                   | value from xmm/m32 to one signed doubleword 
|                                         |       |               |                   | integer in r32 using truncation.            
| F3 REX.W 0F 2C /r CVTTSS2SI r64, xmm/m32| RM    | V/N.E.        | SSE               | Convert one single-precision floating-point 
|                                         |       |               |                   | value from xmm/m32 to one signed quadword   
|                                         |       |               |                   | integer in r64 using truncation.            
| VEX.LIG.F3.0F.W0 2C /r VCVTTSS2SI r32,  | RM    | V/V           | AVX               | Convert one single-precision floating-point 
| xmm1/m32                                |       |               |                   | value from xmm1/m32 to one signed doubleword
|                                         |       |               |                   | integer in r32 using truncation.            
| VEX.LIG.F3.0F.W1 2C /r VCVTTSS2SI r64,  | RM    | V/N.E.1       | AVX               | Convert one single-precision floating-point 
| xmm1/m32                                |       |               |                   | value from xmm1/m32 to one signed quadword  
|                                         |       |               |                   | integer in r64 using truncation.            
Notes: 1. Encoding the VEX prefix with VEX.W=1 in non-64-bit mode is ignored.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts a single-precision floating-point value in the source operand (second
operand) to a signed doubleword integer (or signed quadword integer if operand
size is 64 bits) in the destination operand (first operand). The source operand
can be an XMM register or a 32-bit memory location. The destination operand
is a general-purpose register. When the source operand is an XMM register, the
single-precision floating-point value is contained in the low doubleword of
the register.

When a conversion is inexact, a truncated (round toward zero) result is returned.
If a converted result is larger than the maximum signed doubleword integer,
the floating-point invalid exception is raised. If this exception is masked,
the indefinite integer value (80000000H) is returned.

Legacy SSE instructions: In 64-bit mode, the instruction can access additional
registers (XMM8-XMM15, R8-R15) when used with a REX.R prefix. Use of the REX.W
prefix promotes the instruction to 64-bit operation. See the summary chart at
the beginning of this section for encoding data and limits. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

Operation:

IF 64-Bit Mode and OperandSize = 64
  THEN
     DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_
             Integer_Truncate(SRC[31:0]);
  ELSE
     DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_
             Integer_Truncate(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_cvttss_si32(__m128d a) __int64 _mm_cvttss_si64(__m128d a)


SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CWD
description:
CWD/CDQ/CQO - Convert Word to Doubleword/Convert Doubleword to Quadword:
| Opcode    | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                  
| 99        | CWD        | NP   | Valid      | Valid          | DX:AX ← sign-extend of AX.   
| 99        | CDQ        | NP   | Valid      | Valid          | EDX:EAX ← sign-extend of EAX.
| REX.W + 99| CQO        | NP   | Valid      | N.E.           | RDX:RAX← sign-extend of RAX. 

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Doubles the size of the operand in register AX, EAX, or RAX (depending on the
operand size) by means of sign extension and stores the result in registers
DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction copies the sign
(bit 15) of the value in the AX register into every bit position in the DX register.
The CDQ instruction copies the sign (bit 31) of the value in the EAX register
into every bit position in the EDX register. The CQO instruction (available
in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register
into every bit position in the RDX register.

The CWD instruction can be used to produce a doubleword dividend from a word
before word division. The CDQ instruction can be used to produce a quadword
dividend from a doubleword before doubleword division. The CQO instruction can
be used to produce a double quadword dividend from a quadword before a quadword
division.

The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is
intended for use when the operand-size attribute is 16 and the CDQ instruction
for when the operand-size attribute is 32. Some assemblers may force the operand
size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these
mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size
attribute to determine the size of values to be converted, regardless of the
mnemonic used.

In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO
mnemonics reference the same opcode as CWD/CDQ. See the summary chart at the
beginning of this section for encoding data and limits.

Operation:

IF OperandSize = 16 (* CWD instruction *)
  THEN
     DX <- SignExtend(AX);
  ELSE IF OperandSize = 32 (* CDQ instruction *)
     EDX <- SignExtend(EAX); FI;
  ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)
     RDX <- SignExtend(RAX); FI;
FI;

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: DAA
description:
DAA - Decimal Adjust AL after Addition:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                      
| 27    | DAA        | NP   | Invalid    | Valid          | Decimal adjust AL after addition.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Adjusts the sum of two packed BCD values to create a packed BCD result. The
AL register is the implied source and destination operand. The DAA instruction
is only useful when it follows an ADD instruction that adds (binary addition)
two 2-digit, packed BCD values and stores a byte result in the AL register.
The DAA instruction then adjusts the contents of the AL register to contain
the correct 2-digit, packed BCD result. If a decimal carry is detected, the
CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy
mode. It is not valid in 64-bit mode.

Operation:

IF 64-Bit Mode
  THEN
     #UD;
  ELSE
     old_AL <- AL;
     old_CF <- CF;
     CF <- 0;
     IF (((AL AND 0FH) > 9) or AF = 1)
        THEN
          AL <- AL + 6;
          CF <- old_CF or (Carry from AL <- AL + 6);
          AF <- 1;
        ELSE
          AF <- 0;
     FI;
     IF ((old_AL > 99H) or (old_CF = 1))
       THEN
          AL <- AL + 60H;
          CF <- 1;
       ELSE
          CF <- 0;
     FI;
FI;

Example:
| ADD DAA DAA| AL, BL| Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX
|            |       | After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000 
|            |       | Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000
|            |       | After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111 
|            |       | Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000
|            |       | After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101 

Flags Affected:
The CF and AF flags are set if the adjustment of the value results in a decimal
carry in either digit of the result (see the “Operation” section above). The
SF, ZF, and PF flags are set according to the result. The OF flag is undefined.


Protected Mode Exceptions:
| #UD| If the LOCK prefix is used.

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #UD| If the LOCK prefix is used.

Compatibility Mode Exceptions:
| #UD| If the LOCK prefix is used.

64-Bit Mode Exceptions:
| #UD| If in 64-bit mode.


platform: x86
mnem: DAS
description:
DAS - Decimal Adjust AL after Subtraction:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| 2F    | DAS        | NP   | Invalid    | Valid          | Decimal adjust AL after subtraction.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Adjusts the result of the subtraction of two packed BCD values to create a packed
BCD result. The AL register is the implied source and destination operand. The
DAS instruction is only useful when it follows a SUB instruction that subtracts
(binary subtraction) one 2-digit, packed BCD value from another and stores a
byte result in the AL register. The DAS instruction then adjusts the contents
of the AL register to contain the correct 2-digit, packed BCD result. If a decimal
borrow is detected, the CF and AF flags are set accordingly.

This instruction executes as described above in compatibility mode and legacy
mode. It is not valid in 64-bit mode.

Operation:

IF 64-Bit Mode
  THEN
     #UD;
  ELSE
     old_AL <- AL;
     old_CF <- CF;
     CF <- 0;
     IF (((AL AND 0FH) > 9) or AF = 1)
       THEN
          AL <- AL - 6;
          CF <- old_CF or (Borrow from AL <- AL − 6);
          AF <- 1;
       ELSE
          AF <- 0;
     FI;
     IF ((old_AL > 99H) or (old_CF = 1))
        THEN
          AL <- AL − 60H;
          CF <- 1;
     FI;
FI;

Example:
| SUB DAA| AL, BL| Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC)
|        |       | = XXXXXX After: AL = EEH, BL = 47H,       
|        |       | EFLAGS(0SZAPC) = 010111 Before: AL =      
|        |       | EEH, BL = 47H, EFLAGS(OSZAPC) = 010111    
|        |       | After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) 
|        |       | = X10111                                  

Flags Affected:
The CF and AF flags are set if the adjustment of the value results in a decimal
borrow in either digit of the result (see the “Operation” section above). The
SF, ZF, and PF flags are set according to the result. The OF flag is undefined.


Protected Mode Exceptions:
| #UD| If the LOCK prefix is used.

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #UD| If the LOCK prefix is used.

Compatibility Mode Exceptions:
| #UD| If the LOCK prefix is used.

64-Bit Mode Exceptions:
| #UD| If in 64-bit mode.


platform: x86
mnem: DEC
description:
DEC - Decrement by 1:
| Opcode           | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                        
| FE /1 REX + FE /1| DEC r/m8 DEC r/m8*| M M  | Valid Valid| Valid N.E.     | Decrement r/m8 by 1. Decrement r/m8
|                  |                   |      |            |                | by 1.                              
| FF /1            | DEC r/m16         | M    | Valid      | Valid          | Decrement r/m16 by 1.              
| FF /1            | DEC r/m32         | M    | Valid      | Valid          | Decrement r/m32 by 1.              
| REX.W + FF /1    | DEC r/m64         | M    | Valid      | N.E.           | Decrement r/m64 by 1.              
| 48+rw            | DEC r16           | O    | N.E.       | Valid          | Decrement r16 by 1.                
| 48+rd            | DEC r32           | O    | N.E.       | Valid          | Decrement r32 by 1.                
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1         | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r, w)  | NA       | NA       | NA       
| O    | opcode + rd (r, w)| NA       | NA       | NA       

Description:
Subtracts 1 from the destination operand, while preserving the state of the
CF flag. The destination operand can be a register or a memory location. This
instruction allows a loop counter to be updated without disturbing the CF flag.
(To perform a decrement operation that updates the CF flag, use a SUB instruction
with an immediate operand of 1.)

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through
4FH are REX prefixes). Otherwise, the instruction's 64-bit mode default operation
size is 32 bits. Use of the REX.R prefix permits access to additional registers
(R8-R15). Use of the REX.W prefix promotes operation to 64 bits.

See the summary chart at the beginning of this section for encoding data and
limits.

Operation:

DEST <- DEST - 1;

Flags Affected:
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according
to the result.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand is located         
|                | in a non-writable segment. If a memory        
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: DIV
description:
DIV - Unsigned Divide:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| F6 /6        | DIV r/m8   | M    | Valid      | Valid          | Unsigned divide AX by r/m8, with result 
|              |            |      |            |                | stored in AL ← Quotient, AH ← Remainder.
| REX + F6 /6  | DIV r/m8*  | M    | Valid      | N.E.           | Unsigned divide AX by r/m8, with result 
|              |            |      |            |                | stored in AL ← Quotient, AH ← Remainder.
| F7 /6        | DIV r/m16  | M    | Valid      | Valid          | Unsigned divide DX:AX by r/m16, with    
|              |            |      |            |                | result stored in AX ← Quotient, DX ←    
|              |            |      |            |                | Remainder.                              
| F7 /6        | DIV r/m32  | M    | Valid      | Valid          | Unsigned divide EDX:EAX by r/m32, with  
|              |            |      |            |                | result stored in EAX ← Quotient, EDX    
|              |            |      |            |                | ←Remainder.                             
| REX.W + F7 /6| DIV r/m64  | M    | Valid      | N.E.           | Unsigned divide RDX:RAX by r/m64, with  
|              |            |      |            |                | result stored in RAX ← Quotient, RDX    
|              |            |      |            |                | ←Remainder.                             
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend)
by the source operand (divisor) and stores the result in the AX (AH:AL), DX:AX,
EDX:EAX, or RDX:RAX registers. The source operand can be a general-purpose register
or a memory location. The action of this instruction depends on the operand
size (dividend/divisor). Division using 64-bit operand is available only in
64-bit mode.

Non-integral results are truncated (chopped) towards 0. The remainder is always
less than the divisor in magnitude. Overflow is indicated with the #DE (divide
error) exception rather than with the CF flag.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied,
the instruction divides the unsigned value in RDX:RAX by the source operand
and stores the quotient in RAX, the remainder in RDX.

See the summary chart at the beginning of this section for encoding data and
limits. See Table 3-25.


Table 3-25. DIV Action:
Maximum

| Operand Size           | Dividend| Divisor| Quotient| Remainder| Quotient
| Word/byte              | AX      | r/m8   | AL      | AH       | 255     
| Doubleword/word        | DX:AX   | r/m16  | AX      | DX       | 65,535  
| Quadword/doubleword    | EDX:EAX | r/m32  | EAX     | EDX      | 232 − 1 
| Doublequadword/quadword| RDX:RAX | r/m64  | RAX     | RDX      | 264 − 1 
Operation:

IF SRC = 0
  THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)
  THEN
     temp <- AX / SRC;
     IF temp > FFH
       THEN #DE; (* Divide error *)
       ELSE
          AL <- temp;
          AH <- AX MOD SRC;
     FI;
  ELSE IF OperandSize = 16 (* Doubleword/word operation *)
     THEN
       temp <- DX:AX / SRC;
       IF temp > FFFFH
          THEN #DE; (* Divide error *)
       ELSE
          AX <- temp;
          DX <- DX:AX MOD SRC;
       FI;
     FI;
  ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
     THEN
       temp <- EDX:EAX / SRC;
       IF temp > FFFFFFFFH
          THEN #DE; (* Divide error *)
       ELSE
          EAX <- temp;
          EDX <- EDX:EAX MOD SRC;
       FI;
     FI;
  ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
     THEN
       temp <- RDX:RAX / SRC;
       IF temp > FFFFFFFFFFFFFFFFH
          THEN #DE; (* Divide error *)
       ELSE
          RAX <- temp;
          RDX <- RDX:RAX MOD SRC;
       FI;
     FI;
FI;

Flags Affected:
The CF, OF, SF, ZF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #DE            | If the source operand (divisor) is 0 
|                | If the quotient is too large for the 
|                | designated register.                 
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #DE   | If the source operand (divisor) is 0.
|       | If the quotient is too large for the 
|       | designated register.                 
| #GP   | If a memory operand effective address
|       | is outside the CS, DS, ES, FS, or GS 
|       | segment limit. If the DS, ES, FS, or 
|       | GS register contains a NULL segment  
|       | selector.                            
| #SS(0)| If a memory operand effective address
|       | is outside the SS segment limit.     
| #UD   | If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #DE            | If the source operand (divisor) is 0. 
|                | If the quotient is too large for the  
|                | designated register.                  
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS            | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #DE            | If the source operand (divisor) is 0       
|                | If the quotient is too large for the       
|                | designated register.                       
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: DIVPD
description:
DIVPD - Divide Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 66 0F 5E /r DIVPD xmm1, xmm2/m128       | RM   | V/V           | SSE2              | Divide packed double-precision floating-point
|                                         |      |               |                   | values in xmm1 by packed double-precision    
|                                         |      |               |                   | floating-point values xmm2/m128.             
| VEX.NDS.128.66.0F.WIG 5E /r VDIVPD xmm1,| RVM  | V/V           | AVX               | Divide packed double-precision floating-point
| xmm2, xmm3/m128                         |      |               |                   | values in xmm2 by packed double-precision    
|                                         |      |               |                   | floating-point values in xmm3/mem.           
| VEX.NDS.256.66.0F.WIG 5E /r VDIVPD ymm1,| RVM  | V/V           | AVX               | Divide packed double-precision floating-point
| ymm2, ymm3/m256                         |      |               |                   | values in ymm2 by packed double-precision    
|                                         |      |               |                   | floating-point values in ymm3/mem.           

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an SIMD divide of the two or four packed double-precision floating-point
values in the first source operand by the two or four packed double-precision
floating-point values in the second source operand. See Chapter 11 in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an overview
of a SIMD doubleprecision floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The second source can be
an XMM register or an 128-bit memory location. The destination is not distinct
from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. VEX.128 encoded version: the first
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand can be a YMM register or
a 256-bit memory location. The destination operand is a YMM register.

Operation:

DIVPD (128-bit Legacy SSE version)
DEST[63:0] <- SRC1[63:0] / SRC2[63:0]
DEST[127:64] <- SRC1[127:64] / SRC2[127:64]
DEST[VLMAX-1:128] (Unmodified)
VDIVPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] / SRC2[63:0]
DEST[127:64] <- SRC1[127:64] / SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VDIVPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] / SRC2[63:0]
DEST[127:64] <- SRC1[127:64] / SRC2[127:64]
DEST[191:128] <- SRC1[191:128] / SRC2[191:128]
DEST[255:192] <- SRC1[255:192] / SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| DIVPD: | __m128d _mm_div_pd(__m128d a, __m128d    
|        | b)                                       
| VDIVPD:| __m256d _mm256_div_pd (__m256d a, __m256d
|        | b);                                      

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: DIVPS
description:
DIVPS - Divide Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 0F 5E /r DIVPS xmm1, xmm2/m128       | RM   | V/V           | SSE               | Divide packed single-precision floating-point
|                                      |      |               |                   | values in xmm1 by packed single-precision    
|                                      |      |               |                   | floating-point values xmm2/m128.             
| VEX.NDS.128.0F.WIG 5E /r VDIVPS xmm1,| RVM  | V/V           | AVX               | Divide packed single-precision floating-point
| xmm2, xmm3/m128                      |      |               |                   | values in xmm2 by packed double-precision    
|                                      |      |               |                   | floating-point values in xmm3/mem.           
| VEX.NDS.256.0F.WIG 5E /r VDIVPS ymm1,| RVM  | V/V           | AVX               | Divide packed single-precision floating-point
| ymm2, ymm3/m256                      |      |               |                   | values in ymm2 by packed double-precision    
|                                      |      |               |                   | floating-point values in ymm3/mem.           

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an SIMD divide of the four or eight packed single-precision floating-point
values in the first source operand by the four or eight packed single-precision
floating-point values in the second source operand. See Chapter 10 in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an overview
of a SIMD single-precision floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The second source can be
an XMM register or an 128-bit memory location. The destination is not distinct
from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. VEX.128 encoded version: the first
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand can be a YMM register or
a 256-bit memory location. The destination operand is a YMM register.

Operation:

DIVPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] / SRC2[31:0]
DEST[63:32] <- SRC1[63:32] / SRC2[63:32]
DEST[95:64] <- SRC1[95:64] / SRC2[95:64]
DEST[127:96] <- SRC1[127:96] / SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VDIVPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] / SRC2[31:0]
DEST[63:32] <- SRC1[63:32] / SRC2[63:32]
DEST[95:64] <- SRC1[95:64] / SRC2[95:64]
DEST[127:96] <- SRC1[127:96] / SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VDIVPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] / SRC2[31:0]
DEST[63:32] <- SRC1[63:32] / SRC2[63:32]
DEST[95:64] <- SRC1[95:64] / SRC2[95:64]
DEST[127:96] <- SRC1[127:96] / SRC2[127:96]
DEST[159:128] <- SRC1[159:128] / SRC2[159:128]
DEST[191:160]<- SRC1[191:160] / SRC2[191:160]
DEST[223:192] <- SRC1[223:192] / SRC2[223:192]
DEST[255:224] <- SRC1[255:224] / SRC2[255:224].

Intel C/C++ Compiler Intrinsic Equivalent:
| DIVPS: | __m128 _mm_div_ps(__m128 a, __m128 b) 
| VDIVPS:| __m256 _mm256_div_ps (__m256 a, __m256
|        | b);                                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: DIVSD
description:
DIVSD - Divide Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F2 0F 5E /r DIVSD xmm1, xmm2/m64        | RM   | V/V           | SSE2              | Divide low double-precision floating-point  
|                                         |      |               |                   | value in xmm1 by low double-precision       
|                                         |      |               |                   | floating-point value in xmm2/mem64.         
| VEX.NDS.LIG.F2.0F.WIG 5E /r VDIVSD xmm1,| RVM  | V/V           | AVX               | Divide low double-precision floating        
| xmm2, xmm3/m64                          |      |               |                   | point values in xmm2 by low double precision
|                                         |      |               |                   | floating-point value in xmm3/mem64.         

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Divides the low double-precision floating-point value in the first source operand
by the low double-precision floating-point value in the second source operand,
and stores the double-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 64-bit memory location.
The first source and destination hyperons are XMM registers. The high quadword
of the destination operand is copied from the high quadword of the first source
operand. See Chapter 11 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for an overview of a scalar double-precision floating-point
operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The first source operand
and the destination operand are the same. Bits (VLMAX1:64) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

Operation:

DIVSD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] / SRC[63:0]
DEST[VLMAX-1:64] (Unmodified)
VDIVSD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] / SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| DIVSD:| __m128d _mm_div_sd (m128d a, m128d b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: DIVSS
description:
DIVSS - Divide Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F3 0F 5E /r DIVSS xmm1, xmm2/m32        | RM   | V/V           | SSE               | Divide low single-precision floating-point 
|                                         |      |               |                   | value in xmm1 by low single-precision      
|                                         |      |               |                   | floating-point value in xmm2/m32.          
| VEX.NDS.LIG.F3.0F.WIG 5E /r VDIVSS xmm1,| RVM  | V/V           | AVX               | Divide low single-precision floating       
| xmm2, xmm3/m32                          |      |               |                   | point value in xmm2 by low single precision
|                                         |      |               |                   | floating-point value in xmm3/m32.          

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Divides the low single-precision floating-point value in the first source operand
by the low single-precision floatingpoint value in the second source operand,
and stores the single-precision floating-point result in the destination operand.
The second source operand can be an XMM register or a 32-bit memory location.
The first source and destination operands are XMM registers. The three high-order
doublewords of the destination are copied from the same dwords of the first
source operand. See Chapter 10 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for an overview of a scalar single-precision floating-point
operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The first source operand
and the destination operand are the same. Bits (VLMAX1:32) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

Operation:

DIVSS (128-bit Legacy SSE version)
DEST[31:0] <- DEST[31:0] / SRC[31:0]
DEST[VLMAX-1:32] (Unmodified)
VDIVSS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] / SRC2[31:0]
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| DIVSS:| __m128 _mm_div_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: DPPD
description:
DPPD  -  Dot Product of Packed Double Precision Floating-Point Values:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 66 0F 3A 41 /r ib DPPD xmm1, xmm2/m128,| RMI  | V/V           | SSE4_1            | Selectively multiply packed DP floating-point
| imm8                                   |      |               |                   | values from xmm1 with packed DP floatingpoint
|                                        |      |               |                   | values from xmm2, add and selectively        
|                                        |      |               |                   | store the packed DP floating-point values    
|                                        |      |               |                   | to xmm1.                                     
| VEX.NDS.128.66.0F3A.WIG 41 /r ib VDPPD | RVMI | V/V           | AVX               | Selectively multiply packed DP floating-point
| xmm1,xmm2, xmm3/m128, imm8             |      |               |                   | values from xmm2 with packed DP floatingpoint
|                                        |      |               |                   | values from xmm3, add and selectively        
|                                        |      |               |                   | store the packed DP floating-point values    
|                                        |      |               |                   | to xmm1.                                     

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Conditionally multiplies the packed double-precision floating-point values in
the destination operand (first operand) with the packed double-precision floating-point
values in the source (second operand) depending on a mask extracted from bits
[5:4] of the immediate operand (third operand). If a condition mask bit is zero,
the corresponding multiplication is replaced by a value of 0.0 in the manner
described by Section 12.8.4 of Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1.

The two resulting double-precision values are summed into an intermediate result.
The intermediate result is conditionally broadcasted to the destination using
a broadcast mask specified by bits [1:0] of the immediate byte.

If a broadcast mask bit is "1", the intermediate result is copied to the corresponding
qword element in the destination operand. If a broadcast mask bit is zero, the
corresponding element in the destination is set to zero. DPPD follows the NaN
forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7.
These rules do not cover horizontal prioritization of NaNs. Horizontal propagation
of NaNs to the destination and the positioning of those NaNs in the destination
is implementation dependent. NaNs on the input sources or computationally generated
NaNs will have at least one NaN propagated to the destination. 128-bit Legacy
SSE version: The second source can be an XMM register or an 128-bit memory location.
The destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit
memory location. The destination operand is an XMM register. The upper bits
(VLMAX-1:128) of the corresponding YMM register destination are zeroed. If VDPPD
is encoded with VEX.L= 1, an attempt to execute the instruction encoded with
VEX.L= 1 will cause an #UD exception.

Operation:

DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
  THEN Temp1[63:0] <- DEST[63:0] * SRC[63:0]; // update SIMD exception flags
  ELSE Temp1[63:0] <- +0.0; FI;
IF (imm8[5] = 1)
  THEN Temp1[127:64] <- DEST[127:64] * SRC[127:64]; // update SIMD exception flags
  ELSE Temp1[127:64] <- +0.0; FI;
/* if unmasked exception reported, execute exception handler*/
Temp2[63:0] <- Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
IF (imm8[0] = 1)
  THEN DEST[63:0] <- Temp2[63:0];
  ELSE DEST[63:0] <- +0.0; FI;
IF (imm8[1] = 1)
  THEN DEST[127:64] <- Temp2[63:0];
  ELSE DEST[127:64] <- +0.0; FI;
DPPD (128-bit Legacy SSE version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)
VDPPD (VEX.128 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] <- 0

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| DPPD:| __m128d _mm_dp_pd ( __m128d a, __m128d
|      | b, const int mask);                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal Exceptions are determined
separately for each add and multiply operation. Unmasked exceptions will leave
the destination untouched.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.L= 1.


platform: x86
mnem: DPPS
description:
DPPS  -  Dot Product of Packed Single Precision Floating-Point Values:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                    
| 66 0F 3A 40 /r ib DPPS xmm1, xmm2/m128,| RMI  | V/V           | SSE4_1            | Selectively multiply packed SP floating-point  
| imm8                                   |      |               |                   | values from xmm1 with packed SP floatingpoint  
|                                        |      |               |                   | values from xmm2, add and selectively          
|                                        |      |               |                   | store the packed SP floating-point values      
|                                        |      |               |                   | or zero values to xmm1.                        
| VEX.NDS.128.66.0F3A.WIG 40 /r ib VDPPS | RVMI | V/V           | AVX               | Multiply packed SP floating point values       
| xmm1,xmm2, xmm3/m128, imm8             |      |               |                   | from xmm1 with packed SP floating point        
|                                        |      |               |                   | values from xmm2/mem selectively add           
|                                        |      |               |                   | and store to xmm1.                             
| VEX.NDS.256.66.0F3A.WIG 40 /r ib VDPPS | RVMI | V/V           | AVX               | Multiply packed single-precision floating-point
| ymm1, ymm2, ymm3/m256, imm8            |      |               |                   | values from ymm2 with packed SP floating       
|                                        |      |               |                   | point values from ymm3/mem, selectively        
|                                        |      |               |                   | add pairs of elements and store to ymm1.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Conditionally multiplies the packed single precision floating-point values in
the destination operand (first operand) with the packed single-precision floats
in the source (second operand) depending on a mask extracted from the high 4
bits of the immediate byte (third operand). If a condition mask bit in Imm8[7:4]
is zero, the corresponding multiplication is replaced by a value of 0.0 in the
manner described by Section 12.8.4 of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1.

The four resulting single-precision values are summed into an intermediate result.
The intermediate result is conditionally broadcasted to the destination using
a broadcast mask specified by bits [3:0] of the immediate byte.

If a broadcast mask bit is "1", the intermediate result is copied to the corresponding
dword element in the destination operand. If a broadcast mask bit is zero, the
corresponding element in the destination is set to zero. DPPS follows the NaN
forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7.
These rules do not cover horizontal prioritization of NaNs. Horizontal propagation
of NaNs to the destination and the positioning of those NaNs in the destination
is implementation dependent. NaNs on the input sources or computationally generated
NaNs will have at least one NaN propagated to the destination. 128-bit Legacy
SSE version: The second source can be an XMM register or an 128-bit memory location.
The destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit
memory location. The destination operand is an XMM register. The upper bits
(VLMAX-1:128) of the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand can be a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Operation:

DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
  THEN Temp1[31:0] <- DEST[31:0] * SRC[31:0]; // update SIMD exception flags
  ELSE Temp1[31:0] <- +0.0; FI;
IF (imm8[5] = 1)
  THEN Temp1[63:32] <- DEST[63:32] * SRC[63:32]; // update SIMD exception flags
  ELSE Temp1[63:32] <- +0.0; FI;
IF (imm8[6] = 1)
  THEN Temp1[95:64] <- DEST[95:64] * SRC[95:64]; // update SIMD exception flags
  ELSE Temp1[95:64] <- +0.0; FI;
IF (imm8[7] = 1)
  THEN Temp1[127:96] <- DEST[127:96] * SRC[127:96]; // update SIMD exception flags
  ELSE Temp1[127:96] <- +0.0; FI;
Temp2[31:0] <- Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp3[31:0] <- Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp4[31:0] <- Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
IF (imm8[0] = 1)
  THEN DEST[31:0] <- Temp4[31:0];
  ELSE DEST[31:0] <- +0.0; FI;
IF (imm8[1] = 1)
  THEN DEST[63:32] <- Temp4[31:0];
  ELSE DEST[63:32] <- +0.0; FI;
IF (imm8[2] = 1)
  THEN DEST[95:64] <- Temp4[31:0];
  ELSE DEST[95:64] <- +0.0; FI;
IF (imm8[3] = 1)
  THEN DEST[127:96] <- Temp4[31:0];
  ELSE DEST[127:96] <- +0.0; FI;
DPPS (128-bit Legacy SSE version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)
VDPPS (VEX.128 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] <- 0
VDPPS (VEX.256 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[255:128]<-DP_Primitive(SRC1[255:128], SRC2[255:128]);

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| (V)DPPS:| __m128 _mm_dp_ps ( __m128 a, __m128   
|         | b, const int mask);                   
| VDPPS:  | __m256 _mm256_dp_ps ( __m256 a, __m256
|         | b, const int mask);                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal Exceptions are determined
separately for each add and multiply operation, in the order of their execution.
Unmasked exceptions will leave the destination operands unchanged.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: EMMS
description:
EMMS - Empty MMX Technology State:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                       
| 0F 77 | EMMS       | NP   | Valid      | Valid          | Set the x87 FPU tag word to empty.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This
operation marks the x87 FPU data registers (which are aliased to the MMX technology
registers) as available for use by x87 FPU floating-point instructions. (See
Figure 8-7 in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for the format of the x87 FPU tag word.) All other MMX instructions
(other than the EMMS instruction) set all the tags in x87 FPU tag word to valid
(all 0s).

The EMMS instruction must be used to clear the MMX technology state at the end
of all MMX technology procedures or subroutines and before calling other procedures
or subroutines that may execute x87 floating-point instructions. If a floating-point
instruction loads one of the registers in the x87 FPU data register stack before
the x87 FPU tag word has been reset by the EMMS instruction, an x87 floating-point
register stack overflow can occur that will result in an x87 floating-point
exception or incorrect result.

EMMS operation is the same in non-64-bit modes and 64-bit mode.

Operation:

x87FPUTagWord <- FFFFH;

Intel C/C++ Compiler Intrinsic Equivalent:
void _mm_empty()


Flags Affected:
None.


Protected Mode Exceptions:
| #UD| If CR0.EM[bit 2] = 1.               
| #NM| If CR0.TS[bit 3] = 1.               
| #MF| If there is a pending FPU exception.
| #UD| If the LOCK prefix is used.         

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: ENTER
description:
ENTER - Make Stack Frame for Procedure Parameters:
| Opcode  | Instruction      | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                 
| C8 iw 00| ENTER imm16, 0   | II   | Valid      | Valid          | Create a stack frame for a procedure.       
| C8 iw 01| ENTER imm16,1    | II   | Valid      | Valid          | Create a nested stack frame for a procedure.
| C8 iw ib| ENTER imm16, imm8| II   | Valid      | Valid          | Create a nested stack frame for a procedure.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| II   | iw       | imm8     | NA       | NA       

Description:
Creates a stack frame for a procedure. The first operand (size operand) specifies
the size of the stack frame (that is, the number of bytes of dynamic storage
allocated on the stack for the procedure). The second operand (nesting level
operand) gives the lexical nesting level (0 to 31) of the procedure. The nesting
level determines the number of stack frame pointers that are copied into the
“display area” of the new stack frame from the preceding frame. Both of these
operands are immediate values.

The stack-size attribute determines whether the BP (16 bits), EBP (32 bits),
or RBP (64 bits) register specifies the current frame pointer and whether SP
(16 bits), ESP (32 bits), or RSP (64 bits) specifies the stack pointer. In 64bit
mode, stack-size attribute is always 64-bits.

The ENTER and companion LEAVE instructions are provided to support block structured
languages. The ENTER instruction (when used) is typically the first instruction
in a procedure and is used to set up a new stack frame for a procedure. The
LEAVE instruction is then used at the end of the procedure (just before the
RET instruction) to release the stack frame.

If the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP
register onto the stack, copies the current stack pointer from the SP/ESP/RSP
register into the BP/EBP/RBP register, and loads the SP/ESP/RSP register with
the current stack-pointer value minus the value in the size operand. For nesting
levels of 1 or greater, the processor pushes additional frame pointers on the
stack before adjusting the stack pointer. These additional frame pointers provide
the called procedure with access points to other nested frames on the stack.
See “Procedure Calls for Block-Structured Languages” in Chapter 6 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more information
about the actions of the ENTER instruction.

The ENTER instruction causes a page fault whenever a write using the final value
of the stack pointer (within the current stack segment) would do so.

In 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot
be encoded.

Operation:

NestingLevel <- NestingLevel MOD 32
IF 64-Bit Mode (StackSize = 64)
  THEN
     Push(RBP);
     FrameTemp <- RSP;
  ELSE IF StackSize = 32
     THEN
       Push(EBP);
       FrameTemp <- ESP; FI;
  ELSE (* StackSize = 16 *)
       Push(BP);
       FrameTemp <- SP;
FI;
IF NestingLevel = 0
  THEN GOTO CONTINUE;
FI;
IF (NestingLevel > 1)
  THEN FOR i <- 1 to (NestingLevel - 1)
     DO
       IF 64-Bit Mode (StackSize = 64)
          THEN
             RBP <- RBP - 8;
             Push([RBP]); (* Quadword push *)
          ELSE IF OperandSize = 32
             THEN
               IF StackSize = 32
                  EBP <- EBP - 4;
                  Push([EBP]); (* Doubleword push *)
               ELSE (* StackSize = 16 *)
                  BP <- BP - 4;
                  Push([BP]); (* Doubleword push *)
               FI;
             FI;
          ELSE (* OperandSize = 16 *)
             IF StackSize = 32
               THEN
                  EBP <- EBP - 2;
                  Push([EBP]); (* Word push *)
               ELSE (* StackSize = 16 *)
                  BP <- BP - 2;
                  Push([BP]); (* Word push *)
             FI;
          FI;
  OD;
FI;
IF 64-Bit Mode (StackSize = 64)
  THEN
     Push(FrameTemp); (* Quadword push *)
  ELSE IF OperandSize = 32
     THEN
       Push(FrameTemp); FI; (* Doubleword push *)
  ELSE (* OperandSize = 16 *)
       Push(FrameTemp); (* Word push *)
FI;
CONTINUE:
IF 64-Bit Mode (StackSize = 64)
  THEN
       RBP <- FrameTemp;
       RSP <- RSP − Size;
  ELSE IF StackSize = 32
     THEN
       EBP <- FrameTemp;
       ESP <- ESP − Size; FI;
  ELSE (* StackSize = 16 *)
       BP <- FrameTemp;
       SP <- SP − Size;
FI;
END;

Flags Affected:
None.


Protected Mode Exceptions:
| #SS(0)         | If the new value of the SP or ESP register
|                | is outside the stack segment limit.       
| #PF(fault-code)| If a page fault occurs or if a write      
|                | using the final value of the stack pointer
|                | (within the current stack segment) would  
|                | cause a page fault.                       
| #UD            | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #SS| If the new value of the SP or ESP register
|    | is outside the stack segment limit.       
| #UD| If the LOCK prefix is used.               

Virtual-8086 Mode Exceptions:
| #SS(0)         | If the new value of the SP or ESP register
|                | is outside the stack segment limit.       
| #PF(fault-code)| If a page fault occurs or if a write      
|                | using the final value of the stack pointer
|                | (within the current stack segment) would  
|                | cause a page fault.                       
| #UD            | If the LOCK prefix is used.               

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If the stack address is in a non-canonical
|                | form.                                     
| #PF(fault-code)| If a page fault occurs or if a write      
|                | using the final value of the stack pointer
|                | (within the current stack segment) would  
|                | cause a page fault.                       
| #UD            | If the LOCK prefix is used.               


platform: x86
mnem: EXTRACTPS
description:
EXTRACTPS  -  Extract Packed Single Precision Floating-Point Value:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 66 0F 3A 17 /r ib EXTRACTPS reg/m32,   | MRI  | V/V           | SSE4_1            | Extract a single-precision floating-point  
| xmm2, imm8                             |      |               |                   | value from xmm2 at the source offset       
|                                        |      |               |                   | specified by imm8 and store the result     
|                                        |      |               |                   | to reg or m32. The upper 32 bits of        
|                                        |      |               |                   | r64 is zeroed if reg is r64.               
| VEX.128.66.0F3A.WIG 17 /r ib VEXTRACTPS| MRI  | V/V           | AVX               | Extract one single-precision floating-point
| r/m32, xmm1, imm8                      |      |               |                   | value from xmm1 at the offset specified    
|                                        |      |               |                   | by imm8 and store the result in reg        
|                                        |      |               |                   | or m32. Zero extend the results in 64-bit  
|                                        |      |               |                   | register if applicable.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MRI  | ModRM:r/m (w)| ModRM:reg (r)| imm8     | NA       

Description:
Extracts a single-precision floating-point value from the source operand (second
operand) at the 32-bit offset specified from imm8. Immediate bits higher than
the most significant offset for the vector length are ignored. The extracted
single-precision floating-point value is stored in the low 32-bits of the destination
operand In 64-bit mode, destination register operand has default operand size
of 64 bits. The upper 32-bits of the register are filled with zero. REX.W is
ignored. 128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode
with a general purpose register (GPR) as a destination operand, the packed single
quantity is zero extended to 64 bits. VEX.128 encoded version: When VEX.128.66.0F3A.W1
17 form is used in 64-bit mode with a general purpose register (GPR) as a destination
operand, the packed single quantity is zero extended to 64 bits. VEX.vvvv is
reserved and must be 1111b otherwise instructions will #UD. The source register
is an XMM register. Imm8[1:0] determine the starting DWORD offset from which
to extract the 32-bit floating-point value. If VEXTRACTPS is encoded with VEX.L=
1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.

Operation:

EXTRACTPS (128-bit Legacy SSE version)
SRC_OFFSET <- IMM8[1:0]
IF ( 64-Bit Mode and DEST is register)
  DEST[31:0] <- (SRC[127:0] » (SRC_OFFET*32)) AND 0FFFFFFFFh
  DEST[63:32] <- 0
ELSE
  DEST[31:0] <- (SRC[127:0] » (SRC_OFFET*32)) AND 0FFFFFFFFh
FI
VEXTRACTPS (VEX.128 encoded version)
SRC_OFFSET <- IMM8[1:0]
IF ( 64-Bit Mode and DEST is register)
  DEST[31:0] <- (SRC[127:0] » (SRC_OFFET*32)) AND 0FFFFFFFFh
  DEST[63:32] <- 0
ELSE
  DEST[31:0] <- (SRC[127:0] » (SRC_OFFET*32)) AND 0FFFFFFFFh
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| EXTRACTPS:| _mm_extractmem_ps (float *dest, __m128
|           | a, const int nidx);                   
| EXTRACTPS:| __m128 _mm_extract_ps (__m128 a, const
|           | int nidx);                            

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L= 1.


platform: x86
mnem: F2XM1
description:
F2XM1 - Compute 2x-1:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                     
| D9 F0 | F2XM1      | Valid      | Valid          | Replace ST(0) with (2ST(0) - 1).

Description:
Computes the exponential value of 2 to the power of the source operand minus
1. The source operand is located in register ST(0) and the result is also stored
in ST(0). The value of the source operand must lie in the range -1.0 to +1.0.
If the source value is outside this range, the result is undefined.

The following table shows the results obtained when computing the exponential
value of various classes of numbers, assuming that neither overflow nor underflow
occurs.


Table 3-26. Results Obtained from F2XM1:
| ST(0) SRC  | ST(0) DEST  
| − 1.0 to −0| − 0.5 to − 0
| − 0        | − 0         
| + 0        | + 0         
| + 0 to +1.0| + 0 to 1.0  
Values other than 2 can be exponentiated using the following formula:

xy ← 2(y * log2x)

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(0) <- (2ST(0) − 1);

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Source operand is an SNaN value or unsupported
|    | format.                                       
| #D | Source is a denormal value.                   
| #U | Result is too small for destination           
|    | format.                                       
| #P | Value cannot be represented exactly           
|    | in destination format.                        

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FABS
description:
FABS - Absolute Value:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                        
| D9 E1 | FABS       | Valid      | Valid          | Replace ST with its absolute value.

Description:
Clears the sign bit of ST(0) to create the absolute value of the operand. The
following table shows the results obtained when creating the absolute value
of various classes of numbers.


Table 3-27. Results Obtained from FABS:
| ST(0) SRC| ST(0) DEST
| − ∞      | + ∞       
| − F      | + F       
| − 0      | + 0       
| + 0      | + 0       
| + F      | + F       
| + ∞      | + ∞       
| NaN      | NaN       
Notes: F Means finite floating-point value.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(0) <- |ST(0)|;

FPU Flags Affected:
| C1        | Set to 0. 
| C0, C2, C3| Undefined.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FADD
description:
FADD/FADDP/FIADD - Add:
| Opcode | Instruction       | 64-Bit Mode| Compat/Leg Mode| Description                         
| D8 /0  | FADD m32fp        | Valid      | Valid          | Add m32fp to ST(0) and store result 
|        |                   |            |                | in ST(0).                           
| DC /0  | FADD m64fp        | Valid      | Valid          | Add m64fp to ST(0) and store result 
|        |                   |            |                | in ST(0).                           
| D8 C0+i| FADD ST(0), ST(i) | Valid      | Valid          | Add ST(0) to ST(i) and store result 
|        |                   |            |                | in ST(0).                           
| DC C0+i| FADD ST(i), ST(0) | Valid      | Valid          | Add ST(i) to ST(0) and store result 
|        |                   |            |                | in ST(i).                           
| DE C0+i| FADDP ST(i), ST(0)| Valid      | Valid          | Add ST(0) to ST(i), store result in 
|        |                   |            |                | ST(i), and pop the register stack.  
| DE C1  | FADDP             | Valid      | Valid          | Add ST(0) to ST(1), store result in 
|        |                   |            |                | ST(1), and pop the register stack.  
| DA /0  | FIADD m32int      | Valid      | Valid          | Add m32int to ST(0) and store result
|        |                   |            |                | in ST(0).                           
| DE /0  | FIADD m16int      | Valid      | Valid          | Add m16int to ST(0) and store result
|        |                   |            |                | in ST(0).                           

Description:
Adds the destination and source operands and stores the sum in the destination
location. The destination operand is always an FPU register; the source operand
can be a register or a memory location. Source operands in memory can be in
single-precision or double-precision floating-point format or in word or doubleword
integer format.

The no-operand version of the instruction adds the contents of the ST(0) register
to the ST(1) register. The oneoperand version adds the contents of a memory
location (either a floating-point or an integer value) to the contents of the
ST(0) register. The two-operand version, adds the contents of the ST(0) register
to the ST(i) register or vice versa. The value in ST(0) can be doubled by coding:

FADD ST(0), ST(0);

The FADDP instructions perform the additional operation of popping the FPU register
stack after storing the result. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. (The
no-operand version of the floating-point add instructions always results in
the register stack being popped. In some assemblers, the mnemonic for this instruction
is FADD rather than FADDP.)

The FIADD instructions convert an integer source operand to double extended-precision
floating-point format before performing the addition.

The table on the following page shows the results obtained when adding various
classes of numbers, assuming that neither overflow nor underflow occurs.

When the sum of two operands with opposite signs is 0, the result is +0, except
for the round toward −∞ mode, in which case the result is −0. When the source
operand is an integer 0, it is treated as a +0.

When both operand are infinities of the same sign, the result is ∞ of the expected
sign. If both operands are infinities of opposite signs, an invalid-operation
exception is generated. See Table 3-28.


Table 3-28. FADD/FADDP/FIADD Results:
DEST

| − ∞− ∞| − F − ∞       | − 0 − ∞| + 0 − ∞| + F − ∞   | + ∞   | NaN NaN
| − ∞   | − F           | SRC    | SRC    | ± F or ± 0| + ∞   | NaN    
| − ∞   | DEST          | − 0    | ± 0    | DEST      | + ∞   | NaN    
| − ∞   | DEST          | ± 0    | + 0    | DEST      | + ∞   | NaN    
| − ∞   | ± F or ± 0 + ∞| SRC + ∞| SRC + ∞| + F + ∞   | + ∞+ ∞| NaN NaN
| NaN   | NaN           | NaN    | NaN    | NaN       | NaN   | NaN    
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-arithmetic-operand| Means integer.
| (#IA) exception.                                       |               
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF Instruction = FIADD
  THEN
     DEST <- DEST + ConvertToDoubleExtendedPrecisionFP(SRC);
  ELSE (* Source operand is floating-point value *)
     DEST <- DEST + SRC;
FI;
IF Instruction = FADDP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                
| #IA| Operand is an SNaN value or unsupported  
|    | format. Operands are infinities of unlike
|    | sign.                                    
| #D | Source operand is a denormal value.      
| #U | Result is too small for destination      
|    | format.                                  
| #O | Result is too large for destination      
|    | format.                                  
| #P | Value cannot be represented exactly      
|    | in destination format.                   

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FBLD
description:
FBLD - Load Binary Coded Decimal:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                        
| DF /4 | FBLD m80dec| Valid      | Valid          | Convert BCD value to floating-point
|       |            |            |                | and push onto the FPU stack.       

Description:
Converts the BCD source operand into double extended-precision floating-point
format and pushes the value onto the FPU stack. The source operand is loaded
without rounding errors. The sign of the source operand is preserved, including
that of −0.

The packed BCD digits are assumed to be in the range 0 through 9; the instruction
does not check for invalid digits (AH through FH). Attempting to load an invalid
encoding produces an undefined result.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

TOP <- TOP − 1;
ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);

FPU Flags Affected:
| C1        | Set to 1 if stack overflow occurred;
|           | otherwise, set to 0.                
| C0, C2, C3| Undefined.                          

Floating-Point Exceptions:
| #IS| Stack overflow occurred.

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FBSTP
description:
FBSTP - Store BCD Integer and Pop:
| Opcode| Instruction | 64-Bit Mode| Compat/Leg Mode| Description                         
| DF /6 | FBSTP m80bcd| Valid      | Valid          | Store ST(0) in m80bcd and pop ST(0).

Description:
Converts the value in the ST(0) register to an 18-digit packed BCD integer,
stores the result in the destination operand, and pops the register stack. If
the source value is a non-integral value, it is rounded to an integer value,
according to rounding mode specified by the RC field of the FPU control word.
To pop the register stack, the processor marks the ST(0) register as empty and
increments the stack pointer (TOP) by 1.

The destination operand specifies the address where the first byte destination
value is to be stored. The BCD value (including its sign bit) requires 10 bytes
of space in memory.

The following table shows the results obtained when storing various classes
of numbers in packed BCD format.


Table 3-29. FBSTP Results:
| ST(0) | DEST − ∞ or Value Too Large for DEST
|       | Format −D **                        
| − 0   | − 0                                 
| + 0   | + 0 **                              
| F ≥ +1| + D + ∞ or Value Too Large for DEST 
|       | Format                              
| NaN   | *                                   
Notes: F Means finite floating-point value. D Means packed-BCD number. * Indicates
floating-point invalid-operation (#IA) exception. ** ±0 or ±1, depending on
the rounding mode.

If the converted value is too large for the destination format, or if the source
operand is an ∞, SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operand
condition is signaled. If the invalid-operation exception is not masked, an
invalid-arithmetic-operand exception (#IA) is generated and no value is stored
in the destination operand. If the invalid-operation exception is masked, the
packed BCD indefinite value is stored in memory.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DEST <- BCD(ST(0));
PopRegisterStack;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Converted value that exceeds 18 BCD    
|    | digits in length. Source operand is    
|    | an SNaN, QNaN, ±∞, or in an unsupported
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a segment register is being loaded     
|                | with a segment selector that points       
|                | to a non-writable segment. If a memory    
|                | operand effective address is outside      
|                | the CS, DS, ES, FS, or GS segment limit.  
|                | If the DS, ES, FS, or GS register contains
|                | a NULL segment selector.                  
| #SS(0)         | If a memory operand effective address     
|                | is outside the SS segment limit.          
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.       
| #PF(fault-code)| If a page fault occurs.                   
| #AC(0)         | If alignment checking is enabled and      
|                | an unaligned memory reference is made     
|                | while the current privilege level is      
|                | 3.                                        
| #UD            | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FCHS
description:
FCHS - Change Sign:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description               
| D9 E0 | FCHS       | Valid      | Valid          | Complements sign of ST(0).

Description:
Complements the sign bit of ST(0). This operation changes a positive value into
a negative value of equal magnitude or vice versa. The following table shows
the results obtained when changing the sign of various classes of numbers.


Table 3-30. FCHS Results:
| ST(0) SRC| ST(0) DEST + ∞+ F + 0 − 0 − F − ∞NaN
Notes: * F means finite floating-point value.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

SignBit(ST(0)) <- NOT (SignBit(ST(0)));

FPU Flags Affected:
| C1        | Set to 0. 
| C0, C2, C3| Undefined.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FCLEX
description:
FCLEX/FNCLEX - Clear Exceptions:
| Opcode* | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                          
| 9B DB E2| FCLEX      | Valid      | Valid          | Clear floating-point exception flags 
|         |            |            |                | after checking for pending unmasked  
|         |            |            |                | floating-point exceptions.           
| DB E2   | FNCLEX*    | Valid      | Valid          | Clear floating-point exception flags 
|         |            |            |                | without checking for pending unmasked
|         |            |            |                | floating-point exceptions.           
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the
exception summary status flag (ES), the stack fault flag (SF), and the busy
flag (B) in the FPU status word. The FCLEX instruction checks for and handles
any pending unmasked floating-point exceptions before clearing the exception
flags; the FNCLEX instruction does not.

The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction
followed by an FNCLEX instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.


IA-32 Architecture Compatibility:
When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode,
it is possible (under unusual circumstances) for an FNCLEX instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel®64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNCLEX instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

This instruction affects only the x87 FPU floating-point exception flags. It
does not affect the SIMD floating-point exception flags in the MXCRS register.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FPUStatusWord[0:7] <- 0;
FPUStatusWord[15] <- 0;

FPU Flags Affected:
The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared.
The C0, C1, C2, and C3 flags are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FCMOVcc
description:
FCMOVcc - Floating-Point Conditional Move:
| Opcode*| Instruction          | 64-Bit Mode| Compat/Leg Mode*| Description                           
| DA C0+i| FCMOVB ST(0), ST(i)  | Valid      | Valid           | Move if below (CF=1).                 
| DA C8+i| FCMOVE ST(0), ST(i)  | Valid      | Valid           | Move if equal (ZF=1).                 
| DA D0+i| FCMOVBE ST(0), ST(i) | Valid      | Valid           | Move if below or equal (CF=1 or ZF=1).
| DA D8+i| FCMOVU ST(0), ST(i)  | Valid      | Valid           | Move if unordered (PF=1).             
| DB C0+i| FCMOVNB ST(0), ST(i) | Valid      | Valid           | Move if not below (CF=0).             
| DB C8+i| FCMOVNE ST(0), ST(i) | Valid      | Valid           | Move if not equal (ZF=0).             
| DB D0+i| FCMOVNBE ST(0), ST(i)| Valid      | Valid           | Move if not below or equal (CF=0 and  
|        |                      |            |                 | ZF=0).                                
| DB D8+i| FCMOVNU ST(0), ST(i) | Valid      | Valid           | Move if not unordered (PF=0).         
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Tests the status flags in the EFLAGS register and moves the source operand (second
operand) to the destination operand (first operand) if the given test condition
is true. The condition for each mnemonic os given in the Description column
above and in Chapter 8 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1. The source operand is always in the ST(i) register and the
destination operand is always ST(0).

The FCMOVcc instructions are useful for optimizing small IF constructions. They
also help eliminate branching overhead for IF operations and the possibility
of branch mispredictions by the processor.

A processor may not support the FCMOVcc instructions. Software can check if
the FCMOVcc instructions are supported by checking the processor's feature information
with the CPUID instruction (see “COMISS - Compare Scalar Ordered Single-Precision
Floating-Point Values and Set EFLAGS” in this chapter). If both the CMOV and
FPU feature bits are set, the FCMOVcc instructions are supported.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6
family processors and are not available in earlier IA-32 processors.

Operation:

IF condition TRUE
  THEN ST(0) <- ST(i);
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.

Integer Flags Affected:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FCOM
description:
FCOM/FCOMP/FCOMPP - Compare Floating Point Values:
| Opcode | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                              
| D8 /2  | FCOM m32fp | Valid      | Valid          | Compare ST(0) with m32fp.                
| DC /2  | FCOM m64fp | Valid      | Valid          | Compare ST(0) with m64fp.                
| D8 D0+i| FCOM ST(i) | Valid      | Valid          | Compare ST(0) with ST(i).                
| D8 D1  | FCOM       | Valid      | Valid          | Compare ST(0) with ST(1).                
| D8 /3  | FCOMP m32fp| Valid      | Valid          | Compare ST(0) with m32fp and pop register
|        |            |            |                | stack.                                   
| DC /3  | FCOMP m64fp| Valid      | Valid          | Compare ST(0) with m64fp and pop register
|        |            |            |                | stack.                                   
| D8 D8+i| FCOMP ST(i)| Valid      | Valid          | Compare ST(0) with ST(i) and pop register
|        |            |            |                | stack.                                   
| D8 D9  | FCOMP      | Valid      | Valid          | Compare ST(0) with ST(1) and pop register
|        |            |            |                | stack.                                   
| DE D9  | FCOMPP     | Valid      | Valid          | Compare ST(0) with ST(1) and pop register
|        |            |            |                | stack twice.                             

Description:
Compares the contents of register ST(0) and source value and sets condition
code flags C0, C2, and C3 in the FPU status word according to the results (see
the table below). The source operand can be a data register or a memory location.
If no source operand is given, the value in ST(0) is compared with the value
in ST(1). The sign of zero is ignored, so that -0.0 is equal to +0.0.


Table 3-31. FCOM/FCOMP/FCOMPP Results:
| Condition| C3 0 0 1 1| C2 0 0 0 1| C0 0 1 0 1
Notes: * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception
is generated.

This instruction checks the class of the numbers being compared (see “FXAM - Examine
ModR/M” in this chapter). If either operand is a NaN or is in an unsupported
format, an invalid-arithmetic-operand exception (#IA) is raised and, if the
exception is masked, the condition flags are set to “unordered.” If the invalid-arithmetic-operand
exception is unmasked, the condition code flags are not set.

The FCOMP instruction pops the register stack following the comparison operation
and the FCOMPP instruction pops the register stack twice following the comparison
operation. To pop the register stack, the processor marks the ST(0) register
as empty and increments the stack pointer (TOP) by 1.

The FCOM instructions perform the same operation as the FUCOM instructions.
The only difference is how they handle QNaN operands. The FCOM instructions
raise an invalid-arithmetic-operand exception (#IA) when either or both of the
operands is a NaN value or is in an unsupported format. The FUCOM instructions
perform the same operation as the FCOM instructions, except that they do not
generate an invalid-arithmetic-operand exception for QNaNs.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CASE (relation of operands) OF
  ST > SRC:
  ST < SRC:
  ST = SRC:
ESAC;
IF ST(0) or SRC = NaN or unsupported format
  THEN
     #IA
     IF FPUControlWord.IM = 1
       THEN
          C3, C2, C0 <- 111;
     FI;
FI;
IF Instruction = FCOMP
  THEN
     PopRegisterStack;
FI;
IF Instruction = FCOMPP
  THEN
     PopRegisterStack;
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0.                  
| C0, C2, C3| See table on previous page.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                
| #IA| One or both operands are NaN values      
|    | or have unsupported formats. Register    
|    | is marked empty.                         
| #D | One or both operands are denormal values.

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FCOMI
description:
FCOMI/FCOMIP/FUCOMI/FUCOMIP - Compare Floating Point Values and Set EFLAGS:
| Opcode | Instruction      | 64-Bit Mode| Compat/Leg Mode| Description                                  
| DB F0+i| FCOMI ST, ST(i)  | Valid      | Valid          | Compare ST(0) with ST(i) and set status      
|        |                  |            |                | flags accordingly.                           
| DF F0+i| FCOMIP ST, ST(i) | Valid      | Valid          | Compare ST(0) with ST(i), set status         
|        |                  |            |                | flags accordingly, and pop register          
|        |                  |            |                | stack.                                       
| DB E8+i| FUCOMI ST, ST(i) | Valid      | Valid          | Compare ST(0) with ST(i), check for          
|        |                  |            |                | ordered values, and set status flags         
|        |                  |            |                | accordingly.                                 
| DF E8+i| FUCOMIP ST, ST(i)| Valid      | Valid          | Compare ST(0) with ST(i), check for          
|        |                  |            |                | ordered values, set status flags accordingly,
|        |                  |            |                | and pop register stack.                      

Description:
Performs an unordered comparison of the contents of registers ST(0) and ST(i)
and sets the status flags ZF, PF, and CF in the EFLAGS register according to
the results (see the table below). The sign of zero is ignored for comparisons,
so that -0.0 is equal to +0.0.


Table 3-32. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results:
| Comparison Results*| ZF| PF| CF
| ST0 > ST(i)        | 0 | 0 | 0 
| ST0 < ST(i)        | 0 | 0 | 1 
| ST0 = ST(i)        | 1 | 0 | 0 
| Unordered**        | 1 | 1 | 1 
Notes: * See the IA-32 Architecture Compatibility section below. ** Flags not
set if unmasked invalid-arithmetic-operand (#IA) exception is generated.

An unordered comparison checks the class of the numbers being compared (see
“FXAM - Examine ModR/M” in this chapter). The FUCOMI/FUCOMIP instructions perform
the same operations as the FCOMI/FCOMIP instructions. The only difference is
that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception
(#IA) only when either or both operands are an SNaN or are in an unsupported
format; QNaNs cause the condition code flags to be set to unordered, but do
not cause an exception to be generated. The FCOMI/FCOMIP instructions raise
an invalid-operation exception when either or both of the operands are a NaN
value of any kind or are in an unsupported format.

If the operation results in an invalid-arithmetic-operand exception being raised,
the status flags in the EFLAGS register are set only if the exception is masked.

The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags
to zero in the EFLAGS register (regardless of whether an invalid-operation exception
is detected).

The FCOMIP and FUCOMIP instructions also pop the register stack following the
comparison operation. To pop the register stack, the processor marks the ST(0)
register as empty and increments the stack pointer (TOP) by 1.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture
in the P6 family processors and are not available in earlier IA-32 processors.

Operation:

CASE (relation of operands) OF
  ST(0) > ST(i):
  ST(0) < ST(i):
  ST(0) = ST(i):
ESAC;
IF Instruction is FCOMI or FCOMIP
  THEN
     IF ST(0) or ST(i) = NaN or unsupported format
       THEN
          #IA
          IF FPUControlWord.IM = 1
             THEN
               ZF, PF, CF <- 111;
          FI;
     FI;
FI;
IF Instruction is FUCOMI or FUCOMIP
  THEN
     IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format
       THEN
          ZF, PF, CF <- 111;
       ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)
          #IA;
          IF FPUControlWord.IM = 1
             THEN
               ZF, PF, CF <- 111;
          FI;
     FI;
FI;
IF Instruction is FCOMIP or FUCOMIP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0.    
| C0, C2, C3| Not affected.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| (FCOMI or FCOMIP instruction) One or   
|    | both operands are NaN values or have   
|    | unsupported formats. (FUCOMI or FUCOMIP
|    | instruction) One or both operands are  
|    | SNaN values (but not QNaNs) or have    
|    | undefined formats. Detection of a QNaN 
|    | value does not raise an invalid-operand
|    | exception.                             

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FCOS
description:
FCOS - Cosine:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                   
| D9 FF | FCOS       | Valid      | Valid          | Replace ST(0) with its cosine.

Description:
Computes the cosine of the source operand in register ST(0) and stores the result
in ST(0). The source operand must be given in radians and must be within the
range −263 to +263. The following table shows the results obtained when taking
the cosine of various classes of numbers.


Table 3-33. FCOS Results:
| ST(0) SRC − ∞| ST(0) DEST
| − F          | −1 to +1  
| − 0          | +1        
| + 0          | +1        
| + F + ∞      | − 1 to + 1
| NaN          | NaN       
Notes: F Means finite floating-point value.

| *| Indicates floating-point invalid-arithmetic-operand
|  | (#IA) exception.                                   
If the source operand is outside the acceptable range, the C2 flag in the FPU
status word is set, and the value in register ST(0) remains unchanged. The instruction
does not raise an exception when the source operand is out of range. It is up
to the program to check the C2 flag for out-of-range conditions. Source values
outside the range −263 to +263 can be reduced to the range of the instruction
by subtracting an appropriate integer multiple of 2π or by using the FPREM instruction
with a divisor of 2π. See the section titled “Pi” in Chapter 8 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion
of the proper value to use for π in performing such reductions.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF |ST(0)| < 263
THEN
  C2 <- 0;
  ST(0) <- cosine(ST(0));
ELSE (* Source operand is out-of-range *)
  C2 <- 1;
FI;

FPU Flags Affected:
| C1    | Set to 0 if stack underflow occurred.   
|       | Set if result was rounded up; cleared   
|       | otherwise. Undefined if C2 is 1.        
| C2    | Set to 1 if outside range (−263 < source
|       | operand < +263); otherwise, set to 0.   
| C0, C3| Undefined.                              

Floating-Point Exceptions:
| #IS| Stack underflow occurred.          
| #IA| Source operand is an SNaN value, ∞,
|    | or unsupported format.             
| #D | Source is a denormal value.        
| #P | Value cannot be represented exactly
|    | in destination format.             

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FDECSTP
description:
FDECSTP - Decrement Stack-Top Pointer:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                            
| D9 F6 | FDECSTP    | Valid      | Valid          | Decrement TOP field in FPU status word.

Description:
Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack
pointer). If the TOP field contains a 0, it is set to 7. The effect of this
instruction is to rotate the stack by one position. The contents of the FPU
data registers and tag register are not affected.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF TOP = 0
  THEN TOP <- 7;
  ELSE TOP <- TOP - 1;
FI;

FPU Flags Affected:
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FDIV
description:
FDIV/FDIVP/FIDIV - Divide:
| Opcode | Instruction       | 64-Bit Mode| Compat/Leg Mode| Description                            
| D8 /6  | FDIV m32fp        | Valid      | Valid          | Divide ST(0) by m32fp and store result 
|        |                   |            |                | in ST(0).                              
| DC /6  | FDIV m64fp        | Valid      | Valid          | Divide ST(0) by m64fp and store result 
|        |                   |            |                | in ST(0).                              
| D8 F0+i| FDIV ST(0), ST(i) | Valid      | Valid          | Divide ST(0) by ST(i) and store result 
|        |                   |            |                | in ST(0).                              
| DC F8+i| FDIV ST(i), ST(0) | Valid      | Valid          | Divide ST(i) by ST(0) and store result 
|        |                   |            |                | in ST(i).                              
| DE F8+i| FDIVP ST(i), ST(0)| Valid      | Valid          | Divide ST(i) by ST(0), store result    
|        |                   |            |                | in ST(i), and pop the register stack.  
| DE F9  | FDIVP             | Valid      | Valid          | Divide ST(1) by ST(0), store result    
|        |                   |            |                | in ST(1), and pop the register stack.  
| DA /6  | FIDIV m32int      | Valid      | Valid          | Divide ST(0) by m32int and store result
|        |                   |            |                | in ST(0).                              
| DE /6  | FIDIV m16int      | Valid      | Valid          | Divide ST(0) by m16int and store result
|        |                   |            |                | in ST(0).                              

Description:
Divides the destination operand by the source operand and stores the result
in the destination location. The destination operand (dividend) is always in
an FPU register; the source operand (divisor) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision
floating-point format, word or doubleword integer format.

The no-operand version of the instruction divides the contents of the ST(1)
register by the contents of the ST(0) register. The one-operand version divides
the contents of the ST(0) register by the contents of a memory location (either
a floating-point or an integer value). The two-operand version, divides the
contents of the ST(0) register by the contents of the ST(i) register or vice
versa.

The FDIVP instructions perform the additional operation of popping the FPU register
stack after storing the result. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. The
no-operand version of the floating-point divide instructions always results
in the register stack being popped. In some assemblers, the mnemonic for this
instruction is FDIV rather than FDIVP.

The FIDIV instructions convert an integer source operand to double extended-precision
floating-point format before performing the division. When the source operand
is an integer 0, it is treated as a +0.

If an unmasked divide-by-zero exception (#Z) is generated, no result is stored;
if the exception is masked, an ∞ of the appropriate sign is stored in the destination
operand.

The following table shows the results obtained when dividing various classes
of numbers, assuming that neither overflow nor underflow occurs.


Table 3-34. FDIV/FDIVP/FIDIV Results:
DEST

| − ∞      | − F + 0 | − 0 + 0| + 0 − 0| + F − 0 | + ∞      | NaN NaN    
| + ∞      | + F     | + 0    | − 0    | − F     | − ∞      | NaN        
| + ∞+ ∞− ∞| + F ****| + 0    | − 0    | − F ****| − ∞− ∞+ ∞| NaN NaN NaN
| − ∞      | − F     | − 0    | + 0    | + F     | + ∞      | NaN        
| − ∞      | − F − 0 | − 0 − 0| + 0 + 0| + F + 0 | + ∞      | NaN NaN    
| NaN      | NaN     | NaN    | NaN    | NaN     | NaN      | NaN        
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-arithmetic-operand| Means integer.
| (#IA) exception. ** Indicates floating-point           |               
| zero-divide (#Z) exception.                            |               
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF SRC = 0
  THEN
     #Z;
  ELSE
     IF Instruction is FIDIV
       THEN
          DEST <- DEST / ConvertToDoubleExtendedPrecisionFP(SRC);
       ELSE (* Source operand is floating-point value *)
          DEST <- DEST / SRC;
     FI;
FI;
IF Instruction = FDIVP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Operand is an SNaN value or unsupported
|    | format. ±∞ / ±∞; ±0 / ±0               
| #D | Source is a denormal value.            
| #Z | DEST / ±0, where DEST is not equal to  
|    | ±0.                                    
| #U | Result is too small for destination    
|    | format.                                
| #O | Result is too large for destination    
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FDIVR
description:
FDIVR/FDIVRP/FIDIVR - Reverse Divide:
| Opcode | Instruction        | 64-Bit Mode| Compat/Leg Mode| Description                            
| D8 /7  | FDIVR m32fp        | Valid      | Valid          | Divide m32fp by ST(0) and store result 
|        |                    |            |                | in ST(0).                              
| DC /7  | FDIVR m64fp        | Valid      | Valid          | Divide m64fp by ST(0) and store result 
|        |                    |            |                | in ST(0).                              
| D8 F8+i| FDIVR ST(0), ST(i) | Valid      | Valid          | Divide ST(i) by ST(0) and store result 
|        |                    |            |                | in ST(0).                              
| DC F0+i| FDIVR ST(i), ST(0) | Valid      | Valid          | Divide ST(0) by ST(i) and store result 
|        |                    |            |                | in ST(i).                              
| DE F0+i| FDIVRP ST(i), ST(0)| Valid      | Valid          | Divide ST(0) by ST(i), store result    
|        |                    |            |                | in ST(i), and pop the register stack.  
| DE F1  | FDIVRP             | Valid      | Valid          | Divide ST(0) by ST(1), store result    
|        |                    |            |                | in ST(1), and pop the register stack.  
| DA /7  | FIDIVR m32int      | Valid      | Valid          | Divide m32int by ST(0) and store result
|        |                    |            |                | in ST(0).                              
| DE /7  | FIDIVR m16int      | Valid      | Valid          | Divide m16int by ST(0) and store result
|        |                    |            |                | in ST(0).                              

Description:
Divides the source operand by the destination operand and stores the result
in the destination location. The destination operand (divisor) is always in
an FPU register; the source operand (dividend) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision
floating-point format, word or doubleword integer format.

These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV
instructions. They are provided to support more efficient coding.

The no-operand version of the instruction divides the contents of the ST(0)
register by the contents of the ST(1) register. The one-operand version divides
the contents of a memory location (either a floating-point or an integer value)
by the contents of the ST(0) register. The two-operand version, divides the
contents of the ST(i) register by the contents of the ST(0) register or vice
versa.

The FDIVRP instructions perform the additional operation of popping the FPU
register stack after storing the result. To pop the register stack, the processor
marks the ST(0) register as empty and increments the stack pointer (TOP) by
1. The no-operand version of the floating-point divide instructions always results
in the register stack being popped. In some assemblers, the mnemonic for this
instruction is FDIVR rather than FDIVRP.

The FIDIVR instructions convert an integer source operand to double extended-precision
floating-point format before performing the division.

If an unmasked divide-by-zero exception (#Z) is generated, no result is stored;
if the exception is masked, an ∞ of the appropriate sign is stored in the destination
operand.

The following table shows the results obtained when dividing various classes
of numbers, assuming that neither overflow nor underflow occurs.


Table 3-35. FDIVR/FDIVRP/FIDIVR Results:
DEST

| − ∞     | − F + ∞    | − 0 + ∞| + 0 − ∞| + F − ∞    | + ∞     | NaN NaN    
| +0      | + F        | **     | **     | − F        | −0      | NaN        
| +0 +0 −0| + F + 0 − 0| **     | **     | − F − 0 + 0| −0 −0 +0| NaN NaN NaN
| −0      | − F        | **     | **     | + F        | +0      | NaN        
| −0      | − F − ∞    | **− ∞  | **+ ∞  | + F + ∞    | +0      | NaN NaN    
| NaN     | NaN        | NaN    | NaN    | NaN        | NaN     | NaN        
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-arithmetic-operand| Means integer.
| (#IA) exception. ** Indicates floating-point           |               
| zero-divide (#Z) exception.                            |               
When the source operand is an integer 0, it is treated as a +0. This instruction's
operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF DEST = 0
  THEN
     #Z;
  ELSE
     IF Instruction = FIDIVR
       THEN
          DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;
       ELSE (* Source operand is floating-point value *)
          DEST <- SRC / DEST;
     FI;
FI;
IF Instruction = FDIVRP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Operand is an SNaN value or unsupported
|    | format. ±∞ / ±∞; ±0 / ±0               
| #D | Source is a denormal value.            
| #Z | SRC / ±0, where SRC is not equal to    
|    | ±0.                                    
| #U | Result is too small for destination    
|    | format.                                
| #O | Result is too large for destination    
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FFREE
description:
FFREE - Free Floating-Point Register:
| Opcode | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                 
| DD C0+i| FFREE ST(i)| Valid      | Valid          | Sets tag for ST(i) to empty.

Description:
Sets the tag in the FPU tag register associated with register ST(i) to empty
(11B). The contents of ST(i) and the FPU stack-top pointer (TOP) are not affected.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

TAG(i) <- 11B;

FPU Flags Affected:
C0, C1, C2, C3 undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FICOM
description:
FICOM/FICOMP - Compare Integer:
| Opcode| Instruction  | 64-Bit Mode| Compat/Leg Mode| Description                            
| DE /2 | FICOM m16int | Valid      | Valid          | Compare ST(0) with m16int.             
| DA /2 | FICOM m32int | Valid      | Valid          | Compare ST(0) with m32int.             
| DE /3 | FICOMP m16int| Valid      | Valid          | Compare ST(0) with m16int and pop stack
|       |              |            |                | register.                              
| DA /3 | FICOMP m32int| Valid      | Valid          | Compare ST(0) with m32int and pop stack
|       |              |            |                | register.                              

Description:
Compares the value in ST(0) with an integer source operand and sets the condition
code flags C0, C2, and C3 in the FPU status word according to the results (see
table below). The integer value is converted to double extendedprecision floating-point
format before the comparison is made.


Table 3-36. FICOM/FICOMP Results:
| Condition| C3 0 0 1| C2 0 0 0| C0 0 1 0
| Unordered| 1       | 1       | 1       
These instructions perform an “unordered comparison.” An unordered comparison
also checks the class of the numbers being compared (see “FXAM - Examine ModR/M”
in this chapter). If either operand is a NaN or is in an undefined format, the
condition flags are set to “unordered.”

The sign of zero is ignored, so that -0.0 ← +0.0.

The FICOMP instructions pop the register stack following the comparison. To
pop the register stack, the processor marks the ST(0) register empty and increments
the stack pointer (TOP) by 1.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CASE (relation of operands) OF
  ST(0) > SRC:
  ST(0) < SRC:
  ST(0) = SRC:
  Unordered:
ESAC;
IF Instruction = FICOMP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0.                  
| C0, C2, C3| See table on previous page.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                
| #IA| One or both operands are NaN values      
|    | or have unsupported formats.             
| #D | One or both operands are denormal values.

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FILD
description:
FILD - Load Integer:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                             
| DF /0 | FILD m16int| Valid      | Valid          | Push m16int onto the FPU register stack.
| DB /0 | FILD m32int| Valid      | Valid          | Push m32int onto the FPU register stack.
| DF /5 | FILD m64int| Valid      | Valid          | Push m64int onto the FPU register stack.

Description:
Converts the signed-integer source operand into double extended-precision floating-point
format and pushes the value onto the FPU register stack. The source operand
can be a word, doubleword, or quadword integer. It is loaded without rounding
errors. The sign of the source operand is preserved.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

TOP <- TOP − 1;
ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);

FPU Flags Affected:
| C1        | Set to 1 if stack overflow occurred;
|           | set to 0 otherwise.                 
| C0, C2, C3| Undefined.                          

Floating-Point Exceptions:
| #IS| Stack overflow occurred.

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FINCSTP
description:
FINCSTP - Increment Stack-Top Pointer:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                              
| D9 F7 | FINCSTP    | Valid      | Valid          | Increment the TOP field in the FPU status
|       |            |            |                | register.                                

Description:
Adds one to the TOP field of the FPU status word (increments the top-of-stack
pointer). If the TOP field contains a 7, it is set to 0. The effect of this
instruction is to rotate the stack by one position. The contents of the FPU
data registers and tag register are not affected. This operation is not equivalent
to popping the stack, because the tag for the previous top-of-stack register
is not marked empty.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF TOP = 7
  THEN TOP <- 0;
  ELSE TOP <- TOP + 1;
FI;

FPU Flags Affected:
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FINIT
description:
FINIT/FNINIT - Initialize Floating-Point Unit:
| Opcode  | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                                
| 9B DB E3| FINIT      | Valid      | Valid          | Initialize FPU after checking for pending  
|         |            |            |                | unmasked floating-point exceptions.        
| DB E3   | FNINIT*    | Valid      | Valid          | Initialize FPU without checking for        
|         |            |            |                | pending unmasked floating-point exceptions.
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Sets the FPU control, status, tag, instruction pointer, and data pointer registers
to their default states. The FPU control word is set to 037FH (round to nearest,
all exceptions masked, 64-bit precision). The status word is cleared (no exception
flags set, TOP is set to 0). The data registers in the register stack are left
unchanged, but they are all tagged as empty (11B). Both the instruction and
data pointers are cleared.

The FINIT instruction checks for and handles any pending unmasked floating-point
exceptions before performing the initialization; the FNINIT instruction does
not.

The assembler issues two instructions for the FINIT instruction (an FWAIT instruction
followed by an FNINIT instruction), and the processor executes each of these
instructions in separately. If an exception is generated for either of these
instructions, the save EIP points to the instruction that caused the exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode,
it is possible (under unusual circumstances) for an FNINIT instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel®64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNINIT instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

In the Intel387 math coprocessor, the FINIT/FNINIT instruction does not clear
the instruction and data pointers.

This instruction affects only the x87 FPU. It does not affect the XMM and MXCSR
registers.

Operation:

FPUControlWord <- 037FH;
FPUStatusWord <- 0;
FPUTagWord <- FFFFH;
FPUDataPointer <- 0;
FPUInstructionPointer <- 0;
FPULastInstructionOpcode <- 0;

FPU Flags Affected:
C0, C1, C2, C3 set to 0.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FIST
description:
FIST/FISTP - Store Integer:
| Opcode| Instruction | 64-Bit Mode| Compat/Leg Mode| Description                           
| DF /2 | FIST m16int | Valid      | Valid          | Store ST(0) in m16int.                
| DB /2 | FIST m32int | Valid      | Valid          | Store ST(0) in m32int.                
| DF /3 | FISTP m16int| Valid      | Valid          | Store ST(0) in m16int and pop register
|       |             |            |                | stack.                                
| DB /3 | FISTP m32int| Valid      | Valid          | Store ST(0) in m32int and pop register
|       |             |            |                | stack.                                
| DF /7 | FISTP m64int| Valid      | Valid          | Store ST(0) in m64int and pop register
|       |             |            |                | stack.                                

Description:
The FIST instruction converts the value in the ST(0) register to a signed integer
and stores the result in the destination operand. Values can be stored in word
or doubleword integer format. The destination operand specifies the address
where the first byte of the destination value is to be stored.

The FISTP instruction performs the same operation as the FIST instruction and
then pops the register stack. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. The
FISTP instruction also stores values in quadword integer format.

The following table shows the results obtained when storing various classes
of numbers in integer format.


Table 3-37. FIST/FISTP Results:
| ST(0)  | DEST − ∞ or Value Too Large for DEST   
|        | Format                                 
| F ≤ −1 | − I **                                 
| − 0    | 0                                      
| + 0 NaN| 0 **+ I + ∞ or Value Too Large for DEST
|        | Format                                 
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-operation| Means integer.
| (#IA) exception. ** 0 or ±1, depending        |               
| on the rounding mode.                         |               
If the source value is a non-integral value, it is rounded to an integer value,
according to the rounding mode specified by the RC field of the FPU control
word.

If the converted value is too large for the destination format, or if the source
operand is an ∞, SNaN, QNAN, or is in an unsupported format, an invalid-arithmetic-operand
condition is signaled. If the invalid-operation exception is not masked, an
invalid-arithmetic-operand exception (#IA) is generated and no value is stored
in the destination operand. If the invalid-operation exception is masked, the
integer indefinite value is stored in memory.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DEST <- Integer(ST(0));
IF Instruction = FISTP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred. 
|           | Indicates rounding direction of if the
|           | inexact exception (#P) is generated:  
|           | 0 ← not roundup; 1 ← roundup. Set to  
|           | 0 otherwise.                          
| C0, C2, C3| Undefined.                            

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                
| #IA| Converted value is too large for the     
|    | destination format. Source operand is    
|    | an SNaN, QNaN, ±∞, or unsupported format.
| #P | Value cannot be represented exactly      
|    | in destination format.                   

Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.            
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FISTTP
description:
FISTTP - Store Integer with Truncation:
| Opcode| Instruction  | 64-Bit Mode| Compat/Leg Mode| Description                           
| DF /1 | FISTTP m16int| Valid      | Valid          | Store ST(0) in m16int with truncation.
| DB /1 | FISTTP m32int| Valid      | Valid          | Store ST(0) in m32int with truncation.
| DD /1 | FISTTP m64int| Valid      | Valid          | Store ST(0) in m64int with truncation.

Description:
FISTTP converts the value in ST into a signed integer using truncation (chop)
as rounding mode, transfers the result to the destination, and pop ST. FISTTP
accepts word, short integer, and long integer destinations.

The following table shows the results obtained when storing various classes
of numbers in integer format.


Table 3-38. FISTTP Results:
| ST(0)                             | DEST     
| Value Too Large for DEST Format   | − ∞ or   
| − 1                               | − I 0 + I
| or Value Too Large for DEST Format| + ∞NaN   
Notes: F Means finite floating-point value. Ι Means integer. * Indicates floating-point
invalid-operation (#IA) exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DEST <- ST;
pop ST;

Flags Affected:
C1 is cleared; C0, C2, C3 undefined.


Numeric Exceptions:
Invalid, Stack Invalid (stack underflow), Precision.


Protected Mode Exceptions:
| #GP(0)         | If the destination is in a nonwritable   
|                | segment. For an illegal memory operand   
|                | effective address in the CS, DS, ES,     
|                | FS or GS segments.                       
| #SS(0)         | For an illegal address in the SS segment.
| #PF(fault-code)| For a page fault.                        
| #AC(0)         | If alignment checking is enabled and     
|                | an unaligned memory reference is made    
|                | while the current privilege level is     
|                | 3.                                       
| #NM            | If CR0.EM[bit 2] = 1. If CR0.TS[bit      
|                | 3] = 1.                                  
| #UD            | If CPUID.01H:ECX.SSE3[bit 0] = 0. If     
|                | the LOCK prefix is used.                 

Real Address Mode Exceptions:
| GP(0)| If any part of the operand would lie  
|      | outside of the effective address space
|      | from 0 to 0FFFFH.                     
| #NM  | If CR0.EM[bit 2] = 1. If CR0.TS[bit   
|      | 3] = 1.                               
| #UD  | If CPUID.01H:ECX.SSE3[bit 0] = 0. If  
|      | the LOCK prefix is used.              

Virtual 8086 Mode Exceptions:
| GP(0)          | If any part of the operand would lie  
|                | outside of the effective address space
|                | from 0 to 0FFFFH.                     
| #NM            | If CR0.EM[bit 2] = 1. If CR0.TS[bit   
|                | 3] = 1.                               
| #UD            | If CPUID.01H:ECX.SSE3[bit 0] = 0. If  
|                | the LOCK prefix is used.              
| #PF(fault-code)| For a page fault.                     
| #AC(0)         | For unaligned memory reference if the 
|                | current privilege is 3.               

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3. If the LOCK prefix is used.             


platform: x86
mnem: FLD
description:
FLD - Load Floating Point Value:
| Opcode | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                            
| D9 /0  | FLD m32fp  | Valid      | Valid          | Push m32fp onto the FPU register stack.
| DD /0  | FLD m64fp  | Valid      | Valid          | Push m64fp onto the FPU register stack.
| DB /5  | FLD m80fp  | Valid      | Valid          | Push m80fp onto the FPU register stack.
| D9 C0+i| FLD ST(i)  | Valid      | Valid          | Push ST(i) onto the FPU register stack.

Description:
Pushes the source operand onto the FPU register stack. The source operand can
be in single-precision, doubleprecision, or double extended-precision floating-point
format. If the source operand is in single-precision or double-precision floating-point
format, it is automatically converted to the double extended-precision floatingpoint
format before being pushed on the stack.

The FLD instruction can also push the value in a selected FPU register [ST(i)]
onto the stack. Here, pushing register ST(0) duplicates the stack top.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF SRC is ST(i)
  THEN
     temp <- ST(i);
FI;
TOP <- TOP − 1;
IF SRC is memory-operand
  THEN
     ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);
  ELSE (* SRC is ST(i) *)
     ST(0) <- temp;
FI;

FPU Flags Affected:
| C1        | Set to 1 if stack overflow occurred;
|           | otherwise, set to 0.                
| C0, C2, C3| Undefined.                          

Floating-Point Exceptions:
| #IS| Stack underflow or overflow occurred.         
| #IA| Source operand is an SNaN. Does not           
|    | occur if the source operand is in double      
|    | extended-precision floating-point format      
|    | (FLD m80fp or FLD ST(i)).                     
| #D | Source operand is a denormal value.           
|    | Does not occur if the source operand          
|    | is in double extended-precision floating-point
|    | format.                                       

Protected Mode Exceptions:
| #GP(0)         | If destination is located in a non-writable
|                | segment. If a memory operand effective     
|                | address is outside the CS, DS, ES, FS,     
|                | or GS segment limit. If the DS, ES,        
|                | FS, or GS register is used to access       
|                | memory and it contains a NULL segment      
|                | selector.                                  
| #SS(0)         | If a memory operand effective address      
|                | is outside the SS segment limit.           
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FLD1
description:
FLD1/FLDL2T/FLDL2E/FLDPI/FLDLG2/FLDLN2/FLDZ - Load Constant:
| Opcode*| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                                
| D9 E8  | FLD1       | Valid      | Valid          | Push +1.0 onto the FPU register stack.     
| D9 E9  | FLDL2T     | Valid      | Valid          | Push log<sub>2</sub>10 onto the FPU        
|        |            |            |                | register stack.                            
| D9 EA  | FLDL2E     | Valid      | Valid          | Push log<sub>2</sub>e onto the FPU register
|        |            |            |                | stack.                                     
| D9 EB  | FLDPI      | Valid      | Valid          | Push π onto the FPU register stack.        
| D9 EC  | FLDLG2     | Valid      | Valid          | Push log<sub>10</sub>2 onto the FPU        
|        |            |            |                | register stack.                            
| D9 ED  | FLDLN2     | Valid      | Valid          | Push log<sub>e</sub>2 onto the FPU register
|        |            |            |                | stack.                                     
| D9 EE  | FLDZ       | Valid      | Valid          | Push +0.0 onto the FPU register stack.     
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Push one of seven commonly used constants (in double extended-precision floating-point
format) onto the FPU register stack. The constants that can be loaded with these
instructions include +1.0, +0.0, log<sub>2</sub>10, log<sub>2</sub>e, π, log<sub>10</sub>2,
and log<sub>e</sub>2. For each constant, an internal 66-bit constant is rounded
(as specified by the RC field in the FPU control word) to double extended-precision
floating-point format. The inexact-result exception (#P) is not generated as
a result of the rounding, nor is the C1 flag set in the x87 FPU status word
if the value is rounded up.

See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1, for a description of the π constant.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
When the RC field is set to round-to-nearest, the FPU produces the same constants
that is produced by the Intel 8087 and Intel 287 math coprocessors.

Operation:

TOP <- TOP − 1;
ST(0) <- CONSTANT;

FPU Flags Affected:
| C1        | Set to 1 if stack overflow occurred;
|           | otherwise, set to 0.                
| C0, C2, C3| Undefined.                          

Floating-Point Exceptions:
| #IS| Stack overflow occurred.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FLDCW
description:
FLDCW - Load x87 FPU Control Word:
| Opcode| Instruction | 64-Bit Mode| Compat/Leg Mode| Description                       
| D9 /5 | FLDCW m2byte| Valid      | Valid          | Load FPU control word from m2byte.

Description:
Loads the 16-bit source operand into the FPU control word. The source operand
is a memory location. This instruction is typically used to establish or change
the FPU's mode of operation.

If one or more exception flags are set in the FPU status word prior to loading
a new FPU control word and the new control word unmasks one or more of those
exceptions, a floating-point exception will be generated upon execution of the
next floating-point instruction (except for the no-wait floating-point instructions,
see the section titled “Software Exception Handling” in Chapter 8 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1). To avoid
raising exceptions when changing FPU operating modes, clear any pending exceptions
(using the FCLEX or FNCLEX instruction) before loading the new control word.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FPUControlWord <- SRC;

FPU Flags Affected:
C0, C1, C2, C3 undefined.


Floating-Point Exceptions:
None; however, this operation might unmask a pending exception in the FPU status
word. That exception is then generated upon execution of the next “waiting”
floating-point instruction.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FLDENV
description:
FLDENV - Load x87 FPU Environment:
| Opcode| Instruction      | 64-Bit Mode| Compat/Leg Mode| Description                         
| D9 /4 | FLDENV m14/28byte| Valid      | Valid          | Load FPU environment from m14byte or
|       |                  |            |                | m28byte.                            

Description:
Loads the complete x87 FPU operating environment from memory into the FPU registers.
The source operand specifies the first byte of the operating-environment data
in memory. This data is typically written to the specified memory location by
a FSTENV or FNSTENV instruction.

The FPU operating environment consists of the FPU control word, status word,
tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through
8-12 in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, show the layout in memory of the loaded environment, depending on the operating
mode of the processor (protected or real) and the current operand-size attribute
(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.

The FLDENV instruction should be executed in the same operating mode as the
corresponding FSTENV/FNSTENV instruction.

If one or more unmasked exception flags are set in the new FPU status word,
a floating-point exception will be generated upon execution of the next floating-point
instruction (except for the no-wait floating-point instructions, see the section
titled “Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1). To avoid generating exceptions
when loading a new environment, clear all the exception flags in the FPU status
word that is being loaded.

If a page or limit fault occurs during the execution of this instruction, the
state of the x87 FPU registers as seen by the fault handler may be different
than the state being loaded from memory. In such situations, the fault handler
should ignore the status of the x87 FPU registers, handle the fault, and return.
The FLDENV instruction will then complete the loading of the x87 FPU registers
with no resulting context inconsistency.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FPUControlWord <- SRC[FPUControlWord];
FPUStatusWord <- SRC[FPUStatusWord];
FPUTagWord <- SRC[FPUTagWord];
FPUDataPointer <- SRC[FPUDataPointer];
FPUInstructionPointer <- SRC[FPUInstructionPointer];
FPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];

FPU Flags Affected:
The C0, C1, C2, C3 flags are loaded.


Floating-Point Exceptions:
None; however, if an unmasked exception is loaded in the status word, it is
generated upon execution of the next “waiting” floating-point instruction.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FMUL
description:
FMUL/FMULP/FIMUL - Multiply:
| Opcode | Instruction       | 64-Bit Mode| Compat/Leg Mode| Description                              
| D8 /1  | FMUL m32fp        | Valid      | Valid          | Multiply ST(0) by m32fp and store result 
|        |                   |            |                | in ST(0).                                
| DC /1  | FMUL m64fp        | Valid      | Valid          | Multiply ST(0) by m64fp and store result 
|        |                   |            |                | in ST(0).                                
| D8 C8+i| FMUL ST(0), ST(i) | Valid      | Valid          | Multiply ST(0) by ST(i) and store result 
|        |                   |            |                | in ST(0).                                
| DC C8+i| FMUL ST(i), ST(0) | Valid      | Valid          | Multiply ST(i) by ST(0) and store result 
|        |                   |            |                | in ST(i).                                
| DE C8+i| FMULP ST(i), ST(0)| Valid      | Valid          | Multiply ST(i) by ST(0), store result    
|        |                   |            |                | in ST(i), and pop the register stack.    
| DE C9  | FMULP             | Valid      | Valid          | Multiply ST(1) by ST(0), store result    
|        |                   |            |                | in ST(1), and pop the register stack.    
| DA /1  | FIMUL m32int      | Valid      | Valid          | Multiply ST(0) by m32int and store result
|        |                   |            |                | in ST(0).                                
| DE /1  | FIMUL m16int      | Valid      | Valid          | Multiply ST(0) by m16int and store result
|        |                   |            |                | in ST(0).                                

Description:
Multiplies the destination and source operands and stores the product in the
destination location. The destination operand is always an FPU data register;
the source operand can be an FPU data register or a memory location. Source
operands in memory can be in single-precision or double-precision floating-point
format or in word or doubleword integer format.

The no-operand version of the instruction multiplies the contents of the ST(1)
register by the contents of the ST(0) register and stores the product in the
ST(1) register. The one-operand version multiplies the contents of the ST(0)
register by the contents of a memory location (either a floating point or an
integer value) and stores the product in the ST(0) register. The two-operand
version, multiplies the contents of the ST(0) register by the contents of the
ST(i) register, or vice versa, with the result being stored in the register
specified with the first operand (the destination operand).

The FMULP instructions perform the additional operation of popping the FPU register
stack after storing the product. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. The
no-operand version of the floating-point multiply instructions always results
in the register stack being popped. In some assemblers, the mnemonic for this
instruction is FMUL rather than FMULP.

The FIMUL instructions convert an integer source operand to double extendedprecision
floating-point format before performing the multiplication.

The sign of the result is always the exclusive-OR of the source signs, even
if one or more of the values being multiplied is 0 or ∞. When the source operand
is an integer 0, it is treated as a +0.

The following table shows the results obtained when multiplying various classes
of numbers, assuming that neither overflow nor underflow occurs.


Table 3-39. FMUL/FMULP/FIMUL Results:
DEST

| − ∞+ ∞| − F + ∞    | − 0     | + 0     | + F − ∞    | + ∞− ∞| NaN NaN    
| + ∞   | + F        | +0      | −0      | − F        | − ∞   | NaN        
| + ∞   | + F + 0 − 0| +0 +0 −0| −0 −0 +0| − F − 0 + 0| − ∞   | NaN NaN NaN
| −∞    | − F        | −0      | +0      | + F        | +∞    | NaN        
| −∞−∞  | − F − ∞    | −0      | +0      | + F + ∞    | +∞+∞  | NaN NaN    
| NaN   | NaN        | NaN     | NaN     | NaN        | NaN   | NaN        
Notes: F Means finite floating-point value.

| I * Indicates invalid-arithmetic-operand| Means Integer.
| (#IA) exception.                        |               
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF Instruction = FIMUL
  THEN
     DEST <- DEST * ConvertToDoubleExtendedPrecisionFP(SRC);
  ELSE (* Source operand is floating-point value *)
     DEST <- DEST * SRC;
FI;
IF Instruction = FMULP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Operand is an SNaN value or unsupported
|    | format. One operand is ±0 and the other
|    | is ±∞.                                 
| #D | Source operand is a denormal value.    
| #U | Result is too small for destination    
|    | format.                                
| #O | Result is too large for destination    
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FNOP
description:
FNOP - No Operation:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description               
| D9 D0 | FNOP       | Valid      | Valid          | No operation is performed.

Description:
Performs no FPU operation. This instruction takes up space in the instruction
stream but does not affect the FPU or machine context, except the EIP register.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


FPU Flags Affected:
C0, C1, C2, C3 undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FPATAN
description:
FPATAN - Partial Arctangent:
| Opcode*                              | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                           
| D9 F3 NOTES: * See IA-32 Architecture| FPATAN     | Valid      | Valid          | Replace ST(1) with arctan(ST(1)/ST(0))
| Compatibility section below.         |            |            |                | and pop the register stack.           

Description:
Computes the arctangent of the source operand in register ST(1) divided by the
source operand in register ST(0), stores the result in ST(1), and pops the FPU
register stack. The result in register ST(0) has the same sign as the source
operand ST(1) and a magnitude less than +π.

The FPATAN instruction returns the angle between the X axis and the line from
the origin to the point (X,Y), where Y (the ordinate) is ST(1) and X (the abscissa)
is ST(0). The angle depends on the sign of X and Y independently, not just on
the sign of the ratio Y/X. This is because a point (−X,Y) is in the second quadrant,
resulting in an angle between π/2 and π, while a point (X,−Y) is in the fourth
quadrant, resulting in an angle between 0 and −π/2. A point (−X,−Y) is in the
third quadrant, giving an angle between −π/2 and −π.

The following table shows the results obtained when computing the arctangent
of various classes of numbers, assuming that underflow does not occur.


Table 3-40. FPATAN Results:
ST(0)

| − ∞    | − F       | − 0  | + 0  | + F       | + ∞   | NaN
| − 3π/4*| − π/2     | − π/2| − π/2| − π/2     | − π/4*| NaN
| -p     | −π to −π/2| −π/2 | −π/2 | −π/2 to −0| - 0   | NaN
| -p     | -p        | -p*  | − 0* | − 0       | − 0   | NaN
| +p     | + p       | + π* | + 0* | + 0       | + 0   | NaN
| +p     | +π to +π/2| + π/2| +π/2 | +π/2 to +0| + 0   | NaN
| +3π/4* | +π/2      | +π/2 | +π/2 | + π/2     | + π/4*| NaN
| NaN    | NaN       | NaN  | NaN  | NaN       | NaN   | NaN
Notes: F Means finite floating-point value. * Table 8-10 in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, specifies that the
ratios 0/0 and ∞/∞generate the floating-point invalid arithmetic-operation exception
and, if this exception is masked, the floating-point QNaN indefinite value is
returned. With the FPATAN instruction, the 0/0 or ∞/∞ value is actually not
calculated using division. Instead, the arctangent of the two variables is derived
from a standard mathematical formulation that is generalized to allow complex
numbers as arguments. In this complex variable formulation, arctangent(0,0)
etc. has well defined values. These values are needed to develop a library to
compute transcendental functions with complex arguments, based on the FPU functions
that only allow floating-point values as arguments.

There is no restriction on the range of source operands that FPATAN can accept.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
The source operands for this instruction are restricted for the 80287 math coprocessor
to the following range:

0 ≤ |ST(1)| < |ST(0)| < +∞

Operation:

ST(1) <- arctan(ST(1) / ST(0));
PopRegisterStack;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Source operand is an SNaN value or unsupported
|    | format.                                       
| #D | Source operand is a denormal value.           
| #U | Result is too small for destination           
|    | format.                                       
| #P | Value cannot be represented exactly           
|    | in destination format.                        

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FPREM
description:
FPREM - Partial Remainder:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                              
| D9 F8 | FPREM      | Valid      | Valid          | Replace ST(0) with the remainder obtained
|       |            |            |                | from dividing ST(0) by ST(1).            

Description:
Computes the remainder obtained from dividing the value in the ST(0) register
(the dividend) by the value in the ST(1) register (the divisor or modulus),
and stores the result in ST(0). The remainder represents the following value:

Remainder ← ST(0) − (Q * ST(1))

Here, Q is an integer value that is obtained by truncating the floating-point
number quotient of [ST(0) / ST(1)]toward zero. The sign of the remainder is
the same as the sign of the dividend. The magnitude of the remainder is less
than that of the modulus, unless a partial remainder was computed (as described
below).

This instruction produces an exact result; the inexact-result exception does
not occur and the rounding control has no effect. The following table shows
the results obtained when computing the remainder of various classes of numbers,
assuming that underflow does not occur.


Table 3-41. FPREM Results:
ST(1)

| -∞-0 +0| -F -F or -0 -0 +0 +F or +0 NaN| -0 ****NaN| +0 ****NaN| +F -F or -0 -0 +0 +F or +0 NaN| +∞ST(0) -0 +0 ST(0) NaN| NaN NaN NaN NaN NaN NaN NaN NaN
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception. ** Indicates floating-point zero-divide (#Z) exception.

When the result is 0, its sign is the same as that of the dividend. When the
modulus is ∞, the result is equal to the value in ST(0).

The FPREM instruction does not compute the remainder specified in IEEE Std 754.
The IEEE specified remainder can be computed with the FPREM1 instruction. The
FPREM instruction is provided for compatibility with the Intel 8087 and Intel287
math coprocessors.

The FPREM instruction gets its name “partial remainder” because of the way it
computes the remainder. This instruction arrives at a remainder through iterative
subtraction. It can, however, reduce the exponent of ST(0) by no more than 63
in one execution of the instruction. If the instruction succeeds in producing
a remainder that is less than the modulus, the operation is complete and the
C2 flag in the FPU status word is cleared. Otherwise, C2 is set, and the result
in ST(0) is called the partial remainder. The exponent of the partial remainder
will be less than the exponent of the original dividend by at least 32. Software
can re-execute the instruction (using the partial remainder in ST(0) as the
dividend) until C2 is cleared. (Note that while executing such a remainder-computation
loop, a higher-priority interrupting routine that needs the FPU can force a
context switch in-between the instructions in the loop.)

An important use of the FPREM instruction is to reduce the arguments of periodic
functions. When reduction is complete, the instruction stores the three least-significant
bits of the quotient in the C3, C1, and C0 flags of the FPU

status word. This information is important in argument reduction for the tangent
function (using a modulus of π/4), because it locates the original angle in
the correct one of eight sectors of the unit circle.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

D <- exponent(ST(0)) - exponent(ST(1));
IF D < 64
  THEN
     Q <- Integer(TruncateTowardZero(ST(0) / ST(1)));
     ST(0) <- ST(0) - (ST(1) * Q);
     C2 <- 0;
     C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)
  ELSE
     C2 <- 1;
     N <- An implementation-dependent number between 32 and 63;
     QQ <- Integer(TruncateTowardZero((ST(0)
     ST(0) <- ST(0) - (ST(1) * QQ * 2(D − N));
FI;

FPU Flags Affected:
| C0| Set to bit 2 (Q2) of the quotient.   
| C1| Set to 0 if stack underflow occurred;
|   | otherwise, set to least significant  
|   | bit of quotient (Q0).                
| C2| Set to 0 if reduction complete; set  
|   | to 1 if incomplete.                  
| C3| Set to bit 1 (Q1) of the quotient.   

Floating-Point Exceptions:
| #IS| Stack underflow occurred.               
| #IA| Source operand is an SNaN value, modulus
|    | is 0, dividend is ∞, or unsupported     
|    | format.                                 
| #D | Source operand is a denormal value.     
| #U | Result is too small for destination     
|    | format.                                 

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FPREM1
description:
FPREM1 - Partial Remainder:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                           
| D9 F5 | FPREM1     | Valid      | Valid          | Replace ST(0) with the IEEE remainder 
|       |            |            |                | obtained from dividing ST(0) by ST(1).

Description:
Computes the IEEE remainder obtained from dividing the value in the ST(0) register
(the dividend) by the value in the ST(1) register (the divisor or modulus),
and stores the result in ST(0). The remainder represents the following value:

Remainder ← ST(0) − (Q * ST(1))

Here, Q is an integer value that is obtained by rounding the floating-point
number quotient of [ST(0) / ST(1)]toward the nearest integer value. The magnitude
of the remainder is less than or equal to half the magnitude of the modulus,
unless a partial remainder was computed (as described below).

This instruction produces an exact result; the precision (inexact) exception
does not occur and the rounding control has no effect. The following table shows
the results obtained when computing the remainder of various classes of numbers,
assuming that underflow does not occur.


Table 3-42. FPREM1 Results:
ST(1)

| − ∞−0 +0| − F ±F or −0 − 0 + 0 ± F or + 0| − 0 ****| + 0 ****| + F ± F or − 0 − 0 + 0 ± F or + 0| + ∞ST(0) -0 +0 ST(0)| NaN NaN NaN NaN NaN NaN NaN
| NaN     | NaN                            | NaN     | NaN     | NaN                              | NaN                 | NaN                        
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception. ** Indicates floating-point zero-divide (#Z) exception.

When the result is 0, its sign is the same as that of the dividend. When the
modulus is ∞, the result is equal to the value in ST(0).

The FPREM1 instruction computes the remainder specified in IEEE Standard 754.
This instruction operates differently from the FPREM instruction in the way
that it rounds the quotient of ST(0) divided by ST(1) to an integer (see the
“Operation” section below).

Like the FPREM instruction, FPREM1 computes the remainder through iterative
subtraction, but can reduce the exponent of ST(0) by no more than 63 in one
execution of the instruction. If the instruction succeeds in producing a remainder
that is less than one half the modulus, the operation is complete and the C2
flag in the FPU status word is cleared. Otherwise, C2 is set, and the result
in ST(0) is called the partial remainder. The exponent of the partial remainder
will be less than the exponent of the original dividend by at least 32. Software
can re-execute the instruction (using the partial remainder in ST(0) as the
dividend) until C2 is cleared. (Note that while executing such a remainder-computation
loop, a higher-priority interrupting routine that needs the FPU can force a
context switch in-between the instructions in the loop.)

An important use of the FPREM1 instruction is to reduce the arguments of periodic
functions. When reduction is complete, the instruction stores the three least-significant
bits of the quotient in the C3, C1, and C0 flags of the FPU

status word. This information is important in argument reduction for the tangent
function (using a modulus of π/4), because it locates the original angle in
the correct one of eight sectors of the unit circle.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

D <- exponent(ST(0)) - exponent(ST(1));
IF D < 64
  THEN
     Q <- Integer(RoundTowardNearestInteger(ST(0) / ST(1)));
     ST(0) <- ST(0) - (ST(1) * Q);
     C2 <- 0;
     C0, C3, C1 <- LeastSignificantBits(Q); (* Q2, Q1, Q0 *)
  ELSE
     C2 <- 1;
     N <- An implementation-dependent number between 32 and 63;
     QQ <- Integer(TruncateTowardZero((ST(0)
     ST(0) <- ST(0) - (ST(1) * QQ * 2(D − N));
FI;

FPU Flags Affected:
| C0| Set to bit 2 (Q2) of the quotient.   
| C1| Set to 0 if stack underflow occurred;
|   | otherwise, set to least significant  
|   | bit of quotient (Q0).                
| C2| Set to 0 if reduction complete; set  
|   | to 1 if incomplete.                  
| C3| Set to bit 1 (Q1) of the quotient.   

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                    
| #IA| Source operand is an SNaN value, modulus     
|    | (divisor) is 0, dividend is ∞, or unsupported
|    | format.                                      
| #D | Source operand is a denormal value.          
| #U | Result is too small for destination          
|    | format.                                      

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FPTAN
description:
FPTAN - Partial Tangent:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                            
| D9 F2 | FPTAN      | Valid      | Valid          | Replace ST(0) with its tangent and push
|       |            |            |                | 1 onto the FPU stack.                  

Description:
Computes the tangent of the source operand in register ST(0), stores the result
in ST(0), and pushes a 1.0 onto the FPU register stack. The source operand must
be given in radians and must be less than ±263. The following table shows the
unmasked results obtained when computing the partial tangent of various classes
of numbers, assuming that underflow does not occur.


Table 3-43. FPTAN Results:
| ST(0) SRC − ∞| ST(0) DEST
| − F          | − F to + F
| − 0          | -0        
| + 0          | +0        
| + F + ∞      | − F to + F
| NaN          | NaN       
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception.

If the source operand is outside the acceptable range, the C2 flag in the FPU
status word is set, and the value in register ST(0) remains unchanged. The instruction
does not raise an exception when the source operand is out of range. It is up
to the program to check the C2 flag for out-of-range conditions. Source values
outside the range −263 to +263 can be reduced to the range of the instruction
by subtracting an appropriate integer multiple of 2π or by using the FPREM instruction
with a divisor of 2π. See the section titled “Pi” in Chapter 8 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion
of the proper value to use for π in performing such reductions.

The value 1.0 is pushed onto the register stack after the tangent has been computed
to maintain compatibility with the Intel 8087 and Intel287 math coprocessors.
This operation also simplifies the calculation of other trigonometric functions.
For instance, the cotangent (which is the reciprocal of the tangent) can be
computed by executing a FDIVR instruction after the FPTAN instruction.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF ST(0) < 263
  THEN
     C2 <- 0;
     ST(0) <- tan(ST(0));
     TOP <- TOP − 1;
     ST(0) <- 1.0;
  ELSE (* Source operand is out-of-range *)
     C2 <- 1;
FI;

FPU Flags Affected:
| C1    | Set to 0 if stack underflow occurred;   
|       | set to 1 if stack overflow occurred.    
|       | Set if result was rounded up; cleared   
|       | otherwise.                              
| C2    | Set to 1 if outside range (−263 < source
|       | operand < +263); otherwise, set to 0.   
| C0, C3| Undefined.                              

Floating-Point Exceptions:
| #IS| Stack underflow or overflow occurred.
| #IA| Source operand is an SNaN value, ∞,  
|    | or unsupported format.               
| #D | Source operand is a denormal value.  
| #U | Result is too small for destination  
|    | format.                              
| #P | Value cannot be represented exactly  
|    | in destination format.               

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FRNDINT
description:
FRNDINT - Round to Integer:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description               
| D9 FC | FRNDINT    | Valid      | Valid          | Round ST(0) to an integer.

Description:
Rounds the source value in the ST(0) register to the nearest integral value,
depending on the current rounding mode (setting of the RC field of the FPU control
word), and stores the result in ST(0).

If the source value is ∞, the value is not changed. If the source value is not
an integral value, the floating-point inexact-result exception (#P) is generated.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(0) <- RoundToIntegralValue(ST(0));

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Source operand is an SNaN value or unsupported
|    | format.                                       
| #D | Source operand is a denormal value.           
| #P | Source operand is not an integral value.      

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FRSTOR
description:
FRSTOR - Restore x87 FPU State:
| Opcode| Instruction       | 64-Bit Mode| Compat/Leg Mode| Description                             
| DD /4 | FRSTOR m94/108byte| Valid      | Valid          | Load FPU state from m94byte or m108byte.

Description:
Loads the FPU state (operating environment and register stack) from the memory
area specified with the source operand. This state data is typically written
to the specified memory location by a previous FSAVE/FNSAVE instruction.

The FPU operating environment consists of the FPU control word, status word,
tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through
8-12 in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, show the layout in memory of the stored environment, depending on the operating
mode of the processor (protected or real) and the current operand-size attribute
(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The
contents of the FPU register stack are stored in the 80 bytes immediately following
the operating environment image.

The FRSTOR instruction should be executed in the same operating mode as the
corresponding FSAVE/FNSAVE instruction.

If one or more unmasked exception bits are set in the new FPU status word, a
floating-point exception will be generated. To avoid raising exceptions when
loading a new operating environment, clear all the exception flags in the FPU
status word that is being loaded.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FPUControlWord <- SRC[FPUControlWord];
FPUStatusWord <- SRC[FPUStatusWord];
FPUTagWord <- SRC[FPUTagWord];
FPUDataPointer <- SRC[FPUDataPointer];
FPUInstructionPointer <- SRC[FPUInstructionPointer];
FPULastInstructionOpcode <- SRC[FPULastInstructionOpcode];
ST(0) <- SRC[ST(0)];
ST(1) <- SRC[ST(1)];
ST(2) <- SRC[ST(2)];
ST(3) <- SRC[ST(3)];
ST(4) <- SRC[ST(4)];
ST(5) <- SRC[ST(5)];
ST(6) <- SRC[ST(6)];
ST(7) <- SRC[ST(7)];

FPU Flags Affected:
The C0, C1, C2, C3 flags are loaded.


Floating-Point Exceptions:
None; however, this operation might unmask an existing exception that has been
detected but not generated, because it was masked. Here, the exception is generated
at the completion of the instruction.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSAVE
description:
FSAVE/FNSAVE - Store x87 FPU State:
| Opcode        | Instruction                          | 64-Bit Mode| Compat/Leg Mode| Description                                  
| 9B DD /6 DD /6| FSAVE m94/108byte FNSAVE* m94/108byte| Valid Valid| Valid Valid    | Store FPU state to m94byte or m108byte       
|               |                                      |            |                | after checking for pending unmasked          
|               |                                      |            |                | floating-point exceptions. Then re-initialize
|               |                                      |            |                | the FPU. Store FPU environment to m94byte    
|               |                                      |            |                | or m108byte without checking for pending     
|               |                                      |            |                | unmasked floatingpoint exceptions. Then      
|               |                                      |            |                | re-initialize the FPU.                       
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Stores the current FPU state (operating environment and register stack) at the
specified destination in memory, and then re-initializes the FPU. The FSAVE
instruction checks for and handles pending unmasked floating-point exceptions
before storing the FPU state; the FNSAVE instruction does not.

The FPU operating environment consists of the FPU control word, status word,
tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through
8-12 in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, show the layout in memory of the stored environment, depending on the operating
mode of the processor (protected or real) and the current operand-size attribute
(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used. The
contents of the FPU register stack are stored in the 80 bytes immediately follow
the operating environment image.

The saved image reflects the state of the FPU after all floating-point instructions
preceding the FSAVE/FNSAVE instruction in the instruction stream have been executed.

After the FPU state has been saved, the FPU is reset to the same default values
it is set to with the FINIT/FNINIT instructions (see “FINIT/FNINIT - Initialize
Floating-Point Unit” in this chapter).

The FSAVE/FNSAVE instructions are typically used when the operating system needs
to perform a context switch, an exception handler needs to use the FPU, or an
application program needs to pass a “clean” FPU to a procedure.

The assembler issues two instructions for the FSAVE instruction (an FWAIT instruction
followed by an FNSAVE instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
For Intel math coprocessors and FPUs prior to the Intel Pentium processor, an
FWAIT instruction should be executed before attempting to read from the memory
image stored with a prior FSAVE/FNSAVE instruction. This FWAIT instruction helps
ensure that the storage operation has been completed.

When operating a Pentium or Intel486 processor in MS-DOS compatibility mode,
it is possible (under unusual circumstances) for an FNSAVE instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel®64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNSAVE instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

Operation:

(* Save FPU State and Registers *)
DEST[FPUControlWord] <- FPUControlWord;
DEST[FPUStatusWord] <- FPUStatusWord;
DEST[FPUTagWord] <- FPUTagWord;
DEST[FPUDataPointer] <- FPUDataPointer;
DEST[FPUInstructionPointer] <- FPUInstructionPointer;
DEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;
DEST[ST(0)] <- ST(0);
DEST[ST(1)] <- ST(1);
DEST[ST(2)] <- ST(2);
DEST[ST(3)] <- ST(3);
DEST[ST(4)]<- ST(4);
DEST[ST(5)] <- ST(5);
DEST[ST(6)] <- ST(6);
DEST[ST(7)] <- ST(7);
(* Initialize FPU *)
FPUControlWord <- 037FH;
FPUStatusWord <- 0;
FPUTagWord <- FFFFH;
FPUDataPointer <- 0;
FPUInstructionPointer <- 0;
FPULastInstructionOpcode <- 0;

FPU Flags Affected:
The C0, C1, C2, and C3 flags are saved and then cleared.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #GP(0)         | If destination is located in a non-writable
|                | segment. If a memory operand effective     
|                | address is outside the CS, DS, ES, FS,     
|                | or GS segment limit. If the DS, ES,        
|                | FS, or GS register is used to access       
|                | memory and it contains a NULL segment      
|                | selector.                                  
| #SS(0)         | If a memory operand effective address      
|                | is outside the SS segment limit.           
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: FSCALE
description:
FSCALE - Scale:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description          
| D9 FD | FSCALE     | Valid      | Valid          | Scale ST(0) by ST(1).

Description:
Truncates the value in the source operand (toward 0) to an integral value and
adds that value to the exponent of the destination operand. The destination
and source operands are floating-point values located in registers ST(0) and
ST(1), respectively. This instruction provides rapid multiplication or division
by integral powers of 2. The following table shows the results obtained when
scaling various classes of numbers, assuming that neither overflow nor underflow
occurs.


Table 3-44. FSCALE Results:
ST(1)

| − ∞| − F| − 0| + 0| + F| + ∞| NaN
| NaN| − ∞| − ∞| − ∞| − ∞| − ∞| NaN
| − 0| − F| − F| − F| − F| − ∞| NaN
| − 0| − 0| − 0| − 0| − 0| NaN| NaN
| + 0| + 0| + 0| + 0| + 0| NaN| NaN
| + 0| + F| + F| + F| + F| + ∞| NaN
| NaN| + ∞| + ∞| + ∞| + ∞| + ∞| NaN
| NaN| NaN| NaN| NaN| NaN| NaN| NaN
Notes: F Means finite floating-point value.

In most cases, only the exponent is changed and the mantissa (significand) remains
unchanged. However, when the value being scaled in ST(0) is a denormal value,
the mantissa is also changed and the result may turn out to be a normalized
number. Similarly, if overflow or underflow results from a scale operation,
the resulting mantissa will differ from the source's mantissa.

The FSCALE instruction can also be used to reverse the action of the FXTRACT
instruction, as shown in the following example: FXTRACT; FSCALE; FSTP ST(1);

In this example, the FXTRACT instruction extracts the significand and exponent
from the value in ST(0) and stores them in ST(0) and ST(1) respectively. The
FSCALE then scales the significand in ST(0) by the exponent in ST(1), recreating
the original value before the FXTRACT operation was performed. The FSTP ST(1)
instruction overwrites the exponent (extracted by the FXTRACT instruction) with
the recreated value, which returns the stack to its original state with only
one register [ST(0)] occupied.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(0) <- ST(0) * 2RoundTowardZero(ST(1));

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Source operand is an SNaN value or unsupported
|    | format.                                       
| #D | Source operand is a denormal value.           
| #U | Result is too small for destination           
|    | format.                                       
| #O | Result is too large for destination           
|    | format.                                       
| #P | Value cannot be represented exactly           
|    | in destination format.                        

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FSIN
description:
FSIN - Sine:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                 
| D9 FE | FSIN       | Valid      | Valid          | Replace ST(0) with its sine.

Description:
Computes the sine of the source operand in register ST(0) and stores the result
in ST(0). The source operand must be given in radians and must be within the
range −263 to +263. The following table shows the results obtained when taking
the sine of various classes of numbers, assuming that underflow does not occur.


Table 3-45. FSIN Results:
| SRC (ST(0)) − ∞| DEST (ST(0))
| − F            | − 1 to + 1  
| − 0            | −0          
| + 0            | +0          
| + F + ∞        | − 1 to +1   
| NaN            | NaN         
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception.

If the source operand is outside the acceptable range, the C2 flag in the FPU
status word is set, and the value in register ST(0) remains unchanged. The instruction
does not raise an exception when the source operand is out of range. It is up
to the program to check the C2 flag for out-of-range conditions. Source values
outside the range −263 to +263 can be reduced to the range of the instruction
by subtracting an appropriate integer multiple of 2π or by using the FPREM instruction
with a divisor of 2π. See the section titled “Pi” in Chapter 8 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion
of the proper value to use for π in performing such reductions.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF -263 < ST(0) < 263
  THEN
     C2 <- 0;
     ST(0) <- sin(ST(0));
  ELSE (* Source operand out of range *)
     C2 <- 1;
FI;

FPU Flags Affected:
| C1    | Set to 0 if stack underflow occurred.   
|       | Set if result was rounded up; cleared   
|       | otherwise.                              
| C2    | Set to 1 if outside range (−263 < source
|       | operand < +263); otherwise, set to 0.   
| C0, C3| Undefined.                              

Floating-Point Exceptions:
| #IS| Stack underflow occurred.          
| #IA| Source operand is an SNaN value, ∞,
|    | or unsupported format.             
| #D | Source operand is a denormal value.
| #P | Value cannot be represented exactly
|    | in destination format.             

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FSINCOS
description:
FSINCOS - Sine and Cosine:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                          
| D9 FB | FSINCOS    | Valid      | Valid          | Compute the sine and cosine of ST(0);
|       |            |            |                | replace ST(0) with the sine, and push
|       |            |            |                | the cosine onto the register stack.  

Description:
Computes both the sine and the cosine of the source operand in register ST(0),
stores the sine in ST(0), and pushes the cosine onto the top of the FPU register
stack. (This instruction is faster than executing the FSIN and FCOS instructions
in succession.) The source operand must be given in radians and must be within
the range −263 to +263. The following table shows the results obtained when
taking the sine and cosine of various classes of numbers, assuming that underflow
does not occur.


Table 3-46. FSINCOS Results:
| SRC − ∞| DEST ST(0) Sine
| − F    | − 1 to + 1     
| − 0    | − 0            
| + 0    | + 0            
| + F + ∞| − 1 to + 1     
| NaN    | NaN            
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception.

If the source operand is outside the acceptable range, the C2 flag in the FPU
status word is set, and the value in register ST(0) remains unchanged. The instruction
does not raise an exception when the source operand is out of range. It is up
to the program to check the C2 flag for out-of-range conditions. Source values
outside the range −263 to +263 can be reduced to the range of the instruction
by subtracting an appropriate integer multiple of 2π or by using the FPREM instruction
with a divisor of 2π. See the section titled “Pi” in Chapter 8 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion
of the proper value to use for π in performing such reductions.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF ST(0) < 263
  THEN
     C2 <- 0;
     TEMP <- cosine(ST(0));
     ST(0) <- sine(ST(0));
     TOP <- TOP − 1;
     ST(0) <- TEMP;
  ELSE (* Source operand out of range *)
     C2 <- 1;
FI;

FPU Flags Affected:
| C1    | Set to 0 if stack underflow occurred;       
|       | set to 1 of stack overflow occurs. Set      
|       | if result was rounded up; cleared otherwise.
| C2    | Set to 1 if outside range (−263 < source    
|       | operand < +263); otherwise, set to 0.       
| C0, C3| Undefined.                                  

Floating-Point Exceptions:
| #IS| Stack underflow or overflow occurred.
| #IA| Source operand is an SNaN value, ∞,  
|    | or unsupported format.               
| #D | Source operand is a denormal value.  
| #U | Result is too small for destination  
|    | format.                              
| #P | Value cannot be represented exactly  
|    | in destination format.               

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FSQRT
description:
FSQRT - Square Root:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                             
| D9 FA | FSQRT      | Valid      | Valid          | Computes square root of ST(0) and stores
|       |            |            |                | the result in ST(0).                    

Description:
Computes the square root of the source value in the ST(0) register and stores
the result in ST(0).

The following table shows the results obtained when taking the square root of
various classes of numbers, assuming that neither overflow nor underflow occurs.


Table 3-47. FSQRT Results:
| SRC (ST(0)) − ∞− F| DEST (ST(0))
| − 0               | −0          
| + 0               | +0          
| + F               | +F          
| + ∞               | +∞          
| NaN               | NaN         
Notes: F Means finite floating-point value. * Indicates floating-point invalid-arithmetic-operand
(#IA) exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(0) <- SquareRoot(ST(0));

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Source operand is an SNaN value or unsupported
|    | format. Source operand is a negative          
|    | value (except for −0).                        
| #D | Source operand is a denormal value.           
| #P | Value cannot be represented exactly           
|    | in destination format.                        

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FST
description:
FST/FSTP - Store Floating Point Value:
| Opcode | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                         
| D9 /2  | FST m32fp  | Valid      | Valid          | Copy ST(0) to m32fp.                
| DD /2  | FST m64fp  | Valid      | Valid          | Copy ST(0) to m64fp.                
| DD D0+i| FST ST(i)  | Valid      | Valid          | Copy ST(0) to ST(i).                
| D9 /3  | FSTP m32fp | Valid      | Valid          | Copy ST(0) to m32fp and pop register
|        |            |            |                | stack.                              
| DD /3  | FSTP m64fp | Valid      | Valid          | Copy ST(0) to m64fp and pop register
|        |            |            |                | stack.                              
| DB /7  | FSTP m80fp | Valid      | Valid          | Copy ST(0) to m80fp and pop register
|        |            |            |                | stack.                              
| DD D8+i| FSTP ST(i) | Valid      | Valid          | Copy ST(0) to ST(i) and pop register
|        |            |            |                | stack.                              

Description:
The FST instruction copies the value in the ST(0) register to the destination
operand, which can be a memory location or another register in the FPU register
stack. When storing the value in memory, the value is converted to single-precision
or double-precision floating-point format.

The FSTP instruction performs the same operation as the FST instruction and
then pops the register stack. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. The
FSTP instruction can also store values in memory in double extended-precision
floating-point format.

If the destination operand is a memory location, the operand specifies the address
where the first byte of the destination value is to be stored. If the destination
operand is a register, the operand specifies a register in the register stack
relative to the top of the stack.

If the destination size is single-precision or double-precision, the significand
of the value being stored is rounded to the width of the destination (according
to the rounding mode specified by the RC field of the FPU control word), and
the exponent is converted to the width and bias of the destination format. If
the value being stored is too large for the destination format, a numeric overflow
exception (#O) is generated and, if the exception is unmasked, no value is stored
in the destination operand. If the value being stored is a denormal value, the
denormal exception (#D) is not generated. This condition is simply signaled
as a numeric underflow exception (#U) condition.

If the value being stored is ±0, ±∞, or a NaN, the least-significant bits of
the significand and the exponent are truncated to fit the destination format.
This operation preserves the value's identity as a 0, ∞, or NaN.

If the destination operand is a non-empty register, the invalid-operation exception
is not generated.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DEST <- ST(0);
IF Instruction = FSTP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.     
|           | Indicates rounding direction of if the    
|           | floating-point inexact exception (#P)     
|           | is generated: 0 ←not roundup; 1 ← roundup.
| C0, C2, C3| Undefined.                                

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                         
| #IA| If destination result is an SNaN value            
|    | or unsupported format, except when the            
|    | destination format is in double extended-precision
|    | floating-point format.                            
| #U | Result is too small for the destination           
|    | format.                                           
| #O | Result is too large for the destination           
|    | format.                                           
| #P | Value cannot be represented exactly               
|    | in destination format.                            

Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.            
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSTCW
description:
FSTCW/FNSTCW - Store x87 FPU Control Word:
| Opcode  | Instruction   | 64-Bit Mode| Compat/Leg Mode| Description                                 
| 9B D9 /7| FSTCW m2byte  | Valid      | Valid          | Store FPU control word to m2byte after      
|         |               |            |                | checking for pending unmasked floating-point
|         |               |            |                | exceptions.                                 
| D9 /7   | FNSTCW* m2byte| Valid      | Valid          | Store FPU control word to m2byte without    
|         |               |            |                | checking for pending unmasked floating-point
|         |               |            |                | exceptions.                                 
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Stores the current value of the FPU control word at the specified destination
in memory. The FSTCW instruction checks for and handles pending unmasked floating-point
exceptions before storing the control word; the FNSTCW instruction does not.

The assembler issues two instructions for the FSTCW instruction (an FWAIT instruction
followed by an FNSTCW instruction), and the processor executes each of these
instructions in separately. If an exception is generated for either of these
instructions, the save EIP points to the instruction that caused the exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode,
it is possible (under unusual circumstances) for an FNSTCW instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNSTCW instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

Operation:

DEST <- FPUControlWord;

FPU Flags Affected:
The C0, C1, C2, and C3 flags are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.            
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSTENV
description:
FSTENV/FNSTENV - Store x87 FPU Environment:
| Opcode        | Instruction                          | 64-Bit Mode| Compat/Leg Mode| Description                                
| 9B D9 /6 D9 /6| FSTENV m14/28byte FNSTENV* m14/28byte| Valid Valid| Valid Valid    | Store FPU environment to m14byte or        
|               |                                      |            |                | m28byte after checking for pending unmasked
|               |                                      |            |                | floating-point exceptions. Then mask       
|               |                                      |            |                | all floating-point exceptions. Store       
|               |                                      |            |                | FPU environment to m14byte or m28byte      
|               |                                      |            |                | without checking for pending unmasked      
|               |                                      |            |                | floatingpoint exceptions. Then mask        
|               |                                      |            |                | all floatingpoint exceptions.              
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Saves the current FPU operating environment at the memory location specified
with the destination operand, and then masks all floating-point exceptions.
The FPU operating environment consists of the FPU control word, status word,
tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through
8-12 in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, show the layout in memory of the stored environment, depending on the operating
mode of the processor (protected or real) and the current operand-size attribute
(16-bit or 32-bit). In virtual-8086 mode, the real mode layouts are used.

The FSTENV instruction checks for and handles any pending unmasked floating-point
exceptions before storing the FPU environment; the FNSTENV instruction does
not. The saved image reflects the state of the FPU after all floating-point
instructions preceding the FSTENV/FNSTENV instruction in the instruction stream
have been executed.

These instructions are often used by exception handlers because they provide
access to the FPU instruction and data pointers. The environment is typically
saved in the stack. Masking all exceptions after saving the environment prevents
floating-point exceptions from interrupting the exception handler.

The assembler issues two instructions for the FSTENV instruction (an FWAIT instruction
followed by an FNSTENV instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode,
it is possible (under unusual circumstances) for an FNSTENV instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNSTENV instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

Operation:

DEST[FPUControlWord] <- FPUControlWord;
DEST[FPUStatusWord] <- FPUStatusWord;
DEST[FPUTagWord] <- FPUTagWord;
DEST[FPUDataPointer] <- FPUDataPointer;
DEST[FPUInstructionPointer] <- FPUInstructionPointer;
DEST[FPULastInstructionOpcode] <- FPULastInstructionOpcode;

FPU Flags Affected:
The C0, C1, C2, and C3 are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.            
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSTSW
description:
FSTSW/FNSTSW - Store x87 FPU Status Word:
| Opcode              | Instruction                       | 64-Bit Mode      | Compat/Leg Mode  | Description                                 
| 9B DD /7            | FSTSW m2byte                      | Valid            | Valid            | Store FPU status word at m2byte after       
|                     |                                   |                  |                  | checking for pending unmasked floating-point
|                     |                                   |                  |                  | exceptions.                                 
| 9B DF E0 DD /7 DF E0| FSTSW AX FNSTSW* m2byte FNSTSW* AX| Valid Valid Valid| Valid Valid Valid| Store FPU status word in AX register        
|                     |                                   |                  |                  | after checking for pending unmasked         
|                     |                                   |                  |                  | floating-point exceptions. Store FPU        
|                     |                                   |                  |                  | status word at m2byte without checking      
|                     |                                   |                  |                  | for pending unmasked floating-point         
|                     |                                   |                  |                  | exceptions. Store FPU status word in        
|                     |                                   |                  |                  | AX register without checking for pending    
|                     |                                   |                  |                  | unmasked floating-point exceptions.         
Notes: * See IA-32 Architecture Compatibility section below.


Description:
Stores the current value of the x87 FPU status word in the destination location.
The destination operand can be either a two-byte memory location or the AX register.
The FSTSW instruction checks for and handles pending unmasked floating-point
exceptions before storing the status word; the FNSTSW instruction does not.

The FNSTSW AX form of the instruction is used primarily in conditional branching
(for instance, after an FPU comparison instruction or an FPREM, FPREM1, or FXAM
instruction), where the direction of the branch depends on the state of the
FPU condition code flags. (See the section titled “Branching and Conditional
Moves on FPU Condition Codes” in Chapter 8 of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.) This instruction can also be used to
invoke exception handlers (by examining the exception flags) in environments
that do not use interrupts. When the FNSTSW AX instruction is executed, the
AX register is updated before the processor executes any further instructions.
The status stored in the AX register is thus guaranteed to be from the completion
of the prior FPU instruction.

The assembler issues two instructions for the FSTSW instruction (an FWAIT instruction
followed by an FNSTSW instruction), and the processor executes each of these
instructions separately. If an exception is generated for either of these instructions,
the save EIP points to the instruction that caused the exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
When operating a Pentium or Intel486 processor in MS-DOS compatibility mode,
it is possible (under unusual circumstances) for an FNSTSW instruction to be
interrupted prior to being executed to handle a pending FPU exception. See the
section titled “No-Wait FPU Instructions Can Get FPU Interrupt in Window” in
Appendix D of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for a description of these circumstances. An FNSTSW instruction cannot
be interrupted in this way on a Pentium 4, Intel Xeon, or P6 family processor.

Operation:

DEST <- FPUStatusWord;

FPU Flags Affected:
The C0, C1, C2, and C3 are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.            
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSUB
description:
FSUB/FSUBP/FISUB - Subtract:
| Opcode | Instruction       | 64-Bit Mode| Compat/Leg Mode| Description                            
| D8 /4  | FSUB m32fp        | Valid      | Valid          | Subtract m32fp from ST(0) and store    
|        |                   |            |                | result in ST(0).                       
| DC /4  | FSUB m64fp        | Valid      | Valid          | Subtract m64fp from ST(0) and store    
|        |                   |            |                | result in ST(0).                       
| D8 E0+i| FSUB ST(0), ST(i) | Valid      | Valid          | Subtract ST(i) from ST(0) and store    
|        |                   |            |                | result in ST(0).                       
| DC E8+i| FSUB ST(i), ST(0) | Valid      | Valid          | Subtract ST(0) from ST(i) and store    
|        |                   |            |                | result in ST(i).                       
| DE E8+i| FSUBP ST(i), ST(0)| Valid      | Valid          | Subtract ST(0) from ST(i), store result
|        |                   |            |                | in ST(i), and pop register stack.      
| DE E9  | FSUBP             | Valid      | Valid          | Subtract ST(0) from ST(1), store result
|        |                   |            |                | in ST(1), and pop register stack.      
| DA /4  | FISUB m32int      | Valid      | Valid          | Subtract m32int from ST(0) and store   
|        |                   |            |                | result in ST(0).                       
| DE /4  | FISUB m16int      | Valid      | Valid          | Subtract m16int from ST(0) and store   
|        |                   |            |                | result in ST(0).                       

Description:
Subtracts the source operand from the destination operand and stores the difference
in the destination location. The destination operand is always an FPU data register;
the source operand can be a register or a memory location. Source operands in
memory can be in single-precision or double-precision floating-point format
or in word or doubleword integer format.

The no-operand version of the instruction subtracts the contents of the ST(0)
register from the ST(1) register and stores the result in ST(1). The one-operand
version subtracts the contents of a memory location (either a floatingpoint
or an integer value) from the contents of the ST(0) register and stores the
result in ST(0). The two-operand version, subtracts the contents of the ST(0)
register from the ST(i) register or vice versa.

The FSUBP instructions perform the additional operation of popping the FPU register
stack following the subtraction. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1. The
no-operand version of the floating-point subtract instructions always results
in the register stack being popped. In some assemblers, the mnemonic for this
instruction is FSUB rather than FSUBP.

The FISUB instructions convert an integer source operand to double extended-precision
floating-point format before performing the subtraction.

Table 3-48 shows the results obtained when subtracting various classes of numbers
from one another, assuming that neither overflow nor underflow occurs. Here,
the SRC value is subtracted from the DEST value (DEST − SRC =result).

When the difference between two operands of like sign is 0, the result is +0,
except for the round toward −∞ mode, in which case the result is −0. This instruction
also guarantees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the source
operand is an integer 0, it is treated as a +0.

When one operand is ∞, the result is ∞ of the expected sign. If both operands
are ∞ of the same sign, an invalidoperation exception is generated.


Table 3-48. FSUB/FSUBP/FISUB Results:
SRC

| − ∞ | − F or − I − ∞| − 0 − ∞ | + 0 − ∞ | + F or + I − ∞| + ∞− ∞| NaN NaN
| +∞  | ±F or ±0      | DEST    | DEST    | − F           | − ∞   | NaN    
| +∞  | −SRC          | ±0      | − 0     | − SRC         | − ∞   | NaN    
| +∞  | −SRC          | + 0     | ±0      | − SRC         | − ∞   | NaN    
| +∞+∞| + F + ∞       | DEST + ∞| DEST + ∞| ±F or ±0 + ∞  | − ∞   | NaN NaN
| NaN | NaN           | NaN     | NaN     | NaN           | NaN   | NaN    
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-arithmetic-operand| Means integer.
| (#IA) exception.                                       |               
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF Instruction = FISUB
  THEN
     DEST <- DEST − ConvertToDoubleExtendedPrecisionFP(SRC);
  ELSE (* Source operand is floating-point value *)
     DEST <- DEST − SRC;
FI;
IF Instruction = FSUBP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Operand is an SNaN value or unsupported
|    | format. Operands are infinities of like
|    | sign.                                  
| #D | Source operand is a denormal value.    
| #U | Result is too small for destination    
|    | format.                                
| #O | Result is too large for destination    
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FSUBR
description:
FSUBR/FSUBRP/FISUBR - Reverse Subtract:
| Opcode | Instruction        | 64-Bit Mode| Compat/Leg Mode| Description                            
| D8 /5  | FSUBR m32fp        | Valid      | Valid          | Subtract ST(0) from m32fp and store    
|        |                    |            |                | result in ST(0).                       
| DC /5  | FSUBR m64fp        | Valid      | Valid          | Subtract ST(0) from m64fp and store    
|        |                    |            |                | result in ST(0).                       
| D8 E8+i| FSUBR ST(0), ST(i) | Valid      | Valid          | Subtract ST(0) from ST(i) and store    
|        |                    |            |                | result in ST(0).                       
| DC E0+i| FSUBR ST(i), ST(0) | Valid      | Valid          | Subtract ST(i) from ST(0) and store    
|        |                    |            |                | result in ST(i).                       
| DE E0+i| FSUBRP ST(i), ST(0)| Valid      | Valid          | Subtract ST(i) from ST(0), store result
|        |                    |            |                | in ST(i), and pop register stack.      
| DE E1  | FSUBRP             | Valid      | Valid          | Subtract ST(1) from ST(0), store result
|        |                    |            |                | in ST(1), and pop register stack.      
| DA /5  | FISUBR m32int      | Valid      | Valid          | Subtract ST(0) from m32int and store   
|        |                    |            |                | result in ST(0).                       
| DE /5  | FISUBR m16int      | Valid      | Valid          | Subtract ST(0) from m16int and store   
|        |                    |            |                | result in ST(0).                       

Description:
Subtracts the destination operand from the source operand and stores the difference
in the destination location. The destination operand is always an FPU register;
the source operand can be a register or a memory location. Source operands in
memory can be in single-precision or double-precision floating-point format
or in word or doubleword integer format.

These instructions perform the reverse operations of the FSUB, FSUBP, and FISUB
instructions. They are provided to support more efficient coding.

The no-operand version of the instruction subtracts the contents of the ST(1)
register from the ST(0) register and stores the result in ST(1). The one-operand
version subtracts the contents of the ST(0) register from the contents of a
memory location (either a floating-point or an integer value) and stores the
result in ST(0). The two-operand version, subtracts the contents of the ST(i)
register from the ST(0) register or vice versa.

The FSUBRP instructions perform the additional operation of popping the FPU
register stack following the subtraction. To pop the register stack, the processor
marks the ST(0) register as empty and increments the stack pointer (TOP) by
1. The no-operand version of the floating-point reverse subtract instructions
always results in the register stack being popped. In some assemblers, the mnemonic
for this instruction is FSUBR rather than FSUBRP.

The FISUBR instructions convert an integer source operand to double extended-precision
floating-point format before performing the subtraction.

The following table shows the results obtained when subtracting various classes
of numbers from one another, assuming that neither overflow nor underflow occurs.
Here, the DEST value is subtracted from the SRC value (SRC − DEST = result).

When the difference between two operands of like sign is 0, the result is +0,
except for the round toward −∞ mode, in which case the result is −0. This instruction
also guarantees that +0 − (−0) = +0, and that −0 − (+0) = −0. When the source
operand is an integer 0, it is treated as a +0.

When one operand is ∞, the result is ∞ of the expected sign. If both operands
are ∞ of the same sign, an invalidoperation exception is generated.


Table 3-49. FSUBR/FSUBRP/FISUBR Results:
SRC

| − ∞ | −F or −I + ∞| −0 + ∞   | +0 + ∞   | +F or +I + ∞| + ∞+ ∞| NaN NaN
| −∞  | ±F or ±0    | −DEST    | −DEST    | + F         | + ∞   | NaN    
| −∞  | SRC         | ±0       | + 0      | SRC         | + ∞   | NaN    
| −∞  | SRC         | − 0      | ±0       | SRC         | + ∞   | NaN    
| −∞−∞| − F − ∞     | −DEST − ∞| −DEST − ∞| ±F or ±0 − ∞| + ∞   | NaN NaN
| NaN | NaN         | NaN      | NaN      | NaN         | NaN   | NaN    
Notes: F Means finite floating-point value.

| I * Indicates floating-point invalid-arithmetic-operand| Means integer.
| (#IA) exception.                                       |               
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF Instruction = FISUBR
  THEN
     DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) − DEST;
  ELSE (* Source operand is floating-point value *)
     DEST <- SRC − DEST; FI;
IF Instruction = FSUBRP
  THEN
     PopRegisterStack; FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| Operand is an SNaN value or unsupported
|    | format. Operands are infinities of like
|    | sign.                                  
| #D | Source operand is a denormal value.    
| #U | Result is too small for destination    
|    | format.                                
| #O | Result is too large for destination    
|    | format.                                
| #P | Value cannot be represented exactly    
|    | in destination format.                 

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.  
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #NM            | CR0.EM[bit 2] or CR0.TS[bit 3] = 1.        
| #MF            | If there is a pending x87 FPU exception.   
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: FTST
description:
FTST - TEST:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description            
| D9 E4 | FTST       | Valid      | Valid          | Compare ST(0) with 0.0.

Description:
Compares the value in the ST(0) register with 0.0 and sets the condition code
flags C0, C2, and C3 in the FPU status word according to the results (see table
below).


Table 3-50. FTST Results:
| Condition| C3 0 0 1 1| C2 0 0 0 1| C0 0 1 0 1
This instruction performs an “unordered comparison.” An unordered comparison
also checks the class of the numbers being compared (see “FXAM - Examine ModR/M”
in this chapter). If the value in register ST(0) is a NaN or is in an undefined
format, the condition flags are set to “unordered” and the invalid operation
exception is generated.

The sign of zero is ignored, so that (- 0.0 ← +0.0).

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CASE (relation of operands) OF
  Not comparable:
  ST(0) > 0.0:
  ST(0) < 0.0:
  ST(0) = 0.0:
ESAC;

FPU Flags Affected:
| C1        | Set to 0.      
| C0, C2, C3| See Table 3-50.

Floating-Point Exceptions:
| #IS| Stack underflow occurred.              
| #IA| The source operand is a NaN value or   
|    | is in an unsupported format.           
| #D | The source operand is a denormal value.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FUCOM
description:
FUCOM/FUCOMP/FUCOMPP - Unordered Compare Floating Point Values:
| Opcode | Instruction | 64-Bit Mode| Compat/Leg Mode| Description                              
| DD E0+i| FUCOM ST(i) | Valid      | Valid          | Compare ST(0) with ST(i).                
| DD E1  | FUCOM       | Valid      | Valid          | Compare ST(0) with ST(1).                
| DD E8+i| FUCOMP ST(i)| Valid      | Valid          | Compare ST(0) with ST(i) and pop register
|        |             |            |                | stack.                                   
| DD E9  | FUCOMP      | Valid      | Valid          | Compare ST(0) with ST(1) and pop register
|        |             |            |                | stack.                                   
| DA E9  | FUCOMPP     | Valid      | Valid          | Compare ST(0) with ST(1) and pop register
|        |             |            |                | stack twice.                             

Description:
Performs an unordered comparison of the contents of register ST(0) and ST(i)
and sets condition code flags C0, C2, and C3 in the FPU status word according
to the results (see the table below). If no operand is specified, the contents
of registers ST(0) and ST(1) are compared. The sign of zero is ignored, so that
-0.0 is equal to +0.0.


Table 3-51. FUCOM/FUCOMP/FUCOMPP Results:
| Comparison Results*| C3| C2| C0
| ST0 > ST(i)        | 0 | 0 | 0 
| ST0 < ST(i)        | 0 | 0 | 1 
| ST0 = ST(i)        | 1 | 0 | 0 
| Unordered          | 1 | 1 | 1 
Notes: * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception
is generated.

An unordered comparison checks the class of the numbers being compared (see
“FXAM - Examine ModR/M” in this chapter). The FUCOM/FUCOMP/FUCOMPP instructions
perform the same operations as the FCOM/FCOMP/FCOMPP instructions. The only
difference is that the FUCOM/FUCOMP/FUCOMPP instructions raise the invalid-arithmeticoperand
exception (#IA) only when either or both operands are an SNaN or are in an unsupported
format; QNaNs cause the condition code flags to be set to unordered, but do
not cause an exception to be generated. The FCOM/FCOMP/FCOMPP instructions raise
an invalid-operation exception when either or both of the operands are a NaN
value of any kind or are in an unsupported format.

As with the FCOM/FCOMP/FCOMPP instructions, if the operation results in an invalid-arithmetic-operand
exception being raised, the condition code flags are set only if the exception
is masked.

The FUCOMP instruction pops the register stack following the comparison operation
and the FUCOMPP instruction pops the register stack twice following the comparison
operation. To pop the register stack, the processor marks the ST(0) register
as empty and increments the stack pointer (TOP) by 1.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CASE (relation of operands) OF
  ST > SRC:
  ST < SRC:
  ST = SRC:
ESAC;
IF ST(0) or SRC = QNaN, but not SNaN or unsupported format
  THEN
     C3, C2, C0 <- 111;
  ELSE (* ST(0) or SRC is SNaN or unsupported format *)
     #IA;
     IF FPUControlWord.IM = 1
       THEN
          C3, C2, C0 <- 111;
     FI;
FI;
IF Instruction = FUCOMP
  THEN
     PopRegisterStack;
FI;
IF Instruction = FUCOMPP
  THEN
     PopRegisterStack;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
| C0, C2, C3| See Table 3-51.                      

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                
| #IA| One or both operands are SNaN values     
|    | or have unsupported formats. Detection   
|    | of a QNaN value in and of itself does    
|    | not raise an invalid-operand exception.  
| #D | One or both operands are denormal values.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FXAM
description:
FXAM - Examine ModR/M:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                       
| D9 E5 | FXAM       | Valid      | Valid          | Classify value or number in ST(0).

Description:
Examines the contents of the ST(0) register and sets the condition code flags
C0, C2, and C3 in the FPU status word to indicate the class of value or number
in the register (see the table below).


Table 3-52. FXAM Results:
| Class| C3 0 0 0 0 1 1 1| C2 0 0 1 1 0 0 1| C0 0 1 0 1 0 1 0
The C1 flag is set to the sign of the value in ST(0), regardless of whether
the register is empty or full.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

C1 <- sign bit of ST; (* 0 for positive, 1 for negative *)
CASE (class of value or number in ST(0)) OF
  Unsupported:C3, C2, C0 <- 000;
  NaN:
  Normal:
  Infinity:
  Zero:
  Empty:
  Denormal:
ESAC;

FPU Flags Affected:
| C1        | Sign of value in ST(0).
| C0, C2, C3| See Table 3-52.        

Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FXCH
description:
FXCH - Exchange Register Contents:
| Opcode | Instruction| 64-Bit Mode| Compat/Leg Mode| Description                              
| D9 C8+i| FXCH ST(i) | Valid      | Valid          | Exchange the contents of ST(0) and ST(i).
| D9 C9  | FXCH       | Valid      | Valid          | Exchange the contents of ST(0) and ST(1).

Description:
Exchanges the contents of registers ST(0) and ST(i). If no source operand is
specified, the contents of ST(0) and ST(1) are exchanged.

This instruction provides a simple means of moving values in the FPU register
stack to the top of the stack [ST(0)], so that they can be operated on by those
floating-point instructions that can only operate on values in ST(0). For example,
the following instruction sequence takes the square root of the third register
from the top of the register stack: FXCH ST(3); FSQRT; FXCH ST(3);

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

IF (Number-of-operands) is 1
  THEN
     temp <- ST(0);
     ST(0) <- SRC;
     SRC <- temp;
  ELSE
     temp <- ST(0);
     ST(0) <- ST(1);
     ST(1) <- temp;
FI;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred;
|           | otherwise, set to 1.                 
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FXRSTOR
description:
FXRSTOR - Restore x87 FPU, MMX , XMM, and MXCSR State:
| Opcode/Instruction                | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F AE /1 FXRSTOR m512byte         | M    | Valid      | Valid          | Restore the x87 FPU, MMX, XMM, and MXCSR
|                                   |      |            |                | register state from m512byte.           
| REX.W+ 0F AE /1 FXRSTOR64 m512byte| M    | Valid      | N.E.           | Restore the x87 FPU, MMX, XMM, and MXCSR
|                                   |      |            |                | register state from m512byte.           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Reloads the x87 FPU, MMX technology, XMM, and MXCSR registers from the 512-byte
memory image specified in the source operand. This data should have been written
to memory previously using the FXSAVE instruction, and in the same format as
required by the operating modes. The first byte of the data should be located
on a 16-byte boundary. There are three distinct layouts of the FXSAVE state
map: one for legacy and compatibility mode, a second format for 64-bit mode
FXSAVE/FXRSTOR with REX.W=0, and the third format is for 64-bit mode with FXSAVE64/FXRSTOR64.
Table 3-53 shows the layout of the legacy/compatibility mode state information
in memory and describes the fields in the memory image for the FXRSTOR and FXSAVE
instructions. Table 3-56 shows the layout of the 64-bit mode state information
when REX.W is set (FXSAVE64/FXRSTOR64). Table 3-57 shows the layout of the 64-bit
mode state information when REX.W is clear (FXSAVE/FXRSTOR).

The state image referenced with an FXRSTOR instruction must have been saved
using an FXSAVE instruction or be in the same format as required by Table 3-53,
Table 3-56, or Table 3-57. Referencing a state image saved with an FSAVE, FNSAVE
instruction or incompatible field layout will result in an incorrect state restoration.

The FXRSTOR instruction does not flush pending x87 FPU exceptions. To check
and raise exceptions when loading x87 FPU state information with the FXRSTOR
instruction, use an FWAIT instruction after the FXRSTOR instruction.

If the OSFXSR bit in control register CR4 is not set, the FXRSTOR instruction
may not restore the states of the XMM and MXCSR registers. This behavior is
implementation dependent.

If the MXCSR state contains an unmasked exception with a corresponding status
flag also set, loading the register with the FXRSTOR instruction will not result
in a SIMD floating-point error condition being generated. Only the next occurrence
of this unmasked exception will result in the exception being generated.

Bits 16 through 32 of the MXCSR register are defined as reserved and should
be set to 0. Attempting to write a 1 in any of these bits from the saved state
image will result in a general protection exception (#GP) being generated.

Bytes 464:511 of an FXSAVE image are available for software use. FXRSTOR ignores
the content of bytes 464:511 in an FXSAVE state image.

Operation:

(x87 FPU, MMX, XMM7-XMM0, MXCSR) <- Load(SRC);

x87 FPU and SIMD Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #GP(0)         | For an illegal memory operand effective     
|                | address in the CS, DS, ES, FS or GS         
|                | segments. If a memory operand is not        
|                | aligned on a 16-byte boundary, regardless   
|                | of segment. (See alignment check exception  
|                | [#AC] below.) For an attempt to set         
|                | reserved bits in MXCSR.                     
| #SS(0)         | For an illegal address in the SS segment.   
| #PF(fault-code)| For a page fault.                           
| #NM            | If CR0.TS[bit 3] = 1. If CR0.EM[bit         
|                | 2] = 1.                                     
| #UD            | If CPUID.01H:EDX.FXSR[bit 24] = 0. If       
|                | instruction is preceded by a LOCK prefix.   
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  
| #UD            | If the LOCK prefix is used.                 

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 16-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH. For an attempt to set reserved     
|    | bits in MXCSR.                            
| #NM| If CR0.TS[bit 3] = 1. If CR0.EM[bit       
|    | 2] = 1.                                   
| #UD| If CPUID.01H:EDX.FXSR[bit 24] = 0. If     
|    | the LOCK prefix is used.                  

Virtual-8086 Mode Exceptions:
Same exceptions as in real address mode.

| #PF(fault-code)| For a page fault.              
| #AC            | For unaligned memory reference.
| #UD            | If the LOCK prefix is used.    

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form. If memory operand is not aligned     
|                | on a 16-byte boundary, regardless of       
|                | segment. For an attempt to set reserved    
|                | bits in MXCSR.                             
| #PF(fault-code)| For a page fault.                          
| #NM            | If CR0.TS[bit 3] = 1. If CR0.EM[bit        
|                | 2] = 1.                                    
| #UD            | If CPUID.01H:EDX.FXSR[bit 24] = 0. If      
|                | instruction is preceded by a LOCK prefix.  
| #AC            | If this exception is disabled a general    
|                | protection exception (#GP) is signaled     
|                | if the memory operand is not aligned       
|                | on a 16-byte boundary, as described        
|                | above. If the alignment check exception    
|                | (#AC) is enabled (and the CPL is 3),       
|                | signaling of #AC is not guaranteed and     
|                | may vary with implementation, as follows.  
|                | In all implementations where #AC is        
|                | not signaled, a                            
general protection exception is signaled in its place. In addition, the width
of the alignment check may also vary with implementation. For instance, for
a given implementation, an alignment check exception might be signaled for a
2-byte misalignment, whereas a general protection exception might be signaled
for all other misalignments (4-, 8-, or 16-byte misalignments).


platform: x86
mnem: FXSAVE
description:
FXSAVE - Save x87 FPU, MMX Technology, and SSE State:
| Opcode/Instruction               | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F AE /0 FXSAVE m512byte         | M    | Valid      | Valid          | Save the x87 FPU, MMX, XMM, and MXCSR
|                                  |      |            |                | register state to m512byte.          
| REX.W+ 0F AE /0 FXSAVE64 m512byte| M    | Valid      | N.E.           | Save the x87 FPU, MMX, XMM, and MXCSR
|                                  |      |            |                | register state to m512byte.          

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Saves the current state of the x87 FPU, MMX technology, XMM, and MXCSR registers
to a 512-byte memory location specified in the destination operand. The content
layout of the 512 byte region depends on whether the processor is operating
in non-64-bit operating modes or 64-bit sub-mode of IA-32e mode.

Bytes 464:511 are available to software use. The processor does not write to
bytes 464:511 of an FXSAVE area.

The operation of FXSAVE in non-64-bit modes is described first.


Non-64-Bit Mode Operation:
Table 3-53 shows the layout of the state information in memory when the processor
is operating in legacy modes.


Table 3-53. Non-64-bit-Mode Layout of FXSAVE and FXRSTOR Memory Region:
| 15 Rsvd| 14 MXCSR_MASK| 13 FPU CS Reserved Reserved Reserved| 12| 11 Table 3-53.| 10 FPU IP MXCSR| 9 Non-64-bit-Mode Layout of FXSAVE and| 8 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6| 7 FOP Rsrvd| 6| 5 Rsvd FPU DS ST0/MM0 ST1/MM1 ST2/MM2  | 4 FTW| 3 FSW| 2 FPU DP| 1 FCW| 0 0 16 32 48 64 80 96 112 128 144 160
|        |              | Reserved Reserved Reserved Reserved |   |               |                | FXRSTOR                               | XMM7                                |            |  | ST3/MM3 ST4/MM4 ST5/MM5 ST6/MM6 ST7/MM7|      |      |         |      | 176 192 208 224 240 256 272          
|        |              | Reserved                            |   |               |                |                                       |                                     |            |  |                                        |      |      |         |      |                                      

Memory Region (Contd.):
| 15| 14| 13| 12| 11| 10| 9| 8 Reserved Reserved Reserved Reserved| 7| 6| 5| 4| 3| 2| 1| 0 288 304 320 336 352 368 384 400 416
|   |   |   |   |   |   |  | Reserved Reserved Reserved Reserved  |  |  |  |  |  |  |  | 432 448 464 480 496                  
|   |   |   |   |   |   |  | Reserved Reserved Reserved Available |  |  |  |  |  |  |  |                                      
|   |   |   |   |   |   |  | Available Available                  |  |  |  |  |  |  |  |                                      
The destination operand contains the first byte of the memory image, and it
must be aligned on a 16-byte boundary. A misaligned destination operand will
result in a general-protection (#GP) exception being generated (or in some cases,
an alignment check exception [#AC]).

The FXSAVE instruction is used when an operating system needs to perform a context
switch or when an exception handler needs to save and examine the current state
of the x87 FPU, MMX technology, and/or XMM and MXCSR registers.

The fields in Table 3-53 are defined in Table 3-54.


Table 3-54. Field Definitions:
| Field                  | Definition                                           
| FCW                    | x87 FPU Control Word (16 bits). See                  
|                        | Figure 8-6 in the Intel® 64 and IA-32                
|                        | Architectures Software Developer's Manual,           
|                        | Volume 1, for the layout of the x87                  
|                        | FPU control word.                                    
| FSW                    | x87 FPU Status Word (16 bits). See Figure            
|                        | 8-4 in the Intel® 64 and IA-32 Architectures         
|                        | Software Developer's Manual, Volume                  
|                        | 1, for the layout of the x87 FPU status              
|                        | word.                                                
| Abridged FTW           | x87 FPU Tag Word (8 bits). The tag information       
|                        | saved here is abridged, as described                 
|                        | in the following paragraphs.                         
| FOP                    | x87 FPU Opcode (16 bits). The lower                  
|                        | 11 bits of this field contain the opcode,            
|                        | upper 5 bits are reserved. See Figure                
|                        | 8-8 in the Intel® 64 and IA-32 Architectures         
|                        | Software Developer's Manual, Volume                  
|                        | 1, for the layout of the x87 FPU opcode              
|                        | field.                                               
| FPU IP                 | x87 FPU Instruction Pointer Offset (32               
|                        | bits). The contents of this field differ             
|                        | depending on the current addressing                  
|                        | mode (32-bit or 16-bit) of the processor             
|                        | when the FXSAVE instruction was executed:            
|                        | 32-bit mode  -  32-bit IP offset. 16-bit               
|                        | mode  -  low 16 bits are IP offset; high               
|                        | 16 bits are reserved. See “x87 FPU Instruction       
|                        | and Operand (Data) Pointers” in Chapter              
|                        | 8 of the Intel® 64 and IA-32 Architectures           
|                        | Software Developer's Manual, Volume                  
|                        | 1, for a description of the x87 FPU                  
|                        | instruction pointer.                                 
| FPU CS                 | x87 FPU Instruction Pointer Selector                 
|                        | (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit         
|                        | 13] = 1, the processor deprecates the                
|                        | FPU CS and FPU DS values, and this field             
|                        | is saved as 0000H. (Contd.)                          
| Field                  | Definition                                           
| FPU DP                 | x87 FPU Instruction Operand (Data) Pointer           
|                        | Offset (32 bits). The contents of this               
|                        | field differ depending on the current                
|                        | addressing mode (32-bit or 16-bit) of                
|                        | the processor when the FXSAVE instruction            
|                        | was executed: 32-bit mode  -  32-bit DP                
|                        | offset. 16-bit mode  -  low 16 bits are                
|                        | DP offset; high 16 bits are reserved.                
|                        | See “x87 FPU Instruction and Operand                 
|                        | (Data) Pointers” in Chapter 8 of the                 
|                        | Intel® 64 and IA-32 Architectures Software           
|                        | Developer's Manual, Volume 1, for a                  
|                        | description of the x87 FPU operand pointer.          
| FPU DS                 | x87 FPU Instruction Operand (Data) Pointer           
|                        | Selector (16 bits). If CPUID.(EAX=07H,ECX=0H):EBX[bit
|                        | 13] = 1, the processor deprecates the                
|                        | FPU CS and FPU DS values, and this field             
|                        | is saved as 0000H.                                   
| MXCSR                  | MXCSR Register State (32 bits). See                  
|                        | Figure 10-3 in the Intel® 64 and IA-32               
|                        | Architectures Software Developer's Manual,           
|                        | Volume 1, for the layout of the MXCSR                
|                        | register. If the OSFXSR bit in control               
|                        | register CR4 is not set, the FXSAVE                  
|                        | instruction may not save this register.              
|                        | This behavior is implementation dependent.           
| MXCSR_MASK             | MXCSR_MASK (32 bits). This mask can                  
|                        | be used to adjust values written to                  
|                        | the MXCSR register, ensuring that reserved           
|                        | bits are set to 0. Set the mask bits                 
|                        | and flags in MXCSR to the mode of operation          
|                        | desired for SSE and SSE2 SIMD floating-point         
|                        | instructions. See “Guidelines for Writing            
|                        | to the MXCSR Register” in Chapter 11                 
|                        | of the Intel® 64 and IA-32 Architectures             
|                        | Software Developer's Manual, Volume                  
|                        | 1, for instructions for how to determine             
|                        | and use the MXCSR_MASK value.                        
| ST0/MM0 through ST7/MM7| x87 FPU or MMX technology registers.                 
|                        | These 80-bit fields contain the x87                  
|                        | FPU data registers or the MMX technology             
|                        | registers, depending on the state of                 
|                        | the processor prior to the execution                 
|                        | of the FXSAVE instruction. If the processor          
|                        | had been executing x87 FPU instruction               
|                        | prior to the FXSAVE instruction, the                 
|                        | x87 FPU data registers are saved; if                 
|                        | it had been executing MMX instructions               
|                        | (or SSE or SSE2 instructions that operated           
|                        | on the MMX technology registers), the                
|                        | MMX technology registers are saved.                  
|                        | When the MMX technology registers are                
|                        | saved, the high 16 bits of the field                 
|                        | are reserved.                                        
| XMM0 through XMM7      | XMM registers (128 bits per field).                  
|                        | If the OSFXSR bit in control register                
|                        | CR4 is not set, the FXSAVE instruction               
|                        | may not save these registers. This behavior          
|                        | is implementation dependent.                         
The FXSAVE instruction saves an abridged version of the x87 FPU tag word in
the FTW field (unlike the FSAVE instruction, which saves the complete tag word).
The tag information is saved in physical register order (R0 through R7), rather
than in top-of-stack (TOS) order. With the FXSAVE instruction, however, only
a single bit (1 for valid or 0 for empty) is saved for each tag. For example,
assume that the tag word is currently set as follows:

| R7                                        | R6| R5| R4| R3| R2| R1| R0                                         
| 11                                        | xx| xx| xx| 11| 11| 11| 11 Here, 11B indicates empty stack elements
|                                           |   |   |   |   |   |   | and “xx” indicates valid (00B), zero       
|                                           |   |   |   |   |   |   | (01B), or special (10B). For this example, 
|                                           |   |   |   |   |   |   | the FXSAVE instruction saves only the      
|                                           |   |   |   |   |   |   | following 8 bits of information:           
| R7                                        | R6| R5| R4| R3| R2| R1| R0                                         
| 0 FXSAVE instruction does not check       | 1 | 1 | 1 | 0 | 0 | 0 | 0 Here, a 1 is saved for any valid,        
| for pending unmasked floating-point       |   |   |   |   |   |   | zero, or special tag, and a 0 is saved     
| exceptions. (The FXSAVE operation in      |   |   |   |   |   |   | for any empty tag. The operation of        
| this regard is similar to the operation   |   |   |   |   |   |   | the FXSAVE instruction differs from        
| of the FNSAVE instruction). After the     |   |   |   |   |   |   | that of the FSAVE instruction, the as      
| FXSAVE instruction has saved the state    |   |   |   |   |   |   | follows: •••                               
| of the x87 FPU, MMX technology, XMM,      |   |   |   |   |   |   |                                            
| and MXCSR registers, the processor retains|   |   |   |   |   |   |                                            
| the contents of the registers. Because    |   |   |   |   |   |   |                                            
| of this behavior, the FXSAVE instruction  |   |   |   |   |   |   |                                            
| cannot be used by an application program  |   |   |   |   |   |   |                                            
| to pass a “clean” x87 FPU state to a      |   |   |   |   |   |   |                                            
| procedure, since it retains the current   |   |   |   |   |   |   |                                            
| state. To clean the x87 FPU state, an     |   |   |   |   |   |   |                                            
| application must explicitly execute       |   |   |   |   |   |   |                                            
| an FINIT instruction after an FXSAVE      |   |   |   |   |   |   |                                            
| instruction to reinitialize the x87       |   |   |   |   |   |   |                                            
| FPU state. The format of the memory       |   |   |   |   |   |   |                                            
| image saved with the FXSAVE instruction   |   |   |   |   |   |   |                                            
| is the same regardless of the current     |   |   |   |   |   |   |                                            
| addressing mode (32-bit or 16-bit) and    |   |   |   |   |   |   |                                            
| operating mode (protected, real address,  |   |   |   |   |   |   |                                            
| or system management).                    |   |   |   |   |   |   |                                            
This behavior differs from the FSAVE instructions, where the memory image format
is different depending on the addressing mode and operating mode. Because of
the different image formats, the memory image saved with the FXSAVE instruction
cannot be restored correctly with the FRSTOR instruction, and likewise the state
saved with the FSAVE instruction cannot be restored correctly with the FXRSTOR
instruction.

The FSAVE format for FTW can be recreated from the FTW valid bits and the stored
80-bit FP data (assuming the stored data was not the contents of MMX technology
registers) using Table 3-55.


Table 3-55. Recreating FSAVE Format:
| Exponent all 1's| Exponent all 0's| Fraction all 0's| J and M bits| FTW valid bit x87 FTW
| 0               | 0               | 0               | 0x          | 10                   
| 0               | 0               | 0               | 1x          | 00                   
| 0               | 0               | 1               | 00          | 10                   
| 0               | 0               | 1               | 10          | 00                   
| 0               | 1               | 0               | 0x          | 10                   
| 0               | 1               | 0               | 1x          | 10                   
| 0               | 1               | 1               | 00          | 01                   
| 0               | 1               | 1               | 10          | 10                   
| 1               | 0               | 0               | 1x          | 10                   
| 1               | 0               | 0               | 1x          | 10                   
| 1               | 0               | 1               | 00          | 10                   
| 1               | 0               | 1               | 10          | 10 11                
The J-bit is defined to be the 1-bit binary integer to the left of the decimal
place in the significand. The M-bit is defined to be the most significant bit
of the fractional portion of the significand (i.e., the bit immediately to the
right of the decimal place).

When the M-bit is the most significant bit of the fractional portion of the
significand, it must be 0 if the fraction is all 0's.


IA-32e Mode Operation:
In compatibility sub-mode of IA-32e mode, legacy SSE registers, XMM0 through
XMM7, are saved according to the legacy FXSAVE map. In 64-bit mode, all of the
SSE registers, XMM0 through XMM15, are saved. Additionally, there are two different
layouts of the FXSAVE map in 64-bit mode, corresponding to FXSAVE64 (which requires
REX.W=1) and FXSAVE (REX.W=0). In the FXSAVE64 map (Table 3-56), the FPU IP
and FPU DP pointers are 64-bit wide. In the FXSAVE map for 64-bit mode (Table
3-57), the FPU IP and FPU DP pointers are 32-bits.


Table 3-56. Layout of the 64-bit-mode FXSAVE64 Map (requires REX.W = 1):
| 15 MXCSR_MASK| 14| 13 Reserved Reserved Reserved Reserved| 12 FPU IP| 11| 10 MXCSR Table 3-56.| 9| 8 Layout of the 64-bit-mode FXSAVE64| 7 FOP| 6| 5 Reserved ST0/MM0 ST1/MM1 ST2/MM2 ST3/MM3| 4 FTW FPU DP| 3 FSW| 2| 1 FCW| 0 0 16 32 48 64 80 96 112
|              |   | Reserved Reserved                     |          |   |                     |  | Map                                 |      |  | ST4/MM4 ST5/MM5                           |             |      |  |      |                          

(requires REX.W = 1) (Contd.):
| 15         | 14           | 13 Reserved Reserved                | 12| 11 Table 3-57.| 10                                       | 9 Layout of the 64-bit-mode FXSAVE Map| 8| 7 XMM0 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6      | 6| 5 ST6/MM6 ST7/MM7                        | 4    | 3    | 2       | 1    | 0 128 144 160 176 192 208 224 240 256
|            |              |                                     |   |               |                                          | (REX.W = 0)                           |  | XMM7 XMM8 XMM9 XMM10 XMM11 XMM12 XMM13    |  |                                          |      |      |         |      | 272 288 304 320 336 352 368 384 400  
|            |              |                                     |   |               |                                          |                                       |  | XMM14 XMM15 Reserved Reserved Reserved    |  |                                          |      |      |         |      | 416 432 448 464 480 496              
|            |              |                                     |   |               |                                          |                                       |  | Available Available Available             |  |                                          |      |      |         |      |                                      
| 15 Reserved| 14 MXCSR_MASK| 13 FPU CS Reserved Reserved Reserved| 12| 11            | 10 FPU IP MXCSR Layout of the 64-bit-mode| 9                                     | 8| 7 FOP Reserved XMM0                       | 6| 5 Reserved FPU DS ST0/MM0 ST1/MM1 ST2/MM2| 4 FTW| 3 FSW| 2 FPU DP| 1 FCW| 0 0 16 32 48 64 80 96 112 128 144 160
|            |              | Reserved Reserved Reserved Reserved |   |               | FXSAVE Map (REX.W = 0) (Contd.) (Contd.) |                                       |  |                                           |  | ST3/MM3 ST4/MM4 ST5/MM5 ST6/MM6 ST7/MM7  |      |      |         |      |                                      
|            |              | Reserved Table 3-57.                |   |               |                                          |                                       |  |                                           |  |                                          |      |      |         |      |                                      
| 15         | 14           | 13                                  | 12| 11            | 10                                       | 9                                     | 8| 7 XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7      | 6| 5                                        | 4    | 3    | 2       | 1    | 0 176 192 208 224 240 256 272 288 304
|            |              |                                     |   |               |                                          |                                       |  | XMM8 XMM9 XMM10 XMM11 XMM12 XMM13 XMM14   |  |                                          |      |      |         |      | 320 336 352 368 384 400 416 432 448  
|            |              |                                     |   |               |                                          |                                       |  | XMM15 Reserved Reserved Reserved Available|  |                                          |      |      |         |      | 464 480 496                          
|            |              |                                     |   |               |                                          |                                       |  | Available Available                       |  |                                          |      |      |         |      |                                      
Operation:

IF 64-Bit Mode
  THEN
     IF REX.W = 1
       THEN
          DEST <- Save64BitPromotedFxsave(x87 FPU, MMX, XMM7-XMM0,
          MXCSR);
       ELSE
          DEST <- Save64BitDefaultFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);
     FI;
  ELSE
     DEST <- SaveLegacyFxsave(x87 FPU, MMX, XMM7-XMM0, MXCSR);
FI;

Protected Mode Exceptions:
| #GP(0)         | For an illegal memory operand effective     
|                | address in the CS, DS, ES, FS or GS         
|                | segments. If a memory operand is not        
|                | aligned on a 16-byte boundary, regardless   
|                | of segment. (See the description of         
|                | the alignment check exception [#AC]         
|                | below.)                                     
| #SS(0)         | For an illegal address in the SS segment.   
| #PF(fault-code)| For a page fault.                           
| #NM            | If CR0.TS[bit 3] = 1. If CR0.EM[bit         
|                | 2] = 1.                                     
| #UD            | If CPUID.01H:EDX.FXSR[bit 24] = 0.          
| #UD            | If the LOCK prefix is used.                 
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 16-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #NM| If CR0.TS[bit 3] = 1. If CR0.EM[bit       
|    | 2] = 1.                                   
| #UD| If CPUID.01H:EDX.FXSR[bit 24] = 0. If     
|    | the LOCK prefix is used.                  

Virtual-8086 Mode Exceptions:
Same exceptions as in real address mode.

| #PF(fault-code)| For a page fault.              
| #AC            | For unaligned memory reference.
| #UD            | If the LOCK prefix is used.    

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the         
|                | SS segment is in a non-canonical form.      
| #GP(0)         | If the memory address is in a non-canonical 
|                | form. If memory operand is not aligned      
|                | on a 16-byte boundary, regardless of        
|                | segment.                                    
| #PF(fault-code)| For a page fault.                           
| #NM            | If CR0.TS[bit 3] = 1. If CR0.EM[bit         
|                | 2] = 1.                                     
| #UD            | If CPUID.01H:EDX.FXSR[bit 24] = 0. If       
|                | the LOCK prefix is used.                    
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  

Implementation Note:
The order in which the processor signals general-protection (#GP) and page-fault
(#PF) exceptions when they both occur on an instruction boundary is given in
Table 5-2 in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3B. This order vary for FXSAVE for different processor implementations.


platform: x86
mnem: FXTRACT
description:
FXTRACT - Extract Exponent and Significand:
| Opcode/Instruction| 64-Bit Mode| Compat/Leg Mode| Description                               
| D9 F4 FXTRACT     | Valid      | Valid          | Separate value in ST(0) into exponent     
|                   |            |                | and significand, store exponent in ST(0), 
|                   |            |                | and push the significand onto the register
|                   |            |                | stack.                                    

Description:
Separates the source value in the ST(0) register into its exponent and significand,
stores the exponent in ST(0), and pushes the significand onto the register stack.
Following this operation, the new top-of-stack register ST(0) contains the value
of the original significand expressed as a floating-point value. The sign and
significand of this value are the same as those found in the source operand,
and the exponent is 3FFFH (biased value for a true exponent of zero). The ST(1)
register contains the value of the original operand's true (unbiased) exponent
expressed as a floating-point value. (The operation performed by this instruction
is a superset of the IEEE-recommended logb(x) function.)

This instruction and the F2XM1 instruction are useful for performing power and
range scaling operations. The FXTRACT instruction is also useful for converting
numbers in double extended-precision floating-point format to decimal representations
(e.g., for printing or displaying).

If the floating-point zero-divide exception (#Z) is masked and the source operand
is zero, an exponent value of ∞ is stored in register ST(1) and 0 with the sign
of the source operand is stored in register ST(0).

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

TEMP <- Significand(ST(0));
ST(0) <- Exponent(ST(0));
TOP<- TOP − 1;
ST(0) <- TEMP;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred;
|           | set to 1 if stack overflow occurred. 
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow or overflow occurred.         
| #IA| Source operand is an SNaN value or unsupported
|    | format.                                       
| #Z | ST(0) operand is ±0.                          
| #D | Source operand is a denormal value.           

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FYL2X
description:
FYL2X - Compute y * log2x:
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                                      
| D9 F1 | FYL2X      | Valid      | Valid          | Replace ST(1) with (ST(1) * log<sub>2</sub>ST(0))
|       |            |            |                | and pop the register stack.                      

Description:
Computes (ST(1) * log<sub>2</sub> (ST(0))), stores the result in resister ST(1),
and pops the FPU register stack. The source operand in ST(0) must be a non-zero
positive number.

The following table shows the results obtained when taking the log of various
classes of numbers, assuming that neither overflow nor underflow occurs.


Table 3-58. FYL2X Results:
ST(0)

| − ∞| − F| ±0 + ∞****− ∞| +0<+F<+1 + ∞+ F + 0 − 0 − F − ∞| + 1 −0 −0 +0 +0| + F > + 1 − ∞− F − 0 + 0 + F + ∞| + ∞− ∞− ∞+∞+∞| NaN NaN NaN NaN NaN NaN NaN
| NaN| NaN| NaN          | NaN                            | NaN            | NaN                             | NaN          | NaN                        
Notes: F Means finite floating-point value. * Indicates floating-point invalid-operation
(#IA) exception. ** Indicates floating-point zero-divide (#Z) exception.

If the divide-by-zero exception is masked and register ST(0) contains ±0, the
instruction returns ∞ with a sign that is the opposite of the sign of the source
operand in register ST(1).

The FYL2X instruction is designed with a built-in multiplication to optimize
the calculation of logarithms with an arbitrary positive base (b):

log<sub>b</sub>x ← (log<sub>2</sub>b)-1 * log<sub>2</sub>x

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(1) <- ST(1) * log<sub>2</sub>ST(0);
PopRegisterStack;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.               
| #IA| Either operand is an SNaN or unsupported
|    | format. Source operand in register ST(0)
|    | is a negative finite value (not -0).    
| #Z | Source operand in register ST(0) is     
|    | ±0.                                     
| #D | Source operand is a denormal value.     
| #U | Result is too small for destination     
|    | format.                                 
| #O | Result is too large for destination     
|    | format.                                 
| #P | Value cannot be represented exactly     
|    | in destination format.                  

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: FYL2XP1
description:
FYL2XP1 - Compute y * log2(x +1):
| Opcode| Instruction| 64-Bit Mode| Compat/Leg Mode| Description                                     
| D9 F9 | FYL2XP1    | Valid      | Valid          | Replace ST(1) with ST(1) * log<sub>2</sub>(ST(0)
|       |            |            |                | + 1.0) and pop the register stack.              

Description:
Computes (ST(1) * log<sub>2</sub>(ST(0) + 1.0)), stores the result in register
ST(1), and pops the FPU register stack. The source operand in ST(0) must be
in the range:

| -(1 -| 2⁄2))to(1− ∞       | 2⁄2) The source operand in ST(1) can       
|      |                    | range from −∞ to +∞. If the ST(0) operand  
|      |                    | is outside of its acceptable range,        
|      |                    | the result is undefined and software       
|      |                    | should not rely on an exception being      
|      |                    | generated. Under some circumstances        
|      |                    | exceptions may be generated when ST(0)     
|      |                    | is out of range, but this behavior is      
|      |                    | implementation specific and not guaranteed.
|      |                    | The following table shows the results      
|      |                    | obtained when taking the log epsilon       
|      |                    | of various classes of numbers, assuming    
|      |                    | that underflow does not occur. FYL2XP1     
|      |                    | Results ST(0) NaN NaN                      
| ST(1)| − F − 0 +0 +F +∞NaN| NaN NaN NaN NaN NaN NaN                    
Notes: F Means finite floating-point value. * Indicates floating-point invalid-operation
(#IA) exception.

This instruction provides optimal accuracy for values of epsilon [the value
in register ST(0)] that are close to 0. For small epsilon (ε) values, more significant
digits can be retained by using the FYL2XP1 instruction than by using (ε+1)
as an argument to the FYL2X instruction. The (ε+1) expression is commonly found
in compound interest and annuity calculations. The result can be simply converted
into a value in another logarithm base by including a scale factor in the ST(1)
source operand. The following equation is used to calculate the scale factor
for a particular logarithm base, where n is the logarithm base desired for the
result of the FYL2XP1 instruction:

scale factor ← log<sub>n</sub> 2

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

ST(1) <- ST(1) * log<sub>2</sub>(ST(0) + 1.0);
PopRegisterStack;

FPU Flags Affected:
| C1        | Set to 0 if stack underflow occurred.
|           | Set if result was rounded up; cleared
|           | otherwise.                           
| C0, C2, C3| Undefined.                           

Floating-Point Exceptions:
| #IS| Stack underflow occurred.                     
| #IA| Either operand is an SNaN value or unsupported
|    | format.                                       
| #D | Source operand is a denormal value.           
| #U | Result is too small for destination           
|    | format.                                       
| #O | Result is too large for destination           
|    | format.                                       
| #P | Value cannot be represented exactly           
|    | in destination format.                        

Protected Mode Exceptions:
| #NM| CR0.EM[bit 2] or CR0.TS[bit 3] = 1.     
| #MF| If there is a pending x87 FPU exception.
| #UD| If the LOCK prefix is used.             

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: HADDPD
description:
HADDPD - Packed Double-FP Horizontal Add:
| Opcode/Instruction                 | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                           
| 66 0F 7C /r HADDPD xmm1, xmm2/m128 | RM   | V/V           | SSE3              | Horizontal add packed double-precision
|                                    |      |               |                   | floating-point values from xmm2/m128  
|                                    |      |               |                   | to xmm1.                              
| VEX.NDS.128.66.0F.WIG 7C /r VHADDPD| RVM  | V/V           | AVX               | Horizontal add packed double-precision
| xmm1,xmm2, xmm3/m128               |      |               |                   | floating-point values from xmm2 and   
|                                    |      |               |                   | xmm3/mem.                             
| VEX.NDS.256.66.0F.WIG 7C /r VHADDPD| RVM  | V/V           | AVX               | Horizontal add packed double-precision
| ymm1, ymm2, ymm3/m256              |      |               |                   | floating-point values from ymm2 and   
|                                    |      |               |                   | ymm3/mem.                             

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Adds the double-precision floating-point values in the high and low quadwords
of the destination operand and stores the result in the low quadword of the
destination operand.

Adds the double-precision floating-point values in the high and low quadwords
of the source operand and stores the result in the high quadword of the destination
operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

See Figure 3-15 for HADDPD; see Figure 3-16 for VHADDPD.

HADDPD xmm1, xmm2/m128

xmm2

| [127:64]| [63:0]/m128                               
| [127:64]| xmm1 Result: xmm1[63:0] + xmm1[127:64]xmm1
| [127:64]| [63:0]                                    
OM15993

| Figure 3-15.| HADDPD - Packed Double-FP Horizontal Add
| X3          | X0                                    
| Y3          | Y0                                    
| Y2 + Y3     | X0 + X1 VHADDPD operation             
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the first source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register.
The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand can be a YMM register or a 256-bit memory location.
The destination operand is a YMM register.

Operation:

HADDPD (128-bit Legacy SSE version)
DEST[63:0] <- SRC1[127:64] + SRC1[63:0]
DEST[127:64] <- SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] (Unmodified)
VHADDPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[127:64] + SRC1[63:0]
DEST[127:64] <- SRC2[127:64] + SRC2[63:0]
DEST[VLMAX-1:128] <- 0
VHADDPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[127:64] + SRC1[63:0]
DEST[127:64] <- SRC2[127:64] + SRC2[63:0]
DEST[191:128] <- SRC1[255:192] + SRC1[191:128]
DEST[255:192] <- SRC2[255:192] + SRC2[191:128]

Intel C/C++ Compiler Intrinsic Equivalent:
| VHADDPD:| __m256d _mm256_hadd_pd (__m256d a, __m256d
|         | b);                                       
| HADDPD: | __m128d _mm_hadd_pd (__m128d a, __m128d   
|         | b);                                       

Exceptions:
When the source operand is a memory operand, the operand must be aligned on
a 16-byte boundary or a generalprotection exception (#GP) will be generated.


Numeric Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: HADDPS
description:
HADDPS - Packed Single-FP Horizontal Add:
| Opcode/Instruction                 | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                           
| F2 0F 7C /r HADDPS xmm1, xmm2/m128 | RM   | V/V           | SSE3              | Horizontal add packed single-precision
|                                    |      |               |                   | floating-point values from xmm2/m128  
|                                    |      |               |                   | to xmm1.                              
| VEX.NDS.128.F2.0F.WIG 7C /r VHADDPS| RVM  | V/V           | AVX               | Horizontal add packed single-precision
| xmm1, xmm2, xmm3/m128              |      |               |                   | floating-point values from xmm2 and   
|                                    |      |               |                   | xmm3/mem.                             
| VEX.NDS.256.F2.0F.WIG 7C /r VHADDPS| RVM  | V/V           | AVX               | Horizontal add packed single-precision
| ymm1, ymm2, ymm3/m256              |      |               |                   | floating-point values from ymm2 and   
|                                    |      |               |                   | ymm3/mem.                             

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Adds the single-precision floating-point values in the first and second dwords
of the destination operand and stores the result in the first dword of the destination
operand.

Adds single-precision floating-point values in the third and fourth dword of
the destination operand and stores the result in the second dword of the destination
operand.

Adds single-precision floating-point values in the first and second dword of
the source operand and stores the result in the third dword of the destination
operand.

Adds single-precision floating-point values in the third and fourth dword of
the source operand and stores the result in the fourth dword of the destination
operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

See Figure 3-17 for HADDPS; see Figure 3-18 for VHADDPS.

HADDPS xmm1, xmm2/m128

xmm2/

| [127:96]| [95:64]                                   | [63:32]                         | [31:0]m128                                
| [127:96]| [95:64]xmm2/m128 [31:0] + xmm2/m128[63:32]| [63:32]xmm1[95:64] +xmm1[127:96]| xmm1 xmm2/m128 RESULT: [95:64] + xmm2/xmm1
|         |                                           |                                 | m128[127:96]                              
| [127:96]| [95:64]                                   | [63:32]                         | [31:0]                                    
OM15994

| Figure 3-17.| HADDPS - Packed Single-FP Horizontal Add
| X7          | X0                                    
| Y7          | Y0                                    
| Y6+Y7       | X0+X1 VHADDPS operation               
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the first source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register.
The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand can be a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Operation:

HADDPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[63:32] + SRC1[31:0]
DEST[63:32] <- SRC1[127:96] + SRC1[95:64]
DEST[95:64] <- SRC2[63:32] + SRC2[31:0]
DEST[127:96] <- SRC2[127:96] + SRC2[95:64]
DEST[VLMAX-1:128] (Unmodified)
VHADDPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[63:32] + SRC1[31:0]
DEST[63:32] <- SRC1[127:96] + SRC1[95:64]
DEST[95:64] <- SRC2[63:32] + SRC2[31:0]
DEST[127:96] <- SRC2[127:96] + SRC2[95:64]
DEST[VLMAX-1:128] <- 0
VHADDPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[63:32] + SRC1[31:0]
DEST[63:32] <- SRC1[127:96] + SRC1[95:64]
DEST[95:64] <- SRC2[63:32] + SRC2[31:0]
DEST[127:96] <- SRC2[127:96] + SRC2[95:64]
DEST[159:128] <- SRC1[191:160] + SRC1[159:128]
DEST[191:160] <- SRC1[255:224] + SRC1[223:192]
DEST[223:192] <- SRC2[191:160] + SRC2[159:128]
DEST[255:224] <- SRC2[255:224] + SRC2[223:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| HADDPS: | __m128 _mm_hadd_ps (__m128 a, __m128   
|         | b);                                    
| VHADDPS:| __m256 _mm256_hadd_ps (__m256 a, __m256
|         | b);                                    

Exceptions:
When the source operand is a memory operand, the operand must be aligned on
a 16-byte boundary or a generalprotection exception (#GP) will be generated.


Numeric Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: HLT
description:
HLT - Halt:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description
| F4    | HLT        | NP   | Valid      | Valid          | Halt       

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Stops instruction execution and places the processor in a HALT state. An enabled
interrupt (including NMI and SMI), a debug exception, the BINIT# signal, the
INIT# signal, or the RESET# signal will resume execution. If an interrupt (including
NMI) is used to resume execution after a HLT instruction, the saved instruction
pointer (CS:EIP) points to the instruction following the HLT instruction.

When a HLT instruction is executed on an Intel 64 or IA-32 processor supporting
Intel Hyper-Threading Technology, only the logical processor that executes the
instruction is halted. The other logical processors in the physical processor
remain active, unless they are each individually halted by executing a HLT instruction.

The HLT instruction is a privileged instruction. When the processor is running
in protected or virtual-8086 mode, the privilege level of a program or procedure
must be 0 to execute the HLT instruction.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

Enter Halt state;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not
|       | 0.                                   
| #UD   | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
None.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: HSUBPD
description:
HSUBPD - Packed Double-FP Horizontal Subtract:
| Opcode/Instruction                 | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 66 0F 7D /r HSUBPD xmm1, xmm2/m128 | RM   | V/V           | SSE3              | Horizontal subtract packed double-precision
|                                    |      |               |                   | floating-point values from xmm2/m128       
|                                    |      |               |                   | to xmm1.                                   
| VEX.NDS.128.66.0F.WIG 7D /r VHSUBPD| RVM  | V/V           | AVX               | Horizontal subtract packed double-precision
| xmm1,xmm2, xmm3/m128               |      |               |                   | floating-point values from xmm2 and        
|                                    |      |               |                   | xmm3/mem.                                  
| VEX.NDS.256.66.0F.WIG 7D /r VHSUBPD| RVM  | V/V           | AVX               | Horizontal subtract packed double-precision
| ymm1, ymm2, ymm3/m256              |      |               |                   | floating-point values from ymm2 and        
|                                    |      |               |                   | ymm3/mem.                                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
The HSUBPD instruction subtracts horizontally the packed DP FP numbers of both
operands.

Subtracts the double-precision floating-point value in the high quadword of
the destination operand from the low quadword of the destination operand and
stores the result in the low quadword of the destination operand.

Subtracts the double-precision floating-point value in the high quadword of
the source operand from the low quadword of the source operand and stores the
result in the high quadword of the destination operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

See Figure 3-19 for HSUBPD; see Figure 3-20 for VHSUBPD.

HSUBPD xmm1, xmm2/m128

xmm2

| [127:64]| [63:0]/m128                               
| [127:64]| xmm1 Result: xmm1[63:0] - xmm1[127:64]xmm1
| [127:64]| [63:0]                                    
OM15995

| Figure 3-19.| HSUBPD - Packed Double-FP Horizontal Subtract
| X3          | X0                                         
| Y3          | Y0                                         
| Y2 - Y3     | X0 - X1 VHSUBPD operation                  
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the first source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register.
The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand can be a YMM register or a 256-bit memory location.
The destination operand is a YMM register.

Operation:

HSUBPD (128-bit Legacy SSE version)
DEST[63:0] <- SRC1[63:0] - SRC1[127:64]
DEST[127:64] <- SRC2[63:0] - SRC2[127:64]
DEST[VLMAX-1:128] (Unmodified)
VHSUBPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC1[127:64]
DEST[127:64] <- SRC2[63:0] - SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VHSUBPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC1[127:64]
DEST[127:64] <- SRC2[63:0] - SRC2[127:64]
DEST[191:128] <- SRC1[191:128] - SRC1[255:192]
DEST[255:192] <- SRC2[191:128] - SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| HSUBPD: | __m128d _mm_hsub_pd(__m128d a, __m128d    
|         | b)                                        
| VHSUBPD:| __m256d _mm256_hsub_pd (__m256d a, __m256d
|         | b);                                       

Exceptions:
When the source operand is a memory operand, the operand must be aligned on
a 16-byte boundary or a generalprotection exception (#GP) will be generated.


Numeric Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: HSUBPS
description:
HSUBPS - Packed Single-FP Horizontal Subtract:
| Opcode/Instruction                 | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F2 0F 7D /r HSUBPS xmm1, xmm2/m128 | RM   | V/V           | SSE3              | Horizontal subtract packed single-precision
|                                    |      |               |                   | floating-point values from xmm2/m128       
|                                    |      |               |                   | to xmm1.                                   
| VEX.NDS.128.F2.0F.WIG 7D /r VHSUBPS| RVM  | V/V           | AVX               | Horizontal subtract packed single-precision
| xmm1, xmm2, xmm3/m128              |      |               |                   | floating-point values from xmm2 and        
|                                    |      |               |                   | xmm3/mem.                                  
| VEX.NDS.256.F2.0F.WIG 7D /r VHSUBPS| RVM  | V/V           | AVX               | Horizontal subtract packed single-precision
| ymm1, ymm2, ymm3/m256              |      |               |                   | floating-point values from ymm2 and        
|                                    |      |               |                   | ymm3/mem.                                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Subtracts the single-precision floating-point value in the second dword of the
destination operand from the first dword of the destination operand and stores
the result in the first dword of the destination operand.

Subtracts the single-precision floating-point value in the fourth dword of the
destination operand from the third dword of the destination operand and stores
the result in the second dword of the destination operand.

Subtracts the single-precision floating-point value in the second dword of the
source operand from the first dword of the source operand and stores the result
in the third dword of the destination operand.

Subtracts the single-precision floating-point value in the fourth dword of the
source operand from the third dword of the source operand and stores the result
in the fourth dword of the destination operand.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

See Figure 3-21 for HSUBPS; see Figure 3-22 for VHSUBPS.

HSUBPS xmm1, xmm2/m128

xmm2/

| [127:96]| [95:64]                                   | [63:32]                        | [31:0]m128                                
| [127:96]| [95:64]xmm2/m128 [31:0] - xmm2/m128[63:32]| [63:32]xmm1[95:64] xmm1[127:96]| xmm1 xmm2/m128 RESULT: [95:64] - xmm2/xmm1
|         |                                           |                                | m128[127:96]                              
| [127:96]| [95:64]                                   | [63:32]                        | [31:0]                                    
OM15996

| Figure 3-21.| HSUBPS - Packed Single-FP Horizontal Subtract
| X7          | X0                                         
| Y7          | Y0                                         
| Y6-Y7       | X0-X1 VHSUBPS operation                    
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the first source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register.
The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand can be a YMM register or a 256-bit memory location.
The destination operand is a YMM register.

Operation:

HSUBPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] - SRC1[63:32]
DEST[63:32] <- SRC1[95:64] - SRC1[127:96]
DEST[95:64] <- SRC2[31:0] - SRC2[63:32]
DEST[127:96] <- SRC2[95:64] - SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VHSUBPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC1[63:32]
DEST[63:32] <- SRC1[95:64] - SRC1[127:96]
DEST[95:64] <- SRC2[31:0] - SRC2[63:32]
DEST[127:96] <- SRC2[95:64] - SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VHSUBPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC1[63:32]
DEST[63:32] <- SRC1[95:64] - SRC1[127:96]
DEST[95:64] <- SRC2[31:0] - SRC2[63:32]
DEST[127:96] <- SRC2[95:64] - SRC2[127:96]
DEST[159:128] <- SRC1[159:128] - SRC1[191:160]
DEST[191:160] <- SRC1[223:192] - SRC1[255:224]
DEST[223:192] <- SRC2[159:128] - SRC2[191:160]
DEST[255:224] <- SRC2[223:192] - SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalent:
| HSUBPS: | __m128 _mm_hsub_ps(__m128 a, __m128    
|         | b);                                    
| VHSUBPS:| __m256 _mm256_hsub_ps (__m256 a, __m256
|         | b);                                    

Exceptions:
When the source operand is a memory operand, the operand must be aligned on
a 16-byte boundary or a generalprotection exception (#GP) will be generated.


Numeric Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: IDIV
description:
IDIV - Signed Divide:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| F6 /7        | IDIV r/m8  | M    | Valid      | Valid          | Signed divide AX by r/m8, with result    
|              |            |      |            |                | stored in: AL ← Quotient, AH ← Remainder.
| REX + F6 /7  | IDIV r/m8* | M    | Valid      | N.E.           | Signed divide AX by r/m8, with result    
|              |            |      |            |                | stored in AL ← Quotient, AH ← Remainder. 
| F7 /7        | IDIV r/m16 | M    | Valid      | Valid          | Signed divide DX:AX by r/m16, with result
|              |            |      |            |                | stored in AX ← Quotient, DX ← Remainder. 
| F7 /7        | IDIV r/m32 | M    | Valid      | Valid          | Signed divide EDX:EAX by r/m32, with     
|              |            |      |            |                | result stored in EAX ← Quotient, EDX     
|              |            |      |            |                | ← Remainder.                             
| REX.W + F7 /7| IDIV r/m64 | M    | Valid      | N.E.           | Signed divide RDX:RAX by r/m64, with     
|              |            |      |            |                | result stored in RAX ← Quotient, RDX     
|              |            |      |            |                | ← Remainder.                             
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Divides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source
operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX
registers. The source operand can be a general-purpose register or a memory
location. The action of this instruction depends on the operand size (dividend/divisor).

Non-integral results are truncated (chopped) towards 0. The remainder is always
less than the divisor in magnitude. Overflow is indicated with the #DE (divide
error) exception rather than with the CF flag.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is applied,
the instruction divides the signed value in RDX:RAX by the source operand. RAX
contains a 64-bit quotient; RDX contains a 64-bit remainder.

See the summary chart at the beginning of this section for encoding data and
limits. See Table 3-60.


Table 3-60. IDIV Results:
| Operand Size| Dividend AX DX:AX EDX:EAX RDX:RAX| Divisor r/m8 r/m16 r/m32 r/m64| Quotient AL AX EAX RAX| Remainder AH DX EDX RDX| Quotient Range −128 to +127 −32,768   
|             |                                  |                               |                       |                        | to +32,767 −231 to 232 − 1 −263 to 264
|             |                                  |                               |                       |                        | − 1                                   
Operation:

IF SRC = 0
  THEN #DE; (* Divide error *)
FI;
IF OperandSize = 8 (* Word/byte operation *)
  THEN
     temp <- AX / SRC; (* Signed division *)
     IF (temp > 7FH) or (temp < 80H)
     (* If a positive result is greater than 7FH or a negative result is less than 80H *)
       THEN #DE; (* Divide error *)
       ELSE
          AL <- temp;
          AH <- AX SignedModulus SRC;
     FI;
  ELSE IF OperandSize = 16 (* Doubleword/word operation *)
     THEN
       temp <- DX:AX / SRC; (* Signed division *)
       IF (temp > 7FFFH) or (temp < 8000H)
       (* If a positive result is greater than 7FFFH
       or a negative result is less than 8000H *)
          THEN
             #DE; (* Divide error *)
          ELSE
             AX <- temp;
             DX <- DX:AX SignedModulus SRC;
       FI;
     FI;
  ELSE IF OperandSize = 32 (* Quadword/doubleword operation *)
       temp <- EDX:EAX / SRC; (* Signed division *)
       IF (temp > 7FFFFFFFH) or (temp < 80000000H)
       (* If a positive result is greater than 7FFFFFFFH
       or a negative result is less than 80000000H *)
          THEN
             #DE; (* Divide error *)
          ELSE
             EAX <- temp;
             EDX <- EDXE:AX SignedModulus SRC;
       FI;
     FI;
  ELSE IF OperandSize = 64 (* Doublequadword/quadword operation *)
       temp <- RDX:RAX / SRC; (* Signed division *)
       IF (temp > 7FFFFFFFFFFFFFFFH) or (temp < 8000000000000000H)
       (* If a positive result is greater than 7FFFFFFFFFFFFFFFH
       or a negative result is less than 8000000000000000H *)
          THEN
             #DE; (* Divide error *)
          ELSE
             RAX <- temp;
             RDX <- RDE:RAX SignedModulus SRC;
       FI;
     FI;
FI;

Flags Affected:
The CF, OF, SF, ZF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #DE            | If the source operand (divisor) is 0.   
|                | The signed result (quotient) is too     
|                | large for the destination.              
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #DE| If the source operand (divisor) is 0.
The signed result (quotient) is too large for the destination.

| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #DE| If the source operand (divisor) is 0.
The signed result (quotient) is too large for the destination.

| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #DE            | If the source operand (divisor) is 0       
|                | If the quotient is too large for the       
|                | designated register.                       
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


