# instructions

platform: x86
mnem: ARPL
description:
ARPL - Adjust RPL Field of Segment Selector:
| Opcode| Instruction    | Op/En| 64-bit Mode| Compat/Leg Mode| Description                         
| 63 /r | ARPL r/m16, r16| NP   | N. E.      | Valid          | Adjust RPL of r/m16 to not less than
|       |                |      |            |                | RPL of r16.                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| NP   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
Compares the RPL fields of two segment selectors. The first operand (the destination
operand) contains one segment selector and the second operand (source operand)
contains the other. (The RPL field is located in bits 0 and 1 of each operand.)
If the RPL field of the destination operand is less than the RPL field of the
source operand, the ZF flag is set and the RPL field of the destination operand
is increased to match that of the source operand. Otherwise, the ZF flag is
cleared and no change is made to the destination operand. (The destination operand
can be a word register or a memory location; the source operand must be a word
register.)

The ARPL instruction is provided for use by operating-system procedures (however,
it can also be used by applications). It is generally used to adjust the RPL
of a segment selector that has been passed to the operating system by an application
program to match the privilege level of the application program. Here the segment
selector passed to the operating system is placed in the destination operand
and segment selector for the application program's code segment is placed in
the source operand. (The RPL field in the source operand represents the privilege
level of the application program.) Execution of the ARPL instruction then ensures
that the RPL of the segment selector received by the operating system is no
lower (does not have a higher privilege) than the privilege level of the application
program (the segment selector for the application program's code segment can
be read from the stack following a procedure call).

This instruction executes as described in compatibility mode and legacy mode.
It is not encodable in 64-bit mode.

See “Checking Caller Access Privileges” in Chapter 3, “Protected-Mode Memory
Management,” of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A, for more information about the use of this instruction.

Operation:

IF 64-BIT MODE
  THEN
     See MOVSXD;
  ELSE
     IF DEST[RPL) < SRC[RPL)
       THEN
          ZF <- 1;
          DEST[RPL) <- SRC[RPL);
       ELSE
          ZF <- 0;
     FI;
FI;

Flags Affected:
The ZF flag is set to 1 if the RPL field of the destination operand is less
than that of the source operand; otherwise, it is set to 0.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #UD| The ARPL instruction is not recognized  
|    | in real-address mode. If the LOCK prefix
|    | is used.                                

Virtual-8086 Mode Exceptions:
| #UD| The ARPL instruction is not recognized  
|    | in virtual-8086 mode. If the LOCK prefix
|    | is used.                                

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Not applicable.


platform: x86
mnem: BLENDPD
description:
BLENDPD  -  Blend Packed Double Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 66 0F 3A 0D /r ib BLENDPD xmm1, xmm2/m128,| RMI  | V/V           | SSE4_1            | Select packed DP-FP values from xmm1         
| imm8                                      |      |               |                   | and xmm2/m128 from mask specified in         
|                                           |      |               |                   | imm8 and store the values into xmm1.         
| VEX.NDS.128.66.0F3A.WIG 0D /r ib VBLENDPD | RVMI | V/V           | AVX               | Select packed double-precision floating-point
| xmm1, xmm2, xmm3/m128, imm8               |      |               |                   | Values from xmm2 and xmm3/m128 from          
|                                           |      |               |                   | mask in imm8 and store the values in         
|                                           |      |               |                   | xmm1.                                        
| VEX.NDS.256.66.0F3A.WIG 0D /r ib VBLENDPD | RVMI | V/V           | AVX               | Select packed double-precision floating-point
| ymm1, ymm2, ymm3/m256, imm8               |      |               |                   | Values from ymm2 and ymm3/m256 from          
|                                           |      |               |                   | mask in imm8 and store the values in         
|                                           |      |               |                   | ymm1.                                        

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8[3:0]

Description:
Double-precision floating-point values from the second source operand (third
operand) are conditionally merged with values from the first source operand
(second operand) and written to the destination operand (first operand). The
immediate bits [3:0] determine whether the corresponding double-precision floating-point
value in the destination is copied from the second source or first source. If
a bit in the mask, corresponding to a word, is “1", then the double-precision
floating-point value in the second source operand is copied, else the value
in the first source operand is copied. 128-bit Legacy SSE version: The second
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand can be a YMM register or a 256-bit
memory location. The destination operand is a YMM register.

Operation:

BLENDPD (128-bit Legacy SSE version)
IF (IMM8[0] = 0)THEN DEST[63:0] <- DEST[63:0]
     ELSE DEST [63:0] <- SRC[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] <- DEST[127:64]
     ELSE DEST [127:64] <- SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDPD (VEX.128 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]
     ELSE DEST [63:0] <- SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]
     ELSE DEST [127:64] <- SRC2[127:64] FI
DEST[VLMAX-1:128] <- 0
VBLENDPD (VEX.256 encoded version)
IF (IMM8[0] = 0)THEN DEST[63:0] <- SRC1[63:0]
     ELSE DEST [63:0] <- SRC2[63:0] FI
IF (IMM8[1] = 0) THEN DEST[127:64] <- SRC1[127:64]
     ELSE DEST [127:64] <- SRC2[127:64] FI
IF (IMM8[2] = 0) THEN DEST[191:128] <- SRC1[191:128]
     ELSE DEST [191:128] <- SRC2[191:128] FI
IF (IMM8[3] = 0) THEN DEST[255:192] <- SRC1[255:192]
     ELSE DEST [255:192] <- SRC2[255:192] FI

Intel C/C++ Compiler Intrinsic Equivalent:
| BLENDPD: | __m128d _mm_blend_pd (__m128d v1, __m128d
|          | v2, const int mask);                     
| VBLENDPD:| __m256d _mm256_blend_pd (__m256d a,      
|          | __m256d b, const int mask);              

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: BEXTR
description:
BEXTR  -  Bit Field Extract:
| Opcode/Instruction                   | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                          
| VEX.NDS1.LZ.0F38.W0 F7 /r BEXTR r32a,| RMV  | V/V            | BMI1              | Contiguous bitwise extract from r/m32
| r/m32, r32b                          |      |                |                   | using r32b as control; store result  
|                                      |      |                |                   | in r32a.                             
| VEX.NDS1.LZ.0F38.W1 F7 /r BEXTR r64a,| RMV  | V/N.E.         | BMI1              | Contiguous bitwise extract from r/m64
| r/m64, r64b                          |      |                |                   | using r64b as control; store result  
|                                      |      |                |                   | in r64a                              
Notes: 1. ModRM:r/m is used to encode the first source operand (second operand)
and VEX.vvvv encodes the second source operand (third operand).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3   | Operand 4
| RMV  | ModRM:reg (w)| ModRM:r/m (r)| VEX.vvvv (r)| NA       

Description:
Extracts contiguous bits from the first source operand (the second operand)
using an index value and length value specified in the second source operand
(the third operand). Bit 7:0 of the second source operand specifies the starting
bit position of bit extraction. A START value exceeding the operand size will
not extract any bits from the second source operand. Bit 15:8 of the second
source operand specifies the maximum number of bits (LENGTH) beginning at the
START position to extract. Only bit positions up to (OperandSize -1) of the
first source operand are extracted. The extracted bits are written to the destination
register, starting from the least significant bit. All higher order bits in
the destination operand (starting at bit position LENGTH) are zeroed. The destination
register is cleared if no bits are extracted. This instruction is not supported
in real mode and virtual-8086 mode. The operand size is always 32 bits if not
in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored
in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal
to 0 will cause #UD.

Operation:

START <- SRC2[7:0];
LEN <- SRC2[15:8];
TEMP <- ZERO_EXTEND_TO_512 (SRC1 );
DEST <- ZERO_EXTEND(TEMP[START+LEN -1: START]);
ZF <- (DEST = 0);

Flags Affected:
ZF is updated based on the result. AF, SF, and PF are undefined. All other flags
are cleared.


Intel C/C++ Compiler Intrinsic Equivalent:
| BEXTR:| unsigned __int32 _bextr_u32(unsigned
|       | __int32 src, unsigned __int32 start.
|       | unsigned __int32 len);              
| BEXTR:| unsigned __int64 _bextr_u64(unsigned
|       | __int64 src, unsigned __int32 start.
|       | unsigned __int32 len);              

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BLENDPS
description:
BLENDPS  -  Blend Packed Single Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 66 0F 3A 0C /r ib BLENDPS xmm1, xmm2/m128,| RMI  | V/V           | SSE4_1            | Select packed single precision floating-point
| imm8                                      |      |               |                   | values from xmm1 and xmm2/m128 from          
|                                           |      |               |                   | mask specified in imm8 and store the         
|                                           |      |               |                   | values into xmm1.                            
| VEX.NDS.128.66.0F3A.WIG 0C /r ib VBLENDPS | RVMI | V/V           | AVX               | Select packed single-precision floating-point
| xmm1, xmm2, xmm3/m128, imm8               |      |               |                   | values from xmm2 and xmm3/m128 from          
|                                           |      |               |                   | mask in imm8 and store the values in         
|                                           |      |               |                   | xmm1.                                        
| VEX.NDS.256.66.0F3A.WIG 0C /r ib VBLENDPS | RVMI | V/V           | AVX               | Select packed single-precision floating-point
| ymm1, ymm2, ymm3/m256, imm8               |      |               |                   | values from ymm2 and ymm3/m256 from          
|                                           |      |               |                   | mask in imm8 and store the values in         
|                                           |      |               |                   | ymm1.                                        

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Packed single-precision floating-point values from the second source operand
(third operand) are conditionally merged with values from the first source operand
(second operand) and written to the destination operand (first operand). The
immediate bits [7:0] determine whether the corresponding single precision floating-point
value in the destination is copied from the second source or first source. If
a bit in the mask, corresponding to a word, is “1", then the single-precision
floating-point value in the second source operand is copied, else the value
in the first source operand is copied. 128-bit Legacy SSE version: The second
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand can be a YMM register or a 256-bit
memory location. The destination operand is a YMM register.

Operation:

BLENDPS (128-bit Legacy SSE version)
IF (IMM8[0] = 0) THEN DEST[31:0] <-DEST[31:0]
     ELSE DEST [31:0] <- SRC[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] <- DEST[63:32]
     ELSE DEST [63:32] <- SRC[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] <- DEST[95:64]
     ELSE DEST [95:64] <- SRC[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] <- DEST[127:96]
     ELSE DEST [127:96] <- SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDPS (VEX.128 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]
     ELSE DEST [31:0] <- SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]
     ELSE DEST [63:32] <- SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]
     ELSE DEST [95:64] <- SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]
     ELSE DEST [127:96] <- SRC2[127:96] FI
DEST[VLMAX-1:128] <- 0
VBLENDPS (VEX.256 encoded version)
IF (IMM8[0] = 0) THEN DEST[31:0] <-SRC1[31:0]
     ELSE DEST [31:0] <- SRC2[31:0] FI
IF (IMM8[1] = 0) THEN DEST[63:32] <- SRC1[63:32]
     ELSE DEST [63:32] <- SRC2[63:32] FI
IF (IMM8[2] = 0) THEN DEST[95:64] <- SRC1[95:64]
     ELSE DEST [95:64] <- SRC2[95:64] FI
IF (IMM8[3] = 0) THEN DEST[127:96] <- SRC1[127:96]
     ELSE DEST [127:96] <- SRC2[127:96] FI
IF (IMM8[4] = 0) THEN DEST[159:128] <- SRC1[159:128]
     ELSE DEST [159:128] <- SRC2[159:128] FI
IF (IMM8[5] = 0) THEN DEST[191:160] <- SRC1[191:160]
     ELSE DEST [191:160] <- SRC2[191:160] FI
IF (IMM8[6] = 0) THEN DEST[223:192] <- SRC1[223:192]
     ELSE DEST [223:192] <- SRC2[223:192] FI
IF (IMM8[7] = 0) THEN DEST[255:224] <- SRC1[255:224]
     ELSE DEST [255:224] <- SRC2[255:224] FI.

Intel C/C++ Compiler Intrinsic Equivalent:
| BLENDPS: | __m128 _mm_blend_ps (__m128 v1, __m128  
|          | v2, const int mask);                    
| VBLENDPS:| __m256 _mm256_blend_ps (__m256 a, __m256
|          | b, const int mask);                     

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: BLENDVPD
description:
BLENDVPD  -  Variable Blend Packed Double Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 66 0F 38 15 /r BLENDVPD xmm1, xmm2/m128    | RM0  | V/V           | SSE4_1            | Select packed DP FP values from xmm1       
| , <XMM0>                                   |      |               |                   | and xmm2 from mask specified in XMM0       
|                                            |      |               |                   | and store the values in xmm1.              
| VEX.NDS.128.66.0F3A.W0 4B /r /is4 VBLENDVPD| RVMR | V/V           | AVX               | Conditionally copy double-precision        
| xmm1, xmm2, xmm3/m128, xmm4                |      |               |                   | floatingpoint values from xmm2 or xmm3/m128
|                                            |      |               |                   | to xmm1, based on mask bits in the mask    
|                                            |      |               |                   | operand, xmm4.                             
| VEX.NDS.256.66.0F3A.W0 4B /r /is4 VBLENDVPD| RVMR | V/V           | AVX               | Conditionally copy double-precision        
| ymm1, ymm2, ymm3/m256, ymm4                |      |               |                   | floatingpoint values from ymm2 or ymm3/m256
|                                            |      |               |                   | to ymm1, based on mask bits in the mask    
|                                            |      |               |                   | operand, ymm4.                             

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM0  | ModRM:reg (r, w)| ModRM:r/m (r)| implicit XMM0| NA       
| RVMR | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8[7:4]

Description:
Conditionally copy each quadword data element of double-precision floating-point
value from the second source operand and the first source operand depending
on mask bits defined in the mask register operand. The mask bits are the most
significant bit in each quadword element of the mask register. Each quadword
element of the destination operand is copied from:

 - the corresponding quadword element in the second source operand, If a mask bit
is “1"; or
 - the corresponding quadword element in the first source operand, If a mask bit
is “0"

The register assignment of the implicit mask operand for BLENDVPD is defined
to be the architectural register XMM0. 128-bit Legacy SSE version: The first
source operand and the destination operand is the same. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The mask register
operand is implicitly defined to be the architectural register XMM0. An attempt
to execute BLENDVPD with a VEX prefix will cause #UD. VEX.128 encoded version:
The first source operand and the destination operand are XMM registers. The
second source operand is an XMM register or 128-bit memory location. The mask
operand is the third source register, and encoded in bits[7:4] of the immediate
byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is ignored.
The upper bits (VLMAX-1:128) of the corresponding YMM register (destination
register) are zeroed. VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are
YMM registers. The second source operand can be a YMM register or a 256-bit
memory location. The mask operand is the third source register, and encoded
in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored.
In 32-bit mode, imm8[7] is ignored. VEX.W must be 0, otherwise, the instruction
will #UD. VBLENDVPD permits the mask to be any XMM or YMM register. In contrast,
BLENDVPD treats XMM0 implicitly as the mask and do not support non-destructive
destination operation.

Operation:

BLENDVPD (128-bit Legacy SSE version)
MASK <- XMM0
IF (MASK[63] = 0) THEN DEST[63:0] <- DEST[63:0]
     ELSE DEST [63:0] <- SRC[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] <- DEST[127:64]
     ELSE DEST [127:64] <- SRC[127:64] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPD (VEX.128 encoded version)
MASK <- SRC3
IF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]
     ELSE DEST [63:0] <- SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]
     ELSE DEST [127:64] <- SRC2[127:64] FI
DEST[VLMAX-1:128] <- 0
VBLENDVPD (VEX.256 encoded version)
MASK <- SRC3
IF (MASK[63] = 0) THEN DEST[63:0] <- SRC1[63:0]
     ELSE DEST [63:0] <- SRC2[63:0] FI
IF (MASK[127] = 0) THEN DEST[127:64] <- SRC1[127:64]
     ELSE DEST [127:64] <- SRC2[127:64] FI
IF (MASK[191] = 0) THEN DEST[191:128] <- SRC1[191:128]
     ELSE DEST [191:128] <- SRC2[191:128] FI
IF (MASK[255] = 0) THEN DEST[255:192] <- SRC1[255:192]
     ELSE DEST [255:192] <- SRC2[255:192] FI

Intel C/C++ Compiler Intrinsic Equivalent:
| BLENDVPD: | __m128d _mm_blendv_pd(__m128d v1, __m128d
|           | v2, __m128d v3);                         
| VBLENDVPD:| __m128 _mm_blendv_pd (__m128d a, __m128d 
|           | b, __m128d mask);                        
| VBLENDVPD:| __m256 _mm256_blendv_pd (__m256d a,      
|           | __m256d b, __m256d mask);                

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BLENDVPS
description:
BLENDVPS  -  Variable Blend Packed Single Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                  
| 66 0F 38 14 /r BLENDVPS xmm1, xmm2/m128,   | RM0  | V/V           | SSE4_1            | Select packed single precision floating-point
| <XMM0>                                     |      |               |                   | values from xmm1 and xmm2/m128 from          
|                                            |      |               |                   | mask specified in XMM0 and store the         
|                                            |      |               |                   | values into xmm1.                            
| VEX.NDS.128.66.0F3A.W0 4A /r /is4 VBLENDVPS| RVMR | V/V           | AVX               | Conditionally copy single-precision          
| xmm1, xmm2, xmm3/m128, xmm4                |      |               |                   | floatingpoint values from xmm2 or xmm3/m128  
|                                            |      |               |                   | to xmm1, based on mask bits in the specified 
|                                            |      |               |                   | mask operand, xmm4.                          
| VEX.NDS.256.66.0F3A.W0 4A /r /is4 VBLENDVPS| RVMR | V/V           | AVX               | Conditionally copy single-precision          
| ymm1, ymm2, ymm3/m256, ymm4                |      |               |                   | floatingpoint values from ymm2 or ymm3/m256  
|                                            |      |               |                   | to ymm1, based on mask bits in the specified 
|                                            |      |               |                   | mask register, ymm4.                         

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM0  | ModRM:reg (r, w)| ModRM:r/m (r)| implicit XMM0| NA       
| RVMR | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8[7:4]

Description:
Conditionally copy each dword data element of single-precision floating-point
value from the second source operand and the first source operand depending
on mask bits defined in the mask register operand. The mask bits are the most
significant bit in each dword element of the mask register. Each quadword element
of the destination operand is copied from:

 - the corresponding dword element in the second source operand, If a mask bit
is “1"; or
 - the corresponding dword element in the first source operand, If a mask bit is
“0"

The register assignment of the implicit mask operand for BLENDVPS is defined
to be the architectural register XMM0. 128-bit Legacy SSE version: The first
source operand and the destination operand is the same. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The mask register
operand is implicitly defined to be the architectural register XMM0. An attempt
to execute BLENDVPS with a VEX prefix will cause #UD. VEX.128 encoded version:
The first source operand and the destination operand are XMM registers. The
second source operand is an XMM register or 128-bit memory location. The mask
operand is the third source register, and encoded in bits[7:4] of the immediate
byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is ignored.
The upper bits (VLMAX-1:128) of the corresponding YMM register (destination
register) are zeroed. VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and destination operand are
YMM registers. The second source operand can be a YMM register or a 256-bit
memory location. The mask operand is the third source register, and encoded
in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored.
In 32-bit mode, imm8[7] is ignored. VEX.W must be 0, otherwise, the instruction
will #UD. VBLENDVPS permits the mask to be any XMM or YMM register. In contrast,
BLENDVPS treats XMM0 implicitly as the mask and do not support non-destructive
destination operation.

Operation:

BLENDVPS (128-bit Legacy SSE version)
MASK <- XMM0
IF (MASK[31] = 0) THEN DEST[31:0] <- DEST[31:0]
     ELSE DEST [31:0] <- SRC[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] <- DEST[63:32]
     ELSE DEST [63:32] <- SRC[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] <- DEST[95:64]
     ELSE DEST [95:64] <- SRC[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] <- DEST[127:96]
     ELSE DEST [127:96] <- SRC[127:96] FI
DEST[VLMAX-1:128] (Unmodified)
VBLENDVPS (VEX.128 encoded version)
MASK <- SRC3
IF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]
     ELSE DEST [31:0] <- SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]
     ELSE DEST [63:32] <- SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]
     ELSE DEST [95:64] <- SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]
     ELSE DEST [127:96] <- SRC2[127:96] FI
DEST[VLMAX-1:128] <- 0
VBLENDVPS (VEX.256 encoded version)
MASK <- SRC3
IF (MASK[31] = 0) THEN DEST[31:0] <- SRC1[31:0]
     ELSE DEST [31:0] <- SRC2[31:0] FI
IF (MASK[63] = 0) THEN DEST[63:32] <- SRC1[63:32]
     ELSE DEST [63:32] <- SRC2[63:32] FI
IF (MASK[95] = 0) THEN DEST[95:64] <- SRC1[95:64]
     ELSE DEST [95:64] <- SRC2[95:64] FI
IF (MASK[127] = 0) THEN DEST[127:96] <- SRC1[127:96]
     ELSE DEST [127:96] <- SRC2[127:96] FI
IF (MASK[159] = 0) THEN DEST[159:128] <- SRC1[159:128]
     ELSE DEST [159:128] <- SRC2[159:128] FI
IF (MASK[191] = 0) THEN DEST[191:160] <- SRC1[191:160]
     ELSE DEST [191:160] <- SRC2[191:160] FI
IF (MASK[223] = 0) THEN DEST[223:192] <- SRC1[223:192]
     ELSE DEST [223:192] <- SRC2[223:192] FI
IF (MASK[255] = 0) THEN DEST[255:224] <- SRC1[255:224]
     ELSE DEST [255:224] <- SRC2[255:224] FI

Intel C/C++ Compiler Intrinsic Equivalent:
| BLENDVPS: | __m128 _mm_blendv_ps(__m128 v1, __m128   
|           | v2, __m128 v3);                          
| VBLENDVPS:| __m128 _mm_blendv_ps (__m128 a, __m128   
|           | b, __m128 mask);                         
| VBLENDVPS:| __m256 _mm256_blendv_ps (__m256 a, __m256
|           | b, __m256 mask);                         

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BLSI
description:
BLSI  -  Extract Lowest Set Isolated Bit:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                           
| VEX.NDD.LZ.0F38.W0 F3 /3 BLSI r32, r/m32| VM   | V/V            | BMI1              | Extract lowest set bit from r/m32 and 
|                                         |      |                |                   | set that bit in r32.                  
| VEX.NDD.LZ.0F38.W1 F3 /3 BLSI r64, r/m64| VM   | V/N.E.         | BMI1              | Extract lowest set bit from r/m64, and
|                                         |      |                |                   | set that bit in r64.                  

Instruction Operand Encoding:
| Op/En| Operand 1   | Operand 2    | Operand 3| Operand 4
| VM   | VEX.vvvv (w)| ModRM:r/m (r)| NA       | NA       

Description:
Extracts the lowest set bit from the source operand and set the corresponding
bit in the destination register. All other bits in the destination operand are
zeroed. If no bits are set in the source operand, BLSI sets all the bits in
the destination to 0 and sets ZF and CF. This instruction is not supported in
real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored
in non-64-bit modes. An attempt to execute this instruction with VEX.L not equal
to 0 will cause #UD.

Operation:

temp <- (-SRC) bitwiseAND (SRC);
SF <- temp[OperandSize -1];
ZF <- (temp = 0);
IF SRC = 0
  CF <- 0;
ELSE
  CF <- 1;
FI
DEST <- temp;

Flags Affected:
ZF and SF are updated based on the result. CF is set if the source is not zero.
OF flags are cleared. AF and PF flags are undefined.


Intel C/C++ Compiler Intrinsic Equivalent:
| BLSI:| unsigned __int32 _blsi_u32(unsigned
|      | __int32 src);                      
| BLSI:| unsigned __int64 _blsi_u64(unsigned
|      | __int64 src);                      

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BLSMSK
description:
BLSMSK  -  Get Mask Up to Lowest Set Bit:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                              
| VEX.NDD.LZ.0F38.W0 F3 /2 BLSMSK r32,| VM   | V/V            | BMI1              | Set all lower bits in r32 to “1” starting
| r/m32                               |      |                |                   | from bit 0 to lowest set bit in r/m32.   
| VEX.NDD.LZ.0F38.W1 F3 /2 BLSMSK r64,| VM   | V/N.E.         | BMI1              | Set all lower bits in r64 to “1” starting
| r/m64                               |      |                |                   | from bit 0 to lowest set bit in r/m64.   

Instruction Operand Encoding:
| Op/En| Operand 1   | Operand 2    | Operand 3| Operand 4
| VM   | VEX.vvvv (w)| ModRM:r/m (r)| NA       | NA       

Description:
Sets all the lower bits of the destination operand to “1” up to and including
lowest set bit (=1) in the source operand. If source operand is zero, BLSMSK
sets all bits of the destination operand to 1 and also sets CF to 1. This instruction
is not supported in real mode and virtual-8086 mode. The operand size is always
32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1.
VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction
with VEX.L not equal to 0 will cause #UD.

Operation:

temp <- (SRC-1) XOR (SRC) ;
SF <- temp[OperandSize -1];
ZF <- 0;
IF SRC = 0
  CF <- 1;
ELSE
  CF <- 0;
FI
DEST <- temp;

Flags Affected:
SF is updated based on the result. CF is set if the source if zero. ZF and OF
flags are cleared. AF and PF flag are undefined.


Intel C/C++ Compiler Intrinsic Equivalent:
| BLSMSK:| unsigned __int32 _blsmsk_u32(unsigned
|        | __int32 src);                        
| BLSMSK:| unsigned __int64 _blsmsk_u64(unsigned
|        | __int64 src);                        

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BLSR
description:
BLSR  -  Reset Lowest Set Bit:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDD.LZ.0F38.W0 F3 /1 BLSR r32, r/m32| VM   | V/V            | BMI1              | Reset lowest set bit of r/m32, keep     
|                                         |      |                |                   | all other bits of r/m32 and write result
|                                         |      |                |                   | to r32.                                 
| VEX.NDD.LZ.0F38.W1 F3 /1 BLSR r64, r/m64| VM   | V/N.E.         | BMI1              | Reset lowest set bit of r/m64, keep     
|                                         |      |                |                   | all other bits of r/m64 and write result
|                                         |      |                |                   | to r64.                                 

Instruction Operand Encoding:
| Op/En| Operand 1   | Operand 2    | Operand 3| Operand 4
| VM   | VEX.vvvv (w)| ModRM:r/m (r)| NA       | NA       

Description:
Copies all bits from the source operand to the destination operand and resets
(=0) the bit position in the destination operand that corresponds to the lowest
set bit of the source operand. If the source operand is zero BLSR sets CF. This
instruction is not supported in real mode and virtual-8086 mode. The operand
size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64
requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute
this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

temp <- (SRC-1) bitwiseAND ( SRC );
SF <- temp[OperandSize -1];
ZF <- (temp = 0);
IF SRC = 0
  CF <- 1;
ELSE
  CF <- 0;
FI
DEST <- temp;

Flags Affected:
ZF and SF flags are updated based on the result. CF is set if the source is
zero. OF flag is cleared. AF and PF flags are undefined.


Intel C/C++ Compiler Intrinsic Equivalent:
| BLSR:| unsigned __int32 _blsr_u32(unsigned
|      | __int32 src);                      
| BLSR:| unsigned __int64 _blsr_u64(unsigned
|      | __int64 src);                      

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: BOUND
description:
BOUND - Check Array Index Against Bounds:
| Opcode| Instruction      | Op/En| 64-bit Mode| Compat/Leg Mode| Description                         
| 62 /r | BOUND r16, m16&16| RM   | Invalid    | Valid          | Check if r16 (array index) is within
|       |                  |      |            |                | bounds specified by m16&16.         
| 62 /r | BOUND r32, m32&32| RM   | Invalid    | Valid          | Check if r32 (array index) is within
|       |                  |      |            |                | bounds specified by m16&16.         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
BOUND determines if the first operand (array index) is within the bounds of
an array specified the second operand (bounds operand). The array index is a
signed integer located in a register. The bounds operand is a memory location
that contains a pair of signed doubleword-integers (when the operand-size attribute
is 32) or a pair of signed word-integers (when the operand-size attribute is
16). The first doubleword (or word) is the lower bound of the array and the
second doubleword (or word) is the upper bound of the array. The array index
must be greater than or equal to the lower bound and less than or equal to the
upper bound plus the operand size in bytes. If the index is not within bounds,
a BOUND range exceeded exception (#BR) is signaled. When this exception is generated,
the saved return instruction pointer points to the BOUND instruction.

The bounds limit data structure (two words or doublewords containing the lower
and upper limits of the array) is usually placed just before the array itself,
making the limits addressable via a constant offset from the beginning of the
array. Because the address of the array already will be present in a register,
this practice avoids extra bus cycles to obtain the effective address of the
array bounds.

This instruction executes as described in compatibility mode and legacy mode.
It is not valid in 64-bit mode.

Operation:

IF 64bit Mode
  THEN
     #UD;
  ELSE
     IF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)
     (* Below lower bound or above upper bound *)
       THEN #BR; FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #BR            | If the bounds test fails.                  
| #UD            | If second operand is not a memory location.
|                | If the LOCK prefix is used.                
| #GP(0)         | If a memory operand effective address      
|                | is outside the CS, DS, ES, FS, or GS       
|                | segment limit. If the DS, ES, FS, or       
|                | GS register contains a NULL segment        
|                | selector.                                  
| #SS(0)         | If a memory operand effective address      
|                | is outside the SS segment limit.           
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         

Real-Address Mode Exceptions:
| #BR| If the bounds test fails.                  
| #UD| If second operand is not a memory location.
|    | If the LOCK prefix is used.                
| #GP| If a memory operand effective address      
|    | is outside the CS, DS, ES, FS, or GS       
|    | segment limit.                             
| #SS| If a memory operand effective address      
|    | is outside the SS segment limit.           

Virtual-8086 Mode Exceptions:
| #BR            | If the bounds test fails.                  
| #UD            | If second operand is not a memory location.
|                | If the LOCK prefix is used.                
| #GP(0)         | If a memory operand effective address      
|                | is outside the CS, DS, ES, FS, or GS       
|                | segment limit.                             
| #SS(0)         | If a memory operand effective address      
|                | is outside the SS segment limit.           
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made.     

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #UD| If in 64-bit mode.


platform: x86
mnem: BSF
description:
BSF - Bit Scan Forward:
| Opcode          | Instruction   | Op/En| 64-bit Mode| Compat/Leg Mode| Description               
| 0F BC /r        | BSF r16, r/m16| RM   | Valid      | Valid          | Bit scan forward on r/m16.
| 0F BC /r        | BSF r32, r/m32| RM   | Valid      | Valid          | Bit scan forward on r/m32.
| REX.W + 0F BC /r| BSF r64, r/m64| RM   | Valid      | N.E.           | Bit scan forward on r/m64.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Searches the source operand (second operand) for the least significant set bit
(1 bit). If a least significant 1 bit is found, its bit index is stored in the
destination operand (first operand). The source operand can be a register or
a memory location; the destination operand is a register. The bit index is an
unsigned offset from bit 0 of the source operand. If the content of the source
operand is 0, the content of the destination operand is undefined.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

IF SRC = 0
  THEN
     ZF <- 1;
     DEST is undefined;
  ELSE
     ZF <- 0;
     temp <- 0;
     WHILE Bit(SRC, temp) = 0
     DO
       temp <- temp + 1;
     OD;
     DEST <- temp;
FI;

Flags Affected:
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag
is cleared. The CF, OF, SF, AF, and PF, flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: BSR
description:
BSR - Bit Scan Reverse:
| Opcode          | Instruction   | Op/En| 64-bit Mode| Compat/Leg Mode| Description               
| 0F BD /r        | BSR r16, r/m16| RM   | Valid      | Valid          | Bit scan reverse on r/m16.
| 0F BD /r        | BSR r32, r/m32| RM   | Valid      | Valid          | Bit scan reverse on r/m32.
| REX.W + 0F BD /r| BSR r64, r/m64| RM   | Valid      | N.E.           | Bit scan reverse on r/m64.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Searches the source operand (second operand) for the most significant set bit
(1 bit). If a most significant 1 bit is found, its bit index is stored in the
destination operand (first operand). The source operand can be a register or
a memory location; the destination operand is a register. The bit index is an
unsigned offset from bit 0 of the source operand. If the content source operand
is 0, the content of the destination operand is undefined.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

IF SRC = 0
  THEN
     ZF <- 1;
     DEST is undefined;
  ELSE
     ZF <- 0;
     temp <- OperandSize - 1;
     WHILE Bit(SRC, temp) = 0
     DO
       temp <- temp - 1;
     OD;
     DEST <- temp;
FI;

Flags Affected:
The ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag
is cleared. The CF, OF, SF, AF, and PF, flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: BSWAP
description:
BSWAP - Byte Swap:
| Opcode          | Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description                        
| 0F C8+rd        | BSWAP r32  | O    | Valid*     | Valid          | Reverses the byte order of a 32-bit
|                 |            |      |            |                | register.                          
| REX.W + 0F C8+rd| BSWAP r64  | O    | Valid      | N.E.           | Reverses the byte order of a 64-bit
|                 |            |      |            |                | register.                          
Notes: * See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1         | Operand 2| Operand 3| Operand 4
| O    | opcode + rd (r, w)| NA       | NA       | NA       

Description:
Reverses the byte order of a 32-bit or 64-bit (destination) register. This instruction
is provided for converting littleendian values to big-endian format and vice
versa. To swap bytes in a word value (16-bit register), use the XCHG instruction.
When the BSWAP instruction references a 16-bit register, the result is undefined.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.


IA-32 Architecture Legacy Compatibility:
The BSWAP instruction is not supported on IA-32 processors earlier than the
Intel486™ processor family. For compatibility with this instruction, software
should include functionally equivalent code for execution on Intel processors
earlier than the Intel486 processor family.

Operation:

TEMP <- DEST
IF 64-bit mode AND OperandSize = 64
  THEN
     DEST[7:0] <- TEMP[63:56];
     DEST[15:8] <- TEMP[55:48];
     DEST[23:16] <- TEMP[47:40];
     DEST[31:24] <- TEMP[39:32];
     DEST[39:32] <- TEMP[31:24];
     DEST[47:40] <- TEMP[23:16];
     DEST[55:48] <- TEMP[15:8];
     DEST[63:56] <- TEMP[7:0];
  ELSE
     DEST[7:0] <- TEMP[31:24];
     DEST[15:8] <- TEMP[23:16];
     DEST[23:16] <- TEMP[15:8];
     DEST[31:24] <- TEMP[7:0];
FI;

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: BT
description:
BT - Bit Test:
| Opcode             | Instruction   | Op/En| 64-bit Mode| Compat/Leg Mode| Description                   
| 0F A3 /r           | BT r/m16, r16 | MR   | Valid      | Valid          | Store selected bit in CF flag.
| 0F A3 /r           | BT r/m32, r32 | MR   | Valid      | Valid          | Store selected bit in CF flag.
| REX.W + 0F A3 /r   | BT r/m64, r64 | MR   | Valid      | N.E.           | Store selected bit in CF flag.
| 0F BA /4 ib        | BT r/m16, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag.
| 0F BA /4 ib        | BT r/m32, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag.
| REX.W + 0F BA /4 ib| BT r/m64, imm8| MI   | Valid      | N.E.           | Store selected bit in CF flag.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r)| ModRM:reg (r)| NA       | NA       
| MI   | ModRM:r/m (r)| imm8         | NA       | NA       

Description:
Selects the bit in a bit string (specified with the first operand, called the
bit base) at the bit-position designated by the bit offset (specified by the
second operand) and stores the value of the bit in the CF flag. The bit base
operand can be a register or a memory location; the bit offset operand can be
a register or an immediate value:

 - If the bit base operand specifies a register, the instruction takes the modulo
16, 32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode).
 - If the bit base operand specifies a memory location, the operand represents
the address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced
by the offset operand depends on the operand size.

See also: Bit(BitBase, BitOffset) on page 3-10.

Some assemblers support immediate bit offsets larger than 31 by using the immediate
bit offset field in combination with the displacement field of the memory operand.
In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bit
operands) of the immediate bit offset are stored in the immediate bit offset
field, and the highorder bits are shifted and combined with the byte displacement
in the addressing mode by the assembler. The processor will ignore the high
order bits if they are not zero.

When accessing a bit in memory, the processor may access 4 bytes starting from
the memory address for a 32-bit operand size, using by the following relationship:

Effective Address + (4 * (BitOffset DIV 32))

Or, it may access 2 bytes starting from the memory address for a 16-bit operand,
using this relationship:

Effective Address + (2 * (BitOffset DIV 16))

It may do so even when only a single byte needs to be accessed to reach the
given bit. When using this bit addressing mechanism, software should avoid referencing
areas of memory close to address space holes. In particular, it should avoid
references to memory-mapped I/O registers. Instead, software should use the
MOV instructions to load from or store to these addresses, and use the register
form of these instructions to manipulate the data.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bit operands.
See the summary chart at the beginning of this section for encoding data and
limits.

Operation:

CF <- Bit(BitBase, BitOffset);

Flags Affected:
The CF flag contains the value of the selected bit. The ZF flag is unaffected.
The OF, SF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: BTC
description:
BTC - Bit Test and Complement:
| Opcode             | Instruction    | Op/En| 64-bit Mode| Compat/Leg Mode| Description                                  
| 0F BB /r           | BTC r/m16, r16 | MR   | Valid      | Valid          | Store selected bit in CF flag and complement.
| 0F BB /r           | BTC r/m32, r32 | MR   | Valid      | Valid          | Store selected bit in CF flag and complement.
| REX.W + 0F BB /r   | BTC r/m64, r64 | MR   | Valid      | N.E.           | Store selected bit in CF flag and complement.
| 0F BA /7 ib        | BTC r/m16, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and complement.
| 0F BA /7 ib        | BTC r/m32, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and complement.
| REX.W + 0F BA /7 ib| BTC r/m64, imm8| MI   | Valid      | N.E.           | Store selected bit in CF flag and complement.

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       

Description:
Selects the bit in a bit string (specified with the first operand, called the
bit base) at the bit-position designated by the bit offset operand (second operand),
stores the value of the bit in the CF flag, and complements the selected bit
in the bit string. The bit base operand can be a register or a memory location;
the bit offset operand can be a register or an immediate value:

 - If the bit base operand specifies a register, the instruction takes the modulo
16, 32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode). This allows
any bit position to be selected.
 - If the bit base operand specifies a memory location, the operand represents
the address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced
by the offset operand depends on the operand size.

See also: Bit(BitBase, BitOffset) on page 3-10.

Some assemblers support immediate bit offsets larger than 31 by using the immediate
bit offset field in combination with the displacement field of the memory operand.
See “BT - Bit Test” in this chapter for more information on this addressing mechanism.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

CF <- Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) <- NOT Bit(BitBase, BitOffset);

Flags Affected:
The CF flag contains the value of the selected bit before it is complemented.
The ZF flag is unaffected. The OF, SF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: BTR
description:
BTR - Bit Test and Reset:
| Opcode             | Instruction    | Op/En| 64-bit Mode| Compat/Leg Mode| Description                             
| 0F B3 /r           | BTR r/m16, r16 | MR   | Valid      | Valid          | Store selected bit in CF flag and clear.
| 0F B3 /r           | BTR r/m32, r32 | MR   | Valid      | Valid          | Store selected bit in CF flag and clear.
| REX.W + 0F B3 /r   | BTR r/m64, r64 | MR   | Valid      | N.E.           | Store selected bit in CF flag and clear.
| 0F BA /6 ib        | BTR r/m16, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and clear.
| 0F BA /6 ib        | BTR r/m32, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and clear.
| REX.W + 0F BA /6 ib| BTR r/m64, imm8| MI   | Valid      | N.E.           | Store selected bit in CF flag and clear.

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       

Description:
Selects the bit in a bit string (specified with the first operand, called the
bit base) at the bit-position designated by the bit offset operand (second operand),
stores the value of the bit in the CF flag, and clears the selected bit in the
bit string to 0. The bit base operand can be a register or a memory location;
the bit offset operand can be a register or an immediate value:

 - If the bit base operand specifies a register, the instruction takes the modulo
16, 32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode). This allows
any bit position to be selected.
 - If the bit base operand specifies a memory location, the operand represents
the address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced
by the offset operand depends on the operand size.

See also: Bit(BitBase, BitOffset) on page 3-10.

Some assemblers support immediate bit offsets larger than 31 by using the immediate
bit offset field in combination with the displacement field of the memory operand.
See “BT - Bit Test” in this chapter for more information on this addressing mechanism.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

CF <- Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) <- 0;

Flags Affected:
The CF flag contains the value of the selected bit before it is cleared. The
ZF flag is unaffected. The OF, SF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: BTS
description:
BTS - Bit Test and Set:
| Opcode             | Instruction    | Op/En| 64-bit Mode| Compat/Leg Mode| Description                           
| 0F AB /r           | BTS r/m16, r16 | MR   | Valid      | Valid          | Store selected bit in CF flag and set.
| 0F AB /r           | BTS r/m32, r32 | MR   | Valid      | Valid          | Store selected bit in CF flag and set.
| REX.W + 0F AB /r   | BTS r/m64, r64 | MR   | Valid      | N.E.           | Store selected bit in CF flag and set.
| 0F BA /5 ib        | BTS r/m16, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and set.
| 0F BA /5 ib        | BTS r/m32, imm8| MI   | Valid      | Valid          | Store selected bit in CF flag and set.
| REX.W + 0F BA /5 ib| BTS r/m64, imm8| MI   | Valid      | N.E.           | Store selected bit in CF flag and set.

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       

Description:
Selects the bit in a bit string (specified with the first operand, called the
bit base) at the bit-position designated by the bit offset operand (second operand),
stores the value of the bit in the CF flag, and sets the selected bit in the
bit string to 1. The bit base operand can be a register or a memory location;
the bit offset operand can be a register or an immediate value:

 - If the bit base operand specifies a register, the instruction takes the modulo
16, 32, or 64 of the bit offset operand (modulo size depends on the mode and
register size; 64-bit operands are available only in 64-bit mode). This allows
any bit position to be selected.
 - If the bit base operand specifies a memory location, the operand represents
the address of the byte in memory that contains the bit base (bit 0 of the specified
byte) of the bit string. The range of the bit position that can be referenced
by the offset operand depends on the operand size.

See also: Bit(BitBase, BitOffset) on page 3-10.

Some assemblers support immediate bit offsets larger than 31 by using the immediate
bit offset field in combination with the displacement field of the memory operand.
See “BT - Bit Test” in this chapter for more information on this addressing mechanism.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

CF <- Bit(BitBase, BitOffset);
Bit(BitBase, BitOffset) <- 1;

Flags Affected:
The CF flag contains the value of the selected bit before it is set. The ZF
flag is unaffected. The OF, SF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP            | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS            | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: BZHI
description:
BZHI  -  Zero High Bits Starting with Specified Bit Position:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                            
| VEX.NDS1.LZ.0F38.W0 F5 /r BZHI r32a,| RMV  | V/V            | BMI2              | Zero bits in r/m32 starting with the   
| r/m32, r32b                         |      |                |                   | position in r32b, write result to r32a.
| VEX.NDS1.LZ.0F38.W1 F5 /r BZHI r64a,| RMV  | V/N.E.         | BMI2              | Zero bits in r/m64 starting with the   
| r/m64, r64b                         |      |                |                   | position in r64b, write result to r64a.
Notes: 1. ModRM:r/m is used to encode the first source operand (second operand)
and VEX.vvvv encodes the second source operand (third operand).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3   | Operand 4
| RMV  | ModRM:reg (w)| ModRM:r/m (r)| VEX.vvvv (r)| NA       

Description:
BZHI copies the bits of the first source operand (the second operand) into the
destination operand (the first operand) and clears the higher bits in the destination
according to the INDEX value specified by the second source operand (the third
operand). The INDEX is specified by bits 7:0 of the second source operand. The
INDEX value is saturated at the value of OperandSize -1. CF is set, if the number
contained in the 8 low bits of the third operand is greater than OperandSize
-1. This instruction is not supported in real mode and virtual-8086 mode. The
operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand
size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to
execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

N <- SRC2[7:0]
DEST <- SRC1
IF (N < OperandSize)
  DEST[OperandSize-1:N] <- 0
FI
IF (N > OperandSize - 1)
  CF <- 1
ELSE
  CF <- 0
FI

Flags Affected:
ZF, CF and SF flags are updated based on the result. OF flag is cleared. AF
and PF flags are undefined.


Intel C/C++ Compiler Intrinsic Equivalent:
| BZHI:| unsigned __int32 _bzhi_u32(unsigned  
|      | __int32 src, unsigned __int32 index);
| BZHI:| unsigned __int64 _bzhi_u64(unsigned  
|      | __int64 src, unsigned __int32 index);

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: CALL
description:
CALL - Call Procedure:
| Opcode       | Instruction  | Op/En| 64-bit Mode| Compat/Leg Mode| Description                                    
| E8 cw        | CALL rel16   | M    | N.S.       | Valid          | Call near, relative, displacement relative     
|              |              |      |            |                | to next instruction.                           
| E8 cd        | CALL rel32   | M    | Valid      | Valid          | Call near, relative, displacement relative     
|              |              |      |            |                | to next instruction. 32-bit displacement       
|              |              |      |            |                | sign extended to 64-bits in 64-bit mode.       
| FF /2        | CALL r/m16   | M    | N.E.       | Valid          | Call near, absolute indirect, address          
|              |              |      |            |                | given in r/m16.                                
| FF /2        | CALL r/m32   | M    | N.E.       | Valid          | Call near, absolute indirect, address          
|              |              |      |            |                | given in r/m32.                                
| FF /2        | CALL r/m64   | M    | Valid      | N.E.           | Call near, absolute indirect, address          
|              |              |      |            |                | given in r/m64.                                
| 9A cd        | CALL ptr16:16| D    | Invalid    | Valid          | Call far, absolute, address given in           
|              |              |      |            |                | operand.                                       
| 9A cp        | CALL ptr16:32| D    | Invalid    | Valid          | Call far, absolute, address given in           
|              |              |      |            |                | operand.                                       
| FF /3        | CALL m16:16  | M    | Valid      | Valid          | Call far, absolute indirect address            
|              |              |      |            |                | given in m16:16. In 32-bit mode: if            
|              |              |      |            |                | selector points to a gate, then RIP            
|              |              |      |            |                | = 32-bit zero extended displacement            
|              |              |      |            |                | taken from gate; else RIP = zero extended      
|              |              |      |            |                | 16bit offset from far pointer referenced       
|              |              |      |            |                | in the instruction.                            
| FF /3        | CALL m16:32  | M    | Valid      | Valid          | In 64-bit mode: If selector points to          
|              |              |      |            |                | a gate, then RIP = 64-bit displacement         
|              |              |      |            |                | taken from gate; else RIP = zero extended      
|              |              |      |            |                | 32-bit offset from far pointer referenced      
|              |              |      |            |                | in the instruction.                            
| REX.W + FF /3| CALL m16:64  | M    | Valid      | N.E.           | In 64-bit mode: If selector points to          
|              |              |      |            |                | a gate, then RIP = 64-bit displacement         
|              |              |      |            |                | taken from gate; else RIP = 64-bit offset      
|              |              |      |            |                | from far pointer referenced in the instruction.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| D    | Offset       | NA       | NA       | NA       
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Saves procedure linking information on the stack and branches to the called
procedure specified using the target operand. The target operand specifies the
address of the first instruction in the called procedure. The operand can be
an immediate value, a general-purpose register, or a memory location.

This instruction can be used to execute four types of calls:

 - Near Call  - A call to a procedure in the current code segment (the segment currently
pointed to by the CS register), sometimes referred to as an intra-segment call.
 - Far Call  -  A call to a procedure located in a different segment than the current
code segment, sometimes referred to as an inter-segment call.
 - Inter-privilege-level far call  -  A far call to a procedure in a segment at a
different privilege level than that of the currently executing program or procedure.
 - Task switch  -  A call to a procedure located in a different task.

The latter two call types (inter-privilege-level call and task switch) can only
be executed in protected mode. See “Calling Procedures Using Call and RET” in
Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for additional information on near, far, and inter-privilege-level
calls. See Chapter 7, “Task Management,” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A, for information on performing task switches
with the CALL instruction.

Near Call. When executing a near call, the processor pushes the value of the
EIP register (which contains the offset of the instruction following the CALL
instruction) on the stack (for use later as a return-instruction pointer). The
processor then branches to the address in the current code segment specified
by the target operand. The target operand specifies either an absolute offset
in the code segment (an offset from the base of the code segment) or a relative
offset (a signed displacement relative to the current value of the instruction
pointer in the EIP register; this value points to the instruction following
the CALL instruction). The CS register is not changed on near calls.

For a near call absolute, an absolute offset is specified indirectly in a general-purpose
register or a memory location (r/m16, r/m32, or r/m64). The operand-size attribute
determines the size of the target operand (16, 32 or 64 bits). When in 64-bit
mode, the operand size for near call (and all near branches) is forced to 64-bits.
Absolute offsets are loaded directly into the EIP(RIP) register. If the operand
size attribute is 16, the upper two bytes of the EIP register are cleared, resulting
in a maximum instruction pointer size of 16 bits. When accessing an absolute
offset indirectly using the stack pointer [ESP] as the base register, the base
value used is the value of the ESP before the instruction executes.

A relative offset (rel16 or rel32) is generally specified as a label in assembly
code. But at the machine code level, it is encoded as a signed, 16- or 32-bit
immediate value. This value is added to the value in the EIP(RIP) register.
In 64-bit mode the relative offset is always a 32-bit immediate value which
is sign extended to 64-bits before it is added to the value in the RIP register
for the target calculation. As with absolute offsets, the operand-size attribute
determines the size of the target operand (16, 32, or 64 bits). In 64-bit mode
the target operand will always be 64bits because the operand size is forced
to 64-bits for near branches.

Far Calls in Real-Address or Virtual-8086 Mode. When executing a far call in
real- address or virtual-8086 mode, the processor pushes the current value of
both the CS and EIP registers on the stack for use as a return-instruction pointer.
The processor then performs a “far branch” to the code segment and offset specified
with the target operand for the called procedure. The target operand specifies
an absolute far address either directly with a pointer (ptr16:16 or ptr16:32)
or indirectly with a memory location (m16:16 or m16:32). With the pointer method,
the segment and offset of the called procedure is encoded in the instruction
using a 4-byte (16-bit operand size) or 6byte (32-bit operand size) far address
immediate. With the indirect method, the target operand specifies a memory location
that contains a 4-byte (16-bit operand size) or 6-byte (32-bit operand size)
far address. The operand-size attribute determines the size of the offset (16
or 32 bits) in the far address. The far address is loaded directly into the
CS and EIP registers. If the operand-size attribute is 16, the upper two bytes
of the EIP register are cleared.

Far Calls in Protected Mode. When the processor is operating in protected mode,
the CALL instruction can be used to perform the following types of far calls:

 - Far call to the same privilege level
 - Far call to a different privilege level (inter-privilege level call)
 - Task switch (far call to another task)

In protected mode, the processor always uses the segment selector part of the
far address to access the corresponding descriptor in the GDT or LDT. The descriptor
type (code segment, call gate, task gate, or TSS) and access rights determine
the type of call operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment
at the same privilege level is performed. (If the selected code segment is at
a different privilege level and the code segment is non-conforming, a general-protection
exception is generated.) A far call to the same privilege level in protected
mode is very similar to one carried out in real-address or virtual-8086 mode.
The target operand specifies an absolute far address either directly with a
pointer (ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16
or m16:32). The operand- size attribute determines the size of the offset (16
or 32 bits) in the far address. The new code segment selector and its descriptor
are loaded into CS register; the offset from the instruction is loaded into
the EIP register.

A call gate (described in the next paragraph) can also be used to perform a
far call to a code segment at the same privilege level. Using this mechanism
provides an extra level of indirection and is the preferred method of making
calls between 16-bit and 32-bit code segments.

When executing an inter-privilege-level far call, the code segment for the procedure
being called must be accessed through a call gate. The segment selector specified
by the target operand identifies the call gate. The target

operand can specify the call gate segment selector either directly with a pointer
(ptr16:16 or ptr16:32) or indirectly with a memory location (m16:16 or m16:32).
The processor obtains the segment selector for the new code segment and the
new instruction pointer (offset) from the call gate descriptor. (The offset
from the target operand is ignored when a call gate is used.)

On inter-privilege-level calls, the processor switches to the stack for the
privilege level of the called procedure. The segment selector for the new stack
segment is specified in the TSS for the currently running task. The branch to
the new code segment occurs after the stack switch. (Note that when using a
call gate to perform a far call to a segment at the same privilege level, no
stack switch occurs.) On the new stack, the processor pushes the segment selector
and stack pointer for the calling procedure's stack, an optional set of parameters
from the calling procedures stack, and the segment selector and instruction
pointer for the calling procedure's code segment. (A value in the call gate
descriptor determines how many parameters to copy to the new stack.) Finally,
the processor branches to the address of the procedure being called within the
new code segment.

Executing a task switch with the CALL instruction is similar to executing a
call through a call gate. The target operand specifies the segment selector
of the task gate for the new task activated by the switch (the offset in the
target operand is ignored). The task gate in turn points to the TSS for the
new task, which contains the segment selectors for the task's code and stack
segments. Note that the TSS also contains the EIP value for the next instruction
that was to be executed before the calling task was suspended. This instruction
pointer value is loaded into the EIP register to re-start the calling task.

The CALL instruction can also specify the segment selector of the TSS directly,
which eliminates the indirection of the task gate. See Chapter 7, “Task Management,”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3A, for information on the mechanics of a task switch.

When you execute at task switch with a CALL instruction, the nested task flag
(NT) is set in the EFLAGS register and the new TSS's previous task link field
is loaded with the old task's TSS selector. Code is expected to suspend this
nested task by executing an IRET instruction which, because the NT flag is set,
automatically uses the previous task link to return to the calling task. (See
“Task Linking” in Chapter 7 of the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A, for information on nested tasks.) Switching tasks
with the CALL instruction differs in this regard from JMP instruction. JMP does
not set the NT flag and therefore does not expect an IRET instruction to suspend
the task.

Mixing 16-Bit and 32-Bit Calls. When making far calls between 16-bit and 32-bit
code segments, use a call gate. If the far call is from a 32-bit code segment
to a 16-bit code segment, the call should be made from the first 64 KBytes of
the 32-bit code segment. This is because the operand-size attribute of the instruction
is set to 16, so only a 16-bit return address offset can be saved. Also, the
call should be made using a 16-bit call gate so that 16-bit values can be pushed
on the stack. See Chapter 21, “Mixing 16-Bit and 32-Bit Code,” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 3B, for more
information.

Far Calls in Compatibility Mode. When the processor is operating in compatibility
mode, the CALL instruction can be used to perform the following types of far
calls:

 - Far call to the same privilege level, remaining in compatibility mode
 - Far call to the same privilege level, transitioning to 64-bit mode
 - Far call to a different privilege level (inter-privilege level call), transitioning
to 64-bit mode

Note that a CALL instruction can not be used to cause a task switch in compatibility
mode since task switches are not supported in IA-32e mode.

In compatibility mode, the processor always uses the segment selector part of
the far address to access the corresponding descriptor in the GDT or LDT. The
descriptor type (code segment, call gate) and access rights determine the type
of call operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment
at the same privilege level is performed. (If the selected code segment is at
a different privilege level and the code segment is non-conforming, a general-protection
exception is generated.) A far call to the same privilege level in compatibility
mode is very similar to one carried out in protected mode. The target operand
specifies an absolute far address either directly with a pointer (ptr16:16 or
ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The operand-size
attribute determines the size of the offset (16 or 32 bits) in the far address.
The new code segment selector and its descriptor are loaded into CS register
and the offset from the instruction is loaded into the EIP register. The difference
is that 64-bit mode may be entered. This specified by the L bit in the new code
segment descriptor.

Note that a 64-bit call gate (described in the next paragraph) can also be used
to perform a far call to a code segment at the same privilege level. However,
using this mechanism requires that the target code segment descriptor have the
L bit set, causing an entry to 64-bit mode.

When executing an inter-privilege-level far call, the code segment for the procedure
being called must be accessed through a 64-bit call gate. The segment selector
specified by the target operand identifies the call gate. The target operand
can specify the call gate segment selector either directly with a pointer (ptr16:16
or ptr16:32) or indirectly with a memory location (m16:16 or m16:32). The processor
obtains the segment selector for the new code segment and the new instruction
pointer (offset) from the 16-byte call gate descriptor. (The offset from the
target operand is ignored when a call gate is used.)

On inter-privilege-level calls, the processor switches to the stack for the
privilege level of the called procedure. The segment selector for the new stack
segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the
stack switch. (Note that when using a call gate to perform a far call to a segment
at the same privilege level, an implicit stack switch occurs as a result of
entering 64-bit mode. The SS selector is unchanged, but stack segment accesses
use a segment base of 0x0, the limit is ignored, and the default stack size
is 64-bits. The full value of RSP is used for the offset, of which the upper
32-bits are undefined.) On the new stack, the processor pushes the segment selector
and stack pointer for the calling procedure's stack and the segment selector
and instruction pointer for the calling procedure's code segment. (Parameter
copy is not supported in IA-32e mode.) Finally, the processor branches to the
address of the procedure being called within the new code segment.

Near/(Far) Calls in 64-bit Mode. When the processor is operating in 64-bit mode,
the CALL instruction can be used to perform the following types of far calls:

 - Far call to the same privilege level, transitioning to compatibility mode
 - Far call to the same privilege level, remaining in 64-bit mode
 - Far call to a different privilege level (inter-privilege level call), remaining
in 64-bit mode

Note that in this mode the CALL instruction can not be used to cause a task
switch in 64-bit mode since task switches are not supported in IA-32e mode.

In 64-bit mode, the processor always uses the segment selector part of the far
address to access the corresponding descriptor in the GDT or LDT. The descriptor
type (code segment, call gate) and access rights determine the type of call
operation to be performed.

If the selected descriptor is for a code segment, a far call to a code segment
at the same privilege level is performed. (If the selected code segment is at
a different privilege level and the code segment is non-conforming, a general-protection
exception is generated.) A far call to the same privilege level in 64-bit mode
is very similar to one carried out in compatibility mode. The target operand
specifies an absolute far address indirectly with a memory location (m16:16,
m16:32 or m16:64). The form of CALL with a direct specification of absolute
far address is not defined in 64-bit mode. The operand-size attribute determines
the size of the offset (16, 32, or 64 bits) in the far address. The new code
segment selector and its descriptor are loaded into the CS register; the offset
from the instruction is loaded into the EIP register. The new code segment may
specify entry either into compatibility or 64-bit mode, based on the L bit value.

A 64-bit call gate (described in the next paragraph) can also be used to perform
a far call to a code segment at the same privilege level. However, using this
mechanism requires that the target code segment descriptor have the L bit set.

When executing an inter-privilege-level far call, the code segment for the procedure
being called must be accessed through a 64-bit call gate. The segment selector
specified by the target operand identifies the call gate. The target operand
can only specify the call gate segment selector indirectly with a memory location
(m16:16, m16:32 or m16:64). The processor obtains the segment selector for the
new code segment and the new instruction pointer (offset) from the 16-byte call
gate descriptor. (The offset from the target operand is ignored when a call
gate is used.)

On inter-privilege-level calls, the processor switches to the stack for the
privilege level of the called procedure. The segment selector for the new stack
segment is set to NULL. The new stack pointer is specified in the TSS for the
currently running task. The branch to the new code segment occurs after the
stack switch.

Note that when using a call gate to perform a far call to a segment at the same
privilege level, an implicit stack switch occurs as a result of entering 64-bit
mode. The SS selector is unchanged, but stack segment accesses use a segment
base of 0x0, the limit is ignored, and the default stack size is 64-bits. (The
full value of RSP is used for the

offset.) On the new stack, the processor pushes the segment selector and stack
pointer for the calling procedure's stack and the segment selector and instruction
pointer for the calling procedure's code segment. (Parameter copy is not supported
in IA-32e mode.) Finally, the processor branches to the address of the procedure
being called within the new code segment.

Operation:

IF near call
  THEN IF near relative call
     THEN
       IF OperandSize = 64
          THEN
             tempDEST <- SignExtend(DEST); (* DEST is rel32 *)
             tempRIP <- RIP + tempDEST;
             IF stack not large enough for a 8-byte return address
               THEN #SS(0); FI;
             Push(RIP);
             RIP <- tempRIP;
       FI;
       IF OperandSize = 32
          THEN
             tempEIP <- EIP + DEST; (* DEST is rel32 *)
             IF tempEIP is not within code segment limit THEN #GP(0); FI;
             IF stack not large enough for a 4-byte return address
               THEN #SS(0); FI;
             Push(EIP);
             EIP <- tempEIP;
       FI;
       IF OperandSize = 16
          THEN
             tempEIP <- (EIP + DEST) AND 0000FFFFH; (* DEST is rel16 *)
             IF tempEIP is not within code segment limit THEN #GP(0); FI;
             IF stack not large enough for a 2-byte return address
               THEN #SS(0); FI;
             Push(IP);
             EIP <- tempEIP;
       FI;
     ELSE (* Near absolute call *)
       IF OperandSize = 64
          THEN
             tempRIP <- DEST; (* DEST is r/m64 *)
             IF stack not large enough for a 8-byte return address
               THEN #SS(0); FI;
             Push(RIP);
             RIP <- tempRIP;
       FI;
       IF OperandSize = 32
          THEN
             tempEIP <- DEST; (* DEST is r/m32 *)
             IF tempEIP is not within code segment limit THEN #GP(0); FI;
             IF stack not large enough for a 4-byte return address
               THEN #SS(0); FI;
             Push(EIP);
             EIP <- tempEIP;
       FI;
       IF OperandSize = 16
          THEN
             tempEIP <- DEST AND 0000FFFFH; (* DEST is r/m16 *)
             IF tempEIP is not within code segment limit THEN #GP(0); FI;
             IF stack not large enough for a 2-byte return address
               THEN #SS(0); FI;
             Push(IP);
             EIP <- tempEIP;
       FI;
  FI;rel/abs
FI; near
IF far call and (PE = 0 or (PE = 1 and VM = 1)) (* Real-address or virtual-8086 mode *)
  THEN
     IF OperandSize = 32
       THEN
          IF stack not large enough for a 6-byte return address
             THEN #SS(0); FI;
          IF DEST[31:16] is not zero THEN #GP(0); FI;
          Push(CS); (* Padded with 16 high-order bits *)
          Push(EIP);
          CS <- DEST[47:32]; (* DEST is ptr16:32 or [m16:32] *)
          EIP <- DEST[31:0]; (* DEST is ptr16:32 or [m16:32] *)
       ELSE (* OperandSize = 16 *)
          IF stack not large enough for a 4-byte return address
             THEN #SS(0); FI;
          Push(CS);
          Push(IP);
          CS <- DEST[31:16]; (* DEST is ptr16:16 or [m16:16] *)
          EIP <- DEST[15:0]; (* DEST is ptr16:16 or [m16:16]; clear upper 16 bits *)
     FI;
FI;
IF far call and (PE = 1 and VM = 0) (* Protected mode or IA-32e Mode, not virtual-8086 mode*)
  THEN
     IF segment selector in target operand NULL
       THEN #GP(0); FI;
     IF segment selector index not within descriptor table limits
       THEN #GP(new code segment selector); FI;
     Read type and access rights of selected segment descriptor;
     IF IA32_EFER.LMA = 0
       THEN
          IF segment type is not a conforming or nonconforming code segment, call
          gate, task gate, or TSS
             THEN #GP(segment selector); FI;
       ELSE
          IF segment type is not a conforming or nonconforming code segment or
          64-bit call gate,
             THEN #GP(segment selector); FI;
     FI;
     Depending on type and access rights:
       GO TO CONFORMING-CODE-SEGMENT;
       GO TO NONCONFORMING-CODE-SEGMENT;
       GO TO CALL-GATE;
       GO TO TASK-GATE;
       GO TO TASK-STATE-SEGMENT;
FI;
CONFORMING-CODE-SEGMENT:
  IF L bit = 1 and D bit = 1 and IA32_EFER.LMA = 1
     THEN GP(new code segment selector); FI;
  IF DPL > CPL
     THEN #GP(new code segment selector); FI;
  IF segment not present
     THEN #NP(new code segment selector); FI;
  IF stack not large enough for return address
     THEN #SS(0); FI;
  tempEIP <- DEST(Offset);
  IF OperandSize = 16
     THEN
       tempEIP <- tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
  IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
  segment limit)
     THEN #GP(0); FI;
  IF tempEIP is non-canonical
     THEN #GP(0); FI;
  IF OperandSize = 32
     THEN
       Push(CS); (* Padded with 16 high-order bits *)
       Push(EIP);
       CS <- DEST(CodeSegmentSelector);
       (* Segment descriptor information also loaded *)
       CS(RPL) <- CPL;
       EIP <- tempEIP;
     ELSE
       IF OperandSize = 16
          THEN
             Push(CS);
             Push(IP);
             CS <- DEST(CodeSegmentSelector);
             (* Segment descriptor information also loaded *)
             CS(RPL) <- CPL;
             EIP <- tempEIP;
          ELSE (* OperandSize = 64 *)
             Push(CS); (* Padded with 48 high-order bits *)
             Push(RIP);
             CS <- DEST(CodeSegmentSelector);
             (* Segment descriptor information also loaded *)
             CS(RPL) <- CPL;
             RIP <- tempEIP;
       FI;
  FI;
END;
NONCONFORMING-CODE-SEGMENT:
  IF L-Bit = 1 and D-BIT = 1 and IA32_EFER.LMA = 1
     THEN GP(new code segment selector); FI;
  IF (RPL > CPL) or (DPL != CPL)
     THEN #GP(new code segment selector); FI;
  IF segment not present
     THEN #NP(new code segment selector); FI;
  IF stack not large enough for return address
     THEN #SS(0); FI;
  tempEIP <- DEST(Offset);
  IF OperandSize = 16
     THEN tempEIP <- tempEIP AND 0000FFFFH; FI; (* Clear upper 16 bits *)
  IF (EFER.LMA = 0 or target mode = Compatibility mode) and (tempEIP outside new code
  segment limit)
     THEN #GP(0); FI;
  IF tempEIP is non-canonical
     THEN #GP(0); FI;
  IF OperandSize = 32
     THEN
       Push(CS); (* Padded with 16 high-order bits *)
       Push(EIP);
       CS <- DEST(CodeSegmentSelector);
       (* Segment descriptor information also loaded *)
       CS(RPL) <- CPL;
       EIP <- tempEIP;
     ELSE
       IF OperandSize = 16
          THEN
             Push(CS);
             Push(IP);
             CS <- DEST(CodeSegmentSelector);
             (* Segment descriptor information also loaded *)
             CS(RPL) <- CPL;
             EIP <- tempEIP;
          ELSE (* OperandSize = 64 *)
             Push(CS); (* Padded with 48 high-order bits *)
             Push(RIP);
             CS <- DEST(CodeSegmentSelector);
             (* Segment descriptor information also loaded *)
             CS(RPL) <- CPL;
             RIP <- tempEIP;
       FI;
  FI;
END;
CALL-GATE:
  IF call gate (DPL < CPL) or (RPL > DPL)
     THEN #GP(call-gate selector); FI;
  IF call gate not present
     THEN #NP(call-gate selector); FI;
  IF call-gate code-segment selector is NULL
     THEN #GP(0); FI;
  IF call-gate code-segment selector index is outside descriptor table limits
     THEN #GP(call-gate code-segment selector); FI;
  Read call-gate code-segment descriptor;
  IF call-gate code-segment descriptor does not indicate a code segment
  or call-gate code-segment descriptor DPL > CPL
     THEN #GP(call-gate code-segment selector); FI;
  IF IA32_EFER.LMA = 1 AND (call-gate code-segment descriptor is
  not a 64-bit code segment or call-gate code-segment descriptor has both L-bit and D-bit set)
     THEN #GP(call-gate code-segment selector); FI;
  IF call-gate code segment not present
     THEN #NP(call-gate code-segment selector); FI;
  IF call-gate code segment is non-conforming and DPL < CPL
     THEN go to MORE-PRIVILEGE;
     ELSE go to SAME-PRIVILEGE;
  FI;
END;
MORE-PRIVILEGE:
  IF current TSS is 32-bit
     THEN
       TSSstackAddress <- (new code-segment DPL * 8) + 4;
       IF (TSSstackAddress + 5) > current TSS limit
          THEN #TS(current TSS selector); FI;
       NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 4);
       NewESP <- 4 bytes loaded from (TSS base + TSSstackAddress);
     ELSE
       IF current TSS is 16-bit
          THEN
             TSSstackAddress <- (new code-segment DPL * 4) + 2
             IF (TSSstackAddress + 3) > current TSS limit
               THEN #TS(current TSS selector); FI;
             NewSS <- 2 bytes loaded from (TSS base + TSSstackAddress + 2);
             NewESP <- 2 bytes loaded from (TSS base + TSSstackAddress);
          ELSE (* current TSS is 64-bit *)
             TSSstackAddress <- (new code-segment DPL * 8) + 4;
             IF (TSSstackAddress + 7) > current TSS limit
               THEN #TS(current TSS selector); FI;
             NewSS <- new code-segment DPL; (* NULL selector with RPL = new CPL *)
             NewRSP <- 8 bytes loaded from (current TSS base + TSSstackAddress);
       FI;
  FI;
  IF IA32_EFER.LMA = 0 and NewSS is NULL
     THEN #TS(NewSS); FI;
  Read new code-segment descriptor and new stack-segment descriptor;
  IF IA32_EFER.LMA = 0 and (NewSS RPL != new code-segment DPL
  or new stack-segment DPL != new code-segment DPL or new stack segment is not a
  writable data segment)
     THEN #TS(NewSS); FI
  IF IA32_EFER.LMA = 0 and new stack segment not present
     THEN #SS(NewSS); FI;
  IF CallGateSize = 32
     THEN
       IF new stack does not have room for parameters plus 16 bytes
          THEN #SS(NewSS); FI;
       IF CallGate(InstructionPointer) not within new code-segment limit
          THEN #GP(0); FI;
       SS <- newSS; (* Segment descriptor information also loaded *)
       ESP <- newESP;
       CS:EIP <- CallGate(CS:InstructionPointer);
       (* Segment descriptor information also loaded *)
       Push(oldSS:oldESP); (* From calling procedure *)
       temp <- parameter count from call gate, masked to 5 bits;
       Push(parameters from calling procedure's stack, temp)
       Push(oldCS:oldEIP); (* Return address to calling procedure *)
     ELSE
       IF CallGateSize = 16
          THEN
             IF new stack does not have room for parameters plus 8 bytes
               THEN #SS(NewSS); FI;
             IF (CallGate(InstructionPointer) AND FFFFH) not in new code-segment limit
               THEN #GP(0); FI;
             SS <- newSS; (* Segment descriptor information also loaded *)
             ESP <- newESP;
             CS:IP <- CallGate(CS:InstructionPointer);
             (* Segment descriptor information also loaded *)
             Push(oldSS:oldESP); (* From calling procedure *)
             temp <- parameter count from call gate, masked to 5 bits;
             Push(parameters from calling procedure's stack, temp)
             Push(oldCS:oldEIP); (* Return address to calling procedure *)
          ELSE (* CallGateSize = 64 *)
             IF pushing 32 bytes on the stack would use a non-canonical address
               THEN #SS(NewSS); FI;
             IF (CallGate(InstructionPointer) is non-canonical)
               THEN #GP(0); FI;
             SS <- NewSS; (* NewSS is NULL)
             RSP <- NewESP;
             CS:IP <- CallGate(CS:InstructionPointer);
             (* Segment descriptor information also loaded *)
             Push(oldSS:oldESP); (* From calling procedure *)
             Push(oldCS:oldEIP); (* Return address to calling procedure *)
       FI;
  FI;
  CPL <- CodeSegment(DPL)
  CS(RPL) <- CPL
END;
SAME-PRIVILEGE:
  IF CallGateSize = 32
     THEN
       IF stack does not have room for 8 bytes
          THEN #SS(0); FI;
       IF CallGate(InstructionPointer) not within code segment limit
          THEN #GP(0); FI;
       CS:EIP <- CallGate(CS:EIP) (* Segment descriptor information also loaded *)
       Push(oldCS:oldEIP); (* Return address to calling procedure *)
     ELSE
       If CallGateSize = 16
          THEN
             IF stack does not have room for 4 bytes
               THEN #SS(0); FI;
             IF CallGate(InstructionPointer) not within code segment limit
               THEN #GP(0); FI;
             CS:IP <- CallGate(CS:instruction pointer);
             (* Segment descriptor information also loaded *)
             Push(oldCS:oldIP); (* Return address to calling procedure *)
          ELSE (* CallGateSize = 64)
             IF pushing 16 bytes on the stack touches non-canonical addresses
               THEN #SS(0); FI;
             IF RIP non-canonical
               THEN #GP(0); FI;
             CS:IP <- CallGate(CS:instruction pointer);
             (* Segment descriptor information also loaded *)
             Push(oldCS:oldIP); (* Return address to calling procedure *)
       FI;
  FI;
  CS(RPL) <- CPL
END;
TASK-GATE:
  IF task gate DPL < CPL or RPL
     THEN #GP(task gate selector); FI;
  IF task gate not present
     THEN #NP(task gate selector); FI;
  Read the TSS segment selector in the task-gate descriptor;
  IF TSS segment selector local/global bit is set to local
  or index not within GDT limits
     THEN #GP(TSS selector); FI;
  Access TSS descriptor in GDT;
  IF TSS descriptor specifies that the TSS is busy (low-order 5 bits set to 00001)
     THEN #GP(TSS selector); FI;
  IF TSS not present
     THEN #NP(TSS selector); FI;
  SWITCH-TASKS (with nesting) to TSS;
  IF EIP not within code segment limit
     THEN #GP(0); FI;
END;
TASK-STATE-SEGMENT:
  IF TSS DPL < CPL or RPL
  or TSS descriptor indicates TSS not available
     THEN #GP(TSS selector); FI;
  IF TSS is not present
     THEN #NP(TSS selector); FI;
  SWITCH-TASKS (with nesting) to TSS;
  IF EIP not within code segment limit
     THEN #GP(0); FI;
END;

Flags Affected:
All flags are affected if a task switch occurs; no flags are affected if a task
switch does not occur.


Protected Mode Exceptions:
| #GP(0)| If the target offset in destination   
|       | operand is beyond the new code segment
|       | limit. If the segment selector in the 
|       | destination operand is NULL. If the   
|       | code segment selector in the gate is  
|       | NULL.                                 
If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment
limit. If the DS, ES, FS, or GS register is used to access memory and it contains
a NULL segment selector.

| #GP(selector)  | If a code segment or gate or TSS selector   
|                | index is outside descriptor table limits.   
|                | If the segment descriptor pointed to        
|                | by the segment selector in the destination  
|                | operand is not for a conforming-code        
|                | segment, nonconforming-code segment,        
|                | call gate, task gate, or task state         
|                | segment. If the DPL for a nonconforming-code
|                | segment is not equal to the CPL or the      
|                | RPL for the segment's segment selector      
|                | is greater than the CPL. If the DPL         
|                | for a conforming-code segment is greater    
|                | than the CPL. If the DPL from a call-gate,  
|                | task-gate, or TSS segment descriptor        
|                | is less than the CPL or than the RPL        
|                | of the call-gate, task-gate, or TSS's       
|                | segment selector. If the segment descriptor 
|                | for a segment selector from a call gate     
|                | does not indicate it is a code segment.     
|                | If the segment selector from a call         
|                | gate is beyond the descriptor table         
|                | limits. If the DPL for a code-segment       
|                | obtained from a call gate is greater        
|                | than the CPL. If the segment selector       
|                | for a TSS has its local/global bit set      
|                | for local. If a TSS segment descriptor      
|                | specifies that the TSS is busy or not       
|                | available.                                  
| #SS(0)         | If pushing the return address, parameters,  
|                | or stack segment pointer onto the stack     
|                | exceeds the bounds of the stack segment,    
|                | when no stack switch occurs. If a memory    
|                | operand effective address is outside        
|                | the SS segment limit.                       
| #SS(selector)  | If pushing the return address, parameters,  
|                | or stack segment pointer onto the stack     
|                | exceeds the bounds of the stack segment,    
|                | when a stack switch occurs. If the SS       
|                | register is being loaded as part of         
|                | a stack switch and the segment pointed      
|                | to is marked not present. If stack segment  
|                | does not have room for the return address,  
|                | parameters, or stack segment pointer,       
|                | when stack switch occurs.                   
| #NP(selector)  | If a code segment, data segment, stack      
|                | segment, call gate, task gate, or TSS       
|                | is not present.                             
| #TS(selector)  | If the new stack segment selector and       
|                | ESP are beyond the end of the TSS. If       
|                | the new stack segment selector is NULL.     
|                | If the RPL of the new stack segment         
|                | selector in the TSS is not equal to         
|                | the DPL of the code segment being accessed. 
|                | If DPL of the stack segment descriptor      
|                | for the new stack segment is not equal      
|                | to the DPL of the code segment descriptor.  
|                | If the new stack segment is not a writable  
|                | data segment. If segment-selector index     
|                | for stack segment is outside descriptor     
|                | table limits.                               
| #PF(fault-code)| If a page fault occurs.                     
| #AC(0)         | If alignment checking is enabled and        
|                | an unaligned memory reference is made       
|                | while the current privilege level is        
|                | 3.                                          
| #UD            | If the LOCK prefix is used.                 

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit. If the target offset  
|    | is beyond the code segment limit.    
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit. If the target offset   
|                | is beyond the code segment limit.     
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.

| #GP(selector)| If a memory address accessed by the    
|              | selector is in non-canonical space.    
| #GP(0)       | If the target offset in the destination
|              | operand is non-canonical.              

64-Bit Mode Exceptions:
| #GP(0)         | If a memory address is non-canonical.      
|                | If target offset in destination operand    
|                | is non-canonical. If the segment selector  
|                | in the destination operand is NULL.        
|                | If the code segment selector in the        
|                | 64-bit gate is NULL.                       
| #GP(selector)  | If code segment or 64-bit call gate        
|                | is outside descriptor table limits.        
|                | If code segment or 64-bit call gate        
|                | overlaps non-canonical space. If the       
|                | segment descriptor pointed to by the       
|                | segment selector in the destination        
|                | operand is not for a conforming-code       
|                | segment, nonconforming-code segment,       
|                | or 64-bit call gate. If the segment        
|                | descriptor pointed to by the segment       
|                | selector in the destination operand        
|                | is a code segment and has both the D-bit   
|                | and the L- bit set. If the DPL for a       
|                | nonconforming-code segment is not equal    
|                | to the CPL, or the RPL for the segment's   
|                | segment selector is greater than the       
|                | CPL. If the DPL for a conforming-code      
|                | segment is greater than the CPL. If        
|                | the DPL from a 64-bit call-gate is less    
|                | than the CPL or than the RPL of the        
|                | 64-bit call-gate. If the upper type        
|                | field of a 64-bit call gate is not 0x0.    
|                | If the segment selector from a 64-bit      
|                | call gate is beyond the descriptor table   
|                | limits. If the DPL for a code-segment      
|                | obtained from a 64-bit call gate is        
|                | greater than the CPL. If the code segment  
|                | descriptor pointed to by the selector      
|                | in the 64-bit gate doesn't have the        
|                | L-bit set and the D-bit clear. If the      
|                | segment descriptor for a segment selector  
|                | from the 64-bit call gate does not indicate
|                | it is a code segment.                      
| #SS(0)         | If pushing the return offset or CS selector
|                | onto the stack exceeds the bounds of       
|                | the stack segment when no stack switch     
|                | occurs. If a memory operand effective      
|                | address is outside the SS segment limit.   
|                | If the stack address is in a non-canonical 
|                | form.                                      
| #SS(selector)  | If pushing the old values of SS selector,  
|                | stack pointer, EFLAGS, CS selector,        
|                | offset, or error code onto the stack       
|                | violates the canonical boundary when       
|                | a stack switch occurs.                     
| #NP(selector)  | If a code segment or 64-bit call gate      
|                | is not present.                            
| #TS(selector)  | If the load of the new RSP exceeds the     
|                | limit of the TSS.                          
| #UD            | (64-bit mode only) If a far call is        
|                | direct to an absolute address in memory.   
|                | If the LOCK prefix is used.                
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: CBW
description:
CBW/CWDE/CDQE - Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to Quadword:
| Opcode    | Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description              
| 98        | CBW        | NP   | Valid      | Valid          | AX ← sign-extend of AL.  
| 98        | CWDE       | NP   | Valid      | Valid          | EAX ← sign-extend of AX. 
| REX.W + 98| CDQE       | NP   | Valid      | N.E.           | RAX ← sign-extend of EAX.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Double the size of the source operand by means of sign extension. The CBW (convert
byte to word) instruction copies the sign (bit 7) in the source operand into
every bit in the AH register. The CWDE (convert word to doubleword) instruction
copies the sign (bit 15) of the word in the AX register into the high 16 bits
of the EAX register.

CBW and CWDE reference the same opcode. The CBW instruction is intended for
use when the operand-size attribute is 16; CWDE is intended for use when the
operand-size attribute is 32. Some assemblers may force the operand size. Others
may treat these two mnemonics as synonyms (CBW/CWDE) and use the setting of
the operand-size attribute to determine the size of values to be converted.

In 64-bit mode, the default operation size is the size of the destination register.
Use of the REX.W prefix promotes this instruction (CDQE when promoted) to operate
on 64-bit operands. In which case, CDQE copies the sign (bit 31) of the doubleword
in the EAX register into the high 32 bits of RAX.

Operation:

IF OperandSize = 16 (* Instruction = CBW *)
  THEN
     AX <- SignExtend(AL);
  ELSE IF (OperandSize = 32, Instruction = CWDE)
     EAX <- SignExtend(AX); FI;
  ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)
     RAX <- SignExtend(EAX);
FI;

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: CLC
description:
CLC - Clear Carry Flag:
| Opcode| Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description   
| F8    | CLC        | NP   | Valid      | Valid          | Clear CF flag.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Clears the CF flag in the EFLAGS register. Operation is the same in all non-64-bit
modes and 64-bit mode.

Operation:

CF <- 0;

Flags Affected:
The CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: CLD
description:
CLD - Clear Direction Flag:
| Opcode| Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description   
| FC    | CLD        | NP   | Valid      | Valid          | Clear DF flag.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Clears the DF flag in the EFLAGS register. When the DF flag is set to 0, string
operations increment the index registers (ESI and/or EDI). Operation is the
same in all non-64-bit modes and 64-bit mode.

Operation:

DF <- 0;

Flags Affected:
The DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: CLFLUSH
description:
CLFLUSH - Flush Cache Line:
| Opcode  | Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description                      
| 0F AE /7| CLFLUSH m8 | M    | Valid      | Valid          | Flushes cache line containing m8.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Invalidates the cache line that contains the linear address specified with the
source operand from all levels of the processor cache hierarchy (data and instruction).
The invalidation is broadcast throughout the cache coherence domain. If, at
any level of the cache hierarchy, the line is inconsistent with memory (dirty)
it is written to memory before invalidation. The source operand is a byte memory
location.

The availability of CLFLUSH is indicated by the presence of the CPUID feature
flag CLFSH (bit 19 of the EDX register, see “CPUID - CPU Identification” in this
chapter). The aligned cache line size affected is also indicated with the CPUID
instruction (bits 8 through 15 of the EBX register when the initial value in
the EAX register is 1).

The memory attribute of the page containing the affected line has no effect
on the behavior of this instruction. It should be noted that processors are
free to speculatively fetch and cache data from system memory regions assigned
a memory-type allowing for speculative reads (such as, the WB, WC, and WT memory
types). PREFETCHh instructions can be used to provide the processor with hints
for this speculative behavior. Because this speculative fetching can occur at
any time and is not tied to instruction execution, the CLFLUSH instruction is
not ordered with respect to PREFETCHh instructions or any of the speculative
fetching mechanisms (that is, data can be speculatively loaded into a cache
line just before, during, or after the execution of a CLFLUSH instruction that
references the cache line).

CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed to be
ordered by any other fencing or serializing instructions or by another CLFLUSH
instruction. For example, software can use an MFENCE instruction to ensure that
previous stores are included in the write-back.

The CLFLUSH instruction can be used at all privilege levels and is subject to
all permission checking and faults associated with a byte load (and in addition,
a CLFLUSH instruction is allowed to flush a linear address in an executeonly
segment). Like a load, the CLFLUSH instruction sets the A bit but not the D
bit in the page tables. The CLFLUSH instruction was introduced with the SSE2
extensions; however, because it has its own CPUID feature flag, it can be implemented
in IA-32 processors that do not include the SSE2 extensions. Also, detecting
the presence of the SSE2 extensions with the CPUID instruction does not guarantee
that the CLFLUSH instruction is implemented in the processor.

CLFLUSH operation is the same in non-64-bit modes and 64-bit mode.

Operation:

Flush_Cache_Line(SRC);

Intel C/C++ Compiler Intrinsic Equivalents:
| CLFLUSH:| void _mm_clflush(void const *p)

Protected Mode Exceptions:
| #GP(0)         | For an illegal memory operand effective  
|                | address in the CS, DS, ES, FS or GS      
|                | segments.                                
| #SS(0)         | For an illegal address in the SS segment.
| #PF(fault-code)| For a page fault.                        
| #UD            | If CPUID.01H:EDX.CLFSH[bit 19] = 0.      
|                | If the LOCK prefix is used.              
If instruction prefix is 66H, F2H or F3H.


Real-Address Mode Exceptions:
| #GP| If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #UD| If CPUID.01H:EDX.CLFSH[bit 19] = 0.       
|    | If the LOCK prefix is used. If instruction
|    | prefix is 66H, F2H or F3H.                

Virtual-8086 Mode Exceptions:
Same exceptions as in real address mode.

| #PF(fault-code)| For a page fault.

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| For a page fault.                          
| #UD            | If CPUID.01H:EDX.CLFSH[bit 19] = 0.        
|                | If the LOCK prefix is used. If instruction 
|                | prefix is 66H, F2H or F3H.                 


platform: x86
mnem: CLI
description:
CLI  -  Clear Interrupt Flag:
| Opcode| Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description                              
| FA    | CLI        | NP   | Valid      | Valid          | Clear interrupt flag; interrupts disabled
|       |            |      |            |                | when interrupt flag cleared.             

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
If protected-mode virtual interrupts are not enabled, CLI clears the IF flag
in the EFLAGS register. No other flags are affected. Clearing the IF flag causes
the processor to ignore maskable external interrupts. The IF flag and the CLI
and STI instruction have no affect on the generation of exceptions and NMI interrupts.

When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less
than 3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected.
Table 3-6 indicates the action of the CLI instruction depending on the processor
operating mode and the CPL/IOPL of the running program or procedure.

CLI operation is the same in non-64-bit modes and 64-bit mode.


Table 3-6. Decision Table for CLI Results:
| PE| VM| IOPL | CPL| PVI| VIP| VME| CLI Result
| 0 | X | X    | X  | X  | X  | X  | IF = 0    
| 1 | 0 | ≥ CPL| X  | X  | X  | X  | IF = 0    
| 1 | 0 | < CPL| 3  | 1  | X  | X  | VIF = 0   
| 1 | 0 | < CPL| < 3| X  | X  | X  | GP Fault  
| 1 | 0 | < CPL| X  | 0  | X  | X  | GP Fault  
| 1 | 1 | 3    | X  | X  | X  | X  | IF = 0    
| 1 | 1 | < 3  | X  | X  | X  | 1  | VIF = 0   
| 1 | 1 | < 3  | X  | X  | X  | 0  | GP Fault  
Notes: * X = This setting has no impact.

Operation:

IF PE = 0
  THEN
     IF <- 0; (* Reset Interrupt Flag *)
  ELSE
     IF VM = 0;
       THEN
          IF IOPL ≥ CPL
             THEN
               IF <- 0; (* Reset Interrupt Flag *)
          ELSE
             IF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))
               THEN
                  VIF <- 0; (* Reset Virtual Interrupt Flag *)
               ELSE
                  #GP(0);
             FI;
          FI;
       ELSE (* VM = 1 *)
          IF IOPL = 3
             THEN
               IF <- 0; (* Reset Interrupt Flag *)
             ELSE
               IF (IOPL < 3) AND (VME = 1)
                  THEN
                     VIF <- 0; (* Reset Virtual Interrupt Flag *)
                  ELSE
                     #GP(0);
               FI;
          FI;
     FI;
FI;

Flags Affected:
If protected-mode virtual interrupts are not enabled, IF is set to 0 if the
CPL is equal to or less than the IOPL; otherwise, it is not affected. The other
flags in the EFLAGS register are unaffected.

When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less
than 3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected.


Protected Mode Exceptions:
| #GP(0)| If the CPL is greater (has less privilege)
|       | than the IOPL of the current program      
|       | or procedure.                             
| #UD   | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)| If the CPL is greater (has less privilege)
|       | than the IOPL of the current program      
|       | or procedure.                             
| #UD   | If the LOCK prefix is used.               

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)| If the CPL is greater (has less privilege)
|       | than the IOPL of the current program      
|       | or procedure.                             
| #UD   | If the LOCK prefix is used.               


platform: x86
mnem: CLTS
description:
CLTS - Clear Task-Switched Flag in CR0:
| Opcode| Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description           
| 0F 06 | CLTS       | NP   | Valid      | Valid          | Clears TS flag in CR0.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Clears the task-switched (TS) flag in the CR0 register. This instruction is
intended for use in operating-system procedures. It is a privileged instruction
that can only be executed at a CPL of 0. It is allowed to be executed in realaddress
mode to allow initialization for protected mode.

The processor sets the TS flag every time a task switch occurs. The flag is
used to synchronize the saving of FPU context in multitasking applications.
See the description of the TS flag in the section titled “Control Registers”
in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A, for more information about this flag.

CLTS operation is the same in non-64-bit modes and 64-bit mode.

See Chapter 25, “VMX Non-Root Operation,” of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3C, for more information about the behavior
of this instruction in VMX non-root operation.

Operation:

CR0.TS[bit 3] <- 0;

Flags Affected:
The TS flag in CR0 register is cleared.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not
|       | 0.                                   
| #UD   | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)| CLTS is not recognized in virtual-8086
|       | mode.                                 
| #UD   | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)| If the CPL is greater than 0.
| #UD   | If the LOCK prefix is used.  


platform: x86
mnem: CMC
description:
CMC - Complement Carry Flag:
| Opcode| Instruction| Op/En| 64-bit Mode| Compat/Leg Mode| Description        
| F5    | CMC        | NP   | Valid      | Valid          | Complement CF flag.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Complements the CF flag in the EFLAGS register. CMC operation is the same in
non-64-bit modes and 64-bit mode.

Operation:

EFLAGS.CF[bit 0]<- NOT EFLAGS.CF[bit 0];

Flags Affected:
The CF flag contains the complement of its original value. The OF, ZF, SF, AF,
and PF flags are unaffected.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: CMOVcc
description:
CMOVcc - Conditional Move:
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 47 /r        | CMOVA r16, r/m16  | RM   | Valid      | Valid          | Move if above (CF=0 and ZF=0).         
| 0F 47 /r        | CMOVA r32, r/m32  | RM   | Valid      | Valid          | Move if above (CF=0 and ZF=0).         
| REX.W + 0F 47 /r| CMOVA r64, r/m64  | RM   | Valid      | N.E.           | Move if above (CF=0 and ZF=0).         
| 0F 43 /r        | CMOVAE r16, r/m16 | RM   | Valid      | Valid          | Move if above or equal (CF=0).         
| 0F 43 /r        | CMOVAE r32, r/m32 | RM   | Valid      | Valid          | Move if above or equal (CF=0).         
| REX.W + 0F 43 /r| CMOVAE r64, r/m64 | RM   | Valid      | N.E.           | Move if above or equal (CF=0).         
| 0F 42 /r        | CMOVB r16, r/m16  | RM   | Valid      | Valid          | Move if below (CF=1).                  
| 0F 42 /r        | CMOVB r32, r/m32  | RM   | Valid      | Valid          | Move if below (CF=1).                  
| REX.W + 0F 42 /r| CMOVB r64, r/m64  | RM   | Valid      | N.E.           | Move if below (CF=1).                  
| 0F 46 /r        | CMOVBE r16, r/m16 | RM   | Valid      | Valid          | Move if below or equal (CF=1 or ZF=1). 
| 0F 46 /r        | CMOVBE r32, r/m32 | RM   | Valid      | Valid          | Move if below or equal (CF=1 or ZF=1). 
| REX.W + 0F 46 /r| CMOVBE r64, r/m64 | RM   | Valid      | N.E.           | Move if below or equal (CF=1 or ZF=1). 
| 0F 42 /r        | CMOVC r16, r/m16  | RM   | Valid      | Valid          | Move if carry (CF=1).                  
| 0F 42 /r        | CMOVC r32, r/m32  | RM   | Valid      | Valid          | Move if carry (CF=1).                  
| REX.W + 0F 42 /r| CMOVC r64, r/m64  | RM   | Valid      | N.E.           | Move if carry (CF=1).                  
| 0F 44 /r        | CMOVE r16, r/m16  | RM   | Valid      | Valid          | Move if equal (ZF=1).                  
| 0F 44 /r        | CMOVE r32, r/m32  | RM   | Valid      | Valid          | Move if equal (ZF=1).                  
| REX.W + 0F 44 /r| CMOVE r64, r/m64  | RM   | Valid      | N.E.           | Move if equal (ZF=1).                  
| 0F 4F /r        | CMOVG r16, r/m16  | RM   | Valid      | Valid          | Move if greater (ZF=0 and SF=OF).      
| 0F 4F /r        | CMOVG r32, r/m32  | RM   | Valid      | Valid          | Move if greater (ZF=0 and SF=OF).      
| REX.W + 0F 4F /r| CMOVG r64, r/m64  | RM   | V/N.E.     | NA             | Move if greater (ZF=0 and SF=OF).      
| 0F 4D /r        | CMOVGE r16, r/m16 | RM   | Valid      | Valid          | Move if greater or equal (SF=OF).      
| 0F 4D /r        | CMOVGE r32, r/m32 | RM   | Valid      | Valid          | Move if greater or equal (SF=OF).      
| REX.W + 0F 4D /r| CMOVGE r64, r/m64 | RM   | Valid      | N.E.           | Move if greater or equal (SF=OF).      
| 0F 4C /r        | CMOVL r16, r/m16  | RM   | Valid      | Valid          | Move if less (SF!= OF).                 
| 0F 4C /r        | CMOVL r32, r/m32  | RM   | Valid      | Valid          | Move if less (SF!= OF).                 
| REX.W + 0F 4C /r| CMOVL r64, r/m64  | RM   | Valid      | N.E.           | Move if less (SF!= OF).                 
| 0F 4E /r        | CMOVLE r16, r/m16 | RM   | Valid      | Valid          | Move if less or equal (ZF=1 or SF!= OF).
| 0F 4E /r        | CMOVLE r32, r/m32 | RM   | Valid      | Valid          | Move if less or equal (ZF=1 or SF!= OF).
| REX.W + 0F 4E /r| CMOVLE r64, r/m64 | RM   | Valid      | N.E.           | Move if less or equal (ZF=1 or SF!= OF).
| 0F 46 /r        | CMOVNA r16, r/m16 | RM   | Valid      | Valid          | Move if not above (CF=1 or ZF=1).      
| 0F 46 /r        | CMOVNA r32, r/m32 | RM   | Valid      | Valid          | Move if not above (CF=1 or ZF=1).      
| REX.W + 0F 46 /r| CMOVNA r64, r/m64 | RM   | Valid      | N.E.           | Move if not above (CF=1 or ZF=1).      
| 0F 42 /r        | CMOVNAE r16, r/m16| RM   | Valid      | Valid          | Move if not above or equal (CF=1).     
| 0F 42 /r        | CMOVNAE r32, r/m32| RM   | Valid      | Valid          | Move if not above or equal (CF=1).     
| REX.W + 0F 42 /r| CMOVNAE r64, r/m64| RM   | Valid      | N.E.           | Move if not above or equal (CF=1).     
| 0F 43 /r        | CMOVNB r16, r/m16 | RM   | Valid      | Valid          | Move if not below (CF=0).              
| 0F 43 /r        | CMOVNB r32, r/m32 | RM   | Valid      | Valid          | Move if not below (CF=0).              
| REX.W + 0F 43 /r| CMOVNB r64, r/m64 | RM   | Valid      | N.E.           | Move if not below (CF=0).              
| 0F 47 /r        | CMOVNBE r16, r/m16| RM   | Valid      | Valid          | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 47 /r        | CMOVNBE r32, r/m32| RM   | Valid      | Valid          | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| REX.W + 0F 47 /r| CMOVNBE r64, r/m64| RM   | Valid      | N.E.           | Move if not below or equal (CF=0 and   
|                 |                   |      |            |                | ZF=0).                                 
| 0F 43 /r        | CMOVNC r16, r/m16 | RM   | Valid      | Valid          | Move if not carry (CF=0).              
| 0F 43 /r        | CMOVNC r32, r/m32 | RM   | Valid      | Valid          | Move if not carry (CF=0).              
| REX.W + 0F 43 /r| CMOVNC r64, r/m64 | RM   | Valid      | N.E.           | Move if not carry (CF=0).              
| 0F 45 /r        | CMOVNE r16, r/m16 | RM   | Valid      | Valid          | Move if not equal (ZF=0).              
| 0F 45 /r        | CMOVNE r32, r/m32 | RM   | Valid      | Valid          | Move if not equal (ZF=0).              
| REX.W + 0F 45 /r| CMOVNE r64, r/m64 | RM   | Valid      | N.E.           | Move if not equal (ZF=0).              
| 0F 4E /r        | CMOVNG r16, r/m16 | RM   | Valid      | Valid          | Move if not greater (ZF=1 or SF!= OF).  
| 0F 4E /r        | CMOVNG r32, r/m32 | RM   | Valid      | Valid          | Move if not greater (ZF=1 or SF!= OF).  
| REX.W + 0F 4E /r| CMOVNG r64, r/m64 | RM   | Valid      | N.E.           | Move if not greater (ZF=1 or SF!= OF).  
| 0F 4C /r        | CMOVNGE r16, r/m16| RM   | Valid      | Valid          | Move if not greater or equal (SF!= OF). 
| 0F 4C /r        | CMOVNGE r32, r/m32| RM   | Valid      | Valid          | Move if not greater or equal (SF!= OF). 
| REX.W + 0F 4C /r| CMOVNGE r64, r/m64| RM   | Valid      | N.E.           | Move if not greater or equal (SF!= OF). 
| 0F 4D /r        | CMOVNL r16, r/m16 | RM   | Valid      | Valid          | Move if not less (SF=OF).              
| 0F 4D /r        | CMOVNL r32, r/m32 | RM   | Valid      | Valid          | Move if not less (SF=OF).              
| REX.W + 0F 4D /r| CMOVNL r64, r/m64 | RM   | Valid      | N.E.           | Move if not less (SF=OF).              
| 0F 4F /r        | CMOVNLE r16, r/m16| RM   | Valid      | Valid          | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| 0F 4F /r        | CMOVNLE r32, r/m32| RM   | Valid      | Valid          | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| REX.W + 0F 4F /r| CMOVNLE r64, r/m64| RM   | Valid      | N.E.           | Move if not less or equal (ZF=0 and    
|                 |                   |      |            |                | SF=OF).                                
| 0F 41 /r        | CMOVNO r16, r/m16 | RM   | Valid      | Valid          | Move if not overflow (OF=0).           
| 0F 41 /r        | CMOVNO r32, r/m32 | RM   | Valid      | Valid          | Move if not overflow (OF=0).           
| REX.W + 0F 41 /r| CMOVNO r64, r/m64 | RM   | Valid      | N.E.           | Move if not overflow (OF=0).           
| 0F 4B /r        | CMOVNP r16, r/m16 | RM   | Valid      | Valid          | Move if not parity (PF=0).             
| 0F 4B /r        | CMOVNP r32, r/m32 | RM   | Valid      | Valid          | Move if not parity (PF=0).             
| REX.W + 0F 4B /r| CMOVNP r64, r/m64 | RM   | Valid      | N.E.           | Move if not parity (PF=0).             
| 0F 49 /r        | CMOVNS r16, r/m16 | RM   | Valid      | Valid          | Move if not sign (SF=0).               
| 0F 49 /r        | CMOVNS r32, r/m32 | RM   | Valid      | Valid          | Move if not sign (SF=0).               
| REX.W + 0F 49 /r| CMOVNS r64, r/m64 | RM   | Valid      | N.E.           | Move if not sign (SF=0).               
| 0F 45 /r        | CMOVNZ r16, r/m16 | RM   | Valid      | Valid          | Move if not zero (ZF=0).               
| 0F 45 /r        | CMOVNZ r32, r/m32 | RM   | Valid      | Valid          | Move if not zero (ZF=0).               
| REX.W + 0F 45 /r| CMOVNZ r64, r/m64 | RM   | Valid      | N.E.           | Move if not zero (ZF=0).               
| 0F 40 /r        | CMOVO r16, r/m16  | RM   | Valid      | Valid          | Move if overflow (OF=1).               
| 0F 40 /r        | CMOVO r32, r/m32  | RM   | Valid      | Valid          | Move if overflow (OF=1).               
| REX.W + 0F 40 /r| CMOVO r64, r/m64  | RM   | Valid      | N.E.           | Move if overflow (OF=1).               
| 0F 4A /r        | CMOVP r16, r/m16  | RM   | Valid      | Valid          | Move if parity (PF=1).                 
| 0F 4A /r        | CMOVP r32, r/m32  | RM   | Valid      | Valid          | Move if parity (PF=1).                 
| REX.W + 0F 4A /r| CMOVP r64, r/m64  | RM   | Valid      | N.E.           | Move if parity (PF=1).                 
| 0F 4A /r        | CMOVPE r16, r/m16 | RM   | Valid      | Valid          | Move if parity even (PF=1).            
| 0F 4A /r        | CMOVPE r32, r/m32 | RM   | Valid      | Valid          | Move if parity even (PF=1).            
| REX.W + 0F 4A /r| CMOVPE r64, r/m64 | RM   | Valid      | N.E.           | Move if parity even (PF=1).            
| Opcode          | Instruction       | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 4B /r        | CMOVPO r16, r/m16 | RM   | Valid      | Valid          | Move if parity odd (PF=0).             
| 0F 4B /r        | CMOVPO r32, r/m32 | RM   | Valid      | Valid          | Move if parity odd (PF=0).             
| REX.W + 0F 4B /r| CMOVPO r64, r/m64 | RM   | Valid      | N.E.           | Move if parity odd (PF=0).             
| 0F 48 /r        | CMOVS r16, r/m16  | RM   | Valid      | Valid          | Move if sign (SF=1).                   
| 0F 48 /r        | CMOVS r32, r/m32  | RM   | Valid      | Valid          | Move if sign (SF=1).                   
| REX.W + 0F 48 /r| CMOVS r64, r/m64  | RM   | Valid      | N.E.           | Move if sign (SF=1).                   
| 0F 44 /r        | CMOVZ r16, r/m16  | RM   | Valid      | Valid          | Move if zero (ZF=1).                   
| 0F 44 /r        | CMOVZ r32, r/m32  | RM   | Valid      | Valid          | Move if zero (ZF=1).                   
| REX.W + 0F 44 /r| CMOVZ r64, r/m64  | RM   | Valid      | N.E.           | Move if zero (ZF=1).                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       

Description:
The CMOVcc instructions check the state of one or more of the status flags in
the EFLAGS register (CF, OF, PF, SF, and ZF) and perform a move operation if
the flags are in a specified state (or condition). A condition code (cc) is
associated with each instruction to indicate the condition being tested for.
If the condition is not satisfied, a move is not performed and execution continues
with the instruction following the CMOVcc instruction.

These instructions can move 16-bit, 32-bit or 64-bit values from memory to a
general-purpose register or from one general-purpose register to another. Conditional
moves of 8-bit register operands are not supported.

The condition for each CMOVcc mnemonic is given in the description column of
the above table. The terms “less”and “greater” are used for comparisons of signed
integers and the terms “above” and “below” are used for unsigned integers.

Because a particular state of the status flags can sometimes be interpreted
in two ways, two mnemonics are defined for some opcodes. For example, the CMOVA
(conditional move if above) instruction and the CMOVNBE (conditional move if
not below or equal) instruction are alternate mnemonics for the opcode 0F 47H.

The CMOVcc instructions were introduced in P6 family processors; however, these
instructions may not be supported by all IA-32 processors. Software can determine
if the CMOVcc instructions are supported by checking the processor's feature
information with the CPUID instruction (see “CPUID - CPU Identification” in this
chapter).

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning
of this section for encoding data and limits.

Operation:

temp <- SRC
IF condition TRUE
  THEN
     DEST <- temp;
  FI;
ELSE
  IF (OperandSize = 32 and IA-32e mode active)
     THEN
       DEST[63:32] <- 0;
  FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: CMP
description:
CMP - Compare Two Operands:
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 3C ib           | CMP AL, imm8    | I    | Valid      | Valid          | Compare imm8 with AL.                 
| 3D iw           | CMP AX, imm16   | I    | Valid      | Valid          | Compare imm16 with AX.                
| 3D id           | CMP EAX, imm32  | I    | Valid      | Valid          | Compare imm32 with EAX.               
| REX.W + 3D id   | CMP RAX, imm32  | I    | Valid      | N.E.           | Compare imm32 sign-extended to 64-bits
|                 |                 |      |            |                | with RAX.                             
| 80 /7 ib        | CMP r/m8, imm8  | MI   | Valid      | Valid          | Compare imm8 with r/m8.               
| REX + 80 /7 ib  | CMP r/m8*, imm8 | MI   | Valid      | N.E.           | Compare imm8 with r/m8.               
| 81 /7 iw        | CMP r/m16, imm16| MI   | Valid      | Valid          | Compare imm16 with r/m16.             
| 81 /7 id        | CMP r/m32, imm32| MI   | Valid      | Valid          | Compare imm32 with r/m32.             
| REX.W + 81 /7 id| CMP r/m64, imm32| MI   | Valid      | N.E.           | Compare imm32 sign-extended to 64-bits
|                 |                 |      |            |                | with r/m64.                           
| 83 /7 ib        | CMP r/m16, imm8 | MI   | Valid      | Valid          | Compare imm8 with r/m16.              
| 83 /7 ib        | CMP r/m32, imm8 | MI   | Valid      | Valid          | Compare imm8 with r/m32.              
| REX.W + 83 /7 ib| CMP r/m64, imm8 | MI   | Valid      | N.E.           | Compare imm8 with r/m64.              
| 38 /r           | CMP r/m8, r8    | MR   | Valid      | Valid          | Compare r8 with r/m8.                 
| REX + 38 /r     | CMP r/m8*, r8*  | MR   | Valid      | N.E.           | Compare r8 with r/m8.                 
| 39 /r           | CMP r/m16, r16  | MR   | Valid      | Valid          | Compare r16 with r/m16.               
| 39 /r           | CMP r/m32, r32  | MR   | Valid      | Valid          | Compare r32 with r/m32.               
| REX.W + 39 /r   | CMP r/m64,r64   | MR   | Valid      | N.E.           | Compare r64 with r/m64.               
| 3A /r           | CMP r8, r/m8    | RM   | Valid      | Valid          | Compare r/m8 with r8.                 
| REX + 3A /r     | CMP r8*, r/m8*  | RM   | Valid      | N.E.           | Compare r/m8 with r8.                 
| 3B /r           | CMP r16, r/m16  | RM   | Valid      | Valid          | Compare r/m16 with r16.               
| 3B /r           | CMP r32, r/m32  | RM   | Valid      | Valid          | Compare r/m32 with r32.               
| REX.W + 3B /r   | CMP r64, r/m64  | RM   | Valid      | N.E.           | Compare r/m64 with r64.               
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       
| MR   | ModRM:r/m (r, w)| ModRM:reg (w)| NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       
| I    | AL/AX/EAX/RAX   | imm8         | NA       | NA       

Description:
Compares the first source operand with the second source operand and sets the
status flags in the EFLAGS register according to the results. The comparison
is performed by subtracting the second operand from the first operand and then
setting the status flags in the same manner as the SUB instruction. When an
immediate value is used as an operand, it is sign-extended to the length of
the first operand.

The condition codes used by the Jcc, CMOVcc, and SETcc instructions are based
on the results of a CMP instruction. Appendix B, “EFLAGS Condition Codes,” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1,
shows the relationship of the status flags and the condition codes.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning
of this section for encoding data and limits.

Operation:

temp <- SRC1 − SignExtend(SRC2);
ModifyStatusFlags; (* Modify status flags in the same manner as the SUB instruction*)

Flags Affected:
The CF, OF, SF, ZF, AF, and PF flags are set according to the result.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: CMPPD
description:
CMPPD - Compare Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                  
| 66 0F C2 /r ib CMPPD xmm1, xmm2/m128,| RMI  | V/V          | SSE2              | Compare packed double-precision floatingpoint
| imm8                                 |      |              |                   | values in xmm2/m128 and xmm1 using imm8      
|                                      |      |              |                   | as comparison predicate.                     
| VEX.NDS.128.66.0F.WIG C2 /r ib VCMPPD| RVMI | V/V          | AVX               | Compare packed double-precision floatingpoint
| xmm1, xmm2, xmm3/m128, imm8          |      |              |                   | values in xmm3/m128 and xmm2 using bits      
|                                      |      |              |                   | 4:0 of imm8 as a comparison predicate.       
| VEX.NDS.256.66.0F.WIG C2 /r ib VCMPPD| RVMI | V/V          | AVX               | Compare packed double-precision floatingpoint
| ymm1, ymm2, ymm3/m256, imm8          |      |              |                   | values in ymm3/m256 and ymm2 using bits      
|                                      |      |              |                   | 4:0 of imm8 as a comparison predicate.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Performs a SIMD compare of the packed double-precision floating-point values
in the source operand (second operand) and the destination operand (first operand)
and returns the results of the comparison to the destination operand. The comparison
predicate operand (third operand) specifies the type of comparison performed
on each of the pairs of packed values. The result of each comparison is a quadword
mask of all 1s (comparison true) or all 0s (comparison false). The sign of zero
is ignored for comparisons, so that -0.0 is equal to +0.0. 128-bit Legacy SSE
version: The first source and destination operand (first operand) is an XMM
register. The second source operand (second operand) can be an XMM register
or 128-bit memory location. The comparison predicate operand is an 8-bit immediate,
bits 2:0 of the immediate define the type of comparison to be performed (see
Table 3-7). Bits 7:3 of the immediate is reserved. Bits (VLMAX-1:128) of the
corresponding YMM destination register remain unchanged. Two comparisons are
performed with results written to bits 127:0 of the destination operand.


Table 3-7. Comparison Predicate for CMPPD and CMPPS Instructions:
| Predicate EQ LT LE UNORD NEQ NLT| imm8 Encoding 000B 001B 010B 011B 100B| Description Equal Less-than Less-than-or-equal     | Relation where: A Is 1st Operand B Is  | Emulation Swap Operands, Use LT Swap | Result if NaN Operand False False False| QNaN Oper-and Signals Invalid No Yes 
|                                 | 101B                                  | Greater than Greater-than-or-equal Unordered       | 2nd Operand A = B A < B A ≤ B A > B    | Operands, Use LE                     | False False True True True             | Yes Yes Yes No No Yes (Contd.)       
|                                 |                                       | Not-equal Not-less-than Table 3-7.                 | A ≥ B A, B = Unordered A != B NOT(A <   |                                      |                                        |                                      
|                                 |                                       |                                                    | B) Comparison Predicate for CMPPD and  |                                      |                                        |                                      
|                                 |                                       |                                                    | CMPPS Instructions                     |                                      |                                        |                                      
| Predicate NLE ORD               | imm8 Encoding 110B 111B               | Description Not-less-than-or-equal Not-greater-than| Relation where: A Is 1st Operand B Is  | Emulation Swap Operands, Use NLT Swap| Result if NaN Operand True True True   | QNaN Oper-and Signals Invalid Yes Yes
|                                 |                                       | Not-greater-than-or-equal Ordered                  | 2nd Operand NOT(A ≤ B) NOT(A > B) NOT(A| Operands, Use NLE                    | False                                  | Yes No                               
|                                 |                                       |                                                    | ≥ B) A , B = Ordered                   |                                      |                                        |                                      
The unordered relationship is true when at least one of the two source operands
being compared is a NaN; the ordered relationship is true when neither source
operand is a NaN.

A subsequent computational instruction that uses the mask result in the destination
operand as an input operand will not generate an exception, because a mask of
all 0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds
to a QNaN.

Note that the processors with “CPUID.1H:ECX.AVX =0” do not implement the greater-than,
greater-than-or-equal, not-greater-than, and not-greater-than-or-equal relations.
These comparisons can be made either by using the inverse relationship (that
is, use the “not-less-than-or-equal” to make a “greater-than” comparison) or
by using software emulation. When using software emulation, the program must
swap the operands (copying registers when necessary to protect the data that
will now be in the destination), and then perform the compare using a different
predicate. The predicate to be used for these emulations is listed in Table
3-7 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops
in addition to the three-operand CMPPD instruction, for processors with “CPUID.1H:ECX.AVX
=0”. See Table 3-8. Compiler should treat reserved Imm8 values as illegal syntax.

| : Pseudo-Op CMPEQPD xmm1, xmm2 CMPLTPD  | Table 3-8.| Pseudo-Op and CMPPD Implementation CMPPD
| xmm1, xmm2 CMPLEPD xmm1, xmm2 CMPUNORDPD|           | Implementation CMPPD xmm1, xmm2, 0 CMPPD
| xmm1, xmm2 CMPNEQPD xmm1, xmm2 CMPNLTPD |           | xmm1, xmm2, 1 CMPPD xmm1, xmm2, 2 CMPPD 
| xmm1, xmm2 CMPNLEPD xmm1, xmm2 CMPORDPD |           | xmm1, xmm2, 3 CMPPD xmm1, xmm2, 4 CMPPD 
| xmm1, xmm2                              |           | xmm1, xmm2, 5 CMPPD xmm1, xmm2, 6 CMPPD 
|                                         |           | xmm1, xmm2, 7                           
The greater-than relations that the processor does not implement, require more
than one instruction to emulate in software and therefore should not be implemented
as pseudo-ops. (For these, the programmer should reverse the operands of the
corresponding less than relations and use move instructions to ensure that the
mask is moved to the correct destination register and that the source operand
is left intact.)

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Enhanced Comparison Predicate for VEX-Encoded VCMPPD VEX.128 encoded version:
The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 128-bit memory location.
Bits (VLMAX-1:128) of the destination YMM register are zeroed. Two comparisons
are performed with results written to bits 127:0 of the destination operand.

VEX.256 encoded version: The first source operand (second operand) is a YMM
register. The second source operand (third operand) can be a YMM register or
a 256-bit memory location. The destination operand (first operand) is a YMM
register. Four comparisons are performed with results written to the destination
operand. The comparison predicate operand is an 8-bit immediate:

 - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison
to be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.
Table 3-9. Comparison Predicate for VCMPPD and VCMPPS Instructions

| Predicate      | imm8 Value    | Description                                     | Result: A Is 1st Operand, B Is 2nd Operand| Signals #IA on QNAN Unordered1
|                |               |                                                 | A = B                                     |                               
| EQ_OQ (EQ)     | 0H            | Equal (ordered, non-signaling)                  | True                                      | No                            
| LT_OS (LT)     | 1H            | Less-than (ordered, signaling)                  | False                                     | Yes                           
| LE_OS (LE)     | 2H            | Less-than-or-equal (ordered, signaling)         | True                                      | Yes                           
| UNORD_Q (UNORD)| 3H            | Unordered (non-signaling)                       | False                                     | No                            
| NEQ_UQ (NEQ)   | 4H            | Not-equal (unordered, nonsignaling)             | False                                     | No                            
| NLT_US (NLT)   | 5H            | Not-less-than (unordered, signaling)            | True                                      | Yes                           
| NLE_US (NLE)   | 6H            | Not-less-than-or-equal (unordered, signaling)   | False                                     | Yes                           
| ORD_Q (ORD)    | 7H            | Ordered (non-signaling)                         | True                                      | No                            
| EQ_UQ          | 8H            | Equal (unordered, non-signaling)                | True                                      | No                            
| NGE_US (NGE)   | 9H            | Not-greater-than-or-equal (unordered,           | False                                     | Yes                           
|                |               | signaling)                                      |                                           |                               
| NGT_US (NGT)   | AH            | Not-greater-than (unordered, signaling)         | True                                      | Yes                           
| FALSE_OQ(FALSE)| BH            | False (ordered, non-signaling)                  | False                                     | No                            
| NEQ_OQ         | CH            | Not-equal (ordered, non-signaling)              | False                                     | No                            
| GE_OS (GE)     | DH            | Greater-than-or-equal (ordered, signaling)      | True                                      | Yes                           
| GT_OS (GT)     | EH            | Greater-than (ordered, signaling)               | False                                     | Yes                           
| TRUE_UQ(TRUE)  | FH            | True (unordered, non-signaling)                 | True                                      | No                            
| EQ_OS          | 10H           | Equal (ordered, signaling)                      | True                                      | Yes                           
| LT_OQ          | 11H           | Less-than (ordered, nonsignaling)               | False                                     | No                            
| LE_OQ          | 12H           | Less-than-or-equal (ordered, nonsignaling)      | True                                      | No                            
| UNORD_S        | 13H           | Unordered (signaling)                           | False                                     | Yes                           
| NEQ_US         | 14H           | Not-equal (unordered, signaling)                | False                                     | Yes                           
| NLT_UQ         | 15H           | Not-less-than (unordered, nonsignaling)         | True                                      | No                            
| NLE_UQ         | 16H           | Not-less-than-or-equal (unordered, nonsignaling)| False                                     | No                            
| ORD_S          | 17H           | Ordered (signaling)                             | True                                      | Yes                           
| EQ_US          | 18H Table 3-9.| Equal (unordered, signaling) Comparison         | True                                      | Yes (Contd.)                  
|                |               | Predicate for VCMPPD and VCMPPS Instructions    |                                           |                               
| Predicate      | imm8 Value    | Description                                     | Result: A Is 1st Operand, B Is 2nd Operand| Signals #IA on QNAN Unordered1
|                |               |                                                 | A = B                                     |                               
| NGE_UQ         | 19H           | Not-greater-than-or-equal (unordered,           | False                                     | No                            
|                |               | nonsignaling)                                   |                                           |                               
| NGT_UQ         | 1AH           | Not-greater-than (unordered, nonsignaling)      | True                                      | No                            
| FALSE_OS       | 1BH           | False (ordered, signaling)                      | False                                     | Yes                           
| NEQ_OS         | 1CH           | Not-equal (ordered, signaling)                  | False                                     | Yes                           
| GE_OQ          | 1DH           | Greater-than-or-equal (ordered, nonsignaling)   | True                                      | No                            
| GT_OQ          | 1EH           | Greater-than (ordered, nonsignaling)            | False                                     | No                            
| TRUE_US        | 1FH           | True (unordered, signaling)                     | True                                      | Yes                           
Notes: 1. If either operand A or B is a NAN.

Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates
shown in Table 3-9, software emulation is no longer needed. Compilers and assemblers
may implement the following three-operand pseudo-ops in addition to the four-operand
VCMPPD instruction. See Table 3-10, where the notations of reg1 reg2, and reg3
represent either XMM registers or YMM registers. Compiler should treat reserved
Imm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops
to pre-defined constants to support a simpler intrinsic interface.

| : Pseudo-Op VCMPEQPD reg1, reg2, reg3          | Table 3-10. Table 3-10.| Pseudo-Op and VCMPPD Implementation      
| VCMPLTPD reg1, reg2, reg3 VCMPLEPD reg1,       |                        | CMPPD Implementation VCMPPD reg1, reg2,  
| reg2, reg3 VCMPUNORDPD reg1, reg2, reg3        |                        | reg3, 0 VCMPPD reg1, reg2, reg3, 1 VCMPPD
| VCMPNEQPD reg1, reg2, reg3 VCMPNLTPD           |                        | reg1, reg2, reg3, 2 VCMPPD reg1, reg2,   
| reg1, reg2, reg3 VCMPNLEPD reg1, reg2,         |                        | reg3, 3 VCMPPD reg1, reg2, reg3, 4 VCMPPD
| reg3 VCMPORDPD reg1, reg2, reg3 VCMPEQ_UQPD    |                        | reg1, reg2, reg3, 5 VCMPPD reg1, reg2,   
| reg1, reg2, reg3 VCMPNGEPD reg1, reg2,         |                        | reg3, 6 VCMPPD reg1, reg2, reg3, 7 VCMPPD
| reg3 VCMPNGTPD reg1, reg2, reg3 VCMPFALSEPD    |                        | reg1, reg2, reg3, 8 VCMPPD reg1, reg2,   
| reg1, reg2, reg3 VCMPNEQ_OQPD reg1,            |                        | reg3, 9 VCMPPD reg1, reg2, reg3, 0AH     
| reg2, reg3 VCMPGEPD reg1, reg2, reg3           |                        | VCMPPD reg1, reg2, reg3, 0BH VCMPPD      
| VCMPGTPD reg1, reg2, reg3 VCMPTRUEPD           |                        | reg1, reg2, reg3, 0CH VCMPPD reg1, reg2, 
| reg1, reg2, reg3 VCMPEQ_OSPD reg1, reg2,       |                        | reg3, 0DH VCMPPD reg1, reg2, reg3, 0EH   
| reg3 VCMPLT_OQPD reg1, reg2, reg3 VCMPLE_OQPD  |                        | VCMPPD reg1, reg2, reg3, 0FH VCMPPD      
| reg1, reg2, reg3 Pseudo-Op VCMPUNORD_SPD       |                        | reg1, reg2, reg3, 10H VCMPPD reg1, reg2, 
| reg1, reg2, reg3 VCMPNEQ_USPD reg1,            |                        | reg3, 11H VCMPPD reg1, reg2, reg3, 12H   
| reg2, reg3 VCMPNLT_UQPD reg1, reg2,            |                        | Pseudo-Op and VCMPPD Implementation      
| reg3 VCMPNLE_UQPD reg1, reg2, reg3 VCMPORD_SPD |                        | CMPPD Implementation VCMPPD reg1, reg2,  
| reg1, reg2, reg3 VCMPEQ_USPD reg1, reg2,       |                        | reg3, 13H VCMPPD reg1, reg2, reg3, 14H   
| reg3 VCMPNGE_UQPD reg1, reg2, reg3 VCMPNGT_UQPD|                        | VCMPPD reg1, reg2, reg3, 15H VCMPPD      
| reg1, reg2, reg3 VCMPFALSE_OSPD reg1,          |                        | reg1, reg2, reg3, 16H VCMPPD reg1, reg2, 
| reg2, reg3 VCMPNEQ_OSPD reg1, reg2,            |                        | reg3, 17H VCMPPD reg1, reg2, reg3, 18H   
| reg3 VCMPGE_OQPD reg1, reg2, reg3 VCMPGT_OQPD  |                        | VCMPPD reg1, reg2, reg3, 19H VCMPPD      
| reg1, reg2, reg3 VCMPTRUE_USPD reg1,           |                        | reg1, reg2, reg3, 1AH VCMPPD reg1, reg2, 
| reg2, reg3                                     |                        | reg3, 1BH VCMPPD reg1, reg2, reg3, 1CH   
|                                                |                        | VCMPPD reg1, reg2, reg3, 1DH VCMPPD      
|                                                |                        | reg1, reg2, reg3, 1EH VCMPPD reg1, reg2, 
|                                                |                        | reg3, 1FH                                
Operation:

CASE (COMPARISON PREDICATE) OF
  0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;
  1: OP3 <- LT_OS; OP5 <- LT_OS;
  2: OP3 <- LE_OS; OP5 <- LE_OS;
  3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;
  4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;
  5: OP3 <- NLT_US; OP5 <- NLT_US;
  6: OP3 <- NLE_US; OP5 <- NLE_US;
  7: OP3 <- ORD_Q; OP5 <- ORD_Q;
  8: OP5 <- EQ_UQ;
  9: OP5 <- NGE_US;
  10: OP5 <- NGT_US;
  11: OP5 <- FALSE_OQ;
  12: OP5 <- NEQ_OQ;
  13: OP5 <- GE_OS;
  14: OP5 <- GT_OS;
  15: OP5 <- TRUE_UQ;
  16: OP5 <- EQ_OS;
  17: OP5 <- LT_OQ;
  18: OP5 <- LE_OQ;
  19: OP5 <- UNORD_S;
  20: OP5 <- NEQ_US;
  21: OP5 <- NLT_UQ;
  22: OP5 <- NLE_UQ;
  23: OP5 <- ORD_S;
  24: OP5 <- EQ_US;
  25: OP5 <- NGE_UQ;
  26: OP5 <- NGT_UQ;
  27: OP5 <- FALSE_OS;
  28: OP5 <- NEQ_OS;
  29: OP5 <- GE_OQ;
  30: OP5 <- GT_OQ;
  31: OP5 <- TRUE_US;
  DEFAULT: Reserved;
CMPPD (128-bit Legacy SSE version)
CMP0 <- SRC1[63:0] OP3 SRC2[63:0];
CMP1 <- SRC1[127:64] OP3 SRC2[127:64];
IF CMP0 = TRUE
  THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <- 0000000000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <- 0000000000000000H; FI;
DEST[VLMAX-1:128] (Unmodified)
VCMPPD (VEX.128 encoded version)
CMP0 <- SRC1[63:0] OP5 SRC2[63:0];
CMP1 <- SRC1[127:64] OP5 SRC2[127:64];
IF CMP0 = TRUE
  THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <- 0000000000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <- 0000000000000000H; FI;
DEST[VLMAX-1:128] <- 0
VCMPPD (VEX.256 encoded version)
CMP0 <- SRC1[63:0] OP5 SRC2[63:0];
CMP1 <- SRC1[127:64] OP5 SRC2[127:64];
CMP2 <- SRC1[191:128] OP5 SRC2[191:128];
CMP3 <- SRC1[255:192] OP5 SRC2[255:192];
IF CMP0 = TRUE
  THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <- 0000000000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <- 0000000000000000H; FI;
IF CMP2 = TRUE
  THEN DEST[191:128] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[191:128] <- 0000000000000000H; FI;
IF CMP3 = TRUE
  THEN DEST[255:192] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[255:192] <- 0000000000000000H; FI;

Intel C/C++ Compiler Intrinsic Equivalents:
| CMPPD for equality:                               | __m128d _mm_cmpeq_pd(__m128d a, __m128d   
|                                                   | b)                                        
| CMPPD for less-than: CMPPD for less-than-or-equal:| __m128d _mm_cmplt_pd(__m128d a, __m128d   
| __m128d _mm_cmple_pd(__m128d a, __m128d           | b)                                        
| b)                                                |                                           
| CMPPD for greater-than:                           | __m128d _mm_cmpgt_pd(__m128d a, __m128d   
|                                                   | b)                                        
| CMPPD for greater-than-or-equal:                  | __m128d _mm_cmpge_pd(__m128d a, __m128d   
|                                                   | b)                                        
| CMPPD for inequality:                             | __m128d _mm_cmpneq_pd(__m128d a, __m128d  
|                                                   | b)                                        
| CMPPD for not-less-than:                          | __m128d _mm_cmpnlt_pd(__m128d a, __m128d  
|                                                   | b)                                        
| CMPPD for not-greater-than:                       | __m128d _mm_cmpngt_pd(__m128d a, __m128d  
|                                                   | b)                                        
| CMPPD for not-greater-than-or-equal:              | __m128d _mm_cmpnge_pd(__m128d a, __m128d  
|                                                   | b)                                        
| CMPPD for ordered:                                | __m128d _mm_cmpord_pd(__m128d a, __m128d  
|                                                   | b)                                        
| CMPPD for unordered:                              | __m128d _mm_cmpunord_pd(__m128d a, __m128d
|                                                   | b)                                        
| CMPPD for not-less-than-or-equal: __m256          | __m128d _mm_cmpnle_pd(__m128d a, __m128d  
| _mm256_cmp_pd(__m256 a, __m256 b, const           | b)                                        
| int imm)                                          |                                           
| VCMPPD:                                           | __m128 _mm_cmp_pd(__m128 a, __m128 b,     
|                                                   | const int imm)                            

SIMD Floating-Point Exceptions:
Invalid if SNaN operand and invalid if QNaN and predicate as listed in above
table, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: CMPPS
description:
CMPPS - Compare Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                  
| 0F C2 /r ib CMPPS xmm1, xmm2/m128, imm8 | RMI  | V/V          | SSE               | Compare packed single-precision floatingpoint
|                                         |      |              |                   | values in xmm2/mem and xmm1 using imm8       
|                                         |      |              |                   | as comparison predicate.                     
| VEX.NDS.128.0F.WIG C2 /r ib VCMPPS xmm1,| RVMI | V/V          | AVX               | Compare packed single-precision floatingpoint
| xmm2, xmm3/m128, imm8                   |      |              |                   | values in xmm3/m128 and xmm2 using bits      
|                                         |      |              |                   | 4:0 of imm8 as a comparison predicate.       
| VEX.NDS.256.0F.WIG C2 /r ib VCMPPS ymm1,| RVMI | V/V          | AVX               | Compare packed single-precision floatingpoint
| ymm2, ymm3/m256, imm8                   |      |              |                   | values in ymm3/m256 and ymm2 using bits      
|                                         |      |              |                   | 4:0 of imm8 as a comparison predicate.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Performs a SIMD compare of the packed single-precision floating-point values
in the source operand (second operand) and the destination operand (first operand)
and returns the results of the comparison to the destination operand. The comparison
predicate operand (third operand) specifies the type of comparison performed
on each of the pairs of packed values. The result of each comparison is a doubleword
mask of all 1s (comparison true) or all 0s (comparison false). The sign of zero
is ignored for comparisons, so that -0.0 is equal to +0.0. 128-bit Legacy SSE
version: The first source and destination operand (first operand) is an XMM
register. The second source operand (second operand) can be an XMM register
or 128-bit memory location. The comparison predicate operand is an 8-bit immediate,
bits 2:0 of the immediate define the type of comparison to be performed (see
Table 3-7). Bits 7:3 of the immediate is reserved. Bits (VLMAX-1:128) of the
corresponding YMM destination register remain unchanged. Four comparisons are
performed with results written to bits 127:0 of the destination operand.

The unordered relationship is true when at least one of the two source operands
being compared is a NaN; the ordered relationship is true when neither source
operand is a NaN.

A subsequent computational instruction that uses the mask result in the destination
operand as an input operand will not generate a fault, because a mask of all
0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds
to a QNaN.

Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”,
“greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal
relations” predicates. These comparisons can be made either by using the inverse
relationship (that is, use the “not-less-than-or-equal” to make a “greater-than”
comparison) or by using software emulation. When using software emulation, the
program must swap the operands (copying registers when necessary to protect
the data that will now be in the destination), and then perform the compare
using a different predicate. The predicate to be used for these emulations is
listed in Table 3-7 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops
in addition to the three-operand CMPPS instruction, for processors with “CPUID.1H:ECX.AVX
=0”. See Table 3-11. Compiler should treat reserved Imm8 values as illegal syntax.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).


Table 3-11. Pseudo-Ops and CMPPS:
| Pseudo-Op            | Implementation     
| CMPEQPS xmm1, xmm2   | CMPPS xmm1, xmm2, 0
| CMPLTPS xmm1, xmm2   | CMPPS xmm1, xmm2, 1
| CMPLEPS xmm1, xmm2   | CMPPS xmm1, xmm2, 2
| CMPUNORDPS xmm1, xmm2| CMPPS xmm1, xmm2, 3
| CMPNEQPS xmm1, xmm2  | CMPPS xmm1, xmm2, 4
| CMPNLTPS xmm1, xmm2  | CMPPS xmm1, xmm2, 5
| CMPNLEPS xmm1, xmm2  | CMPPS xmm1, xmm2, 6
| CMPORDPS xmm1, xmm2  | CMPPS xmm1, xmm2, 7
The greater-than relations not implemented by processor require more than one
instruction to emulate in software and therefore should not be implemented as
pseudo-ops. (For these, the programmer should reverse the operands of the corresponding
less than relations and use move instructions to ensure that the mask is moved
to the correct destination register and that the source operand is left intact.)

Enhanced Comparison Predicate for VEX-Encoded VCMPPS VEX.128 encoded version:
The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 128-bit memory location.
Bits (VLMAX-1:128) of the destination YMM register are zeroed. Four comparisons
are performed with results written to bits 127:0 of the destination operand.
VEX.256 encoded version: The first source operand (second operand) is a YMM
register. The second source operand (third operand) can be a YMM register or
a 256-bit memory location. The destination operand (first operand) is a YMM
register. Eight comparisons are performed with results written to the destination
operand. The comparison predicate operand is an 8-bit immediate:

 - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison
to be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.

Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates
shown in Table 3-9, software emulation is no longer needed. Compilers and assemblers
may implement the following three-operand pseudo-ops in addition to the four-operand
VCMPPS instruction. See Table 3-12, where the notation of reg1 and reg2 represent
either XMM registers or YMM registers. Compiler should treat reserved Imm8 values
as illegal syntax. Alternately, intrinsics can map the pseudo-ops to pre-defined
constants to support a simpler intrinsic interface.

| : Pseudo-Op VCMPEQPS reg1, reg2, reg3          | Table 3-12. Table 3-12.| Pseudo-Op and VCMPPS Implementation           
| VCMPLTPS reg1, reg2, reg3 VCMPLEPS reg1,       |                        | CMPPS Implementation VCMPPS reg1, reg2,       
| reg2, reg3 VCMPUNORDPS reg1, reg2, reg3        |                        | reg3, 0 VCMPPS reg1, reg2, reg3, 1 VCMPPS     
| VCMPNEQPS reg1, reg2, reg3 VCMPNLTPS           |                        | reg1, reg2, reg3, 2 VCMPPS reg1, reg2,        
| reg1, reg2, reg3 VCMPNLEPS reg1, reg2,         |                        | reg3, 3 VCMPPS reg1, reg2, reg3, 4 VCMPPS     
| reg3 VCMPORDPS reg1, reg2, reg3 VCMPEQ_UQPS    |                        | reg1, reg2, reg3, 5 VCMPPS reg1, reg2,        
| reg1, reg2, reg3 VCMPNGEPS reg1, reg2,         |                        | reg3, 6 VCMPPS reg1, reg2, reg3, 7 VCMPPS     
| reg3 VCMPNGTPS reg1, reg2, reg3 VCMPFALSEPS    |                        | reg1, reg2, reg3, 8 VCMPPS reg1, reg2,        
| reg1, reg2, reg3 Pseudo-Op VCMPNEQ_OQPS        |                        | reg3, 9 VCMPPS reg1, reg2, reg3, 0AH          
| reg1, reg2, reg3 VCMPGEPS reg1, reg2,          |                        | VCMPPS reg1, reg2, reg3, 0BH Pseudo-Op        
| reg3 VCMPGTPS reg1, reg2, reg3 VCMPTRUEPS      |                        | and VCMPPS Implementation CMPPS Implementation
| reg1, reg2, reg3 VCMPEQ_OSPS reg1, reg2,       |                        | VCMPPS reg1, reg2, reg3, 0CH VCMPPS           
| reg3 VCMPLT_OQPS reg1, reg2, reg3 VCMPLE_OQPS  |                        | reg1, reg2, reg3, 0DH VCMPPS reg1, reg2,      
| reg1, reg2, reg3 VCMPUNORD_SPS reg1,           |                        | reg3, 0EH VCMPPS reg1, reg2, reg3, 0FH        
| reg2, reg3 VCMPNEQ_USPS reg1, reg2,            |                        | VCMPPS reg1, reg2, reg3, 10H VCMPPS           
| reg3 VCMPNLT_UQPS reg1, reg2, reg3 VCMPNLE_UQPS|                        | reg1, reg2, reg3, 11H VCMPPS reg1, reg2,      
| reg1, reg2, reg3 VCMPORD_SPS reg1, reg2,       |                        | reg3, 12H VCMPPS reg1, reg2, reg3, 13H        
| reg3 VCMPEQ_USPS reg1, reg2, reg3 VCMPNGE_UQPS |                        | VCMPPS reg1, reg2, reg3, 14H VCMPPS           
| reg1, reg2, reg3 VCMPNGT_UQPS reg1,            |                        | reg1, reg2, reg3, 15H VCMPPS reg1, reg2,      
| reg2, reg3 VCMPFALSE_OSPS reg1, reg2,          |                        | reg3, 16H VCMPPS reg1, reg2, reg3, 17H        
| reg3 VCMPNEQ_OSPS reg1, reg2, reg3 VCMPGE_OQPS |                        | VCMPPS reg1, reg2, reg3, 18H VCMPPS           
| reg1, reg2, reg3 VCMPGT_OQPS reg1, reg2,       |                        | reg1, reg2, reg3, 19H VCMPPS reg1, reg2,      
| reg3 VCMPTRUE_USPS reg1, reg2, reg3            |                        | reg3, 1AH VCMPPS reg1, reg2, reg3, 1BH        
|                                                |                        | VCMPPS reg1, reg2, reg3, 1CH VCMPPS           
|                                                |                        | reg1, reg2, reg3, 1DH VCMPPS reg1, reg2,      
|                                                |                        | reg3, 1EH VCMPPS reg1, reg2, reg3, 1FH        
Operation:

CASE (COMPARISON PREDICATE) OF
  0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;
  1: OP3 <- LT_OS; OP5 <- LT_OS;
  2: OP3 <- LE_OS; OP5 <- LE_OS;
  3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;
  4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;
  5: OP3 <- NLT_US; OP5 <- NLT_US;
  6: OP3 <- NLE_US; OP5 <- NLE_US;
  7: OP3 <- ORD_Q; OP5 <- ORD_Q;
  8: OP5 <- EQ_UQ;
  9: OP5 <- NGE_US;
  10: OP5 <- NGT_US;
  11: OP5 <- FALSE_OQ;
  12: OP5 <- NEQ_OQ;
  13: OP5 <- GE_OS;
  14: OP5 <- GT_OS;
  15: OP5 <- TRUE_UQ;
  16: OP5 <- EQ_OS;
  17: OP5 <- LT_OQ;
  18: OP5 <- LE_OQ;
  19: OP5 <- UNORD_S;
  20: OP5 <- NEQ_US;
  21: OP5 <- NLT_UQ;
  22: OP5 <- NLE_UQ;
  23: OP5 <- ORD_S;
  24: OP5 <- EQ_US;
  25: OP5 <- NGE_UQ;
  26: OP5 <- NGT_UQ;
  27: OP5 <- FALSE_OS;
  28: OP5 <- NEQ_OS;
  29: OP5 <- GE_OQ;
  30: OP5 <- GT_OQ;
  31: OP5 <- TRUE_US;
  DEFAULT: Reserved
EASC;
CMPPS (128-bit Legacy SSE version)
CMP0 <- SRC1[31:0] OP3 SRC2[31:0];
CMP1 <- SRC1[63:32] OP3 SRC2[63:32];
CMP2 <- SRC1[95:64] OP3 SRC2[95:64];
CMP3 <- SRC1[127:96] OP3 SRC2[127:96];
IF CMP0 = TRUE
  THEN DEST[31:0] <-FFFFFFFFH;
  ELSE DEST[31:0] <- 000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[63:32] <- FFFFFFFFH;
  ELSE DEST[63:32] <- 000000000H; FI;
IF CMP2 = TRUE
  THEN DEST[95:64] <- FFFFFFFFH;
  ELSE DEST[95:64] <- 000000000H; FI;
IF CMP3 = TRUE
  THEN DEST[127:96] <- FFFFFFFFH;
  ELSE DEST[127:96] <-000000000H; FI;
DEST[VLMAX-1:128] (Unmodified)
VCMPPS (VEX.128 encoded version)
CMP0 <- SRC1[31:0] OP5 SRC2[31:0];
CMP1 <- SRC1[63:32] OP5 SRC2[63:32];
CMP2 <- SRC1[95:64] OP5 SRC2[95:64];
CMP3 <- SRC1[127:96] OP5 SRC2[127:96];
IF CMP0 = TRUE
  THEN DEST[31:0] <-FFFFFFFFH;
  ELSE DEST[31:0] <- 000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[63:32] <- FFFFFFFFH;
  ELSE DEST[63:32] <- 000000000H; FI;
IF CMP2 = TRUE
  THEN DEST[95:64] <- FFFFFFFFH;
  ELSE DEST[95:64] <- 000000000H; FI;
IF CMP3 = TRUE
  THEN DEST[127:96] <- FFFFFFFFH;
  ELSE DEST[127:96] <-000000000H; FI;
DEST[VLMAX-1:128] <- 0
VCMPPS (VEX.256 encoded version)
CMP0 <- SRC1[31:0] OP5 SRC2[31:0];
CMP1 <- SRC1[63:32] OP5 SRC2[63:32];
CMP2 <- SRC1[95:64] OP5 SRC2[95:64];
CMP3 <- SRC1[127:96] OP5 SRC2[127:96];
CMP4 <- SRC1[159:128] OP5 SRC2[159:128];
CMP5 <- SRC1[191:160] OP5 SRC2[191:160];
CMP6 <- SRC1[223:192] OP5 SRC2[223:192];
CMP7 <- SRC1[255:224] OP5 SRC2[255:224];
IF CMP0 = TRUE
  THEN DEST[31:0] <-FFFFFFFFH;
  ELSE DEST[31:0] <- 000000000H; FI;
IF CMP1 = TRUE
  THEN DEST[63:32] <- FFFFFFFFH;
  ELSE DEST[63:32] <-000000000H; FI;
IF CMP2 = TRUE
  THEN DEST[95:64] <- FFFFFFFFH;
  ELSE DEST[95:64] <- 000000000H; FI;
IF CMP3 = TRUE
  THEN DEST[127:96] <- FFFFFFFFH;
  ELSE DEST[127:96] <- 000000000H; FI;
IF CMP4 = TRUE
  THEN DEST[159:128] <- FFFFFFFFH;
  ELSE DEST[159:128] <- 000000000H; FI;
IF CMP5 = TRUE
  THEN DEST[191:160] <- FFFFFFFFH;
  ELSE DEST[191:160] <- 000000000H; FI;
IF CMP6 = TRUE
  THEN DEST[223:192] <- FFFFFFFFH;
  ELSE DEST[223:192] <-000000000H; FI;
IF CMP7 = TRUE
  THEN DEST[255:224] <- FFFFFFFFH;
  ELSE DEST[255:224] <- 000000000H; FI;

Intel C/C++ Compiler Intrinsic Equivalents:
| CMPPS for equality:                     | __m128 _mm_cmpeq_ps(__m128 a, __m128   
|                                         | b)                                     
| CMPPS for less-than:                    | __m128 _mm_cmplt_ps(__m128 a, __m128   
|                                         | b)                                     
| CMPPS for less-than-or-equal:           | __m128 _mm_cmple_ps(__m128 a, __m128   
|                                         | b)                                     
| CMPPS for greater-than:                 | __m128 _mm_cmpgt_ps(__m128 a, __m128   
|                                         | b)                                     
| CMPPS for greater-than-or-equal:        | __m128 _mm_cmpge_ps(__m128 a, __m128   
|                                         | b)                                     
| CMPPS for inequality:                   | __m128 _mm_cmpneq_ps(__m128 a, __m128  
|                                         | b)                                     
| CMPPS for not-less-than:                | __m128 _mm_cmpnlt_ps(__m128 a, __m128  
|                                         | b)                                     
| CMPPS for not-greater-than:             | __m128 _mm_cmpngt_ps(__m128 a, __m128  
|                                         | b)                                     
| CMPPS for not-greater-than-or-equal:    | __m128 _mm_cmpnge_ps(__m128 a, __m128  
|                                         | b)                                     
| CMPPS for ordered:                      | __m128 _mm_cmpord_ps(__m128 a, __m128  
|                                         | b)                                     
| CMPPS for unordered:                    | __m128 _mm_cmpunord_ps(__m128 a, __m128
|                                         | b)                                     
| CMPPS for not-less-than-or-equal: __m256| __m128 _mm_cmpnle_ps(__m128 a, __m128  
| _mm256_cmp_ps(__m256 a, __m256 b, const | b)                                     
| int imm) __m128 _mm_cmp_ps(__m128 a,    |                                        
| __m128 b, const int imm)                |                                        

SIMD Floating-Point Exceptions:
Invalid if SNaN operand and invalid if QNaN and predicate as listed in above
table, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: CMPS
description:
CMPS/CMPSB/CMPSW/CMPSD/CMPSQ - Compare String Operands:
| Opcode    | Instruction  | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| A6        | CMPS m8, m8  | NP   | Valid      | Valid          | For legacy mode, compare byte at address 
|           |              |      |            |                | DS:(E)SI with byte at address ES:(E)DI;  
|           |              |      |            |                | For 64bit mode compare byte at address   
|           |              |      |            |                | (R|E)SI to byte at address (R|E)DI.      
|           |              |      |            |                | The status flags are set accordingly.    
| A7        | CMPS m16, m16| NP   | Valid      | Valid          | For legacy mode, compare word at address 
|           |              |      |            |                | DS:(E)SI with word at address ES:(E)DI;  
|           |              |      |            |                | For 64bit mode compare word at address   
|           |              |      |            |                | (R|E)SI with word at address (R|E)DI.    
|           |              |      |            |                | The status flags are set accordingly.    
| A7        | CMPS m32, m32| NP   | Valid      | Valid          | For legacy mode, compare dword at address
|           |              |      |            |                | DS:(E)SI at dword at address ES:(E)DI;   
|           |              |      |            |                | For 64bit mode compare dword at address  
|           |              |      |            |                | (R|E)SI at dword at address (R|E)DI.     
|           |              |      |            |                | The status flags are set accordingly.    
| REX.W + A7| CMPS m64, m64| NP   | Valid      | N.E.           | Compares quadword at address (R|E)SI     
|           |              |      |            |                | with quadword at address (R|E)DI and     
|           |              |      |            |                | sets the status flags accordingly.       
| A6        | CMPSB        | NP   | Valid      | Valid          | For legacy mode, compare byte at address 
|           |              |      |            |                | DS:(E)SI with byte at address ES:(E)DI;  
|           |              |      |            |                | For 64bit mode compare byte at address   
|           |              |      |            |                | (R|E)SI with byte at address (R|E)DI.    
|           |              |      |            |                | The status flags are set accordingly.    
| A7        | CMPSW        | NP   | Valid      | Valid          | For legacy mode, compare word at address 
|           |              |      |            |                | DS:(E)SI with word at address ES:(E)DI;  
|           |              |      |            |                | For 64bit mode compare word at address   
|           |              |      |            |                | (R|E)SI with word at address (R|E)DI.    
|           |              |      |            |                | The status flags are set accordingly.    
| A7        | CMPSD        | NP   | Valid      | Valid          | For legacy mode, compare dword at address
|           |              |      |            |                | DS:(E)SI with dword at address ES:(E)DI; 
|           |              |      |            |                | For 64-bit mode compare dword at address 
|           |              |      |            |                | (R|E)SI with dword at address (R|E)DI.   
|           |              |      |            |                | The status flags are set accordingly.    
| REX.W + A7| CMPSQ        | NP   | Valid      | N.E.           | Compares quadword at address (R|E)SI     
|           |              |      |            |                | with quadword at address (R|E)DI and     
|           |              |      |            |                | sets the status flags accordingly.       

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Compares the byte, word, doubleword, or quadword specified with the first source
operand with the byte, word, doubleword, or quadword specified with the second
source operand and sets the status flags in the EFLAGS register according to
the results.

Both source operands are located in memory. The address of the first source
operand is read from DS:SI, DS:ESI or RSI (depending on the address-size attribute
of the instruction is 16, 32, or 64, respectively). The address of the second
source operand is read from ES:DI, ES:EDI or RDI (again depending on the address-size
attribute of the

instruction is 16, 32, or 64). The DS segment may be overridden with a segment
override prefix, but the ES segment cannot be overridden.

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands”
form and the “nooperands” form. The explicit-operands form (specified with the
CMPS mnemonic) allows the two source operands to be specified explicitly. Here,
the source operands should be symbols that indicate the size and location of
the source values. This explicit-operand form is provided to allow documentation.
However, note that the documentation provided by this form can be misleading.
That is, the source operand symbols must specify the correct type (size) of
the operands (bytes, words, or doublewords, quadwords), but they do not have
to specify the correct location. Locations of the source operands are always
specified by the DS:(E)SI (or RSI) and ES:(E)DI (or RDI) registers, which must
be loaded correctly before the compare string instruction is executed.

The no-operands form provides “short forms” of the byte, word, and doubleword
versions of the CMPS instructions. Here also the DS:(E)SI (or RSI) and ES:(E)DI
(or RDI) registers are assumed by the processor to specify the location of the
source operands. The size of the source operands is selected with the mnemonic:
CMPSB (byte comparison), CMPSW (word comparison), CMPSD (doubleword comparison),
or CMPSQ (quadword comparison using REX.W).

After the comparison, the (E/R)SI and (E/R)DI registers increment or decrement
automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E/R)SI and (E/R)DI register increment; if the DF
flag is 1, the registers decrement.) The registers increment or decrement by
1 for byte operations, by 2 for word operations, 4 for doubleword operations.
If operand size is 64, RSI and RDI registers increment by 8 for quadword operations.

The CMPS, CMPSB, CMPSW, CMPSD, and CMPSQ instructions can be preceded by the
REP prefix for block comparisons. More often, however, these instructions will
be used in a LOOP construct that takes some action based on the setting of the
status flags before the next comparison is made. See “REP/REPE/REPZ /REPNE/REPNZ - Repeat
String Operation Prefix” in Chapter 4 of the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 2B, for a description of the REP prefix.

In 64-bit mode, the instruction's default address size is 64 bits, 32 bit address
size is supported using the prefix 67H. Use of the REX.W prefix promotes doubleword
operation to 64 bits (see CMPSQ). See the summary chart at the beginning of
this section for encoding data and limits.

Operation:

temp <- SRC1 - SRC2;
SetStatusFlags(temp);
IF (64-Bit Mode)
  THEN
     IF (Byte comparison)
     THEN IF DF = 0
       THEN
          (R|E)SI <- (R|E)SI + 1;
          (R|E)DI <- (R|E)DI + 1;
       ELSE
          (R|E)SI <- (R|E)SI - 1;
          (R|E)DI <- (R|E)DI - 1;
       FI;
     ELSE IF (Word comparison)
       THEN IF DF = 0
          THEN
             (R|E)SI <- (R|E)SI + 2;
             (R|E)DI <- (R|E)DI + 2;
          ELSE
             (R|E)SI <- (R|E)SI - 2;
             (R|E)DI <- (R|E)DI - 2;
          FI;
     ELSE IF (Doubleword comparison)
       THEN IF DF = 0
          THEN
             (R|E)SI <- (R|E)SI + 4;
             (R|E)DI <- (R|E)DI + 4;
          ELSE
             (R|E)SI <- (R|E)SI - 4;
             (R|E)DI <- (R|E)DI - 4;
          FI;
     ELSE (* Quadword comparison *)
       THEN IF DF = 0
          (R|E)SI <- (R|E)SI + 8;
          (R|E)DI <- (R|E)DI + 8;
       ELSE
          (R|E)SI <- (R|E)SI - 8;
          (R|E)DI <- (R|E)DI - 8;
       FI;
     FI;
  ELSE (* Non-64-bit Mode *)
     IF (byte comparison)
     THEN IF DF = 0
       THEN
          (E)SI <- (E)SI + 1;
          (E)DI <- (E)DI + 1;
       ELSE
          (E)SI <- (E)SI - 1;
          (E)DI <- (E)DI - 1;
       FI;
     ELSE IF (Word comparison)
       THEN IF DF = 0
          (E)SI <- (E)SI + 2;
          (E)DI <- (E)DI + 2;
       ELSE
          (E)SI <- (E)SI - 2;
          (E)DI <- (E)DI - 2;
       FI;
     ELSE (* Doubleword comparison *)
       THEN IF DF = 0
          (E)SI <- (E)SI + 4;
          (E)DI <- (E)DI + 4;
       ELSE
          (E)SI <- (E)SI - 4;
          (E)DI <- (E)DI - 4;
       FI;
     FI;
FI;

Flags Affected:
The CF, OF, SF, ZF, AF, and PF flags are set according to the temporary result
of the comparison.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: CMPSD
description:
CMPSD - Compare Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F2 0F C2 /r ib CMPSD xmm1, xmm2/m64, | RMI  | V/V           | SSE2              | Compare low double-precision floating-point
| imm8                                 |      |               |                   | value in xmm2/m64 and xmm1 using imm8      
|                                      |      |               |                   | as comparison predicate.                   
| VEX.NDS.LIG.F2.0F.WIG C2 /r ib VCMPSD| RVMI | V/V           | AVX               | Compare low double precision floating-point
| xmm1, xmm2, xmm3/m64, imm8           |      |               |                   | value in xmm3/m64 and xmm2 using bits      
|                                      |      |               |                   | 4:0 of imm8 as comparison predicate.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Compares the low double-precision floating-point values in the source operand
(second operand) and the destination operand (first operand) and returns the
results of the comparison to the destination operand. The comparison predicate
operand (third operand) specifies the type of comparison performed. The comparison
result is a quadword mask of all 1s (comparison true) or all 0s (comparison
false). The sign of zero is ignored for comparisons, so that -0.0 is equal to
+0.0. 128-bit Legacy SSE version: The first source and destination operand (first
operand) is an XMM register. The second source operand (second operand) can
be an XMM register or 64-bit memory location. The comparison predicate operand
is an 8-bit immediate, bits 2:0 of the immediate define the type of comparison
to be performed (see Table 3-7). Bits 7:3 of the immediate is reserved. Bits
(VLMAX-1:64) of the corresponding YMM destination register remain unchanged.

The unordered relationship is true when at least one of the two source operands
being compared is a NaN; the ordered relationship is true when neither source
operand is a NaN.

A subsequent computational instruction that uses the mask result in the destination
operand as an input operand will not generate a fault, because a mask of all
0s corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds
to a QNaN.

Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”,
“greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal
relations” predicates. These comparisons can be made either by using the inverse
relationship (that is, use the “not-less-than-or-equal” to make a “greater-than”
comparison) or by using software emulation. When using software emulation, the
program must swap the operands (copying registers when necessary to protect
the data that will now be in the destination operand), and then perform the
compare using a different predicate. The predicate to be used for these emulations
is listed in Table 3-7 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops
in addition to the three-operand CMPSD instruction, for processors with “CPUID.1H:ECX.AVX
=0”. See Table 3-13. Compiler should treat reserved Imm8 values as illegal syntax.


Table 3-13. Pseudo-Ops and CMPSD:
| Pseudo-Op            | Implementation    
| CMPEQSD xmm1, xmm2   | CMPSD xmm1,xmm2, 0
| CMPLTSD xmm1, xmm2   | CMPSD xmm1,xmm2, 1
| CMPLESD xmm1, xmm2   | CMPSD xmm1,xmm2, 2
| CMPUNORDSD xmm1, xmm2| CMPSD xmm1,xmm2, 3
| CMPNEQSD xmm1, xmm2  | CMPSD xmm1,xmm2, 4
| CMPNLTSD xmm1, xmm2  | CMPSD xmm1,xmm2, 5
| CMPNLESD xmm1, xmm2  | CMPSD xmm1,xmm2, 6
| CMPORDSD xmm1, xmm2  | CMPSD xmm1,xmm2, 7
The greater-than relations not implemented in the processor require more than
one instruction to emulate in software and therefore should not be implemented
as pseudo-ops. (For these, the programmer should reverse the operands of the
corresponding less than relations and use move instructions to ensure that the
mask is moved to the correct destination register and that the source operand
is left intact.)

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Enhanced Comparison Predicate for VEX-Encoded VCMPSD VEX.128 encoded version:
The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 64-bit memory location.
Bits (VLMAX-1:128) of the destination YMM register are zeroed. The comparison
predicate operand is an 8-bit immediate:

 - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison
to be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.

Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates
shown in Table 3-9, software emulation is no longer needed. Compilers and assemblers
may implement the following three-operand pseudo-ops in addition to the four-operand
VCMPSD instruction. See Table 3-14, where the notations of reg1 reg2, and reg3
represent either XMM registers or YMM registers. Compiler should treat reserved
Imm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops
to pre-defined constants to support a simpler intrinsic interface.

| : Pseudo-Op VCMPEQSD reg1, reg2, reg3          | Table 3-14. Table 3-14.| Pseudo-Op and VCMPSD Implementation      
| VCMPLTSD reg1, reg2, reg3 VCMPLESD reg1,       |                        | CMPSD Implementation VCMPSD reg1, reg2,  
| reg2, reg3 VCMPUNORDSD reg1, reg2, reg3        |                        | reg3, 0 VCMPSD reg1, reg2, reg3, 1 VCMPSD
| VCMPNEQSD reg1, reg2, reg3 VCMPNLTSD           |                        | reg1, reg2, reg3, 2 VCMPSD reg1, reg2,   
| reg1, reg2, reg3 VCMPNLESD reg1, reg2,         |                        | reg3, 3 VCMPSD reg1, reg2, reg3, 4 VCMPSD
| reg3 VCMPORDSD reg1, reg2, reg3 VCMPEQ_UQSD    |                        | reg1, reg2, reg3, 5 VCMPSD reg1, reg2,   
| reg1, reg2, reg3 VCMPNGESD reg1, reg2,         |                        | reg3, 6 VCMPSD reg1, reg2, reg3, 7 VCMPSD
| reg3 VCMPNGTSD reg1, reg2, reg3 VCMPFALSESD    |                        | reg1, reg2, reg3, 8 VCMPSD reg1, reg2,   
| reg1, reg2, reg3 VCMPNEQ_OQSD reg1,            |                        | reg3, 9 VCMPSD reg1, reg2, reg3, 0AH     
| reg2, reg3 VCMPGESD reg1, reg2, reg3           |                        | VCMPSD reg1, reg2, reg3, 0BH VCMPSD      
| VCMPGTSD reg1, reg2, reg3 Pseudo-Op            |                        | reg1, reg2, reg3, 0CH VCMPSD reg1, reg2, 
| VCMPTRUESD reg1, reg2, reg3 VCMPEQ_OSSD        |                        | reg3, 0DH VCMPSD reg1, reg2, reg3, 0EH   
| reg1, reg2, reg3 VCMPLT_OQSD reg1, reg2,       |                        | Pseudo-Op and VCMPSD Implementation      
| reg3 VCMPLE_OQSD reg1, reg2, reg3 VCMPUNORD_SSD|                        | (Contd.) CMPSD Implementation VCMPSD     
| reg1, reg2, reg3 VCMPNEQ_USSD reg1,            |                        | reg1, reg2, reg3, 0FH VCMPSD reg1, reg2, 
| reg2, reg3 VCMPNLT_UQSD reg1, reg2,            |                        | reg3, 10H VCMPSD reg1, reg2, reg3, 11H   
| reg3 VCMPNLE_UQSD reg1, reg2, reg3 VCMPORD_SSD |                        | VCMPSD reg1, reg2, reg3, 12H VCMPSD      
| reg1, reg2, reg3 VCMPEQ_USSD reg1, reg2,       |                        | reg1, reg2, reg3, 13H VCMPSD reg1, reg2, 
| reg3 VCMPNGE_UQSD reg1, reg2, reg3 VCMPNGT_UQSD|                        | reg3, 14H VCMPSD reg1, reg2, reg3, 15H   
| reg1, reg2, reg3 VCMPFALSE_OSSD reg1,          |                        | VCMPSD reg1, reg2, reg3, 16H VCMPSD      
| reg2, reg3 VCMPNEQ_OSSD reg1, reg2,            |                        | reg1, reg2, reg3, 17H VCMPSD reg1, reg2, 
| reg3 VCMPGE_OQSD reg1, reg2, reg3 VCMPGT_OQSD  |                        | reg3, 18H VCMPSD reg1, reg2, reg3, 19H   
| reg1, reg2, reg3 VCMPTRUE_USSD reg1,           |                        | VCMPSD reg1, reg2, reg3, 1AH VCMPSD      
| reg2, reg3                                     |                        | reg1, reg2, reg3, 1BH VCMPSD reg1, reg2, 
|                                                |                        | reg3, 1CH VCMPSD reg1, reg2, reg3, 1DH   
|                                                |                        | VCMPSD reg1, reg2, reg3, 1EH VCMPSD      
|                                                |                        | reg1, reg2, reg3, 1FH                    
Operation:

CASE (COMPARISON PREDICATE) OF
  0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;
  1: OP3 <- LT_OS; OP5 <- LT_OS;
  2: OP3 <- LE_OS; OP5 <- LE_OS;
  3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;
  4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;
  5: OP3 <- NLT_US; OP5 <- NLT_US;
  6: OP3 <- NLE_US; OP5 <- NLE_US;
  7: OP3 <- ORD_Q; OP5 <- ORD_Q;
  8: OP5 <- EQ_UQ;
  9: OP5 <- NGE_US;
  10: OP5 <- NGT_US;
  11: OP5 <- FALSE_OQ;
  12: OP5 <- NEQ_OQ;
  13: OP5 <- GE_OS;
  14: OP5 <- GT_OS;
  15: OP5 <- TRUE_UQ;
  16: OP5 <- EQ_OS;
  17: OP5 <- LT_OQ;
  18: OP5 <- LE_OQ;
  19: OP5 <- UNORD_S;
  20: OP5 <- NEQ_US;
  21: OP5 <- NLT_UQ;
  22: OP5 <- NLE_UQ;
  23: OP5 <- ORD_S;
  24: OP5 <- EQ_US;
  25: OP5 <- NGE_UQ;
  26: OP5 <- NGT_UQ;
  27: OP5 <- FALSE_OS;
  28: OP5 <- NEQ_OS;
  29: OP5 <- GE_OQ;
  30: OP5 <- GT_OQ;
  31: OP5 <- TRUE_US;
  DEFAULT: Reserved
ESAC;
CMPSD (128-bit Legacy SSE version)
CMP0 <- DEST[63:0] OP3 SRC[63:0];
IF CMP0 = TRUE
THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] <- 0000000000000000H; FI;
DEST[VLMAX-1:64] (Unmodified)
VCMPSD (VEX.128 encoded version)
CMP0 <- SRC1[63:0] OP5 SRC2[63:0];
IF CMP0 = TRUE
THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
ELSE DEST[63:0] <- 0000000000000000H; FI;
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalents:
| CMPSD for equality:                                     | __m128d _mm_cmpeq_sd(__m128d a, __m128d   
|                                                         | b)                                        
| CMPSD for less-than:                                    | __m128d _mm_cmplt_sd(__m128d a, __m128d   
|                                                         | b)                                        
| CMPSD for less-than-or-equal:                           | __m128d _mm_cmple_sd(__m128d a, __m128d   
|                                                         | b)                                        
| CMPSD for greater-than:                                 | __m128d _mm_cmpgt_sd(__m128d a, __m128d   
|                                                         | b)                                        
| CMPSD for greater-than-or-equal:                        | __m128d _mm_cmpge_sd(__m128d a, __m128d   
|                                                         | b)                                        
| CMPSD for inequality:                                   | __m128d _mm_cmpneq_sd(__m128d a, __m128d  
|                                                         | b)                                        
| CMPSD for not-less-than:                                | __m128d _mm_cmpnlt_sd(__m128d a, __m128d  
|                                                         | b)                                        
| CMPSD for not-greater-than: CMPSD for                   | __m128d _mm_cmpngt_sd(__m128d a, __m128d  
| not-greater-than-or-equal: __m128d _mm_cmpnge_sd(__m128d| b)                                        
| a, __m128d b)                                           |                                           
| CMPSD for ordered:                                      | __m128d _mm_cmpord_sd(__m128d a, __m128d  
|                                                         | b)                                        
| CMPSD for unordered:                                    | __m128d _mm_cmpunord_sd(__m128d a, __m128d
|                                                         | b)                                        
| CMPSD for not-less-than-or-equal:                       | __m128d _mm_cmpnle_sd(__m128d a, __m128d  
|                                                         | b)                                        
| VCMPSD:                                                 | __m128 _mm_cmp_sd(__m128 a, __m128 b,     
|                                                         | const int imm)                            

SIMD Floating-Point Exceptions:
Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,
Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CMPSS
description:
CMPSS - Compare Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| F3 0F C2 /r ib CMPSS xmm1, xmm2/m32, | RMI  | V/V           | SSE               | Compare low single-precision floating-point
| imm8                                 |      |               |                   | value in xmm2/m32 and xmm1 using imm8      
|                                      |      |               |                   | as comparison predicate.                   
| VEX.NDS.LIG.F3.0F.WIG C2 /r ib VCMPSS| RVMI | V/V           | AVX               | Compare low single precision floating-point
| xmm1, xmm2, xmm3/m32, imm8           |      |               |                   | value in xmm3/m32 and xmm2 using bits      
|                                      |      |               |                   | 4:0 of imm8 as comparison predicate.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Compares the low single-precision floating-point values in the source operand
(second operand) and the destination operand (first operand) and returns the
results of the comparison to the destination operand. The comparison predicate
operand (third operand) specifies the type of comparison performed. The comparison
result is a doubleword mask of all 1s (comparison true) or all 0s (comparison
false). The sign of zero is ignored for comparisons, so that -0.0 is equal to
+0.0. 128-bit Legacy SSE version: The first source and destination operand (first
operand) is an XMM register. The second source operand (second operand) can
be an XMM register or 64-bit memory location. The comparison predicate operand
is an 8-bit immediate, bits 2:0 of the immediate define the type of comparison
to be performed (see Table 3-7). Bits 7:3 of the immediate is reserved. Bits
(VLMAX-1:32) of the corresponding YMM destination register remain unchanged.

The unordered relationship is true when at least one of the two source operands
being compared is a NaN; the ordered relationship is true when neither source
operand is a NaN

A subsequent computational instruction that uses the mask result in the destination
operand as an input operand will not generate a fault, since a mask of all 0s
corresponds to a floating-point value of +0.0 and a mask of all 1s corresponds
to a QNaN.

Note that processors with “CPUID.1H:ECX.AVX =0” do not implement the “greater-than”,
“greater-than-or-equal”, “not-greater than”, and “not-greater-than-or-equal
relations” predicates. These comparisons can be made either by using the inverse
relationship (that is, use the “not-less-than-or-equal” to make a “greater-than”
comparison) or by using software emulation. When using software emulation, the
program must swap the operands (copying registers when necessary to protect
the data that will now be in the destination operand), and then perform the
compare using a different predicate. The predicate to be used for these emulations
is listed in Table 3-7 under the heading Emulation.

Compilers and assemblers may implement the following two-operand pseudo-ops
in addition to the three-operand CMPSS instruction, for processors with “CPUID.1H:ECX.AVX
=0”. See Table 3-15. Compiler should treat reserved Imm8 values as illegal syntax.


Table 3-15. Pseudo-Ops and CMPSS:
| Pseudo-Op            | CMPSS Implementation
| CMPEQSS xmm1, xmm2   | CMPSS xmm1, xmm2, 0 
| CMPLTSS xmm1, xmm2   | CMPSS xmm1, xmm2, 1 
| CMPLESS xmm1, xmm2   | CMPSS xmm1, xmm2, 2 
| CMPUNORDSS xmm1, xmm2| CMPSS xmm1, xmm2, 3 
| CMPNEQSS xmm1, xmm2  | CMPSS xmm1, xmm2, 4 
| CMPNLTSS xmm1, xmm2  | CMPSS xmm1, xmm2, 5 
| CMPNLESS xmm1, xmm2  | CMPSS xmm1, xmm2, 6 
| CMPORDSS xmm1, xmm2  | CMPSS xmm1, xmm2, 7 
The greater-than relations not implemented in the processor require more than
one instruction to emulate in software and therefore should not be implemented
as pseudo-ops. (For these, the programmer should reverse the operands of the
corresponding less than relations and use move instructions to ensure that the
mask is moved to the correct destination register and that the source operand
is left intact.)

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Enhanced Comparison Predicate for VEX-Encoded VCMPSD VEX.128 encoded version:
The first source operand (second operand) is an XMM register. The second source
operand (third operand) can be an XMM register or a 32-bit memory location.
Bits (VLMAX-1:128) of the destination YMM register are zeroed. The comparison
predicate operand is an 8-bit immediate:

 - For instructions encoded using the VEX prefix, bits 4:0 define the type of comparison
to be performed (see Table 3-9). Bits 5 through 7 of the immediate are reserved.

Processors with “CPUID.1H:ECX.AVX =1” implement the full complement of 32 predicates
shown in Table 3-9, software emulation is no longer needed. Compilers and assemblers
may implement the following three-operand pseudo-ops in addition to the four-operand
VCMPSS instruction. See Table 3-16, where the notations of reg1 reg2, and reg3
represent either XMM registers or YMM registers. Compiler should treat reserved
Imm8 values as illegal syntax. Alternately, intrinsics can map the pseudo-ops
to pre-defined constants to support a simpler intrinsic interface.

| : Pseudo-Op VCMPEQSS reg1, reg2, reg3          | Table 3-16. Table 3-16.| Pseudo-Op and VCMPSS Implementation      
| VCMPLTSS reg1, reg2, reg3 VCMPLESS reg1,       |                        | CMPSS Implementation VCMPSS reg1, reg2,  
| reg2, reg3 VCMPUNORDSS reg1, reg2, reg3        |                        | reg3, 0 VCMPSS reg1, reg2, reg3, 1 VCMPSS
| VCMPNEQSS reg1, reg2, reg3 VCMPNLTSS           |                        | reg1, reg2, reg3, 2 VCMPSS reg1, reg2,   
| reg1, reg2, reg3 VCMPNLESS reg1, reg2,         |                        | reg3, 3 VCMPSS reg1, reg2, reg3, 4 VCMPSS
| reg3 VCMPORDSS reg1, reg2, reg3 VCMPEQ_UQSS    |                        | reg1, reg2, reg3, 5 VCMPSS reg1, reg2,   
| reg1, reg2, reg3 VCMPNGESS reg1, reg2,         |                        | reg3, 6 VCMPSS reg1, reg2, reg3, 7 VCMPSS
| reg3 VCMPNGTSS reg1, reg2, reg3 VCMPFALSESS    |                        | reg1, reg2, reg3, 8 VCMPSS reg1, reg2,   
| reg1, reg2, reg3 VCMPNEQ_OQSS reg1,            |                        | reg3, 9 VCMPSS reg1, reg2, reg3, 0AH     
| reg2, reg3 VCMPGESS reg1, reg2, reg3           |                        | VCMPSS reg1, reg2, reg3, 0BH VCMPSS      
| VCMPGTSS reg1, reg2, reg3 Pseudo-Op            |                        | reg1, reg2, reg3, 0CH VCMPSS reg1, reg2, 
| VCMPTRUESS reg1, reg2, reg3 VCMPEQ_OSSS        |                        | reg3, 0DH VCMPSS reg1, reg2, reg3, 0EH   
| reg1, reg2, reg3 VCMPLT_OQSS reg1, reg2,       |                        | Pseudo-Op and VCMPSS Implementation      
| reg3 VCMPLE_OQSS reg1, reg2, reg3 VCMPUNORD_SSS|                        | (Contd.) CMPSS Implementation VCMPSS     
| reg1, reg2, reg3 VCMPNEQ_USSS reg1,            |                        | reg1, reg2, reg3, 0FH VCMPSS reg1, reg2, 
| reg2, reg3 VCMPNLT_UQSS reg1, reg2,            |                        | reg3, 10H VCMPSS reg1, reg2, reg3, 11H   
| reg3 VCMPNLE_UQSS reg1, reg2, reg3 VCMPORD_SSS |                        | VCMPSS reg1, reg2, reg3, 12H VCMPSS      
| reg1, reg2, reg3 VCMPEQ_USSS reg1, reg2,       |                        | reg1, reg2, reg3, 13H VCMPSS reg1, reg2, 
| reg3 VCMPNGE_UQSS reg1, reg2, reg3 VCMPNGT_UQSS|                        | reg3, 14H VCMPSS reg1, reg2, reg3, 15H   
| reg1, reg2, reg3 VCMPFALSE_OSSS reg1,          |                        | VCMPSS reg1, reg2, reg3, 16H VCMPSS      
| reg2, reg3 VCMPNEQ_OSSS reg1, reg2,            |                        | reg1, reg2, reg3, 17H VCMPSS reg1, reg2, 
| reg3 VCMPGE_OQSS reg1, reg2, reg3 VCMPGT_OQSS  |                        | reg3, 18H VCMPSS reg1, reg2, reg3, 19H   
| reg1, reg2, reg3 VCMPTRUE_USSS reg1,           |                        | VCMPSS reg1, reg2, reg3, 1AH VCMPSS      
| reg2, reg3                                     |                        | reg1, reg2, reg3, 1BH VCMPSS reg1, reg2, 
|                                                |                        | reg3, 1CH VCMPSS reg1, reg2, reg3, 1DH   
|                                                |                        | VCMPSS reg1, reg2, reg3, 1EH VCMPSS      
|                                                |                        | reg1, reg2, reg3, 1FH                    
Operation:

CASE (COMPARISON PREDICATE) OF
  0: OP3 <- EQ_OQ; OP5 <- EQ_OQ;
  1: OP3 <- LT_OS; OP5 <- LT_OS;
  2: OP3 <- LE_OS; OP5 <- LE_OS;
  3: OP3 <- UNORD_Q; OP5 <- UNORD_Q;
  4: OP3 <- NEQ_UQ; OP5 <- NEQ_UQ;
  5: OP3 <- NLT_US; OP5 <- NLT_US;
  6: OP3 <- NLE_US; OP5 <- NLE_US;
  7: OP3 <- ORD_Q; OP5 <- ORD_Q;
  8: OP5 <- EQ_UQ;
  9: OP5 <- NGE_US;
  10: OP5 <- NGT_US;
  11: OP5 <- FALSE_OQ;
  12: OP5 <- NEQ_OQ;
  13: OP5 <- GE_OS;
  14: OP5 <- GT_OS;
  15: OP5 <- TRUE_UQ;
  16: OP5 <- EQ_OS;
  17: OP5 <- LT_OQ;
  18: OP5 <- LE_OQ;
  19: OP5 <- UNORD_S;
  20: OP5 <- NEQ_US;
  21: OP5 <- NLT_UQ;
  22: OP5 <- NLE_UQ;
  23: OP5 <- ORD_S;
  24: OP5 <- EQ_US;
  25: OP5 <- NGE_UQ;
  26: OP5 <- NGT_UQ;
  27: OP5 <- FALSE_OS;
  28: OP5 <- NEQ_OS;
  29: OP5 <- GE_OQ;
  30: OP5 <- GT_OQ;
  31: OP5 <- TRUE_US;
  DEFAULT: Reserved
ESAC;
CMPSS (128-bit Legacy SSE version)
CMP0 <- DEST[31:0] OP3 SRC[31:0];
IF CMP0 = TRUE
THEN DEST[31:0] <- FFFFFFFFH;
ELSE DEST[31:0] <- 00000000H; FI;
DEST[VLMAX-1:32] (Unmodified)
VCMPSS (VEX.128 encoded version)
CMP0 <- SRC1[31:0] OP5 SRC2[31:0];
IF CMP0 = TRUE
THEN DEST[31:0] <- FFFFFFFFH;
ELSE DEST[31:0] <- 00000000H; FI;
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalents:
| CMPSS for equality:                                   | __m128 _mm_cmpeq_ss(__m128 a, __m128   
|                                                       | b)                                     
| CMPSS for less-than:                                  | __m128 _mm_cmplt_ss(__m128 a, __m128   
|                                                       | b)                                     
| CMPSS for less-than-or-equal:                         | __m128 _mm_cmple_ss(__m128 a, __m128   
|                                                       | b)                                     
| CMPSS for greater-than:                               | __m128 _mm_cmpgt_ss(__m128 a, __m128   
|                                                       | b)                                     
| CMPSS for greater-than-or-equal:                      | __m128 _mm_cmpge_ss(__m128 a, __m128   
|                                                       | b)                                     
| CMPSS for inequality:                                 | __m128 _mm_cmpneq_ss(__m128 a, __m128  
|                                                       | b)                                     
| CMPSS for not-less-than:                              | __m128 _mm_cmpnlt_ss(__m128 a, __m128  
|                                                       | b)                                     
| CMPSS for not-greater-than: CMPSS for                 | __m128 _mm_cmpngt_ss(__m128 a, __m128  
| not-greater-than-or-equal: __m128 _mm_cmpnge_ss(__m128| b)                                     
| a, __m128 b)                                          |                                        
| CMPSS for ordered:                                    | __m128 _mm_cmpord_ss(__m128 a, __m128  
|                                                       | b)                                     
| CMPSS for unordered:                                  | __m128 _mm_cmpunord_ss(__m128 a, __m128
|                                                       | b)                                     
| CMPSS for not-less-than-or-equal:                     | __m128 _mm_cmpnle_ss(__m128 a, __m128  
|                                                       | b)                                     
| VCMPSS:                                               | __m128 _mm_cmp_ss(__m128 a, __m128 b,  
|                                                       | const int imm)                         

SIMD Floating-Point Exceptions:
Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,
Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: CMPXCHG
description:
CMPXCHG - Compare and Exchange:
| Opcode/Instruction                | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F B0/r CMPXCHG r/m8, r8          | MR   | Valid      | Valid*         | Compare AL with r/m8. If equal, ZF is  
|                                   |      |            |                | set and r8 is loaded into r/m8. Else,  
|                                   |      |            |                | clear ZF and load r/m8 into AL.        
| REX + 0F B0/r CMPXCHG r/m8**,r8   | MR   | Valid      | N.E.           | Compare AL with r/m8. If equal, ZF is  
|                                   |      |            |                | set and r8 is loaded into r/m8. Else,  
|                                   |      |            |                | clear ZF and load r/m8 into AL.        
| 0F B1/r CMPXCHG r/m16, r16        | MR   | Valid      | Valid*         | Compare AX with r/m16. If equal, ZF    
|                                   |      |            |                | is set and r16 is loaded into r/m16.   
|                                   |      |            |                | Else, clear ZF and load r/m16 into AX. 
| 0F B1/r CMPXCHG r/m32, r32        | MR   | Valid      | Valid*         | Compare EAX with r/m32. If equal, ZF   
|                                   |      |            |                | is set and r32 is loaded into r/m32.   
|                                   |      |            |                | Else, clear ZF and load r/m32 into EAX.
| REX.W + 0F B1/r CMPXCHG r/m64, r64| MR   | Valid      | N.E.           | Compare RAX with r/m64. If equal, ZF   
|                                   |      |            |                | is set and r64 is loaded into r/m64.   
|                                   |      |            |                | Else, clear ZF and load r/m64 into RAX.
Notes: * See the IA-32 Architecture Compatibility section below. ** In 64-bit
mode, r/m8 can not be encoded to access the following byte registers if a REX
prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       

Description:
Compares the value in the AL, AX, EAX, or RAX register with the first operand
(destination operand). If the two values are equal, the second operand (source
operand) is loaded into the destination operand. Otherwise, the destination
operand is loaded into the AL, AX, EAX or RAX register. RAX register is available
only in 64-bit mode.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically. To simplify the interface to the processor's bus, the
destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails;
otherwise, the source operand is written into the destination. (The processor
never produces a locked read without also producing a locked write.)

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning
of this section for encoding data and limits.


IA-32 Architecture Compatibility:
This instruction is not supported on Intel processors earlier than the Intel486
processors.

Operation:

(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)
TEMP <- DEST
IF accumulator = TEMP
  THEN
     ZF <- 1;
     DEST <- SRC;
  ELSE
     ZF <- 0;
     accumulator <- TEMP;
     DEST <- TEMP;
FI;

Flags Affected:
The ZF flag is set if the values in the destination operand and register AL,
AX, or EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags
are set according to the results of the comparison operation.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used but the destination 
|                | is not a memory operand.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: CMPXCHG8B
description:
CMPXCHG8B/CMPXCHG16B - Compare and Exchange Bytes:
| Opcode/Instruction                   | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F C7 /1 m64 CMPXCHG8B m64           | M    | Valid      | Valid*         | Compare EDX:EAX with m64. If equal,     
|                                      |      |            |                | set ZF and load ECX:EBX into m64. Else, 
|                                      |      |            |                | clear ZF and load m64 into EDX:EAX.     
| REX.W + 0F C7 /1 m128 CMPXCHG16B m128| M    | Valid      | N.E.           | Compare RDX:RAX with m128. If equal,    
|                                      |      |            |                | set ZF and load RCX:RBX into m128. Else,
|                                      |      |            |                | clear ZF and load m128 into RDX:RAX.    
Notes: *See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r, w)| NA       | NA       | NA       

Description:
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand
size is 128 bits) with the operand (destination operand). If the values are
equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored in
the destination operand. Otherwise, the value in the destination operand is
loaded into EDX:EAX (or RDX:RAX). The destination operand is an 8-byte memory
location (or 16-byte memory location if operand size is 128 bits). For the EDX:EAX
and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX
and EBX contain the low-order 32 bits of a 64-bit value. For the RDX:RAX and
RCX:RBX register pairs, RDX and RCX contain the highorder 64 bits and RAX and
RBX contain the low-order 64bits of a 128-bit value.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically. To simplify the interface to the processor's bus, the
destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails;
otherwise, the source operand is written into the destination. (The processor
never produces a locked read without also producing a locked write.)

In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes
operation to 128 bits. Note that CMPXCHG16B requires that the destination (memory)
operand be 16-byte aligned. See the summary chart at the beginning of this section
for encoding data and limits. For information on the CPUID flag that indicates
CMPXCHG16B, see page 3-170.


IA-32 Architecture Compatibility:
This instruction encoding is not supported on Intel processors earlier than
the Pentium processors.

Operation:

IF (64-Bit Mode and OperandSize = 64)
  THEN
     TEMP128 <- DEST
     IF (RDX:RAX = TEMP128)
       THEN
          ZF <- 1;
          DEST <- RCX:RBX;
       ELSE
          ZF <- 0;
          RDX:RAX <- TEMP128;
          DEST <- TEMP128;
          FI;
     FI
  ELSE
     TEMP64 <- DEST;
     IF (EDX:EAX = TEMP64)
       THEN
          ZF <- 1;
          DEST <- ECX:EBX;
       ELSE
          ZF <- 0;
          EDX:EAX <- TEMP64;
          DEST <- TEMP64;
          FI;
     FI;
FI;

Flags Affected:
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise
it is cleared. The CF, PF, AF, SF, and OF flags are unaffected.


Protected Mode Exceptions:
| #UD            | If the destination is not a memory operand.    
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             

Real-Address Mode Exceptions:
| #UD| If the destination operand is not a  
|    | memory location.                     
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     

Virtual-8086 Mode Exceptions:
| #UD            | If the destination operand is not a   
|                | memory location.                      
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form. If memory operand for CMPXCHG16B     
|                | is not aligned on a 16-byte boundary.      
|                | If CPUID.01H:ECX.CMPXCHG16B[bit 13]        
|                | = 0.                                       
| #UD            | If the destination operand is not a        
|                | memory location.                           
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: COMISD
description:
COMISD - Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS:
| Opcode/Instruction                   | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 66 0F 2F /r COMISD xmm1, xmm2/m64    | RM   | V/V           | SSE2              | Compare low double-precision floating-point
|                                      |      |               |                   | values in xmm1 and xmm2/mem64 and set      
|                                      |      |               |                   | the EFLAGS flags accordingly.              
| VEX.LIG.66.0F.WIG 2F /r VCOMISD xmm1,| RM   | V/V           | AVX               | Compare low double precision floating-point
| xmm2/m64                             |      |               |                   | values in xmm1 and xmm2/mem64 and set      
|                                      |      |               |                   | the EFLAGS flags accordingly.              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
Compares the double-precision floating-point values in the low quadwords of
operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF,
and CF flags in the EFLAGS register according to the result (unordered, greater
than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are
set to 0. The unordered result is returned if either source operand is a NaN
(QNaN or SNaN).The sign of zero is ignored for comparisons, so that -0.0 is
equal to +0.0.

Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location.

The COMISD instruction differs from the UCOMISD instruction in that it signals
a SIMD floating-point invalid operation exception (#I) when a source operand
is either a QNaN or SNaN. The UCOMISD instruction signals an invalid numeric
exception only if a source operand is an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception
is generated.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). Note: In VEX-encoded versions, VEX.vvvv is reserved
and must be 1111b, otherwise instructions will #UD.

Operation:

RESULT <- OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
  UNORDERED:
  GREATER_THAN:
  LESS_THAN:
  EQUAL:
ESAC;
OF, AF, SF <- 0; }

Intel C/C++ Compiler Intrinsic Equivalents:
int _mm_comieq_sd (__m128d a, __m128d b) int _mm_comilt_sd (__m128d a, __m128d
b) int _mm_comile_sd (__m128d a, __m128d b) int _mm_comigt_sd (__m128d a, __m128d
b) int _mm_comige_sd (__m128d a, __m128d b) int _mm_comineq_sd (__m128d a, __m128d
b)


SIMD Floating-Point Exceptions:
Invalid (if SNaN or QNaN operands), Denormal.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: COMISS
description:
COMISS - Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS:
| Opcode/Instruction                         | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 0F 2F /r COMISS xmm1, xmm2/m32             | RM   | V/V           | SSE               | Compare low single-precision floating-point
|                                            |      |               |                   | values in xmm1 and xmm2/mem32 and set      
|                                            |      |               |                   | the EFLAGS flags accordingly.              
| VEX.LIG.0F.WIG 2F /r VCOMISS xmm1, xmm2/m32| RM   | V/V           | AVX               | Compare low single precision floating-point
|                                            |      |               |                   | values in xmm1 and xmm2/mem32 and set      
|                                            |      |               |                   | the EFLAGS flags accordingly.              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
Compares the single-precision floating-point values in the low doublewords of
operand 1 (first operand) and operand 2 (second operand), and sets the ZF, PF,
and CF flags in the EFLAGS register according to the result (unordered, greater
than, less than, or equal). The OF, SF, and AF flags in the EFLAGS register
are set to 0. The unordered result is returned if either source operand is a
NaN (QNaN or SNaN). The sign of zero is ignored for comparisons, so that -0.0
is equal to +0.0.

Operand 1 is an XMM register; Operand 2 can be an XMM register or a 32 bit memory
location.

The COMISS instruction differs from the UCOMISS instruction in that it signals
a SIMD floating-point invalid operation exception (#I) when a source operand
is either a QNaN or SNaN. The UCOMISS instruction signals an invalid numeric
exception only if a source operand is an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception
is generated.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). Note: In VEX-encoded versions, VEX.vvvv is reserved
and must be 1111b, otherwise instructions will #UD.

Operation:

RESULT <- OrderedCompare(SRC1[31:0] <> SRC2[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
  UNORDERED:
  GREATER_THAN:
  LESS_THAN:
  EQUAL:
ESAC;
OF,AF,SF <- 0; }

Intel C/C++ Compiler Intrinsic Equivalents:
int _mm_comieq_ss (__m128 a, __m128 b) int _mm_comilt_ss (__m128 a, __m128 b)
int _mm_comile_ss (__m128 a, __m128 b) int _mm_comigt_ss (__m128 a, __m128 b)
int _mm_comige_ss (__m128 a, __m128 b) int _mm_comineq_ss (__m128 a, __m128
b)


SIMD Floating-Point Exceptions:
Invalid (if SNaN or QNaN operands), Denormal.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CPUID
description:
CPUID - CPU Identification:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F A2 | CPUID      | NP   | Valid      | Valid          | Returns processor identification and   
|       |            |      |            |                | feature information to the EAX, EBX,   
|       |            |      |            |                | ECX, and EDX registers, as determined  
|       |            |      |            |                | by input entered in EAX (in some cases,
|       |            |      |            |                | ECX as well).                          

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID
instruction. If a software procedure can set and clear this flag, the processor
executing the procedure supports the CPUID instruction. This instruction operates
the same in non-64-bit modes and 64-bit mode. CPUID returns processor identification
and feature information in the EAX, EBX, ECX, and EDX registers.1 The instruction's
output is dependent on the contents of the EAX register upon execution (in some
cases, ECX as well). For example, the following pseudocode loads EAX with 00H
and causes CPUID to return a Maximum Return Value and the Vendor Identification
String in the appropriate registers:

MOV EAX, 00H CPUID

Table 3-17 shows information returned, depending on the initial value loaded
into the EAX register. Table 3-18 shows the maximum CPUID input value recognized
for each family of IA-32 processors on which CPUID is implemented.

Two types of information are returned: basic and extended function information.
If a value entered for CPUID.EAX is higher than the maximum input value for
basic or extended function for that processor then the data for the highest
basic information leaf is returned. For example, using the Intel Core i7 processor,
the following is true: CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *) CPUID.EAX
= 0AH (* Returns Architectural Performance Monitoring leaf. *) CPUID.EAX = 0BH
(* Returns Extended Topology Enumeration leaf. *) CPUID.EAX = 0CH (* INVALID:
Returns the same information as CPUID.EAX = 0BH. *) CPUID.EAX = 80000008H (*
Returns linear/physical address size data. *) CPUID.EAX = 8000000AH (* INVALID:
Returns same information as CPUID.EAX = 0BH. *)

If a value entered for CPUID.EAX is less than or equal to the maximum input
value and the leaf is not supported on that processor then 0 is returned in
all the registers. For example, using the Intel Core i7 processor, the following
is true: CPUID.EAX = 07H (*Returns EAX=EBX=ECX=EDX=0. *)

When CPUID returns the highest basic leaf information as a result of an invalid
input EAX value, any dependence on input ECX value in the basic leaf is honored.

CPUID can be executed at any privilege level to serialize instruction execution.
Serializing instruction execution guarantees that any modifications to flags,
registers, and memory for previous instructions are completed before the next
instruction is fetched and executed.

See also:

“Serializing Instructions” in Chapter 8, “Multiple-Processor Management,” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

| 1.| On Intel 64 processors, CPUID clears   
|   | the high 32 bits of the RAX/RBX/RCX/RDX
|   | registers in all modes.                
“Caching Translation Information” in Chapter 4, “Paging,” in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.


Table 3-17. Information Returned by CPUID Instruction:
Initial EAX

| Value Basic CPUID Information Maximum     | Information Provided about the Processor
| Input Value for Basic CPUID Information   |                                         
| (see Table 3-18) “Genu”“ntel”“ineI”Version|                                         
| Information: Type, Family, Model, and     |                                         
| Stepping ID (see Figure 3-5) Bits 07-00:  |                                         
| Brand Index Bits 15-08: CLFLUSH line      |                                         
| size (Value * 8 = cache line size in      |                                         
| bytes) Bits 23-16: Maximum number of      |                                         
| addressable IDs for logical processors    |                                         
| in this physical package*. Bits 31-24:    |                                         
| Initial APIC ID Feature Information       |                                         
| (see Figure 3-6 and Table 3-20) Feature   |                                         
| Information (see Figure 3-7 and Table     |                                         
| 3-21)                                     |                                         
Notes: * The nearest power-of-2 integer that is not smaller than EBX[23:16]
is the number of unique initial APIC IDs reserved for addressing different logical
processors in a physical package. This field is only valid if CPUID.1.EDX.HTT[bit
28]= 1.

| 02H| EAX EBX ECX EDX| Cache and TLB Information (see Table         
|    |                | 3-22) Cache and TLB Information Cache        
|    |                | and TLB Information Cache and TLB Information
| 03H| EAX EBX ECX EDX| Reserved. Reserved. Bits 00-31 of 96         
|    |                | bit processor serial number. (Available      
|    |                | in Pentium III processor only; otherwise,    
|    |                | the value in this register is reserved.)     
|    |                | Bits 32-63 of 96 bit processor serial        
|    |                | number. (Available in Pentium III processor  
|    |                | only; otherwise, the value in this register  
|    |                | is reserved.)                                
Notes: Processor serial number (PSN) is not supported in the Pentium 4 processor
or later. On all models, use the PSN flag (returned using CPUID) to check for
PSN support before accessing the feature.

See AP-485, Intel Processor Identification and the CPUID Instruction (Order
Number 241618) for more information on PSN.

CPUID leaves > 3 < 80000000 are visible only when IA32_MISC_ENABLE.BOOT_NT4[bit
22] = 0 (default).

Deterministic Cache Parameters Leaf

| 04H| NOTES: Leaf 04H output depends on the       
|    | initial value in ECX.*See also: “INPUT      
|    | EAX = 4: Returns Deterministic Cache        
|    | Parameters for each level on page 3-178.    
| EAX| Bits 04-00: Cache Type Field 0 = Null       
|    | - No more caches 1 = Data Cache 2 =         
|    | Instruction Cache 3 = Unified Cache         
|    | 4-31 = Reserved Information Returned        
|    | by CPUID Instruction (Contd.) Initial       
|    | EAX Information Provided about the Processor
|    | Bits 07-05: Cache Level (starts at 1)       
|    | Bit 08: Self Initializing cache level       
|    | (does not need SW initialization) Bit       
|    | 09: Fully Associative cache Bits 13-10:     
|    | Reserved Bits 25-14: Maximum number         
|    | of addressable IDs for logical processors   
|    | sharing this cache**, ***Bits 31-26:        
|    | Maximum number of addressable IDs for       
|    | processor cores in the physical package**,  
|    | ****, *****                                 
| EBX| Bits 11-00: L = System Coherency Line       
|    | Size**Bits 21-12: P = Physical Line         
|    | partitions**Bits 31-22: W = Ways of         
|    | associativity**                             
| ECX| Bits 31-00: S = Number of Sets**            
| EDX| Bit 0: Write-Back Invalidate/Invalidate     
|    | 0 = WBINVD/INVD from threads sharing        
|    | this cache acts upon lower level caches     
|    | for threads sharing this cache. 1 =         
|    | WBINVD/INVD is not guaranteed to act        
|    | upon lower level caches of non-originating  
|    | threads sharing this cache. Bit 1: Cache    
|    | Inclusiveness 0 = Cache is not inclusive    
|    | of lower cache levels. 1 = Cache is         
|    | inclusive of lower cache levels. Bit        
|    | 2: Complex Cache Indexing 0 = Direct        
|    | mapped cache. 1 = A complex function        
|    | is used to index the cache, potentially     
|    | using all address bits. Bits 31-03:         
|    | Reserved = 0                                
Notes: * If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0.
Invalid sub-leaves of EAX = 04H: ECX = n, n > 3. ** Add one to the return value
to get the result. ***The nearest power-of-2 integer that is not smaller than
(1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing
different logical processors sharing this cache **** The nearest power-of-2
integer that is not smaller than (1 + EAX[31:26]) is the number of unique Core_IDs
reserved for addressing different processor cores in a physical package. Core
ID is a subset of bits of the initial APIC ID. ***** The returned value is constant
for valid initial values in ECX. Valid ECX values start from 0.

MONITOR/MWAIT Leaf

| 05H| EAX EBX ECX EDX| Bits 15-00: Smallest monitor-line size      
|    |                | in bytes (default is processor's monitor    
|    |                | granularity) Bits 31-16: Reserved =         
|    |                | 0 Bits 15-00: Largest monitor-line size     
|    |                | in bytes (default is processor's monitor    
|    |                | granularity) Bits 31-16: Reserved =         
|    |                | 0 Bit 00: Enumeration of Monitor-Mwait      
|    |                | extensions (beyond EAX and EBX registers)   
|    |                | supported Bit 01: Supports treating         
|    |                | interrupts as break-event for MWAIT,        
|    |                | even when interrupts disabled Bits 31       
|    |                | - 02: Reserved Information Returned         
|    |                | by CPUID Instruction (Contd.) Initial       
|    |                | EAX Information Provided about the Processor
|    |                | Bits 03 - 00: Number of C0* sub C-states    
|    |                | supported using MWAIT Bits 07 - 04:         
|    |                | Number of C1* sub C-states supported        
|    |                | using MWAIT Bits 11 - 08: Number of         
|    |                | C2* sub C-states supported using MWAIT      
|    |                | Bits 15 - 12: Number of C3* sub C-states    
|    |                | supported using MWAIT Bits 19 - 16:         
|    |                | Number of C4* sub C-states supported        
|    |                | using MWAIT Bits 23 - 20: Number of         
|    |                | C5* sub C-states supported using MWAIT      
|    |                | Bits 27 - 24: Number of C6* sub C-states    
|    |                | supported using MWAIT Bits 31 - 28:         
|    |                | Number of C7* sub C-states supported        
|    |                | using MWAIT                                 

NOTE::
| *                                                             | The definition of C0 through C7 states    
|                                                               | for MWAIT extension are processor-specific
|                                                               | C-states, not ACPI Cstates. Thermal       
|                                                               | and Power Management Leaf                 
| Bit 00: Digital temperature sensor is                         | EAX EBX                                   
| supported if set Bit 01: Intel Turbo                          |                                           
| Boost Technology Available (see description                   |                                           
| of IA32_MISC_ENABLE[38]). Bit 02: ARAT.                       |                                           
| APIC-Timer-always-running feature is                          |                                           
| supported if set. Bit 03: Reserved Bit                        |                                           
| 04: PLN. Power limit notification controls                    |                                           
| are supported if set. Bit 05: ECMD.                           |                                           
| Clock modulation duty cycle extension                         |                                           
| is supported if set. Bit 06: PTM. Package                     |                                           
| thermal management is supported if set.                       |                                           
| Bit 07: HWP. HWP base registers (IA32_PM_ENALBE[bit           |                                           
| 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST,                  |                                           
| IA32_HWP_STATUS) are supported if set.                        |                                           
| Bit 08: HWP_Notification. IA32_HWP_INTERRUPT                  |                                           
| MSR is supported if set. Bit 09: HWP_Activity_Window.         |                                           
| IA32_HWP_REQUEST[bits 41:32] is supported                     |                                           
| if set. Bit 10: HWP_Energy_Performance_Preference.            |                                           
| IA32_HWP_REQUEST[bits 31:24] is supported                     |                                           
| if set. Bit 11: HWP_Package_Level_Request.                    |                                           
| IA32_HWP_REQUEST_PKG MSR is supported                         |                                           
| if set. Bit 12: Reserved. Bit 13: HDC.                        |                                           
| HDC base registers IA32_PKG_HDC_CTL,                          |                                           
| IA32_PM_CTL1, IA32_THREAD_STALL MSRs                          |                                           
| are supported if set. Bits 31 - 15:                           |                                           
| Reserved Bits 03 - 00: Number of Interrupt                    |                                           
| Thresholds in Digital Thermal Sensor                          |                                           
| Bits 31 - 04: Reserved                                        |                                           
| Bit 00: Hardware Coordination Feedback                        | ECX                                       
| Capability (Presence of IA32_MPERF and                        |                                           
| IA32_APERF). The capability to provide                        |                                           
| a measure of delivered processor performance                  |                                           
| (since last reset of the counters),                           |                                           
| as a percentage of expected processor                         |                                           
| performance at frequency specified in                         |                                           
| CPUID Brand String Bits 02 - 01: Reserved                     |                                           
| = 0 Bit 03: The processor supports performance-energy         |                                           
| bias preference if CPUID.06H:ECX.SETBH[bit                    |                                           
| 3] is set and it also implies the presence                    |                                           
| of a new architectural MSR called IA32_ENERGY_PERF_BIAS       |                                           
| (1B0H) Bits 31 - 04: Reserved = 0                             |                                           
| Reserved = 0                                                  | EDX Structured Extended Feature Flags     
|                                                               | Enumeration Leaf (Output depends on       
|                                                               | ECX input value) Sub-leaf 0 (Input ECX    
|                                                               | = 0). *                                   
| Bits 31-00: Reports the maximum input                         | EAX                                       
| value for supported leaf 7 sub-leaves.                        |                                           
| Table 3-17.                                                   | Information Returned by CPUID Instruction 
|                                                               | (Contd.) Initial EAX Information Provided 
|                                                               | about the Processor                       
| Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE| EBX                                       
| if 1. Bit 01: IA32_TSC_ADJUST MSR is                          |                                           
| supported if 1. Bit 02: Reserved Bit                          |                                           
| 03: BMI1 Bit 04: HLE Bit 05: AVX2 Bit                         |                                           
| 06: Reserved Bit 07: SMEP. Supports                           |                                           
| Supervisor-Mode Execution Prevention                          |                                           
| if 1. Bit 08: BMI2 Bit 09: Supports                           |                                           
| Enhanced REP MOVSB/STOSB if 1. Bit 10:                        |                                           
| INVPCID. If 1, supports INVPCID instruction                   |                                           
| for system software that manages process-context              |                                           
| identifiers. Bit 11: RTM Bit 12: Supports                     |                                           
| Platform Quality of Service Monitoring                        |                                           
| (PQM) capability if 1. Bit 13: Deprecates                     |                                           
| FPU CS and FPU DS values if 1. Bit 14:                        |                                           
| Reserved. Bit 15: Supports Platform                           |                                           
| Quality of Service Enforcement (PQE)                          |                                           
| capability if 1. Bits 31:16: Reserved                         |                                           
| Reserved                                                      | ECX                                       
| Reserved                                                      | EDX                                       

NOTE::
* If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Invalid
sub-leaves of EAX = 07H: ECX = n, n > 0.

Direct Cache Access Information Leaf

| 09H    | EAX EBX ECX EDX Architectural Performance    | Value of bits [31:0] of IA32_PLATFORM_DCA_CAP
|        | Monitoring Leaf                              | MSR (address 1F8H) Reserved Reserved         
|        |                                              | Reserved                                     
| 0AH 0BH| EAX EBX ECX EDX Extended Topology Enumeration| Bits 07 - 00: Version ID of architectural    
|        | Leaf EAX EBX ECX EDX                         | performance monitoring Bits 15- 08:          
|        |                                              | Number of general-purpose performance        
|        |                                              | monitoring counter per logical processor     
|        |                                              | Bits 23 - 16: Bit width of general-purpose,  
|        |                                              | performance monitoring counter Bits          
|        |                                              | 31 - 24: Length of EBX bit vector to         
|        |                                              | enumerate architectural performance          
|        |                                              | monitoring events Bit 00: Core cycle         
|        |                                              | event not available if 1 Bit 01: Instruction 
|        |                                              | retired event not available if 1 Bit         
|        |                                              | 02: Reference cycles event not available     
|        |                                              | if 1 Bit 03: Last-level cache reference      
|        |                                              | event not available if 1 Bit 04: Last-level  
|        |                                              | cache misses event not available if          
|        |                                              | 1 Bit 05: Branch instruction retired         
|        |                                              | event not available if 1 Bit 06: Branch      
|        |                                              | mispredict retired event not available       
|        |                                              | if 1 Bits 31- 07: Reserved = 0 Reserved      
|        |                                              | = 0 Bits 04 - 00: Number of fixed-function   
|        |                                              | performance counters (if Version ID          
|        |                                              | > 1) Bits 12- 05: Bit width of fixed-function
|        |                                              | performance counters (if Version ID          
|        |                                              | > 1) Reserved = 0 Information Returned       
|        |                                              | by CPUID Instruction (Contd.) Initial        
|        |                                              | EAX Information Provided about the Processor 
|        |                                              | NOTES: Most of Leaf 0BH output depends       
|        |                                              | on the initial value in ECX. The EDX         
|        |                                              | output of leaf 0BH is always valid and       
|        |                                              | does not vary with input value in ECX.       
|        |                                              | Output value in ECX[7:0] always equals       
|        |                                              | input value in ECX[7:0]. For sub-leaves      
|        |                                              | that return an invalid level-type of         
|        |                                              | 0 in ECX[15:8]; EAX and EBX will return      
|        |                                              | 0. If an input value n in ECX returns        
|        |                                              | the invalid level-type of 0 in ECX[15:8],    
|        |                                              | other input values with ECX >n also          
|        |                                              | return 0 in ECX[15:8]. Bits 04-00: Number    
|        |                                              | of bits to shift right on x2APIC ID          
|        |                                              | to get a unique topology ID of the next      
|        |                                              | level type*. All logical processors          
|        |                                              | with the same next level ID share current    
|        |                                              | level. Bits 31-05: Reserved. Bits 15         
|        |                                              | - 00: Number of logical processors at        
|        |                                              | this level type. The number reflects         
|        |                                              | configuration as shipped by Intel**.         
|        |                                              | Bits 31- 16: Reserved. Bits 07 - 00:         
|        |                                              | Level number. Same value in ECX input        
|        |                                              | Bits 15 - 08: Level type***. Bits 31         
|        |                                              | - 16:: Reserved. Bits 31- 00: x2APIC         
|        |                                              | ID the current logical processor.            
Notes: * Software should use this field (EAX[4:0]) to enumerate processor topology
of the system.

** Software must not use EBX[15:0] to enumerate processor topology of the system.
This value in this field (EBX[15:0]) is only intended for display/diagnostic
purposes. The actual number of logical processors available to BIOS/OS/Applications
may be different from the value of EBX[15:0], depending on software and platform
hardware configurations.

*** The value of the “level type” field is not related to level numbers in any
way, higher “level type” values do not mean higher levels. Level type field
has the following encoding: 0 : invalid 1 : SMT 2 : Core 3-255 : Reserved

Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)

| 0DH                                     | NOTES: Leaf 0DH main leaf (ECX = 0).               
| EAX                                     | Bits 31-00: Reports the valid bit fields           
|                                         | of the lower 32 bits of XCR0. If a bit             
|                                         | is 0, the corresponding bit field in               
|                                         | XCR0 is reserved. Bit 00: legacy x87               
|                                         | Bit 01: 128-bit SSE Bit 02: 256-bit                
|                                         | AVX Bits 31- 03: Reserved                          
| EBX                                     | Bits 31-00: Maximum size (bytes, from              
|                                         | the beginning of the XSAVE/XRSTOR save             
|                                         | area) required by enabled features in              
|                                         | XCR0. May be different than ECX if some            
|                                         | features at the end of the XSAVE save              
|                                         | area are not enabled.                              
| ECX                                     | Bit 31-00: Maximum size (bytes, from               
|                                         | the beginning of the XSAVE/XRSTOR save             
|                                         | area) of the XSAVE/XRSTOR save area                
|                                         | required by all supported features in              
|                                         | the processor, i.e all the valid bit               
|                                         | fields in XCR0.                                    
| EDX Processor Extended State Enumeration| Bit 31-00: Reports the valid bit fields            
| Sub-leaf (EAX = 0DH, ECX = 1)           | of the upper 32 bits of XCR0. If a bit             
|                                         | is 0, the corresponding bit field in               
|                                         | XCR0 is reserved. Information Returned             
|                                         | by CPUID Instruction (Contd.) Initial              
|                                         | EAX Information Provided about the Processor       
| EAX                                     | Bits 31-04: Reserved Bit 00: XSAVEOPT              
|                                         | is available Bit 01: Supports XSAVEC               
|                                         | and the compacted form of XRSTOR if                
|                                         | set Bit 02: Supports XGETBV with ECX               
|                                         | = 1 if set Bit 03: Supports XSAVES/XRSTORS         
|                                         | and IA32_XSS if set                                
| EBX                                     | Bits 31-00: The size in bytes of the               
|                                         | XSAVE area containing all states enabled           
|                                         | by XCRO | IA32_XSS.                                
| ECX                                     | Bits 31-00: Reports the valid bit fields           
|                                         | of the lower 32 bits of IA32_XSS. If               
|                                         | a bit is 0, the corresponding bit field            
|                                         | in IA32_XSS is reserved. Bits 07-00:               
|                                         | Reserved Bit 08: IA32_XSS[bit 8] is                
|                                         | supported if 1 Bits 31-09: Reserved                
| EDX Processor Extended State Enumeration| Bits 31-00: Reports the valid bit fields           
| Sub-leaves (EAX = 0DH, ECX = n, n >     | of the upper 32 bits of IA32_XSS. If               
| 1)                                      | a bit is 0, the corresponding bit field            
|                                         | in IA32_XSS is reserved. Bits 31-00:               
|                                         | Reserved                                           
| 0DH                                     | NOTES: Leaf 0DH output depends on the              
|                                         | initial value in ECX. Each valid sub-leaf          
|                                         | index maps to a valid bit in either                
|                                         | the XCR0 register or the IA32_XSS MSR              
|                                         | starting at bit position 2. * If ECX               
|                                         | contains an invalid sub-leaf index,                
|                                         | EAX/EBX/ECX/EDX return 0. Invalid sub-leaves       
|                                         | of EAX = 0DH: ECX = n, n > 2.                      
| EAX                                     | Bits 31-0: The size in bytes (from the             
|                                         | offset specified in EBX) of the save               
|                                         | area for an extended state feature associated      
|                                         | with a valid sub-leaf index, n. This               
|                                         | field reports 0 if the sub-leaf index,             
|                                         | n, does not map to a valid bit in the              
|                                         | XCR0 register*.                                    
| EBX                                     | Bits 31-0: The offset in bytes of this             
|                                         | extended state component's save area               
|                                         | from the beginning of the XSAVE/XRSTOR             
|                                         | area. This field reports 0 if the sub-leaf         
|                                         | index, n, is invalid*.                             
| ECX                                     | This field reports 0 if the sub-leaf               
|                                         | index, n, is invalid*; otherwise, bit              
|                                         | 0 is set if the sub-leaf index, n, maps            
|                                         | to a valid bit in the IA32_XSS MSR,                
|                                         | and bits 31-1 are reserved.                        
| EDX Platform QoS Monitoring Enumeration | This field reports 0 if the sub-leaf               
| Sub-leaf (EAX = 0FH, ECX = 0)           | index, n, is invalid*; otherwise it                
|                                         | is reserved.                                       
| 0FH                                     | NOTES: Leaf 0FH output depends on the              
|                                         | initial value in ECX. Sub-leaf index               
|                                         | 0 reports valid resource type starting             
|                                         | at bit position 1 of EDX                           
| EAX                                     | Reserved.                                          
| EBX                                     | Bits 31-0: Maximum range (zero-based)              
|                                         | of RMID within this physical processor             
|                                         | of all types.                                      
| ECX                                     | Reserved.                                          
| EDX L3 Cache QoS Monitoring Capability  | Bit 00: Reserved. Bit 01: Supports L3              
| Enumeration Sub-leaf (EAX = 0FH, ECX    | Cache QoS Monitoring if 1. Bits 31:02:             
| = 1)                                    | Reserved Information Returned by CPUID             
|                                         | Instruction (Contd.) Initial EAX Information       
|                                         | Provided about the Processor                       
| 0FH                                     | NOTES: Leaf 0FH output depends on the              
|                                         | initial value in ECX.                              
| EAX                                     | Reserved.                                          
| EBX                                     | Bits 31-0: Conversion factor from reported         
|                                         | IA32_QM_CTR value to occupancy metric              
|                                         | (bytes).                                           
| ECX                                     | Maximum range (zero-based) of RMID of              
|                                         | this resource type.                                
| EDX Platform QoS Enforcement Enumeration| Bit 00: Supports L3 occupancy monitoring           
| Sub-leaf (EAX = 10H, ECX = 0)           | if 1. Bits 31:01: Reserved                         
| 10H                                     | NOTES: Leaf 10H output depends on the              
|                                         | initial value in ECX. Sub-leaf index               
|                                         | 0 reports valid resource identification            
|                                         | (ResID) starting at bit position 1 of              
|                                         | EDX                                                
| EAX                                     | Reserved.                                          
| EBX                                     | Bit 00: Reserved. Bit 01: Supports L3              
|                                         | Cache QoS Enforcement if 1. Bits 31:02:            
|                                         | Reserved                                           
| ECX                                     | Reserved.                                          
| EDX L3 Cache QoS Enforcement Enumeration| Reserved.                                          
| Sub-leaf (EAX = 10H, ECX = ResID =1)    |                                                    
| 10H                                     | NOTES: Leaf 10H output depends on the              
|                                         | initial value in ECX.                              
| EAX                                     | Bits 4:0: Length of the capacity bit               
|                                         | mask for the corresponding ResID. Bits             
|                                         | 31:05: Reserved                                    
| EBX                                     | Bits 31-0: Bit-granular map of isolation/contention
|                                         | of allocation units.                               
| ECX                                     | Bit 00: Reserved. Bit 01: Updates of               
|                                         | COS should be infrequent if 1. Bits                
|                                         | 31:02: Reserved                                    
| EDX Unimplemented CPUID Leaf Functions  | Bits 15:0: Highest COS number supported            
| Extended Function CPUID Information     | for this ResID. Bits 31:16: Reserved               
|                                         | Invalid. No existing or future CPU will            
|                                         | return processor identification or feature         
|                                         | information if the initial EAX value               
|                                         | is in the range 40000000H to 4FFFFFFFH.            
|                                         | 4FFFFFFFH                                          
| EAX                                     | Maximum Input Value for Extended Function          
|                                         | CPUID Information (see Table 3-18).                
| EBX ECX EDX                             | Reserved Reserved Reserved Information             
|                                         | Returned by CPUID Instruction (Contd.)             
|                                         | Initial EAX Information Provided about             
|                                         | the Processor                                      
| EAX                                     | Extended Processor Signature and Feature           
|                                         | Bits.                                              
| EBX                                     | Reserved                                           
| ECX                                     | Bit 00: LAHF/SAHF available in 64-bit              
|                                         | mode Bits 04-01 Reserved Bit 05: LZCNT             
|                                         | Bits 07-06 Reserved Bit 08: PREFETCHW              
|                                         | Bits 31-09 Reserved                                
| EDX                                     | Bits 10-00: Reserved Bit 11: SYSCALL/SYSRET        
|                                         | available in 64-bit mode Bits 19-12:               
|                                         | Reserved = 0 Bit 20: Execute Disable               
|                                         | Bit available Bits 25-21: Reserved =               
|                                         | 0 Bit 26: 1-GByte pages are available              
|                                         | if 1 Bit 27: RDTSCP and IA32_TSC_AUX               
|                                         | are available if 1 Bits 28: Reserved               
|                                         | = 0 Bit 29: Intel® 64 Architecture available       
|                                         | if 1 Bits 31-30: Reserved = 0                      
| EAX EBX ECX EDX                         | Processor Brand String Processor Brand             
|                                         | String Continued Processor Brand String            
|                                         | Continued Processor Brand String Continued         
| EAX EBX ECX EDX                         | Processor Brand String Continued Processor         
|                                         | Brand String Continued Processor Brand             
|                                         | String Continued Processor Brand String            
|                                         | Continued                                          
| EAX EBX ECX EDX                         | Processor Brand String Continued Processor         
|                                         | Brand String Continued Processor Brand             
|                                         | String Continued Processor Brand String            
|                                         | Continued                                          
| EAX EBX ECX EDX                         | Reserved = 0 Reserved = 0 Reserved =               
|                                         | 0 Reserved = 0                                     
| EAX EBX                                 | Reserved = 0 Reserved = 0                          
| ECX EDX                                 | Bits 07-00: Cache Line size in bytes               
|                                         | Bits 11-08: Reserved Bits 15-12: L2                
|                                         | Associativity field *Bits 31-16: Cache             
|                                         | size in 1K units Reserved = 0 Information          
|                                         | Returned by CPUID Instruction (Contd.)             
|                                         | Initial EAX Information Provided about             
|                                         | the Processor                                      
Notes: * L2 associativity field encodings: 00H - Disabled 01H - Direct mapped
02H - 2-way 04H - 4-way 06H - 8-way 08H - 16-way 0FH - Fully associative

| 80000007H| EAX EBX ECX EDX| Reserved = 0 Reserved = 0 Reserved =        
|          |                | 0 Bits 07-00: Reserved = 0 Bit 08: Invariant
|          |                | TSC available if 1 Bits 31-09: Reserved     
|          |                | = 0                                         
| 80000008H| EAX EBX ECX EDX| Linear/Physical Address size Bits 07-00:    
|          |                | #Physical Address Bits*Bits 15-8: #Linear   
|          |                | Address Bits Bits 31-16: Reserved =         
|          |                | 0 Reserved = 0 Reserved = 0 Reserved        
|          |                | = 0                                         
Notes: 

| *| If CPUID.80000008H:EAX[7:0] is supported,
|  | the maximum physical address number      
|  | supported should come from this field.   

INPUT EAX = 0: Returns CPUID's Highest Value for Basic Processor Information and the Vendor Identification String:
When CPUID executes with EAX set to 0, the processor returns the highest value
the CPUID recognizes for returning basic processor information. The value is
returned in the EAX register (see Table 3-18) and is processor specific. A vendor
identification string is also returned in EBX, EDX, and ECX. For Intel processors,
the string is “GenuineIntel” and is expressed: EBX ← 756e6547h (* "Genu", with
G in the low eight bits of BL *) EDX ← 49656e69h (* "ineI", with i in the low
eight bits of DL *) ECX ← 6c65746eh (* "ntel", with n in the low eight bits
of CL *)


INPUT EAX = 80000000H: Returns CPUID's Highest Value for Extended Processor Information:
When CPUID executes with EAX set to 80000000H, the processor returns the highest
value the processor recognizes for returning extended processor information.
The value is returned in the EAX register (see Table 3-18) and is processor
specific.


Table 3-18. Highest CPUID Source Operand for Intel 64 and IA-32 Processors:
Highest Value in EAX Intel 64 or IA-32 Processors

| Basic Information                        | Extended Function Information CPUID     
|                                          | Not Implemented                         
| 01H                                      | Not Implemented                         
| Highest CPUID Source Operand for Intel   | (Contd.) Highest Value in EAX Intel     
| 64 and IA-32 Processors Basic Information| 64 or IA-32 Processors Extended Function
|                                          | Information                             
| 02H                                      | Not Implemented Processors              
| 03H                                      | Not Implemented                         
| 02H                                      | 80000004H                               
| 02H                                      | 80000004H                               
| 02H                                      | 80000004H                               
| 05H                                      | 80000008H Technology                    
| 05H                                      | 80000008H                               
| 06H                                      | 80000008H                               
| 0AH                                      | 80000008H                               
| 0AH                                      | 80000008H                               
| 0AH                                      | 80000008H Series                        
| 0DH                                      | 80000008H                               
| 0AH                                      | 80000008H                               
| 0AH                                      | 80000008H                               
| 0BH                                      | 80000008H                               

IA32_BIOS_SIGN_ID Returns Microcode Update Signature:
For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID
MSR is loaded with the update signature whenever CPUID executes. The signature
is returned in the upper DWORD. For details, see Chapter 9 in the Intel® 64
and IA-32 Architectures Software Developer's Manual, Volume 3A.


INPUT EAX = 1: Returns Model, Family, Stepping Information:
When CPUID executes with EAX set to 1, version information is returned in EAX
(see Figure 3-5). For example: model, family, and processor type for the Intel
Xeon processor 5100 series is as follows:

 - Model  -  1111B
 - Family  -  0101B
 - Processor Type  -  00B

See Table 3-19 for available processor type values. Stepping IDs are provided
as needed.

| 31| 28 27 Extended Family ID| 20 19 Extended Model ID| 16 15 14 13 12 11| 8 Family ID| 7 Model| 4| 3 Stepping ID| 0 EAX
Extended Family ID (0) Extended Model ID (0) Processor Type Family (0FH for
the Pentium 4 Processor Family) Model

Reserved

OM16525

| Figure 3-5.| Version Information Returned by CPUID
|            | in EAX Processor Type Field Encoding 
|            | 00B 01B 10B 11B                      
NOTE See Chapter 17 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for information on identifying earlier IA-32 processors.

The Extended Family ID needs to be examined only when the Family ID is 0FH.
Integrate the fields into a display using the following rule:

IF Family_ID != 0FH THEN DisplayFamily = Family_ID; ELSE DisplayFamily = Extended_Family_ID
+ Family_ID; (* Right justify and zero-extend 4-bit field. *) FI; (* Show DisplayFamily
as HEX field. *)

The Extended Model ID needs to be examined only when the Family ID is 06H or
0FH. Integrate the field into a display using the following rule:

IF (Family_ID = 06H or Family_ID = 0FH) THEN DisplayModel = (Extended_Model_ID
« 4) + Model_ID; (* Right justify and zero-extend 4-bit field; display Model_ID
as HEX field.*) ELSE DisplayModel = Model_ID; FI; (* Show DisplayModel as HEX
field. *)


INPUT EAX = 1: Returns Additional Information in EBX:
When CPUID executes with EAX set to 1, additional information is returned to
the EBX register:

 - Brand index (low byte of EBX)  -  this number provides an entry into a brand string
table that contains brand strings for IA-32 processors. More information about
this field is provided later in this section.
 - CLFLUSH instruction cache line size (second byte of EBX)  -  this number indicates
the size of the cache line flushed with CLFLUSH instruction in 8-byte increments.
This field was introduced in the Pentium 4 processor.
 - Local APIC ID (high byte of EBX)  -  this number is the 8-bit ID that is assigned
to the local APIC on the processor during power up. This field was introduced
in the Pentium 4 processor.


INPUT EAX = 1: Returns Feature Information in ECX and EDX:
When CPUID executes with EAX set to 1, feature information is returned in ECX
and EDX.

 - Figure 3-6 and Table 3-20 show encodings for ECX.
 - Figure 3-7 and Table 3-21 show encodings for EDX.

For all feature flags, a 1 indicates that the feature is supported. Use Intel
to properly interpret feature flags.


NOTE:
Software must confirm that a processor feature is present using feature flags
returned by CPUID prior to using the feature. Software should not depend on
future offerings retaining all features.

| 31 30 29 28 27 26 25 24 23 22 21 20| 17| 16| 15| 14| 13| 12| 11| 10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0
| 19 18                              |   |   |   |   |   |   |   |   |  |  |  |  |  |  |  |  |  |  
ECX 0

RDRAND F16C AVX OSXSAVE XSAVE AES TSC-Deadline POPCNT MOVBE x2APIC

| SSE4_2  - SSE4_1  - DCA  - PCID  - PDCM  - | SSE4.2 SSE4.1 Direct Cache Access Process-context
|                                  | Identifiers Perf/Debug Capability MSR            
xTPR Update Control CMPXCHG16B

| FMA  - SDBG CNXT-ID  -  L1 Context ID SSSE3  | Fused Multiply Add SSSE3 Extensions                 
|  - TM2  -  Thermal Monitor 2 EST  - SMX  -       | Technology 64-bit DS Area Carryless                 
| Safer Mode Extensions VMX  -  Virtual      | Multiplication SSE3 Extensions OM16524b             
| Machine Extensions DS-CPL  -  CPL Qualified| Feature Information Returned in the                 
| Debug Store MONITOR  -  MONITOR/MWAIT      | ECX Register Feature Information Returned           
| DTES64 PCLMULQDQ SSE3 Reserved           | in the ECX Register Description Streaming           
|                                          | SIMD Extensions 3 (SSE3). A value of                
|                                          | 1 indicates the processor supports this             
|                                          | technology. PCLMULQDQ. A value of 1                 
|                                          | indicates the processor supports the                
|                                          | PCLMULQDQ instruction 64-bit DS Area.               
|                                          | A value of 1 indicates the processor                
|                                          | supports DS area using 64-bit layout                
|                                          | MONITOR/MWAIT. A value of 1 indicates               
|                                          | the processor supports this feature.                
|                                          | CPL Qualified Debug Store. A value of               
|                                          | 1 indicates the processor supports the              
|                                          | extensions to the Debug Store feature               
|                                          | to allow for branch message storage                 
|                                          | qualified by CPL. Virtual Machine Extensions.       
|                                          | A value of 1 indicates that the processor           
|                                          | supports this technology Safer Mode                 
|                                          | Extensions. A value of 1 indicates that             
|                                          | the processor supports this technology.             
|                                          | See Chapter 5, “Safer Mode Extensions               
|                                          | Reference”. Enhanced Intel SpeedStep®               
|                                          | technology. A value of 1 indicates that             
|                                          | the processor supports this technology.             
|                                          | Thermal Monitor 2. A value of 1 indicates           
|                                          | whether the processor supports this                 
|                                          | technology. A value of 1 indicates the              
|                                          | presence of the Supplemental Streaming              
|                                          | SIMD Extensions 3 (SSSE3). A value of               
|                                          | 0 indicates the instruction extensions              
|                                          | are not present in the processor (Contd.)           
|                                          | Description L1 Context ID. A value of               
|                                          | 1 indicates the L1 data cache mode can              
|                                          | be set to either adaptive mode or shared            
|                                          | mode. A value of 0 indicates this feature           
|                                          | is not supported. See definition of                 
|                                          | the IA32_MISC_ENABLE MSR Bit 24 (L1                 
|                                          | Data Cache Context Mode) for details.               
|                                          | A value of 1 indicates the processor                
|                                          | supports IA32_DEBUG_INTERFACE MSR for               
|                                          | silicon debug. A value of 1 indicates               
|                                          | the processor supports FMA extensions               
|                                          | using YMM state. CMPXCHG16B Available.              
|                                          | A value of 1 indicates that the feature             
|                                          | is available. See the “CMPXCHG8B/CMPXCHG16B - Compare 
|                                          | and Exchange Bytes” section in this                 
|                                          | chapter for a description. xTPR Update              
|                                          | Control. A value of 1 indicates that                
|                                          | the processor supports changing IA32_MISC_ENABLE[bit
|                                          | 23]. Perfmon and Debug Capability: A                
|                                          | value of 1 indicates the processor supports         
|                                          | the performance and debug feature indication        
|                                          | MSR IA32_PERF_CAPABILITIES. Reserved                
|                                          | Process-context identifiers. A value                
|                                          | of 1 indicates that the processor supports          
|                                          | PCIDs and that software may set CR4.PCIDE           
|                                          | to 1. A value of 1 indicates the processor          
|                                          | supports the ability to prefetch data               
|                                          | from a memory mapped device. A value                
|                                          | of 1 indicates that the processor supports          
|                                          | SSE4.1. A value of 1 indicates that                 
|                                          | the processor supports SSE4.2. A value              
|                                          | of 1 indicates that the processor supports          
|                                          | x2APIC feature. A value of 1 indicates              
|                                          | that the processor supports MOVBE instruction.      
|                                          | A value of 1 indicates that the processor           
|                                          | supports the POPCNT instruction. A value            
|                                          | of 1 indicates that the processor's                 
|                                          | local APIC timer supports one-shot operation        
|                                          | using a TSC deadline value. A value                 
|                                          | of 1 indicates that the processor supports          
|                                          | the AESNI instruction extensions. A                 
|                                          | value of 1 indicates that the processor             
|                                          | supports the XSAVE/XRSTOR processor                 
|                                          | extended states feature, the XSETBV/XGETBV          
|                                          | instructions, and XCR0. A value of 1                
|                                          | indicates that the OS has set CR4.OSXSAVE[bit       
|                                          | 18] to enable the XSAVE feature set.                
|                                          | A value of 1 indicates the processor                
|                                          | supports the AVX instruction extensions.            
|                                          | A value of 1 indicates that processor               
|                                          | supports 16-bit floating-point conversion           
|                                          | instructions. A value of 1 indicates                
|                                          | that processor supports RDRAND instruction.         
|                                          | Always returns 0. 0                                 
EDX

PBE-Pend. Brk. EN. TM-Therm. Monitor HTT-Multi-threading SS-Self Snoop SSE2-SSE2
Extensions SSE-SSE Extensions FXSR-FXSAVE/FXRSTOR MMX-MMX Technology ACPI-Thermal
Monitor and Clock Ctrl DS-Debug Store CLFSH-CFLUSH instruction PSN-Processor
Serial Number PSE-36 - Page Size Extension PAT-Page Attribute Table CMOV-Conditional
Move/Compare Instruction MCA-Machine Check Architecture PGE-PTE Global Bit MTRR-Memory
Type Range Registers SEP-SYSENTER and SYSEXIT APIC-APIC on Chip CX8-CMPXCHG8B
Inst. MCE-Machine Check Exception PAE-Physical Address Extensions MSR-RDMSR
and WRMSR Support TSC-Time Stamp Counter PSE-Page Size Extensions DE-Debugging
Extensions VME-Virtual-8086 Mode Enhancement FPU-x87 FPU on Chip

Reserved

OM16523

| Figure 3-7.                         | Feature Information Returned in the               
|                                     | EDX Register More on Feature Information          
|                                     | Returned in the EDX Register Description          
|                                     | Floating Point Unit On-Chip. The processor        
|                                     | contains an x87 FPU. Virtual 8086 Mode            
|                                     | Enhancements. Virtual 8086 mode enhancements,     
|                                     | including CR4.VME for controlling the             
|                                     | feature, CR4.PVI for protected mode               
|                                     | virtual interrupts, software interrupt            
|                                     | indirection, expansion of the TSS with            
|                                     | the software indirection bitmap, and              
|                                     | EFLAGS.VIF and EFLAGS.VIP flags. Debugging        
|                                     | Extensions. Support for I/O breakpoints,          
|                                     | including CR4.DE for controlling the              
|                                     | feature, and optional trapping of accesses        
|                                     | to DR4 and DR5. Page Size Extension.              
|                                     | Large pages of size 4 MByte are supported,        
|                                     | including CR4.PSE for controlling the             
|                                     | feature, the defined dirty bit in PDE             
|                                     | (Page Directory Entries), optional reserved       
|                                     | bit trapping in CR3, PDEs, and PTEs.              
|                                     | Time Stamp Counter. The RDTSC instruction         
|                                     | is supported, including CR4.TSD for               
|                                     | controlling privilege. Model Specific             
|                                     | Registers RDMSR and WRMSR Instructions.           
|                                     | The RDMSR and WRMSR instructions are              
|                                     | supported. Some of the MSRs are implementation    
|                                     | dependent. Physical Address Extension.            
|                                     | Physical addresses greater than 32 bits           
|                                     | are supported: extended page table entry          
|                                     | formats, an extra level in the page               
|                                     | translation tables is defined, 2-MByte            
|                                     | pages are supported instead of 4 Mbyte            
|                                     | pages if PAE bit is 1. Machine Check              
|                                     | Exception. Exception 18 is defined for            
|                                     | Machine Checks, including CR4.MCE for             
|                                     | controlling the feature. This feature             
|                                     | does not define the model-specific implementations
|                                     | of machine-check error logging, reporting,        
|                                     | and processor shutdowns. Machine Check            
|                                     | exception handlers may have to depend             
|                                     | on processor version to do model specific         
|                                     | processing of the exception, or test              
|                                     | for the presence of the Machine Check             
|                                     | feature. CMPXCHG8B Instruction. The               
|                                     | compare-and-exchange 8 bytes (64 bits)            
|                                     | instruction is supported (implicitly              
|                                     | locked and atomic). APIC On-Chip. The             
|                                     | processor contains an Advanced Programmable       
|                                     | Interrupt Controller (APIC), responding           
|                                     | to memory mapped commands in the physical         
|                                     | address range FFFE0000H to FFFE0FFFH              
|                                     | (by default - some processors permit              
|                                     | the APIC to be relocated). Reserved               
|                                     | SYSENTER and SYSEXIT Instructions. The            
|                                     | SYSENTER and SYSEXIT and associated               
|                                     | MSRs are supported. Memory Type Range             
|                                     | Registers. MTRRs are supported. The               
|                                     | MTRRcap MSR contains feature bits that            
|                                     | describe what memory types are supported,         
|                                     | how many variable MTRRs are supported,            
|                                     | and whether fixed MTRRs are supported.            
|                                     | Page Global Bit. The global bit is supported      
|                                     | in paging-structure entries that map              
|                                     | a page, indicating TLB entries that               
|                                     | are common to different processes and             
|                                     | need not be flushed. The CR4.PGE bit              
|                                     | controls this feature. Machine Check              
|                                     | Architecture. The Machine Check Architecture,     
|                                     | which provides a compatible mechanism             
|                                     | for error reporting in P6 family, Pentium         
|                                     | 4, Intel Xeon processors, and future              
|                                     | processors, is supported. The MCG_CAP             
|                                     | MSR contains feature bits describing              
|                                     | how many banks of error reporting MSRs            
|                                     | are supported. Conditional Move Instructions.     
|                                     | The conditional move instruction CMOV             
|                                     | is supported. In addition, if x87 FPU             
|                                     | is present as indicated by the CPUID.FPU          
|                                     | feature bit, then the FCOMI and FCMOV             
|                                     | instructions are supported Page Attribute         
|                                     | Table. Page Attribute Table is supported.         
|                                     | This feature augments the Memory Type             
|                                     | Range Registers (MTRRs), allowing an              
|                                     | operating system to specify attributes            
|                                     | of memory accessed through a linear               
|                                     | address on a 4KB granularity. 36-Bit              
|                                     | Page Size Extension. 4-MByte pages addressing     
|                                     | physical memory beyond 4 GBytes are               
|                                     | supported with 32-bit paging. This feature        
|                                     | indicates that upper bits of the physical         
|                                     | address of a 4-MByte page are encoded             
|                                     | in bits 20:13 of the page-directory               
|                                     | entry. Such physical addresses are limited        
|                                     | by MAXPHYADDR and may be up to 40 bits            
|                                     | in size. Processor Serial Number. The             
|                                     | processor supports the 96-bit processor           
|                                     | identification number feature and the             
|                                     | feature is enabled. CLFLUSH Instruction.          
|                                     | CLFLUSH Instruction is supported. Reserved        
| More on Feature Information Returned| Table 3-21. Description Debug Store.              
| in the EDX Register (Contd.)        | The processor supports the ability to             
|                                     | write debug information into a memory             
|                                     | resident buffer. This feature is used             
|                                     | by the branch trace store (BTS) and               
|                                     | precise event-based sampling (PEBS)               
|                                     | facilities (see Chapter 23, “Introduction         
|                                     | to Virtual-Machine Extensions,” in the            
|                                     | Intel® 64 and IA-32 Architectures Software        
|                                     | Developer's Manual, Volume 3C). Thermal           
|                                     | Monitor and Software Controlled Clock             
|                                     | Facilities. The processor implements              
|                                     | internal MSRs that allow processor temperature    
|                                     | to be monitored and processor performance         
|                                     | to be modulated in predefined duty cycles         
|                                     | under software control. Intel MMX Technology.     
|                                     | The processor supports the Intel MMX              
|                                     | technology. FXSAVE and FXRSTOR Instructions.      
|                                     | The FXSAVE and FXRSTOR instructions               
|                                     | are supported for fast save and restore           
|                                     | of the floating point context. Presence           
|                                     | of this bit also indicates that CR4.OSFXSR        
|                                     | is available for an operating system              
|                                     | to indicate that it supports the FXSAVE           
|                                     | and FXRSTOR instructions. SSE. The processor      
|                                     | supports the SSE extensions. SSE2. The            
|                                     | processor supports the SSE2 extensions.           
|                                     | Self Snoop. The processor supports the            
|                                     | management of conflicting memory types            
|                                     | by performing a snoop of its own cache            
|                                     | structure for transactions issued to              
|                                     | the bus. Max APIC IDs reserved field              
|                                     | is Valid. A value of 0 for HTT indicates          
|                                     | there is only a single logical processor          
|                                     | in A value of 1 for HTT indicates the             
|                                     | value in CPUID.1.EBX[23:16] (the Maximum          
|                                     | number of addressable IDs for logical             
|                                     | processors in this package) is valid              
|                                     | for the package. Thermal Monitor. The             
|                                     | processor implements the thermal monitor          
|                                     | automatic thermal control circuitry               
|                                     | (TCC). Reserved Pending Break Enable.             
|                                     | The processor supports the use of the             
|                                     | FERR#/PBE# pin when the processor is              
|                                     | in the stop-clock state (STPCLK# is               
|                                     | asserted) to signal the processor that            
|                                     | an interrupt is pending and that the              
|                                     | processor should return to normal operation       
|                                     | to handle the interrupt. Bit 10 (PBE              
|                                     | enable) in the IA32_MISC_ENABLE MSR               
|                                     | enables this capability.                          

INPUT EAX = 2: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX:
When CPUID executes with EAX set to 2, the processor returns information about
the processor's internal TLBs, cache and prefetch hardware in the EAX, EBX,
ECX, and EDX registers. The information is reported in encoded form and fall
into the following categories:

 - The least-significant byte in register EAX (register AL) indicates the number
of times the CPUID instruction must be executed with an input value of 2 to
get a complete description of the processor's TLB/Cache/Prefetch hardware. The
Intel Xeon processor 7400 series will return a 1.
 - The most significant bit (bit 31) of each register indicates whether the register
contains valid information (set to 0) or is reserved (set to 1).
 - If a register contains valid information, the information is contained in 1
byte descriptors. There are four types of encoding values for the byte descriptor,
the encoding type is noted in the second column of Table 3-22. Table 3-22 lists
the encoding of these descriptors. Note that the order of descriptors in the
EAX, EBX, ECX, and EDX registers is not defined; that is, specific bytes are
not designated to contain descriptors for specific cache, prefetch, or TLB types.
The descriptors may appear in any order. Note also a processor may report a
general descriptor type (FFH) and not report any byte descriptor of “cache type”
via CPUID leaf 2. Table 3-22. Encoding of CPUID Leaf 2 Descriptors

| Value 00H 01H 02H 03H 04H 05H 06H 08H     | Type Null descriptor, this byte contains       | Description (Contd.)                     
| 09H 0AH 0BH 0CH 0DH 0EH 1DH 21H 22H       | no information Instruction TLB: 4 KByte        |                                          
| 23H 24H 25H 29H 2CH 30H 40H 41H 42H       | pages, 4-way set associative, 32 entries       |                                          
| 43H 44H 45H 46H 47H 48H 49H 4AH 4BH       | Instruction TLB: 4 MByte pages, fully          |                                          
| 4CH 4DH 4EH 4FH                           | associative, 2 entries Data TLB: 4 KByte       |                                          
|                                           | pages, 4-way set associative, 64 entries       |                                          
|                                           | Data TLB: 4 MByte pages, 4-way set associative,|                                          
|                                           | 8 entries Data TLB1: 4 MByte pages,            |                                          
|                                           | 4-way set associative, 32 entries 1st-level    |                                          
|                                           | instruction cache: 8 KBytes, 4-way set         |                                          
|                                           | associative, 32 byte line size 1st-level       |                                          
|                                           | instruction cache: 16 KBytes, 4-way            |                                          
|                                           | set associative, 32 byte line size 1st-level   |                                          
|                                           | instruction cache: 32KBytes, 4-way set         |                                          
|                                           | associative, 64 byte line size 1st-level       |                                          
|                                           | data cache: 8 KBytes, 2-way set associative,   |                                          
|                                           | 32 byte line size Instruction TLB: 4           |                                          
|                                           | MByte pages, 4-way set associative,            |                                          
|                                           | 4 entries 1st-level data cache: 16 KBytes,     |                                          
|                                           | 4-way set associative, 32 byte line            |                                          
|                                           | size 1st-level data cache: 16 KBytes,          |                                          
|                                           | 4-way set associative, 64 byte line            |                                          
|                                           | size 1st-level data cache: 24 KBytes,          |                                          
|                                           | 6-way set associative, 64 byte line            |                                          
|                                           | size 2nd-level cache: 128 KBytes, 2-way        |                                          
|                                           | set associative, 64 byte line size 2nd-level   |                                          
|                                           | cache: 256 KBytes, 8-way set associative,      |                                          
|                                           | 64 byte line size 3rd-level cache: 512         |                                          
|                                           | KBytes, 4-way set associative, 64 byte         |                                          
|                                           | line size, 2 lines per sector 3rd-level        |                                          
|                                           | cache: 1 MBytes, 8-way set associative,        |                                          
|                                           | 64 byte line size, 2 lines per sector          |                                          
|                                           | 2nd-level cache: 1 MBytes, 16-way set          |                                          
|                                           | associative, 64 byte line size 3rd-level       |                                          
|                                           | cache: 2 MBytes, 8-way set associative,        |                                          
|                                           | 64 byte line size, 2 lines per sector          |                                          
|                                           | 3rd-level cache: 4 MBytes, 8-way set           |                                          
|                                           | associative, 64 byte line size, 2 lines        |                                          
|                                           | per sector 1st-level data cache: 32            |                                          
|                                           | KBytes, 8-way set associative, 64 byte         |                                          
|                                           | line size 1st-level instruction cache:         |                                          
|                                           | 32 KBytes, 8-way set associative, 64           |                                          
|                                           | byte line size No 2nd-level cache or,          |                                          
|                                           | if processor contains a valid 2nd-level        |                                          
|                                           | cache, no 3rd-level cache 2nd-level            |                                          
|                                           | cache: 128 KBytes, 4-way set associative,      |                                          
|                                           | 32 byte line size 2nd-level cache: 256         |                                          
|                                           | KBytes, 4-way set associative, 32 byte         |                                          
|                                           | line size 2nd-level cache: 512 KBytes,         |                                          
|                                           | 4-way set associative, 32 byte line            |                                          
|                                           | size 2nd-level cache: 1 MByte, 4-way           |                                          
|                                           | set associative, 32 byte line size 2nd-level   |                                          
|                                           | cache: 2 MByte, 4-way set associative,         |                                          
|                                           | 32 byte line size 3rd-level cache: 4           |                                          
|                                           | MByte, 4-way set associative, 64 byte          |                                          
|                                           | line size 3rd-level cache: 8 MByte,            |                                          
|                                           | 8-way set associative, 64 byte line            |                                          
|                                           | size 2nd-level cache: 3MByte, 12-way           |                                          
|                                           | set associative, 64 byte line size 3rd-level   |                                          
|                                           | cache: 4MB, 16-way set associative,            |                                          
|                                           | 64-byte line size (Intel Xeon processor        |                                          
|                                           | MP, Family 0FH, Model 06H); 2nd-level          |                                          
|                                           | cache: 4 MByte, 16-way set associative,        |                                          
|                                           | 64 byte line size 3rd-level cache: 6MByte,     |                                          
|                                           | 12-way set associative, 64 byte line           |                                          
|                                           | size 3rd-level cache: 8MByte, 16-way           |                                          
|                                           | set associative, 64 byte line size 3rd-level   |                                          
|                                           | cache: 12MByte, 12-way set associative,        |                                          
|                                           | 64 byte line size 3rd-level cache: 16MByte,    |                                          
|                                           | 16-way set associative, 64 byte line           |                                          
|                                           | size 2nd-level cache: 6MByte, 24-way           |                                          
|                                           | set associative, 64 byte line size Instruction |                                          
|                                           | TLB: 4 KByte pages, 32 entries Table           |                                          
|                                           | 3-22.                                          |                                          
| Value 50H 51H 52H 55H 56H 57H 59H 5AH     | Type Instruction TLB: 4 KByte and 2-MByte      | Description (Contd.)                     
| 5BH 5CH 5DH 60H 61H 63H 66H 67H 68H       | or 4-MByte pages, 64 entries Instruction       |                                          
| 70H 71H 72H 76H 78H 79H 7AH 7BH 7CH       | TLB: 4 KByte and 2-MByte or 4-MByte            |                                          
| 7DH 7FH 80H 82H 83H 84H 85H 86H 87H       | pages, 128 entries Instruction TLB:            |                                          
| A0H B0H B1H B2H B3H B4H                   | 4 KByte and 2-MByte or 4-MByte pages,          |                                          
|                                           | 256 entries Instruction TLB: 2-MByte           |                                          
|                                           | or 4-MByte pages, fully associative,           |                                          
|                                           | 7 entries Data TLB0: 4 MByte pages,            |                                          
|                                           | 4-way set associative, 16 entries Data         |                                          
|                                           | TLB0: 4 KByte pages, 4-way associative,        |                                          
|                                           | 16 entries Data TLB0: 4 KByte pages,           |                                          
|                                           | fully associative, 16 entries Data TLB0:       |                                          
|                                           | 2-MByte or 4 MByte pages, 4-way set            |                                          
|                                           | associative, 32 entries Data TLB: 4            |                                          
|                                           | KByte and 4 MByte pages, 64 entries            |                                          
|                                           | Data TLB: 4 KByte and 4 MByte pages,128        |                                          
|                                           | entries Data TLB: 4 KByte and 4 MByte          |                                          
|                                           | pages,256 entries 1st-level data cache:        |                                          
|                                           | 16 KByte, 8-way set associative, 64            |                                          
|                                           | byte line size Instruction TLB: 4 KByte        |                                          
|                                           | pages, fully associative, 48 entries           |                                          
|                                           | Data TLB: 1 GByte pages, 4-way set associative,|                                          
|                                           | 4 entries 1st-level data cache: 8 KByte,       |                                          
|                                           | 4-way set associative, 64 byte line            |                                          
|                                           | size 1st-level data cache: 16 KByte,           |                                          
|                                           | 4-way set associative, 64 byte line            |                                          
|                                           | size 1st-level data cache: 32 KByte,           |                                          
|                                           | 4-way set associative, 64 byte line            |                                          
|                                           | size Trace cache: 12 K-μop, 8-way set          |                                          
|                                           | associative Trace cache: 16 K-μop, 8-way       |                                          
|                                           | set associative Trace cache: 32 K-μop,         |                                          
|                                           | 8-way set associative Instruction TLB:         |                                          
|                                           | 2M/4M pages, fully associative, 8 entries      |                                          
|                                           | 2nd-level cache: 1 MByte, 4-way set            |                                          
|                                           | associative, 64byte line size 2nd-level        |                                          
|                                           | cache: 128 KByte, 8-way set associative,       |                                          
|                                           | 64 byte line size, 2 lines per sector          |                                          
|                                           | 2nd-level cache: 256 KByte, 8-way set          |                                          
|                                           | associative, 64 byte line size, 2 lines        |                                          
|                                           | per sector 2nd-level cache: 512 KByte,         |                                          
|                                           | 8-way set associative, 64 byte line            |                                          
|                                           | size, 2 lines per sector 2nd-level cache:      |                                          
|                                           | 1 MByte, 8-way set associative, 64 byte        |                                          
|                                           | line size, 2 lines per sector 2nd-level        |                                          
|                                           | cache: 2 MByte, 8-way set associative,         |                                          
|                                           | 64byte line size 2nd-level cache: 512          |                                          
|                                           | KByte, 2-way set associative, 64-byte          |                                          
|                                           | line size 2nd-level cache: 512 KByte,          |                                          
|                                           | 8-way set associative, 64-byte line            |                                          
|                                           | size 2nd-level cache: 256 KByte, 8-way         |                                          
|                                           | set associative, 32 byte line size 2nd-level   |                                          
|                                           | cache: 512 KByte, 8-way set associative,       |                                          
|                                           | 32 byte line size 2nd-level cache: 1           |                                          
|                                           | MByte, 8-way set associative, 32 byte          |                                          
|                                           | line size 2nd-level cache: 2 MByte,            |                                          
|                                           | 8-way set associative, 32 byte line            |                                          
|                                           | size 2nd-level cache: 512 KByte, 4-way         |                                          
|                                           | set associative, 64 byte line size 2nd-level   |                                          
|                                           | cache: 1 MByte, 8-way set associative,         |                                          
|                                           | 64 byte line size DTLB: 4k pages, fully        |                                          
|                                           | associative, 32 entries Instruction            |                                          
|                                           | TLB: 4 KByte pages, 4-way set associative,     |                                          
|                                           | 128 entries Instruction TLB: 2M pages,         |                                          
|                                           | 4-way, 8 entries or 4M pages, 4-way,           |                                          
|                                           | 4 entries Instruction TLB: 4KByte pages,       |                                          
|                                           | 4-way set associative, 64 entries Data         |                                          
|                                           | TLB: 4 KByte pages, 4-way set associative,     |                                          
|                                           | 128 entries Data TLB1: 4 KByte pages,          |                                          
|                                           | 4-way associative, 256 entries Table           |                                          
|                                           | 3-22.                                          |                                          
| Value B5H B6H BAH C0H C1H C2H CAH D0H     | Type Instruction TLB: 4KByte pages,            | Description Example 3-1. The first member
| D1H D2H D6H D7H D8H DCH DDH DEH E2H       | 8-way set associative, 64 entries Instruction  | of the family of Pentium 4 processors    
| E3H E4H EAH EBH ECH F0H F1H FFH EAX       | TLB: 4KByte pages, 8-way set associative,      | returns the following information about  
| EBX ECX EDX The least-significant byte    | 128 entries Data TLB1: 4 KByte pages,          | caches and TLBs when the CPUID executes  
| (byte 0) of register EAX is set to 01H.   | 4-way associative, 64 entries Data TLB:        | with an input value of 2: Which means:   
| This indicates that CPUID needs to be     | 4 KByte and 4 MByte pages, 4-way associative,  | •••••                                    
| executed once with an input value of      | 8 entries Shared 2nd-Level TLB: 4 KByte/2MByte |                                          
| 2 to retrieve complete information about  | pages, 8-way associative, 1024 entries         |                                          
| caches and TLBs. The most-significant     | DTLB: 4 KByte/2 MByte pages, 4-way associative,|                                          
| bit of all four registers (EAX, EBX,      | 16 entries Shared 2nd-Level TLB: 4 KByte       |                                          
| ECX, and EDX) is set to 0, indicating     | pages, 4-way associative, 512 entries          |                                          
| that each register contains valid 1-byte  | 3rd-level cache: 512 KByte, 4-way set          |                                          
| descriptors. Bytes 1, 2, and 3 of register| associative, 64 byte line size 3rd-level       |                                          
| EAX indicate that the processor has:      | cache: 1 MByte, 4-way set associative,         |                                          
|  -  -  - The descriptors in registers EBX       | 64 byte line size 3rd-level cache: 2           |                                          
| and ECX are valid, but contain NULL       | MByte, 4-way set associative, 64 byte          |                                          
| descriptors. Bytes 0, 1, 2, and 3 of      | line size 3rd-level cache: 1 MByte,            |                                          
| register EDX indicate that the processor  | 8-way set associative, 64 byte line            |                                          
| has:  -  -  -  -                                  | size 3rd-level cache: 2 MByte, 8-way           |                                          
|                                           | set associative, 64 byte line size 3rd-level   |                                          
|                                           | cache: 4 MByte, 8-way set associative,         |                                          
|                                           | 64 byte line size 3rd-level cache: 1.5         |                                          
|                                           | MByte, 12-way set associative, 64 byte         |                                          
|                                           | line size 3rd-level cache: 3 MByte,            |                                          
|                                           | 12-way set associative, 64 byte line           |                                          
|                                           | size 3rd-level cache: 6 MByte, 12-way          |                                          
|                                           | set associative, 64 byte line size 3rd-level   |                                          
|                                           | cache: 2 MByte, 16-way set associative,        |                                          
|                                           | 64 byte line size 3rd-level cache: 4           |                                          
|                                           | MByte, 16-way set associative, 64 byte         |                                          
|                                           | line size 3rd-level cache: 8 MByte,            |                                          
|                                           | 16-way set associative, 64 byte line           |                                          
|                                           | size 3rd-level cache: 12MByte, 24-way          |                                          
|                                           | set associative, 64 byte line size 3rd-level   |                                          
|                                           | cache: 18MByte, 24-way set associative,        |                                          
|                                           | 64 byte line size 3rd-level cache: 24MByte,    |                                          
|                                           | 24-way set associative, 64 byte line           |                                          
|                                           | size 64-Byte prefetching 128-Byte prefetching  |                                          
|                                           | CPUID leaf 2 does not report cache descriptor  |                                          
|                                           | information, use CPUID leaf 4 to query         |                                          
|                                           | cache parameters Example of Cache and          |                                          
|                                           | TLB Interpretation 66 5B 50 01H 0H 0H          |                                          
|                                           | 00 7A 70 00H 50H - a 64-entry instruction      |                                          
|                                           | TLB, for mapping 4-KByte and 2-MByte           |                                          
|                                           | or 4-MByte pages. 5BH - a 64-entry data        |                                          
|                                           | TLB, for mapping 4-KByte and 4-MByte           |                                          
|                                           | pages. 66H - an 8-KByte 1st level data         |                                          
|                                           | cache, 4-way set associative, with a           |                                          
|                                           | 64-Byte cache line size. 00H - NULL            |                                          
|                                           | descriptor. 70H - Trace cache: 12 K-μop,       |                                          
|                                           | 8-way set associative. 7AH - a 256-KByte       |                                          
|                                           | 2nd level cache, 8-way set associative,        |                                          
|                                           | with a sectored, 64-byte cache line            |                                          
|                                           | size. 00H - NULL descriptor.                   |                                          

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level:
When CPUID executes with EAX set to 04H and ECX contains an index value, the
processor returns encoded data that describe a set of deterministic cache parameters
(for the cache level associated with the input in ECX). Valid index values start
from 0.

Software can enumerate the deterministic cache parameters for each level of
the cache hierarchy starting with an index value of 0, until the parameters
report the value associated with the cache type field is 0. The architecturally
defined fields reported by deterministic cache parameters are documented in
Table 3-17.

This Cache Size in Bytes

= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)

= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)

The CPUID leaf 04H also reports data that can be used to derive the topology
of processor cores in a physical package. This information is constant for all
valid index values. Software can query the raw data reported by executing CPUID
with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm
described in Chapter 8, “Multiple-Processor Management,” in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.


INPUT EAX = 05H: Returns MONITOR and MWAIT Features:
When CPUID executes with EAX set to 05H, the processor returns information about
features available to MONITOR/MWAIT instructions. The MONITOR instruction is
used for address-range monitoring in conjunction with MWAIT instruction. The
MWAIT instruction optionally provides additional extensions for advanced power
management. See Table 3-17.


INPUT EAX = 06H: Returns Thermal and Power Management Features:
When CPUID executes with EAX set to 06H, the processor returns information about
thermal and power management features. See Table 3-17.


INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information:
When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information
about the maximum input value for sub-leaves that contain extended feature flags.
See Table 3-17.

When CPUID executes with EAX set to 07H and the input value of ECX is invalid
(see leaf 07H entry in Table 3-17), the processor returns 0 in EAX/EBX/ECX/EDX.
In subleaf 0, EAX returns the maximum input value of the highest leaf 7 sub-leaf,
and EBX, ECX & EDX contain information of extended feature flags.


INPUT EAX = 09H: Returns Direct Cache Access Information:
When CPUID executes with EAX set to 09H, the processor returns information about
Direct Cache Access capabilities. See Table 3-17.


INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features:
When CPUID executes with EAX set to 0AH, the processor returns information about
support for architectural performance monitoring capabilities. Architectural
performance monitoring is supported if the version ID (see Table 3-17) is greater
than Pn 0. See Table 3-17.

For each version of architectural performance monitoring capability, software
must enumerate this leaf to discover the programming facilities and the architectural
performance events available in the processor. The details are described in
Chapter 23, “Introduction to Virtual-Machine Extensions,” in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 3C.


INPUT EAX = 0BH: Returns Extended Topology Information:
When CPUID executes with EAX set to 0BH, the processor returns information about
extended topology enumeration data. Software must detect the presence of CPUID
leaf 0BH by verifying (a) the highest leaf index supported by CPUID is >= 0BH,
and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-17.


INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information:
When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information
about the bit-vector representation of all processor state extensions that are
supported in the processor and storage size requirements of the XSAVE/XRSTOR
area. See Table 3-17.

When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf
index), the processor returns information about the size and offset of each
processor extended state save area within the XSAVE/XRSTOR area. See Table 3-17.
Software can use the forward-extendable technique depicted below to query the
valid sub-leaves and obtain size and offset information for each processor extended
state save area:

For i = 2 to 62 // sub-leaf 1 is reserved IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i]
= 1 ) // VECTOR is the 64-bit value of EDX:EAX Execute CPUID.(EAX=0DH, ECX =
i) to examine size and offset for sub-leaf i; FI;


INPUT EAX = 0FH: Returns Platform Quality of Service (PQoS) Monitoring Enumeration Information:
When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information
about the bit-vector representation of QoS monitoring resource types that are
supported in the processor and maximum range of RMID values the processor can
use to monitor of any supported resource types. Each bit, starting from bit
1, corresponds to a specific resource type if the bit is set. The bit position
corresponds to the sub-leaf index (or ResID) that software must use to query
QoS monitoring capability available for that type. See Table 3-17.

When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid
ResID), the processor returns information software can use to program IA32_PQR_ASSOC,
IA32_QM_EVTSEL MSRs before reading QoS data from the IA32_QM_CTR MSR.


INPUT EAX = 10H: Returns Platform Quality of Service (PQoS) Enforcement Enumeration Information:
When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information
about the bit-vector representation of QoS Enforcement resource types that are
supported in the processor. Each bit, starting from bit 1, corresponds to a
specific resource type if the bit is set. The bit position corresponds to the
sub-leaf index (or ResID) that software must use to query QoS enforcement capability
available for that type. See Table 3-17.

When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid
ResID), the processor returns information about available classes of service
and range of QoS mask MSRs that software can use to configure each class of
services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.


METHODS FOR RETURNING BRANDING INFORMATION:
Use the following techniques to access branding information:

| 1.| Processor brand string method; this    
|   | method also returns the processor's    
|   | maximum operating frequency            
| 2.| Processor brand index; this method uses
|   | a software supplied brand string table.
These two methods are discussed in the following sections. For methods that
are available in early processors, see Section: “Identification of Earlier IA-32
Processors” in Chapter 17 of the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1.


The Processor Brand String Method:
Figure 3-8 describes the algorithm used for detection of the brand string. Processor
brand identification software should execute this algorithm on all Intel 64
and IA-32 processors.

This method (introduced with Pentium 4 processors) returns an ASCII brand identification
string and the maximum operating frequency of the processor to the EAX, EBX,
ECX, and EDX registers.

Input: EAX=0x80000000

CPUID

| False| Processor Brand String Not Supported
CPUID True ≥Function Extended Supported

EAX Return Value =Max. Extended CPUID Function Index

True

| IF (EAX Return Value ≥ 0x80000004)| Processor Brand String Supported
OM15194

| Figure 3-8.| Determination of Support for the Processor
|            | Brand String                              

How Brand Strings Work:
To use the brand string method, execute CPUID with EAX input of 8000002H through
80000004H. For each input value, CPUID returns 16 ASCII characters using EAX,
EBX, ECX, and EDX. The returned string will be NULL-terminated.

Table 3-23 shows the brand string that is returned by the first processor in
the Pentium 4 processor family.


Table 3-23. Processor Brand String Returned with Pentium 4 Processor:
| EAX Input Value| Return Values                              | ASCII Equivalent                      
| Table 3-23.    | Processor Brand String Returned with       | (Contd.) ””””“(let”“P )R”“itne”“R(mu”“
|                | Pentium 4 Processor EAX = 20202020H        | 4 )”“ UPC”“0051”“\0zHM”               
|                | EBX = 20202020H ECX = 20202020H EDX        |                                       
|                | = 6E492020H EAX = 286C6574H EBX = 50202952H|                                       
|                | ECX = 69746E65H EDX = 52286D75H EAX        |                                       
|                | = 20342029H EBX = 20555043H ECX = 30303531H|                                       
|                | EDX = 007A484DH                            |                                       

Extracting the Maximum Processor Frequency from Brand Strings:
Figure 3-9 provides an algorithm which software can use to extract the maximum
processor operating frequency from the processor brand string.


NOTE:
When a frequency is given in a brand string, it is the maximum qualified frequency
of the processor, not the frequency at which the processor is currently running.

| Figure 3-9.| Algorithm for Extracting Maximum Processor
|            | Frequency                                 

The Processor Brand Index Method:
The brand index method (introduced with Pentium® III Xeon® processors) provides
an entry point into a brand identification table that is maintained in memory
by system software and is accessible from system- and user-level code. In this
table, each brand index is associate with an ASCII brand identification string
that identifies the official Intel family and model number of a processor.

When CPUID executes with EAX set to 1, the processor returns a brand index to
the low byte in EBX. Software can then use this index to locate the brand identification
string for the processor in the brand identification table. The first entry
(brand index 0) in this table is reserved, allowing for backward compatibility
with processors that do not support the brand identification feature. Starting
with processor signature family ID = 0FH, model = 03H, brand index method is
no longer supported. Use brand string method instead.

Table 3-24 shows brand indices that have identification strings associated with
them.


Table 3-24. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings:
| Brand Index This processor does not         | Brand String                         
| support the brand identification feature    |                                      
| Intel(R) Celeron(R) processor1 Intel(R)     |                                      
| Pentium(R) III processor1                   |                                      
| Table 3-24. Intel(R) Pentium(R) III         | Mapping of Brand Indices; and Intel  
| Xeon(R) processor; If processor signature   | 64 and IA-32 Processor Brand Strings 
| = 000006B1h, then Intel(R) Celeron(R)       | NOTES: 1. Indicates versions of these
| processor Intel(R) Pentium(R) III processor | processors that were introduced after
| Mobile Intel(R) Pentium(R) III processor-M  | the Pentium III                      
| Mobile Intel(R) Celeron(R) processor1       |                                      
| Intel(R) Pentium(R) 4 processor Intel(R)    |                                      
| Pentium(R) 4 processor Intel(R) Celeron(R)  |                                      
| processor1 Intel(R) Xeon(R) processor;      |                                      
| If processor signature = 00000F13h,         |                                      
| then Intel(R) Xeon(R) processor MP Intel(R) |                                      
| Xeon(R) processor MP Mobile Intel(R)        |                                      
| Pentium(R) 4 processor-M; If processor      |                                      
| signature = 00000F13h, then Intel(R)        |                                      
| Xeon(R) processor Mobile Intel(R) Celeron(R)|                                      
| processor1 Mobile Genuine Intel(R) processor|                                      
| Intel(R) Celeron(R) M processor Mobile      |                                      
| Intel(R) Celeron(R) processor1 Intel(R)     |                                      
| Celeron(R) processor Mobile Genuine         |                                      
| Intel(R) processor Intel(R) Pentium(R)      |                                      
| M processor Mobile Intel(R) Celeron(R)      |                                      
| processor1 RESERVED                         |                                      

IA-32 Architecture Compatibility:
CPUID is not supported in early models of the Intel486 processor or in any IA-32
processor earlier than the Intel486 processor.

Operation:

IA32_BIOS_SIGN_ID MSR <- Update with installed microcode revision number;
CASE (EAX) OF
  EAX = 0:
     EAX <- Highest basic function input value understood by CPUID;
     EBX <- Vendor identification string;
     EDX <- Vendor identification string;
     ECX <- Vendor identification string;
  BREAK;
  EAX = 1H:
     EAX[3:0] <- Stepping ID;
     EAX[7:4] <- Model;
     EAX[11:8] <- Family;
     EAX[13:12] <- Processor type;
     EAX[15:14] <- Reserved;
     EAX[19:16] <- Extended Model;
     EAX[27:20] <- Extended Family;
     EAX[31:28] <- Reserved;
     EBX[7:0] <- Brand Index; (* Reserved if the value is zero. *)
     EBX[15:8] <- CLFLUSH Line Size;
     EBX[16:23] <- Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
     EBX[24:31] <- Initial APIC ID;
     ECX <- Feature flags; (* See Figure 3-6. *)
     EDX <- Feature flags; (* See Figure 3-7. *)
  BREAK;
  EAX = 2H:
     EAX <- Cache and TLB information;
     EBX <- Cache and TLB information;
     ECX <- Cache and TLB information;
     EDX <- Cache and TLB information;
  BREAK;
  EAX = 3H:
     EAX <- Reserved;
     EBX <- Reserved;
     ECX <- ProcessorSerialNumber[31:0];
     (* Pentium III processors only, otherwise reserved. *)
     EDX <- ProcessorSerialNumber[63:32];
     (* Pentium III processors only, otherwise reserved. *
  BREAK
  EAX = 4H:
     EAX <- Deterministic Cache Parameters Leaf; (* See Table 3-17. *)
     EBX <- Deterministic Cache Parameters Leaf;
     ECX <- Deterministic Cache Parameters Leaf;
     EDX <- Deterministic Cache Parameters Leaf;
  BREAK;
  EAX = 5H:
     EAX <- MONITOR/MWAIT Leaf; (* See Table 3-17. *)
     EBX <- MONITOR/MWAIT Leaf;
     ECX <- MONITOR/MWAIT Leaf;
     EDX <- MONITOR/MWAIT Leaf;
  BREAK;
  EAX = 6H:
     EAX <- Thermal and Power Management Leaf; (* See Table 3-17. *)
     EBX <- Thermal and Power Management Leaf;
     ECX <- Thermal and Power Management Leaf;
     EDX <- Thermal and Power Management Leaf;
  BREAK;
  EAX = 7H:
     EAX <- Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-17. *)
     EBX <- Structured Extended Feature Flags Enumeration Leaf;
     ECX <- Structured Extended Feature Flags Enumeration Leaf;
     EDX <- Structured Extended Feature Flags Enumeration Leaf;
  BREAK;
  EAX = 8H:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Reserved = 0;
     EDX <- Reserved = 0;
  BREAK;
  EAX = 9H:
     EAX <- Direct Cache Access Information Leaf; (* See Table 3-17. *)
     EBX <- Direct Cache Access Information Leaf;
     ECX <- Direct Cache Access Information Leaf;
     EDX <- Direct Cache Access Information Leaf;
  BREAK;
  EAX = AH:
     EAX <- Architectural Performance Monitoring Leaf; (* See Table 3-17. *)
     EBX <- Architectural Performance Monitoring Leaf;
     ECX <- Architectural Performance Monitoring Leaf;
     EDX <- Architectural Performance Monitoring Leaf;
     BREAK
  EAX = BH:
     EAX <- Extended Topology Enumeration Leaf; (* See Table 3-17. *)
     EBX <- Extended Topology Enumeration Leaf;
     ECX <- Extended Topology Enumeration Leaf;
     EDX <- Extended Topology Enumeration Leaf;
  BREAK;
  EAX = CH:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Reserved = 0;
     EDX <- Reserved = 0;
  BREAK;
  EAX = DH:
     EAX <- Processor Extended State Enumeration Leaf; (* See Table 3-17. *)
     EBX <- Processor Extended State Enumeration Leaf;
     ECX <- Processor Extended State Enumeration Leaf;
     EDX <- Processor Extended State Enumeration Leaf;
  BREAK;
  EAX = EH:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Reserved = 0;
     EDX <- Reserved = 0;
  BREAK;
  EAX = FH:
     EAX <- Platform Quality of Service Monitoring Enumeration Leaf; (* See Table 3-17. *)
     EBX <- Platform Quality of Service Monitoring Enumeration Leaf;
     ECX <- Platform Quality of Service Monitoring Enumeration Leaf;
     EDX <- Platform Quality of Service Monitoring Enumeration Leaf;
  BREAK;
  EAX = 10H:
     EAX <- Platform Quality of Service Enforcement Enumeration Leaf; (* See Table 3-17. *)
     EBX <- Platform Quality of Service Enforcement Enumeration Leaf;
     ECX <- Platform Quality of Service Enforcement Enumeration Leaf;
     EDX <- Platform Quality of Service Enforcement Enumeration Leaf;
  BREAK;
BREAK;
  EAX = 80000000H:
     EAX <- Highest extended function input value understood by CPUID;
     EBX <- Reserved;
     ECX <- Reserved;
     EDX <- Reserved;
  BREAK;
  EAX = 80000001H:
     EAX <- Reserved;
     EBX <- Reserved;
     ECX <- Extended Feature Bits (* See Table 3-17.*);
     EDX <- Extended Feature Bits (* See Table 3-17. *);
  BREAK;
  EAX = 80000002H:
     EAX <- Processor Brand String;
     EBX <- Processor Brand String, continued;
     ECX <- Processor Brand String, continued;
     EDX <- Processor Brand String, continued;
  BREAK;
  EAX = 80000003H:
     EAX <- Processor Brand String, continued;
     EBX <- Processor Brand String, continued;
     ECX <- Processor Brand String, continued;
     EDX <- Processor Brand String, continued;
  BREAK;
  EAX = 80000004H:
     EAX <- Processor Brand String, continued;
     EBX <- Processor Brand String, continued;
     ECX <- Processor Brand String, continued;
     EDX <- Processor Brand String, continued;
  BREAK;
  EAX = 80000005H:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Reserved = 0;
     EDX <- Reserved = 0;
  BREAK;
  EAX = 80000006H:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Cache information;
     EDX <- Reserved = 0;
  BREAK;
  EAX = 80000007H:
     EAX <- Reserved = 0;
     EBX <- Reserved = 0;
     ECX <- Reserved = 0;
     EDX <- Reserved = Misc Feature Flags;
  BREAK;
  EAX = 80000008H:
     EAX <- Reserved = Physical Address Size Information;
     EBX <- Reserved = Virtual Address Size Information;
     ECX <- Reserved = 0;
     EDX <- Reserved = 0;
  BREAK;
  EAX >= 40000000H and EAX <= 4FFFFFFFH:
  DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
     (* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
     EAX <- Reserved; (* Information returned for highest basic information leaf. *)
     EBX <- Reserved; (* Information returned for highest basic information leaf. *)
     ECX <- Reserved; (* Information returned for highest basic information leaf. *)
     EDX <- Reserved; (* Information returned for highest basic information leaf. *)
  BREAK;
ESAC;

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used. In earlier 
|    | IA-32 processors that do not support   
|    | the CPUID instruction, execution of    
|    | the instruction results in an invalid  
|    | opcode (#UD) exception being generated.


platform: x86
mnem: CRC32
description:
CRC32  -  Accumulate CRC32 Value:
| Opcode/Instruction                   | Op/En| 64-Bit Mode| Compat/Leg Mode| Description               
| F2 0F 38 F0 /r CRC32 r32, r/m8       | RM   | Valid      | Valid          | Accumulate CRC32 on r/m8. 
| F2 REX 0F 38 F0 /r CRC32 r32, r/m8*  | RM   | Valid      | N.E.           | Accumulate CRC32 on r/m8. 
| F2 0F 38 F1 /r CRC32 r32, r/m16      | RM   | Valid      | Valid          | Accumulate CRC32 on r/m16.
| F2 0F 38 F1 /r CRC32 r32, r/m32      | RM   | Valid      | Valid          | Accumulate CRC32 on r/m32.
| F2 REX.W 0F 38 F0 /r CRC32 r64, r/m8 | RM   | Valid      | N.E.           | Accumulate CRC32 on r/m8. 
| F2 REX.W 0F 38 F1 /r CRC32 r64, r/m64| RM   | Valid      | N.E.           | Accumulate CRC32 on r/m64.
Notes: *In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       

Description:
Starting with an initial value in the first operand (destination operand), accumulates
a CRC32 (polynomial 0x11EDC6F41) value for the second operand (source operand)
and stores the result in the destination operand. The source operand can be
a register or a memory location. The destination operand must be an r32 or r64
register. If the destination is an r64 register, then the 32-bit result is stored
in the least significant double word and 00000000H is stored in the most significant
double word of the r64 register.

The initial value supplied in the destination operand is a double word integer
stored in the r32 register or the least significant double word of the r64 register.
To incrementally accumulate a CRC32 value, software retains the result of the
previous CRC32 operation in the destination operand, then executes the CRC32
instruction again with new input data in the source operand. Data contained
in the source operand is processed in reflected bit order. This means that the
most significant bit of the source operand is treated as the least significant
bit of the quotient, and so on, for all the bits of the source operand. Likewise,
the result of the CRC operation is stored in the destination operand in reflected
bit order. This means that the most significant bit of the resulting CRC (bit
31) is stored in the least significant bit of the destination operand (bit 0),
and so on, for all the bits of the CRC.

Operation:

Notes: 

BIT_REFLECT64: DST[63-0] = SRC[0-63]BIT_REFLECT32: DST[31-0] = SRC[0-31]BIT_REFLECT16:
DST[15-0] = SRC[0-15]BIT_REFLECT8: DST[7-0] = SRC[0-7]MOD2: Remainder from Polynomial
division modulus 2

CRC32 instruction for 64-bit source operand and 64-bit destination operand:

TEMP1[63-0]  BIT_REFLECT64 (SRC[63-0]) TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[95-0]  TEMP1[63-0] « 32 TEMP4[95-0]  TEMP2[31-0] « 64 TEMP5[95-0] 
TEMP3[95-0] XOR TEMP4[95-0]TEMP6[31-0]  TEMP5[95-0] MOD2 11EDC6F41H DEST[31-0]
 BIT_REFLECT (TEMP6[31-0]) DEST[63-32]  00000000H

CRC32 instruction for 32-bit source operand and 32-bit destination operand:

TEMP1[31-0]  BIT_REFLECT32 (SRC[31-0]) TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[63-0]  TEMP1[31-0] « 32 TEMP4[63-0]  TEMP2[31-0] « 32 TEMP5[63-0] 
TEMP3[63-0] XOR TEMP4[63-0]TEMP6[31-0]  TEMP5[63-0] MOD2 11EDC6F41H DEST[31-0]
 BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 16-bit source operand and 32-bit destination operand:

TEMP1[15-0]  BIT_REFLECT16 (SRC[15-0]) TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[47-0]  TEMP1[15-0] « 32 TEMP4[47-0]  TEMP2[31-0] « 16 TEMP5[47-0] 
TEMP3[47-0] XOR TEMP4[47-0]TEMP6[31-0]  TEMP5[47-0] MOD2 11EDC6F41H DEST[31-0]
 BIT_REFLECT (TEMP6[31-0])

CRC32 instruction for 8-bit source operand and 64-bit destination operand:

TEMP1[7-0]  BIT_REFLECT8(SRC[7-0]) TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0]  TEMP1[7-0] « 32 TEMP4[39-0]  TEMP2[31-0] « 8 TEMP5[39-0]  TEMP3[39-0]
XOR TEMP4[39-0]TEMP6[31-0]  TEMP5[39-0] MOD2 11EDC6F41H DEST[31-0]  BIT_REFLECT
(TEMP6[31-0]) DEST[63-32]  00000000H

CRC32 instruction for 8-bit source operand and 32-bit destination operand:

TEMP1[7-0]  BIT_REFLECT8(SRC[7-0]) TEMP2[31-0]  BIT_REFLECT32 (DEST[31-0])
TEMP3[39-0]  TEMP1[7-0] « 32 TEMP4[39-0]  TEMP2[31-0] « 8 TEMP5[39-0]  TEMP3[39-0]
XOR TEMP4[39-0]TEMP6[31-0]  TEMP5[39-0] MOD2 11EDC6F41H DEST[31-0]  BIT_REFLECT
(TEMP6[31-0])


Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data ) unsigned int
_mm_crc32_u16( unsigned int crc, unsigned short data ) unsigned int _mm_crc32_u32(
unsigned int crc, unsigned int data ) unsinged __int64 _mm_crc32_u64( unsinged
__int64 crc, unsigned __int64 data )


SIMD Floating Point Exceptions:
None


Protected Mode Exceptions:
| #GP(0)          | If a memory operand effective address
|                 | is outside the CS, DS, ES, FS or GS  
|                 | segments.                            
| #SS(0)          | If a memory operand effective address
|                 | is outside the SS segment limit.     
| #PF (fault-code)| For a page fault.                    
| #AC(0)          | If alignment checking is enabled and 
|                 | an unaligned memory reference is made
|                 | while the current privilege level is 
|                 | 3.                                   
| #UD             | If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
|                 | If LOCK prefix is used.              

Real-Address Mode Exceptions:
| #GP(0)| If any part of the operand lies outside
|       | of the effective address space from    
|       | 0 to 0FFFFH.                           
| #SS(0)| If a memory operand effective address  
|       | is outside the SS segment limit.       
| #UD   | If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.  
|       | If LOCK prefix is used.                

Virtual 8086 Mode Exceptions:
| #GP(0)          | If any part of the operand lies outside
|                 | of the effective address space from    
|                 | 0 to 0FFFFH.                           
| #SS(0)          | If a memory operand effective address  
|                 | is outside the SS segment limit.       
| #PF (fault-code)| For a page fault.                      
| #AC(0)          | If alignment checking is enabled and   
|                 | an unaligned memory reference is made. 
| #UD             | If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.  
|                 | If LOCK prefix is used.                

Compatibility Mode Exceptions:
Same exceptions as in Protected Mode.


64-Bit Mode Exceptions:
| #GP(0)          | If the memory address is in a non-canonical
|                 | form.                                      
| #SS(0)          | If a memory address referencing the        
|                 | SS segment is in a non-canonical form.     
| #PF (fault-code)| For a page fault.                          
| #AC(0)          | If alignment checking is enabled and       
|                 | an unaligned memory reference is made      
|                 | while the current privilege level is       
|                 | 3.                                         
| #UD             | If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.      
|                 | If LOCK prefix is used.                    


platform: x86
mnem: CVTDQ2PD
description:
CVTDQ2PD - Convert Packed Dword Integers to Packed Double-Precision FP Values:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                           
| F3 0F E6 CVTDQ2PD xmm1, xmm2/m64       | RM   | V/V           | SSE2              | Convert two packed signed doubleword  
|                                        |      |               |                   | integers from xmm2/m128 to two packed 
|                                        |      |               |                   | double-precision floating-point values
|                                        |      |               |                   | in xmm1.                              
| VEX.128.F3.0F.WIG E6 /r VCVTDQ2PD xmm1,| RM   | V/V           | AVX               | Convert two packed signed doubleword  
| xmm2/m64                               |      |               |                   | integers from xmm2/mem to two packed  
|                                        |      |               |                   | double-precision floating-point values
|                                        |      |               |                   | in xmm1.                              
| VEX.256.F3.0F.WIG E6 /r VCVTDQ2PD ymm1,| RM   | V/V           | AVX               | Convert four packed signed doubleword 
| xmm2/m128                              |      |               |                   | integers from xmm2/mem to four packed 
|                                        |      |               |                   | double-precision floating-point values
|                                        |      |               |                   | in ymm1.                              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed signed doubleword integers in the source operand (second
operand) to two packed doubleprecision floating-point values in the destination
operand (first operand).

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 64- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding XMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 64- bit memory location. The destination operation is an XMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 128- bit memory
location. The destination operation is a YMM register. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

| SRC X3| X3 X2| X2 X1| X1| X0 X0
DEST

| Figure 3-10.| CVTDQ2PD (VEX.256 encoded version)
Operation:

CVTDQ2PD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[VLMAX-1:128] (unmodified)
VCVTDQ2PD (VEX.128 encoded version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[VLMAX-1:128] <- 0
VCVTDQ2PD (VEX.256 encoded version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTDQ2PD: | __m128d _mm_cvtepi32_pd(__m128i a) 
| VCVTDQ2PD:| __m256d _mm256_cvtepi32_pd (__m128i
|           | src)                               

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTDQ2PS
description:
CVTDQ2PS - Convert Packed Dword Integers to Packed Single-Precision FP Values:
| Opcode/Instruction                  | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                           
| 0F 5B /r CVTDQ2PS xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert four packed signed doubleword 
|                                     |      |               |                   | integers from xmm2/m128 to four packed
|                                     |      |               |                   | single-precision floating-point values
|                                     |      |               |                   | in xmm1.                              
| VEX.128.0F.WIG 5B /r VCVTDQ2PS xmm1,| RM   | V/V           | AVX               | Convert four packed signed doubleword 
| xmm2/m128                           |      |               |                   | integers from xmm2/mem to four packed 
|                                     |      |               |                   | single-precision floating-point values
|                                     |      |               |                   | in xmm1.                              
| VEX.256.0F.WIG 5B /r VCVTDQ2PS ymm1,| RM   | V/V           | AVX               | Convert eight packed signed doubleword
| ymm2/m256                           |      |               |                   | integers from ymm2/mem to eight packed
|                                     |      |               |                   | single-precision floating-point values
|                                     |      |               |                   | in ymm1.                              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts four packed signed doubleword integers in the source operand (second
operand) to four packed singleprecision floating-point values in the destination
operand (first operand).

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. The upper bits (VLMAX-1:128) of the corresponding XMM register destination
are unmodified. VEX.128 encoded version: The source operand is an XMM register
or 128- bit memory location. The destination operation is an XMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is a YMM register. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

Operation:

CVTDQ2PS (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[VLMAX-1:128] (unmodified)
VCVTDQ2PS (VEX.128 encoded version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[VLMAX-1:128] <- 0
VCVTDQ2PS (VEX.256 encoded version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[159:128] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTDQ2PS: | __m128 _mm_cvtepi32_ps(__m128i a)      
| VCVTDQ2PS:| __m256 _mm256_cvtepi32_ps (__m256i src)

SIMD Floating-Point Exceptions:
Precision.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTPD2DQ
description:
CVTPD2DQ - Convert Packed Double-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                             
| F2 0F E6 /r CVTPD2DQ xmm1, xmm2/m128   | RM   | V/V           | SSE2              | Convert two packed double-precision     
|                                        |      |               |                   | floatingpoint values from xmm2/m128     
|                                        |      |               |                   | to two packed signed doubleword integers
|                                        |      |               |                   | in xmm1.                                
| VEX.128.F2.0F.WIG E6 /r VCVTPD2DQ xmm1,| RM   | V/V           | AVX               | Convert two packed double-precision     
| xmm2/m128                              |      |               |                   | floatingpoint values in xmm2/mem to     
|                                        |      |               |                   | two signed doubleword integers in xmm1. 
| VEX.256.F2.0F.WIG E6 /r VCVTPD2DQ xmm1,| RM   | V/V           | AVX               | Convert four packed double-precision    
| ymm2/m256                              |      |               |                   | floatingpoint values in ymm2/mem to     
|                                        |      |               |                   | four signed doubleword integers in xmm1.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed double-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. The result is stored in the low quadword
of the destination operand and the high quadword is cleared to all 0s.

When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (80000000H)
is returned.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The source operand is an
XMM register or 128- bit memory location. The destination operation is an XMM
register. Bits[127:64] of the destination XMM register are zeroed. However,
the upper bits (VLMAX-1:128) of the corresponding YMM register destination are
unmodified. VEX.128 encoded version: The source operand is an XMM register or
128- bit memory location. The destination operation is a YMM register. The upper
bits (VLMAX-1:64) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory
location. The destination operation is an XMM register. The upper bits (255:128)
of the corresponding YMM register destination are zeroed. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will
#UD.

| SRC DEST| X3 Figure 3-11.| X2 0 VCVTPD2DQ (VEX.256 encoded version)| X1 X2| X0 X0
Operation:

CVTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[127:64] <- 0
DEST[VLMAX-1:128] (unmodified)
VCVTPD2DQ (VEX.128 encoded version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[VLMAX-1:64] <- 0
VCVTPD2DQ (VEX.256 encoded version)
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[95:64] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])
DEST[127:96] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)
DEST[255:128]<- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPD2DQ:| __m128i _mm_cvtpd_epi32 (__m128d src)
| CVTPD2DQ:| __m128i _mm256_cvtpd_epi32 (__m256d  
|          | src)                                 

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: CVTPD2PI
description:
CVTPD2PI - Convert Packed Double-Precision FP Values to Packed Dword Integers:
| Opcode/Instruction               | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 66 0F 2D /r CVTPD2PI mm, xmm/m128| RM   | Valid      | Valid          | Convert two packed double-precision  
|                                  |      |            |                | floatingpoint values from xmm/m128 to
|                                  |      |            |                | two packed signed doubleword integers
|                                  |      |            |                | in mm.                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts two packed double-precision floating-point values in the source operand
(second operand) to two packed signed doubleword integers in the destination
operand (first operand).

The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an MMX technology register.

When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (80000000H)
is returned.

This instruction causes a transition from x87 FPU to MMX technology operation
(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word
is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPD2PI
instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent:
| CVTPD1PI:| __m64 _mm_cvtpd_pi32(__m128d a)

SIMD Floating-Point Exceptions:
Invalid, Precision.


Other Exceptions:
See Table 22-4, “Exception Conditions for Legacy SIMD/MMX Instructions with
FP Exception and 16-Byte Alignment,” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3B.


