# instructions

platform: ARM
mnem: UQSHL
description:
       Unsigned saturating shift left (immediate)       (C7.3.327)


       Scalar


           31 30 29 28 27 26 25 24 23 22        19 18    16 15 14 13 12 11 10 9        5 4    0
            0 1 1 1 1 1 1 1 0            !=0000      immb     0 1 1 1 0 1           Rn     Rd
                  U                       immh                        op


       Scalar variant

       UQSHL <V><d>, <V><n>, #<shift>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if immh == '0000' then ReservedValue();
         integer esize = 8 << HighestSetBit(immh);
         integer datasize = esize;
         integer elements = 1;

         integer shift = UInt(immh:immb) - esize;

         boolean src_unsigned;
         boolean dst_unsigned;
         case op:U of
              when '00' UnallocatedEncoding();
              when '01' src_unsigned = FALSE; dst_unsigned = TRUE;
              when '10' src_unsigned = FALSE; dst_unsigned = FALSE;
              when '11' src_unsigned = TRUE;    dst_unsigned = TRUE;


       Vector


           31 30 29 28 27 26 25 24 23 22        19 18    16 15 14 13 12 11 10 9        5 4    0
            0 Q 1 0 1 1 1 1 0            !=0000      immb     0 1 1 1 0 1           Rn     Rd
                  U                       immh                        op


       Vector variant

       UQSHL <Vd>.<T>, <Vn>.<T>, #<shift>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if immh == '0000' then SEE "Advanced SIMD modified immediate";
         if immh<3>:Q == '10' then ReservedValue();
         integer esize = 8 << HighestSetBit(immh);
         integer datasize = if Q == '1' then 128 else 64;
         integer elements = datasize DIV esize;

         integer shift = UInt(immh:immb) - esize;

         boolean src_unsigned;
         boolean dst_unsigned;
         case op:U of
              when '00' UnallocatedEncoding();
    when '01' src_unsigned = FALSE; dst_unsigned = TRUE;
    when '10' src_unsigned = FALSE; dst_unsigned = FALSE;
    when '11' src_unsigned = TRUE;      dst_unsigned = TRUE;


Assembler symbols

<V>           Is a width specifier, encoded in the "immh" field. It can have the following values:

              B           when immh = 0001

              H           when immh = 001x

              S           when immh = 01xx

              D           when immh = 1xxx

              It is RESERVED when immh = 0000.

<d>           Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>           Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>           Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

              8B          when immh = 0001, Q = 0

              16B         when immh = 0001, Q = 1

              4H          when immh = 001x, Q = 0

              8H          when immh = 001x, Q = 1

              2S          when immh = 01xx, Q = 0

              4S          when immh = 01xx, Q = 1

              2D          when immh = 1xxx, Q = 1

              See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

              It is RESERVED when immh = 1xxx, Q = 0.

<Vn>          Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<shift>       For the scalar variant: is the left shift amount, in the range 0 to the operand width in bits minus 1,
              encoded in the "immh:immb" field. It can have the following values:

              (UInt(immh:immb)-8)when immh = 0001

              (UInt(immh:immb)-16)when immh = 001x

              (UInt(immh:immb)-32)when immh = 01xx

              (UInt(immh:immb)-64)when immh = 1xxx

              It is RESERVED when immh = 0000.

              For the vector variant: is the left shift amount, in the range 0 to the element width in bits minus 1,
              encoded in the "immh:immb" field. It can have the following values:

              (UInt(immh:immb)-8)when immh = 0001

              (UInt(immh:immb)-16)when immh = 001x

              (UInt(immh:immb)-32)when immh = 01xx

              (UInt(immh:immb)-64)when immh = 1xxx

              See Advanced SIMD modified immediate on page C4-213 when immh = 0000.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand  = V[n];
 bits(datasize) result;
         integer element;
         boolean sat;

         for e = 0 to elements-1
              element = Int(Elem[operand, e, esize], src_unsigned) << shift;
              (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
              if sat then FPSR.QC = '1';

         V[d] = result;


platform: ARM
mnem: UQSHRN
description:
Unsigned saturating shift right narrow (immediate)       (C7.3.329)


Scalar


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 1 1 1 1 1 1 1 0              !=0000     immb      1 0 0 1 0 1              Rn             Rd
        U                         immh                           op


Scalar variant

UQSHRN <Vb><d>, <Va><n>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then ReservedValue();
 if immh<3> == '1' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = esize;
 integer elements = 1;
 integer part = 0;

 integer shift = (2 * esize) - UInt(immh:immb);
 boolean round = (op == '1');
 boolean unsigned = (U == '1');


Vector


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 Q 1 0 1 1 1 1 0              !=0000     immb      1 0 0 1 0 1              Rn             Rd
        U                         immh                           op


Vector variant

UQSHRN{2} <Vd>.<Tb>, <Vn>.<Ta>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then SEE "Advanced SIMD modified immediate";
 if immh<3> == '1' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = 64;
 integer part = UInt(Q);
 integer elements = datasize DIV esize;

 integer shift = (2 * esize) - UInt(immh:immb);
 boolean round = (op == '1');
 boolean unsigned = (U == '1');
       Assembler symbols

       2                 Is the second and upper half specifier. If present it causes the operation to be performed on the upper
                         64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
                         the following values:

                         [absent]    when Q = 0

                         [present]   when Q = 1

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <Tb>              Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                         8B          when immh = 0001, Q = 0

                         16B         when immh = 0001, Q = 1

                         4H          when immh = 001x, Q = 0

                         8H          when immh = 001x, Q = 1

                         2S          when immh = 01xx, Q = 0

                         4S          when immh = 01xx, Q = 1

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                         It is RESERVED when immh = 1xxx, Q = x.

       <Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.

       <Ta>              Is an arrangement specifier, encoded in the "immh" field. It can have the following values:

                         8H          when immh = 0001

                         4S          when immh = 001x

                         2D          when immh = 01xx

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000.

                         It is RESERVED when immh = 1xxx.

       <Vb>              Is the destination width specifier, encoded in the "immh" field. It can have the following values:

                         B           when immh = 0001

                         H           when immh = 001x

                         S           when immh = 01xx

                         It is RESERVED when:

                         .      immh = 0000.

                         .      immh = 1xxx.

       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.

       <Va>              Is the source width specifier, encoded in the "immh" field. It can have the following values:

                         H           when immh = 0001

                         S           when immh = 001x

                         D           when immh = 01xx

                         It is RESERVED when:

                         .      immh = 0000.

                         .      immh = 1xxx.

       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <shift>           For the scalar variant: is the right shift amount, in the range 1 to the destination operand width in
                         bits, encoded in the "immh:immb" field. It can have the following values:

                         (16-UInt(immh:immb))when immh = 0001
              (32-UInt(immh:immb))when immh = 001x

              (64-UInt(immh:immb))when immh = 01xx

              It is RESERVED when:

              .      immh = 0000.

              .      immh = 1xxx.

              For the vector variant: is the right shift amount, in the range 1 to the destination element width in
              bits, encoded in the "immh:immb" field. It can have the following values:

              (16-UInt(immh:immb))when immh = 0001

              (32-UInt(immh:immb))when immh = 001x

              (64-UInt(immh:immb))when immh = 01xx

              See Advanced SIMD modified immediate on page C4-213 when immh = 0000.

              It is RESERVED when immh = 1xxx.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(datasize*2) operand = V[n];
 bits(datasize) result;
 integer round_const = if round then (1 << (shift - 1)) else 0;
 integer element;
 boolean sat;

 for e = 0 to elements-1
     element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
     (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
    if sat then FPSR.QC = '1';

 Vpart[d, part] = result;


platform: ARM
mnem: UQSUB
description:
       Unsigned saturating subtract       (C7.3.330)


       Scalar


           31 30 29 28 27 26 25 24 23 22 21 20             16 15 14 13 12 11 10 9                5 4          0
            0 1 1 1 1 1 1 0 size 1                   Rm         0 0 1 0 1 1               Rn             Rd
                  U


       Scalar variant

       UQSUB <V><d>, <V><n>, <V><m>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);
         integer m = UInt(Rm);
         integer esize = 8 << UInt(size);
         integer datasize = esize;
         integer elements = 1;
         boolean unsigned = (U == '1');


       Vector


           31 30 29 28 27 26 25 24 23 22 21 20             16 15 14 13 12 11 10 9                5 4          0
            0 Q 1 0 1 1 1 0 size 1                   Rm         0 0 1 0 1 1               Rn             Rd
                  U


       Vector variant

       UQSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);
         integer m = UInt(Rm);
         if size:Q == '110' then ReservedValue();
         integer esize = 8 << UInt(size);
         integer datasize = if Q == '1' then 128 else 64;
         integer elements = datasize DIV esize;
         boolean unsigned = (U == '1');


       Assembler symbols

       <V>               Is a width specifier, encoded in the "size" field. It can have the following values:

                         B           when size = 00

                         H           when size = 01

                         S           when size = 10

                         D           when size = 11

       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.

       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <m>               Is the number of the second SIMD&FP source register, encoded in the "Rm" field.
<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>           Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              2D          when size = 11, Q = 1

              It is RESERVED when size = 11, Q = 0.

<Vn>          Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>          Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand1 = V[n];
 bits(datasize) operand2 = V[m];
 bits(datasize) result;
 integer element1;
 integer element2;
 integer diff;
 boolean sat;

 for e = 0 to elements-1
     element1 = Int(Elem[operand1, e, esize], unsigned);
     element2 = Int(Elem[operand2, e, esize], unsigned);
     diff = element1 - element2;
     (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
    if sat then FPSR.QC = '1';

 V[d] = result;


platform: ARM
mnem: UQXTN
description:
       Unsigned saturating extract narrow       (C7.3.331)


       Scalar


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                    5 4             0
            0 1 1 1 1 1 1 0 size 1 0 0 0 0 1 0 1 0 0 1 0                                   Rn               Rd
                  U


       Scalar variant

       UQXTN <Vb><d>, <Va><n>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if size == '11' then ReservedValue();
         integer esize = 8 << UInt(size);
         integer datasize = esize;
         integer part = 0;
         integer elements = 1;

         boolean unsigned = (U == '1');


       Vector


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                    5 4             0
            0 Q 1 0 1 1 1 0 size 1 0 0 0 0 1 0 1 0 0 1 0                                   Rn               Rd
                  U


       Vector variant

       UQXTN{2} <Vd>.<Tb>, <Vn>.<Ta>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if size == '11' then ReservedValue();
         integer esize = 8 << UInt(size);
         integer datasize = 64;
         integer part = UInt(Q);
         integer elements = datasize DIV esize;

         boolean unsigned = (U == '1');


       Assembler symbols

       2                 Is the second and upper half specifier. If present it causes the operation to be performed on the upper
                         64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
                         the following values:

                         [absent]    when Q = 0

                         [present]   when Q = 1

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.
<Tb>          Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              It is RESERVED when size = 11, Q = x.

<Vn>          Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ta>          Is an arrangement specifier, encoded in the "size" field. It can have the following values:

              8H          when size = 00

              4S          when size = 01

              2D          when size = 10

              It is RESERVED when size = 11.

<Vb>          Is the destination width specifier, encoded in the "size" field. It can have the following values:

              B           when size = 00

              H           when size = 01

              S           when size = 10

              It is RESERVED when size = 11.

<d>           Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Va>          Is the source width specifier, encoded in the "size" field. It can have the following values:

              H           when size = 00

              S           when size = 01

              D           when size = 10

              It is RESERVED when size = 11.

<n>           Is the number of the SIMD&FP source register, encoded in the "Rn" field.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(2*datasize) operand = V[n];
 bits(datasize) result;
 bits(2*esize) element;
 boolean sat;

 for e = 0 to elements-1
     element = Elem[operand, e, 2*esize];
     (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
     if sat then FPSR.QC = '1';

 Vpart[d, part] = result;


platform: ARM
mnem: URECPE
description:
Unsigned reciprocal estimate       (C7.3.332)




    31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                  5 4            0
     0 Q 0 0 1 1 1 0 1 sz 1 0 0 0 0 1 1 1 0 0 1 0                                Rn              Rd




Vector variant

URECPE <Vd>.<T>, <Vn>.<T>


Decode for this encoding

  integer d = UInt(Rd);
  integer n = UInt(Rn);

  if sz == '1' then ReservedValue();
  integer esize = 32;
  integer datasize = if Q == '1' then 128 else 64;
  integer elements = datasize DIV esize;


Assembler symbols

<Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>               Is an arrangement specifier, encoded in the "sz:Q" field. It can have the following values:

                  2S          when sz = 0, Q = 0

                  4S          when sz = 0, Q = 1

                  It is RESERVED when sz = 1, Q = x.

<Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.


Operation

  CheckFPAdvSIMDEnabled64();
  bits(datasize) operand = V[n];
  bits(datasize) result;
  bits(32) element;

  for e = 0 to elements-1
       element = Elem[operand, e, 32];
       Elem[result, e, 32] = UnsignedRecipEstimate(element);

  V[d] = result;


platform: ARM
mnem: URHADD
description:
Unsigned rounding halving add       (C7.3.333)




  31 30 29 28 27 26 25 24 23 22 21 20          16 15 14 13 12 11 10 9                 5 4           0
  0 Q 1 0 1 1 1 0 size 1                 Rm         0 0 0 1 0 1               Rn              Rd
        U


Three registers of the same type variant

URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);
 if size == '11' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;

 boolean unsigned = (U == '1');


Assembler symbols

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>           Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              It is RESERVED when size = 11, Q = x.

<Vn>          Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>          Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand1 = V[n];
 bits(datasize) operand2 = V[m];
 bits(datasize) result;
 integer element1;
 integer element2;

 for e = 0 to elements-1
     element1 = Int(Elem[operand1, e, esize], unsigned);
     element2 = Int(Elem[operand2, e, esize], unsigned);
     Elem[result, e, esize] = (element1 + element2 + 1)<esize:1>;

 V[d] = result;


platform: ARM
mnem: URSHL
description:
       Unsigned rounding shift left (register)       (C7.3.334)


       Scalar


           31 30 29 28 27 26 25 24 23 22 21 20             16 15 14 13 12 11 10 9                5 4          0
            0 1 1 1 1 1 1 0 size 1                  Rm          0 1 0 1 0 1               Rn             Rd
                  U                                                       R S


       Scalar variant

       URSHL <V><d>, <V><n>, <V><m>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);
         integer m = UInt(Rm);
         integer esize = 8 << UInt(size);
         integer datasize = esize;
         integer elements = 1;
         boolean unsigned = (U == '1');
         boolean rounding = (R == '1');
         boolean saturating = (S == '1');
         if S == '0' && size != '11' then ReservedValue();


       Vector


           31 30 29 28 27 26 25 24 23 22 21 20             16 15 14 13 12 11 10 9                5 4          0
            0 Q 1 0 1 1 1 0 size 1                  Rm          0 1 0 1 0 1               Rn             Rd
                  U                                                       R S


       Vector variant

       URSHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);
         integer m = UInt(Rm);
         if size:Q == '110' then ReservedValue();
         integer esize = 8 << UInt(size);
         integer datasize = if Q == '1' then 128 else 64;
         integer elements = datasize DIV esize;
         boolean unsigned = (U == '1');
         boolean rounding = (R == '1');
         boolean saturating = (S == '1');


       Assembler symbols

       <V>               Is a width specifier, encoded in the "size" field. It can have the following values:

                         D           when size = 11

                         It is RESERVED when:

                         .      size = 0x.

                         .      size = 10.

       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.
<n>           Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<m>           Is the number of the second SIMD&FP source register, encoded in the "Rm" field.

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>           Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              2D          when size = 11, Q = 1

              It is RESERVED when size = 11, Q = 0.

<Vn>          Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>          Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand1 = V[n];
 bits(datasize) operand2 = V[m];
 bits(datasize) result;

 integer round_const = 0;
 integer shift;
 integer element;
 boolean sat;

 for e = 0 to elements-1
     shift = SInt(Elem[operand2, e, esize]<7:0>);
     if rounding then
         round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift
     element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
     if saturating then
         (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
         if sat then FPSR.QC = '1';
     else
         Elem[result, e, esize] = element<esize-1:0>;

 V[d] = result;


platform: ARM
mnem: URSHR
description:
       Unsigned rounding shift right (immediate)       (C7.3.335)


       Scalar


           31 30 29 28 27 26 25 24 23 22          19 18    16 15 14 13 12 11 10 9               5 4          0
            0 1 1 1 1 1 1 1 0              !=0000     immb      0 0 1 0 0 1             Rn             Rd
                  U                         immh                    o1 o0


       Scalar variant

       URSHR <V><d>, <V><n>, #<shift>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if immh<3> != '1' then ReservedValue();
         integer esize = 8 << 3;
         integer datasize = esize;
         integer elements = 1;

         integer shift = (esize * 2) - UInt(immh:immb);
         boolean unsigned = (U == '1');
         boolean round = (o1 == '1');
         boolean accumulate = (o0 == '1');


       Vector


           31 30 29 28 27 26 25 24 23 22          19 18    16 15 14 13 12 11 10 9               5 4          0
            0 Q 1 0 1 1 1 1 0              !=0000     immb      0 0 1 0 0 1             Rn             Rd
                  U                         immh                    o1 o0


       Vector variant

       URSHR <Vd>.<T>, <Vn>.<T>, #<shift>


       Decode for this encoding

         integer d = UInt(Rd);
         integer n = UInt(Rn);

         if immh == '0000' then SEE "Advanced SIMD modified immediate";
         if immh<3>:Q == '10' then ReservedValue();
         integer esize = 8 << HighestSetBit(immh);
         integer datasize = if Q == '1' then 128 else 64;
         integer elements = datasize DIV esize;

         integer shift = (esize * 2) - UInt(immh:immb);
         boolean unsigned = (U == '1');
         boolean round = (o1 == '1');
         boolean accumulate = (o0 == '1');


       Assembler symbols

       <V>               Is a width specifier, encoded in the "immh" field. It can have the following values:

                         D           when immh = 1xxx

                         It is RESERVED when immh = 0xxx.
<d>           Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>           Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>           Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

              8B           when immh = 0001, Q = 0

              16B          when immh = 0001, Q = 1

              4H           when immh = 001x, Q = 0

              8H           when immh = 001x, Q = 1

              2S           when immh = 01xx, Q = 0

              4S           when immh = 01xx, Q = 1

              2D           when immh = 1xxx, Q = 1

              See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

              It is RESERVED when immh = 1xxx, Q = 0.

<Vn>          Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<shift>       For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in the "immh:immb"
              field. It can have the following values:

              (128-UInt(immh:immb))when immh = 1xxx

              It is RESERVED when immh = 0xxx.

              For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded
              in the "immh:immb" field. It can have the following values:

              (16-UInt(immh:immb))when immh = 0001

              (32-UInt(immh:immb))when immh = 001x

              (64-UInt(immh:immb))when immh = 01xx

              (128-UInt(immh:immb))when immh = 1xxx

              See Advanced SIMD modified immediate on page C4-213 when immh = 0000.


Operation for all encodings

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand   = V[n];
 bits(datasize) operand2;
 bits(datasize) result;
 integer round_const = if round then (1 << (shift - 1)) else 0;
 integer element;

 operand2 = if accumulate then V[d] else Zeros();
 for e = 0 to elements-1
     element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
     Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

 V[d] = result;


platform: ARM
mnem: URSQRTE
description:
Unsigned reciprocal square root estimate       (C7.3.336)




    31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                  5 4            0
     0 Q 1 0 1 1 1 0 1 sz 1 0 0 0 0 1 1 1 0 0 1 0                                Rn              Rd




Vector variant

URSQRTE <Vd>.<T>, <Vn>.<T>


Decode for this encoding

  integer d = UInt(Rd);
  integer n = UInt(Rn);

  if sz == '1' then ReservedValue();
  integer esize = 32;
  integer datasize = if Q == '1' then 128 else 64;
  integer elements = datasize DIV esize;


Assembler symbols

<Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>               Is an arrangement specifier, encoded in the "sz:Q" field. It can have the following values:

                  2S          when sz = 0, Q = 0

                  4S          when sz = 0, Q = 1

                  It is RESERVED when sz = 1, Q = x.

<Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.


Operation

  CheckFPAdvSIMDEnabled64();
  bits(datasize) operand = V[n];
  bits(datasize) result;
  bits(32) element;

  for e = 0 to elements-1
       element = Elem[operand, e, 32];
       Elem[result, e, 32] = UnsignedRSqrtEstimate(element);

  V[d] = result;


platform: ARM
mnem: URSRA
description:
Unsigned rounding shift right and accumulate (immediate)       (C7.3.337)


Scalar


  31 30 29 28 27 26 25 24 23 22        19 18    16 15 14 13 12 11 10 9                5 4          0
  0 1 1 1 1 1 1 1 0             !=0000     immb      0 0 1 1 0 1              Rn             Rd
        U                        immh                    o1 o0


Scalar variant

URSRA <V><d>, <V><n>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh<3> != '1' then ReservedValue();
 integer esize = 8 << 3;
 integer datasize = esize;
 integer elements = 1;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Vector


  31 30 29 28 27 26 25 24 23 22        19 18    16 15 14 13 12 11 10 9                5 4          0
  0 Q 1 0 1 1 1 1 0             !=0000     immb      0 0 1 1 0 1              Rn             Rd
        U                        immh                    o1 o0


Vector variant

URSRA <Vd>.<T>, <Vn>.<T>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then SEE "Advanced SIMD modified immediate";
 if immh<3>:Q == '10' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Assembler symbols

<V>           Is a width specifier, encoded in the "immh" field. It can have the following values:

              D           when immh = 1xxx

              It is RESERVED when immh = 0xxx.
       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.

       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <T>               Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                         8B           when immh = 0001, Q = 0

                         16B          when immh = 0001, Q = 1

                         4H           when immh = 001x, Q = 0

                         8H           when immh = 001x, Q = 1

                         2S           when immh = 01xx, Q = 0

                         4S           when immh = 01xx, Q = 1

                         2D           when immh = 1xxx, Q = 1

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                         It is RESERVED when immh = 1xxx, Q = 0.

       <Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.

       <shift>           For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in the "immh:immb"
                         field. It can have the following values:

                         (128-UInt(immh:immb))when immh = 1xxx

                         It is RESERVED when immh = 0xxx.

                         For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded
                         in the "immh:immb" field. It can have the following values:

                         (16-UInt(immh:immb))when immh = 0001

                         (32-UInt(immh:immb))when immh = 001x

                         (64-UInt(immh:immb))when immh = 01xx

                         (128-UInt(immh:immb))when immh = 1xxx

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000.


       Operation for all encodings

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand      = V[n];
         bits(datasize) operand2;
         bits(datasize) result;
         integer round_const = if round then (1 << (shift - 1)) else 0;
         integer element;

         operand2 = if accumulate then V[d] else Zeros();
         for e = 0 to elements-1
              element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
              Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USHL
description:
Unsigned shift left (register)       (C7.3.338)


Scalar


  31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9                5 4          0
  0 1 1 1 1 1 1 0 size 1                   Rm         0 1 0 0 0 1               Rn             Rd
        U                                                       R S


Scalar variant

USHL <V><d>, <V><n>, <V><m>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);
 integer esize = 8 << UInt(size);
 integer datasize = esize;
 integer elements = 1;
 boolean unsigned = (U == '1');
 boolean rounding = (R == '1');
 boolean saturating = (S == '1');
 if S == '0' && size != '11' then ReservedValue();


Vector


  31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9                5 4          0
  0 Q 1 0 1 1 1 0 size 1                   Rm         0 1 0 0 0 1               Rn             Rd
        U                                                       R S


Vector variant

USHL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);
 if size:Q == '110' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;
 boolean unsigned = (U == '1');
 boolean rounding = (R == '1');
 boolean saturating = (S == '1');


Assembler symbols

<V>            Is a width specifier, encoded in the "size" field. It can have the following values:

               D             when size = 11

               It is RESERVED when:

               .       size = 0x.

               .       size = 10.

<d>            Is the number of the SIMD&FP destination register, in the "Rd" field.
       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <m>               Is the number of the second SIMD&FP source register, encoded in the "Rm" field.

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <T>               Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

                         8B          when size = 00, Q = 0

                         16B         when size = 00, Q = 1

                         4H          when size = 01, Q = 0

                         8H          when size = 01, Q = 1

                         2S          when size = 10, Q = 0

                         4S          when size = 10, Q = 1

                         2D          when size = 11, Q = 1

                         It is RESERVED when size = 11, Q = 0.

       <Vn>              Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

       <Vm>              Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


       Operation for all encodings

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand1 = V[n];
         bits(datasize) operand2 = V[m];
         bits(datasize) result;

         integer round_const = 0;
         integer shift;
         integer element;
         boolean sat;

         for e = 0 to elements-1
              shift = SInt(Elem[operand2, e, esize]<7:0>);
              if rounding then
                   round_const = 1 << (-shift - 1); // 0 for left shift, 2^(n-1) for right shift
              element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
              if saturating then
                   (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
                   if sat then FPSR.QC = '1';
              else
                   Elem[result, e, esize] = element<esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USHLL
description:
Unsigned shift left long (immediate)       (C7.3.339)

This instruction is used by the alias UXTL. See the Alias conditions table for details of when each alias is preferred.




  31 30 29 28 27 26 25 24 23 22           19 18    16 15 14 13 12 11 10 9                5 4             0
  0 Q 1 0 1 1 1 1 0                !=0000     immb      1 0 1 0 0 1               Rn               Rd
         U                          immh


Vector variant

USHLL{2} <Vd>.<Ta>, <Vn>.<Tb>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then SEE "Advanced SIMD modified immediate";
 if immh<3> == '1' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = 64;
 integer part = UInt(Q);
 integer elements = datasize DIV esize;

 integer shift = UInt(immh:immb) - esize;
 boolean unsigned = (U == '1');


Alias conditions


                      Alias                   is preferred when

                      UXTL                     immb == '000' && BitCount(immh) == 1



Assembler symbols

2               Is the second and upper half specifier. If present it causes the operation to be performed on the upper
                64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
                the following values:

                [absent]     when Q = 0

                [present]    when Q = 1

<Vd>            Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>            Is an arrangement specifier, encoded in the "immh" field. It can have the following values:

                8H           when immh = 0001

                4S           when immh = 001x

                2D           when immh = 01xx

                See Advanced SIMD modified immediate on page C4-213 when immh = 0000.

                It is RESERVED when immh = 1xxx.

<Vn>            Is the name of the SIMD&FP source register, encoded in the "Rn" field.
       <Tb>              Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                         8B           when immh = 0001, Q = 0

                         16B          when immh = 0001, Q = 1

                         4H           when immh = 001x, Q = 0

                         8H           when immh = 001x, Q = 1

                         2S           when immh = 01xx, Q = 0

                         4S           when immh = 01xx, Q = 1

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                         It is RESERVED when immh = 1xxx, Q = x.

       <shift>           Is the left shift amount, in the range 0 to the source element width in bits minus 1, encoded in the
                         "immh:immb" field. It can have the following values:

                         (UInt(immh:immb)-8)when immh = 0001

                         (UInt(immh:immb)-16)when immh = 001x

                         (UInt(immh:immb)-32)when immh = 01xx

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000.

                         It is RESERVED when immh = 1xxx.


       Operation

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand = Vpart[n, part];
         bits(datasize*2) result;
         integer element;

         for e = 0 to elements-1
              element = Int(Elem[operand, e, esize], unsigned) << shift;
              Elem[result, e, 2*esize] = element<2*esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USHR
description:
Unsigned shift right (immediate)       (C7.3.340)


Scalar


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 1 1 1 1 1 1 1 0              !=0000     immb      0 0 0 0 0 1              Rn             Rd
        U                         immh                    o1 o0


Scalar variant

USHR <V><d>, <V><n>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh<3> != '1' then ReservedValue();
 integer esize = 8 << 3;
 integer datasize = esize;
 integer elements = 1;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Vector


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 Q 1 0 1 1 1 1 0              !=0000     immb      0 0 0 0 0 1              Rn             Rd
        U                         immh                    o1 o0


Vector variant

USHR <Vd>.<T>, <Vn>.<T>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then SEE "Advanced SIMD modified immediate";
 if immh<3>:Q == '10' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Assembler symbols

<V>            Is a width specifier, encoded in the "immh" field. It can have the following values:

               D           when immh = 1xxx

               It is RESERVED when immh = 0xxx.
       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.

       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <T>               Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                         8B           when immh = 0001, Q = 0

                         16B          when immh = 0001, Q = 1

                         4H           when immh = 001x, Q = 0

                         8H           when immh = 001x, Q = 1

                         2S           when immh = 01xx, Q = 0

                         4S           when immh = 01xx, Q = 1

                         2D           when immh = 1xxx, Q = 1

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                         It is RESERVED when immh = 1xxx, Q = 0.

       <Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.

       <shift>           For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in the "immh:immb"
                         field. It can have the following values:

                         (128-UInt(immh:immb))when immh = 1xxx

                         It is RESERVED when immh = 0xxx.

                         For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded
                         in the "immh:immb" field. It can have the following values:

                         (16-UInt(immh:immb))when immh = 0001

                         (32-UInt(immh:immb))when immh = 001x

                         (64-UInt(immh:immb))when immh = 01xx

                         (128-UInt(immh:immb))when immh = 1xxx

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000.


       Operation for all encodings

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand      = V[n];
         bits(datasize) operand2;
         bits(datasize) result;
         integer round_const = if round then (1 << (shift - 1)) else 0;
         integer element;

         operand2 = if accumulate then V[d] else Zeros();
         for e = 0 to elements-1
              element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
              Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USQADD
description:
Unsigned saturating accumulate of signed value       (C7.3.341)


Scalar


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                 5 4          0
  0 1 1 1 1 1 1 0 size 1 0 0 0 0 0 0 0 1 1 1 0                                 Rn             Rd
        U


Scalar variant

USQADD <V><d>, <V><n>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 integer esize = 8 << UInt(size);
 integer datasize = esize;
 integer elements = 1;

 boolean unsigned = (U == '1');


Vector


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                 5 4          0
  0 Q 1 0 1 1 1 0 size 1 0 0 0 0 0 0 0 1 1 1 0                                 Rn             Rd
        U


Vector variant

USQADD <Vd>.<T>, <Vn>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if size:Q == '110' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;

 boolean unsigned = (U == '1');


Assembler symbols

<V>           Is a width specifier, encoded in the "size" field. It can have the following values:

              B           when size = 00

              H           when size = 01

              S           when size = 10

              D           when size = 11

<d>           Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>           Is the number of the SIMD&FP source register, encoded in the "Rn" field.
       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <T>               Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

                         8B          when size = 00, Q = 0

                         16B         when size = 00, Q = 1

                         4H          when size = 01, Q = 0

                         8H          when size = 01, Q = 1

                         2S          when size = 10, Q = 0

                         4S          when size = 10, Q = 1

                         2D          when size = 11, Q = 1

                         It is RESERVED when size = 11, Q = 0.

       <Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.


       Operation for all encodings

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand = V[n];
         bits(datasize) result;

         bits(datasize) operand2 = V[d];
         integer op1;
         integer op2;
         boolean sat;

         for e = 0 to elements-1
              op1 = Int(Elem[operand, e, esize], !unsigned);
              op2 = Int(Elem[operand2, e, esize], unsigned);
              (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
              if sat then FPSR.QC = '1';
         V[d] = result;


platform: ARM
mnem: USRA
description:
Unsigned shift right and accumulate (immediate)       (C7.3.342)


Scalar


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 1 1 1 1 1 1 1 0              !=0000     immb      0 0 0 1 0 1              Rn             Rd
        U                         immh                    o1 o0


Scalar variant

USRA <V><d>, <V><n>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh<3> != '1' then ReservedValue();
 integer esize = 8 << 3;
 integer datasize = esize;
 integer elements = 1;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Vector


  31 30 29 28 27 26 25 24 23 22         19 18    16 15 14 13 12 11 10 9                5 4          0
  0 Q 1 0 1 1 1 1 0              !=0000     immb      0 0 0 1 0 1              Rn             Rd
        U                         immh                    o1 o0


Vector variant

USRA <Vd>.<T>, <Vn>.<T>, #<shift>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if immh == '0000' then SEE "Advanced SIMD modified immediate";
 if immh<3>:Q == '10' then ReservedValue();
 integer esize = 8 << HighestSetBit(immh);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;

 integer shift = (esize * 2) - UInt(immh:immb);
 boolean unsigned = (U == '1');
 boolean round = (o1 == '1');
 boolean accumulate = (o0 == '1');


Assembler symbols

<V>            Is a width specifier, encoded in the "immh" field. It can have the following values:

               D           when immh = 1xxx

               It is RESERVED when immh = 0xxx.
       <d>               Is the number of the SIMD&FP destination register, in the "Rd" field.

       <n>               Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

       <Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

       <T>               Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                         8B           when immh = 0001, Q = 0

                         16B          when immh = 0001, Q = 1

                         4H           when immh = 001x, Q = 0

                         8H           when immh = 001x, Q = 1

                         2S           when immh = 01xx, Q = 0

                         4S           when immh = 01xx, Q = 1

                         2D           when immh = 1xxx, Q = 1

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                         It is RESERVED when immh = 1xxx, Q = 0.

       <Vn>              Is the name of the SIMD&FP source register, encoded in the "Rn" field.

       <shift>           For the scalar variant: is the right shift amount, in the range 1 to 64, encoded in the "immh:immb"
                         field. It can have the following values:

                         (128-UInt(immh:immb))when immh = 1xxx

                         It is RESERVED when immh = 0xxx.

                         For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded
                         in the "immh:immb" field. It can have the following values:

                         (16-UInt(immh:immb))when immh = 0001

                         (32-UInt(immh:immb))when immh = 001x

                         (64-UInt(immh:immb))when immh = 01xx

                         (128-UInt(immh:immb))when immh = 1xxx

                         See Advanced SIMD modified immediate on page C4-213 when immh = 0000.


       Operation for all encodings

         CheckFPAdvSIMDEnabled64();
         bits(datasize) operand      = V[n];
         bits(datasize) operand2;
         bits(datasize) result;
         integer round_const = if round then (1 << (shift - 1)) else 0;
         integer element;

         operand2 = if accumulate then V[d] else Zeros();
         for e = 0 to elements-1
              element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
              Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USUBL
description:
Unsigned subtract long       (C7.3.343)




  31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9                5 4             0
  0 Q 1 0 1 1 1 0 size 1                  Rm          0 0 1 0 0 0               Rn               Rd
        U                                                   o1


Three registers, not all the same type variant

USUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);

 if size == '11' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = 64;
 integer part = UInt(Q);
 integer elements = datasize DIV esize;

 boolean sub_op = (o1 == '1');
 boolean unsigned = (U == '1');


Assembler symbols

2             Is the second and upper half specifier. If present it causes the operation to be performed on the upper
              64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
              the following values:

              [absent]    when Q = 0

              [present]   when Q = 1

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>          Is an arrangement specifier, encoded in the "size" field. It can have the following values:

              8H          when size = 00

              4S          when size = 01

              2D          when size = 10

              It is RESERVED when size = 11.

<Vn>          Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>          Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              It is RESERVED when size = 11, Q = x.
       <Vm>              Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


       Operation

         CheckFPAdvSIMDEnabled64();
         bits(datasize)      operand1 = Vpart[n, part];
         bits(datasize)      operand2 = Vpart[m, part];
         bits(2*datasize) result;
         integer element1;
         integer element2;
         integer sum;

         for e = 0 to elements-1
              element1 = Int(Elem[operand1, e, esize], unsigned);
              element2 = Int(Elem[operand2, e, esize], unsigned);
              if sub_op then
                   sum = element1 - element2;
              else
                   sum = element1 + element2;
              Elem[result, e, 2*esize] = sum<2*esize-1:0>;

         V[d] = result;


platform: ARM
mnem: USUBW
description:
Unsigned subtract wide       (C7.3.344)




  31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9                5 4             0
  0 Q 1 0 1 1 1 0 size 1                  Rm          0 0 1 1 0 0               Rn               Rd
        U                                                   o1


Three registers, not all the same type variant

USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);

 if size == '11' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = 64;
 integer part = UInt(Q);
 integer elements = datasize DIV esize;

 boolean sub_op = (o1 == '1');
 boolean unsigned = (U == '1');


Assembler symbols

2             Is the second and upper half specifier. If present it causes the operation to be performed on the upper
              64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
              the following values:

              [absent]    when Q = 0

              [present]   when Q = 1

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>          Is an arrangement specifier, encoded in the "size" field. It can have the following values:

              8H          when size = 00

              4S          when size = 01

              2D          when size = 10

              It is RESERVED when size = 11.

<Vn>          Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>          Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

<Tb>          Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1
                         It is RESERVED when size = 11, Q = x.


       Operation

         CheckFPAdvSIMDEnabled64();
         bits(2*datasize) operand1 = V[n];
         bits(datasize)      operand2 = Vpart[m, part];
         bits(2*datasize) result;
         integer element1;
         integer element2;
         integer sum;

         for e = 0 to elements-1
              element1 = Int(Elem[operand1, e, 2*esize], unsigned);
              element2 = Int(Elem[operand2, e, esize], unsigned);
              if sub_op then
                   sum = element1 - element2;
              else
                   sum = element1 + element2;
              Elem[result, e, 2*esize] = sum<2*esize-1:0>;

         V[d] = result;


platform: ARM
mnem: UXTL
description:
Unsigned extend long       (C7.3.345)

This instruction is an alias of the USHLL, USHLL2 instruction. This means that:

.      The encodings in this description are named to match the encodings of USHLL, USHLL2.

.      The description of USHLL, USHLL2 gives the operational pseudocode for this instruction.




  31 30 29 28 27 26 25 24 23 22           19 18    16 15 14 13 12 11 10 9                5 4             0
   0 Q 1 0 1 1 1 1 0               !=0000     0 0 0 1 0 1 0 0 1                   Rn               Rd
         U                          immh      immb


Vector variant

UXTL{2} <Vd>.<Ta>, <Vn>.<Tb>

is equivalent to

USHLL{2}   <Vd>.<Ta>, <Vn>.<Tb>, #0

and is the preferred disassembly when BitCount(immh) == 1.


Assembler symbols

2               Is the second and upper half specifier. If present it causes the operation to be performed on the upper
                64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
                the following values:

                [absent]     when Q = 0

                [present]    when Q = 1

<Vd>            Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>            Is an arrangement specifier, encoded in the "immh" field. It can have the following values:

                8H           when immh = 0001

                4S           when immh = 001x

                2D           when immh = 01xx

                See Advanced SIMD modified immediate on page C4-213 when immh = 0000.

                It is RESERVED when immh = 1xxx.

<Vn>            Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Tb>            Is an arrangement specifier, encoded in the "immh:Q" field. It can have the following values:

                8B           when immh = 0001, Q = 0

                16B          when immh = 0001, Q = 1

                4H           when immh = 001x, Q = 0

                8H           when immh = 001x, Q = 1

                2S           when immh = 01xx, Q = 0

                4S           when immh = 01xx, Q = 1

                See Advanced SIMD modified immediate on page C4-213 when immh = 0000, Q = x.

                It is RESERVED when immh = 1xxx, Q = x.
       Operation

       The description of USHLL, USHLL2 gives the operational pseudocode for this instruction.


platform: ARM
mnem: UZP1
description:
Unzip vectors (primary)       (C7.3.346)




  31 30 29 28 27 26 25 24 23 22 21 20           16 15 14 13 12 11 10 9                 5 4           0
  0 Q 0 0 1 1 1 0 size 0                  Rm         0 0 0 1 1 0               Rn              Rd
                                                       op


Advanced SIMD variant

UZP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);

 if size:Q == '110' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;
 integer part = UInt(op);


Assembler symbols

<Vd>           Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>            Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

               8B          when size = 00, Q = 0

               16B         when size = 00, Q = 1

               4H          when size = 01, Q = 0

               8H          when size = 01, Q = 1

               2S          when size = 10, Q = 0

               4S          when size = 10, Q = 1

               2D          when size = 11, Q = 1

               It is RESERVED when size = 11, Q = 0.

<Vn>           Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>           Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operandl = V[n];
 bits(datasize) operandh = V[m];
 bits(datasize) result;
 integer e;

 bits(datasize*2) zipped = operandh:operandl;
 for e = 0 to elements-1
     Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];

 V[d] = result;


platform: ARM
mnem: UZP2
description:
Unzip vectors (secondary)       (C7.3.347)




    31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9               5 4             0
     0 Q 0 0 1 1 1 0 size 0                  Rm         0 1 0 1 1 0               Rn              Rd
                                                          op


Advanced SIMD variant

UZP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

  integer d = UInt(Rd);
  integer n = UInt(Rn);
  integer m = UInt(Rm);

  if size:Q == '110' then ReservedValue();
  integer esize = 8 << UInt(size);
  integer datasize = if Q == '1' then 128 else 64;
  integer elements = datasize DIV esize;
  integer part = UInt(op);


Assembler symbols

<Vd>              Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>               Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

                  8B          when size = 00, Q = 0

                  16B         when size = 00, Q = 1

                  4H          when size = 01, Q = 0

                  8H          when size = 01, Q = 1

                  2S          when size = 10, Q = 0

                  4S          when size = 10, Q = 1

                  2D          when size = 11, Q = 1

                  It is RESERVED when size = 11, Q = 0.

<Vn>              Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>              Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation

  CheckFPAdvSIMDEnabled64();
  bits(datasize) operandl = V[n];
  bits(datasize) operandh = V[m];
  bits(datasize) result;
  integer e;

  bits(datasize*2) zipped = operandh:operandl;
  for e = 0 to elements-1
       Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];

  V[d] = result;


platform: ARM
mnem: XTN
description:
Extract narrow       (C7.3.348)




  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9                  5 4             0
  0 Q 0 0 1 1 1 0 size 1 0 0 0 0 1 0 0 1 0 1 0                                  Rn               Rd




Vector variant

XTN{2} <Vd>.<Tb>, <Vn>.<Ta>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);

 if size == '11' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = 64;
 integer part = UInt(Q);
 integer elements = datasize DIV esize;


Assembler symbols

2             Is the second and upper half specifier. If present it causes the operation to be performed on the upper
              64 bits of the registers holding the narrower elements, and is encoded in the "Q" field. It can have
              the following values:

              [absent]    when Q = 0

              [present]   when Q = 1

<Vd>          Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Tb>          Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

              8B          when size = 00, Q = 0

              16B         when size = 00, Q = 1

              4H          when size = 01, Q = 0

              8H          when size = 01, Q = 1

              2S          when size = 10, Q = 0

              4S          when size = 10, Q = 1

              It is RESERVED when size = 11, Q = x.

<Vn>          Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<Ta>          Is an arrangement specifier, encoded in the "size" field. It can have the following values:

              8H          when size = 00

              4S          when size = 01

              2D          when size = 10

              It is RESERVED when size = 11.
       Operation

         CheckFPAdvSIMDEnabled64();
         bits(2*datasize) operand = V[n];
         bits(datasize) result;
         bits(2*esize) element;

         for e = 0 to elements-1
              element = Elem[operand, e, 2*esize];
              Elem[result, e, esize] = element<esize-1:0>;
         Vpart[d, part] = result;


platform: ARM
mnem: ZIP1
description:
Zip vectors (primary)       (C7.3.349)




  31 30 29 28 27 26 25 24 23 22 21 20            16 15 14 13 12 11 10 9                 5 4           0
  0 Q 0 0 1 1 1 0 size 0                   Rm         0 0 1 1 1 0               Rn              Rd
                                                        op


Advanced SIMD variant

ZIP1 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);

 if size:Q == '110' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;
 integer part = UInt(op);
 integer pairs = elements DIV 2;


Assembler symbols

<Vd>            Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>             Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

                8B          when size = 00, Q = 0

                16B         when size = 00, Q = 1

                4H          when size = 01, Q = 0

                8H          when size = 01, Q = 1

                2S          when size = 10, Q = 0

                4S          when size = 10, Q = 1

                2D          when size = 11, Q = 1

                It is RESERVED when size = 11, Q = 0.

<Vn>            Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>            Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand1 = V[n];
 bits(datasize) operand2 = V[m];
 bits(datasize) result;

 integer base = part * pairs;
 integer p;

 for p = 0 to pairs-1
     Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
              Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

         V[d] = result;


platform: ARM
mnem: ZIP2
description:
Zip vectors (secondary)       (C7.3.350)




  31 30 29 28 27 26 25 24 23 22 21 20           16 15 14 13 12 11 10 9                 5 4           0
  0 Q 0 0 1 1 1 0 size 0                  Rm         0 1 1 1 1 0               Rn              Rd
                                                       op


Advanced SIMD variant

ZIP2 <Vd>.<T>, <Vn>.<T>, <Vm>.<T>


Decode for this encoding

 integer d = UInt(Rd);
 integer n = UInt(Rn);
 integer m = UInt(Rm);

 if size:Q == '110' then ReservedValue();
 integer esize = 8 << UInt(size);
 integer datasize = if Q == '1' then 128 else 64;
 integer elements = datasize DIV esize;
 integer part = UInt(op);
 integer pairs = elements DIV 2;


Assembler symbols

<Vd>           Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>            Is an arrangement specifier, encoded in the "size:Q" field. It can have the following values:

               8B          when size = 00, Q = 0

               16B         when size = 00, Q = 1

               4H          when size = 01, Q = 0

               8H          when size = 01, Q = 1

               2S          when size = 10, Q = 0

               4S          when size = 10, Q = 1

               2D          when size = 11, Q = 1

               It is RESERVED when size = 11, Q = 0.

<Vn>           Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>           Is the name of the second SIMD&FP source register, encoded in the "Rm" field.


Operation

 CheckFPAdvSIMDEnabled64();
 bits(datasize) operand1 = V[n];
 bits(datasize) operand2 = V[m];
 bits(datasize) result;

 integer base = part * pairs;
 integer p;

 for p = 0 to pairs-1
     Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
              Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];

         V[d] = result;


platform: ARM
mnem: ASRS
description:
Arithmetic Shift Right, setting flags (immediate) shifts a register value right by an immediate number of bits,       (F7.1.16)
shifting in copies of its sign bit, and writes the result to the destination register.

If the destination register is not the PC, this instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination register is the PC:

.      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

.      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32
       state on page G1-3845.

.      The instruction is UNDEFINED in Hyp mode.

.      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.

This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

.      The encodings in this description are named to match the encodings of MOV, MOVS (register).

.      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


A1


  31        28 27 26 25 24 23 22 21 20 19 18 17 16 15              12 11             7 6 5 4 3           0
     !=1111     0 0 0 1 1 0 1 1 (0) (0) (0) (0)               Rd            imm5       1 0 0       Rm
      cond                              S                                              type


MOVS, shift or rotate by value variant

ASRS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

is equivalent to

MOVS{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>

and is always the preferred disassembly.


T2


  15 14 13 12 11 10               6 5       3 2       0
   0 0 0 1 0            imm5            Rn        Rd
              op


T2 variant

ASRS{<q>} {<Rd>,} <Rm>, #<imm>// Outside IT block

is equivalent to

MOVS{<q>} <Rd>, <Rm>, ASR #<imm>

and is the preferred disassembly when !InITBlock().
        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                  12 11           8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0) imm3                             Rd       imm2 1 0           Rm
                                              S                                                  type


        MOVS, shift or rotate by value variant

        ASRS.W {<Rd>,} <Rm>, #<imm>// Outside IT block, and <Rd>, <Rm>, <imm> can be represented in T2

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>

        and is always the preferred disassembly.

        ASRS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, ASR #<imm>

        and is always the preferred disassembly.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
                        deprecates using the PC as the destination register, but if the PC is used, the instruction performs an
                        exception return, that restores PSTATE from SPSR_<current_mode>.

                        For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>            For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
                        used.

                        For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.

        <imm>           For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as
                        <imm> modulo 32.

                        For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as
                        <imm> modulo 32.


        Operation for all encodings

        The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: BFC
description:
        Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the       (F7.1.19)
        register.


        A1


          31        28 27 26 25 24 23 22 21 20             16 15         12 11             7 6 5 4 3 2 1 0
             !=1111     0 1 1 1 1 1 0               msb            Rd               lsb        0 0 1 1 1 1 1
              cond


        A1 variant

        BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>


        Decode for this encoding

         d = UInt(Rd);    msbit = UInt(msb);    lsbit = UInt(lsb);
         if d == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                    12 11          8 7 6 5 4                   0
           1 1 1 1 0 (0) 1 1 0 1 1 0 1 1 1 1 0                      imm3          Rd      imm2 (0)         msb




        T1 variant

        BFC{<c>}{<q>} <Rd>, #<lsb>, #<width>


        Decode for this encoding

         d = UInt(Rd);    msbit = UInt(msb);    lsbit = UInt(imm3:imm2);
         if d == 15 then UNPREDICTABLE;     // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly BFC on page J1-5332.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

        <lsb>           For encoding A1: is the least significant bit to be cleared, in the range 0 to 31, encoded in the "lsb"
                        field.

                        For encoding T1: is the least significant bit that is to be cleared, in the range 0 to 31, encoded in the
                        "imm3:imm2" field.

        <width>         Is the number of bits to be cleared, in the range 1 to 32-<lsb>, encoded in the "msb" field as
                        <lsb>+<width>-1.
Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    if msbit >= lsbit then
        R[d]<msbit:lsbit> = Replicate('0', msbit-lsbit+1);
        // Other bits of R[d] are unchanged
    else
        UNPREDICTABLE;


platform: ARM
mnem: BKPT
description:
Breakpoint causes a Software Breakpoint Instruction exception.       (F7.1.24)

Breakpoint is always unconditional, even when inside an IT block.


A1


  31       28 27 26 25 24 23 22 21 20 19                                    8 7 6 5 4 3              0
     !=1111    0 0 0 1 0 0 1 0                         imm12                   0 1 1 1        imm4
      cond


A1 variant

BKPT{<q>} {#}<imm>


Decode for this encoding

 imm16 = imm12:imm4;
 if cond != '1110' then UNPREDICTABLE;     // BKPT must be encoded with AL condition


T1


  15 14 13 12 11 10 9 8 7                        0
  1 0 1 1 1 1 1 0                   imm8




T1 variant

BKPT{<q>} {#}<imm>


Decode for this encoding

 imm16 = ZeroExtend(imm8, 16);


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly BKPT on page J1-5332.


Assembler symbols

<q>            See Standard assembler syntax fields on page F2-2506. An BKPT instruction must be unconditional.

<imm>          For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
               "imm12:imm4" field. The PE:

               .     Records this value in the Comment field of ESR_ELx.ISS if the Software Breakpoint
                     Instruction exception is taken to an exception level that is using AArch64.

               .     Ignores this value otherwise.

               For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.
               The PE:

               .     Records this value in the Comment field of ESR_ELx.ISS if the Software Breakpoint
                     Instruction exception is taken to an exception level that is using AArch64.

               .     Ignores this value otherwise.
        Operation for all encodings

         EncodingSpecificOperations();
         AArch32.SoftwareBreakpoint(imm16);


platform: ARM
mnem: BLX
description:
Branch with Link calls a subroutine at a PC-relative address.       (F7.1.25)

Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and
changes instruction set from A32 to T32, or from T32 to A32.


A1


  31       28 27 26 25 24 23                                                                         0
    !=1111    1 0 1 1                                        imm24
     cond


A1 variant

BL{<c>}{<q>} <label>


Decode for this encoding

 imm32 = SignExtend(imm24:'00', 32);     targetInstrSet = InstrSet_A32;


A2


  31       28 27 26 25 24 23                                                                         0
  1 1 1 1 1 0 1 H                                            imm24
     cond


A2 variant

BLX{<c>}{<q>} <label>


Decode for this encoding

 imm32 = SignExtend(imm24:H:'0', 32);     targetInstrSet = InstrSet_T32;


T1


  15 14 13 12 11 10 9                             0 15 14 13 12 11 10                                0
  1 1 1 1 0 S                   imm10                1 1 J1 1 J2                   imm11




T1 variant

BL{<c>}{<q>} <label>


Decode for this encoding

 I1 = NOT(J1 EOR S);    I2 = NOT(J2 EOR S);   imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
 targetInstrSet = CurrentInstrSet();
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


T2


  15 14 13 12 11 10 9                             0 15 14 13 12 11 10                                0
  1 1 1 1 0 S                  imm10H                1 1 J1 0 J2                  imm10L             H
        T2 variant

        BLX{<c>}{<q>} <label>


        Decode for this encoding

         if H == '1' then UNDEFINED;
         I1 = NOT(J1 EOR S);   I2 = NOT(J2 EOR S);     imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
         targetInstrSet = InstrSet_A32;
         if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
        UNPREDICTABLE behaviors.


        Assembler symbols

        <c>            For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                       For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <label>        For encoding A1: the label of the instruction that is to be branched to. The assembler calculates the
                       required value of the offset from the PC value of the BL instruction to this label, then selects an
                       encoding that sets imm32 to that offset. Permitted offsets are multiples of 4 in the range 33554432 to 33554428.

                       For encoding A2: the label of the instruction that is to be branched to. The assembler calculates the
                       required value of the offset from the PC value of the BLX instruction to this label, then selects an
                       encoding with imm32 set to that offset. Permitted offsets are even numbers in the range 33554432
                       to 33554430.

                       For encoding T1: the label of the instruction that is to be branched to. The assembler calculates the
                       required value of the offset from the PC value of the BL instruction to this label, then selects an
                       encoding with imm32 set to that offset. Permitted offsets are even numbers in the range 16777216
                       to 16777214.

                       For encoding T2: the label of the instruction that is to be branched to. The assembler calculates the
                       required value of the offset from the Align(PC, 4) value of the BLX instruction to this label, then
                       selects an encoding with imm32 set to that offset. Permitted offsets are multiples of 4 in the range
                       16777216 to 16777212.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             if CurrentInstrSet() == InstrSet_A32 then
                 LR = PC - 4;
             else
                 LR = PC<31:1> : '1';
             if targetInstrSet == InstrSet_A32 then
                 targetAddress = Align(PC,4) + imm32;
             else
                 targetAddress = PC + imm32;
             SelectInstrSet(targetInstrSet);
             BranchWritePC(targetAddress);


platform: ARM
mnem: BX
description:
Branch and Exchange causes a branch to an address and instruction set specified by a register.       (F7.1.27)


A1


  31       28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3                  0
     !=1111   0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 0 1         Rm
      cond


A1 variant

BX{<c>}{<q>} <Rm>


Decode for this encoding

 m = UInt(Rm);


T1


  15 14 13 12 11 10 9 8 7 6           3 2 1 0
  0 1 0 0 0 1 1 1 0              Rm     (0) (0) (0)




T1 variant

BX{<c>}{<q>} <Rm>


Decode for this encoding

 m = UInt(Rm);
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rm>          For encoding A1: is the general-purpose register holding the address to be branched to, encoded in
              the "Rm" field. The SP can be used, but this is deprecated. The PC can be used.

              For encoding T1: is the general-purpose register holding the address to be branched to, encoded in
              the "Rm" field. The SP can be used, but this is deprecated. The PC can be used. Note: If <Rm> is the
              PC at a non word-aligned address, it results in UNPREDICTABLE behavior because the address passed
              to the BXWritePC() pseudocode function has bits<1:0> = '10'.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     BXWritePC(R[m]);


platform: ARM
mnem: BXJ
description:
Branch and Exchange, previously Branch and Exchange Jazelle.       (F7.1.28)

In ARMv8, BXJ behaves as a BX instruction, see BX. This means it causes a branch to an address and instruction set
specified by a register.


A1


  31       28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3                           0
     !=1111     0 0 0 1 0 0 1 0 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 0 0 1 0              Rm
      cond


A1 variant

BXJ{<c>}{<q>} <Rm>


Decode for this encoding

 m = UInt(Rm);
 if m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 1 0 0 1 1 1 1 0 0                    Rn      1 0 (0) 0 (1) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0)




T1 variant

BXJ{<c>}{<q>} <Rm>


Decode for this encoding

 m = UInt(Rm);
 if m == 15 then UNPREDICTABLE;     // ARMv8-A removes UNPREDICTABLE for R13
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rm>            Is the general-purpose register holding the address to be branched to, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     BXWritePC(R[m]);


platform: ARM
mnem: CDP
description:
        Coprocessor Data Processing is a generic coprocessor instruction. The coproc field identifies the target conceptual       (F7.1.30)
        coprocessor. This must be one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the opc1,
        opc2, CRd, CRn, and CRm field values that are valid CDP and CDP2 instructions. Other encodings are UNDEFINED. For more
        information see Conceptual coprocessor support on page E1-2414 and General behavior of System registers on
        page G4-4172.


        A1


          31        28 27 26 25 24 23           20 19         16 15        12 11         8 7      5 4 3          0
             !=1111      1 1 1 0         opc1           CRn          CRd          !=101x      opc2   0      CRm
              cond                                                                coproc


        A1 variant

        CDP{<c>}{<q>} <coproc>, {#}<opc1>, <CRd>, <CRn>, <CRm> {, {#}<opc2>}


        Decode for this encoding

         if coproc == '101x' then SEE "Floating-point instructions";
         cp = UInt(coproc);


        A2


          31        28 27 26 25 24 23           20 19         16 15        12 11         8 7      5 4 3          0
           1 1 1 1 1 1 1 0               opc1           CRn          CRd          !=101x      opc2   0      CRm
              cond                                                                coproc


        A2 variant

        CDP2{<c>}{<q>} <coproc>, {#}<opc1>, <CRd>, <CRn>, <CRm> {, {#}<opc2>}


        Decode for this encoding

         if coproc == '101x' then SEE "Floating-point instructions";
         cp = UInt(coproc);


        T1


          15 14 13 12 11 10 9 8 7                4 3           0 15        12 11         8 7      5 4 3          0
           1 1 1 0 1 1 1 0               opc1           CRn          CRd          !=101x      opc2   0      CRm
                                                                                  coproc


        T1 variant

        CDP{<c>}{<q>} <coproc>, {#}<opc1>, <CRd>, <CRn>, <CRm> {, {#}<opc2>}


        Decode for this encoding

         if coproc == '101x' then SEE "Floating-point instructions";
         cp = UInt(coproc);
T2


  15 14 13 12 11 10 9 8 7             4 3          0 15          12 11        8 7       5 4 3          0
  1 1 1 1 1 1 1 0               opc1         CRn          CRd          !=101x      opc2    0    CRm
                                                                       coproc


T2 variant

CDP2{<c>}{<q>} <coproc>, {#}<opc1>, <CRd>, <CRn>, <CRm> {, {#}<opc2>}


Decode for this encoding

 if coproc == '101x' then SEE "Floating-point instructions";
 cp = UInt(coproc);


Notes for all encodings

Floating-point instructions: Floating-point data-processing instructions on page F5-2599.


Assembler symbols

<c>             For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

<q>             See Standard assembler syntax fields on page F2-2506.

<coproc>        Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                p11, p14, and p15.

<opc1>          Is a coprocessor-specific opcode, in the range 0 to 15, encoded in the "opc1" field.

<CRd>           Is the destination coprocessor register, encoded in the "CRd" field.

<CRn>           Is the coprocessor register that contains the first operand, encoded in the "CRn" field.

<CRm>           Is the coprocessor register that contains the second operand, encoded in the "CRm" field.

<opc2>          Is a coprocessor-specific opcode in the range 0 to 7, defaulting to 0 and encoded in the "opc2" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     Coproc_CheckInstr(cp, ThisInstr());
     Coproc_InternalOperation(cp, ThisInstr());


platform: ARM
mnem: CPS
description:
Change PE State changes one or more of the PSTATE.{A, I, F} interrupt mask bits and, optionally, the PSTATE.M       (F7.1.39)
mode field, without changing any other PSTATE bits.

CPS is treated as NOP if executed in User mode unless it is defined as being CONSTRAINED UNPREDICTABLE elsewhere
in this section.

The PE checks whether the value being written to PSTATE.M is legal. See Illegal changes to PSTATE.M on
page G1-3822.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4                         0
   1 1 1 1 0 0 0 1 0 0 0 0 imod M 0 (0) (0) (0) (0) (0) (0) (0) A I F 0                        mode




CPS variant

Applies when imod = 00 && M = 1.

CPS{<q>} #<mode>// Cannot be conditional


CPSID variant

Applies when imod = 11 && M = 0.

CPSID{<q>} <iflags>// Cannot be conditional


CPSID variant

Applies when imod = 11 && M = 1.

CPSID{<q>} <iflags> , #<mode>// Cannot be conditional


CPSIE variant

Applies when imod = 10 && M = 0.

CPSIE{<q>} <iflags>// Cannot be conditional


CPSIE variant

Applies when imod = 10 && M = 1.

CPSIE{<q>} <iflags> , #<mode>// Cannot be conditional


Decode for all variants of this encoding

 if mode != '00000' && M == '0' then UNPREDICTABLE;
 if (imod<1> == '1' && A:I:F == '000') || (imod<1> == '0' && A:I:F != '000') then UNPREDICTABLE;
 enable = (imod == '10');      disable = (imod == '11');      changemode = (M == '1');
 affectA = (A == '1');      affectI = (I == '1');   affectF = (F == '1');
 if (imod == '00' && M == '0') || imod == '01' then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
   1 0 1 1 0 1 1 0 0 1 1 im (0) A I F
        CPSID variant

        Applies when im = 1.

        CPSID{<q>} <iflags>// Not permitted in IT block


        CPSIE variant

        Applies when im = 0.

        CPSIE{<q>} <iflags>// Not permitted in IT block


        Decode for all variants of this encoding

         if A:I:F == '000' then UNPREDICTABLE;
         enable = (im == '0');   disable = (im == '1');     changemode = FALSE;
         affectA = (A == '1');   affectI = (I == '1');    affectF = (F == '1');
         if InITBlock() then UNPREDICTABLE;


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4                        0
           1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) imod M A I F                mode




        CPS variant

        Applies when imod = 00 && M = 1.

        CPS{<q>} #<mode>// Not permitted in IT block


        CPSID variant

        Applies when imod = 11 && M = 0.

        CPSID.W <iflags>// Not permitted in IT block


        CPSID variant

        Applies when imod = 11 && M = 1.

        CPSID{<q>} <iflags>, #<mode>// Not permitted in IT block


        CPSIE variant

        Applies when imod = 10 && M = 0.

        CPSIE.W <iflags>// Not permitted in IT block


        CPSIE variant

        Applies when imod = 10 && M = 1.

        CPSIE{<q>} <iflags>, #<mode>// Not permitted in IT block


        Decode for all variants of this encoding

         if imod == '00' && M == '0' then SEE "Hint instructions";
         if mode != '00000' && M == '0' then UNPREDICTABLE;
         if (imod<1> == '1' && A:I:F == '000') || (imod<1> == '0' && A:I:F != '000') then UNPREDICTABLE;
         enable = (imod == '10');    disable = (imod == '11');    changemode = (M == '1');
         affectA = (A == '1');   affectI = (I == '1');    affectF = (F == '1');
         if imod == '01' || InITBlock() then UNPREDICTABLE;
Notes for all encodings

Hint instructions: In encoding T2, if the imod field is 00 and the M bit is 0, a hint instruction is encoded. To determine
which hint instruction, see Change PE State, and hints on page F3-2534.

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly CPS (T32) on page J1-5378 and CPS
(A32) on page J1-5377.


Assembler symbols

<q>             See Standard assembler syntax fields on page F2-2506.

<iflags>        Is a sequence of one or more of the following, specifying which interrupt mask bits are affected:

                a           Sets the A bit in the instruction, causing the specified effect on PSTATE.A, the
                            asynchronous abort mask bit.

                i           Sets the I bit in the instruction, causing the specified effect on PSTATE.I, the IRQ
                            interrupt mask bit.

                f           Sets the F bit in the instruction, causing the specified effect on PSTATE.F, the FIQ
                            interrupt mask bit.

<mode>          Is the number of the mode to change to, in the range 0 to 31, encoded in the "mode" field.


Operation for all encodings

 if CurrentInstrSet() == InstrSet_A32 then
     EncodingSpecificOperations();
     if PSTATE.EL != EL0 then
          if enable then
              if affectA then PSTATE.A = '0';
              if affectI then PSTATE.I = '0';
              if affectF then PSTATE.F = '0';
          if disable then
              if affectA then PSTATE.A = '1';
              if affectI then PSTATE.I = '1';
              if affectF then PSTATE.F = '1';
          if changemode then
              // WriteMode will set PSTATE.IL if 'mode' is not legal.
              AArch32.WriteMode(mode);
 else
     EncodingSpecificOperations();
     if PSTATE.EL != EL0 then
          if enable then
              if affectA then PSTATE.A = '0';
              if affectI then PSTATE.I = '0';
              if affectF then PSTATE.F = '0';
          if disable then
              if affectA then PSTATE.A = '1';
              if affectI then PSTATE.I = '1';
              if affectF then PSTATE.F = '1';
          if changemode then
              // WriteMode will set PSTATE.IL if 'mode' is not legal.
              AArch32.WriteMode(mode);


platform: ARM
mnem: CRC32
description:
        CRC32 performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It is an       (F7.1.40)
        OPTIONAL instruction. It takes an input CRC value in the first source operand, and performs a CRC on an input value
        in the second source operand that can be 8, 16, or 32 bits, and returns the output CRC value. To align with common
        usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the
        CRC calculation.

                 Note
        ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.



        A1


          31       28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                 0
             !=1111     0 0 0 1 0        sz     0      Rn           Rd       (0) (0) 0 (0) 0 1 0 0       Rm
              cond                                                                  C


        CRC32B variant

        Applies when sz = 00.

        CRC32B{<q>} <Rd>, <Rn>, <Rm>


        CRC32H variant

        Applies when sz = 01.

        CRC32H{<q>} <Rd>, <Rn>, <Rm>


        CRC32W variant

        Applies when sz = 10.

        CRC32W{<q>} <Rd>, <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
         size = 8 << UInt(sz);
         crc32c = (C == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if size == 64 then UNPREDICTABLE;
         if cond != '1110' then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3             0
           1 1 1 1 1 0 1 0 1 1 0 0                     Rn       1 1 1 1           Rd       1 0  sz       Rm
                                                C


        CRC32B variant

        Applies when sz = 00.

        CRC32B{<q>} <Rd>, <Rn>, <Rm>


        CRC32H variant

        Applies when sz = 01.
CRC32H{<q>} <Rd>, <Rn>, <Rm>


CRC32W variant

Applies when sz = 10.

CRC32W{<q>} <Rd>, <Rn>, <Rm>


Decode for all variants of this encoding

 d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
 size = 8 << UInt(sz);
 crc32c = (C == '1');
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 if size == 64 then UNPREDICTABLE;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors, and particularly CRC32, CRC32C on page J1-5333.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506. An CRC32 instruction must be unconditional.

<Rd>          Is the general-purpose accumulator output register, encoded in the "Rd" field.

<Rn>          Is the general-purpose accumulator input register, encoded in the "Rn" field.

<Rm>          Is the general-purpose data source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();

     if !HaveCRCExt() then
         UNDEFINED;

     acc = R[n];              // accumulator
     val = R[m]<size-1:0>;    // input value
     poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>;
     tempacc = BitReverse(acc):Zeros(size);
     tempval = BitReverse(val):Zeros(32);
     // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
     R[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));


platform: ARM
mnem: CRC32C
description:
        CRC32C performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It is an       (F7.1.41)
        OPTIONAL instruction. It takes an input CRC value in the first source operand, and performs a CRC on an input value
        in the second source operand that can be 8, 16, or 32 bits, and returns the output CRC value. To align with common
        usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the
        CRC calculation.

                 Note
        ID_ISAR5.CRC32 indicates whether this instruction is supported in the T32 and A32 instruction sets.



        A1


          31       28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                 0
             !=1111     0 0 0 1 0        sz     0      Rn           Rd       (0) (0) 1 (0) 0 1 0 0       Rm
              cond                                                                  C


        CRC32CB variant

        Applies when sz = 00.

        CRC32CB{<q>} <Rd>, <Rn>, <Rm>


        CRC32CH variant

        Applies when sz = 01.

        CRC32CH{<q>} <Rd>, <Rn>, <Rm>


        CRC32CW variant

        Applies when sz = 10.

        CRC32CW{<q>} <Rd>, <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
         size = 8 << UInt(sz);
         crc32c = (C == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if size == 64 then UNPREDICTABLE;
         if cond != '1110' then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3             0
           1 1 1 1 1 0 1 0 1 1 0 1                     Rn       1 1 1 1           Rd       1 0  sz       Rm
                                                C


        CRC32CB variant

        Applies when sz = 00.

        CRC32CB{<q>} <Rd>, <Rn>, <Rm>


        CRC32CH variant

        Applies when sz = 01.
CRC32CH{<q>} <Rd>, <Rn>, <Rm>


CRC32CW variant

Applies when sz = 10.

CRC32CW{<q>} <Rd>, <Rn>, <Rm>


Decode for all variants of this encoding

 d = UInt(Rd); n = UInt(Rn); m = UInt(Rm);
 size = 8 << UInt(sz);
 crc32c = (C == '1');
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 if size == 64 then UNPREDICTABLE;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors, and particularly CRC32, CRC32C on page J1-5333.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506. An CRC32C instruction must be
              unconditional.

<Rd>          Is the general-purpose accumulator output register, encoded in the "Rd" field.

<Rn>          Is the general-purpose accumulator input register, encoded in the "Rn" field.

<Rm>          Is the general-purpose data source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();

     if !HaveCRCExt() then
         UNDEFINED;

     acc = R[n];              // accumulator
     val = R[m]<size-1:0>;    // input value
     poly = (if crc32c then 0x1EDC6F41 else 0x04C11DB7)<31:0>;
     tempacc = BitReverse(acc):Zeros(size);
     tempval = BitReverse(val):Zeros(32);
     // Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
     R[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));


platform: ARM
mnem: DBG
description:
Debug Hint provides a hint to debug and related systems. See the system documentation for what use (if any) is       (F7.1.42)
made of this instruction.


A1


  31       28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3                   0
     !=1111    0 0 1 1 0 0 1 0 0 0 0 0 (1) (1) (1) (1) (0) (0) (0) (0) 1 1 1 1                option
      cond


A1 variant

DBG{<c>}{<q>} #<option>


Decode for this encoding

 // Any decoding of 'option' is specified by the debug system


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3                             0
   1 1 1 1 0 0 1 1 1 0 1 0 (1) (1) (1) (1) 1 0 (0) 0 (0) 0 0 0 1 1 1 1                        option




T1 variant

DBG{<c>}{<q>} #<option>


Decode for this encoding

 // Any decoding of 'option' is specified by the debug system


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<option>       Is a 4-bit unsigned immediate, in the range 0 to 15, encoded in the "option" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     Hint_Debug(option);


platform: ARM
mnem: EORS
description:
        Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value,       (F7.1.46)
        and writes the result to the destination register.

        If the destination register is not the PC, the EORS variant of the instruction updates the condition flags based on the
        result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The EOR variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The EORS variant of the instruction performs an exception return without the use of the stack. In this case:

               --      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                      AArch32 state on page G1-3845.

               --      The instruction is UNDEFINED in Hyp mode.

               --      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


           31       28 27 26 25 24 23 22 21 20 19           16 15        12 11                                   0
             !=1111     0 0 1 0 0 0 1 S                 Rn          Rd                      imm12
              cond


        EOR variant

        Applies when S = 0.

        EOR{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        EORS variant

        Applies when S = 1.

        EORS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);     n = UInt(Rn);     setflags = (S == '1');
         (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14      12 11         8 7                       0
           1 1 1 1 0 i 0 0 1 0 0 S                      Rn       0   imm3        Rd                 imm8




        EOR variant

        Applies when S = 0.

        EOR{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        EORS variant

        Applies when S = 1 && Rd != 1111.
EORS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


Decode for all variants of this encoding

 if Rd == '1111' && S == '1' then SEE TEQ (immediate);
 d = UInt(Rd);  n = UInt(Rn);     setflags = (S == '1');
 (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if (d == 15 && !setflags) || n == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted,
              this register is the same as <Rn>. ARM deprecates using the PC as the destination register, but if the
              PC is used:

              .      For the EOR variant, the instruction is a branch to the address calculated by the operation.
                     This is an interworking branch, see Pseudocode description of operations on the AArch32
                     general-purpose registers and the PC on page E1-2378.

              .      For the EORS variant, the instruction performs an exception return, that restores PSTATE
                     from SPSR_<current_mode>.

              For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted,
              this register is the same as <Rn>.

<Rn>          For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be
              used.

              For encoding T1: is the general-purpose source register, encoded in the "Rn" field.

<const>       For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
              page F4-2559 for the range of values.

              For encoding T1: an immediate value. See Modified immediate constants in T32 instructions on
              page F3-2530 for the range of values.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     result = R[n] EOR imm32;
     if d == 15 then             // Can only occur for A32 encoding
         if setflags then
             ALUExceptionReturn(result);
         else
             ALUWritePC(result);
     else
         R[d] = result;
         if setflags then
             PSTATE.N = result<31>;
             PSTATE.Z = IsZeroBit(result);
             PSTATE.C = carry;
             // PSTATE.V unchanged


platform: ARM
mnem: IT
description:
If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the       (F7.1.53)
IT block are the same as, or the inverse of, the condition the IT instruction specifies for the first instruction in the
block.

The IT instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can
change the condition flags.

16-bit instructions in the IT block, other than CMP, CMN and TST, do not set the condition flags. An IT instruction with
the AL condition can change the behavior without conditional execution.

The architecture permits exception return to an instruction in the IT block only if the restoration of the CPSR
restores ITSTATE to a state consistent with the conditions specified by the IT instruction. Any other exception
return to an instruction in an IT block is UNPREDICTABLE. Any branch to a target instruction in an IT block is not
permitted, and if such a branch is made it is UNPREDICTABLE what condition is used when executing that target
instruction and any subsequent instruction in the IT block.

See also Conditional instructions on page F1-2469 and Conditional execution on page F2-2507.


T1


  15 14 13 12 11 10 9 8 7                4 3           0
   1 0 1 1 1 1 1 1              firstcond       !=0000
                                                 mask


T1 variant

IT{<x>{<y>{<z>}}}{<q>} <cond>


Decode for this encoding

 if mask == '0000' then SEE "Related encodings";
 if firstcond == '1111' || (firstcond == '1110' && BitCount(mask) != 1) then UNPREDICTABLE;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly IT on page J1-5334.

Related encodings: If-Then, and hints on page F3-2527.


Assembler symbols

<x>             The condition for the second instruction in the IT block. If omitted, the "mask" field is set to 0b1000.
                If present it is encoded in the "mask[3]" field:

                T             firstcond[0]

                E             NOT firstcond[0]

<y>             The condition for the third instruction in the IT block. If omitted and <x> is present, the "mask[2:0]"
                field is set to 0b100. If <y> is present it is encoded in the "mask[2]" field:

                T             firstcond[0]

                E             NOT firstcond[0]

<z>             The condition for the fourth instruction in the IT block. If omitted and <y> is present, the "mask[1:0]"
                field is set to 0b10. If <z> is present, the "mask[0]" field is set to 1, and it is encoded in the "mask[1]"
                field:

                T             firstcond[0]
                       E            NOT firstcond[0]

        <q>            See Standard assembler syntax fields on page F2-2506.

        <cond>         The condition for the first instruction in the IT block, encoded in the "firstcond" field. See
                       Table F2-1 on page F2-2507 for the range of conditions available, and the encodings.

        The conditions specified in an IT instruction must match those specified in the syntax of the instructions in its IT
        block. When assembling to A32 code, assemblers check IT instruction syntax for validity but do not generate
        assembled instructions for them. See Conditional instructions on page F1-2469.


        Operation

         EncodingSpecificOperations();
         AArch32.CheckITEnabled(mask);
         PSTATE.IT<7:0> = firstcond:mask;


platform: ARM
mnem: LDA
description:
Load-Acquire Word loads a word from memory and writes it to a register. The instruction also has memory ordering       (F7.1.54)
semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111   0 0 0 1 1 0 0 1               Rn            Rt      (1) (1) 0 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDA{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                  Rn            Rt      (1) (1) (1) (1) 1 0 1 0 (1) (1) (1) (1)




T1 variant

LDA{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     R[t] = MemO[address, 4];


platform: ARM
mnem: LDAB
description:
Load-Acquire Byte loads a byte from memory, zero-extends it to form a 32-bit word and writes it to a register. The       (F7.1.55)
instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111     0 0 0 1 1 1 0 1               Rn           Rt      (1) (1) 0 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                    Rn           Rt      (1) (1) (1) (1) 1 0 0 0 (1) (1) (1) (1)




T1 variant

LDAB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     R[t] = ZeroExtend(MemO[address, 1], 32);


platform: ARM
mnem: LDAEX
description:
Load-Acquire Exclusive Word loads a word from memory, writes it to a register and:       (F7.1.56)

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111    0 0 0 1 1 0 0 1              Rn            Rt      (1) (1) 1 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAEX{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                  Rn            Rt      (1) (1) (1) (1) 1 1 1 0 (1) (1) (1) (1)




T1 variant

LDAEX{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDAEX on page J1-5349.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address, 4);
             R[t] = MemO[address, 4];


platform: ARM
mnem: LDAEXB
description:
Load-Acquire Exclusive Byte loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register       (F7.1.57)
and:

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111    0 0 0 1 1 1 0 1              Rn            Rt      (1) (1) 1 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAEXB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                  Rn            Rt      (1) (1) (1) (1) 1 1 0 0 (1) (1) (1) (1)




T1 variant

LDAEXB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDAEXB on page J1-5349.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address, 1);
             R[t] = ZeroExtend(MemO[address, 1], 32);


platform: ARM
mnem: LDAEXD
description:
Load-Acquire Exclusive Doubleword loads a doubleword from memory, writes it to two registers and:       (F7.1.58)

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

The instruction also acts as a barrier instruction with the ordering requirements described in Load-Acquire,
Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111    0 0 0 1 1 0 1 1                 Rn           Rt       (1) (1) 1 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   t2 = t + 1;    n = UInt(Rn);
 if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11         8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                     Rn           Rt            Rt2     1 1 1 1 (1) (1) (1) (1)




T1 variant

LDAEXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   t2 = UInt(Rt2);     n = UInt(Rn);
 if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDAEXD on page J1-5350.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
               <Rt> must be even-numbered and not R14.

               For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
        <Rt2>          For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

                       For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address, 8);
             value = MemO[address, 8];
             // Extract words from 64-bit loaded value such that R[t] is
             // loaded from address and R[t2] from address+4.
             R[t]  = if BigEndian() then value<63:32> else value<31:0>;
             R[t2] = if BigEndian() then value<31:0>     else value<63:32>;


platform: ARM
mnem: LDAEXH
description:
Load-Acquire Exclusive Halfword loads a halfword from memory, zero-extends it to form a 32-bit word, writes it       (F7.1.59)
to a register and:

.      If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
       executing PE in a global monitor.

.      Causes the executing PE to indicate an active exclusive access in the local monitor.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111     0 0 0 1 1 1 1 1              Rn            Rt      (1) (1) 1 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAEXH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                   Rn            Rt      (1) (1) (1) (1) 1 1 0 1 (1) (1) (1) (1)




T1 variant

LDAEXH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDAEXH on page J1-5349.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address, 2);
             R[t] = ZeroExtend(MemO[address, 2], 32);


platform: ARM
mnem: LDAH
description:
Load-Acquire Halfword loads a halfword from memory, zero-extends it to form a 32-bit word and writes it to a       (F7.1.60)
register. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on
page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111     0 0 0 1 1 1 1 1              Rn            Rt      (1) (1) 0 0 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDAH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                   Rn            Rt      (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1)




T1 variant

LDAH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior, see Appendix J1 Architectural Constraints on
UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             R[t] = ZeroExtend(MemO[address, 2], 32);


platform: ARM
mnem: LDC
description:
Load Coprocessor (immediate) loads data from consecutive memory addresses to a conceptual coprocessor.       (F7.1.61)

This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the imm8, CRd, and D field values
that are valid LDC and LDC2 instructions. Other encodings are UNDEFINED. For more information see Conceptual
coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

In an implementation that includes EL2, the permitted LDC access to a system control register can be trapped to Hyp
mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would
be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see
Trapping general CP14 accesses to debug registers on page G1-3923.

For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11          8 7                      0
     !=1111     1 1 0 P U D W 1             !=1111        CRd          !=101x              imm8
      cond                                    Rn                        coproc


Offset variant

Applies when P = 1 && W = 0.

LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 1.

LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


Unindexed variant

Applies when P = 0 && U = 1 && W = 0.

LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


Decode for all variants of this encoding

 if Rn == '1111' then SEE LDC (literal);
 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MRRC, MRRC2;
 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 n = UInt(Rn);    cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);       index = (P == '1');    add = (U == '1');     wback = (W == '1');


A2


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11          8 7                      0
   1 1 1 1 1 1 0 P U D W 1                  !=1111        CRd          !=101x              imm8
      cond                                    Rn                        coproc
        Offset variant

        Applies when P = 1 && W = 0.

        LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 1.

        LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.

        LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


        Unindexed variant

        Applies when P = 0 && U = 1 && W = 0.

        LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


        Decode for all variants of this encoding

         if Rn == '1111' then SEE LDC (literal);
         if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
         if P == '0' && U == '0' && D == '1' && W == '0' then SEE MRRC, MRRC2;
         if coproc == '101x' then UNDEFINED;
         n = UInt(Rn); cp = UInt(coproc);
         imm32 = ZeroExtend(imm8:'00', 32);      index = (P == '1');add = (U == '1');wback = (W == '1');


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15      12 11       8 7                  0
           1 1 1 0 1 1 0 P U D W 1                  !=1111       CRd     !=101x         imm8
                                                      Rn                 coproc


        Offset variant

        Applies when P = 1 && W = 0.

        LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 1.

        LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.

        LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


        Unindexed variant

        Applies when P = 0 && U = 1 && W = 0.

        LDC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>
Decode for all variants of this encoding

 if Rn == '1111' then SEE LDC (literal);
 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MRRC, MRRC2;
 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 n = UInt(Rn);  cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);     index = (P == '1');   add = (U == '1');    wback = (W == '1');


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15       12 11         8 7                       0
  1 1 1 1 1 1 0 P U D W 1                 !=1111        CRd         !=101x              imm8
                                            Rn                      coproc


Offset variant

Applies when P = 1 && W = 0.

LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 1.

LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


Unindexed variant

Applies when P = 0 && U = 1 && W = 0.

LDC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


Decode for all variants of this encoding

 if Rn == '1111' then SEE LDC (literal);
 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MRRC, MRRC2;
 if coproc == '101x' then UNDEFINED;
 n = UInt(Rn); cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);     index = (P == '1');   add = (U == '1');    wback = (W == '1');


Notes for all encodings

Advanced SIMD and floating-point: Advanced SIMD and floating-point register load/store instructions on
page F5-2602.


Assembler symbols

L             If specified, selects the D == 1 form of the encoding. If omitted, selects the D == 0 form.

<c>           For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

              For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

<q>           See Standard assembler syntax fields on page F2-2506.
        <coproc>       Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                       p11, p14, and p15.

        <CRd>          Is the coprocessor register to be transferred, encoded in the "CRd" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see LDC, LDC2
                       (literal).

        <option>       Is a coprocessor option, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field.

        +/-            Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
                       encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <imm>          Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting
                       to 0 and encoded in the "imm8" field, as <imm>/4.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             Coproc_CheckInstr(cp, ThisInstr());
             offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
             address = if index then offset_addr else R[n];
             repeat
                 Coproc_SendLoadedWord(MemA[address,4], cp, ThisInstr());
                 address = address + 4;
             until Coproc_DoneLoading(cp, ThisInstr());
             if wback then R[n] = offset_addr;


platform: ARM
mnem: LDM
description:
        Load Multiple (Increment After, Full Descending) loads multiple registers from consecutive memory locations       (F7.1.63)
        using an address from a base register. The consecutive memory locations start at this address, and the address just
        above the highest of those locations can optionally be written back to the base register.

        The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
        from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
        page F2-2514.

        The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see
        Pseudocode description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.

        Related system instructions are LDM (User registers) and LDM (exception return).

        This instruction is used by the alias POP (multiple registers). See the Alias conditions on page F7-2761 table for
        details of when each alias is preferred.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15                                              0
             !=1111    1 0 0 0 1 0 W 1                Rn                          register_list
              cond


        A1 variant

        LDM{IA}{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        LDMFD{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Descending stack


        Decode for this encoding

         n = UInt(Rn);    registers = register_list;    wback = (W == '1');
         if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
         if wback && registers<n> == '1' then UNPREDICTABLE;


        T1


          15 14 13 12 11 10      8 7                      0
           1 1 0 0 1          Rn           register_list




        T1 variant

        LDM{IA}{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        LDMFD{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Descending stack


        Decode for this encoding

         n = UInt(Rn);    registers = '00000000':register_list;      wback = (registers<n> == '0');
         if BitCount(registers) < 1 then UNPREDICTABLE;


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12                                      0
           1 1 1 0 1 0 0 0 1 0 W 1                    Rn       P M (0)                 register_list
T2 variant

LDM{IA}{<c>}.W <Rn>{!}, <registers>// Preferred syntax, if <Rn>, '!' and <registers> can be represented
in T1
LDMFD{<c>}.W <Rn>{!}, <registers>// Alternate syntax, Full Descending stack, if <Rn>, '!' and <registers>
can be represented in T1
LDM{IA}{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
LDMFD{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Descending stack


Decode for this encoding

 n = UInt(Rn);  registers = P:M:'0':register_list;         wback = (W == '1');
 if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;
 if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDM/LDMIA/LDMFD (T32) on
page J1-5334 and LDM/LDMIA/LDMFD (A32) on page J1-5335.


Alias conditions


                Alias                           is preferred when

                POP (multiple registers)        W == '1' && Rn == '1101' && BitCount(register_list) > 1



Assembler symbols

IA             Is an optional suffix for the Increment After form.

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.

!              For encoding A1 and T2: the address adjusted by the size of the data loaded is written back to the
               base register. If specified, it is encoded in the "W" field as 1, otherwise this field defaults to 0.

               For encoding T1: the address adjusted by the size of the data loaded is written back to the base
               register. It is omitted if <Rn> is included in <registers>, otherwise it must be present.

<registers>    For encoding A1: is a list of one or more registers to be loaded, separated by commas and
               surrounded by { and }. The PC can be in the list. ARM deprecates using these instructions with both
               the LR and the PC in the list.

               For encoding T1: is a list of one or more registers to be loaded, separated by commas and surrounded
               by { and }. The registers in the list must be in the range R0-R7, encoded in the "register_list" field.

               For encoding T2: is a list of one or more registers to be loaded, separated by commas and surrounded
               by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field,
               and can optionally contain one of the LR or the PC. If the LR is in the list, the "M" field is set to 1,
               otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.
               If the PC is in the list:

               .      The LR must not be in the list.

               .      The instruction must be either outside any IT block, or the last instruction in an IT block.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             for i = 0 to 14
                 if registers<i> == '1' then
                     R[i] = MemA[address,4];      address = address + 4;
             if registers<15> == '1' then
                 LoadWritePC(MemA[address,4]);
             if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
             if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;


platform: ARM
mnem: LDMDA
description:
Load Multiple Decrement After (Full Ascending) loads multiple registers from consecutive memory locations using       (F7.1.66)
an address from a base register. The consecutive memory locations end at this address, and the address just below
the lowest of those locations can optionally be written back to the base register.

The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
page F2-2514.

The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see
Pseudocode description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.

Related system instructions are LDM (User registers) and LDM (exception return).


A1


  31       28 27 26 25 24 23 22 21 20 19             16 15                                              0
     !=1111    1 0 0 0 0 0 W 1                 Rn                           register_list
      cond


A1 variant

LDMDA{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
LDMFA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Ascending stack


Decode for this encoding

 n = UInt(Rn);    registers = register_list;       wback = (W == '1');
 if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDMDA/LDMFA on page J1-5336.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

!               The address adjusted by the size of the data loaded is written back to the base register. If specified,
                it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<registers>     Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The
                PC can be in the list. ARM deprecates using these instructions with both the LR and the PC in the
                list.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n] - 4*BitCount(registers) + 4;
     for i = 0 to 14
         if registers<i> == '1' then
              R[i] = MemA[address,4];      address = address + 4;
     if registers<15> == '1' then
                 LoadWritePC(MemA[address,4]);
             if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
             if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;


platform: ARM
mnem: LDMDB
description:
Load Multiple Decrement Before (Empty Ascending) loads multiple registers from consecutive memory locations       (F7.1.67)
using an address from a base register. The consecutive memory locations end just below this address, and the
address of the lowest of those locations can optionally be written back to the base register.

The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
page F2-2514.

The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see
Pseudocode description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.

Related system instructions are LDM (User registers) and LDM (exception return).


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15                                              0
     !=1111     1 0 0 1 0 0 W 1              Rn                          register_list
      cond


A1 variant

LDMDB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
LDMEA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Ascending stack


Decode for this encoding

 n = UInt(Rn);   registers = register_list;     wback = (W == '1');
 if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12                                      0
  1 1 1 0 1 0 0 1 0 0 W 1                    Rn       P M (0)                 register_list




T1 variant

LDMDB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
LDMEA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Ascending stack


Decode for this encoding

 n = UInt(Rn);   registers = P:M:'0':register_list;      wback = (W == '1');
 if n == 15 || BitCount(registers) < 2 || (P == '1' && M == '1') then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;
 if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDMDB/LDMEA on page J1-5336.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.
        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.

        !              The address adjusted by the size of the data loaded is written back to the base register. If specified,
                       it is encoded in the "W" field as 1, otherwise this field defaults to 0.

        <registers>    For encoding A1: is a list of one or more registers to be loaded, separated by commas and
                       surrounded by { and }. The PC can be in the list. ARM deprecates using these instructions with both
                       the LR and the PC in the list.

                       For encoding T1: is a list of one or more registers to be loaded, separated by commas and surrounded
                       by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field,
                       and can optionally contain one of the LR or the PC. If the LR is in the list, the "M" field is set to 1,
                       otherwise it defaults to 0. If the PC is in the list, the "P" field is set to 1, otherwise it defaults to 0.
                       If the PC is in the list:

                       .      The LR must not be in the list.

                       .      The instruction must be either outside any IT block, or the last instruction in an IT block.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n] - 4*BitCount(registers);
             for i = 0 to 14
                 if registers<i> == '1' then
                     R[i] = MemA[address,4];      address = address + 4;
             if registers<15> == '1' then
                 LoadWritePC(MemA[address,4]);
             if wback && registers<n> == '0' then R[n] = R[n] - 4*BitCount(registers);
             if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;


platform: ARM
mnem: LDMIB
description:
Load Multiple Increment Before (Empty Descending) loads multiple registers from consecutive memory locations       (F7.1.68)
using an address from a base register. The consecutive memory locations start just above this address, and the
address of the last of those locations can optionally be written back to the base register.

The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
page F2-2514.

The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see
Pseudocode description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.

Related system instructions are LDM (User registers) and LDM (exception return).


A1


  31        28 27 26 25 24 23 22 21 20 19            16 15                                              0
     !=1111     1 0 0 1 1 0 W 1                Rn                           register_list
      cond


A1 variant

LDMIB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
LDMED{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Descending stack


Decode for this encoding

 n = UInt(Rn);    registers = register_list;       wback = (W == '1');
 if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDMIB/LDMED on page J1-5336.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

!               The address adjusted by the size of the data loaded is written back to the base register. If specified,
                it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<registers>     Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The
                PC can be in the list. ARM deprecates using these instructions with both the LR and the PC in the
                list.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n] + 4;
     for i = 0 to 14
         if registers<i> == '1' then
              R[i] = MemA[address,4];      address = address + 4;
     if registers<15> == '1' then
                 LoadWritePC(MemA[address,4]);
             if wback && registers<n> == '0' then R[n] = R[n] + 4*BitCount(registers);
             if wback && registers<n> == '1' then R[n] = bits(32) UNKNOWN;


platform: ARM
mnem: LDRBT
description:
        Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to       (F7.1.75)
        a register. For information about memory accesses see Memory accesses on page F2-2513.

        The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
        actually running in User mode.

        LDRBT is UNPREDICTABLE in Hyp mode.

        The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
        base register value and an immediate offset, and leaves the base register unchanged.

        The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
        memory access, and calculates a new address from a base register value and an offset and writes it back to the base
        register. The offset can be an immediate value or an optionally-shifted register value.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15       12 11                                  0
             !=1111      0 1 0 0 U 1 1 1              Rn          Rt                      imm12
              cond


        A1 variant

        LDRBT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


        Decode for this encoding

         t = UInt(Rt);     n = UInt(Rn);  postindex = TRUE;   add = (U == '1');
         register_form = FALSE;     imm32 = ZeroExtend(imm12, 32);
         if t == 15 || n == 15 || n == t then UNPREDICTABLE;


        A2


          31        28 27 26 25 24 23 22 21 20 19         16 15       12 11             7 6 5 4 3            0
             !=1111      0 1 1 0 U 1 1 1              Rn          Rt           imm5        type 0      Rm
              cond


        A2 variant

        LDRBT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}


        Decode for this encoding

         t = UInt(Rt);     n = UInt(Rn);  m = UInt(Rm);   postindex = TRUE;    add = (U == '1');
         register_form = TRUE;     (shift_t, shift_n) = DecodeImmShift(type, imm5);
         if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11 10 9 8 7                         0
           1 1 1 1 1 0 0 0 0 0 0 1                  !=1111        Rt       1 1 1 0              imm8
                                                      Rn


        T1 variant

        LDRBT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
Decode for this encoding

 if Rn == '1111' then SEE LDRB (literal);
 t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;   add = TRUE;
 register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
 if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRBT on page J1-5339.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC
               can be used, but this is deprecated.

               For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The SP can be
               used.

               For encoding A2 and T1: is the general-purpose base register, encoded in the "Rn" field.

+/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
               + if omitted and encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

               For encoding A2: specifies the index register is added to or subtracted from the base register,
               defaulting to + if omitted and encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

<Rm>           Is the general-purpose index register, encoded in the "Rm" field.

<shift>        The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts
               applied to a register on page F2-2510.

+              Specifies the offset is added to the base register.

<imm>          For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
               defaulting to 0 and encoded in the "imm12" field.

               For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
               defaulting to 0 and encoded in the "imm8" field.


Operation for all encodings

 if ConditionPassed() then
     if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
     EncodingSpecificOperations();
     offset = if register_form then Shift(R[m], shift_t, shift_n, PSTATE.C) else imm32;
     offset_addr = if add then (R[n] + offset) else (R[n] - offset);
     address = if postindex then R[n] else offset_addr;
     R[t] = ZeroExtend(MemU_unpriv[address,1],32);
     if postindex then R[n] = offset_addr;


platform: ARM
mnem: LDRD
description:
        Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two       (F7.1.76)
        words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing.
        For information about memory accesses see Memory accesses on page F2-2513.


        A1


          31       28 27 26 25 24 23 22 21 20 19          16 15      12 11         8 7 6 5 4 3              0
             !=1111   0 0 0 P U 1 W 0               !=1111        Rt       imm4H      1 1 0 1        imm4L
              cond                                    Rn


        Offset variant

        Applies when P = 1 && W = 0.

        LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 0.

        LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.

        LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!


        Decode for all variants of this encoding

         if Rn == '1111' then SEE LDRD (literal);
         if Rt<0> == '1' then UNPREDICTABLE;
         t = UInt(Rt);  t2 = t+1;    n = UInt(Rn);    imm32 = ZeroExtend(imm4H:imm4L, 32);
         index = (P == '1');   add = (U == '1');     wback = (P == '0') || (W == '1');
         if P == '0' && W == '1' then UNPREDICTABLE;
         if wback && (n == t || n == t2) then UNPREDICTABLE;
         if t2 == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15       12 11         8 7                      0
           1 1 1 0 1 0 0 P U 1 W 1                  !=1111        Rt        Rt2                 imm8
                                                      Rn


        Offset variant

        Applies when P = 1 && W = 0.

        LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 1.

        LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.
LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!


Decode for all variants of this encoding

 if P == '0' && W == '0' then SEE "Related encodings";
 if Rn == '1111' then SEE LDRD (literal);
 t = UInt(Rt);  t2 = UInt(Rt2);     n = UInt(Rn);   imm32 = ZeroExtend(imm8:'00', 32);
 index = (P == '1');   add = (U == '1');    wback = (W == '1');
 if wback && (n == t || n == t2) then UNPREDICTABLE;
 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRD (immediate) on page J1-5346.

Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch on
page F3-2536.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
               This register must be even-numbered and not R14.

               For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>          For encoding A1: is the second general-purpose register to be transferred. This register must be
               <R(t+1)>.

               For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Rn>           For encoding A1 or T1: is the general-purpose base register, encoded in the "Rn" field. For PC use
               see LDRD (literal).

               For the post-indexed or pre-indexed variant: is the general-purpose base register, encoded in the
               "Rn" field.

+/-            Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
               encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

<imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
               defaulting to 0 and encoded in the "imm4H:imm4L" field.

               For the post-indexed or pre-indexed variant: is the unsigned immediate byte offset, a multiple of 4,
               in the range 0 to 1020, encoded in the "imm8" field as <imm>/4.

               For the post-indexed or pre-indexed variant: is the 8-bit unsigned immediate byte offset, in the range
               0 to 255, encoded in the "imm4H:imm4L" field.

               For encoding T1: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to
               1020, defaulting to 0 and encoded in the "imm8" field as <imm>/4.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
     address = if index then offset_addr else R[n];
     if address == Align(address, 8) then
         data = MemA[address,8];
                 if BigEndian()   then
                     R[t] = data<63:32>;
                     R[t2] = data<31:0>;
                 else
                     R[t] = data<31:0>;
                     R[t2] = data<63:32>;
             else
                 R[t] = MemA[address,4];
                 R[t2] = MemA[address+4,4];
             if wback then R[n] = offset_addr;


platform: ARM
mnem: LDREX
description:
Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from       (F7.1.79)
memory, writes it to a register and:

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111    0 0 0 1 1 0 0 1              Rn            Rt      (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDREX{<c>}{<q>} <Rt>, [<Rn> {, {#}<imm>}]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);    imm32 = Zeros(32); // Zero offset
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7                         0
   1 1 1 0 1 0 0 0 0 1 0 1                  Rn            Rt      (1) (1) (1) (1)        imm8




T1 variant

LDREX{<c>}{<q>} <Rt>, [<Rn> {, #<imm>}]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);    imm32 = ZeroExtend(imm8:'00', 32);
 if t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDREX on page J1-5348.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.

<imm>          For encoding A1: the immediate offset added to the value of <Rn> to calculate the address. <imm> can
               only be 0 or omitted.
                       For encoding T1: the immediate offset added to the value of <Rn> to calculate the address. <imm> can
                       be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n] + imm32;
             AArch32.SetExclusiveMonitors(address,4);
             R[t] = MemA[address,4];


platform: ARM
mnem: LDREXB
description:
Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends       (F7.1.80)
it to form a 32-bit word, writes it to a register and:

.       If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
        executing PE in a global monitor.

.       Causes the executing PE to indicate an active exclusive access in the local monitor.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


   31        28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
      !=1111     0 0 0 1 1 1 0 1                Rn          Rt        (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1)
       cond


A1 variant

LDREXB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);     n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


   15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3 2 1 0
    1 1 1 0 1 0 0 0 1 1 0 1                     Rn          Rt        (1) (1) (1) (1) 0 1 0 0 (1) (1) (1) (1)




T1 variant

LDREXB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);     n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDREXB on page J1-5349.


Assembler symbols

<c>              See Standard assembler syntax fields on page F2-2506.

<q>              See Standard assembler syntax fields on page F2-2506.

<Rt>             Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>             Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address,1);
             R[t] = ZeroExtend(MemA[address,1], 32);


platform: ARM
mnem: LDREXD
description:
Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from       (F7.1.81)
memory, writes it to two registers and:

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111    0 0 0 1 1 0 1 1               Rn           Rt      (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   t2 = t + 1;   n = UInt(Rn);
 if Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11         8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                   Rn           Rt           Rt2     0 1 1 1 (1) (1) (1) (1)




T1 variant

LDREXD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   t2 = UInt(Rt2);    n = UInt(Rn);
 if t == 15 || t2 == 15 || t == t2 || n == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDREXD on page J1-5349.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
               <Rt> must be even-numbered and not R14.

               For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
        <Rt2>          For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

                       For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address,8);
             value = MemA[address,8];
             // Extract words from 64-bit loaded value such that R[t] is
             // loaded from address and R[t2] from address+4.
             R[t]  = if BigEndian() then value<63:32> else value<31:0>;
             R[t2] = if BigEndian() then value<31:0> else value<63:32>;


platform: ARM
mnem: LDREXH
description:
Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory,       (F7.1.82)
zero-extends it to form a 32-bit word, writes it to a register and:

.     If the address has the Shared Memory attribute, marks the physical address as exclusive access for the
      executing PE in a global monitor.

.     Causes the executing PE to indicate an active exclusive access in the local monitor.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
     !=1111     0 0 0 1 1 1 1 1              Rn             Rt      (1) (1) 1 1 1 0 0 1 (1) (1) (1) (1)
      cond


A1 variant

LDREXH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 1                   Rn             Rt      (1) (1) (1) (1) 0 1 0 1 (1) (1) (1) (1)




T1 variant

LDREXH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt);   n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDREXH on page J1-5348.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             address = R[n];
             AArch32.SetExclusiveMonitors(address,2);
             R[t] = ZeroExtend(MemA[address,2], 32);


platform: ARM
mnem: LDRHT
description:
        Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and       (F7.1.86)
        writes it to a register. For information about memory accesses see Memory accesses on page F2-2513.

        The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
        actually running in User mode.

        LDRHT is UNPREDICTABLE in Hyp mode.

        The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
        base register value and an immediate offset, and leaves the base register unchanged.

        The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
        memory access, and calculates a new address from a base register value and an offset and writes it back to the base
        register. The offset can be an immediate value or a register value.


        A1


          31         28 27 26 25 24 23 22 21 20 19         16 15       12 11          8 7 6 5 4 3            0
             !=1111      0 0 0 0 U 1 1 1               Rn           Rt      imm4H        1 0 1 1     imm4L
              cond


        A1 variant

        LDRHT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


        Decode for this encoding

         t = UInt(Rt);     n = UInt(Rn);    postindex = TRUE;   add = (U == '1');
         register_form = FALSE;       imm32 = ZeroExtend(imm4H:imm4L, 32);
         if t == 15 || n == 15 || n == t then UNPREDICTABLE;


        A2


          31         28 27 26 25 24 23 22 21 20 19         16 15       12 11 10 9 8 7 6 5 4 3                0
             !=1111      0 0 0 0 U 0 1 1               Rn           Rt    (0) (0) (0) (0) 1 0 1 1      Rm
              cond


        A2 variant

        LDRHT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>


        Decode for this encoding

         t = UInt(Rt);     n = UInt(Rn);    m = UInt(Rm);  postindex = TRUE;   add = (U == '1');
         register_form = TRUE;
         if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7                        0
           1 1 1 1 1 0 0 0 0 0 1 1                  !=1111          Rt     1 1 1 0              imm8
                                                       Rn


        T1 variant

        LDRHT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
Decode for this encoding

 if Rn == '1111' then SEE LDRH (literal);
 t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;    add = TRUE;
 register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
 if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRHT on page J1-5341.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.

+/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
               + if omitted and encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

               For encoding A2: specifies the index register is added to or subtracted from the base register,
               defaulting to + if omitted and encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

<Rm>           Is the general-purpose index register, encoded in the "Rm" field.

+              Specifies the offset is added to the base register.

<imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
               defaulting to 0 and encoded in the "imm4H:imm4L" field.

               For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
               defaulting to 0 and encoded in the "imm8" field.


Operation for all encodings

 if ConditionPassed() then
     if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
     EncodingSpecificOperations();
     offset = if register_form then R[m] else imm32;
     offset_addr = if add then (R[n] + offset) else (R[n] - offset);
     address = if postindex then R[n] else offset_addr;
     data = MemU_unpriv[address,2];
     if postindex then R[n] = offset_addr;
     R[t] = ZeroExtend(data, 32);


platform: ARM
mnem: LDRSBT
description:
Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and       (F7.1.90)
writes it to a register. For information about memory accesses see Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

LDRSBT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or a register value.


A1


  31         28 27 26 25 24 23 22 21 20 19         16 15       12 11            8 7 6 5 4 3            0
     !=1111      0 0 0 0 U 1 1 1               Rn           Rt         imm4H       1 1 0 1      imm4L
      cond


A1 variant

LDRSBT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);     n = UInt(Rn);    postindex = TRUE;   add = (U == '1');
 register_form = FALSE;       imm32 = ZeroExtend(imm4H:imm4L, 32);
 if t == 15 || n == 15 || n == t then UNPREDICTABLE;


A2


  31         28 27 26 25 24 23 22 21 20 19         16 15       12 11 10 9 8 7 6 5 4 3                  0
     !=1111      0 0 0 0 U 0 1 1               Rn           Rt      (0) (0) (0) (0) 1 1 0 1      Rm
      cond


A2 variant

LDRSBT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>


Decode for this encoding

 t = UInt(Rt);     n = UInt(Rn);    m = UInt(Rm);  postindex = TRUE;      add = (U == '1');
 register_form = TRUE;
 if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7                          0
  1 1 1 1 1 0 0 1 0 0 0 1                   !=1111          Rt       1 1 1 0             imm8
                                               Rn


T1 variant

LDRSBT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then SEE LDRSB (literal);
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;    add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRSBT on page J1-5342.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm4H:imm4L" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then R[m] else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             R[t] = SignExtend(MemU_unpriv[address,1], 32);
             if postindex then R[n] = offset_addr;


platform: ARM
mnem: LDRSHT
description:
Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word,       (F7.1.94)
and writes it to a register. For information about memory accesses see Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

LDRSHT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or a register value.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15       12 11            8 7 6 5 4 3            0
     !=1111     0 0 0 0 U 1 1 1               Rn            Rt         imm4H       1 1 1 1      imm4L
      cond


A1 variant

LDRSHT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);     postindex = TRUE;   add = (U == '1');
 register_form = FALSE;      imm32 = ZeroExtend(imm4H:imm4L, 32);
 if t == 15 || n == 15 || n == t then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3                  0
     !=1111     0 0 0 0 U 0 1 1               Rn            Rt      (0) (0) (0) (0) 1 1 1 1      Rm
      cond


A2 variant

LDRSHT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);     m = UInt(Rm);  postindex = TRUE;      add = (U == '1');
 register_form = TRUE;
 if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7                          0
  1 1 1 1 1 0 0 1 0 0 1 1                    !=1111         Rt       1 1 1 0             imm8
                                              Rn


T1 variant

LDRSHT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then SEE LDRSH (literal);
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;    add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRSHT on page J1-5343.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm4H:imm4L" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then R[m] else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             data = MemU_unpriv[address,2];
             if postindex then R[n] = offset_addr;
             R[t] = SignExtend(data, 32);


platform: ARM
mnem: LDRT
description:
Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory       (F7.1.95)
accesses see Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

LDRT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or an optionally-shifted register value.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11                                  0
     !=1111     0 1 0 0 U 0 1 1              Rn           Rt                      imm12
      cond


A1 variant

LDRT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   postindex = TRUE;   add = (U == '1');
 register_form = FALSE;     imm32 = ZeroExtend(imm12, 32);
 if t == 15 || n == 15 || n == t then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11             7 6 5 4 3            0
     !=1111     0 1 1 0 U 0 1 1              Rn           Rt            imm5       type 0      Rm
      cond


A2 variant

LDRT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   m = UInt(Rm);   postindex = TRUE;     add = (U == '1');
 register_form = TRUE;     (shift_t, shift_n) = DecodeImmShift(type, imm5);
 if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11 10 9 8 7                         0
  1 1 1 1 1 0 0 0 0 1 0 1                  !=1111         Rt      1 1 1 0               imm8
                                             Rn


T1 variant

LDRT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then SEE LDR (literal);
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;   add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly LDRT on page J1-5343.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC
                       can be used, but this is deprecated.

                       For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>           For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The SP can be
                       used.

                       For encoding A2 and T1: is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        <shift>        The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts
                       applied to a register on page F2-2510.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
                       defaulting to 0 and encoded in the "imm12" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then Shift(R[m], shift_t, shift_n, PSTATE.C) else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             data = MemU_unpriv[address,4];
             if postindex then R[n] = offset_addr;
             R[t] = data;


platform: ARM
mnem: LSLS
description:
Logical Shift Left, setting flags (immediate) shifts a register value left by an immediate number of bits, shifting in       (F7.1.98)
zeros, and writes the result to the destination register.

If the destination register is not the PC, this instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination register is the PC:

.      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

.      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32
       state on page G1-3845.

.      The instruction is UNDEFINED in Hyp mode.

.      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.

This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

.      The encodings in this description are named to match the encodings of MOV, MOVS (register).

.      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


A1


  31        28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11            7 6 5 4 3             0
     !=1111     0 0 0 1 1 0 1 1 (0) (0) (0) (0)              Rd           !=00000     0 0 0        Rm
      cond                              S                                   imm5      type


MOVS, shift or rotate by value variant

LSLS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

is equivalent to

MOVS{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>

and is always the preferred disassembly.


T2


  15 14 13 12 11 10              6 5        3 2       0
   0 0 0 0 0           !=00000         Rn         Rd
              op        imm5


T2 variant

LSLS{<q>} {<Rd>,} <Rm>, #<imm>// Outside IT block

is equivalent to

MOVS{<q>} <Rd>, <Rm>, LSL #<imm>

and is the preferred disassembly when !InITBlock().
        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                  12 11           8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0) imm3                             Rd       imm2 0 0           Rm
                                              S                                                  type


        MOVS, shift or rotate by value variant

        LSLS.W {<Rd>,} <Rm>, #<imm>// Outside IT block, and <Rd>, <Rm>, <imm> can be represented in T2

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>

        and is always the preferred disassembly.

        LSLS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, LSL #<imm>

        and is always the preferred disassembly.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
                        deprecates using the PC as the destination register, but if the PC is used, the instruction performs an
                        exception return, that restores PSTATE from SPSR_<current_mode>.

                        For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>            For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
                        used.

                        For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.

        <imm>           For encoding A1 and T2: is the shift amount, in the range 1 to 31, encoded in the "imm5" field.

                        For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.


        Operation for all encodings

        The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: LSRS
description:
Logical Shift Right, setting flags (immediate) shifts a register value right by an immediate number of bits, shifting       (F7.1.102)
in zeros, and writes the result to the destination register.

If the destination register is not the PC, this instruction updates the condition flags based on the result.

The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
deprecates any use of these encodings. However, when the destination register is the PC:

.      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

.      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32
       state on page G1-3845.

.      The instruction is UNDEFINED in Hyp mode.

.      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.

This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

.      The encodings in this description are named to match the encodings of MOV, MOVS (register).

.      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


A1


  31        28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11            7 6 5 4 3             0
     !=1111     0 0 0 1 1 0 1 1 (0) (0) (0) (0)              Rd             imm5      0 1 0        Rm
      cond                              S                                             type


MOVS, shift or rotate by value variant

LSRS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

is equivalent to

MOVS{<c>}{<q>} <Rd>, <Rm>, LSR #<imm>

and is always the preferred disassembly.


T2


  15 14 13 12 11 10               6 5       3 2       0
   0 0 0 0 1            imm5           Rn         Rd
              op


T2 variant

LSRS{<q>} {<Rd>,} <Rm>, #<imm>// Outside IT block

is equivalent to

MOVS{<q>} <Rd>, <Rm>, LSR #<imm>

and is the preferred disassembly when !InITBlock().
        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                  12 11           8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0) imm3                             Rd       imm2 0 1           Rm
                                              S                                                  type


        MOVS, shift or rotate by value variant

        LSRS.W {<Rd>,} <Rm>, #<imm>// Outside IT block, and <Rd>, <Rm>, <imm> can be represented in T2

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, LSR #<imm>

        and is always the preferred disassembly.

        LSRS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, LSR #<imm>

        and is always the preferred disassembly.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
                        deprecates using the PC as the destination register, but if the PC is used, the instruction performs an
                        exception return, that restores PSTATE from SPSR_<current_mode>.

                        For encoding T2 and T3: is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>            For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
                        used.

                        For encoding T2 and T3: is the general-purpose source register, encoded in the "Rm" field.

        <imm>           For encoding A1 and T2: is the shift amount, in the range 1 to 32, encoded in the "imm5" field as
                        <imm> modulo 32.

                        For encoding T3: is the shift amount, in the range 1 to 32, encoded in the "imm3:imm2" field as
                        <imm> modulo 32.


        Operation for all encodings

        The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: MCR
description:
Move to Coprocessor from general-purpose register passes the value of a general-purpose register to a conceptual       (F7.1.104)
coprocessor.

This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the opc1, opc2, CRn, and CRd field
values that are valid MCR and MCR2 instructions. Other encodings are UNDEFINED. For more information see
Conceptual coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

In an implementation that includes EL2, MCR accesses to system control registers can be trapped to Hyp mode,
meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be
permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2
configurable controls on page G1-3909.

Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps.


A1


  31        28 27 26 25 24 23      21 20 19        16 15        12 11          8 7       5 4 3          0
     !=1111     1 1 1 0       opc1     0     CRn            Rt         !=101x       opc2    1    CRm
      cond                                                              coproc


A1 variant

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


Decode for this encoding

 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 t = UInt(Rt);    cp = UInt(coproc);
 if t == 15   then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


A2


  31        28 27 26 25 24 23      21 20 19        16 15        12 11          8 7       5 4 3          0
   1 1 1 1 1 1 1 0            opc1     0     CRn            Rt         !=101x       opc2    1    CRm
      cond                                                              coproc


A2 variant

MCR2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


Decode for this encoding

 if coproc == '101x' then UNDEFINED;
 t = UInt(Rt);    cp = UInt(coproc);
 if t == 15   then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


T1


  15 14 13 12 11 10 9 8 7          5 4 3           0 15         12 11          8 7       5 4 3          0
   1 1 1 0 1 1 1 0            opc1     0     CRn            Rt         !=101x       opc2    1    CRm
                                                                        coproc


T1 variant

MCR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
        Decode for this encoding

         if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
         t = UInt(Rt);   cp = UInt(coproc);
         if t == 15   then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        T2


          15 14 13 12 11 10 9 8 7          5 4 3            0 15       12 11         8 7       5 4 3          0
           1 1 1 1 1 1 1 0            opc1    0      CRn           Rt        !=101x       opc2    1    CRm
                                                                             coproc


        T2 variant

        MCR2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


        Decode for this encoding

         if coproc == '101x' then UNDEFINED;
         t = UInt(Rt);   cp = UInt(coproc);
         if t == 15   then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.

        Advanced SIMD and floating-point: 8, 16, and 32-bit transfers accessing the SIMD and floating-point register file
        on page F5-2606.


        Assembler symbols

        <c>            For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                       For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <coproc>       Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                       p11, p14, and p15.

        <opc1>         Is a coprocessor-specific opcode in the range 0 to 7, encoded in the "opc1" field.

        <Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <CRn>          Is the first coprocessor register, encoded in the "CRn" field.

        <CRm>          Is the second coprocessor register, encoded in the "CRm" field.

        <opc2>         Is a coprocessor-specific opcode in the range 0 to 7, defaulting to 0 and encoded in the "opc2" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             Coproc_CheckInstr(cp, ThisInstr());
             Coproc_SendOneWord(R[t], cp, ThisInstr());


platform: ARM
mnem: MCRR
description:
Move to Coprocessor from two general-purpose registers passes the values of two general-purpose registers to a       (F7.1.105)
conceptual coprocessor.

This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the opc1, and CRm field values that
are valid MCRR and MCRR2 instructions. Other encodings are UNDEFINED. For more information see Conceptual
coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

In an implementation that includes EL2, MCRR accesses to system control registers can be trapped to Hyp mode,
meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be
permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2
configurable controls on page G1-3909.

Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7          4 3         0
     !=1111     1 1 0 0 0 1 0 0              Rt2            Rt         !=101x        opc1        CRm
      cond                                                              coproc


A1 variant

MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


Decode for this encoding

 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 t = UInt(Rt);    t2 = UInt(Rt2);   cp = UInt(coproc);
 if t == 15 || t2 == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7          4 3         0
   1 1 1 1 1 1 0 0 0 1 0 0                   Rt2            Rt         !=101x        opc1        CRm
      cond                                                              coproc


A2 variant

MCRR2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


Decode for this encoding

 if coproc == '101x' then UNDEFINED;
 t = UInt(Rt);    t2 = UInt(Rt2);   cp = UInt(coproc);
 if t == 15 || t2 == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11          8 7          4 3         0
   1 1 1 0 1 1 0 0 0 1 0 0                   Rt2            Rt         !=101x        opc1        CRm
                                                                        coproc
        T1 variant

        MCRR{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


        Decode for this encoding

         if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
         t = UInt(Rt);   t2 = UInt(Rt2);     cp = UInt(coproc);
         if t == 15 || t2 == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11        8 7          4 3          0
           1 1 1 1 1 1 0 0 0 1 0 0                    Rt2           Rt         !=101x        opc1         CRm
                                                                               coproc


        T2 variant

        MCRR2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


        Decode for this encoding

         if coproc == '101x' then UNDEFINED;
         t = UInt(Rt);   t2 = UInt(Rt2);     cp = UInt(coproc);
         if t == 15 || t2 == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.

        Advanced SIMD and floating-point: 64-bit transfers accessing the SIMD and floating-point register file on
        page F5-2607.


        Assembler symbols

        <c>             For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                        For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <coproc>        Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                        p11, p14, and p15.

        <opc1>          Is a coprocessor-specific opcode in the range 0 to 15, encoded in the "opc1" field.

        <Rt>            Is the first general-purpose register to be transferred, encoded in the "Rt" field.

        <Rt2>           Is the second general-purpose register to be transferred, encoded in the "Rt2" field.

        <CRm>           Is a coprocessor register, encoded in the "CRm" field.

        The relative significance of <Rt2> and <Rt> is IMPLEMENTATION DEFINED for IMPLEMENTATION DEFINED uses of the
        MCRR and MRRC instructions. For the architected uses, as described in this manual, <Rt2> transfers bits[63:32] of the
        selected coprocessor register, while <Rt> transfers bits[31:0].
Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    Coproc_CheckInstr(cp, ThisInstr());
    Coproc_SendTwoWords(R[t2], R[t], cp, ThisInstr());


platform: ARM
mnem: MLAS
description:
        Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of       (F7.1.106)
        the result are written to the destination register. These 32 bits do not depend on whether the source register values
        are considered to be signed values or unsigned values.

        In an A32 instruction, the condition flags can optionally be updated based on the result. Use of this option adversely
        affects performance on many implementations.


        A1


          31        28 27 26 25 24 23 22 21 20 19            16 15        12 11       8 7 6 5 4 3                0
             !=1111     0 0 0 0 0 0 1 S                Rd           Ra           Rm      1 0 0 1          Rn
              cond


        Flag setting variant

        Applies when S = 1.

        MLAS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Not flag setting variant

        Applies when S = 0.

        MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);    a = UInt(Ra);   setflags = (S == '1');
         if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11       8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 0 0 0                     Rn         !=1111         Rd      0 0 0 0          Rm
                                                                    Ra


        T1 variant

        MLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for this encoding

         if Ra == '1111' then SEE MUL;
         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);    a = UInt(Ra);   setflags = FALSE;
         if d == 15 || n == 15 || m      == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.
<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

<Ra>          Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = SInt(R[n]);     // operand1 = UInt(R[n]) produces the same final results
    operand2 = SInt(R[m]);     // operand2 = UInt(R[m]) produces the same final results
    addend    = SInt(R[a]);    // addend    = UInt(R[a]) produces the same final results
    result = operand1 * operand2 + addend;
    R[d] = result<31:0>;
    if setflags then
        PSTATE.N = result<31>;
        PSTATE.Z = IsZeroBit(result<31:0>);
        // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: MOVS
description:
        Move (immediate) writes an immediate value to the destination register.       (F7.1.108)

        If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on
        the result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The MOV variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The MOVS variant of the instruction performs an exception return without the use of the stack. In this case:

               --      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                      AArch32 state on page G1-3845.

               --      The instruction is UNDEFINED in Hyp mode.

               --      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


          31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11                                   0
             !=1111     0 0 1 1 1 0 1 S (0) (0) (0) (0)            Rd                     imm12
              cond


        MOV variant

        Applies when S = 0.

        MOV{<c>}{<q>} <Rd>, #<const>


        MOVS variant

        Applies when S = 1.

        MOVS{<c>}{<q>} <Rd>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);    setflags = (S == '1');      (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);


        A2


          31        28 27 26 25 24 23 22 21 20 19          16 15       12 11                                   0
             !=1111     0 0 1 1 0 0 0 0               imm4         Rd                     imm12
              cond


        A2 variant

        MOV{<c>}{<q>} <Rd>, #<imm16>// <imm16> can not be represented in A1
        MOVW{<c>}{<q>} <Rd>, #<imm16>// <imm16> can be represented in A1


        Decode for this encoding

         d = UInt(Rd);    setflags = FALSE;     imm32 = ZeroExtend(imm4:imm12, 32);
         if d == 15 then UNPREDICTABLE;
T1


  15 14 13 12 11 10    8 7                    0
  0 0 1 0 0        Rd             imm8




T1 variant

MOV<c>{<q>} <Rd>, #<imm8>// Inside IT block
MOVS{<q>} <Rd>, #<imm8>// Outside IT block


Decode for this encoding

 d = UInt(Rd);  setflags = !InITBlock();  imm32 = ZeroExtend(imm8, 32);     carry = PSTATE.C;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14              12 11        8 7                      0
  1 1 1 1 0 i 0 0 0 1 0 S 1 1 1 1 0                   imm3         Rd              imm8




MOV variant

Applies when S = 0.

MOV<c>.W <Rd>, #<const>// Inside IT block, and <Rd>, <const> can be represented in T1
MOV{<c>}{<q>} <Rd>, #<const>


MOVS variant

Applies when S = 1.

MOVS.W <Rd>, #<const>// Outside IT block, and <Rd>, <const> can be represented in T1
MOVS{<c>}{<q>} <Rd>, #<const>


Decode for all variants of this encoding

 d = UInt(Rd);  setflags = (S == '1');  (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


T3


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15 14      12 11        8 7                      0
  1 1 1 1 0 i 1 0 0 1 0 0               imm4      0   imm3         Rd              imm8




T3 variant

MOV{<c>}{<q>} <Rd>, #<imm16>// <imm16> cannot be represented in T1 or T2
MOVW{<c>}{<q>} <Rd>, #<imm16>// <imm16> can be represented in T1 or T2


Decode for this encoding

 d = UInt(Rd);  setflags = FALSE;  imm32 = ZeroExtend(imm4:i:imm3:imm8, 32);
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
                       deprecates using the PC as the destination register, but if the PC is used:

                       .      For the MOV variant, the instruction is a branch to the address calculated by the operation.
                              This is an interworking branch, see Pseudocode description of operations on the AArch32
                              general-purpose registers and the PC on page E1-2378.

                       .      For the MOVS variant, the instruction performs an exception return, that restores PSTATE
                              from SPSR_<current_mode>.

                       For encoding A2, T1, T2 and T3: is the general-purpose destination register, encoded in the "Rd"
                       field.

        <imm8>         Is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.

        <imm16>        For encoding A2: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
                       "imm4:imm12" field.

                       For encoding T3: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
                       "imm4:i:imm3:imm8" field.

        <const>        For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
                       page F4-2559 for the range of values.

                       For encoding T2: an immediate value. See Modified immediate constants in T32 instructions on
                       page F3-2530 for the range of values.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             result = imm32;
             if d == 15 then            // Can only occur for encoding A1
                 if setflags then
                      ALUExceptionReturn(result);
                 else
                      ALUWritePC(result);
             else
                 R[d] = result;
                 if setflags then
                      PSTATE.N = result<31>;
                      PSTATE.Z = IsZeroBit(result);
                      PSTATE.C = carry;
                      // PSTATE.V unchanged


platform: ARM
mnem: MOVT
description:
Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents       (F7.1.111)
of the bottom halfword.


A1


  31        28 27 26 25 24 23 22 21 20 19       16 15         12 11                                  0
     !=1111    0 0 1 1 0 1 0 0            imm4           Rd                     imm12
      cond


A1 variant

MOVT{<c>}{<q>} <Rd>, #<imm16>


Decode for this encoding

 d = UInt(Rd);   imm16 = imm4:imm12;
 if d == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14      12 11         8 7                      0
   1 1 1 1 0 i 1 0 1 1 0 0                imm4      0    imm3         Rd               imm8




T1 variant

MOVT{<c>}{<q>} <Rd>, #<imm16>


Decode for this encoding

 d = UInt(Rd);   imm16 = imm4:i:imm3:imm8;
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<imm16>        For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
               "imm4:imm12" field.

               For encoding T1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
               "imm4:i:imm3:imm8" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             R[d]<31:16> = imm16;
             // R[d]<15:0> unchanged


platform: ARM
mnem: MRC
description:
Move to general-purpose register from Coprocessor causes a conceptual coprocessor to transfer a value to a       (F7.1.112)
general-purpose register or to the condition flags.

This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the opc1, opc2, CRn, and CRd field
values that are valid MRC and MRC2 instructions. Other encodings are UNDEFINED. For more information see
Conceptual coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

In an implementation that includes EL2, MRC accesses to system control registers can be trapped to Hyp mode,
meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be
permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2
configurable controls on page G1-3909.

Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps.


A1


  31        28 27 26 25 24 23      21 20 19        16 15        12 11          8 7       5 4 3          0
     !=1111     1 1 1 0       opc1     1     CRn            Rt         !=101x       opc2    1    CRm
      cond                                                              coproc


A1 variant

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


Decode for this encoding

 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 t = UInt(Rt);    cp = UInt(coproc);
 // ARMv8-A removes UNPREDICTABLE for R13


A2


  31        28 27 26 25 24 23      21 20 19        16 15        12 11          8 7       5 4 3          0
   1 1 1 1 1 1 1 0            opc1     1     CRn            Rt         !=101x       opc2    1    CRm
      cond                                                              coproc


A2 variant

MRC2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


Decode for this encoding

 if coproc == '101x' then UNDEFINED;
 t = UInt(Rt);    cp = UInt(coproc);
 // ARMv8-A removes UNPREDICTABLE for R13


T1


  15 14 13 12 11 10 9 8 7          5 4 3           0 15         12 11          8 7       5 4 3          0
   1 1 1 0 1 1 1 0            opc1     1     CRn            Rt         !=101x       opc2    1    CRm
                                                                        coproc


T1 variant

MRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}
        Decode for this encoding

         if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
         t = UInt(Rt);  cp = UInt(coproc);
         // ARMv8-A removes UNPREDICTABLE for R13


        T2


          15 14 13 12 11 10 9 8 7          5 4 3            0 15        12 11         8 7       5 4 3            0
           1 1 1 1 1 1 1 0            opc1    1      CRn           Rt          !=101x     opc2     1     CRm
                                                                               coproc


        T2 variant

        MRC2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <CRn>, <CRm>{, {#}<opc2>}


        Decode for this encoding

         if coproc == '101x' then UNDEFINED;
         t = UInt(Rt);  cp = UInt(coproc);
         // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.

        Advanced SIMD and floating-point: 8, 16, and 32-bit transfers accessing the SIMD and floating-point register file
        on page F5-2606.


        Assembler symbols

        <c>            For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                       For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <coproc>       Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                       p11, p14, and p15.

        <opc1>         Is a coprocessor-specific opcode in the range 0 to 7, encoded in the "opc1" field.

        <Rt>           Is the general-purpose register to be transferred or APSR_nzcv (encoded as 0b1111), encoded in the
                       "Rt" field. If APSR_nzcv is used, bits [31:28] of the transferred value are written to the PSTATE
                       condition flags.

        <CRn>          Is the first coprocessor register, encoded in the "CRn" field.

        <CRm>          Is the second coprocessor register, encoded in the "CRm" field.

        <opc2>         Is a coprocessor-specific opcode in the range 0 to 7, defaulting to 0 and encoded in the "opc2" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             Coproc_CheckInstr(cp, ThisInstr());
             value = Coproc_GetOneWord(cp, ThisInstr());
             if t != 15 then
                 R[t] = value;
             elsif Coproc_CanWriteAPSR(cp, ThisInstr()) then
                 PSTATE.<N,Z,C,V> = value<31:28>;
      // value<27:0> are not used.
   else
      PSTATE.<N,Z,C,V> = bits(4) UNKNOWN;


platform: ARM
mnem: MRRC
description:
        Move to two general-purpose registers from Coprocessor causes a conceptual coprocessor to transfer values to two       (F7.1.113)
        general-purpose registers.

        This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
        one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the opc1, and CRm field values that
        are valid MRRC and MRRC2 instructions. Other encodings are UNDEFINED. For more information see Conceptual
        coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

        In an implementation that includes EL2, MRRC accesses to system control registers can be trapped to Hyp mode,
        meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be
        permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see EL2
        configurable controls on page G1-3909.

        Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7          4 3         0
             !=1111     1 1 0 0 0 1 0 1              Rt2            Rt         !=101x        opc1        CRm
              cond                                                              coproc


        A1 variant

        MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


        Decode for this encoding

         if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
         t = UInt(Rt);    t2 = UInt(Rt2);   cp = UInt(coproc);
         if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        A2


          31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7          4 3         0
           1 1 1 1 1 1 0 0 0 1 0 1                   Rt2            Rt         !=101x        opc1        CRm
              cond                                                              coproc


        A2 variant

        MRRC2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


        Decode for this encoding

         if coproc == '101x' then UNDEFINED;
         t = UInt(Rt);    t2 = UInt(Rt2);   cp = UInt(coproc);
         if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11          8 7          4 3         0
           1 1 1 0 1 1 0 0 0 1 0 1                   Rt2            Rt         !=101x        opc1        CRm
                                                                                coproc
T1 variant

MRRC{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


Decode for this encoding

 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 t = UInt(Rt);   t2 = UInt(Rt2);     cp = UInt(coproc);
 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11        8 7          4 3          0
   1 1 1 1 1 1 0 0 0 1 0 1                    Rt2           Rt         !=101x        opc1         CRm
                                                                       coproc


T2 variant

MRRC2{<c>}{<q>} <coproc>, {#}<opc1>, <Rt>, <Rt2>, <CRm>


Decode for this encoding

 if coproc == '101x' then UNDEFINED;
 t = UInt(Rt);   t2 = UInt(Rt2);     cp = UInt(coproc);
 if t == 15 || t2 == 15 || t == t2 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

Advanced SIMD and floating-point: 64-bit transfers accessing the SIMD and floating-point register file on
page F5-2607.


Assembler symbols

<c>             For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

                For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

<q>             See Standard assembler syntax fields on page F2-2506.

<coproc>        Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                p11, p14, and p15.

<opc1>          Is a coprocessor-specific opcode in the range 0 to 15, encoded in the "opc1" field.

<Rt>            Is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>           Is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<CRm>           Is a coprocessor register, encoded in the "CRm" field.

The relative significance of <Rt2> and {syntax{<Rt>} is IMPLEMENTATION DEFINED for IMPLEMENTATION DEFINED
uses of the MCRR and MRRC instructions. For the architected uses, as described in this manual, <Rt2> transfers
bits[63:32] of the selected coprocessor register, while <Rt> transfers bits[31:0].


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     Coproc_CheckInstr(cp, ThisInstr());
     (R[t2], R[t]) = Coproc_GetTwoWords(cp, ThisInstr());


platform: ARM
mnem: MULS
description:
        Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination       (F7.1.119)
        register. These 32 bits do not depend on whether the source register values are considered to be signed values or
        unsigned values.

        Optionally, it can update the condition flags based on the result. In the T32 instruction set, this option is limited to
        only a few forms of the instruction. Use of this option adversely affects performance on many implementations.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15 14 13 12 11           8 7 6 5 4 3                0
             !=1111     0 0 0 0 0 0 0 S               Rd     (0) (0) (0) (0)    Rm       1 0 0 1            Rn
              cond


        Flag setting variant

        Applies when S = 1.

        MULS{<c>}{<q>} <Rd>, <Rn>{, <Rm>}


        Not flag setting variant

        Applies when S = 0.

        MUL{<c>}{<q>} <Rd>, <Rn>{, <Rm>}


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);   setflags = (S == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5             3 2      0
           0 1 0 0 0 0 1 1 0 1               Rn       Rdm




        T1 variant

        MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>}// Inside IT block
        MULS{<q>} <Rdm>, <Rn>{, <Rdm>}// Outside IT block


        Decode for this encoding

         d = UInt(Rdm);    n = UInt(Rn);   m = UInt(Rdm);    setflags = !InITBlock();


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11           8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 0 0 0                    Rn      1 1 1 1           Rd       0 0 0 0           Rm




        T2 variant

        MUL<c>.W <Rd>, <Rn>{, <Rm>}// Inside IT block, and <Rd>, <Rn>, <Rm> can be represented in T1
        MUL{<c>}{<q>} <Rd>, <Rn>{, <Rm>}
Decode for this encoding

 d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);  setflags = FALSE;
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rdm>          Is the second general-purpose source register holding the multiplier and the destination register,
               encoded in the "Rdm" field.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field. If
               omitted, <Rd> is used.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand1 = SInt(R[n]);     // operand1 = UInt(R[n]) produces the same final results
     operand2 = SInt(R[m]);     // operand2 = UInt(R[m]) produces the same final results
     result = operand1 * operand2;
     R[d] = result<31:0>;
     if setflags then
         PSTATE.N = result<31>;
         PSTATE.Z = IsZeroBit(result<31:0>);
         // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: MVNS
description:
        Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register.       (F7.1.120)

        If the destination register is not the PC, the MVNS variant of the instruction updates the condition flags based on
        the result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The MVN variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The MVNS variant of the instruction performs an exception return without the use of the stack. In this case:

               --      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                      AArch32 state on page G1-3845.

               --      The instruction is UNDEFINED in Hyp mode.

               --      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


          31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11                                   0
             !=1111     0 0 1 1 1 1 1 S (0) (0) (0) (0)            Rd                     imm12
              cond


        MVN variant

        Applies when S = 0.

        MVN{<c>}{<q>} <Rd>, #<const>


        MVNS variant

        Applies when S = 1.

        MVNS{<c>}{<q>} <Rd>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);    setflags = (S == '1');
         (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                  12 11         8 7                       0
           1 1 1 1 0        i  0 0 0 1 1 S 1 1 1 1 0                imm3        Rd               imm8




        MVN variant

        Applies when S = 0.

        MVN{<c>}{<q>} <Rd>, #<const>


        MVNS variant

        Applies when S = 1.

        MVNS{<c>}{<q>} <Rd>, #<const>
Decode for all variants of this encoding

 d = UInt(Rd);   setflags = (S == '1');
 (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
               deprecates using the PC as the destination register, but if the PC is used:

               .     For the MVN variant, the instruction is a branch to the address calculated by the operation.
                     This is an interworking branch, see Pseudocode description of operations on the AArch32
                     general-purpose registers and the PC on page E1-2378.

               .     For the MVNS variant, the instruction performs an exception return, that restores PSTATE
                     from SPSR_<current_mode>.

               For encoding T1: is the general-purpose destination register, encoded in the "Rd" field.

<const>        For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
               page F4-2559 for the range of values.

               For encoding T1: an immediate value. See Modified immediate constants in T32 instructions on
               page F3-2530 for the range of values.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     result = NOT(imm32);
     if d == 15 then           // Can only occur for A32 encoding
         if setflags then
              ALUExceptionReturn(result);
         else
              ALUWritePC(result);
     else
         R[d] = result;
         if setflags then
              PSTATE.N = result<31>;
              PSTATE.Z = IsZeroBit(result);
              PSTATE.C = carry;
              // PSTATE.V unchanged


platform: ARM
mnem: ORNS
description:
Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an       (F7.1.124)
immediate value, and writes the result to the destination register. It can optionally update the condition flags based
on the result.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14      12 11          8 7                      0
  1 1 1 1 0 i 0 0 0 1 1 S                  !=1111      0   imm3          Rd                imm8
                                             Rn


Flag setting variant

Applies when S = 1.

ORNS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


Not flag setting variant

Applies when S = 0.

ORN{<c>}{<q>} {<Rd>,} <Rn>, #<const>


Decode for all variants of this encoding

 if Rn == '1111' then SEE MVN (immediate);
 d = UInt(Rd);  n = UInt(Rn);    setflags = (S == '1');
 (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the
               same as <Rn>.

<Rn>           Is the general-purpose source register, encoded in the "Rn" field.

<const>        An immediate value. See Modified immediate constants in T32 instructions on page F3-2530 for the
               range of values.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     result = R[n] OR NOT(imm32);
     R[d] = result;
     if setflags then
         PSTATE.N = result<31>;
         PSTATE.Z = IsZeroBit(result);
         PSTATE.C = carry;
         // PSTATE.V unchanged


platform: ARM
mnem: ORRS
description:
        Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes       (F7.1.126)
        the result to the destination register.

        If the destination register is not the PC, the ORRS variant of the instruction updates the condition flags based on the
        result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The ORR variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The ORRS variant of the instruction performs an exception return without the use of the stack. In this case:

               --       The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --       The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                       AArch32 state on page G1-3845.

               --       The instruction is UNDEFINED in Hyp mode.

               --       The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


           31       28 27 26 25 24 23 22 21 20 19            16 15       12 11                                   0
             !=1111     0 0 1 1 1 0 0 S                 Rn          Rd                      imm12
               cond


        ORR variant

        Applies when S = 0.

        ORR{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        ORRS variant

        Applies when S = 1.

        ORRS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);     n = UInt(Rn);     setflags = (S == '1');
         (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14     12 11         8 7                       0
           1 1 1 1 0 i 0 0 0 1 0 S                     !=1111    0   imm3        Rd                 imm8
                                                        Rn


        ORR variant

        Applies when S = 0.

        ORR{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        ORRS variant

        Applies when S = 1.
ORRS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


Decode for all variants of this encoding

 if Rn == '1111' then SEE MOV (immediate);
 d = UInt(Rd);   n = UInt(Rn);     setflags = (S == '1');
 (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if d == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted,
               this register is the same as <Rn>. ARM deprecates using the PC as the destination register, but if the
               PC is used:

               .      For the ORR variant, the instruction is a branch to the address calculated by the operation.
                      This is an interworking branch, see Pseudocode description of operations on the AArch32
                      general-purpose registers and the PC on page E1-2378.

               .      For the ORRS variant, the instruction performs an exception return, that restores PSTATE
                      from SPSR_<current_mode>.

               For encoding T1: is the general-purpose destination register, encoded in the "Rd" field. If omitted,
               this register is the same as <Rn>.

<Rn>           For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be
               used.

               For encoding T1: is the general-purpose source register, encoded in the "Rn" field.

<const>        For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
               page F4-2559 for the range of values.

               For encoding T1: an immediate value. See Modified immediate constants in T32 instructions on
               page F3-2530 for the range of values.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     result = R[n] OR imm32;
     if d == 15 then              // Can only occur for A32 encoding
         if setflags then
              ALUExceptionReturn(result);
         else
              ALUWritePC(result);
     else
         R[d] = result;
         if setflags then
              PSTATE.N = result<31>;
              PSTATE.Z = IsZeroBit(result);
              PSTATE.C = carry;
              // PSTATE.V unchanged


platform: ARM
mnem: PKHBT
description:
        Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand.       (F7.1.129)


        A1


          31       28 27 26 25 24 23 22 21 20 19         16 15       12 11           7 6 5 4 3              0
             !=1111   0 1 1 0 1 0 0 0                 Rn         Rd          imm5      tb 0 1         Rm
              cond


        PKHBT variant

        Applies when tb = 0.

        PKHBT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, LSL #<imm>}


        PKHTB variant

        Applies when tb = 1.

        PKHTB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ASR #<imm>}


        Decode for all variants of this encoding

         d = UInt(Rd);  n = UInt(Rn);    m = UInt(Rm);   tbform = (tb == '1');
         (shift_t, shift_n) = DecodeImmShift(tb:'0', imm5);
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14     12 11       8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 1 1 0 0                    Rn     (0)  imm3      Rd      imm2 tb 0         Rm
                                              S                                               T


        PKHBT variant

        Applies when tb = 0.

        PKHBT{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, LSL #<imm>}// tbform == FALSE


        PKHTB variant

        Applies when tb = 1.

        PKHTB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ASR #<imm>}// tbform == TRUE


        Decode for all variants of this encoding

         if S == '1' || T == '1' then UNDEFINED;
         d = UInt(Rd);  n = UInt(Rn);    m = UInt(Rm);   tbform = (tb == '1');
         (shift_t, shift_n) = DecodeImmShift(tb:'0', imm3:imm2);
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register, encoded in the "Rm" field.

<imm>         For encoding A1: the shift to apply to the value read from <Rm>, encoded in imm5. Is one of:

              omitted      No shift, encoded as 0b00000.

              1-31         Left shift by specified number of bits, encoded as a binary number.

              For encoding A1: the shift to apply to the value read from <Rm>, encoded in imm5. Is one of:

              omitted      Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>,
                           <Rm>, <Rn> had been written.

              1-32         Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as
                           0b00000. Other shift amounts are encoded as binary numbers.

                        Note
              An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not
              standard UAL and must not be used for disassembly.


              For encoding T1: the shift to apply to the value read from <Rm>, encoded in imm3:imm2. For PKHBT,
              it is one of:

              omitted      No shift, encoded as 0b00000.

              1-31         Left shift by specified number of bits, encoded as a binary number.

               For PKHTB, it is one of:

              omitted      Instruction is a pseudo-instruction and is assembled as though PKHBT{<c>}{<q>} <Rd>,
                           <Rm>, <Rn> had been written.

              1-32         Arithmetic right shift by specified number of bits. A shift by 32 bits is encoded as
                           0b00000. Other shift amounts are encoded as binary numbers.

                        Note
              An assembler can permit <imm> = 0 to mean the same thing as omitting the shift, but this is not
              standard UAL and must not be used for disassembly.



Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = Shift(R[m], shift_t, shift_n, PSTATE.C);        // PSTATE.C ignored
    R[d]<15:0>   = if tbform then operand2<15:0> else R[n]<15:0>;
    R[d]<31:16> = if tbform then R[n]<31:16>         else operand2<31:16>;


platform: ARM
mnem: PLD
description:
        Preload Data (immediate) signals the memory system that data memory accesses from a specified address are likely       (F7.1.130)
        in the near future. The memory system can respond by taking actions that are expected to speed up the memory
        accesses when they do occur, such as preloading the cache line containing the specified address into the data cache.

        The PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write.

        The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches
        on page E2-2425.


        A1


          31 30 29 28 27 26 25 24 23 22 21 20 19           16 15 14 13 12 11                                    0
           1 1 1 1 0 1 0 1 U R 0 1                   !=1111   (1) (1) (1) (1)              imm12
                                                      Rn


        Preload read variant

        Applies when R = 1.

        PLD{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]


        Preload write variant

        Applies when R = 0.

        PLDW{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]


        Decode for all variants of this encoding

         if Rn == '1111' then SEE PLD (literal);
         n = UInt(Rn);    imm32 = ZeroExtend(imm12, 32);     add = (U == '1');     is_pldw = (R == '0');


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11                                     0
           1 1 1 1 1 0 0 0 1 0 W 1                   !=1111    1 1 1 1                     imm12
                                                      Rn


        Preload read variant

        Applies when W = 0.

        PLD{<c>}{<q>} [<Rn> {, #{+}<imm>}]


        Preload write variant

        Applies when W = 1.

        PLDW{<c>}{<q>} [<Rn> {, #{+}<imm>}]


        Decode for all variants of this encoding

         if Rn == '1111' then SEE PLD (literal);
         n = UInt(Rn);    imm32 = ZeroExtend(imm12, 32);     add = TRUE;     is_pldw = (W == '1');
T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11 10 9 8 7                            0
  1 1 1 1 1 0 0 0 0 0 W 1                  !=1111     1 1 1 1 1 1 0 0                    imm8
                                             Rn


Preload read variant

Applies when W = 0.

PLD{<c>}{<q>} [<Rn> {, #-<imm>}]


Preload write variant

Applies when W = 1.

PLDW{<c>}{<q>} [<Rn> {, #-<imm>}]


Decode for all variants of this encoding

 if Rn == '1111' then SEE PLD (literal);
 n = UInt(Rn);  imm32 = ZeroExtend(imm8, 32);       add = FALSE;   is_pldw = (W == '1');


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            For encoding A1: see Standard assembler syntax fields on page F2-2506. Must be AL or omitted.

               For encoding T1 and T2: see Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field. If the PC is used, see PLD (literal).

+/-            Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
               encoded in the "U" field. It can have the following values:

               -           when U = 0

               +           when U = 1

+              Specifies the offset is added to the base register.

<imm>          For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
               defaulting to 0 and encoded in the "imm12" field.

               For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
               defaulting to 0 and encoded in the "imm12" field.

               For encoding T2: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
               defaulting to 0 and encoded in the "imm8" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = if add then (R[n] + imm32) else (R[n] - imm32);
     if is_pldw then
         Hint_PreloadDataForWrite(address);
     else
         Hint_PreloadData(address);


platform: ARM
mnem: PLI
description:
        Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely       (F7.1.133)
        in the near future. The memory system can respond by taking actions that are expected to speed up the memory
        accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction
        cache.

        The effect of a PLI instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on
        page E2-2425.


        A1


          31 30 29 28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11                                    0
           1 1 1 1 0 1 0 0 U 1 0 1                    Rn      (1) (1) (1) (1)            imm12




        A1 variant

        PLI{<c>}{<q>} [<Rn> {, #{+/-}<imm>}]
        PLI{<c>}{<q>} <label>// Normal form
        PLI{<c>}{<q>} [PC, #{+/-}<imm>]// Alternative form


        Decode for this encoding

         n = UInt(Rn);    imm32 = ZeroExtend(imm12, 32);     add = (U == '1');


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11                                     0
           1 1 1 1 1 0 0 1 1 0 0 1                  !=1111     1 1 1 1                   imm12
                                                      Rn


        T1 variant

        PLI{<c>}{<q>} [<Rn> {, #{+}<imm>}]


        Decode for this encoding

         if Rn == '1111' then SEE encoding T3;
         n = UInt(Rn);    imm32 = ZeroExtend(imm12, 32);     add = TRUE;


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11 10 9 8 7                            0
           1 1 1 1 1 0 0 1 0 0 0 1                  !=1111     1 1 1 1 1 1 0 0                   imm8
                                                      Rn


        T2 variant

        PLI{<c>}{<q>} [<Rn> {, #-<imm>}]


        Decode for this encoding

         if Rn == '1111' then SEE encoding T3;
         n = UInt(Rn);    imm32 = ZeroExtend(imm8, 32);    add = FALSE;
T3


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11                                                     0
   1 1 1 1 1 0 0 1 U 0 0 1 1 1 1 1 1 1 1 1                                            imm12




T3 variant

PLI{<c>}{<q>} <label>// Preferred syntax
PLI{<c>}{<q>} [PC, #{+/-}<imm>]// Alternative syntax


Decode for this encoding

 n = 15;   imm32 = ZeroExtend(imm12, 32);       add = (U == '1');


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>              For encoding A1: see Standard assembler syntax fields on page F2-2506. Must be AL or omitted.

                 For encoding T1, T2 and T3: see Standard assembler syntax fields on page F2-2506.

<q>              See Standard assembler syntax fields on page F2-2506.

<label>          The label of the instruction that is likely to be accessed in the near future. The assembler calculates
                 the required value of the offset from the Align(PC, 4) value of the instruction to this label. The offset
                 must be in the range 4095 to 4095. If the offset is zero or positive, imm32 is equal to the offset and
                 add == TRUE. If the offset is negative, imm32 is equal to minus the offset and add == FALSE.

<Rn>             Is the general-purpose base register, encoded in the "Rn" field.

+/-              Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
                 encoded in the "U" field. It can have the following values:

                 -            when U = 0

                 +            when U = 1

+                Specifies the offset is added to the base register.

<imm>            For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
                 defaulting to 0 and encoded in the "imm12" field.

                 For encoding T1: is an optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
                 defaulting to 0 and encoded in the "imm12" field.

                 For encoding T2: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                 defaulting to 0 and encoded in the "imm8" field.

                 For encoding T3: is a 12-bit unsigned immediate byte offset, in the range 0 to 4095, encoded in the
                 "imm12" field.

For the literal forms of the instruction, encoding T3 is used, or Rn is encoded as 0b1111 in encoding A1, to indicate
that the PC is the base register.

The alternative literal syntax permits the addition or subtraction of the offset and the immediate offset to be specified
separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more
information, see Use of labels in UAL instruction syntax on page F1-2469.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             base = if n == 15 then Align(PC,4) else R[n];
             address = if add then (base + imm32) else (base - imm32);
             Hint_PreloadInstr(address);


platform: ARM
mnem: POP
description:
Pop Multiple Registers from Stack loads multiple general-purpose registers from the stack, loading from       (F7.1.135)
consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data.

The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
page F2-2514.

The registers loaded can include the PC, causing a branch to a loaded address. This is an interworking branch, see
Pseudocode description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.


T1


  15 14 13 12 11 10 9 8 7                               0
  1 0 1 1 1 1 0 P                   register_list




T1 variant

POP{<c>}{<q>} <registers>// Preferred syntax
LDM{<c>}{<q>} SP!, <registers>// Alternate syntax


Decode for this encoding

 registers = P:'0000000':register_list;           UnalignedAllowed = FALSE;
 if BitCount(registers) < 1 then UNPREDICTABLE;
 if registers<15> == '1' && InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly POP (T32) on page J1-5351 and POP
(A32) on page J1-5352.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<registers>     Is a list of one or more registers to be loaded, separated by commas and surrounded by { and }. The
                registers in the list must be in the range R0-R7, encoded in the "register_list" field, and can
                optionally include the PC. If the PC is in the list, the "P" field is set to 1, otherwise this field defaults
                to 0. If the PC is in the list, the instruction must be either outside any IT block, or the last instruction
                in an IT block.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = SP;
     for i = 0 to 14
         if registers<i> == '1' then
              R[i] = if UnalignedAllowed then MemU[address,4] else MemA[address,4];
              address = address + 4;
     if registers<15> == '1' then
         if UnalignedAllowed then
              if address<1:0> == '00' then
                   LoadWritePC(MemU[address,4]);
              else
                         UNPREDICTABLE;
                 else
                     LoadWritePC(MemA[address,4]);
             if registers<13> == '0' then SP = SP + 4*BitCount(registers);
             if registers<13> == '1' then SP = bits(32) UNKNOWN;


platform: ARM
mnem: PUSH
description:
Push Multiple Registers to Stack stores multiple general-purpose registers to the stack, storing to consecutive       (F7.1.138)
memory locations ending just below the address in SP, and updates SP to point to the start of the stored data.

The lowest-numbered register is stored to the lowest memory address, through to the highest-numbered register to
the highest memory address. See also Encoding of lists of general-purpose registers and the PC on page F2-2514.


T1


  15 14 13 12 11 10 9 8 7                           0
  1 0 1 1 0 1 0 M                  register_list




T1 variant

PUSH{<c>}{<q>} <registers>// Preferred syntax
STMDB{<c>}{<q>} SP!, <registers>// Alternate syntax


Decode for this encoding

 registers = '0':M:'000000':register_list;       UnalignedAllowed = FALSE;
 if BitCount(registers) < 1 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly PUSH on page J1-5353.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<registers>    Is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The
               registers in the list must be in the range R0-R7, encoded in the "register_list" field, and can
               optionally include the LR. If the LR is in the list, the "M" field is set to 1, otherwise this field defaults
               to 0.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = SP - 4*BitCount(registers);
     for i = 0 to 14
         if registers<i> == '1' then
              if i == 13 && i != LowestSetBit(registers) then           // Only possible for encoding A1
                  MemA[address,4] = bits(32) UNKNOWN;
              else
                  if UnalignedAllowed then
                       MemU[address,4] = R[i];
                  else
                       MemA[address,4] = R[i];
              address = address + 4;
     if registers<15> == '1' then      // Only possible for encoding A1 or A2
         if UnalignedAllowed then
              MemU[address,4] = PCStoreValue();
         else
              MemA[address,4] = PCStoreValue();
     SP = SP - 4*BitCount(registers);


platform: ARM
mnem: QADD
description:
Saturating Add adds two register values, saturates the result to the 32-bit signed integer range -231 to (231 - 1), and       (F7.1.141)
writes the result to the destination register. If saturation occurs, it sets PSTATE.Q to 1.


A1


  31        28 27 26 25 24 23 22 21 20 19             16 15       12 11 10 9 8 7 6 5 4 3                  0
     !=1111     0 0 0 1 0 0 0 0                 Rn            Rd       (0) (0) (0) (0) 0 1 0 1      Rm
      cond


A1 variant

QADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15 14 13 12 11              8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 0 0 0                       Rn        1 1 1 1           Rd         1 0 0 0      Rm




T1 variant

QADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>            Is the first general-purpose source register, encoded in the "Rm" field.

<Rn>            Is the second general-purpose source register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     (R[d], sat) = SignedSatQ(SInt(R[m]) + SInt(R[n]), 32);
     if sat then
         PSTATE.Q = '1';


platform: ARM
mnem: QADD16
description:
     Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range -215       (F7.1.142)
     <= x <= 215 - 1, and writes the results to the destination register.


     A1


       31       28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                 0
          !=1111    0 1 1 0 0 0 1 0                 Rn           Rd      (1) (1) (1) (1) 0 0 0 1       Rm
           cond


     A1 variant

     QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 0 0 1                     Rn       1 1 1 1          Rd        0 0 0 1        Rm




     T1 variant

     QADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>            See Standard assembler syntax fields on page F2-2506.

     <q>            See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);
sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);
R[d]<15:0>  = SignedSat(sum1, 16);
R[d]<31:16> = SignedSat(sum2, 16);


platform: ARM
mnem: QADD8
description:
     Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range -27 <=       (F7.1.143)
     x <= 27 - 1, and writes the results to the destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
          !=1111    0 1 1 0 0 0 1 0                 Rn           Rd     (1) (1) (1) (1) 1 0 0 1         Rm
           cond


     A1 variant

     QADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11           8 7 6 5 4 3             0
        1 1 1 1 1 0 1 0 1 0 0 0                     Rn       1 1 1 1         Rd        0 0 0 1          Rm




     T1 variant

     QADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);
          sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);
          sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);
sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);
R[d]<7:0>   = SignedSat(sum1, 8);
R[d]<15:8>  = SignedSat(sum2, 8);
R[d]<23:16> = SignedSat(sum3, 8);
R[d]<31:24> = SignedSat(sum4, 8);


platform: ARM
mnem: QASX
description:
     Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.144)
     16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range -215 <= x
     <= 215 - 1, and writes the results to the destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                   0
          !=1111     0 1 1 0 0 0 1 0                Rn           Rd     (1) (1) (1) (1) 0 0 1 1         Rm
           cond


     A1 variant

     QASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3              0
        1 1 1 1 1 0 1 0 1 0 1 0                     Rn       1 1 1 1         Rd        0 0 0 1          Rm




     T1 variant

     QASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff = SInt(R[n]<15:0>) - SInt(R[m]<31:16>);
sum  = SInt(R[n]<31:16>) + SInt(R[m]<15:0>);
R[d]<15:0>  = SignedSat(diff, 16);
R[d]<31:16> = SignedSat(sum, 16);


platform: ARM
mnem: QDADD
description:
     Saturating Double and Add adds a doubled register value to another register value, and writes the result to the       (F7.1.145)
     destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range
     -231 <= x <= 231 - 1. If saturation occurs in either operation, it sets PSTATE.Q to 1.


     A1


       31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                  0
          !=1111     0 0 0 1 0 1 0 0               Rn            Rd       (0) (0) (0) (0) 0 1 0 1        Rm
           cond


     A1 variant

     QDADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3             0
        1 1 1 1 1 0 1 0 1 0 0 0                    Rn       1 1 1 1            Rd         1 0 0 1        Rm




     T1 variant

     QDADD{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rm>            Is the first general-purpose source register, encoded in the "Rm" field.

     <Rn>            Is the second general-purpose source register, encoded in the "Rn" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          (doubled, sat1) = SignedSatQ(2 * SInt(R[n]), 32);
(R[d], sat2)  = SignedSatQ(SInt(R[m]) + SInt(doubled), 32);
if sat1 || sat2 then
   PSTATE.Q = '1';


platform: ARM
mnem: QDSUB
description:
     Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result       (F7.1.146)
     to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed
     integer range -231 <= x <= 231 - 1. If saturation occurs in either operation, it sets PSTATE.Q to 1.


     A1


       31        28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                  0
          !=1111     0 0 0 1 0 1 1 0                Rn          Rd       (0) (0) (0) (0) 0 1 0 1        Rm
           cond


     A1 variant

     QDSUB{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 0 0 0                     Rn      1 1 1 1           Rd         1 0 1 1        Rm




     T1 variant

     QDSUB{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rm>            Is the first general-purpose source register, encoded in the "Rm" field.

     <Rn>            Is the second general-purpose source register, encoded in the "Rn" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          (doubled, sat1) = SignedSatQ(2 * SInt(R[n]), 32);
(R[d], sat2)  = SignedSatQ(SInt(R[m]) - SInt(doubled), 32);
if sat1 || sat2 then
   PSTATE.Q = '1';


platform: ARM
mnem: QSAX
description:
     Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.147)
     16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range -215 <= x
     <= 215 - 1, and writes the results to the destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                   0
          !=1111     0 1 1 0 0 0 1 0                Rn           Rd     (1) (1) (1) (1) 0 1 0 1         Rm
           cond


     A1 variant

     QSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3              0
        1 1 1 1 1 0 1 0 1 1 1 0                     Rn       1 1 1 1         Rd        0 0 0 1          Rm




     T1 variant

     QSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum   = SInt(R[n]<15:0>) + SInt(R[m]<31:16>);
diff = SInt(R[n]<31:16>) - SInt(R[m]<15:0>);
R[d]<15:0>  = SignedSat(sum, 16);
R[d]<31:16> = SignedSat(diff, 16);


platform: ARM
mnem: QSUB
description:
        Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed       (F7.1.148)
        integer range -231 <= x <= 231 - 1, and writes the result to the destination register. If saturation occurs, it sets
        PSTATE.Q to 1.


        A1


          31       28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                   0
             !=1111    0 0 0 1 0 0 1 0                Rn           Rd      (0) (0) (0) (0) 0 1 0 1          Rm
              cond


        A1 variant

        QSUB{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


        Decode for this encoding

         d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3               0
           1 1 1 1 1 0 1 0 1 0 0 0                    Rn      1 1 1 1            Rd        1 0 1 0          Rm




        T1 variant

        QSUB{<c>}{<q>} {<Rd>,} <Rm>, <Rn>


        Decode for this encoding

         d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>           Is the first general-purpose source register, encoded in the "Rm" field.

        <Rn>           Is the second general-purpose source register, encoded in the "Rn" field.
Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    (R[d], sat) = SignedSatQ(SInt(R[m]) - SInt(R[n]), 32);
    if sat then
        PSTATE.Q = '1';


platform: ARM
mnem: QSUB16
description:
     Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer       (F7.1.149)
     range -215 <= x <= 215 - 1, and writes the results to the destination register.


     A1


       31       28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                  0
          !=1111   0 1 1 0 0 0 1 0                 Rn           Rd       (1) (1) (1) (1) 0 1 1 1      Rm
           cond


     A1 variant

     QSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 1 0 1                    Rn       1 1 1 1           Rd        0 0 0 1       Rm




     T1 variant

     QSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>            See Standard assembler syntax fields on page F2-2506.

     <q>            See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff1 = SInt(R[n]<15:0>) - SInt(R[m]<15:0>);
diff2 = SInt(R[n]<31:16>) - SInt(R[m]<31:16>);
R[d]<15:0>  = SignedSat(diff1, 16);
R[d]<31:16> = SignedSat(diff2, 16);


platform: ARM
mnem: QSUB8
description:
     Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range       (F7.1.150)
     -27 <= x <= 27 - 1, and writes the results to the destination register.


     A1


       31       28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                  0
          !=1111    0 1 1 0 0 0 1 0                 Rn           Rd      (1) (1) (1) (1) 1 1 1 1         Rm
           cond


     A1 variant

     QSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3             0
        1 1 1 1 1 0 1 0 1 1 0 0                     Rn       1 1 1 1          Rd        0 0 0 1          Rm




     T1 variant

     QSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>            See Standard assembler syntax fields on page F2-2506.

     <q>            See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff1 = SInt(R[n]<7:0>) - SInt(R[m]<7:0>);
          diff2 = SInt(R[n]<15:8>) - SInt(R[m]<15:8>);
          diff3 = SInt(R[n]<23:16>) - SInt(R[m]<23:16>);
diff4 = SInt(R[n]<31:24>) - SInt(R[m]<31:24>);
R[d]<7:0>   = SignedSat(diff1, 8);
R[d]<15:8>  = SignedSat(diff2, 8);
R[d]<23:16> = SignedSat(diff3, 8);
R[d]<31:24> = SignedSat(diff4, 8);


platform: ARM
mnem: REVSH
description:
        Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and       (F7.1.154)
        sign-extends the result to 32 bits.


        A1


          31       28 27 26 25 24 23 22 21 20 19 18 17 16 15        12 11 10 9 8 7 6 5 4 3                 0
             !=1111    0 1 1 0 1 1 1 1 (1) (1) (1) (1)           Rd     (1) (1) (1) (1) 1 0 1 1      Rn
              cond


        A1 variant

        REVSH{<c>}{<q>} <Rd>, <Rm>


        Decode for this encoding

         d = UInt(Rd);   m = UInt(Rm);
         if d == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5            3 2     0
           1 0 1 1 1 0 1 0 1 1               Rs        Rd




        T1 variant

        REVSH{<c>}{<q>} <Rd>, <Rm>


        Decode for this encoding

         d = UInt(Rd);   m = UInt(Rm);


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14 13 12 11            8 7 6 5 4 3           0
           1 1 1 1 1 0 1 0 1 0 0 1                   Rm       1 1 1 1        Rd         1 0 1 1      Rm




        T2 variant

        REVSH{<c>}.W <Rd>, <Rm>// <Rd>, <Rm> can be represented in T1
        REVSH{<c>}{<q>} <Rd>, <Rm>


        Decode for this encoding

         if !Consistent(Rm) then UNPREDICTABLE;
         d = UInt(Rd);   m = UInt(Rm);
         if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly REVSH on page J1-5355.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>          For encoding A1 and T1: is the general-purpose source register, encoded in the "Rm" field.

              For encoding T2: is the general-purpose source register, encoded in the "Rm" field. Its number must
              be encoded twice.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    bits(32) result;
    result<31:8>   = SignExtend(R[m]<7:0>, 24);
    result<7:0>    = R[m]<15:8>;
    R[d] = result;


platform: ARM
mnem: RFE
description:
        Return From Exception loads two consecutive memory locations using an address in a base register:       (F7.1.155)

        .      The word loaded from the lower address is treated as an instruction address. The PE branches to it.

        .      The word loaded from the higher address is used to restore PSTATE. This word must be in the format of an
               SPSR.

        An address adjusted by the size of the data loaded can optionally be written back to the base register.

        The PE checks the value of the word loaded from the higher address for an illegal return event. See Illegal return
        events from AArch32 state on page G1-3845.

        RFE is UNDEFINED in Hyp mode and CONSTRAINED UNPREDICTABLE in User mode.


        A1


          31 30 29 28 27 26 25 24 23 22 21 20 19         16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
           1 1 1 1 1 0 0 P U 0 W 1                    Rn     (0) (0) (0) (0) (1) (0) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0)




        Decrement After variant

        Applies when P = 0 && U = 0.

        RFEDA{<c>}{<q>} <Rn>{!}


        Decrement Before variant

        Applies when P = 1 && U = 0.

        RFEDB{<c>}{<q>} <Rn>{!}


        Increment After variant

        Applies when P = 0 && U = 1.

        RFE{IA}{<c>}{<q>} <Rn>{!}


        Increment Before variant

        Applies when P = 1 && U = 1.

        RFEIB{<c>}{<q>} <Rn>{!}


        Decode for all variants of this encoding

         n = UInt(Rn);
         wback = (W == '1');   increment = (U == '1');     wordhigher = (P == U);
         if n == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
           1 1 1 0 1 0 0 0 0 0 W 1                    Rn     (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)




        T1 variant

        RFEDB{<c>}{<q>} <Rn>{!}// Outside or last in IT block
Decode for this encoding

 n = UInt(Rn);    wback = (W == '1');   increment = FALSE;       wordhigher = FALSE;
 if n == 15 then UNPREDICTABLE;
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  1 1 1 0 1 0 0 1 1 0 W 1                    Rn       (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)




T2 variant

RFE{IA}{<c>}{<q>} <Rn>{!}// Outside or last in IT block


Decode for this encoding

 n = UInt(Rn);    wback = (W == '1');   increment = TRUE;      wordhigher = FALSE;
 if n == 15 then UNPREDICTABLE;
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly RFE on page J1-5381.


Assembler symbols

IA              For encoding A1: is an optional suffix to indicate the Increment After variant.

                For encoding T2: is an optional suffix for the Increment After form.

<c>             For encoding A1: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

                For encoding T1 and T2: see Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

!               The address adjusted by the size of the data loaded is written back to the base register. If specified,
                it is encoded in the "W" field as 1, otherwise this field defaults to 0.

RFEFA, RFEEA, RFEFD, and RFEED are pseudo-instructions for RFEDA, RFEDB, RFEIA, and RFEIB respectively, referring to
their use for popping data from Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      if PSTATE.EL == EL2 then
          UNDEFINED;
      elsif PSTATE.EL == EL0 then
          UNPREDICTABLE;                             // UNDEFINED or NOP
      else
          address = if increment then R[n] else R[n]-8;
          if wordhigher then address = address+4;
          new_pc_value = MemA[address,4];
          spsr = MemA[address+4,4];
          if wback then R[n] = if increment then R[n]+8 else R[n]-8;
          AArch32.ExceptionReturn(new_pc_value, spsr);


platform: ARM
mnem: RORS
description:
        Rotate Right, setting flags (immediate) provides the value of the contents of a register rotated by a constant value.       (F7.1.158)
        The bits that are rotated off the right end are inserted into the vacated bit positions on the left.

        If the destination register is not the PC, this instruction updates the condition flags based on the result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

        .      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32
               state on page G1-3845.

        .      The instruction is UNDEFINED in Hyp mode.

        .      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.

        This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

        .      The encodings in this description are named to match the encodings of MOV, MOVS (register).

        .      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


        A1


          31        28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11             7 6 5 4 3            0
             !=1111     0 0 0 1 1 0 1 1 (0) (0) (0) (0)              Rd          !=00000      1 1 0         Rm
              cond                              S                                 imm5        type


        MOVS, shift or rotate by value variant

        RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>

        and is always the preferred disassembly.


        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                     12 11        8 7 6 5 4 3               0
           1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0)                       imm3         Rd       imm2 1 1         Rm
                                                S                                                type


        MOVS, shift or rotate by value variant

        Applies when !(imm3 == 000 && imm2 == 00).

        RORS{<c>}{<q>} {<Rd>,} <Rm>, #<imm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, ROR #<imm>

        and is always the preferred disassembly.


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.
<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
               deprecates using the PC as the destination register, but if the PC is used, the instruction performs an
               exception return, that restores PSTATE from SPSR_<current_mode>.

               For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.

<Rm>           For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
               used.

               For encoding T3: is the general-purpose source register, encoded in the "Rm" field.

<imm>          For encoding A1: is the shift amount, in the range 1 to 31, encoded in the "imm5" field.

               For encoding T3: is the shift amount, in the range 1 to 31, encoded in the "imm3:imm2" field.


Operation for all encodings

The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: RRX
description:
        Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry       (F7.1.160)
        flag shifted into bit[31].

        This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

        .      The encodings in this description are named to match the encodings of MOV, MOVS (register).

        .      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


        A1


          31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11              7 6 5 4 3              0
             !=1111     0 0 0 1 1 0 1 0 (0) (0) (0) (0)           Rd        0 0 0 0 0 1 1 0                Rm
              cond                            S                                 imm5         type


        MOV, rotate right with extend variant

        RRX{<c>}{<q>} {<Rd>,} <Rm>

        is equivalent to

        MOV{<c>}{<q>} <Rd>, <Rm>, RRX

        and is always the preferred disassembly.


        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                  12 11          8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 0 1 0 0 1 1 1 1 (0) 0 0 0                            Rd        0 0 1 1          Rm
                                              S                    imm3                  imm2 type


        MOV, rotate right with extend variant

        RRX{<c>}{<q>} {<Rd>,} <Rm>

        is equivalent to

        MOV{<c>}{<q>} <Rd>, <Rm>, RRX

        and is always the preferred disassembly.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
                        deprecates using the PC as the destination register, but if the PC is used, the instruction is a branch
                        to the address calculated by the operation. This is an interworking branch, see Pseudocode
                        description of operations on the AArch32 general-purpose registers and the PC on page E1-2378.

                        For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>            For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
                        used.

                        For encoding T3: is the general-purpose source register, encoded in the "Rm" field.
Operation for all encodings

The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: RRXS
description:
        Rotate Right with Extend, setting flags provides the value of the contents of a register shifted right by one place,       (F7.1.161)
        with the Carry flag shifted into bit[31].

        If the destination register is not the PC, this instruction updates the condition flags based on the result, and bit[0] is
        shifted into the Carry flag.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

        .      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from AArch32
               state on page G1-3845.

        .      The instruction is UNDEFINED in Hyp mode.

        .      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.

        This instruction is an alias of the MOV, MOVS (register) instruction. This means that:

        .      The encodings in this description are named to match the encodings of MOV, MOVS (register).

        .      The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


        A1


          31        28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11             7 6 5 4 3             0
             !=1111     0 0 0 1 1 0 1 1 (0) (0) (0) (0)              Rd       0 0 0 0 0 1 1 0               Rm
              cond                              S                                 imm5         type


        MOVS, rotate right with extend variant

        RRXS{<c>}{<q>} {<Rd>,} <Rm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, RRX

        and is always the preferred disassembly.


        T3


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14                     12 11         8 7 6 5 4 3                0
           1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 1 (0) 0 0 0                              Rd        0 0 1 1         Rm
                                                S                     imm3                 imm2 type


        MOVS, rotate right with extend variant

        RRXS{<c>}{<q>} {<Rd>,} <Rm>

        is equivalent to

        MOVS{<c>}{<q>} <Rd>, <Rm>, RRX

        and is always the preferred disassembly.


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.
<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. ARM
               deprecates using the PC as the destination register, but if the PC is used, the instruction performs an
               exception return, that restores PSTATE from SPSR_<current_mode>.

               For encoding T3: is the general-purpose destination register, encoded in the "Rd" field.

<Rm>           For encoding A1: is the general-purpose source register, encoded in the "Rm" field. The PC can be
               used.

               For encoding T3: is the general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

The description of MOV, MOVS (register) gives the operational pseudocode for this instruction.


platform: ARM
mnem: RSB
description:
        Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the       (F7.1.162)
        destination register.

        If the destination register is not the PC, the RSBS variant of the instruction updates the condition flags based on the
        result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The RSB variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The RSBS variant of the instruction performs an exception return without the use of the stack. In this case:

               --      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                      AArch32 state on page G1-3845.

               --      The instruction is UNDEFINED in Hyp mode.

               --      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15        12 11                                   0
             !=1111     0 0 1 0 0 1 1 S                 Rn          Rd                      imm12
              cond


        RSB variant

        Applies when S = 0.

        RSB{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        RSBS variant

        Applies when S = 1.

        RSBS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);      setflags = (S == '1');   imm32 = A32ExpandImm(imm12);


        T1


          15 14 13 12 11 10 9 8 7 6 5               3 2     0
           0 1 0 0 0 0 1 0 0 1                  Rn       Rd




        T1 variant

        RSB<c>{<q>} {<Rd>, }<Rn>, #0// Inside IT block
        RSBS{<q>} {<Rd>, }<Rn>, #0// Outside IT block


        Decode for this encoding

         d = UInt(Rd);    n = UInt(Rn);      setflags = !InITBlock();    imm32 = Zeros(32); // immediate = #0
T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14    12 11          8 7                      0
  1 1 1 1 0 i 0 1 1 1 0 S                     Rn       0   imm3         Rd              imm8




RSB variant

Applies when S = 0.

RSB<c>.W {<Rd>,} <Rn>, #0// Inside IT block
RSB{<c>}{<q>} {<Rd>,} <Rn>, #<const>


RSBS variant

Applies when S = 1.

RSBS.W {<Rd>,} <Rn>, #0// Outside IT block
RSBS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


Decode for all variants of this encoding

 d = UInt(Rd);  n = UInt(Rn);      setflags = (S == '1');   imm32 = T32ExpandImm(i:imm3:imm8);
 if d == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           For encoding A1: is the general-purpose destination register, encoded in the "Rd" field. If omitted,
               this register is the same as <Rn>. ARM deprecates using the PC as the destination register, but if the
               PC is used:

               .      For the RSB variant, the instruction is a branch to the address calculated by the operation.
                      This is an interworking branch, see Pseudocode description of operations on the AArch32
                      general-purpose registers and the PC on page E1-2378.

               .      For the RSBS variant, the instruction performs an exception return, that restores PSTATE
                      from SPSR_<current_mode>.

               For encoding T1 and T2: is the general-purpose destination register, encoded in the "Rd" field. If
               omitted, this register is the same as <Rn>.

<Rn>           For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be
               used.

               For encoding T1 and T2: is the general-purpose source register, encoded in the "Rn" field.

<const>        For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
               page F4-2559 for the range of values.

               For encoding T2: an immediate value. See Modified immediate constants in T32 instructions on
               page F3-2530 for the range of values.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             (result, nzcv) = AddWithCarry(NOT(R[n]), imm32, '1');
             if d == 15 then            // Can only occur for A32 encoding
                 if setflags then
                     ALUExceptionReturn(result);
                 else
                     ALUWritePC(result);
             else
                 R[d] = result;
                 if setflags then
                     PSTATE.<N,Z,C,V> = nzcv;


platform: ARM
mnem: RSC
description:
        Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an       (F7.1.165)
        immediate value, and writes the result to the destination register.

        If the destination register is not the PC, the RSCS variant of the instruction updates the condition flags based on the
        result.

        The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM
        deprecates any use of these encodings. However, when the destination register is the PC:

        .      The RSC variant of the instruction is an interworking branch, see Pseudocode description of operations on
               the AArch32 general-purpose registers and the PC on page E1-2378.

        .      The RSCS variant of the instruction performs an exception return without the use of the stack. In this case:

               --      The PE branches to the address written to the PC, and restores PSTATE from SPSR_<current_mode>.

               --      The PE checks SPSR_<current_mode> for an illegal return event. See Illegal return events from
                      AArch32 state on page G1-3845.

               --      The instruction is UNDEFINED in Hyp mode.

               --      The instruction is CONSTRAINED UNPREDICTABLE in User mode and System mode.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15        12 11                                    0
             !=1111     0 0 1 0 1 1 1 S                 Rn          Rd                      imm12
              cond


        RSC variant

        Applies when S = 0.

        RSC{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        RSCS variant

        Applies when S = 1.

        RSCS{<c>}{<q>} {<Rd>,} <Rn>, #<const>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);      setflags = (S == '1');   imm32 = A32ExpandImm(imm12);


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.

        <q>              See Standard assembler syntax fields on page F2-2506.

        <Rd>             Is the general-purpose destination register, encoded in the "Rd" field. If omitted, this register is the
                         same as <Rn>. ARM deprecates using the PC as the destination register, but if the PC is used:

                         .      For the RSC variant, the instruction is a branch to the address calculated by the operation.
                                This is an interworking branch, see Pseudocode description of operations on the AArch32
                                general-purpose registers and the PC on page E1-2378.

                         .      For the RSCS variant, the instruction performs an exception return, that restores PSTATE
                                from SPSR_<current_mode>.

        <Rn>             Is the general-purpose source register, encoded in the "Rn" field. The PC can be used.
<const>       An immediate value. See Modified immediate constants in A32 instructions on page F4-2559 for the
              range of values.


Operation

 if ConditionPassed() then
    EncodingSpecificOperations();
    (result, nzcv) = AddWithCarry(NOT(R[n]), imm32, PSTATE.C);
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.<N,Z,C,V> = nzcv;


platform: ARM
mnem: SADD16
description:
     Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets       (F7.1.168)
     PSTATE.GE according to the results of the additions.


     A1


       31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                  0
          !=1111   0 1 1 0 0 0 0 1                 Rn          Rd      (1) (1) (1) (1) 0 0 0 1       Rm
           cond


     A1 variant

     SADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3             0
        1 1 1 1 1 0 1 0 1 0 0 1                    Rn      1 1 1 1          Rd        0 0 0 0        Rm




     T1 variant

     SADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>            See Standard assembler syntax fields on page F2-2506.

     <q>            See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);
          sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);
          R[d]<15:0>   = sum1<15:0>;
R[d]<31:16> = sum2<15:0>;
PSTATE.GE<1:0> = if sum1 >= 0 then '11' else '00';
PSTATE.GE<3:2> = if sum2 >= 0 then '11' else '00';


platform: ARM
mnem: SADD8
description:
     Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets       (F7.1.169)
     PSTATE.GE according to the results of the additions.


     A1


       31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                 0
          !=1111   0 1 1 0 0 0 0 1                 Rn          Rd      (1) (1) (1) (1) 1 0 0 1       Rm
           cond


     A1 variant

     SADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 0 0 0                    Rn      1 1 1 1          Rd        0 0 0 0        Rm




     T1 variant

     SADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>            See Standard assembler syntax fields on page F2-2506.

     <q>            See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);
          sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);
          sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);
sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);
R[d]<7:0>   = sum1<7:0>;
R[d]<15:8>  = sum2<7:0>;
R[d]<23:16> = sum3<7:0>;
R[d]<31:24> = sum4<7:0>;
PSTATE.GE<0>  = if sum1 >= 0 then '1' else '0';
PSTATE.GE<1>  = if sum2 >= 0 then '1' else '0';
PSTATE.GE<2>  = if sum3 >= 0 then '1' else '0';
PSTATE.GE<3>  = if sum4 >= 0 then '1' else '0';


platform: ARM
mnem: SASX
description:
     Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit       (F7.1.170)
     integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets PSTATE.GE
     according to the results.


     A1


       31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                     0
          !=1111    0 1 1 0 0 0 0 1                Rn          Rd       (1) (1) (1) (1) 0 0 1 1          Rm
           cond


     A1 variant

     SASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11              8 7 6 5 4 3               0
        1 1 1 1 1 0 1 0 1 0 1 0                    Rn      1 1 1 1           Rd        0 0 0 0           Rm




     T1 variant

     SASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff = SInt(R[n]<15:0>) - SInt(R[m]<31:16>);
          sum  = SInt(R[n]<31:16>) + SInt(R[m]<15:0>);
R[d]<15:0>  = diff<15:0>;
R[d]<31:16> = sum<15:0>;
PSTATE.GE<1:0> = if diff >= 0 then '11' else '00';
PSTATE.GE<3:2> = if sum  >= 0 then '11' else '00';


platform: ARM
mnem: SEL
description:
Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values       (F7.1.176)
of the PSTATE.GE flags.


A1


  31       28 27 26 25 24 23 22 21 20 19             16 15          12 11 10 9 8 7 6 5 4 3                0
     !=1111    0 1 1 0 1 0 0 0                  Rn            Rd       (1) (1) (1) (1) 1 0 1 1       Rm
      cond


A1 variant

SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11               8 7 6 5 4 3           0
   1 1 1 1 1 0 1 0 1 0 1 0                      Rn       1 1 1 1            Rd         1 0 0 0       Rm




T1 variant

SEL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     R[d]<7:0>     = if PSTATE.GE<0> == '1' then R[n]<7:0>           else R[m]<7:0>;
             R[d]<15:8>  = if PSTATE.GE<1> == '1' then R[n]<15:8>    else R[m]<15:8>;
             R[d]<23:16> = if PSTATE.GE<2> == '1' then R[n]<23:16> else R[m]<23:16>;
             R[d]<31:24> = if PSTATE.GE<3> == '1' then R[n]<31:24> else R[m]<31:24>;


platform: ARM
mnem: SETEND
description:
Set Endianness writes a new value to PSTATE.E.       (F7.1.177)


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 (0) (0) (0) (0) (0) (0) E (0) 0 0 0 0 (0) (0) (0) (0)




A1 variant

SETEND{<q>} <endian_specifier>// Cannot be conditional


Decode for this encoding

 set_bigend = (E == '1');


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
  1 0 1 1 0 1 1 0 0 1 0 (1) E (0) (0) (0)




T1 variant

SETEND{<q>} <endian_specifier>// Not permitted in IT block


Decode for this encoding

 set_bigend = (E == '1');
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<q>            See Standard assembler syntax fields on page F2-2506.

<endian_specifier>

               Is the endianness to be selected, and the value to be set in PSTATE.E, encoded in the "E" field. It
               can have the following values:

               LE          when E = 0

               BE          when E = 1


Operation for all encodings

 EncodingSpecificOperations();
 AArch32.CheckSETENDEnabled();
 PSTATE.E = if set_bigend then '1' else '0';


platform: ARM
mnem: SHADD16
description:
     Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the       (F7.1.180)
     destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3               0
          !=1111    0 1 1 0 0 0 1 1                Rn           Rd      (1) (1) (1) (1) 0 0 0 1     Rm
           cond


     A1 variant

     SHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3          0
        1 1 1 1 1 0 1 0 1 0 0 1                    Rn       1 1 1 1          Rd        0 0 1 0      Rm




     T1 variant

     SHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<15:0>) + SInt(R[m]<15:0>);
sum2 = SInt(R[n]<31:16>) + SInt(R[m]<31:16>);
R[d]<15:0>  = sum1<16:1>;
R[d]<31:16> = sum2<16:1>;


platform: ARM
mnem: SHADD8
description:
     Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the       (F7.1.181)
     destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3               0
          !=1111    0 1 1 0 0 0 1 1                Rn           Rd      (1) (1) (1) (1) 1 0 0 1     Rm
           cond


     A1 variant

     SHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3          0
        1 1 1 1 1 0 1 0 1 0 0 0                    Rn       1 1 1 1          Rd        0 0 1 0      Rm




     T1 variant

     SHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum1 = SInt(R[n]<7:0>) + SInt(R[m]<7:0>);
          sum2 = SInt(R[n]<15:8>) + SInt(R[m]<15:8>);
          sum3 = SInt(R[n]<23:16>) + SInt(R[m]<23:16>);
sum4 = SInt(R[n]<31:24>) + SInt(R[m]<31:24>);
R[d]<7:0>   = sum1<8:1>;
R[d]<15:8>  = sum2<8:1>;
R[d]<23:16> = sum3<8:1>;
R[d]<31:24> = sum4<8:1>;


platform: ARM
mnem: SHASX
description:
     Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.182)
     signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the
     destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                 0
          !=1111    0 1 1 0 0 0 1 1                Rn           Rd      (1) (1) (1) (1) 0 0 1 1       Rm
           cond


     A1 variant

     SHASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 0 1 0                    Rn       1 1 1 1          Rd        0 0 1 0        Rm




     T1 variant

     SHASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff = SInt(R[n]<15:0>) - SInt(R[m]<31:16>);
sum  = SInt(R[n]<31:16>) + SInt(R[m]<15:0>);
R[d]<15:0>  = diff<16:1>;
R[d]<31:16> = sum<16:1>;


platform: ARM
mnem: SHSAX
description:
     Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.183)
     signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the
     destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                 0
          !=1111    0 1 1 0 0 0 1 1                Rn           Rd      (1) (1) (1) (1) 0 1 0 1       Rm
           cond


     A1 variant

     SHSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
        1 1 1 1 1 0 1 0 1 1 1 0                    Rn       1 1 1 1          Rd        0 0 1 0        Rm




     T1 variant

     SHSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          sum  = SInt(R[n]<15:0>) + SInt(R[m]<31:16>);
diff = SInt(R[n]<31:16>) - SInt(R[m]<15:0>);
R[d]<15:0>  = sum<16:1>;
R[d]<31:16> = diff<16:1>;


platform: ARM
mnem: SHSUB16
description:
     Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results       (F7.1.184)
     to the destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
          !=1111     0 1 1 0 0 0 1 1               Rn           Rd      (1) (1) (1) (1) 0 1 1 1       Rm
           cond


     A1 variant

     SHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3           0
        1 1 1 1 1 0 1 0 1 1 0 1                    Rn       1 1 1 1          Rd        0 0 1 0        Rm




     T1 variant

     SHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff1 = SInt(R[n]<15:0>) - SInt(R[m]<15:0>);
diff2 = SInt(R[n]<31:16>) - SInt(R[m]<31:16>);
R[d]<15:0>  = diff1<16:1>;
R[d]<31:16> = diff2<16:1>;


platform: ARM
mnem: SHSUB8
description:
     Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results       (F7.1.185)
     to the destination register.


     A1


       31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
          !=1111     0 1 1 0 0 0 1 1               Rn           Rd      (1) (1) (1) (1) 1 1 1 1      Rm
           cond


     A1 variant

     SHSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


     T1


       15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3           0
        1 1 1 1 1 0 1 0 1 1 0 0                    Rn       1 1 1 1          Rd        0 0 1 0       Rm




     T1 variant

     SHSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


     Decode for this encoding

      d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
      if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

     <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

     <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


     Operation for all encodings

      if ConditionPassed() then
          EncodingSpecificOperations();
          diff1 = SInt(R[n]<7:0>) - SInt(R[m]<7:0>);
          diff2 = SInt(R[n]<15:8>) - SInt(R[m]<15:8>);
          diff3 = SInt(R[n]<23:16>) - SInt(R[m]<23:16>);
diff4 = SInt(R[n]<31:24>) - SInt(R[m]<31:24>);
R[d]<7:0>   = diff1<8:1>;
R[d]<15:8>  = diff2<8:1>;
R[d]<23:16> = diff3<8:1>;
R[d]<31:24> = diff4<8:1>;


platform: ARM
mnem: SMLABB
description:
        Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on       (F7.1.187)
        two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The
        other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the
        result is written to the destination register.

        If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. It is not possible
        for overflow to occur during the multiplication.


        A1


           31       28 27 26 25 24 23 22 21 20 19          16 15        12 11         8 7 6 5 4 3               0
             !=1111     0 0 0 1 0 0 0 0               Rd           Ra           Rm       1 M N 0         Rn
              cond


        SMLABB variant

        Applies when M = 0 && N = 0.

        SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLABT variant

        Applies when M = 1 && N = 0.

        SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLATB variant

        Applies when M = 0 && N = 1.

        SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLATT variant

        Applies when M = 1 && N = 1.

        SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         d = UInt(Rd);     n = UInt(Rn);    m = UInt(Rm);   a = UInt(Ra);
         n_high = (N == '1');      m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11         8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 0 0 0 1                    Rn         !=1111         Rd       0 0 N M         Rm
                                                                   Ra


        SMLABB variant

        Applies when N = 0 && M = 0.

        SMLABB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLABT variant

        Applies when N = 0 && M = 1.
SMLABT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


SMLATB variant

Applies when N = 1 && M = 0.

SMLATB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


SMLATT variant

Applies when N = 1 && M = 1.

SMLATT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


Decode for all variants of this encoding

 if Ra == '1111' then SEE SMULBB, SMULBT, SMULTB, SMULTT;
 d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);  a = UInt(Ra);
 n_high = (N == '1');    m_high = (M == '1');
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register holding the multiplicand in the bottom or top half
               (selected by <x>), encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register holding the multiplier in the bottom or top half
               (selected by <y>), encoded in the "Rm" field.

<Ra>           Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
     operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
     result = SInt(operand1) * SInt(operand2) + SInt(R[a]);
     R[d] = result<31:0>;
     if result != SInt(result<31:0>) then     // Signed overflow
         PSTATE.Q = '1';


platform: ARM
mnem: SMLAD
description:
        Signed Multiply Accumulate Dual performs two signed 16 x 16-bit multiplications. It adds the products to a 32-bit       (F7.1.188)
        accumulate operand.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        This instruction sets PSTATE.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the
        multiplications.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15        12 11       8 7 6 5 4 3               0
             !=1111     0 1 1 1 0 0 0 0               Rd        !=1111        Rm       0 0 M 1         Rn
              cond                                                Ra


        SMLAD variant

        Applies when M = 0.

        SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLADX variant

        Applies when M = 1.

        SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMUAD;
         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);   a = UInt(Ra);
         m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11       8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 0 0 1 0                    Rn        !=1111        Rd       0 0 0 M         Rm
                                                                  Ra


        SMLAD variant

        Applies when M = 0.

        SMLAD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLADX variant

        Applies when M = 1.

        SMLADX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMUAD;
         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);   a = UInt(Ra);
         m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.

<Ra>           Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand2 = if m_swap then ROR(R[m],16) else R[m];
     product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
     product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
     result = product1 + product2 + SInt(R[a]);
     R[d] = result<31:0>;
     if result != SInt(result<31:0>) then     // Signed overflow
         PSTATE.Q = '1';


platform: ARM
mnem: SMLALS
description:
        Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates       (F7.1.189)
        this with a 64-bit value.

        In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely
        affects performance on many implementations.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15       12 11         8 7 6 5 4 3                0
             !=1111    0 0 0 0 1 1 1 S               RdHi        RdLo         Rm       1 0 0 1           Rn
              cond


        Flag setting variant

        Applies when S = 1.

        SMLALS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Not flag setting variant

        Applies when S = 0.

        SMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);    dHi = UInt(RdHi);     n = UInt(Rn);  m = UInt(Rm);   setflags = (S == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if dHi == dLo then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11         8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 1 1 0 0                    Rn         RdLo        RdHi      0 0 0 0          Rm




        T1 variant

        SMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for this encoding

         dLo = UInt(RdLo);    dHi = UInt(RdHi);     n = UInt(Rn);  m = UInt(Rm);   setflags = FALSE;
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13
         if dHi == dLo then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly SMLAL on page J1-5357.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.
<RdLo>        Is the general-purpose source register holding the lower 32 bits of the addend, and the destination
              register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>        Is the general-purpose source register holding the upper 32 bits of the addend, and the destination
              register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    result = SInt(R[n]) * SInt(R[m]) + SInt(R[dHi]:R[dLo]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;
    if setflags then
        PSTATE.N = result<63>;
        PSTATE.Z = IsZeroBit(result<63:0>);
        // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: SMLALBB
description:
        Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and       (F7.1.190)
        accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom
        or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit
        product is sign-extended and accumulated with a 64-bit accumulate value.

        Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected
        if it occurs. Instead, the result wraps around modulo 264.


        A1


           31        28 27 26 25 24 23 22 21 20 19           16 15        12 11         8 7 6 5 4 3               0
              !=1111     0 0 0 1 0 1 0 0              RdHi          RdLo          Rm       1 M N 0           Rn
               cond


        SMLALBB variant

        Applies when M = 0 && N = 0.

        SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLALBT variant

        Applies when M = 1 && N = 0.

        SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLALTB variant

        Applies when M = 0 && N = 1.

        SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLALTT variant

        Applies when M = 1 && N = 1.

        SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);      dHi = UInt(RdHi);    n = UInt(Rn);    m = UInt(Rm);
         n_high = (N == '1');      m_high = (M == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if dHi == dLo then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15        12 11         8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 1 1 0 0                     Rn           RdLo         RdHi      1 0 N M           Rm




        SMLALBB variant

        Applies when N = 0 && M = 0.

        SMLALBB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>
SMLALBT variant

Applies when N = 0 && M = 1.

SMLALBT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


SMLALTB variant

Applies when N = 1 && M = 0.

SMLALTB{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


SMLALTT variant

Applies when N = 1 && M = 1.

SMLALTT{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for all variants of this encoding

 dLo = UInt(RdLo);   dHi = UInt(RdHi);    n = UInt(Rn);      m = UInt(Rm);
 n_high = (N == '1');    m_high = (M == '1');
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13
 if dHi == dLo then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly SMLALBB, SMLALBT, SMLALTB,
SMLALTT on page J1-5357.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<RdLo>         Is the general-purpose source register holding the lower 32 bits of the addend, and the destination
               register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>         Is the general-purpose source register holding the upper 32 bits of the addend, and the destination
               register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>           For encoding A1: is the first general-purpose source register holding the multiplicand in the bottom
               or top half (selected by <x>), encoded in the "Rn" field.

               For encoding T1: is the first general-purpose source register holding the multiplicand in the bottom
               or top half (selected by <x>), encoded in the "Rn" field.

<Rm>           For encoding A1: is the second general-purpose source register holding the multiplier in the bottom
               or top half (selected by <y>), encoded in the "Rm" field.

               For encoding T1: is the second general-purpose source register holding the multiplier in the bottom
               or top half (selected by <x>), encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
     operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
     result = SInt(operand1) * SInt(operand2) + SInt(R[dHi]:R[dLo]);
     R[dHi] = result<63:32>;
     R[dLo] = result<31:0>;


platform: ARM
mnem: SMLALD
description:
        Signed Multiply Accumulate Long Dual performs two signed 16 x 16-bit multiplications. It adds the products to a       (F7.1.191)
        64-bit accumulate operand.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected
        if it occurs. Instead, the result wraps around modulo 264.


        A1


           31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7 6 5 4 3               0
              !=1111     0 1 1 1 0 1 0 0             RdHi         RdLo            Rm       0 0 M 1          Rn
               cond


        SMLALD variant

        Applies when M = 0.

        SMLALD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLALDX variant

        Applies when M = 1.

        SMLALDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);      dHi = UInt(RdHi);   n = UInt(Rn);    m = UInt(Rm);     m_swap = (M == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if dHi == dLo then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15          12 11          8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 1 1 0 0                     Rn         RdLo           RdHi      1 1 0 M          Rm




        SMLALD variant

        Applies when M = 0.

        SMLALD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLALDX variant

        Applies when M = 1.

        SMLALDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);      dHi = UInt(RdHi);   n = UInt(Rn);    m = UInt(Rm);     m_swap = (M == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13
         if dHi == dLo then UNPREDICTABLE;
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly SMLALD on page J1-5358.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<RdLo>         Is the general-purpose source register holding the lower 32 bits of the addend, and the destination
               register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>         Is the general-purpose source register holding the upper 32 bits of the addend, and the destination
               register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand2 = if m_swap then ROR(R[m],16) else R[m];
     product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
     product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
     result = product1 + product2 + SInt(R[dHi]:R[dLo]);
     R[dHi] = result<63:32>;
     R[dLo] = result<31:0>;


platform: ARM
mnem: SMLAWB
description:
        Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply       (F7.1.192)
        acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the
        bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits
        of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The
        bottom 16 bits of the 48-bit product are ignored.

        If overflow occurs during the addition of the accumulate value, the instruction sets PSTATE.Q to 1. No overflow
        can occur during the multiplication.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15         12 11       8 7 6 5 4 3                0
             !=1111     0 0 0 1 0 0 1 0                Rd           Ra           Rm      1 M 0 0           Rn
              cond


        SMLAWB variant

        Applies when M = 0.

        SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLAWT variant

        Applies when M = 1.

        SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);    a = UInt(Ra);     m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15          12 11       8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 0 1 1                     Rn         !=1111         Rd      0 0 0 M           Rm
                                                                    Ra


        SMLAWB variant

        Applies when M = 0.

        SMLAWB{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLAWT variant

        Applies when M = 1.

        SMLAWT{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMULWB, SMULWT;
         d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);    a = UInt(Ra);     m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register holding the multiplier in the bottom or top half
               (selected by <y>), encoded in the "Rm" field.

<Ra>           Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
     result = SInt(R[n]) * SInt(operand2) + (SInt(R[a]) << 16);
     R[d] = result<47:16>;
     if (result >> 16) != SInt(R[d]) then     // Signed overflow
         PSTATE.Q = '1';


platform: ARM
mnem: SMLSD
description:
        Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the       (F7.1.193)
        products to a 32-bit accumulate operand.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        This instruction sets PSTATE.Q to 1 if the accumulate operation overflows. Overflow cannot occur during the
        multiplications or subtraction.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15        12 11       8 7 6 5 4 3               0
             !=1111     0 1 1 1 0 0 0 0               Rd        !=1111        Rm       0 1 M 1         Rn
              cond                                                Ra


        SMLSD variant

        Applies when M = 0.

        SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLSDX variant

        Applies when M = 1.

        SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMUSD;
         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);   a = UInt(Ra);    m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11       8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 0 1 0 0                    Rn        !=1111        Rd       0 0 0 M         Rm
                                                                  Ra


        SMLSD variant

        Applies when M = 0.

        SMLSD{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMLSDX variant

        Applies when M = 1.

        SMLSDX{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMUSD;
         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);   a = UInt(Ra);    m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.

<Ra>           Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand2 = if m_swap then ROR(R[m],16) else R[m];
     product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
     product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
     result = product1 - product2 + SInt(R[a]);
     R[d] = result<31:0>;
     if result != SInt(result<31:0>) then     // Signed overflow
         PSTATE.Q = '1';


platform: ARM
mnem: SMLSLD
description:
        Signed Multiply Subtract Long Dual performs two signed 16 x 16-bit multiplications. It adds the difference of the       (F7.1.194)
        products to a 64-bit accumulate operand.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected
        if it occurs. Instead, the result wraps around modulo 264.


        A1


           31        28 27 26 25 24 23 22 21 20 19         16 15         12 11          8 7 6 5 4 3               0
              !=1111     0 1 1 1 0 1 0 0             RdHi         RdLo            Rm       0 1 M 1          Rn
               cond


        SMLSLD variant

        Applies when M = 0.

        SMLSLD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLSLDX variant

        Applies when M = 1.

        SMLSLDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);      dHi = UInt(RdHi);   n = UInt(Rn);    m = UInt(Rm);     m_swap = (M == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if dHi == dLo then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15          12 11          8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 1 1 0 1                     Rn         RdLo           RdHi      1 1 0 M          Rm




        SMLSLD variant

        Applies when M = 0.

        SMLSLD{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        SMLSLDX variant

        Applies when M = 1.

        SMLSLDX{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);      dHi = UInt(RdHi);   n = UInt(Rn);    m = UInt(Rm);     m_swap = (M == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         // ARMv8-A removes UPREDICTABLE for R13
         if dHi == dLo then UNPREDICTABLE;
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly SMLSLD on page J1-5358.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<RdLo>         Is the general-purpose source register holding the lower 32 bits of the addend, and the destination
               register for the lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>         Is the general-purpose source register holding the upper 32 bits of the addend, and the destination
               register for the upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand2 = if m_swap then ROR(R[m],16) else R[m];
     product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
     product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
     result = product1 - product2 + SInt(R[dHi]:R[dLo]);
     R[dHi] = result<63:32>;
     R[dLo] = result<31:0>;


platform: ARM
mnem: SMMLA
description:
        Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most       (F7.1.195)
        significant 32 bits of the result, and adds an accumulate value.

        Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant
        0x80000000 is added to the product before the high word is extracted.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15         12 11        8 7 6 5 4 3                0
             !=1111     0 1 1 1 0 1 0 1                Rd           !=1111       Rm       0 0 R 1            Rn
              cond                                                   Ra


        SMMLA variant

        Applies when R = 0.

        SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMMLAR variant

        Applies when R = 1.

        SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMMUL;
         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);   a = UInt(Ra);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15          12 11        8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 1 0 1                     Rn           !=1111       Rd       0 0 0 R           Rm
                                                                     Ra


        SMMLA variant

        Applies when R = 0.

        SMMLA{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMMLAR variant

        Applies when R = 1.

        SMMLAR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         if Ra == '1111' then SEE SMMUL;
         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);   a = UInt(Ra);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

<Ra>          Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    result = (SInt(R[a]) << 32) + SInt(R[n]) * SInt(R[m]);
    if round then result = result + 0x80000000;
    R[d] = result<63:32>;


platform: ARM
mnem: SMMLS
description:
        Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a       (F7.1.196)
        32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that
        subtraction.

        Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this
        case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15         12 11          8 7 6 5 4 3              0
             !=1111     0 1 1 1 0 1 0 1                Rd            Ra           Rm       1 1 R 1          Rn
              cond


        SMMLS variant

        Applies when R = 0.

        SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMMLSR variant

        Applies when R = 1.

        SMMLSR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);     a = UInt(Ra);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15          12 11          8 7 6 5 4 3              0
           1 1 1 1 1 0 1 1 0 1 1 0                     Rn            Ra            Rd      0 0 0 R          Rm




        SMMLS variant

        Applies when R = 0.

        SMMLS{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        SMMLSR variant

        Applies when R = 1.

        SMMLSR{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);   m = UInt(Rm);     a = UInt(Ra);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.

<Ra>          Is the third general-purpose source register holding the addend, encoded in the "Ra" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    result = (SInt(R[a]) << 32) - SInt(R[n]) * SInt(R[m]);
    if round then result = result + 0x80000000;
    R[d] = result<63:32>;


platform: ARM
mnem: SMMUL
description:
        Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of       (F7.1.197)
        the result, and writes those bits to the destination register.

        Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant
        0x80000000 is added to the product before the high word is extracted.


        A1


          31         28 27 26 25 24 23 22 21 20 19           16 15 14 13 12 11         8 7 6 5 4 3                0
             !=1111     0 1 1 1 0 1 0 1                Rd        1 1 1 1         Rm       0 0 R 1            Rn
              cond


        SMMUL variant

        Applies when R = 0.

        SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMMULR variant

        Applies when R = 1.

        SMMULR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11          8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 1 0 1                     Rn        1 1 1 1         Rd       0 0 0 R           Rm




        SMMUL variant

        Applies when R = 0.

        SMMUL{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMMULR variant

        Applies when R = 1.

        SMMULR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);     round = (R == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    result = SInt(R[n]) * SInt(R[m]);
    if round then result = result + 0x80000000;
    R[d] = result<63:32>;


platform: ARM
mnem: SMUAD
description:
        Signed Dual Multiply Add performs two signed 16 x 16-bit multiplications. It adds the products together, and writes       (F7.1.198)
        the result to the destination register.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        This instruction sets PSTATE.Q to 1 if the addition overflows. The multiplications cannot overflow.


        A1


          31        28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11       8 7 6 5 4 3               0
             !=1111     0 1 1 1 0 0 0 0               Rd        1 1 1 1       Rm       0 0 M 1         Rn
              cond


        SMUAD variant

        Applies when M = 0.

        SMUAD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMUADX variant

        Applies when M = 1.

        SMUADX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);  m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11        8 7 6 5 4 3               0
           1 1 1 1 1 0 1 1 0 0 1 0                    Rn        1 1 1 1       Rd       0 0 0 M         Rm




        SMUAD variant

        Applies when M = 0.

        SMUAD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMUADX variant

        Applies when M = 1.

        SMUADX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);  m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_swap then ROR(R[m],16) else R[m];
    product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
    product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
    result = product1 + product2;
    R[d] = result<31:0>;
    if result != SInt(result<31:0>) then     // Signed overflow
        PSTATE.Q = '1';


platform: ARM
mnem: SMULBB
description:
        Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of       (F7.1.199)
        their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written
        to the destination register. No overflow is possible during this instruction.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15 14 13 12 11           8 7 6 5 4 3              0
             !=1111     0 0 0 1 0 1 1 0               Rd        (0) (0) (0) (0)  Rm        1 M N 0         Rn
              cond


        SMULBB variant

        Applies when M = 0 && N = 0.

        SMULBB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULBT variant

        Applies when M = 1 && N = 0.

        SMULBT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULTB variant

        Applies when M = 0 && N = 1.

        SMULTB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULTT variant

        Applies when M = 1 && N = 1.

        SMULTT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
         n_high = (N == '1');     m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3              0
           1 1 1 1 1 0 1 1 0 0 0 1                    Rn         1 1 1 1         Rd        0 0 N M         Rm




        SMULBB variant

        Applies when N = 0 && M = 0.

        SMULBB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULBT variant

        Applies when N = 0 && M = 1.

        SMULBT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
SMULTB variant

Applies when N = 1 && M = 0.

SMULTB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


SMULTT variant

Applies when N = 1 && M = 1.

SMULTT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for all variants of this encoding

 d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
 n_high = (N == '1');    m_high = (M == '1');
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register holding the multiplicand in the bottom or top half
               (selected by <x>), encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register holding the multiplier in the bottom or top half
               (selected by <y>), encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
     operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
     result = SInt(operand1) * SInt(operand2);
     R[d] = result<31:0>;
     // Signed overflow cannot occur


platform: ARM
mnem: SMULLS
description:
        Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result.       (F7.1.200)

        In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely
        affects performance on many implementations.


        A1


          31        28 27 26 25 24 23 22 21 20 19         16 15       12 11         8 7 6 5 4 3                0
             !=1111    0 0 0 0 1 1 0 S               RdHi        RdLo         Rm       1 0 0 1           Rn
              cond


        Flag setting variant

        Applies when S = 1.

        SMULLS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Not flag setting variant

        Applies when S = 0.

        SMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for all variants of this encoding

         dLo = UInt(RdLo);    dHi = UInt(RdHi);     n = UInt(Rn);  m = UInt(Rm);  setflags = (S == '1');
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         if dHi == dLo then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11         8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 1 0 0 0                    Rn         RdLo        RdHi      0 0 0 0          Rm




        T1 variant

        SMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


        Decode for this encoding

         dLo = UInt(RdLo);    dHi = UInt(RdHi);     n = UInt(Rn);  m = UInt(Rm);  setflags = FALSE;
         if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13
         if dHi == dLo then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly SMULL on page J1-5357.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.
<RdLo>        Is the general-purpose destination register for the lower 32 bits of the result, encoded in the "RdLo"
              field.

<RdHi>        Is the general-purpose destination register for the upper 32 bits of the result, encoded in the "RdHi"
              field.

<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    result = SInt(R[n]) * SInt(R[m]);
    R[dHi] = result<63:32>;
    R[dLo] = result<31:0>;
    if setflags then
        PSTATE.N = result<63>;
        PSTATE.Z = IsZeroBit(result<63:0>);
        // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: SMULWB
description:
        Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed       (F7.1.201)
        16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second
        source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom
        16 bits of the 48-bit product are ignored. No overflow is possible during this instruction.


        A1


          31        28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11           8 7 6 5 4 3               0
             !=1111     0 0 0 1 0 0 1 0               Rd      (0) (0) (0) (0)   Rm        1 M 1 0          Rn
              cond


        SMULWB variant

        Applies when M = 0.

        SMULWB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULWT variant

        Applies when M = 1.

        SMULWT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);   m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11           8 7 6 5 4 3                0
           1 1 1 1 1 0 1 1 0 0 1 1                    Rn       1 1 1 1           Rd       0 0 0 M          Rm




        SMULWB variant

        Applies when M = 0.

        SMULWB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMULWT variant

        Applies when M = 1.

        SMULWT{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);   m_high = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register holding the multiplier in the bottom or top half
              (selected by <y>), encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
    product = SInt(R[n]) * SInt(operand2);
    R[d] = product<47:16>;
    // Signed overflow cannot occur


platform: ARM
mnem: SMUSD
description:
        Signed Multiply Subtract Dual performs two signed 16 x 16-bit multiplications. It subtracts one of the products from       (F7.1.202)
        the other, and writes the result to the destination register.

        Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This
        produces top x bottom and bottom x top multiplication.

        Overflow cannot occur.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15 14 13 12 11      8 7 6 5 4 3                 0
             !=1111     0 1 1 1 0 0 0 0                Rd       1 1 1 1        Rm      0 1 M 1          Rn
              cond


        SMUSD variant

        Applies when M = 0.

        SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMUSDX variant

        Applies when M = 1.

        SMUSDX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);    m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11      8 7 6 5 4 3                 0
           1 1 1 1 1 0 1 1 0 1 0 0                     Rn       1 1 1 1        Rd      0 0 0 M          Rm




        SMUSD variant

        Applies when M = 0.

        SMUSD{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        SMUSDX variant

        Applies when M = 1.

        SMUSDX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


        Decode for all variants of this encoding

         d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);    m_swap = (M == '1');
         if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rd>          Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>          Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>          Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    operand2 = if m_swap then ROR(R[m],16) else R[m];
    product1 = SInt(R[n]<15:0>) * SInt(operand2<15:0>);
    product2 = SInt(R[n]<31:16>) * SInt(operand2<31:16>);
    result = product1 - product2;
    R[d] = result<31:0>;
    // Signed overflow cannot occur


platform: ARM
mnem: SRS
description:
        Store Return State stores the LR_<current_mode> and SPSR_<current_mode> to the stack of a specified mode. For       (F7.1.203)
        information about memory accesses see Memory accesses on page F2-2513.

        SRS is UNDEFINED in Hyp mode.

        SRS is UNPREDICTABLE if it is executed in User or System mode, or if the specified mode is any of the following:

        .      Not implemented.

        .      A mode that Table G1-2 on page G1-3806 does not show.

        .      Not accessible from the context that the SRS instruction is executed in, as follows:

               --      A mode that is at a higher Exception level.

               --      When executing in Non-secure state, Monitor mode.

        SRS is trapped to EL3 if all of the following are true:

        .      It is executed at Secure PL1.

        .      The specified mode is monitor mode.

        .      EL3 is using AArch64.

        See Traps to EL3 of Secure monitor functionality from Secure EL1 using AArch32 on page D1-1586.


        A1


          31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4                     0
           1 1 1 1 1 0 0 P U 1 W 0 (1) (1) (0) (1) (0) (0) (0) (0) (0) (1) (0) (1) (0) (0) (0)      mode




        Decrement After variant

        Applies when P = 0 && U = 0.

        SRSDA{<c>}{<q>} SP{!}, #<mode>


        Decrement Before variant

        Applies when P = 1 && U = 0.

        SRSDB{<c>}{<q>} SP{!}, #<mode>


        Increment After variant

        Applies when P = 0 && U = 1.

        SRS{IA}{<c>}{<q>} SP{!}, #<mode>


        Increment Before variant

        Applies when P = 1 && U = 1.

        SRSIB{<c>}{<q>} SP{!}, #<mode>


        Decode for all variants of this encoding

         wback = (W == '1');     increment = (U == '1');     wordhigher = (P == U);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4                                  0
  1 1 1 0 1 0 0 0 0 0 W 0 (1) (1) (0) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0)         mode




T1 variant

SRSDB{<c>}{<q>} SP{!}, #<mode>


Decode for this encoding

 wback = (W == '1');     increment = FALSE;   wordhigher = FALSE;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4                                  0
  1 1 1 0 1 0 0 1 1 0 W 0 (1) (1) (0) (1) (1) (1) (0) (0) (0) (0) (0) (0) (0) (0) (0)         mode




T2 variant

SRS{IA}{<c>}{<q>} SP{!}, #<mode>


Decode for this encoding

 wback = (W == '1');     increment = TRUE;   wordhigher = FALSE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly SRS (T32) on page J1-5381 and SRS
(A32) on page J1-5382.


Assembler symbols

IA              For encoding A1: is an optional suffix to indicate the Increment After variant.

                For encoding T2: is an optional suffix for the Increment After form.

<c>             For encoding A1: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

                For encoding T1 and T2: see Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

!               The address adjusted by the size of the data loaded is written back to the base register. If specified,
                it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<mode>          Is the number of the mode whose Banked SP is used as the base register, encoded in the "mode"
                field. For details of PE modes and their numbers see AArch32 PE mode descriptions on
                page G1-3806.

SRSFA, SRSEA, SRSFD, and SRSED are pseudo-instructions for SRSIB, SRSIA, SRSDB, and SRSDA respectively, referring to
their use for pushing data onto Full Ascending, Empty Ascending, Full Descending, and Empty Descending stacks.
        Operation for all encodings

         if CurrentInstrSet() == InstrSet_A32 then
             if ConditionPassed() then
                 EncodingSpecificOperations();
                 if PSTATE.EL == EL2 then              // UNDEFINED at EL2
                     UNDEFINED;

                 // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these
                 // to be security holes
                 if PSTATE.M IN {M32_User,M32_System} then
                     UNPREDICTABLE;
                 elsif mode == M32_Hyp then            // Check for attempt to access Hyp mode SP
                     UNPREDICTABLE;
                 elsif mode == M32_Monitor then        // Check for attempt to access Monitor mode SP
                     if !HaveEL(EL3) || !IsSecure()      then
                         UNPREDICTABLE;
                     elsif !ELUsingAArch32(EL3) then
                         AArch64.MonitorModeTrap();

                 base = Rmode[13,mode];
                 address = if increment then base else base-8;
                 if wordhigher then address = address+4;
                 MemA[address,4]     = LR;
                 MemA[address+4,4] = SPSR[];
                 if wback then Rmode[13,mode] = if increment then base+8 else base-8;
         else
             if ConditionPassed() then
                 EncodingSpecificOperations();
                 if PSTATE.EL == EL2 then              // UNDEFINED at EL2
                     UNDEFINED;

                 // Check for UNPREDICTABLE cases. The definition of UNPREDICTABLE does not permit these
                 // to be security holes
                 if PSTATE.M IN {M32_User,M32_System} then
                     UNPREDICTABLE;
                 elsif mode == M32_Hyp then            // Check for attempt to access Hyp mode SP
                     UNPREDICTABLE;
                 elsif mode == M32_Monitor then        // Check for attempt to access Monitor mode SP
                     if !HaveEL(EL3) || !IsSecure()      then
                         UNPREDICTABLE;
                     elsif !ELUsingAArch32(EL3) then
                         AArch64.MonitorModeTrap();

                 base = Rmode[13,mode];
                 address = if increment then base else base-8;
                 if wordhigher then address = address+4;
                 MemA[address,4]     = LR;
                 MemA[address+4,4] = SPSR[];
                 if wback then Rmode[13,mode] = if increment then base+8 else base-8;


