# instructions

platform: x86_64
mnem: VFIXUPIMMPD
description:
VFIXUPIMMPD-Fix Up Special Packed Float64 Values
 Opcode/                              Op /   64/32      CPUID        Description
 Instruction                          En     bit Mode   Feature
                                             Support    Flag
 EVEX.NDS.128.66.0F3A.W1 54 /r ib     FV     V/V        AVX512VL     Fix up special numbers in float64 vector xmm1, float64
 VFIXUPIMMPD xmm1 {k1}{z}, xmm2,                        AVX512F      vector xmm2 and int64 vector xmm3/m128/m64bcst
 xmm3/m128/m64bcst, imm8                                             and store the result in xmm1, under writemask.
 EVEX.NDS.256.66.0F3A.W1 54 /r ib     FV     V/V        AVX512VL     Fix up special numbers in float64 vector ymm1, float64
 VFIXUPIMMPD ymm1 {k1}{z}, ymm2,                        AVX512F      vector ymm2 and int64 vector ymm3/m256/m64bcst
 ymm3/m256/m64bcst, imm8                                             and store the result in ymm1, under writemask.
 EVEX.NDS.512.66.0F3A.W1 54 /r ib     FV     V/V        AVX512F      Fix up elements of float64 vector in zmm2 using int64
 VFIXUPIMMPD zmm1 {k1}{z}, zmm2,                                     vector table in zmm3/m512/m64bcst, combine with
 zmm3/m512/m64bcst{sae}, imm8                                        preserved elements from zmm1, and store the result in
                                                                     zmm1.



                                             Instruction Operand Encoding
       Op/En              Operand 1                 Operand 2                Operand 3                    Operand 4
         FV            ModRM:reg (r, w)             EVEX.vvvv               ModRM:r/m (r)                   Imm8

Description
Perform fix-up of quad-word elements encoded in double-precision floating-point format in the first source operand
(the second operand) using a 32-bit, two-level look-up table specified in the corresponding quadword element of
the second source operand (the third operand) with exception reporting specifier imm8. The elements that are
fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table
response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from
the first source operand and the preserved element in the first operand are combined as the final results in the
destination operand (the first operand).
The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.
The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-
rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in the destination with the corresponding bit clear in k1 retain their
previous values or are set to 0.





Operation
enum TOKEN_TYPE
{
   QNAN_TOKEN <- 0,
   SNAN_TOKEN <- 1,
   ZERO_VALUE_TOKEN <- 2,
   POS_ONE_VALUE_TOKEN <- 3,
   NEG_INF_TOKEN <- 4,
   POS_INF_TOKEN <- 5,
   NEG_VALUE_TOKEN <- 6,
   POS_VALUE_TOKEN <- 7
}

FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){
   tsrc[63:0] <- ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]
   CASE(tsrc[63:0] of TOKEN_TYPE) {
        QNAN_TOKEN: j <- 0;
        SNAN_TOKEN: j <- 1;
        ZERO_VALUE_TOKEN: j <- 2;
        POS_ONE_VALUE_TOKEN: j <- 3;
        NEG_INF_TOKEN: j <- 4;
        POS_INF_TOKEN: j <- 5;
        NEG_VALUE_TOKEN: j <- 6;
        POS_VALUE_TOKEN: j <- 7;
   }    ; end source special CASE(tsrc...)

   ; The required response from src3 table is extracted
   token_response[3:0] = tbl3[3+4*j:4*j];

   CASE(token_response[3:0]) {
       0000: dest[63:0] <- dest[63:0] ;            ; preserve content of DEST
       0001: dest[63:0] <- tsrc[63:0];             ; pass through src1 normal input value, denormal as zero
       0010: dest[63:0] <- QNaN(tsrc[63:0]);
       0011: dest[63:0] <- QNAN_Indefinite;
       0100: dest[63:0] <- -INF;
       0101: dest[63:0] <- +INF;
       0110: dest[63:0] <- tsrc.sign? -INF : +INF;
       0111: dest[63:0] <- -0;
       1000: dest[63:0] <- +0;
       1001: dest[63:0] <- -1;
       1010: dest[63:0] <- +1;
       1011: dest[63:0] <- 1/2;
       1100: dest[63:0] <- 90.0;
       1101: dest[63:0] <- PI/2;
       1110: dest[63:0] <- MAX_FLOAT;
       1111: dest[63:0] <- -MAX_FLOAT;
   }       ; end of token_response CASE





    ; The required fault reporting from imm8 is extracted
    ; TOKENs are mutually exclusive and TOKENs priority defines the order.
    ; Multiple faults related to a single token can occur simultaneously.
    IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
    IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
    IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
          ; end fault reporting
    return dest[63:0];
}         ; end of FIXUPIMM_DP()

VFIXUPIMMPD
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[63:0], imm8 [7:0])
                    ELSE
                         DEST[i+63:i] <- FIXUPIMM_DP(DEST[i+63:i], SRC1[i+63:i], SRC2[i+63:i], imm8 [7:0])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Immediate Control Description:




                                                      7 6 5 4 3 2 1 0
                                                      | | | | | | | |
                           + INF     ->        #IE----+ | | | | | | |
                           - VE      ->        #IE------+ | | | | | |
                           - INF     ->        #IE--------+ | | | | |
                            SNaN     ->        #IE----------+ | | | |
                            ONE      ->        #IE------------+ | | |
                            ONE      ->        #ZE--------------+ | |
                            ZERO     ->        #IE----------------+ |
                            ZERO     ->        #ZE------------------+

                                  Figure 5-9. VFIXUPIMMPD Immediate Control Description


Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPD __m512d _mm512_fixupimm_pd( __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_pd( __mmask8 k, __m512d a, __m512i tbl, int imm);
VFIXUPIMMPD __m512d _mm512_fixupimm_round_pd( __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_mask_fixupimm_round_pd(__m512d s, __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m512d _mm512_maskz_fixupimm_round_pd( __mmask8 k, __m512d a, __m512i tbl, int imm, int sae);
VFIXUPIMMPD __m256d _mm256_fixupimm_pd( __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m256d _mm256_mask_fixupimm_pd(__m256d s, __mmask8 k, __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m256d _mm256_maskz_fixupimm_pd( __mmask8 k, __m256d a, __m256i tbl, int imm);
VFIXUPIMMPD __m128d _mm_fixupimm_pd( __m128d a, __m128i tbl, int imm);
VFIXUPIMMPD __m128d _mm_mask_fixupimm_pd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMPD __m128d _mm_maskz_fixupimm_pd( __mmask8 k, __m128d a, __m128i tbl, int imm);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VFIXUPIMMPS
description:
VFIXUPIMMPS-Fix Up Special Packed Float32 Values
 Opcode/                                  Op /   64/32      CPUID      Description
 Instruction                              En     bit Mode   Feature
                                                 Support    Flag
 EVEX.NDS.128.66.0F3A.W0 54 /r            FV     V/V        AVX512VL   Fix up special numbers in float32 vector xmm1, float32
 VFIXUPIMMPS xmm1 {k1}{z}, xmm2,                            AVX512F    vector xmm2 and int32 vector xmm3/m128/m32bcst
 xmm3/m128/m32bcst, imm8                                               and store the result in xmm1, under writemask.
 EVEX.NDS.256.66.0F3A.W0 54 /r            FV     V/V        AVX512VL   Fix up special numbers in float32 vector ymm1, float32
 VFIXUPIMMPS ymm1 {k1}{z}, ymm2,                            AVX512F    vector ymm2 and int32 vector ymm3/m256/m32bcst
 ymm3/m256/m32bcst, imm8                                               and store the result in ymm1, under writemask.
 EVEX.NDS.512.66.0F3A.W0 54 /r ib         FV     V/V        AVX512F    Fix up elements of float32 vector in zmm2 using int32
 VFIXUPIMMPS zmm1 {k1}{z}, zmm2,                                       vector table in zmm3/m512/m32bcst, combine with
 zmm3/m512/m32bcst{sae}, imm8                                          preserved elements from zmm1, and store the result in
                                                                       zmm1.



                                                 Instruction Operand Encoding
       Op/En              Operand 1                    Operand 2                Operand 3                   Operand 4
        FV             ModRM:reg (r, w)                EVEX.vvvv             ModRM:r/m (r)                     Imm8

Description
Perform fix-up of doubleword elements encoded in single-precision floating-point format in the first source operand
(the second operand) using a 32-bit, two-level look-up table specified in the corresponding doubleword element of
the second source operand (the third operand) with exception reporting specifier imm8. The elements that are
fixed-up are selected by mask bits of 1 specified in the opmask k1. Mask bits of 0 in the opmask k1 or table
response action of 0000b preserves the corresponding element of the first operand. The fixed-up elements from
the first source operand and the preserved element in the first operand are combined as the final results in the
destination operand (the first operand).
The destination and the first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.
The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-
rect result. To deal with this, VFIXUPIMMPS can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.





Operation
enum TOKEN_TYPE
{
   QNAN_TOKEN <- 0,
   SNAN_TOKEN <- 1,
   ZERO_VALUE_TOKEN <- 2,
   POS_ONE_VALUE_TOKEN <- 3,
   NEG_INF_TOKEN <- 4,
   POS_INF_TOKEN <- 5,
   NEG_VALUE_TOKEN <- 6,
   POS_VALUE_TOKEN <- 7
}

FIXUPIMM_SP ( dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){
   tsrc[31:0] <- ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
   CASE(tsrc[63:0] of TOKEN_TYPE) {
        QNAN_TOKEN: j <- 0;
        SNAN_TOKEN: j <- 1;
        ZERO_VALUE_TOKEN: j <- 2;
        POS_ONE_VALUE_TOKEN: j <- 3;
        NEG_INF_TOKEN: j <- 4;
        POS_INF_TOKEN: j <- 5;
        NEG_VALUE_TOKEN: j <- 6;
        POS_VALUE_TOKEN: j <- 7;
   }        ; end source special CASE(tsrc...)

   ; The required response from src3 table is extracted
   token_response[3:0] = tbl3[3+4*j:4*j];

   CASE(token_response[3:0]) {
       0000: dest[31:0] <- dest[31:0];        ; preserve content of DEST
       0001: dest[31:0] <- tsrc[31:0];        ; pass through src1 normal input value, denormal as zero
       0010: dest[31:0] <- QNaN(tsrc[31:0]);
       0011: dest[31:0] <- QNAN_Indefinite;
       0100: dest[31:0] <- -INF;
       0101: dest[31:0] <- +INF;
       0110: dest[31:0] <- tsrc.sign? -INF : +INF;
       0111: dest[31:0] <- -0;
       1000: dest[31:0] <- +0;
       1001: dest[31:0] <- -1;
       1010: dest[31:0] <- +1;
       1011: dest[31:0] <- 1/2;
       1100: dest[31:0] <- 90.0;
       1101: dest[31:0] <- PI/2;
       1110: dest[31:0] <- MAX_FLOAT;
       1111: dest[31:0] <- -MAX_FLOAT;
   }       ; end of token_response CASE





    ; The required fault reporting from imm8 is extracted
    ; TOKENs are mutually exclusive and TOKENs priority defines the order.
    ; Multiple faults related to a single token can occur simultaneously.
    IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
    IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
    IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
          ; end fault reporting
    return dest[31:0];
}         ; end of FIXUPIMM_SP()

VFIXUPIMMPS (EVEX)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1) AND (SRC2 *is memory*)
                  THEN
                       DEST[i+31:i] <- FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[31:0], imm8 [7:0])
                  ELSE
                       DEST[i+31:i] <- FIXUPIMM_SP(DEST[i+31:i], SRC1[i+31:i], SRC2[i+31:i], imm8 [7:0])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE DEST[i+31:i] <- 0          ; zeroing-masking
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Immediate Control Description:




                                                                 7 6 5 4 3 2 1 0

                           + INF      ->       #IE
                           - VE       ->       #IE
                           - INF      ->       #IE
                            SNaN      ->       #IE
                            ONE       ->       #IE
                            ONE       ->       #ZE
                            ZERO      ->       #IE
                            ZERO      ->       #ZE

                                 Figure 5-10. VFIXUPIMMPS Immediate Control Description


Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMPS __m512 _mm512_fixupimm_ps( __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_ps( __mmask16 k, __m512 a, __m512i tbl, int imm);
VFIXUPIMMPS __m512 _mm512_fixupimm_round_ps( __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_mask_fixupimm_round_ps(__m512 s, __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m512 _mm512_maskz_fixupimm_round_ps( __mmask16 k, __m512 a, __m512i tbl, int imm, int sae);
VFIXUPIMMPS __m256 _mm256_fixupimm_ps( __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m256 _mm256_mask_fixupimm_ps(__m256 s, __mmask8 k, __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m256 _mm256_maskz_fixupimm_ps( __mmask8 k, __m256 a, __m256i tbl, int imm);
VFIXUPIMMPS __m128 _mm_fixupimm_ps( __m128 a, __m128i tbl, int imm);
VFIXUPIMMPS __m128 _mm_mask_fixupimm_ps(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMPS __m128 _mm_maskz_fixupimm_ps( __mmask8 k, __m128 a, __m128i tbl, int imm);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VFIXUPIMMSD
description:
VFIXUPIMMSD-Fix Up Special Scalar Float64 Value
 Opcode/                            Op /   64/32       CPUID      Description
 Instruction                        En     bit Mode    Feature
                                           Support     Flag
 EVEX.NDS.LIG.66.0F3A.W1 55 /r ib   T1S    V/V         AVX512F    Fix up a float64 number in the low quadword element of
 VFIXUPIMMSD xmm1 {k1}{z},                                        xmm2 using scalar int32 table in xmm3/m64 and store the
 xmm2, xmm3/m64{sae}, imm8                                        result in xmm1.



                                             Instruction Operand Encoding
      Op/En               Operand 1                   Operand 2                 Operand 3                   Operand 4
       T1S             ModRM:reg (r, w)               EVEX.vvvv             ModRM:r/m (r)                      Imm8

Description
Perform a fix-up of the low quadword element encoded in double-precision floating-point format in the first source
operand (the second operand) using a 32-bit, two-level look-up table specified in the low quadword element of the
second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-up is
selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action of
0000b preserves the corresponding element of the first operand. The fixed-up element from the first source
operand or the preserved element in the first operand becomes the low quadword element of the destination
operand (the first operand). Bits 127:64 of the destination operand is copied from the corresponding bits of the first
source operand. The destination and first source operands are XMM registers. The second source operand can be a
XMM register or a 64- bit memory location.
The two-level look-up table perform a fix-up of each DP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one source
so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-
rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

Operation
enum TOKEN_TYPE
{
   QNAN_TOKEN <- 0,
   SNAN_TOKEN <- 1,
   ZERO_VALUE_TOKEN <- 2,
   POS_ONE_VALUE_TOKEN <- 3,
   NEG_INF_TOKEN <- 4,
   POS_INF_TOKEN <- 5,
   NEG_VALUE_TOKEN <- 6,
   POS_VALUE_TOKEN <- 7
}





FIXUPIMM_DP (dest[63:0], src1[63:0],tbl3[63:0], imm8 [7:0]){
    tsrc[63:0] <- ((src1[62:52] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[63:0]
    CASE(tsrc[63:0] of TOKEN_TYPE) {
         QNAN_TOKEN: j <- 0;
         SNAN_TOKEN: j <- 1;
         ZERO_VALUE_TOKEN: j <- 2;
         POS_ONE_VALUE_TOKEN: j <- 3;
         NEG_INF_TOKEN: j <- 4;
         POS_INF_TOKEN: j <- 5;
         NEG_VALUE_TOKEN: j <- 6;
         POS_VALUE_TOKEN: j <- 7;
    }        ; end source special CASE(tsrc...)

    ; The required response from src3 table is extracted
    token_response[3:0] = tbl3[3+4*j:4*j];

    CASE(token_response[3:0]) {
        0000: dest[63:0] <- dest[63:0]         ; preserve content of DEST
        0001: dest[63:0] <- tsrc[63:0];        ; pass through src1 normal input value, denormal as zero
        0010: dest[63:0] <- QNaN(tsrc[63:0]);
        0011: dest[63:0] <- QNAN_Indefinite;
        0100:dest[63:0] <- -INF;
        0101: dest[63:0] <- +INF;
        0110: dest[63:0] <- tsrc.sign? -INF : +INF;
        0111: dest[63:0] <- -0;
        1000: dest[63:0] <- +0;
        1001: dest[63:0] <- -1;
        1010: dest[63:0] <- +1;
        1011: dest[63:0] <- 1/2;
        1100: dest[63:0] <- 90.0;
        1101: dest[63:0] <- PI/2;
        1110: dest[63:0] <- MAX_FLOAT;
        1111: dest[63:0] <- -MAX_FLOAT;
    }       ; end of token_response CASE

    ; The required fault reporting from imm8 is extracted
    ; TOKENs are mutually exclusive and TOKENs priority defines the order.
    ; Multiple faults related to a single token can occur simultaneously.
    IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
    IF (tsrc[63:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
    IF (tsrc[63:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
    IF (tsrc[63:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
          ; end fault reporting
    return dest[63:0];
}         ; end of FIXUPIMM_DP()





VFIXUPIMMSD (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[63:0] <- FIXUPIMM_DP(DEST[63:0], SRC1[63:0], SRC2[63:0], imm8 [7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE DEST[63:0] <- 0          ; zeroing-masking
         FI
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0


Immediate Control Description:




                                                                    7 6 5 4 3 2 1 0

                          + INF     ->       #IE
                          - VE      ->       #IE
                          - INF     ->       #IE
                           SNaN     ->       #IE
                           ONE      ->       #IE
                           ONE      ->       #ZE
                           ZERO     ->       #IE
                           ZERO     ->       #ZE

                               Figure 5-11. VFIXUPIMMSD Immediate Control Description


Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMSD __m128d _mm_fixupimm_sd( __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_mask_fixupimm_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_maskz_fixupimm_sd( __mmask8 k, __m128d a, __m128i tbl, int imm);
VFIXUPIMMSD __m128d _mm_fixupimm_round_sd( __m128d a, __m128i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_mask_fixupimm_round_sd(__m128d s, __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);
VFIXUPIMMSD __m128d _mm_maskz_fixupimm_round_sd( __mmask8 k, __m128d a, __m128i tbl, int imm, int sae);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VFIXUPIMMSS
description:
VFIXUPIMMSS-Fix Up Special Scalar Float32 Value
 Opcode/                                  Op /    64/32      CPUID     Description
 Instruction                              En      bit Mode   Feature
                                                  Support    Flag
 EVEX.NDS.LIG.66.0F3A.W0 55 /r ib         T1S     V/V        AVX512F   Fix up a float32 number in the low doubleword element
 VFIXUPIMMSS xmm1 {k1}{z}, xmm2,                                       in xmm2 using scalar int32 table in xmm3/m32 and store
 xmm3/m32{sae}, imm8                                                   the result in xmm1.



                                                  Instruction Operand Encoding
       Op/En                  Operand 1                  Operand 2               Operand 3                  Operand 4
        T1S                ModRM:reg (r, w)              EVEX.vvvv             ModRM:r/m (r)                  Imm8

Description
Perform a fix-up of the low doubleword element encoded in single-precision floating-point format in the first source
operand (the second operand) using a 32-bit, two-level look-up table specified in the low doubleword element of
the second source operand (the third operand) with exception reporting specifier imm8. The element that is fixed-
up is selected by mask bit of 1 specified in the opmask k1. Mask bit of 0 in the opmask k1 or table response action
of 0000b preserves the corresponding element of the first operand. The fixed-up element from the first source
operand or the preserved element in the first operand becomes the low doubleword element of the destination
operand (the first operand) Bits 127:32 of the destination operand is copied from the corresponding bits of the first
source operand. The destination and first source operands are XMM registers. The second source operand can be a
XMM register or a 32-bit memory location.
The two-level look-up table perform a fix-up of each SP FP input data in the first source operand by decoding the
input data encoding into 8 token types. A response table is defined for each token type that converts the input
encoding in the first source operand with one of 16 response actions.
This instruction is specifically intended for use in fixing up the results of arithmetic calculations involving one
source so that they match the spec, although it is generally useful for fixing up the results of multiple-instruction
sequences to reflect special-number inputs. For example, consider rcp(0). Input 0 to rcp, and you should get INF
according to the DX10 spec. However, evaluating rcp via Newton-Raphson, where x=approx(1/0), yields an incor-
rect result. To deal with this, VFIXUPIMMPD can be used after the N-R reciprocal sequence to set the result to the
correct value (i.e. INF when the input is 0).
If MXCSR.DAZ is not set, denormal input elements in the first source operand are considered as normal inputs and
do not trigger any fixup nor fault reporting.
Imm8 is used to set the required flags reporting. It supports #ZE and #IE fault reporting (see details below).
MXCSR.DAZ is used and refer to zmm2 only (i.e. zmm1 is not considered as zero in case MXCSR.DAZ is set).
MXCSR mask bits are ignored and are treated as if all mask bits are set to masked response). If any of the imm8
bits is set and the condition met for fault reporting, MXCSR.IE or MXCSR.ZE might be updated.

Operation
enum TOKEN_TYPE
{
   QNAN_TOKEN <- 0,
   SNAN_TOKEN <- 1,
   ZERO_VALUE_TOKEN <- 2,
   POS_ONE_VALUE_TOKEN <- 3,
   NEG_INF_TOKEN <- 4,
   POS_INF_TOKEN <- 5,
   NEG_VALUE_TOKEN <- 6,
   POS_VALUE_TOKEN <- 7
}





FIXUPIMM_SP (dest[31:0], src1[31:0],tbl3[31:0], imm8 [7:0]){
    tsrc[31:0] <- ((src1[30:23] = 0) AND (MXCSR.DAZ =1)) ? 0.0 : src1[31:0]
    CASE(tsrc[63:0] of TOKEN_TYPE) {
         QNAN_TOKEN: j <- 0;
         SNAN_TOKEN: j <- 1;
         ZERO_VALUE_TOKEN: j <- 2;
         POS_ONE_VALUE_TOKEN: j <- 3;
         NEG_INF_TOKEN: j <- 4;
         POS_INF_TOKEN: j <- 5;
         NEG_VALUE_TOKEN: j <- 6;
         POS_VALUE_TOKEN: j = 7;
    }        ; end source special CASE(tsrc...)

    ; The required response from src3 table is extracted
    token_response[3:0] = tbl3[3+4*j:4*j];

    CASE(token_response[3:0]) {
        0000: dest[31:0] <- dest[31:0];        ; preserve content of DEST
        0001: dest[31:0] <- tsrc[31:0];        ; pass through src1 normal input value, denormal as zero
        0010: dest[31:0] <- QNaN(tsrc[31:0]);
        0011: dest[31:0] <- QNAN_Indefinite;
        0100: dest[31:0] <- -INF;
        0101: dest[31:0] <- +INF;
        0110: dest[31:0] <- tsrc.sign? -INF : +INF;
        0111: dest[31:0] <- -0;
        1000: dest[31:0] <- +0;
        1001: dest[31:0] <- -1;
        1010: dest[31:0] <- +1;
        1011: dest[31:0] <- 1/2;
        1100: dest[31:0] <- 90.0;
        1101: dest[31:0] <- PI/2;
        1110: dest[31:0] <- MAX_FLOAT;
        1111: dest[31:0] <- -MAX_FLOAT;
    }       ; end of token_response CASE

    ; The required fault reporting from imm8 is extracted
    ; TOKENs are mutually exclusive and TOKENs priority defines the order.
    ; Multiple faults related to a single token can occur simultaneously.
    IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[0] then set #ZE;
    IF (tsrc[31:0] of TOKEN_TYPE: ZERO_VALUE_TOKEN) AND imm8[1] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[2] then set #ZE;
    IF (tsrc[31:0] of TOKEN_TYPE: ONE_VALUE_TOKEN) AND imm8[3] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: SNAN_TOKEN) AND imm8[4] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: NEG_INF_TOKEN) AND imm8[5] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: NEG_VALUE_TOKEN) AND imm8[6] then set #IE;
    IF (tsrc[31:0] of TOKEN_TYPE: POS_INF_TOKEN) AND imm8[7] then set #IE;
          ; end fault reporting
    return dest[31:0];
}         ; end of FIXUPIMM_SP()





VFIXUPIMMSS (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[31:0] <- FIXUPIMM_SP(DEST[31:0], SRC1[31:0], SRC2[31:0], imm8 [7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE DEST[31:0] <- 0          ; zeroing-masking
         FI
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0



Immediate Control Description:




                                                                    7 6 5 4 3 2 1 0

                            + INF     ->           #IE
                            - VE      ->           #IE
                            - INF     ->           #IE
                             SNaN     ->           #IE
                             ONE      ->           #IE
                             ONE      ->           #ZE
                             ZERO     ->           #IE
                             ZERO     ->           #ZE

                                  Figure 5-12. VFIXUPIMMSS Immediate Control Description


Intel C/C++ Compiler Intrinsic Equivalent
VFIXUPIMMSS __m128 _mm_fixupimm_ss( __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_mask_fixupimm_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_maskz_fixupimm_ss( __mmask8 k, __m128 a, __m128i tbl, int imm);
VFIXUPIMMSS __m128 _mm_fixupimm_round_ss( __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_mask_fixupimm_round_ss(__m128 s, __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);
VFIXUPIMMSS __m128 _mm_maskz_fixupimm_round_ss( __mmask8 k, __m128 a, __m128i tbl, int imm, int sae);

SIMD Floating-Point Exceptions

Zero, Invalid

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VFMADD132PD
description:
VFMADD132PD/VFMADD213PD/VFMADD231PD-Fused Multiply-Add of Packed Double-
Precision Floating-Point Values
 Opcode/                                Op/     64/32       CPUID          Description
 Instruction                            En      bit Mode    Feature
                                                Support     Flag
 VEX.NDS.128.66.0F38.W1 98 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD132PD xmm1, xmm2,                                                   values from xmm1 and xmm3/mem, add to xmm2
 xmm3/m128                                                                 and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 A8 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD213PD xmm1, xmm2,                                                   values from xmm1 and xmm2, add to xmm3/mem
 xmm3/m128                                                                 and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 B8 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD231PD xmm1, xmm2,                                                   values from xmm2 and xmm3/mem, add to xmm1
 xmm3/m128                                                                 and put result in xmm1.
 VEX.NDS.256.66.0F38.W1 98 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD132PD ymm1, ymm2,                                                   values from ymm1 and ymm3/mem, add to ymm2
 ymm3/m256                                                                 and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 A8 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD213PD ymm1, ymm2,                                                   values from ymm1 and ymm2, add to ymm3/mem
 ymm3/m256                                                                 and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 B8 /r           RVM     V/V         FMA            Multiply packed double-precision floating-point
 VFMADD231PD ymm1, ymm2,                                                   values from ymm2 and ymm3/mem, add to ymm1
 ymm3/m256                                                                 and put result in ymm1.
 EVEX.NDS.128.66.0F38.W1 98 /r          RVM     V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD132PD xmm1 {k1}{z}, xmm2,                            AVX512F        values from xmm1 and xmm3/m128/m64bcst, add
 xmm3/m128/m64bcst                                                         to xmm2 and put result in xmm1.
 EVEX.NDS.128.66.0F38.W1 A8 /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD213PD xmm1 {k1}{z}, xmm2,                            AVX512F        values from xmm1 and xmm2, add to
 xmm3/m128/m64bcst                                                         xmm3/m128/m64bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W1 B8 /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD231PD xmm1 {k1}{z}, xmm2,                            AVX512F        values from xmm2 and xmm3/m128/m64bcst, add
 xmm3/m128/m64bcst                                                         to xmm1 and put result in xmm1.
 EVEX.NDS.256.66.0F38.W1 98 /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD132PD ymm1 {k1}{z}, ymm2,                            AVX512F        values from ymm1 and ymm3/m256/m64bcst, add
 ymm3/m256/m64bcst                                                         to ymm2 and put result in ymm1.
 EVEX.NDS.256.66.0F38.W1 A8 /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD213PD ymm1 {k1}{z}, ymm2,                            AVX512F        values from ymm1 and ymm2, add to
 ymm3/m256/m64bcst                                                         ymm3/m256/m64bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W1 B8 /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point
 VFMADD231PD ymm1 {k1}{z}, ymm2,                            AVX512F        values from ymm2 and ymm3/m256/m64bcst, add
 ymm3/m256/m64bcst                                                         to ymm1 and put result in ymm1.
 EVEX.NDS.512.66.0F38.W1 98 /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point
 VFMADD132PD zmm1 {k1}{z}, zmm2,                                           values from zmm1 and zmm3/m512/m64bcst, add
 zmm3/m512/m64bcst{er}                                                     to zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 A8 /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point
 VFMADD213PD zmm1 {k1}{z}, zmm2,                                           values from zmm1 and zmm2, add to
 zmm3/m512/m64bcst{er}                                                     zmm3/m512/m64bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 B8 /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point
 VFMADD231PD zmm1 {k1}{z}, zmm2,                                           values from zmm2 and zmm3/m512/m64bcst, add
 zmm3/m512/m64bcst{er}                                                     to zmm1 and put result in zmm1.





                                                Instruction Operand Encoding
      Op/En                Operand 1                  Operand 2                    Operand 3                  Operand 4
       RVM             ModRM:reg (r, w)              VEX.vvvv (r)                ModRM:r/m (r)                   NA
        FV             ModRM:reg (r, w)             EVEX.vvvv (r)                ModRM:r/m (r)                   NA

Description
Performs a set of SIMD multiply-add computation on packed double-precision floating-point values using three
source operands and writes the multiply-add results in the destination operand. The destination operand is also the
first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD
register or a memory location.
VFMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source
operand to the two, four or eight packed double-precision floating-point values in the third source operand, adds
the infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in
the second source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
VFMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand,
adds the infinite precision intermediate result to the two, four or eight packed double-precision floating-point
values in the third source operand, performs rounding and stores the resulting two, four or eight packed double-
precision floating-point values to the destination operand (first source operand).
VFMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand, adds the
infinite precision intermediate result to the two, four or eight packed double-precision floating-point values in the
first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in
reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The
destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.





Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxPD __m512d _mm512_fmadd_pd(__m512d a, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_fmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_mask_fmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_maskz_fmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMADDxxxPD __m512d _mm512_mask3_fmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMADDxxxPD __m512d _mm512_mask_fmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_maskz_fmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDxxxPD __m512d _mm512_mask3_fmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDxxxPD __m256d _mm256_mask_fmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMADDxxxPD __m256d _mm256_maskz_fmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMADDxxxPD __m256d _mm256_mask3_fmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_mask_fmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDxxxPD __m128d _mm_maskz_fmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDxxxPD __m128d _mm_mask3_fmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDxxxPD __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);
VFMADDxxxPD __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMADD132PS
description:
VFMADD132PS/VFMADD213PS/VFMADD231PS-Fused Multiply-Add of Packed Single-
Precision Floating-Point Values
 Opcode/                                     Op/     64/32       CPUID         Description
 Instruction                                 En      bit Mode    Feature
                                                     Support     Flag
 VEX.NDS.128.66.0F38.W0 98 /r                RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD132PS xmm1, xmm2,                                                       from xmm1 and xmm3/mem, add to xmm2 and put
 xmm3/m128                                                                     result in xmm1.
 VEX.NDS.128.66.0F38.W0 A8 /r                RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD213PS xmm1, xmm2,                                                       from xmm1 and xmm2, add to xmm3/mem and put
 xmm3/m128                                                                     result in xmm1.
 VEX.NDS.128.66.0F38.W0 B8 /r                RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD231PS xmm1, xmm2,                                                       from xmm2 and xmm3/mem, add to xmm1 and put
 xmm3/m128                                                                     result in xmm1.
 VEX.NDS.256.66.0F38.W0 98 /r                RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD132PS ymm1, ymm2,                                                       from ymm1 and ymm3/mem, add to ymm2 and put
 ymm3/m256                                                                     result in ymm1.
 VEX.NDS.256.66.0F38.W0 A8 /r                RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD213PS ymm1, ymm2,                                                       from ymm1 and ymm2, add to ymm3/mem and put
 ymm3/m256                                                                     result in ymm1.
 VEX.NDS.256.66.0F38.0 B8 /r                 RVM     V/V         FMA           Multiply packed single-precision floating-point values
 VFMADD231PS ymm1, ymm2,                                                       from ymm2 and ymm3/mem, add to ymm1 and put
 ymm3/m256                                                                     result in ymm1.
 EVEX.NDS.128.66.0F38.W0 98 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD132PS xmm1 {k1}{z}, xmm2,                                 AVX512F       from xmm1 and xmm3/m128/m32bcst, add to
 xmm3/m128/m32bcst                                                             xmm2 and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 A8 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD213PS xmm1 {k1}{z}, xmm2,                                 AVX512F       from xmm1 and xmm2, add to
 xmm3/m128/m32bcst                                                             xmm3/m128/m32bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 B8 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD231PS xmm1 {k1}{z}, xmm2,                                 AVX512F       from xmm2 and xmm3/m128/m32bcst, add to
 xmm3/m128/m32bcst                                                             xmm1 and put result in xmm1.
 EVEX.NDS.256.66.0F38.W0 98 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD132PS ymm1 {k1}{z}, ymm2,                                 AVX512F       from ymm1 and ymm3/m256/m32bcst, add to
 ymm3/m256/m32bcst                                                             ymm2 and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 A8 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD213PS ymm1 {k1}{z}, ymm2,                                 AVX512F       from ymm1 and ymm2, add to
 ymm3/m256/m32bcst                                                             ymm3/m256/m32bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 B8 /r               FV      V/V         AVX512VL      Multiply packed single-precision floating-point values
 VFMADD231PS ymm1 {k1}{z}, ymm2,                                 AVX512F       from ymm2 and ymm3/m256/m32bcst, add to
 ymm3/m256/m32bcst                                                             ymm1 and put result in ymm1.
 EVEX.NDS.512.66.0F38.W0 98 /r               FV      V/V         AVX512F       Multiply packed single-precision floating-point values
 VFMADD132PS zmm1 {k1}{z}, zmm2,                                               from zmm1 and zmm3/m512/m32bcst, add to
 zmm3/m512/m32bcst{er}                                                         zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 A8 /r               FV      V/V         AVX512F       Multiply packed single-precision floating-point values
 VFMADD213PS zmm1 {k1}{z}, zmm2,                                               from zmm1 and zmm2, add to
 zmm3/m512/m32bcst{er}                                                         zmm3/m512/m32bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 B8 /r               FV      V/V         AVX512F       Multiply packed single-precision floating-point values
 VFMADD231PS zmm1 {k1}{z}, zmm2,                                               from zmm2 and zmm3/m512/m32bcst, add to
 zmm3/m512/m32bcst{er}                                                         zmm1 and put result in zmm1.





                                            Instruction Operand Encoding
      Op/En             Operand 1                 Operand 2                   Operand 3                    Operand 4
       RVM           ModRM:reg (r, w)            VEX.vvvv (r)               ModRM:r/m (r)                      NA
        FV           ModRM:reg (r, w)           EVEX.vvvv (r)               ModRM:r/m (r)                      NA

Description
Performs a set of SIMD multiply-add computation on packed single-precision floating-point values using three
source operands and writes the multiply-add results in the destination operand. The destination operand is also the
first source operand. The second operand must be a SIMD register. The third source operand can be a SIMD
register or a memory location.
VFMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the infinite precision intermediate result to the four, eight or sixteen packed single-precision
floating-point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen
packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) is a ZMM register and encoded in
reg_field. The second source operand is a ZMM register and encoded in EVEX.vvvv. The third source operand is a
ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The
destination operand is conditionally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.





Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-4
ELSEIF (VEX.256)
    MAXNUM <- 8
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-4
ELSEIF (VEX.256)
    MAXNUM <- 8
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-4
ELSEIF (VEX.256)
    MAXNUM <- 8
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxPS __m512 _mm512_fmadd_ps(__m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_fmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_mask_fmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_maskz_fmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMADDxxxPS __m512 _mm512_mask_fmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_maskz_fmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMADDxxxPS __m512 _mm512_mask3_fmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDxxxPS __m256 _mm256_mask_fmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMADDxxxPS __m256 _mm256_maskz_fmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMADDxxxPS __m256 _mm256_mask3_fmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMADDxxxPS __m128 _mm_mask_fmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_maskz_fmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxPS __m128 _mm_mask3_fmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxPS __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);
VFMADDxxxPS __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMADD132SD
description:
VFMADD132SD/VFMADD213SD/VFMADD231SD-Fused Multiply-Add of Scalar Double-
Precision Floating-Point Values
 Opcode/                                 Op/      64/32      CPUID         Description
 Instruction                             En       bit Mode   Feature
                                                  Support    Flag
 VEX.DDS.LIG.66.0F38.W1 99 /r            RVM      V/V        FMA          Multiply scalar double-precision floating-point value
 VFMADD132SD xmm1, xmm2,                                                  from xmm1 and xmm3/m64, add to xmm2 and put
 xmm3/m64                                                                 result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 A9 /r            RVM      V/V        FMA          Multiply scalar double-precision floating-point value
 VFMADD213SD xmm1, xmm2,                                                  from xmm1 and xmm2, add to xmm3/m64 and put
 xmm3/m64                                                                 result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 B9 /r            RVM      V/V        FMA          Multiply scalar double-precision floating-point value
 VFMADD231SD xmm1, xmm2,                                                  from xmm2 and xmm3/m64, add to xmm1 and put
 xmm3/m64                                                                 result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 99 /r           T1S      V/V        AVX512F      Multiply scalar double-precision floating-point value
 VFMADD132SD xmm1 {k1}{z}, xmm2,                                          from xmm1 and xmm3/m64, add to xmm2 and put
 xmm3/m64{er}                                                             result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 A9 /r           T1S      V/V        AVX512F      Multiply scalar double-precision floating-point value
 VFMADD213SD xmm1 {k1}{z}, xmm2,                                          from xmm1 and xmm2, add to xmm3/m64 and put
 xmm3/m64{er}                                                             result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 B9 /r           T1S      V/V        AVX512F      Multiply scalar double-precision floating-point value
 VFMADD231SD xmm1 {k1}{z}, xmm2,                                          from xmm2 and xmm3/m64, add to xmm1 and put
 xmm3/m64{er}                                                             result in xmm1.



                                               Instruction Operand Encoding
       Op/En             Operand 1                   Operand 2                  Operand 3                    Operand 4
       RVM            ModRM:reg (r, w)              VEX.vvvv (r)              ModRM:r/m (r)                      NA
        T1S           ModRM:reg (r, w)             EVEX.vvvv (r)              ModRM:r/m (r)                      NA

Description
Performs a SIMD multiply-add computation on the low double-precision floating-point values using three source
operands and writes the multiply-add result in the destination operand. The destination operand is also the first
source operand. The first and second operand are XMM registers. The third source operand can be an XMM register
or a 64-bit memory location.
VFMADD132SD: Multiplies the low double-precision floating-point value from the first source operand to the low
double-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low double-precision floating-point values in the second source operand, performs rounding and stores the
resulting double-precision floating-point value to the destination operand (first source operand).
VFMADD213SD: Multiplies the low double-precision floating-point value from the second source operand to the low
double-precision floating-point value in the first source operand, adds the infinite precision intermediate result to
the low double-precision floating-point value in the third source operand, performs rounding and stores the
resulting double-precision floating-point value to the destination operand (first source operand).
VFMADD231SD: Multiplies the low double-precision floating-point value from the second source to the low double-
precision floating-point value in the third source operand, adds the infinite precision intermediate result to the low
double-precision floating-point value in the first source operand, performs rounding and stores the resulting
double-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination is updated according to the writemask.





Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0





VFMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFMADD132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <- MAX_VL-1:128RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:63] <- DEST[127:63]
DEST[MAX_VL-1:128] <- 0

VFMADD213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:63] <- DEST[127:63]
DEST[MAX_VL-1:128] <- 0

VFMADD231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:63] <- DEST[127:63]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxSD __m128d _mm_fmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_mask_fmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDxxxSD __m128d _mm_maskz_fmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDxxxSD __m128d _mm_mask3_fmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDxxxSD __m128d _mm_mask_fmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_maskz_fmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFMADDxxxSD __m128d _mm_mask3_fmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFMADDxxxSD __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFMADD132SS
description:
VFMADD132SS/VFMADD213SS/VFMADD231SS-Fused Multiply-Add of Scalar Single-Precision
Floating-Point Values
 Opcode/                                     Op /     64/32      CPUID         Description
 Instruction                                 En       bit Mode   Feature
                                                      Support    Flag
 VEX.DDS.LIG.66.0F38.W0 99 /r                RVM      V/V        FMA           Multiply scalar single-precision floating-point value
 VFMADD132SS xmm1, xmm2,                                                       from xmm1 and xmm3/m32, add to xmm2 and put
 xmm3/m32                                                                      result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 A9 /r                RVM      V/V        FMA           Multiply scalar single-precision floating-point value
 VFMADD213SS xmm1, xmm2,                                                       from xmm1 and xmm2, add to xmm3/m32 and put
 xmm3/m32                                                                      result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 B9 /r                RVM      V/V        FMA           Multiply scalar single-precision floating-point value
 VFMADD231SS xmm1, xmm2,                                                       from xmm2 and xmm3/m32, add to xmm1 and put
 xmm3/m32                                                                      result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 99 /r               T1S      V/V        AVX512F       Multiply scalar single-precision floating-point value
 VFMADD132SS xmm1 {k1}{z}, xmm2,                                               from xmm1 and xmm3/m32, add to xmm2 and put
 xmm3/m32{er}                                                                  result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 A9 /r               T1S      V/V        AVX512F       Multiply scalar single-precision floating-point value
 VFMADD213SS xmm1 {k1}{z}, xmm2,                                               from xmm1 and xmm2, add to xmm3/m32 and put
 xmm3/m32{er}                                                                  result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 B9 /r               T1S      V/V        AVX512F       Multiply scalar single-precision floating-point value
 VFMADD231SS xmm1 {k1}{z}, xmm2,                                               from xmm2 and xmm3/m32, add to xmm1 and put
 xmm3/m32{er}                                                                  result in xmm1.



                                                   Instruction Operand Encoding
      Op/En                Operand 1                   Operand 2                    Operand 3                     Operand 4
       RVM              ModRM:reg (r, w)               VEX.vvvv (r)               ModRM:r/m (r)                       NA
       T1S              ModRM:reg (r, w)              EVEX.vvvv (r)               ModRM:r/m (r)                       NA

Description
Performs a SIMD multiply-add computation on single-precision floating-point values using three source operands
and writes the multiply-add results in the destination operand. The destination operand is also the first source
operand. The first and second operands are XMM registers. The third source operand can be a XMM register or a
32-bit memory location.
VFMADD132SS: Multiplies the low single-precision floating-point value from the first source operand to the low
single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the second source operand, performs rounding and stores the
resulting single-precision floating-point value to the destination operand (first source operand).
VFMADD213SS: Multiplies the low single-precision floating-point value from the second source operand to the low
single-precision floating-point value in the first source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the third source operand, performs rounding and stores the
resulting single-precision floating-point value to the destination operand (first source operand).
VFMADD231SS: Multiplies the low single-precision floating-point value from the second source operand to the low
single-precision floating-point value in the third source operand, adds the infinite precision intermediate result to
the low single-precision floating-point value in the first source operand, performs rounding and stores the resulting
single-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.





EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0





VFMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0]] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] + DEST[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFMADDxxxSS __m128 _mm_fmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask_fmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_maskz_fmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDxxxSS __m128 _mm_mask3_fmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDxxxSS __m128 _mm_mask_fmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_maskz_fmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFMADDxxxSS __m128 _mm_mask3_fmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMADDxxxSS __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFMADDSUB132PD
description:
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD-Fused Multiply-Alternating
Add/Subtract of Packed Double-Precision Floating-Point Values
 Opcode/                              Op /    64/32       CPUID        Description
 Instruction                          En      bit Mode    Feature
                                              Support     Flag
 VEX.DDS.128.66.0F38.W1 96 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB132PD xmm1, xmm2,                                            from xmm1 and xmm3/mem, add/subtract elements in
 xmm3/m128                                                             xmm2 and put result in xmm1.
 VEX.DDS.128.66.0F38.W1 A6 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB213PD xmm1, xmm2,                                            from xmm1 and xmm2, add/subtract elements in
 xmm3/m128                                                             xmm3/mem and put result in xmm1.
 VEX.DDS.128.66.0F38.W1 B6 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB231PD xmm1, xmm2,                                            from xmm2 and xmm3/mem, add/subtract elements in
 xmm3/m128                                                             xmm1 and put result in xmm1.
 VEX.DDS.256.66.0F38.W1 96 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB132PD ymm1, ymm2,                                            from ymm1 and ymm3/mem, add/subtract elements in
 ymm3/m256                                                             ymm2 and put result in ymm1.
 VEX.DDS.256.66.0F38.W1 A6 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB213PD ymm1, ymm2,                                            from ymm1 and ymm2, add/subtract elements in
 ymm3/m256                                                             ymm3/mem and put result in ymm1.
 VEX.DDS.256.66.0F38.W1 B6 /r         RVM     V/V         FMA          Multiply packed double-precision floating-point values
 VFMADDSUB231PD ymm1, ymm2,                                            from ymm2 and ymm3/mem, add/subtract elements in
 ymm3/m256                                                             ymm1 and put result in ymm1.
 EVEX.DDS.128.66.0F38.W1 A6 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB213PD xmm1 {k1}{z},                             AVX512F      from xmm1 and xmm2, add/subtract elements in
 xmm2, xmm3/m128/m64bcst                                               xmm3/m128/m64bcst and put result in xmm1 subject to
                                                                       writemask k1.
 EVEX.DDS.128.66.0F38.W1 B6 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB231PD xmm1 {k1}{z},                             AVX512F      from xmm2 and xmm3/m128/m64bcst, add/subtract
 xmm2, xmm3/m128/m64bcst                                               elements in xmm1 and put result in xmm1 subject to
                                                                       writemask k1.
 EVEX.DDS.128.66.0F38.W1 96 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB132PD xmm1 {k1}{z},                             AVX512F      from xmm1 and xmm3/m128/m64bcst, add/subtract
 xmm2, xmm3/m128/m64bcst                                               elements in xmm2 and put result in xmm1 subject to
                                                                       writemask k1.
 EVEX.DDS.256.66.0F38.W1 A6 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB213PD ymm1 {k1}{z},                             AVX512F      from ymm1 and ymm2, add/subtract elements in
 ymm2, ymm3/m256/m64bcst                                               ymm3/m256/m64bcst and put result in ymm1 subject to
                                                                       writemask k1.
 EVEX.DDS.256.66.0F38.W1 B6 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB231PD ymm1 {k1}{z},                             AVX512F      from ymm2 and ymm3/m256/m64bcst, add/subtract
 ymm2, ymm3/m256/m64bcst                                               elements in ymm1 and put result in ymm1 subject to
                                                                       writemask k1.
 EVEX.DDS.256.66.0F38.W1 96 /r        FV      V/V         AVX512VL     Multiply packed double-precision floating-point values
 VFMADDSUB132PD ymm1 {k1}{z},                             AVX512F      from ymm1 and ymm3/m256/m64bcst, add/subtract
 ymm2, ymm3/m256/m64bcst                                               elements in ymm2 and put result in ymm1 subject to
                                                                       writemask k1.




 Opcode/                                  Op /   64/32       CPUID       Description
 Instruction                              En     bit Mode    Feature
                                                 Support     Flag
 EVEX.DDS.512.66.0F38.W1 A6 /r            FV     V/V         AVX512F     Multiply packed double-precision floating-point values
 VFMADDSUB213PD zmm1 {k1}{z},                                            from zmm1and zmm2, add/subtract elements in
 zmm2, zmm3/m512/m64bcst{er}                                             zmm3/m512/m64bcst and put result in zmm1 subject to
                                                                         writemask k1.
 EVEX.DDS.512.66.0F38.W1 B6 /r            FV     V/V         AVX512F     Multiply packed double-precision floating-point values
 VFMADDSUB231PD zmm1 {k1}{z},                                            from zmm2 and zmm3/m512/m64bcst, add/subtract
 zmm2, zmm3/m512/m64bcst{er}                                             elements in zmm1 and put result in zmm1 subject to
                                                                         writemask k1.
 EVEX.DDS.512.66.0F38.W1 96 /r            FV     V/V         AVX512F     Multiply packed double-precision floating-point values
 VFMADDSUB132PD zmm1 {k1}{z},                                            from zmm1 and zmm3/m512/m64bcst, add/subtract
 zmm2, zmm3/m512/m64bcst{er}                                             elements in zmm2 and put result in zmm1 subject to
                                                                         writemask k1.


                                                 Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                 Operand 3                  Operand 4
       RVM             ModRM:reg (r, w)                VEX.vvvv (r)             ModRM:r/m (r)                     NA
       FV              ModRM:reg (r, w)                EVEX.vvvv (r)            ModRM:r/m (r)                     NA

Description
VFMADDSUB132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first
source operand to the two or four packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, adds the odd double-precision floating-point elements and subtracts the
even double-precision floating-point values in the second source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMADDSUB213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, adds the odd double-precision floating-point elements and
subtracts the even double-precision floating-point values in the third source operand, performs rounding and
stores the resulting two or four packed double-precision floating-point values to the destination operand (first
source operand).
VFMADDSUB231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the third source
operand. From the infinite precision intermediate result, adds the odd double-precision floating-point elements and
subtracts the even double-precision floating-point values in the first source operand, performs rounding and stores
the resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.





VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFMADDSUB132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] - SRC2[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]
FI

VFMADDSUB213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] - SRC3[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]
FI

VFMADDSUB231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] - DEST[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]
FI





VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
                   FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
                   FI;
             FI

        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_pd(__m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMADDSUBxxxPD __m512d _mm512_mask_fmaddsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_maskz_fmaddsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMADDSUBxxxPD __m512d _mm512_mask3_fmaddsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMADDSUBxxxPD __m256d _mm256_mask_fmaddsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMADDSUBxxxPD __m256d _mm256_maskz_fmaddsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMADDSUBxxxPD __m256d _mm256_mask3_fmaddsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMADDSUBxxxPD __m128d _mm_mask_fmaddsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_maskz_fmaddsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMADDSUBxxxPD __m128d _mm_mask3_fmaddsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMADDSUBxxxPD __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);
VFMADDSUBxxxPD __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMADDSUB132PS
description:
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS-Fused Multiply-Alternating
Add/Subtract of Packed Single-Precision Floating-Point Values
 Opcode/                           Op /    64/32       CPUID         Description
 Instruction                       En      bit Mode    Feature
                                           Support     Flag
 VEX.DDS.128.66.0F38.W0 96 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB132PS xmm1, xmm2,                                          xmm1 and xmm3/mem, add/subtract elements in xmm2
 xmm3/m128                                                           and put result in xmm1.
 VEX.DDS.128.66.0F38.W0 A6 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB213PS xmm1, xmm2,                                          xmm1 and xmm2, add/subtract elements in xmm3/mem
 xmm3/m128                                                           and put result in xmm1.
 VEX.DDS.128.66.0F38.W0 B6 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB231PS xmm1, xmm2,                                          xmm2 and xmm3/mem, add/subtract elements in xmm1
 xmm3/m128                                                           and put result in xmm1.
 VEX.DDS.256.66.0F38.W0 96 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB132PS ymm1, ymm2,                                          ymm1 and ymm3/mem, add/subtract elements in ymm2
 ymm3/m256                                                           and put result in ymm1.
 VEX.DDS.256.66.0F38.W0 A6 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB213PS ymm1, ymm2,                                          ymm1 and ymm2, add/subtract elements in ymm3/mem
 ymm3/m256                                                           and put result in ymm1.
 VEX.DDS.256.66.0F38.W0 B6 /r      RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMADDSUB231PS ymm1, ymm2,                                          ymm2 and ymm3/mem, add/subtract elements in ymm1
 ymm3/m256                                                           and put result in ymm1.
 EVEX.DDS.128.66.0F38.W0 A6 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB213PS xmm1 {k1}{z},                          AVX512F       xmm1 and xmm2, add/subtract elements in
 xmm2, xmm3/m128/m32bcst                                             xmm3/m128/m32bcst and put result in xmm1 subject to
                                                                     writemask k1.
 EVEX.DDS.128.66.0F38.W0 B6 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB231PS xmm1 {k1}{z},                          AVX512F       xmm2 and xmm3/m128/m32bcst, add/subtract elements
 xmm2, xmm3/m128/m32bcst                                             in xmm1 and put result in xmm1 subject to writemask k1.
 EVEX.DDS.128.66.0F38.W0 96 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB132PS xmm1 {k1}{z},                          AVX512F       xmm1 and xmm3/m128/m32bcst, add/subtract elements
 xmm2, xmm3/m128/m32bcst                                             in zmm2 and put result in xmm1 subject to writemask k1.
 EVEX.DDS.256.66.0F38.W0 A6 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB213PS ymm1 {k1}{z},                          AVX512F       ymm1 and ymm2, add/subtract elements in
 ymm2, ymm3/m256/m32bcst                                             ymm3/m256/m32bcst and put result in ymm1 subject to
                                                                     writemask k1.
 EVEX.DDS.256.66.0F38.W0 B6 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB231PS ymm1 {k1}{z},                          AVX512F       ymm2 and ymm3/m256/m32bcst, add/subtract elements
 ymm2, ymm3/m256/m32bcst                                             in ymm1 and put result in ymm1 subject to writemask k1.
 EVEX.DDS.256.66.0F38.W0 96 /r     FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMADDSUB132PS ymm1 {k1}{z},                          AVX512F       ymm1 and ymm3/m256/m32bcst, add/subtract elements
 ymm2, ymm3/m256/m32bcst                                             in ymm2 and put result in ymm1 subject to writemask k1.
 EVEX.DDS.512.66.0F38.W0 A6 /r     FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMADDSUB213PS zmm1 {k1}{z},                                        zmm1 and zmm2, add/subtract elements in
 zmm2, zmm3/m512/m32bcst{er}                                         zmm3/m512/m32bcst and put result in zmm1 subject to
                                                                     writemask k1.
 EVEX.DDS.512.66.0F38.W0 B6 /r     FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMADDSUB231PS zmm1 {k1}{z},                                        zmm2 and zmm3/m512/m32bcst, add/subtract elements
 zmm2, zmm3/m512/m32bcst{er}                                         in zmm1 and put result in zmm1 subject to writemask k1.
 EVEX.DDS.512.66.0F38.W0 96 /r     FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMADDSUB132PS zmm1 {k1}{z},                                        zmm1 and zmm3/m512/m32bcst, add/subtract elements
 zmm2, zmm3/m512/m32bcst{er}                                         in zmm2 and put result in zmm1 subject to writemask k1.





                                                Instruction Operand Encoding
       Op/En                Operand 1                  Operand 2                   Operand 3                  Operand 4
        RVM              ModRM:reg (r, w)             VEX.vvvv (r)               ModRM:r/m (r)                    NA
         FV              ModRM:reg (r, w)             EVEX.vvvv (r)              ModRM:r/m (r)                    NA

Description
VFMADDSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the corresponding packed single-precision floating-point values in the third source operand.
From the infinite precision intermediate result, adds the odd single-precision floating-point elements and subtracts
the even single-precision floating-point values in the second source operand, performs rounding and stores the
resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMADDSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and
subtracts the even single-precision floating-point values in the third source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMADDSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, adds the odd single-precision floating-point elements and
subtracts the even single-precision floating-point values in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.





Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMADDSUB132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADDSUB213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFMADDSUB231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) (4, 128), (8, 256),= (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
              IF j *is even*
                    THEN DEST[i+31:i] <-
                         RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
                    ELSE DEST[i+31:i] <-
                         RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
              FI
         ELSE
              IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
                        FI;
             FI

        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
                     ELSE DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+31:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADDSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
                        FI;



            FI
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
                     ELSE DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+31:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMADDSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_ps(__m512 a, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMADDSUBxxxPS __m512 _mm512_mask_fmaddsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_maskz_fmaddsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMADDSUBxxxPS __m512 _mm512_mask3_fmaddsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMADDSUBxxxPS __m256 _mm256_mask_fmaddsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMADDSUBxxxPS __m256 _mm256_maskz_fmaddsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMADDSUBxxxPS __m256 _mm256_mask3_fmaddsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMADDSUBxxxPS __m128 _mm_mask_fmaddsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMADDSUBxxxPS __m128 _mm_maskz_fmaddsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMADDSUBxxxPS __m128 _mm_mask3_fmaddsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMADDSUBxxxPS __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);
VFMADDSUBxxxPS __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMSUBADD132PD
description:
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD-Fused Multiply-Alternating
Subtract/Add of Packed Double-Precision Floating-Point Values
 Opcode/                                  Op /   64/32       CPUID         Description
 Instruction                              En     bit Mode    Feature
                                                 Support     Flag
 VEX.DDS.128.66.0F38.W1 97 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD132PD xmm1, xmm2,                                                from xmm1 and xmm3/mem, subtract/add elements
 xmm3/m128                                                                 in xmm2 and put result in xmm1.
 VEX.DDS.128.66.0F38.W1 A7 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD213PD xmm1, xmm2,                                                from xmm1 and xmm2, subtract/add elements in
 xmm3/m128                                                                 xmm3/mem and put result in xmm1.
 VEX.DDS.128.66.0F38.W1 B7 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD231PD xmm1, xmm2,                                                from xmm2 and xmm3/mem, subtract/add elements
 xmm3/m128                                                                 in xmm1 and put result in xmm1.
 VEX.DDS.256.66.0F38.W1 97 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD132PD ymm1, ymm2,                                                from ymm1 and ymm3/mem, subtract/add elements
 ymm3/m256                                                                 in ymm2 and put result in ymm1.
 VEX.DDS.256.66.0F38.W1 A7 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD213PD ymm1, ymm2,                                                from ymm1 and ymm2, subtract/add elements in
 ymm3/m256                                                                 ymm3/mem and put result in ymm1.
 VEX.DDS.256.66.0F38.W1 B7 /r             RVM    V/V         FMA           Multiply packed double-precision floating-point values
 VFMSUBADD231PD ymm1, ymm2,                                                from ymm2 and ymm3/mem, subtract/add elements
 ymm3/m256                                                                 in ymm1 and put result in ymm1.
 EVEX.DDS.128.66.0F38.W1 97 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD132PD xmm1 {k1}{z},                                AVX512F       from xmm1 and xmm3/m128/m64bcst, subtract/add
 xmm2, xmm3/m128/m64bcst                                                   elements in xmm2 and put result in xmm1 subject to
                                                                           writemask k1.
 EVEX.DDS.128.66.0F38.W1 A7 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD213PD xmm1 {k1}{z},                                AVX512F       from xmm1 and xmm2, subtract/add elements in
 xmm2, xmm3/m128/m64bcst                                                   xmm3/m128/m64bcst and put result in xmm1
                                                                           subject to writemask k1.
 EVEX.DDS.128.66.0F38.W1 B7 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD231PD xmm1 {k1}{z},                                AVX512F       from xmm2 and xmm3/m128/m64bcst, subtract/add
 xmm2, xmm3/m128/m64bcst                                                   elements in xmm1 and put result in xmm1 subject to
                                                                           writemask k1.
 EVEX.DDS.256.66.0F38.W1 97 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD132PD ymm1 {k1}{z},                                AVX512F       from ymm1 and ymm3/m256/m64bcst, subtract/add
 ymm2, ymm3/m256/m64bcst                                                   elements in ymm2 and put result in ymm1 subject to
                                                                           writemask k1.
 EVEX.DDS.256.66.0F38.W1 A7 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD213PD ymm1 {k1}{z},                                AVX512F       from ymm1 and ymm2, subtract/add elements in
 ymm2, ymm3/m256/m64bcst                                                   ymm3/m256/m64bcst and put result in ymm1
                                                                           subject to writemask k1.
 EVEX.DDS.256.66.0F38.W1 B7 /r            FV     V/V         AVX512VL      Multiply packed double-precision floating-point values
 VFMSUBADD231PD ymm1 {k1}{z},                                AVX512F       from ymm2 and ymm3/m256/m64bcst, subtract/add
 ymm2, ymm3/m256/m64bcst                                                   elements in ymm1 and put result in ymm1 subject to
                                                                           writemask k1.




 Opcode/                                   Op /    64/32        CPUID     Description
 Instruction                               En      bit Mode     Feature
                                                   Support      Flag
 EVEX.DDS.512.66.0F38.W1 97 /r             FV      V/V          AVX512F   Multiply packed double-precision floating-point values
 VFMSUBADD132PD zmm1 {k1}{z},                                             from zmm1 and zmm3/m512/m64bcst, subtract/add
 zmm2, zmm3/m512/m64bcst{er}                                              elements in zmm2 and put result in zmm1 subject to
                                                                          writemask k1.
 EVEX.DDS.512.66.0F38.W1 A7 /r             FV      V/V          AVX512F   Multiply packed double-precision floating-point values
 VFMSUBADD213PD zmm1 {k1}{z},                                             from zmm1 and zmm2, subtract/add elements in
 zmm2, zmm3/m512/m64bcst{er}                                              zmm3/m512/m64bcst and put result in zmm1 subject
                                                                          to writemask k1.
 EVEX.DDS.512.66.0F38.W1 B7 /r             FV      V/V          AVX512F   Multiply packed double-precision floating-point values
 VFMSUBADD231PD zmm1 {k1}{z},                                             from zmm2 and zmm3/m512/m64bcst, subtract/add
 zmm2, zmm3/m512/m64bcst{er}                                              elements in zmm1 and put result in zmm1 subject to
                                                                          writemask k1.


                                                  Instruction Operand Encoding
       Op/En               Operand 1                      Operand 2               Operand 3                   Operand 4
        RVM             ModRM:reg (r, w)                 VEX.vvvv (r)            ModRM:r/m (r)                    NA
         FV             ModRM:reg (r, w)                 EVEX.vvvv (r)           ModRM:r/m (r)                    NA

Description
VFMSUBADD132PD: Multiplies the two, four, or eight packed double-precision floating-point values from the first
source operand to the two or four packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and adds the
even double-precision floating-point values in the second source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMSUBADD213PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and
adds the even double-precision floating-point values in the third source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
VFMSUBADD231PD: Multiplies the two, four, or eight packed double-precision floating-point values from the
second source operand to the two or four packed double-precision floating-point values in the third source operand.
From the infinite precision intermediate result, subtracts the odd double-precision floating-point elements and
adds the even double-precision floating-point values in the first source operand, performs rounding and stores the
resulting two or four packed double-precision floating-point values to the destination operand (first source
operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-
ally updated with write mask k1.





VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMSUBADD132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192]
FI

VFMSUBADD213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192]
FI

VFMSUBADD231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
    DEST[127:64] <-RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
    DEST[191:128] <-RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128])
    DEST[255:192] <-RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192]
FI





VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] + SRC2[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] + SRC2[i+63:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
                        FI;
             FI

        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[63:0])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] + SRC3[i+63:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
                     ELSE DEST[i+63:i] <-
                          RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+63:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] + DEST[i+63:i])
                             ELSE
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] + DEST[i+63:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+63:i] <-
                        RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])

                         ELSE
                             DEST[i+63:i] <-
                     RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
                     FI;
            FI
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_pd(__m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMSUBADDxxxPD __m512d _mm512_mask_fmsubadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_maskz_fmsubadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBADDxxxPD __m512d _mm512_mask3_fmsubadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBADDxxxPD __m256d _mm256_mask_fmsubadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_maskz_fmsubadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMSUBADDxxxPD __m256d _mm256_mask3_fmsubadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMSUBADDxxxPD __m128d _mm_mask_fmsubadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_maskz_fmsubadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBADDxxxPD __m128d _mm_mask3_fmsubadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBADDxxxPD __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);
VFMSUBADDxxxPD __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMSUBADD132PS
description:
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS-Fused Multiply-Alternating
Subtract/Add of Packed Single-Precision Floating-Point Values
 Opcode/                              Op /    64/32       CPUID         Description
 Instruction                          En      bit Mode    Feature
                                              Support     Flag
 VEX.DDS.128.66.0F38.W0 97 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD132PS xmm1, xmm2,                                             xmm1 and xmm3/mem, subtract/add elements in xmm2
 xmm3/m128                                                              and put result in xmm1.
 VEX.DDS.128.66.0F38.W0 A7 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD213PS xmm1, xmm2,                                             xmm1 and xmm2, subtract/add elements in xmm3/mem
 xmm3/m128                                                              and put result in xmm1.
 VEX.DDS.128.66.0F38.W0 B7 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD231PS xmm1, xmm2,                                             xmm2 and xmm3/mem, subtract/add elements in xmm1
 xmm3/m128                                                              and put result in xmm1.
 VEX.DDS.256.66.0F38.W0 97 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD132PS ymm1, ymm2,                                             ymm1 and ymm3/mem, subtract/add elements in ymm2
 ymm3/m256                                                              and put result in ymm1.
 VEX.DDS.256.66.0F38.W0 A7 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD213PS ymm1, ymm2,                                             ymm1 and ymm2, subtract/add elements in ymm3/mem
 ymm3/m256                                                              and put result in ymm1.
 VEX.DDS.256.66.0F38.W0 B7 /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFMSUBADD231PS ymm1, ymm2,                                             ymm2 and ymm3/mem, subtract/add elements in ymm1
 ymm3/m256                                                              and put result in ymm1.
 EVEX.DDS.128.66.0F38.W0 97 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD132PS xmm1 {k1}{z},                             AVX512F       xmm1 and xmm3/m128/m32bcst, subtract/add elements
 xmm2, xmm3/m128/m32bcst                                                in xmm2 and put result in xmm1 subject to writemask k1.
 EVEX.DDS.128.66.0F38.W0 A7 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD213PS xmm1 {k1}{z},                             AVX512F       xmm1 and xmm2, subtract/add elements in
 xmm2, xmm3/m128/m32bcst                                                xmm3/m128/m32bcst and put result in xmm1 subject to
                                                                        writemask k1.
 EVEX.DDS.128.66.0F38.W0 B7 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD231PS xmm1 {k1}{z},                             AVX512F       xmm2 and xmm3/m128/m32bcst, subtract/add elements
 xmm2, xmm3/m128/m32bcst                                                in xmm1 and put result in xmm1 subject to writemask k1.
 EVEX.DDS.256.66.0F38.W0 97 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD132PS ymm1 {k1}{z},                             AVX512F       ymm1 and ymm3/m256/m32bcst, subtract/add elements
 ymm2, ymm3/m256/m32bcst                                                in ymm2 and put result in ymm1 subject to writemask k1.
 EVEX.DDS.256.66.0F38.W0 A7 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD213PS ymm1 {k1}{z},                             AVX512F       ymm1 and ymm2, subtract/add elements in
 ymm2, ymm3/m256/m32bcst                                                ymm3/m256/m32bcst and put result in ymm1 subject to
                                                                        writemask k1.
 EVEX.DDS.256.66.0F38.W0 B7 /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFMSUBADD231PS ymm1 {k1}{z},                             AVX512F       ymm2 and ymm3/m256/m32bcst, subtract/add elements
 ymm2, ymm3/m256/m32bcst                                                in ymm1 and put result in ymm1 subject to writemask k1.
 EVEX.DDS.512.66.0F38.W0 97 /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMSUBADD132PS zmm1 {k1}{z},                                           zmm1 and zmm3/m512/m32bcst, subtract/add elements
 zmm2, zmm3/m512/m32bcst{er}                                            in zmm2 and put result in zmm1 subject to writemask k1.
 EVEX.DDS.512.66.0F38.W0 A7 /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMSUBADD213PS zmm1 {k1}{z},                                           zmm1 and zmm2, subtract/add elements in
 zmm2, zmm3/m512/m32bcst{er}                                            zmm3/m512/m32bcst and put result in zmm1 subject to
                                                                        writemask k1.
 EVEX.DDS.512.66.0F38.W0 B7 /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFMSUBADD231PS zmm1 {k1}{z},                                           zmm2 and zmm3/m512/m32bcst, subtract/add elements
 zmm2, zmm3/m512/m32bcst{er}                                            in zmm1 and put result in zmm1 subject to writemask k1.





                                             Instruction Operand Encoding
       Op/En             Operand 1                   Operand 2                   Operand 3                  Operand 4
       RVM            ModRM:reg (r, w)              VEX.vvvv (r)               ModRM:r/m (r)                   NA
        FV            ModRM:reg (r, w)             EVEX.vvvv (r)               ModRM:r/m (r)                   NA

Description
VFMSUBADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the corresponding packed single-precision floating-point values in the third source operand.
From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements and adds
the even single-precision floating-point values in the second source operand, performs rounding and stores the
resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMSUBADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements
and adds the even single-precision floating-point values in the third source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
VFMSUBADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the
second source operand to the corresponding packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, subtracts the odd single-precision floating-point elements
and adds the even single-precision floating-point values in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.





Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFMSUBADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUBADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUBADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM -1{
    n <- 64*i;
    DEST[n+31:n] <-RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
    DEST[n+63:n+32] <-RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <-0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI



VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+31:i] <-
                          RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
                     ELSE DEST[i+31:i] <-
                          RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+31:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] + SRC2[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] + SRC2[i+31:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
                        FI;
             FI

        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
                     ELSE DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+31:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[31:0])
                        ELSE
                             DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] + SRC3[i+31:i])
                   FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF j *is even*
                     THEN DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
                     ELSE DEST[i+31:i] <-
                          RoundFPControl(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
               FI
         ELSE
               IF *merging-masking*                 ; merging-masking
                     THEN *DEST[i+31:i] remains unchanged*
                     ELSE                           ; zeroing-masking
                          DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUBADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF j *is even*
                   THEN
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] + DEST[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] + DEST[i+31:i])
                        FI;
                   ELSE
                        IF (EVEX.b = 1)
                             THEN
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
                             ELSE
                                 DEST[i+31:i] <-
                        RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
                        FI;
             FI
        ELSE
             IF *merging-masking*                 ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_ps(__m512 a, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBADDxxxPS __m512 _mm512_mask_fmsubadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_maskz_fmsubadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMSUBADDxxxPS __m512 _mm512_mask3_fmsubadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBADDxxxPS __m256 _mm256_mask_fmsubadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMSUBADDxxxPS __m256 _mm256_maskz_fmsubadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMSUBADDxxxPS __m256 _mm256_mask3_fmsubadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_mask_fmsubadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBADDxxxPS __m128 _mm_maskz_fmsubadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBADDxxxPS __m128 _mm_mask3_fmsubadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBADDxxxPS __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);
VFMSUBADDxxxPS __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMSUB132PD
description:
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD-Fused Multiply-Subtract of Packed Double-
Precision Floating-Point Values
 Opcode/                                Op/     64/32       CPUID          Description
 Instruction                            En      bit Mode    Feature
                                                Support     Flag
 VEX.NDS.128.66.0F38.W1 9A /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB132PD xmm1, xmm2,                                                   from xmm1 and xmm3/mem, subtract xmm2 and put
 xmm3/m128                                                                 result in xmm1.
 VEX.NDS.128.66.0F38.W1 AA /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB213PD xmm1, xmm2,                                                   from xmm1 and xmm2, subtract xmm3/mem and put
 xmm3/m128                                                                 result in xmm1.
 VEX.NDS.128.66.0F38.W1 BA /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB231PD xmm1, xmm2,                                                   from xmm2 and xmm3/mem, subtract xmm1 and put
 xmm3/m128                                                                 result in xmm1.
 VEX.NDS.256.66.0F38.W1 9A /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB132PD ymm1, ymm2,                                                   from ymm1 and ymm3/mem, subtract ymm2 and put
 ymm3/m256                                                                 result in ymm1.
 VEX.NDS.256.66.0F38.W1 AA /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB213PD ymm1, ymm2,                                                   from ymm1 and ymm2, subtract ymm3/mem and put
 ymm3/m256                                                                 result in ymm1.
 VEX.NDS.256.66.0F38.W1 BA /r           RVM     V/V         FMA            Multiply packed double-precision floating-point values
 VFMSUB231PD ymm1, ymm2,                                                   from ymm2 and ymm3/mem, subtract ymm1 and put
 ymm3/m256                                                                 result in ymm1.S
 EVEX.NDS.128.66.0F38.W1 9A /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB132PD xmm1 {k1}{z},                                  AVX512F        from xmm1 and xmm3/m128/m64bcst, subtract xmm2
 xmm2, xmm3/m128/m64bcst                                                   and put result in xmm1 subject to writemask k1.
 EVEX.NDS.128.66.0F38.W1 AA /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB213PD xmm1 {k1}{z},                                  AVX512F        from xmm1 and xmm2, subtract xmm3/m128/m64bcst
 xmm2, xmm3/m128/m64bcst                                                   and put result in xmm1 subject to writemask k1.
 EVEX.NDS.128.66.0F38.W1 BA /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB231PD xmm1 {k1}{z},                                  AVX512F        from xmm2 and xmm3/m128/m64bcst, subtract xmm1
 xmm2, xmm3/m128/m64bcst                                                   and put result in xmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F38.W1 9A /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB132PD ymm1 {k1}{z},                                  AVX512F        from ymm1 and ymm3/m256/m64bcst, subtract ymm2
 ymm2, ymm3/m256/m64bcst                                                   and put result in ymm1 subject to writemask k1.
 EVEX.NDS.256.66.0F38.W1 AA /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB213PD ymm1 {k1}{z},                                  AVX512F        from ymm1 and ymm2, subtract ymm3/m256/m64bcst
 ymm2, ymm3/m256/m64bcst                                                   and put result in ymm1 subject to writemask k1.
 EVEX.NDS.256.66.0F38.W1 BA /r          FV      V/V         AVX512VL       Multiply packed double-precision floating-point values
 VFMSUB231PD ymm1 {k1}{z},                                  AVX512F        from ymm2 and ymm3/m256/m64bcst, subtract ymm1
 ymm2, ymm3/m256/m64bcst                                                   and put result in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F38.W1 9A /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point values
 VFMSUB132PD zmm1 {k1}{z},                                                 from zmm1 and zmm3/m512/m64bcst, subtract zmm2
 zmm2, zmm3/m512/m64bcst{er}                                               and put result in zmm1 subject to writemask k1.
 EVEX.NDS.512.66.0F38.W1 AA /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point values
 VFMSUB213PD zmm1 {k1}{z},                                                 from zmm1 and zmm2, subtract zmm3/m512/m64bcst
 zmm2, zmm3/m512/m64bcst{er}                                               and put result in zmm1 subject to writemask k1.
 EVEX.NDS.512.66.0F38.W1 BA /r          FV      V/V         AVX512F        Multiply packed double-precision floating-point values
 VFMSUB231PD zmm1 {k1}{z},                                                 from zmm2 and zmm3/m512/m64bcst, subtract zmm1
 zmm2, zmm3/m512/m64bcst{er}                                               and put result in zmm1 subject to writemask k1.





                                             Instruction Operand Encoding
       Op/En             Operand 1                  Operand 2                   Operand 3                   Operand 4
       RVM            ModRM:reg (r, w)             VEX.vvvv (r)               ModRM:r/m (r)                     NA
        FV            ModRM:reg (r, w)            EVEX.vvvv (r)               ModRM:r/m (r)                     NA

Description
Performs a set of SIMD multiply-subtract computation on packed double-precision floating-point values using three
source operands and writes the multiply-subtract results in the destination operand. The destination operand is
also the first source operand. The second operand must be a SIMD register. The third source operand can be a
SIMD register or a memory location.
VFMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first source
operand to the two, four or eight packed double-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point
values in the second source operand, performs rounding and stores the resulting two, four or eight packed double-
precision floating-point values to the destination operand (first source operand).
VFMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand.
From the infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-
point values in the third source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand. From the
infinite precision intermediate result, subtracts the two, four or eight packed double-precision floating-point values
in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.





Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFMSUB132PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUB213PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUB231PD DEST, SRC2, SRC3 (VEX encoded versions)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMSUB132PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[63:0] - SRC2[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(DEST[i+63:i]*SRC3[i+63:i] - SRC2[i+63:i])
             FI;
             ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB213PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[63:0])
+31:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*DEST[i+63:i] - SRC3[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB231PD DEST, SRC2, SRC3 (EVEX encoded versions, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[63:0] - DEST[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(SRC2[i+63:i]*SRC3[i+63:i] - DEST[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxPD __m512d _mm512_fmsub_pd(__m512d a, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_fmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask_fmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_maskz_fmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFMSUBxxxPD __m512d _mm512_mask3_fmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFMSUBxxxPD __m512d _mm512_mask_fmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_maskz_fmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFMSUBxxxPD __m512d _mm512_mask3_fmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFMSUBxxxPD __m256d _mm256_mask_fmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFMSUBxxxPD __m256d _mm256_maskz_fmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFMSUBxxxPD __m256d _mm256_mask3_fmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFMSUBxxxPD __m128d _mm_mask_fmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBxxxPD __m128d _mm_maskz_fmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBxxxPD __m128d _mm_mask3_fmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBxxxPD __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);
VFMSUBxxxPD __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMSUB132PS
description:
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS-Fused Multiply-Subtract of Packed Single-
Precision Floating-Point Values
 Opcode/                             Op/E    64/32        CPUID         Description
 Instruction                         n       bit Mode     Feature
                                             Support      Flag
 VEX.NDS.128.66.0F38.W0 9A /r        RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB132PS xmm1, xmm2,                                                from xmm1 and xmm3/mem, subtract xmm2 and put
 xmm3/m128                                                              result in xmm1.
 VEX.NDS.128.66.0F38.W0 AA /r        RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB213PS xmm1, xmm2,                                                from xmm1 and xmm2, subtract xmm3/mem and put
 xmm3/m128                                                              result in xmm1.
 VEX.NDS.128.66.0F38.W0 BA /r        RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB231PS xmm1, xmm2,                                                from xmm2 and xmm3/mem, subtract xmm1 and put
 xmm3/m128                                                              result in xmm1.
 VEX.NDS.256.66.0F38.W0 9A /r        RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB132PS ymm1, ymm2,                                                from ymm1 and ymm3/mem, subtract ymm2 and put
 ymm3/m256                                                              result in ymm1.
 VEX.NDS.256.66.0F38.W0 AA /r        RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB213PS ymm1, ymm2,                                                from ymm1 and ymm2, subtract ymm3/mem and put
 ymm3/m256                                                              result in ymm1.
 VEX.NDS.256.66.0F38.0 BA /r         RVM     V/V          FMA           Multiply packed single-precision floating-point values
 VFMSUB231PS ymm1, ymm2,                                                from ymm2 and ymm3/mem, subtract ymm1 and put
 ymm3/m256                                                              result in ymm1.
 EVEX.NDS.128.66.0F38.W0 9A /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB132PS xmm1 {k1}{z},                                AVX512F       from xmm1 and xmm3/m128/m32bcst, subtract
 xmm2, xmm3/m128/m32bcst                                                xmm2 and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 AA /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB213PS xmm1 {k1}{z},                                AVX512F       from xmm1 and xmm2, subtract
 xmm2, xmm3/m128/m32bcst                                                xmm3/m128/m32bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 BA /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB231PS xmm1 {k1}{z},                                AVX512F       from xmm2 and xmm3/m128/m32bcst, subtract
 xmm2, xmm3/m128/m32bcst                                                xmm1 and put result in xmm1.
 EVEX.NDS.256.66.0F38.W0 9A /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB132PS ymm1 {k1}{z},                                AVX512F       from ymm1 and ymm3/m256/m32bcst, subtract
 ymm2, ymm3/m256/m32bcst                                                ymm2 and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 AA /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB213PS ymm1 {k1}{z},                                AVX512F       from ymm1 and ymm2, subtract
 ymm2, ymm3/m256/m32bcst                                                ymm3/m256/m32bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 BA /r       FV      V/V          AVX512VL      Multiply packed single-precision floating-point values
 VFMSUB231PS ymm1 {k1}{z},                                AVX512F       from ymm2 and ymm3/m256/m32bcst, subtract
 ymm2, ymm3/m256/m32bcst                                                ymm1 and put result in ymm1.
 EVEX.NDS.512.66.0F38.W0 9A /r       FV      V/V          AVX512F       Multiply packed single-precision floating-point values
 VFMSUB132PS zmm1 {k1}{z},                                              from zmm1 and zmm3/m512/m32bcst, subtract zmm2
 zmm2, zmm3/m512/m32bcst{er}                                            and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 AA /r       FV      V/V          AVX512F       Multiply packed single-precision floating-point values
 VFMSUB213PS zmm1 {k1}{z},                                              from zmm1 and zmm2, subtract zmm3/m512/m32bcst
 zmm2, zmm3/m512/m32bcst{er}                                            and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 BA /r       FV      V/V          AVX512F       Multiply packed single-precision floating-point values
 VFMSUB231PS zmm1 {k1}{z},                                              from zmm2 and zmm3/m512/m32bcst, subtract zmm1
 zmm2, zmm3/m512/m32bcst{er}                                            and put result in zmm1.





                                                 Instruction Operand Encoding
       Op/En                Operand 1                    Operand 2                    Operand 3                  Operand 4
       RVM               ModRM:reg (r, w)               VEX.vvvv (r)                ModRM:r/m (r)                   NA
        FV               ModRM:reg (r, w)              EVEX.vvvv (r)                ModRM:r/m (r)                   NA

Description
Performs a set of SIMD multiply-subtract computation on packed single-precision floating-point values using three
source operands and writes the multiply-subtract results in the destination operand. The destination operand is
also the first source operand. The second operand must be a SIMD register. The third source operand can be a
SIMD register or a memory location.
VFMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision
floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand. From the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision
floating-point values in the third source operand, performs rounding and stores the resulting four, eight or sixteen
packed single-precision floating-point values to the destination operand (first source operand).
VFMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From
the infinite precision intermediate result, subtracts the four, eight or sixteen packed single-precision floating-point
values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed single-
precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.





Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[31:0] - SRC2[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(DEST[i+31:i]*SRC3[i+31:i] - SRC2[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[31:0])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*DEST[i+31:i] - SRC3[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[31:0] - DEST[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(SRC2[i+31:i]*SRC3[i+31:i] - DEST[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxPS __m512 _mm512_fmsub_ps(__m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_fmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFMSUBxxxPS __m512 _mm512_mask_fmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_maskz_fmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFMSUBxxxPS __m512 _mm512_mask3_fmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFMSUBxxxPS __m256 _mm256_mask_fmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFMSUBxxxPS __m256 _mm256_maskz_fmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFMSUBxxxPS __m256 _mm256_mask3_fmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_mask_fmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_maskz_fmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxPS __m128 _mm_mask3_fmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxPS __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);
VFMSUBxxxPS __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFMSUB132SD
description:
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD-Fused Multiply-Subtract of Scalar Double-
Precision Floating-Point Values
 Opcode/                                Op /    64/32       CPUID         Description
 Instruction                            En      bit Mode    Feature
                                                Support     Flag
 VEX.DDS.LIG.66.0F38.W1 9B /r           RVM     V/V         FMA           Multiply scalar double-precision floating-point value from
 VFMSUB132SD xmm1, xmm2,                                                  xmm1 and xmm3/m64, subtract xmm2 and put result in
 xmm3/m64                                                                 xmm1.
 VEX.DDS.LIG.66.0F38.W1 AB /r           RVM     V/V         FMA           Multiply scalar double-precision floating-point value from
 VFMSUB213SD xmm1, xmm2,                                                  xmm1 and xmm2, subtract xmm3/m64 and put result in
 xmm3/m64                                                                 xmm1.
 VEX.DDS.LIG.66.0F38.W1 BB /r           RVM     V/V         FMA           Multiply scalar double-precision floating-point value from
 VFMSUB231SD xmm1, xmm2,                                                  xmm2 and xmm3/m64, subtract xmm1 and put result in
 xmm3/m64                                                                 xmm1.
 EVEX.DDS.LIG.66.0F38.W1 9B /r          T1S     V/V         AVX512F       Multiply scalar double-precision floating-point value from
 VFMSUB132SD xmm1 {k1}{z},                                                xmm1 and xmm3/m64, subtract xmm2 and put result in
 xmm2, xmm3/m64{er}                                                       xmm1.
 EVEX.DDS.LIG.66.0F38.W1 AB /r          T1S     V/V         AVX512F       Multiply scalar double-precision floating-point value from
 VFMSUB213SD xmm1 {k1}{z},                                                xmm1 and xmm2, subtract xmm3/m64 and put result in
 xmm2, xmm3/m64{er}                                                       xmm1.
 EVEX.DDS.LIG.66.0F38.W1 BB /r          T1S     V/V         AVX512F       Multiply scalar double-precision floating-point value from
 VFMSUB231SD xmm1 {k1}{z},                                                xmm2 and xmm3/m64, subtract xmm1 and put result in
 xmm2, xmm3/m64{er}                                                       xmm1.



                                                 Instruction Operand Encoding
      Op/En                Operand 1                   Operand 2                     Operand 3                    Operand 4
       RVM              ModRM:reg (r, w)              VEX.vvvv (r)                 ModRM:r/m (r)                      NA
       T1S              ModRM:reg (r, w)              EVEX.vvvv (r)                ModRM:r/m (r)                      NA

Description
Performs a SIMD multiply-subtract computation on the low packed double-precision floating-point values using
three source operands and writes the multiply-subtract result in the destination operand. The destination operand
is also the first source operand. The second operand must be a XMM register. The third source operand can be a
XMM register or a 64-bit memory location.
VFMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand. From the infinite precision inter-
mediate result, subtracts the low packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand to
the low packed double-precision floating-point value in the first source operand. From the infinite precision inter-
mediate result, subtracts the low packed double-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand. From the infinite precision intermediate
result, subtracts the low packed double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.




EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0





VFMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxSD __m128d _mm_fmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask_fmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFMSUBxxxSD __m128d _mm_mask_fmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_maskz_fmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFMSUBxxxSD __m128d _mm_mask3_fmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFMSUBxxxSD __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFMSUB132SS
description:
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS-Fused Multiply-Subtract of Scalar Single-
Precision Floating-Point Values
 Opcode/                         Op /       64/32       CPUID           Description
 Instruction                     En         bit Mode    Feature
                                            Support     Flag
 VEX.DDS.LIG.66.0F38.W0 9B /r    RVM        V/V         FMA             Multiply scalar single-precision floating-point value from
 VFMSUB132SS xmm1, xmm2,                                                xmm1 and xmm3/m32, subtract xmm2 and put result in
 xmm3/m32                                                               xmm1.
 VEX.DDS.LIG.66.0F38.W0 AB /r    RVM        V/V         FMA             Multiply scalar single-precision floating-point value from
 VFMSUB213SS xmm1, xmm2,                                                xmm1 and xmm2, subtract xmm3/m32 and put result in
 xmm3/m32                                                               xmm1.
 VEX.DDS.LIG.66.0F38.W0 BB /r    RVM        V/V         FMA             Multiply scalar single-precision floating-point value from
 VFMSUB231SS xmm1, xmm2,                                                xmm2 and xmm3/m32, subtract xmm1 and put result in
 xmm3/m32                                                               xmm1.
 EVEX.DDS.LIG.66.0F38.W0 9B /r   T1S        V/V         AVX512F         Multiply scalar single-precision floating-point value from
 VFMSUB132SS xmm1 {k1}{z},                                              xmm1 and xmm3/m32, subtract xmm2 and put result in
 xmm2, xmm3/m32{er}                                                     xmm1.
 EVEX.DDS.LIG.66.0F38.W0 AB /r   T1S        V/V         AVX512F         Multiply scalar single-precision floating-point value from
 VFMSUB213SS xmm1 {k1}{z},                                              xmm1 and xmm2, subtract xmm3/m32 and put result in
 xmm2, xmm3/m32{er}                                                     xmm1.
 EVEX.DDS.LIG.66.0F38.W0 BB /r   T1S        V/V         AVX512F         Multiply scalar single-precision floating-point value from
 VFMSUB231SS xmm1 {k1}{z},                                              xmm2 and xmm3/m32, subtract xmm1 and put result in
 xmm2, xmm3/m32{er}                                                     xmm1.



                                                  Instruction Operand Encoding
        Op/En               Operand 1                    Operand 2                     Operand 3                    Operand 4
        RVM              ModRM:reg (r, w)               VEX.vvvv (r)                  ModRM:r/m (r)                     NA
         T1S             ModRM:reg (r, w)               EVEX.vvvv (r)                 ModRM:r/m (r)                     NA

Description
Performs a SIMD multiply-subtract computation on the low packed single-precision floating-point values using
three source operands and writes the multiply-subtract result in the destination operand. The destination operand
is also the first source operand. The second operand must be a XMM register. The third source operand can be a
XMM register or a 32-bit memory location.
VFMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to the
low packed single-precision floating-point value in the third source operand. From the infinite precision interme-
diate result, subtracts the low packed single-precision floating-point values in the second source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the first source operand. From the infinite precision interme-
diate result, subtracts the low packed single-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low
packed single-precision floating-point value in the third source operand. From the infinite precision intermediate
result, subtracts the low packed single-precision floating-point value in the first source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.




EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(DEST[31:0]*SRC3[31:0] - SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(SRC2[31:0]*DEST[31:0] - SRC3[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0





VFMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(SRC2[31:0]*SRC3[63:0] - DEST[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(SRC2[31:0]*SRC3[31:0] - DEST[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFMSUBxxxSS __m128 _mm_fmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_mask_fmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_maskz_fmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFMSUBxxxSS __m128 _mm_mask3_fmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFMSUBxxxSS __m128 _mm_mask_fmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_maskz_fmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFMSUBxxxSS __m128 _mm_mask3_fmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFMSUBxxxSS __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFNMADD132PD
description:
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD-Fused Negative Multiply-Add of Packed
Double-Precision Floating-Point Values
 Opcode/                              Op/    64/32        CPUID         Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 VEX.NDS.128.66.0F38.W1 9C /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD132PD xmm1, xmm2,                                               xmm1 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                              and add to xmm2 and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 AC /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD213PD xmm1, xmm2,                                               xmm1 and xmm2, negate the multiplication result and add
 xmm3/m128                                                              to xmm3/mem and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 BC /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD231PD xmm1, xmm2,                                               xmm2 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                              and add to xmm1 and put result in xmm1.
 VEX.NDS.256.66.0F38.W1 9C /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD132PD ymm1, ymm2,                                               ymm1 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                              add to ymm2 and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 AC /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD213PD ymm1, ymm2,                                               ymm1 and ymm2, negate the multiplication result and add
 ymm3/m256                                                              to ymm3/mem and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 BC /r         RVM    V/V          FMA           Multiply packed double-precision floating-point values from
 VFNMADD231PD ymm1, ymm2,                                               ymm2 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                              add to ymm1 and put result in ymm1.
 EVEX.NDS.128.66.0F38.W1 9C /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD132PD xmm0 {k1}{z},                               AVX512F       xmm1 and xmm3/m128/m64bcst, negate the
 xmm1, xmm2/m128/m64bcst                                                multiplication result and add to xmm2 and put result in
                                                                        xmm1.
 EVEX.NDS.128.66.0F38.W1 AC /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD213PD xmm1 {k1}{z},                               AVX512F       xmm1 and xmm2, negate the multiplication result and add
 xmm2, xmm3/m128/m64bcst                                                to xmm3/m128/m64bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W1 BC /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD231PD xmm1 {k1}{z},                               AVX512F       xmm2 and xmm3/m128/m64bcst, negate the
 xmm2, xmm3/m128/m64bcst                                                multiplication result and add to xmm1 and put result in
                                                                        xmm1.
 EVEX.NDS.256.66.0F38.W1 9C /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD132PD ymm1 {k1}{z},                               AVX512F       ymm1 and ymm3/m256/m64bcst, negate the
 ymm2, ymm3/m256/m64bcst                                                multiplication result and add to ymm2 and put result in
                                                                        ymm1.
 EVEX.NDS.256.66.0F38.W1 AC /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD213PD ymm1 {k1}{z},                               AVX512F       ymm1 and ymm2, negate the multiplication result and add
 ymm2, ymm3/m256/m64bcst                                                to ymm3/m256/m64bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W1 BC /r        FV     V/V          AVX512VL      Multiply packed double-precision floating-point values from
 VFNMADD231PD ymm1 {k1}{z},                               AVX512F       ymm2 and ymm3/m256/m64bcst, negate the
 ymm2, ymm3/m256/m64bcst                                                multiplication result and add to ymm1 and put result in
                                                                        ymm1.
 EVEX.NDS.512.66.0F38.W1 9C /r        FV     V/V          AVX512F       Multiply packed double-precision floating-point values from
 VFNMADD132PD zmm1 {k1}{z},                                             zmm1 and zmm3/m512/m64bcst, negate the multiplication
 zmm2, zmm3/m512/m64bcst{er}                                            result and add to zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 AC /r        FV     V/V          AVX512F       Multiply packed double-precision floating-point values from
 VFNMADD213PD zmm1 {k1}{z},                                             zmm1 and zmm2, negate the multiplication result and add
 zmm2, zmm3/m512/m64bcst{er}                                            to zmm3/m512/m64bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 BC /r        FV     V/V          AVX512F       Multiply packed double-precision floating-point values from
 VFNMADD231PD zmm1 {k1}{z},                                             zmm2 and zmm3/m512/m64bcst, negate the multiplication
 zmm2, zmm3/m512/m64bcst{er}                                            result and add to zmm1 and put result in zmm1.





                                                   Instruction Operand Encoding
       Op/En                  Operand 1                   Operand 2                    Operand 3                     Operand 4
        RVM                ModRM:reg (r, w)              VEX.vvvv (r)                ModRM:r/m (r)                       NA
         FV                ModRM:reg (r, w)             EVEX.vvvv (r)                ModRM:r/m (r)                       NA

Description
VFNMADD132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first
source operand to the two, four or eight packed double-precision floating-point values in the third source operand,
adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating-
point values in the second source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFNMADD213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand,
adds the negated infinite precision intermediate result to the two, four or eight packed double-precision floating-
point values in the third source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
VFNMADD231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand, the
negated infinite precision intermediate result to the two, four or eight packed double-precision floating-point values
in the first source operand, performs rounding and stores the resulting two, four or eight packed double-precision
floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).





VFNMADD132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(-(DEST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMADD213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMADD231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI





VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMADD132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) + SRC2[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) + SRC2[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMADD213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[63:0])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) + SRC3[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMADD231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) + DEST[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) + DEST[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPD __m512d _mm512_fnmadd_pd(__m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFNMADDxxxPD __m512d _mm512_mask_fnmadd_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_maskz_fnmadd_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFNMADDxxxPD __m512d _mm512_mask3_fnmadd_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMADDxxxPD __m256d _mm256_mask_fnmadd_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_maskz_fnmadd_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFNMADDxxxPD __m256d _mm256_mask3_fnmadd_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_mask_fnmadd_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMADDxxxPD __m128d _mm_maskz_fnmadd_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxPD __m128d _mm_mask3_fnmadd_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxPD __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);
VFNMADDxxxPD __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFNMADD132PS
description:
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS-Fused Negative Multiply-Add of Packed
Single-Precision Floating-Point Values
 Opcode/                            Op/     64/32       CPUID          Description
 Instruction                        En      bit Mode    Feature
                                            Support     Flag
 VEX.NDS.128.66.0F38.W0 9C /r       RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD132PS xmm1, xmm2,                                              xmm1 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                             and add to xmm2 and put result in xmm1.
 VEX.NDS.128.66.0F38.W0 AC /r       RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD213PS xmm1, xmm2,                                              xmm1 and xmm2, negate the multiplication result and add
 xmm3/m128                                                             to xmm3/mem and put result in xmm1.
 VEX.NDS.128.66.0F38.W0 BC /r       RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD231PS xmm1, xmm2,                                              xmm2 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                             and add to xmm1 and put result in xmm1.
 VEX.NDS.256.66.0F38.W0 9C /r       RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD132PS ymm1, ymm2,                                              ymm1 and ymm3/mem, negate the multiplication result
 ymm3/m256                                                             and add to ymm2 and put result in ymm1.
 VEX.NDS.256.66.0F38.W0 AC /r       RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD213PS ymm1, ymm2,                                              ymm1 and ymm2, negate the multiplication result and add
 ymm3/m256                                                             to ymm3/mem and put result in ymm1.
 VEX.NDS.256.66.0F38.0 BC /r        RVM     V/V         FMA            Multiply packed single-precision floating-point values from
 VFNMADD231PS ymm1, ymm2,                                              ymm2 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                             add to ymm1 and put result in ymm1.
 EVEX.NDS.128.66.0F38.W0 9C /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD132PS xmm1 {k1}{z},                             AVX512F        xmm1 and xmm3/m128/m32bcst, negate the multiplication
 xmm2, xmm3/m128/m32bcst                                               result and add to xmm2 and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 AC /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD213PS xmm1 {k1}{z},                             AVX512F        xmm1 and xmm2, negate the multiplication result and add
 xmm2, xmm3/m128/m32bcst                                               to xmm3/m128/m32bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 BC /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD231PS xmm1 {k1}{z},                             AVX512F        xmm2 and xmm3/m128/m32bcst, negate the multiplication
 xmm2, xmm3/m128/m32bcst                                               result and add to xmm1 and put result in xmm1.
 EVEX.NDS.256.66.0F38.W0 9C /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD132PS ymm1 {k1}{z},                             AVX512F        ymm1 and ymm3/m256/m32bcst, negate the multiplication
 ymm2, ymm3/m256/m32bcst                                               result and add to ymm2 and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 AC /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD213PS ymm1 {k1}{z},                             AVX512F        ymm1 and ymm2, negate the multiplication result and add
 ymm2, ymm3/m256/m32bcst                                               to ymm3/m256/m32bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 BC /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD231PS ymm1 {k1}{z},                             AVX512F        ymm2 and ymm3/m256/m32bcst, negate the multiplication
 ymm2, ymm3/m256/m32bcst                                               result and add to ymm1 and put result in ymm1.
 EVEX.NDS.512.66.0F38.W0 9C /r      FV      V/V         AVX512VL       Multiply packed single-precision floating-point values from
 VFNMADD132PS zmm1 {k1}{z},                             AVX512F        zmm1 and zmm3/m512/m32bcst, negate the multiplication
 zmm2, zmm3/m512/m32bcst{er}                                           result and add to zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 AC /r      FV      V/V         AVX512F        Multiply packed single-precision floating-point values from
 VFNMADD213PS zmm1 {k1}{z},                                            zmm1 and zmm2, negate the multiplication result and add
 zmm2, zmm3/m512/m32bcst{er}                                           to zmm3/m512/m32bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 BC /r      FV      V/V         AVX512F        Multiply packed single-precision floating-point values from
 VFNMADD231PS zmm1 {k1}{z},                                            zmm2 and zmm3/m512/m32bcst, negate the multiplication
 zmm2, zmm3/m512/m32bcst{er}                                           result and add to zmm1 and put result in zmm1.





                                                  Instruction Operand Encoding
       Op/En                Operand 1                    Operand 2                     Operand 3                     Operand 4
       RVM               ModRM:reg (r, w)               VEX.vvvv (r)                 ModRM:r/m (r)                      NA
        FV               ModRM:reg (r, w)              EVEX.vvvv (r)                 ModRM:r/m (r)                      NA

Description
VFNMADD132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-
sion floating-point values in the second source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-
sion floating-point values in the third source operand, performs rounding and stores the resulting the four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMADD231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand, adds the negated infinite precision intermediate result to the four, eight or sixteen packed single-preci-
sion floating-point values in the first source operand, performs rounding and stores the resulting four, eight or
sixteen packed single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFNMADD132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI




VFNMADD213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMADD231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



VFNMADD132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) + SRC2[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) + SRC2[i+31:i])
             FI;

        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMADD213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[31:0])

                 ELSE
                     DEST[i+31:i] <-
            RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) + SRC3[i+31:i])
            FI;
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMADD231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) + DEST[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) + DEST[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxPS __m512 _mm512_fnmadd_ps(__m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask_fnmadd_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFNMADDxxxPS __m512 _mm512_mask_fnmadd_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_maskz_fnmadd_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMADDxxxPS __m512 _mm512_mask3_fnmadd_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFNMADDxxxPS __m256 _mm256_mask_fnmadd_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFNMADDxxxPS __m256 _mm256_maskz_fnmadd_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFNMADDxxxPS __m256 _mm256_mask3_fnmadd_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFNMADDxxxPS __m128 _mm_mask_fnmadd_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_maskz_fnmadd_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m128 _mm_mask3_fnmadd_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxPS __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);
VFNMADDxxxPS __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFNMADD132SD
description:
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD-Fused Negative Multiply-Add of Scalar
Double-Precision Floating-Point Values
 Opcode/                           Op /     64/32       CPUID          Description
 Instruction                       En       bit Mode    Feature
                                            Support     Flag
 VEX.DDS.LIG.66.0F38.W1 9D /r      RVM      V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMADD132SD xmm1, xmm2,                                              xmm1 and xmm3/mem, negate the multiplication result and
 xmm3/m64                                                              add to xmm2 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 AD /r      RVM      V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMADD213SD xmm1, xmm2,                                              xmm1 and xmm2, negate the multiplication result and add to
 xmm3/m64                                                              xmm3/mem and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 BD /r      RVM      V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMADD231SD xmm1, xmm2,                                              xmm2 and xmm3/mem, negate the multiplication result and
 xmm3/m64                                                              add to xmm1 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 9D /r     T1S      V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMADD132SD xmm1 {k1}{z},                                            xmm1 and xmm3/m64, negate the multiplication result and
 xmm2, xmm3/m64{er}                                                    add to xmm2 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 AD /r     T1S      V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMADD213SD xmm1 {k1}{z},                                            xmm1 and xmm2, negate the multiplication result and add to
 xmm2, xmm3/m64{er}                                                    xmm3/m64 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 BD /r     T1S      V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMADD231SD xmm1 {k1}{z},                                            xmm2 and xmm3/m64, negate the multiplication result and
 xmm2, xmm3/m64{er}                                                    add to xmm1 and put result in xmm1.



                                                  Instruction Operand Encoding
       Op/En                Operand 1                   Operand 2                     Operand 3                 Operand 4
        RVM              ModRM:reg (r, w)              VEX.vvvv (r)                  ModRM:r/m (r)                 NA
        T1S              ModRM:reg (r, w)              EVEX.vvvv (r)                 ModRM:r/m (r)                 NA

Description
VFNMADD132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand, adds the negated infinite preci-
sion intermediate result to the low packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFNMADD213SD: Multiplies the low packed double-precision floating-point value from the second source operand
to the low packed double-precision floating-point value in the first source operand, adds the negated infinite preci-
sion intermediate result to the low packed double-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed double-precision floating-point value to the destination operand
(first source operand).
VFNMADD231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand, adds the negated infinite precision inter-
mediate result to the low packed double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.





EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFNMADD132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(DEST[63:0]*SRC3[63:0]) + SRC2[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFNMADD213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0





VFNMADD231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFNMADD132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFNMADD213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFNMADD231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxSD __m128d _mm_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMADDxxxSD __m128d _mm_maskz_fnmadd_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMADDxxxSD __m128d _mm_mask_fnmadd_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_maskz_fnmadd_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFNMADDxxxSD __m128d _mm_mask3_fnmadd_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFNMADDxxxSD __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFNMADD132SS
description:
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS-Fused Negative Multiply-Add of Scalar
Single-Precision Floating-Point Values
 Opcode/                                  Op /   64/32        CPUID        Description
 Instruction                              En     bit Mode     Feature
                                                 Support      Flag
 VEX.DDS.LIG.66.0F38.W0 9D /r             RVM    V/V          FMA          Multiply scalar single-precision floating-point value from
 VFNMADD132SS xmm1, xmm2,                                                  xmm1 and xmm3/m32, negate the multiplication result
 xmm3/m32                                                                  and add to xmm2 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 AD /r             RVM    V/V          FMA          Multiply scalar single-precision floating-point value from
 VFNMADD213SS xmm1, xmm2,                                                  xmm1 and xmm2, negate the multiplication result and
 xmm3/m32                                                                  add to xmm3/m32 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 BD /r             RVM    V/V          FMA          Multiply scalar single-precision floating-point value from
 VFNMADD231SS xmm1, xmm2,                                                  xmm2 and xmm3/m32, negate the multiplication result
 xmm3/m32                                                                  and add to xmm1 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 9D /r            T1S    V/V          AVX512F      Multiply scalar single-precision floating-point value from
 VFNMADD132SS xmm1 {k1}{z},                                                xmm1 and xmm3/m32, negate the multiplication result
 xmm2, xmm3/m32{er}                                                        and add to xmm2 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 AD /r            T1S    V/V          AVX512F      Multiply scalar single-precision floating-point value from
 VFNMADD213SS xmm1 {k1}{z},                                                xmm1 and xmm2, negate the multiplication result and
 xmm2, xmm3/m32{er}                                                        add to xmm3/m32 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 BD /r            T1S    V/V          AVX512F      Multiply scalar single-precision floating-point value from
 VFNMADD231SS xmm1 {k1}{z},                                                xmm2 and xmm3/m32, negate the multiplication result
 xmm2, xmm3/m32{er}                                                        and add to xmm1 and put result in xmm1.



                                                 Instruction Operand Encoding
        Op/En                 Operand 1                     Operand 2                 Operand 3                     Operand 4
        RVM                ModRM:reg (r, w)              VEX.vvvv (r)               ModRM:r/m (r)                      NA
         T1S               ModRM:reg (r, w)             EVEX.vvvv (r)               ModRM:r/m (r)                      NA

Description
VFNMADD132SS: Multiplies the low packed single-precision floating-point value from the first source operand to
the low packed single-precision floating-point value in the third source operand, adds the negated infinite precision
intermediate result to the low packed single-precision floating-point value in the second source operand, performs
rounding and stores the resulting packed single-precision floating-point value to the destination operand (first
source operand).
VFNMADD213SS: Multiplies the low packed single-precision floating-point value from the second source operand
to the low packed single-precision floating-point value in the first source operand, adds the negated infinite preci-
sion intermediate result to the low packed single-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed single-precision floating-point value to the destination operand
(first source operand).
VFNMADD231SS: Multiplies the low packed single-precision floating-point value from the second source operand
to the low packed single-precision floating-point value in the third source operand, adds the negated infinite preci-
sion intermediate result to the low packed single-precision floating-point value in the first source operand,
performs rounding and stores the resulting packed single-precision floating-point value to the destination operand
(first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.





EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "+" symbols represent multiplication and addition with infinite precision inputs and outputs (no
rounding).

VFNMADD132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFNMADD213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*DEST[31:0]) + SRC3[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0





VFNMADD231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) + DEST[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFNMADD132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFNMADD213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFNMADD231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) + DEST[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMADDxxxSS __m128 _mm_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMADDxxxSS __m128 _mm_maskz_fnmadd_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMADDxxxSS __m128 _mm_mask3_fnmadd_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMADDxxxSS __m128 _mm_mask_fnmadd_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_maskz_fnmadd_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFNMADDxxxSS __m128 _mm_mask3_fnmadd_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMADDxxxSS __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFNMSUB132PD
description:
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD-Fused Negative Multiply-Subtract of
Packed Double-Precision Floating-Point Values
 Opcode/                           Op/     64/32       CPUID          Description
 Instruction                       En      bit Mode    Feature
                                           Support     Flag
 VEX.NDS.128.66.0F38.W1 9E /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB132PD xmm1, xmm2,                                             xmm1 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                            and subtract xmm2 and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 AE /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB213PD xmm1, xmm2,                                             xmm1 and xmm2, negate the multiplication result and
 xmm3/m128                                                            subtract xmm3/mem and put result in xmm1.
 VEX.NDS.128.66.0F38.W1 BE /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB231PD xmm1, xmm2,                                             xmm2 and xmm3/mem, negate the multiplication result
 xmm3/m128                                                            and subtract xmm1 and put result in xmm1.
 VEX.NDS.256.66.0F38.W1 9E /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB132PD ymm1, ymm2,                                             ymm1 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                            subtract ymm2 and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 AE /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB213PD ymm1, ymm2,                                             ymm1 and ymm2, negate the multiplication result and
 ymm3/m256                                                            subtract ymm3/mem and put result in ymm1.
 VEX.NDS.256.66.0F38.W1 BE /r      RVM     V/V         FMA            Multiply packed double-precision floating-point values from
 VFNMSUB231PD ymm1, ymm2,                                             ymm2 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                            subtract ymm1 and put result in ymm1.
 EVEX.NDS.128.66.0F38.W1 9E /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB132PD xmm1 {k1}{z},                            AVX512F        xmm1 and xmm3/m128/m64bcst, negate the
 xmm2, xmm3/m128/m64bcst                                              multiplication result and subtract xmm2 and put result in
                                                                      xmm1.
 EVEX.NDS.128.66.0F38.W1 AE /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB213PD xmm1 {k1}{z},                            AVX512F        xmm1 and xmm2, negate the multiplication result and
 xmm2, xmm3/m128/m64bcst                                              subtract xmm3/m128/m64bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W1 BE /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB231PD xmm1 {k1}{z},                            AVX512F        xmm2 and xmm3/m128/m64bcst, negate the
 xmm2, xmm3/m128/m64bcst                                              multiplication result and subtract xmm1 and put result in
                                                                      xmm1.
 EVEX.NDS.256.66.0F38.W1 9E /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB132PD ymm1 {k1}{z},                            AVX512F        ymm1 and ymm3/m256/m64bcst, negate the
 ymm2, ymm3/m256/m64bcst                                              multiplication result and subtract ymm2 and put result in
                                                                      ymm1.
 EVEX.NDS.256.66.0F38.W1 AE /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB213PD ymm1 {k1}{z},                            AVX512F        ymm1 and ymm2, negate the multiplication result and
 ymm2, ymm3/m256/m64bcst                                              subtract ymm3/m256/m64bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W1 BE /r     FV      V/V         AVX512VL       Multiply packed double-precision floating-point values from
 VFNMSUB231PD ymm1 {k1}{z},                            AVX512F        ymm2 and ymm3/m256/m64bcst, negate the
 ymm2, ymm3/m256/m64bcst                                              multiplication result and subtract ymm1 and put result in
                                                                      ymm1.
 EVEX.NDS.512.66.0F38.W1 9E /r     FV      V/V         AVX512F        Multiply packed double-precision floating-point values from
 VFNMSUB132PD zmm1 {k1}{z},                                           zmm1 and zmm3/m512/m64bcst, negate the multiplication
 zmm2, zmm3/m512/m64bcst{er}                                          result and subtract zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 AE /r     FV      V/V         AVX512F        Multiply packed double-precision floating-point values from
 VFNMSUB213PD zmm1 {k1}{z},                                           zmm1 and zmm2, negate the multiplication result and
 zmm2, zmm3/m512/m64bcst{er}                                          subtract zmm3/m512/m64bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W1 BE /r     FV      V/V         AVX512F        Multiply packed double-precision floating-point values from
 VFNMSUB231PD zmm1 {k1}{z},                                           zmm2 and zmm3/m512/m64bcst, negate the multiplication
 zmm2, zmm3/m512/m64bcst{er}                                          result and subtract zmm1 and put result in zmm1.





                                                   Instruction Operand Encoding
       Op/En                  Operand 1                   Operand 2                     Operand 3                    Operand 4
        RVM               ModRM:reg (r, w)               VEX.vvvv (r)                 ModRM:r/m (r)                      NA
         FV               ModRM:reg (r, w)              EVEX.vvvv (r)                 ModRM:r/m (r)                      NA

Description
VFNMSUB132PD: Multiplies the two, four or eight packed double-precision floating-point values from the first
source operand to the two, four or eight packed double-precision floating-point values in the third source operand.
From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision
floating-point values in the second source operand, performs rounding and stores the resulting two, four or eight
packed double-precision floating-point values to the destination operand (first source operand).
VFNMSUB213PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source operand to the two, four or eight packed double-precision floating-point values in the first source operand.
From negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision
floating-point values in the third source operand, performs rounding and stores the resulting two, four or eight
packed double-precision floating-point values to the destination operand (first source operand).
VFNMSUB231PD: Multiplies the two, four or eight packed double-precision floating-point values from the second
source to the two, four or eight packed double-precision floating-point values in the third source operand. From
negated infinite precision intermediate results, subtracts the two, four or eight packed double-precision floating-
point values in the first source operand, performs rounding and stores the resulting two, four or eight packed
double-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFNMSUB132PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI




VFNMSUB213PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMSUB231PD DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 64*i;
    DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



VFNMSUB132PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[63:0]) - SRC2[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(DEST[i+63:i]*SRC3[i+63:i]) - SRC2[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMSUB213PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[63:0])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*DEST[i+63:i]) - SRC3[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               RoundFPControl(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMSUB231PD DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[63:0]) - DEST[i+63:i])
                  ELSE
                       DEST[i+63:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+63:i]*SRC3[i+63:i]) - DEST[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxPD __m512d _mm512_fnmsub_pd(__m512d a, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_pd(__m512d a, __mmask8 k, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_pd(__mmask8 k, __m512d a, __m512d b, __m512d c);
VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_pd(__m512d a, __m512d b, __m512d c, __mmask8 k);
VFNMSUBxxxPD __m512d _mm512_mask_fnmsub_round_pd(__m512d a, __mmask8 k, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_maskz_fnmsub_round_pd(__mmask8 k, __m512d a, __m512d b, __m512d c, int r);
VFNMSUBxxxPD __m512d _mm512_mask3_fnmsub_round_pd(__m512d a, __m512d b, __m512d c, __mmask8 k, int r);
VFNMSUBxxxPD __m256d _mm256_mask_fnmsub_pd(__m256d a, __mmask8 k, __m256d b, __m256d c);
VFNMSUBxxxPD __m256d _mm256_maskz_fnmsub_pd(__mmask8 k, __m256d a, __m256d b, __m256d c);
VFNMSUBxxxPD __m256d _mm256_mask3_fnmsub_pd(__m256d a, __m256d b, __m256d c, __mmask8 k);
VFNMSUBxxxPD __m128d _mm_mask_fnmsub_pd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMSUBxxxPD __m128d _mm_maskz_fnmsub_pd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMSUBxxxPD __m128d _mm_mask3_fnmsub_pd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMSUBxxxPD __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);
VFNMSUBxxxPD __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFNMSUB132PS
description:
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS-Fused Negative Multiply-Subtract of
Packed Single-Precision Floating-Point Values
 Opcode/                              Op/     64/32       CPUID         Description
 Instruction                          En      bit Mode    Feature
                                              Support     Flag
 VEX.NDS.128.66.0F38.W0 9E /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB132PS xmm1, xmm2,                                               xmm1 and xmm3/mem, negate the multiplication result and
 xmm3/m128                                                              subtract xmm2 and put result in xmm1.
 VEX.NDS.128.66.0F38.W0 AE /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB213PS xmm1, xmm2,                                               xmm1 and xmm2, negate the multiplication result and
 xmm3/m128                                                              subtract xmm3/mem and put result in xmm1.
 VEX.NDS.128.66.0F38.W0 BE /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB231PS xmm1, xmm2,                                               xmm2 and xmm3/mem, negate the multiplication result and
 xmm3/m128                                                              subtract xmm1 and put result in xmm1.
 VEX.NDS.256.66.0F38.W0 9E /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB132PS ymm1, ymm2,                                               ymm1 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                              subtract ymm2 and put result in ymm1.
 VEX.NDS.256.66.0F38.W0 AE /r         RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB213PS ymm1, ymm2,                                               ymm1 and ymm2, negate the multiplication result and
 ymm3/m256                                                              subtract ymm3/mem and put result in ymm1.
 VEX.NDS.256.66.0F38.0 BE /r          RVM     V/V         FMA           Multiply packed single-precision floating-point values from
 VFNMSUB231PS ymm1, ymm2,                                               ymm2 and ymm3/mem, negate the multiplication result and
 ymm3/m256                                                              subtract ymm1 and put result in ymm1.
 EVEX.NDS.128.66.0F38.W0 9E /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB132PS xmm1 {k1}{z},                               AVX512F       xmm1 and xmm3/m128/m32bcst, negate the multiplication
 xmm2, xmm3/m128/m32bcst                                                result and subtract xmm2 and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 AE /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB213PS xmm1 {k1}{z},                               AVX512F       xmm1 and xmm2, negate the multiplication result and
 xmm2, xmm3/m128/m32bcst                                                subtract xmm3/m128/m32bcst and put result in xmm1.
 EVEX.NDS.128.66.0F38.W0 BE /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB231PS xmm1 {k1}{z},                               AVX512F       xmm2 and xmm3/m128/m32bcst, negate the multiplication
 xmm2, xmm3/m128/m32bcst                                                result subtract add to xmm1 and put result in xmm1.
 EVEX.NDS.256.66.0F38.W0 9E /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB132PS ymm1 {k1}{z},                               AVX512F       ymm1 and ymm3/m256/m32bcst, negate the multiplication
 ymm2, ymm3/m256/m32bcst                                                result and subtract ymm2 and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 AE /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB213PS ymm1 {k1}{z},                               AVX512F       ymm1 and ymm2, negate the multiplication result and
 ymm2, ymm3/m256/m32bcst                                                subtract ymm3/m256/m32bcst and put result in ymm1.
 EVEX.NDS.256.66.0F38.W0 BE /r        FV      V/V         AVX512VL      Multiply packed single-precision floating-point values from
 VFNMSUB231PS ymm1 {k1}{z},                               AVX512F       ymm2 and ymm3/m256/m32bcst, negate the multiplication
 ymm2, ymm3/m256/m32bcst                                                result subtract add to ymm1 and put result in ymm1.
 EVEX.NDS.512.66.0F38.W0 9E /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFNMSUB132PS zmm1 {k1}{z},                                             zmm1 and zmm3/m512/m32bcst, negate the multiplication
 zmm2, zmm3/m512/m32bcst{er}                                            result and subtract zmm2 and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 AE /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFNMSUB213PS zmm1 {k1}{z},                                             zmm1 and zmm2, negate the multiplication result and
 zmm2, zmm3/m512/m32bcst{er}                                            subtract zmm3/m512/m32bcst and put result in zmm1.
 EVEX.NDS.512.66.0F38.W0 BE /r        FV      V/V         AVX512F       Multiply packed single-precision floating-point values from
 VFNMSUB231PS zmm1 {k1}{z},                                             zmm2 and zmm3/m512/m32bcst, negate the multiplication
 zmm2, zmm3/m512/m32bcst{er}                                            result subtract add to zmm1 and put result in zmm1.





                                                   Instruction Operand Encoding
         Op/En                  Operand 1                   Operand 2                    Operand 3                   Operand 4
         RVM                 ModRM:reg (r, w)              VEX.vvvv (r)                ModRM:r/m (r)                     NA
            FV               ModRM:reg (r, w)              EVEX.vvvv (r)               ModRM:r/m (r)                     NA

Description
VFNMSUB132PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the first
source operand to the four, eight or sixteen packed single-precision floating-point values in the third source
operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-
precision floating-point values in the second source operand, performs rounding and stores the resulting four, eight
or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMSUB213PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source operand to the four, eight or sixteen packed single-precision floating-point values in the first source
operand. From negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-
precision floating-point values in the third source operand, performs rounding and stores the resulting four, eight
or sixteen packed single-precision floating-point values to the destination operand (first source operand).
VFNMSUB231PS: Multiplies the four, eight or sixteen packed single-precision floating-point values from the second
source to the four, eight or sixteen packed single-precision floating-point values in the third source operand. From
negated infinite precision intermediate results, subtracts the four, eight or sixteen packed single-precision floating-
point values in the first source operand, performs rounding and stores the resulting four, eight or sixteen packed
single-precision floating-point values to the destination operand (first source operand).
EVEX encoded versions: The destination operand (also first source operand) and the second source operand are
ZMM/YMM/XMM register. The third source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is condition-
ally updated with write mask k1.
VEX.256 encoded version: The destination operand (also first source operand) is a YMM register and encoded in
reg_field. The second source operand is a YMM register and encoded in VEX.vvvv. The third source operand is a
YMM register or a 256-bit memory location and encoded in rm_field.
VEX.128 encoded version: The destination operand (also first source operand) is a XMM register and encoded in
reg_field. The second source operand is a XMM register and encoded in VEX.vvvv. The third source operand is a
XMM register or a 128-bit memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFNMSUB132PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR( - (DEST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI




VFNMSUB213PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMSUB231PS DEST, SRC2, SRC3 (VEX encoded version)
IF (VEX.128) THEN
    MAXNUM <-2
ELSEIF (VEX.256)
    MAXNUM <- 4
FI
For i = 0 to MAXNUM-1 {
    n <- 32*i;
    DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])
}
IF (VEX.128) THEN
    DEST[MAX_VL-1:128] <- 0
ELSEIF (VEX.256)
    DEST[MAX_VL-1:256] <- 0
FI

VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



VFNMSUB132PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[31:0]) - SRC2[i+31:i])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(DEST[i+31:i]*SRC3[i+31:i]) - SRC2[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VFNMSUB213PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[31:0])
                  ELSE
                       DEST[i+31:i] <-
             RoundFPControl_MXCSR(-(SRC2[i+31:i]*DEST[i+31:i]) - SRC3[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VFNMSUB231PS DEST, SRC2, SRC3 (EVEX encoded version, when src3 operand is a memory source)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*



        THEN
            IF (EVEX.b = 1)
                 THEN
                     DEST[i+31:i] <-
            RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[31:0]) - DEST[i+31:i])
                 ELSE
                     DEST[i+31:i] <-
            RoundFPControl_MXCSR(-(SRC2[i+31:i]*SRC3[i+31:i]) - DEST[i+31:i])
            FI;
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxPS __m512 _mm512_fnmsub_ps(__m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_ps(__m512 a, __mmask16 k, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_ps(__mmask16 k, __m512 a, __m512 b, __m512 c);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_ps(__m512 a, __m512 b, __m512 c, __mmask16 k);
VFNMSUBxxxPS __m512 _mm512_mask_fnmsub_round_ps(__m512 a, __mmask16 k, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_maskz_fnmsub_round_ps(__mmask16 k, __m512 a, __m512 b, __m512 c, int r);
VFNMSUBxxxPS __m512 _mm512_mask3_fnmsub_round_ps(__m512 a, __m512 b, __m512 c, __mmask16 k, int r);
VFNMSUBxxxPS __m256 _mm256_mask_fnmsub_ps(__m256 a, __mmask8 k, __m256 b, __m256 c);
VFNMSUBxxxPS __m256 _mm256_maskz_fnmsub_ps(__mmask8 k, __m256 a, __m256 b, __m256 c);
VFNMSUBxxxPS __m256 _mm256_mask3_fnmsub_ps(__m256 a, __m256 b, __m256 c, __mmask8 k);
VFNMSUBxxxPS __m128 _mm_mask_fnmsub_ps(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMSUBxxxPS __m128 _mm_maskz_fnmsub_ps(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMSUBxxxPS __m128 _mm_mask3_fnmsub_ps(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMSUBxxxPS __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);
VFNMSUBxxxPS __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: VFNMSUB132SD
description:
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD-Fused Negative Multiply-Subtract of
Scalar Double-Precision Floating-Point Values
 Opcode/                            Op /    64/32       CPUID          Description
 Instruction                        En      bit Mode    Feature
                                            Support     Flag
 VEX.DDS.LIG.66.0F38.W1 9F /r       RVM     V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMSUB132SD xmm1, xmm2,                                              xmm1 and xmm3/mem, negate the multiplication result and
 xmm3/m64                                                              subtract xmm2 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 AF /r       RVM     V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMSUB213SD xmm1, xmm2,                                              xmm1 and xmm2, negate the multiplication result and
 xmm3/m64                                                              subtract xmm3/mem and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W1 BF /r       RVM     V/V         FMA            Multiply scalar double-precision floating-point value from
 VFNMSUB231SD xmm1, xmm2,                                              xmm2 and xmm3/mem, negate the multiplication result and
 xmm3/m64                                                              subtract xmm1 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 9F /r      T1S     V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMSUB132SD xmm1 {k1}{z},                                            xmm1 and xmm3/m64, negate the multiplication result and
 xmm2, xmm3/m64{er}                                                    subtract xmm2 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 AF /r      T1S     V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMSUB213SD xmm1 {k1}{z},                                            xmm1 and xmm2, negate the multiplication result and
 xmm2, xmm3/m64{er}                                                    subtract xmm3/m64 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W1 BF /r      T1S     V/V         AVX512F        Multiply scalar double-precision floating-point value from
 VFNMSUB231SD xmm1 {k1}{z},                                            xmm2 and xmm3/m64, negate the multiplication result and
 xmm2, xmm3/m64{er}                                                    subtract xmm1 and put result in xmm1.



                                                  Instruction Operand Encoding
       Op/En                Operand 1                   Operand 2                     Operand 3                   Operand 4
        RVM              ModRM:reg (r, w)              VEX.vvvv (r)                  ModRM:r/m (r)                   NA
        T1S              ModRM:reg (r, w)              EVEX.vvvv (r)                 ModRM:r/m (r)                   NA

Description
VFNMSUB132SD: Multiplies the low packed double-precision floating-point value from the first source operand to
the low packed double-precision floating-point value in the third source operand. From negated infinite precision
intermediate result, subtracts the low double-precision floating-point value in the second source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VFNMSUB213SD: Multiplies the low packed double-precision floating-point value from the second source operand
to the low packed double-precision floating-point value in the first source operand. From negated infinite precision
intermediate result, subtracts the low double-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed double-precision floating-point value to the destination operand (first
source operand).
VFNMSUB231SD: Multiplies the low packed double-precision floating-point value from the second source to the low
packed double-precision floating-point value in the third source operand. From negated infinite precision interme-
diate result, subtracts the low double-precision floating-point value in the first source operand, performs rounding
and stores the resulting packed double-precision floating-point value to the destination operand (first source
operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:64 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.





EVEX encoded version: The low quadword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.

Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFNMSUB132SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFNMSUB213SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*DEST[63:0]) - SRC3[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0





VFNMSUB231SD DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundFPControl(-(SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- DEST[127:64]
DEST[MAX_VL-1:128] <- 0

VFNMSUB132SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFNMSUB213SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

VFNMSUB231SD DEST, SRC2, SRC3 (VEX encoded version)
DEST[63:0] <-RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
DEST[127:64] <-DEST[127:64]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxSD __m128d _mm_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_sd(__m128d a, __mmask8 k, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_maskz_fnmsub_sd(__mmask8 k, __m128d a, __m128d b, __m128d c);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_sd(__m128d a, __m128d b, __m128d c, __mmask8 k);
VFNMSUBxxxSD __m128d _mm_mask_fnmsub_round_sd(__m128d a, __mmask8 k, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_maskz_fnmsub_round_sd(__mmask8 k, __m128d a, __m128d b, __m128d c, int r);
VFNMSUBxxxSD __m128d _mm_mask3_fnmsub_round_sd(__m128d a, __m128d b, __m128d c, __mmask8 k, int r);
VFNMSUBxxxSD __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFNMSUB132SS
description:
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS-Fused Negative Multiply-Subtract of
Scalar Single-Precision Floating-Point Values
 Opcode/                             Op /     64/32       CPUID          Description
 Instruction                         En       bit Mode    Feature
                                              Support     Flag
 VEX.DDS.LIG.66.0F38.W0 9F /r        RVM      V/V         FMA            Multiply scalar single-precision floating-point value from
 VFNMSUB132SS xmm1, xmm2,                                                xmm1 and xmm3/m32, negate the multiplication result and
 xmm3/m32                                                                subtract xmm2 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 AF /r        RVM      V/V         FMA            Multiply scalar single-precision floating-point value from
 VFNMSUB213SS xmm1, xmm2,                                                xmm1 and xmm2, negate the multiplication result and
 xmm3/m32                                                                subtract xmm3/m32 and put result in xmm1.
 VEX.DDS.LIG.66.0F38.W0 BF /r        RVM      V/V         FMA            Multiply scalar single-precision floating-point value from
 VFNMSUB231SS xmm1, xmm2,                                                xmm2 and xmm3/m32, negate the multiplication result and
 xmm3/m32                                                                subtract xmm1 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 9F /r       T1S      V/V         AVX512F        Multiply scalar single-precision floating-point value from
 VFNMSUB132SS xmm1 {k1}{z},                                              xmm1 and xmm3/m32, negate the multiplication result and
 xmm2, xmm3/m32{er}                                                      subtract xmm2 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 AF /r       T1S      V/V         AVX512F        Multiply scalar single-precision floating-point value from
 VFNMSUB213SS xmm1 {k1}{z},                                              xmm1 and xmm2, negate the multiplication result and
 xmm2, xmm3/m32{er}                                                      subtract xmm3/m32 and put result in xmm1.
 EVEX.DDS.LIG.66.0F38.W0 BF /r       T1S      V/V         AVX512F        Multiply scalar single-precision floating-point value from
 VFNMSUB231SS xmm1 {k1}{z},                                              xmm2 and xmm3/m32, negate the multiplication result and
 xmm2, xmm3/m32{er}                                                      subtract xmm1 and put result in xmm1.



                                                    Instruction Operand Encoding
        Op/En                 Operand 1                   Operand 2                     Operand 3                   Operand 4
        RVM                ModRM:reg (r, w)              VEX.vvvv (r)                  ModRM:r/m (r)                     NA
         T1S               ModRM:reg (r, w)              EVEX.vvvv (r)                 ModRM:r/m (r)                     NA

Description
VFNMSUB132SS: Multiplies the low packed single-precision floating-point value from the first source operand to
the low packed single-precision floating-point value in the third source operand. From negated infinite precision
intermediate result, the low single-precision floating-point value in the second source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VFNMSUB213SS: Multiplies the low packed single-precision floating-point value from the second source operand to
the low packed single-precision floating-point value in the first source operand. From negated infinite precision
intermediate result, the low single-precision floating-point value in the third source operand, performs rounding
and stores the resulting packed single-precision floating-point value to the destination operand (first source
operand).
VFNMSUB231SS: Multiplies the low packed single-precision floating-point value from the second source to the low
packed single-precision floating-point value in the third source operand. From negated infinite precision interme-
diate result, the low single-precision floating-point value in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point value to the destination operand (first source operand).
VEX.128 and EVEX encoded version: The destination operand (also first source operand) is encoded in reg_field.
The second source operand is encoded in VEX.vvvv/EVEX.vvvv. The third source operand is encoded in rm_field.
Bits 127:32 of the destination are unchanged. Bits MAXVL-1:128 of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination is updated according to the writemask.
Compiler tools may optionally support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column.



Operation
In the operations below, "*" and "-" symbols represent multiplication and subtraction with infinite precision inputs and outputs (no
rounding).

VFNMSUB132SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFNMSUB213SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0





VFNMSUB231SS DEST, SRC2, SRC3 (EVEX encoded version)
IF (EVEX.b = 1) and SRC3 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundFPControl(-(SRC2[31:0]*SRC3[63:0]) - DEST[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- DEST[127:32]
DEST[MAX_VL-1:128] <- 0

VFNMSUB132SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFNMSUB213SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

VFNMSUB231SS DEST, SRC2, SRC3 (VEX encoded version)
DEST[31:0] <-RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[31:0]) - DEST[31:0])
DEST[127:32] <-DEST[127:32]
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VFNMSUBxxxSS __m128 _mm_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_mask_fnmsub_ss(__m128 a, __mmask8 k, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_ss(__mmask8 k, __m128 a, __m128 b, __m128 c);
VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_ss(__m128 a, __m128 b, __m128 c, __mmask8 k);
VFNMSUBxxxSS __m128 _mm_mask_fnmsub_round_ss(__m128 a, __mmask8 k, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_maskz_fnmsub_round_ss(__mmask8 k, __m128 a, __m128 b, __m128 c, int r);
VFNMSUBxxxSS __m128 _mm_mask3_fnmsub_round_ss(__m128 a, __m128 b, __m128 c, __mmask8 k, int r);
VFNMSUBxxxSS __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.

EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: VFPCLASSPD
description:
VFPCLASSPD-Tests Types Of a Packed Float64 Values
 Opcode/                              Op /       64/32              CPUID          Description
 Instruction                          En         bit Mode           Feature
                                                 Support            Flag
 EVEX.128.66.0F3A.W1 66 /r ib         FV         V/V                AVX512VL       Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPD k2 {k1},                                                AVX512DQ       +Infinity, -Infinity, denormal, finite negative. The immediate
 xmm2/m128/m64bcst, imm8                                                           field provides a mask bit for each of these category tests. The
                                                                                   masked test results are OR-ed together to form a mask result.
 EVEX.256.66.0F3A.W1 66 /r ib         FV         V/V                AVX512VL       Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPD k2 {k1},                                                AVX512DQ       +Infinity, -Infinity, denormal, finite negative. The immediate
 ymm2/m256/m64bcst, imm8                                                           field provides a mask bit for each of these category tests. The
                                                                                   masked test results are OR-ed together to form a mask result.
 EVEX.512.66.0F3A.W1 66 /r ib         FV         V/V                AVX512DQ       Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPD k2 {k1},                                                               +Infinity, -Infinity, denormal, finite negative. The immediate
 zmm2/m512/m64bcst, imm8                                                           field provides a mask bit for each of these category tests. The
                                                                                   masked test results are OR-ed together to form a mask result.



                                                         Instruction Operand Encoding
             Op/En                    Operand 1                              Operand 2                           Operand 3                 Operand 4
              FV                 ModRM:reg (w)                            ModRM:r/m (r)                             NA                        NA

Description
The FPCLASSPD instruction checks the packed double precision floating point values for special categories, speci-
fied by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the
input data element is classified against. The classified results of all specified categories of an input value are ORed
together to form the final boolean result for the input element. The result of each element is written to the corre-
sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:8/4/2] of the destination are
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-6.



                                 7              6            5           4           3        2              1           0

                               SNaN        Neg. Finite   Denormal       Neg. INF   +INF     Neg. 0      +0           QNaN




                   Figure 5-13. Imm8 Byte Specifier of Special Case FP Values for VFPCLASSPD/SD/PS/SS



                                 Table 5-6. Classifier Operations for VFPCLASSPD/SD/PS/SS
Bits          Imm8[0]       Imm8[1]           Imm8[2]               Imm8[3]        Imm8[4]           Imm8[5]             Imm8[6]             Imm8[7]
Category      QNAN          PosZero           NegZero               PosINF         NegINF            Denormal            Negative            SNAN
Classifier    Checks for    Checks for        Checks for -          Checks for     Checks for -      Checks for          Checks for          Checks for
              QNaN          +0                0                     +INF           INF               Denormal            Negative finite     SNaN

The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){

   //* Start checking the source operand for special type *//
   NegNum <- tsrc[63];
   IF (tsrc[62:52]=07FFh) Then ExpAllOnes <- 1; FI;
   IF (tsrc[62:52]=0h) Then ExpAllZeros <- 1;
   IF (ExpAllZeros AND MXCSR.DAZ) Then
         MantAllZeros <- 1;
   ELSIF (tsrc[51:0]=0h) Then
         MantAllZeros <- 1;
   FI;
   ZeroNumber <- ExpAllZeros AND MantAllZeros
   SignalingBit <- tsrc[51];

   sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
   qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
   Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
   Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0
   PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
   NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
   Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm
   FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite

     bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
              ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
              ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
              ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
     Return bResult;
} //* end of CheckFPClassDP() *//

VFPCLASSPD (EVEX Encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b == 1) AND (SRC *is memory*)
                    THEN
                         DEST[j] <- CheckFPClassDP(SRC1[63:0], imm8[7:0]);
                    ELSE
                         DEST[j] <- CheckFPClassDP(SRC1[i+63:i], imm8[7:0]);
               FI;
         ELSE DEST[j] <- 0                  ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPD __mmask8 _mm512_fpclass_pd_mask( __m512d a, int c);
VFPCLASSPD __mmask8 _mm512_mask_fpclass_pd_mask( __mmask8 m, __m512d a, int c)
VFPCLASSPD __mmask8 _mm256_fpclass_pd_mask( __m256d a, int c)
VFPCLASSPD __mmask8 _mm256_mask_fpclass_pd_mask( __mmask8 m, __m256d a, int c)
VFPCLASSPD __mmask8 _mm_fpclass_pd_mask( __m128d a, int c)
VFPCLASSPD __mmask8 _mm_mask_fpclass_pd_mask( __mmask8 m, __m128d a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E4
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VFPCLASSPS
description:
VFPCLASSPS-Tests Types Of a Packed Float32 Values
 Opcode/                            Op /    64/32        CPUID         Description
 Instruction                        En      bit Mode     Feature
                                            Support      Flag
 EVEX.128.66.0F3A.W0 66 /r ib       FV      V/V          AVX512VL      Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPS k2 {k1},                                     AVX512DQ      +Infinity, -Infinity, denormal, finite negative. The immediate
 xmm2/m128/m32bcst, imm8                                               field provides a mask bit for each of these category tests. The
                                                                       masked test results are OR-ed together to form a mask result.
 EVEX.256.66.0F3A.W0 66 /r ib       FV      V/V          AVX512VL      Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPS k2 {k1},                                     AVX512DQ      +Infinity, -Infinity, denormal, finite negative. The immediate
 ymm2/m256/m32bcst, imm8                                               field provides a mask bit for each of these category tests. The
                                                                       masked test results are OR-ed together to form a mask result.
 EVEX.512.66.0F3A.W0 66 /r ib       FV      V/V          AVX512DQ      Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSPS k2 {k1},                                                   +Infinity, -Infinity, denormal, finite negative. The immediate
 zmm2/m512/m32bcst, imm8                                               field provides a mask bit for each of these category tests. The
                                                                       masked test results are OR-ed together to form a mask result.



                                                    Instruction Operand Encoding
            Op/En                  Operand 1                     Operand 2                    Operand 3               Operand 4
              FV                 ModRM:reg (w)                  ModRM:r/m (r)                     NA                      NA

Description
The FPCLASSPS instruction checks the packed single-precision floating point values for special categories, specified
by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point values that the input
data element is classified against. The classified results of all specified categories of an input value are ORed
together to form the final boolean result for the input element. The result of each element is written to the corre-
sponding bit in a mask register k2 according to the writemask k1. Bits [MAX_KL-1:16/8/4] of the destination are
cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-6.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){

   //* Start checking the source operand for special type *//
   NegNum <- tsrc[31];
   IF (tsrc[30:23]=0FFh) Then ExpAllOnes <- 1; FI;
   IF (tsrc[30:23]=0h) Then ExpAllZeros <- 1;
   IF (ExpAllZeros AND MXCSR.DAZ) Then
         MantAllZeros <- 1;
   ELSIF (tsrc[22:0]=0h) Then
         MantAllZeros <- 1;
   FI;
   ZeroNumber= ExpAllZeros AND MantAllZeros
   SignalingBit= tsrc[22];

   sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
   qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
   Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0



   Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0
   PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
   NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
   Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm
   FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite

     bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
              ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
              ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
              ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
     Return bResult;
} //* end of CheckSPClassSP() *//

VFPCLASSPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b == 1) AND (SRC *is memory*)
                    THEN
                         DEST[j] <- CheckFPClassDP(SRC1[31:0], imm8[7:0]);
                    ELSE
                         DEST[j] <- CheckFPClassDP(SRC1[i+31:i], imm8[7:0]);
               FI;
         ELSE DEST[j] <- 0                  ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSPS __mmask16 _mm512_fpclass_ps_mask( __m512 a, int c);
VFPCLASSPS __mmask16 _mm512_mask_fpclass_ps_mask( __mmask16 m, __m512 a, int c)
VFPCLASSPS __mmask8 _mm256_fpclass_ps_mask( __m256 a, int c)
VFPCLASSPS __mmask8 _mm256_mask_fpclass_ps_mask( __mmask8 m, __m256 a, int c)
VFPCLASSPS __mmask8 _mm_fpclass_ps_mask( __m128 a, int c)
VFPCLASSPS __mmask8 _mm_mask_fpclass_ps_mask( __mmask8 m, __m128 a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E4
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VFPCLASSSD
description:
VFPCLASSSD-Tests Types Of a Scalar Float64 Values
 Opcode/                            Op /   64/32        CPUID        Description
 Instruction                        En     bit Mode     Feature
                                           Support      Flag
 EVEX.LIG.66.0F3A.W1 67 /r ib       T1S    V/V          AVX512DQ     Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSSD k2 {k1},                                                 +Infinity, -Infinity, denormal, finite negative. The immediate
 xmm2/m64, imm8                                                      field provides a mask bit for each of these category tests. The
                                                                     masked test results are OR-ed together to form a mask result.



                                                    Instruction Operand Encoding
          Op/En                   Operand 1                    Operand 2                     Operand 3               Operand 4
            T1S                 ModRM:reg (w)                 ModRM:r/m (r)                      NA                      NA

Description
The FPCLASSSD instruction checks the low double precision floating point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-6.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
CheckFPClassDP (tsrc[63:0], imm8[7:0]){

   NegNum <- tsrc[63];
   IF (tsrc[62:52]=07FFh) Then ExpAllOnes <- 1; FI;
   IF (tsrc[62:52]=0h) Then ExpAllZeros <- 1;
   IF (ExpAllZeros AND MXCSR.DAZ) Then
         MantAllZeros <- 1;
   ELSIF (tsrc[51:0]=0h) Then
         MantAllZeros <- 1;
   FI;
   ZeroNumber <- ExpAllZeros AND MantAllZeros
   SignalingBit <- tsrc[51];

   sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
   qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
   Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
   Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0
   PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
   NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
   Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm
   FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite

     bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
              ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
              ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
              ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
     Return bResult;
} //* end of CheckFPClassDP() *//



VFPCLASSSD (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[0] <-
             CheckFPClassDP(SRC1[63:0], imm8[7:0])
    ELSE DEST[0] <- 0             ; zeroing-masking only
FI;
DEST[MAX_KL-1:1] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSD __mmask8 _mm_fpclass_sd_mask( __m128d a, int c)
VFPCLASSSD __mmask8 _mm_mask_fpclass_sd_mask( __mmask8 m, __m128d a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E6
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VFPCLASSSS
description:
VFPCLASSSS-Tests Types Of a Scalar Float32 Values
 Opcode/                           Op /    64/32        CPUID       Description
 Instruction                       En      bit Mode     Feature
                                           Support      Flag
 EVEX.LIG.66.0F3A.W0 67 /r         T1S     V/V          AVX512DQ    Tests the input for the following categories: NaN, +0, -0,
 VFPCLASSSS k2 {k1},                                                +Infinity, -Infinity, denormal, finite negative. The immediate
 xmm2/m32, imm8                                                     field provides a mask bit for each of these category tests. The
                                                                    masked test results are OR-ed together to form a mask result.



                                                    Instruction Operand Encoding
           Op/En                    Operand 1                   Operand 2                    Operand 3              Operand 4
              T1S                 ModRM:reg (w)               ModRM:r/m (r)                     NA                      NA

Description
The FPCLASSSS instruction checks the low single-precision floating point value in the source operand for special
categories, specified by the set bits in the imm8 byte. Each set bit in imm8 specifies a category of floating-point
values that the input data element is classified against. The classified results of all specified categories of an input
value are ORed together to form the final boolean result for the input element. The result is written to the low bit
in a mask register k2 according to the writemask k1. Bits MAX_KL-1: 1 of the destination are cleared.
The classification categories specified by imm8 are shown in Figure 5-13. The classification test for each category
is listed in Table 5-6.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
CheckFPClassSP (tsrc[31:0], imm8[7:0]){

   //* Start checking the source operand for special type *//
   NegNum <- tsrc[31];
   IF (tsrc[30:23]=0FFh) Then ExpAllOnes <- 1; FI;
   IF (tsrc[30:23]=0h) Then ExpAllZeros <- 1;
   IF (ExpAllZeros AND MXCSR.DAZ) Then
         MantAllZeros <- 1;
   ELSIF (tsrc[22:0]=0h) Then
         MantAllZeros <- 1;
   FI;
   ZeroNumber= ExpAllZeros AND MantAllZeros
   SignalingBit= tsrc[22];

   sNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND NOT(SignalingBit) ; // sNaN
   qNaN_res <- ExpAllOnes AND NOT(MantAllZeros) AND SignalingBit;; // qNaN
   Pzero_res <- NOT(NegNum) AND ExpAllZeros AND MantAllZeros;; // +0
   Nzero_res <- NegNum AND ExpAllZeros AND MantAllZeros;; // -0
   PInf_res <- NOT(NegNum) AND ExpAllOnes AND MantAllZeros;; // +Inf
   NInf_res <- NegNum AND ExpAllOnes AND MantAllZeros;; // -Inf
   Denorm_res <- ExpAllZeros AND NOT(MantAllZeros);; // denorm
   FinNeg_res <- NegNum AND NOT(ExpAllOnes) AND NOT(ZeroNumber);; // -finite

   bResult = ( imm8[0] AND qNaN_res ) OR (imm8[1] AND Pzero_res ) OR
            ( imm8[2] AND Nzero_res ) OR ( imm8[3] AND PInf_res ) OR
            ( imm8[4] AND NInf_res ) OR ( imm8[5] AND Denorm_res ) OR
            ( imm8[6] AND FinNeg_res ) OR ( imm8[7] AND sNaN_res ) ;
   Return bResult;
} //* end of CheckSPClassSP() *//

VFPCLASSSS (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[0] <-
             CheckFPClassSP(SRC1[31:0], imm8[7:0])
    ELSE DEST[0] <- 0              ; zeroing-masking only
FI;
DEST[MAX_KL-1:1] <- 0



Intel C/C++ Compiler Intrinsic Equivalent
VFPCLASSSS __mmask8 _mm_fpclass_ss_mask( __m128 a, int c)
VFPCLASSSS __mmask8 _mm_mask_fpclass_ss_mask( __mmask8 m, __m128 a, int c)

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E6
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VGATHERDPD
description:
VGATHERDPD/VGATHERQPD - Gather Packed DP FP Values Using Signed Dword/Qword Indices
 Opcode/                                   Op/     64/3     CPUID      Description
 Instruction                               En      2-bit    Feature
                                                   Mode     Flag
 VEX.DDS.128.66.0F38.W1 92 /r              RMV     V/V      AVX2       Using dword indices specified in vm32x, gather double-pre-
 VGATHERDPD xmm1, vm32x, xmm2                                          cision FP values from memory conditioned on mask speci-
                                                                       fied by xmm2. Conditionally gathered elements are merged
                                                                       into xmm1.

 VEX.DDS.128.66.0F38.W1 93 /r              RMV     V/V      AVX2       Using qword indices specified in vm64x, gather double-pre-
 VGATHERQPD xmm1, vm64x, xmm2                                          cision FP values from memory conditioned on mask speci-
                                                                       fied by xmm2. Conditionally gathered elements are merged
                                                                       into xmm1.

 VEX.DDS.256.66.0F38.W1 92 /r              RMV     V/V      AVX2       Using dword indices specified in vm32x, gather double-pre-
 VGATHERDPD ymm1, vm32x, ymm2                                          cision FP values from memory conditioned on mask speci-
                                                                       fied by ymm2. Conditionally gathered elements are merged
                                                                       into ymm1.

 VEX.DDS.256.66.0F38.W1 93 /r              RMV     V/V      AVX2       Using qword indices specified in vm64y, gather double-pre-
 VGATHERQPD ymm1, vm64y, ymm2                                          cision FP values from memory conditioned on mask speci-
                                                                       fied by ymm2. Conditionally gathered elements are merged
                                                                       into ymm1.



                                                 Instruction Operand Encoding
  Op/En              Operand 1                     Operand 2                     Operand 3                    Operand 4
   RMV            ModRM:reg (r,w)            BaseReg (R): VSIB:base,          VEX.vvvv (r, w)                     NA
                                            VectorReg(R): VSIB:index

Description
The instruction conditionally loads up to 2 or 4 double-precision floating-point values from memory addresses
specified by the memory operand (the second operand) and using qword indices. The memory operand uses the
VSIB form of the SIB byte to specify a general purpose register operand as the common base, a vector register for
an array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 double-
precision floating-point values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.





VEX.128 version: The instruction will gather two double-precision floating-point values. For dword indices, only the
lower two indices in the vector index register are used.
VEX.256 version: The instruction will gather four double-precision floating-point values. For dword indices, only
the lower four indices in the vector index register are used.
Note that:
.   If any pair of the index, mask, or destination registers are the same, this instruction results a #UD fault.
.   The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
    64 memory-ordering model.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
    to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
    conventional order.
.   Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   This instruction will cause a #UD if the address size attribute is 16-bit.
.   This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
.   This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
    is implementation specific, and some implementations may use loads larger than the data element size or load
    elements an indeterminate number of times.
.   The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
    bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
    bits are ignored.





Operation
DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;

VGATHERDPD (VEX.128 version)
FOR j<- 0 to 1
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 1
   k <- j * 32;
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63: i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)

VGATHERQPD (VEX.128 version)
FOR j<- 0 to 1
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 1
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits this instruction
   FI;
   MASK[i +63: i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)





VGATHERQPD (VEX.256 version)
FOR j<- 0 to 3
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63: i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)

VGATHERDPD (VEX.256 version)
FOR j<- 0 to 3
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   k <- j * 32;
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index, const int scale);
VGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base, __m128i index, __m256d mask, const int
scale);
VGATHERQPD: __m128d _mm_i64gather_pd (double const * base, __m128i index, const int scale);
VGATHERQPD: __m128d _mm_mask_i64gather_pd (__m128d src, double const * base, __m128i index, __m128d mask, const int
scale);
VGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i index, const int scale);
VGATHERQPD: __m256d _mm256_mask_i64gather_pd (__m256d src, double const * base, __m256i index, __m256d mask, const int
scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 12.






platform: x86_64
mnem: VGATHERDPS
description:
VGATHERDPS/VGATHERQPS - Gather Packed SP FP values Using Signed Dword/Qword Indices
 Opcode/                             Op/    64/32     CPUID       Description
 Instruction                         En     -bit      Feature
                                            Mode      Flag
 VEX.DDS.128.66.0F38.W0 92 /r        RMV    V/V       AVX2        Using dword indices specified in vm32x, gather single-preci-
 VGATHERDPS xmm1, vm32x, xmm2                                     sion FP values from memory conditioned on mask specified
                                                                  by xmm2. Conditionally gathered elements are merged into
                                                                  xmm1.

 VEX.DDS.128.66.0F38.W0 93 /r        RMV    V/V       AVX2        Using qword indices specified in vm64x, gather single-preci-
 VGATHERQPS xmm1, vm64x, xmm2                                     sion FP values from memory conditioned on mask specified
                                                                  by xmm2. Conditionally gathered elements are merged into
                                                                  xmm1.

 VEX.DDS.256.66.0F38.W0 92 /r        RMV    V/V       AVX2        Using dword indices specified in vm32y, gather single-preci-
 VGATHERDPS ymm1, vm32y, ymm2                                     sion FP values from memory conditioned on mask specified
                                                                  by ymm2. Conditionally gathered elements are merged into
                                                                  ymm1.

 VEX.DDS.256.66.0F38.W0 93 /r        RMV    V/V       AVX2        Using qword indices specified in vm64y, gather single-preci-
 VGATHERQPS xmm1, vm64y, xmm2                                     sion FP values from memory conditioned on mask specified
                                                                  by xmm2. Conditionally gathered elements are merged into
                                                                  xmm1.



                                           Instruction Operand Encoding
   Op/En           Operand 1                 Operand 2                      Operand 3                      Operand 4
     A          ModRM:reg (r,w)         BaseReg (R): VSIB:base,          VEX.vvvv (r, w)                      NA
                                       VectorReg(R): VSIB:index

Description
The instruction conditionally loads up to 4 or 8 single-precision floating-point values from memory addresses spec-
ified by the memory operand (the second operand) and using dword indices. The memory operand uses the VSIB
form of the SIB byte to specify a general purpose register operand as the common base, a vector register for an
array of indices relative to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 single-precision floating-point values from the
VSIB addressing memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits
of the destination register are zero'ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.



VEX.128 version: For dword indices, the instruction will gather four single-precision floating-point values. For
qword indices, the instruction will gather two values and zeroes the upper 64 bits of the destination.
VEX.256 version: For dword indices, the instruction will gather eight single-precision floating-point values. For
qword indices, the instruction will gather four values and zeroes the upper 128 bits of the destination.
Note that:
.   If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
.   The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
    64 memory-ordering model.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
    to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
    conventional order.
.   Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   This instruction will cause a #UD if the address size attribute is 16-bit.
.   This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
.   This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
    is implementation specific, and some implementations may use loads larger than the data element size or load
    elements an indeterminate number of times.
.   The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
    bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
    bits are ignored.





Operation
DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;

VGATHERDPS (VEX.128 version)
FOR j<- 0 to 3
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 3
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)

VGATHERQPS (VEX.128 version)
FOR j<- 0 to 3
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 1
   k <- j * 64;
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
MASK[127:64] <- 0;
DEST[VLMAX-1:64] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)





VGATHERDPS (VEX.256 version)
FOR j<- 0 to 7
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 7
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)

VGATHERQPS (VEX.256 version)
FOR j<- 0 to 7
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   k <- j * 64;
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPS:     __m128 _mm_i32gather_ps (float const * base, __m128i index, const int scale);
VGATHERDPS:     __m128 _mm_mask_i32gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERDPS:     __m256 _mm256_i32gather_ps (float const * base, __m256i index, const int scale);
VGATHERDPS:     __m256 _mm256_mask_i32gather_ps (__m256 src, float const * base, __m256i index, __m256 mask, const int
scale);
VGATHERQPS:     __m128 _mm_i64gather_ps (float const * base, __m128i index, const int scale);
VGATHERQPS:     __m128 _mm_mask_i64gather_ps (__m128 src, float const * base, __m128i index, __m128 mask, const int scale);
VGATHERQPS:     __m128 _mm256_i64gather_ps (float const * base, __m256i index, const int scale);
VGATHERQPS:     __m128 _mm256_mask_i64gather_ps (__m128 src, float const * base, __m256i index, __m128 mask, const int
scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 12






platform: x86_64
mnem: VGATHERDPS
description:
VGATHERDPS/VGATHERDPD-Gather Packed Single, Packed Double with Signed Dword
    Opcode/                          Op/    64/32        CPUID         Description
    Instruction                      En     bit Mode     Feature
                                            Support      Flag
    EVEX.128.66.0F38.W0 92 /vsib     T1S    V/V          AVX512VL      Using signed dword indices, gather single-precision floating-
    VGATHERDPS xmm1 {k1}, vm32x                          AVX512F       point values from memory using k1 as completion mask.
    EVEX.256.66.0F38.W0 92 /vsib     T1S    V/V          AVX512VL      Using signed dword indices, gather single-precision floating-
    VGATHERDPS ymm1 {k1}, vm32y                          AVX512F       point values from memory using k1 as completion mask.
    EVEX.512.66.0F38.W0 92 /vsib     T1S    V/V          AVX512F       Using signed dword indices, gather single-precision floating-
    VGATHERDPS zmm1 {k1}, vm32z                                        point values from memory using k1 as completion mask.
    EVEX.128.66.0F38.W1 92 /vsib     T1S    V/V          AVX512VL      Using signed dword indices, gather float64 vector into
    VGATHERDPD xmm1 {k1},                                AVX512F       float64 vector xmm1 using k1 as completion mask.
    vm32x
    EVEX.256.66.0F38.W1 92 /vsib     T1S    V/V          AVX512VL      Using signed dword indices, gather float64 vector into
    VGATHERDPD ymm1 {k1},                                AVX512F       float64 vector ymm1 using k1 as completion mask.
    vm32x
    EVEX.512.66.0F38.W1 92 /vsib     T1S    V/V          AVX512F       Using signed dword indices, gather float64 vector into
    VGATHERDPD zmm1 {k1}, vm32y                                        float64 vector zmm1 using k1 as completion mask.



                                                  Instruction Operand Encoding
        Op/En               Operand 1                    Operand 2                   Operand 3                    Operand 4
                                                    BaseReg (R): VSIB:base,
         T1S             ModRM:reg (w)                                                   NA                          NA
                                                   VectorReg(R): VSIB:index

Description
A set of single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into a vector register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only
be loaded if their corresponding mask bit is one. If an element's mask bit is not set, the corresponding element of
the destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it
triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the right most one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
.     The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
      64 memory-ordering model.
.     Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
      elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
      closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
      in the conventional order.
.     Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
      the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
      instruction is repeatable - given the same input values and architectural state, the same set of elements to the
      left of the faulting one will be gathered.




.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement

VGATHERDPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         THEN DEST[i+31:i] <-
               MEM[BASE_ADDR +
                         SignExtend(VINDEX[i+31:i]) * SCALE + DISP]
               k1[j] <- 0
         ELSE *DEST[i+31:i] <- remains unchanged*
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0

VGATHERDPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         THEN DEST[i+63:i] <- MEM[BASE_ADDR +
                         SignExtend(VINDEX[k+31:k]) * SCALE + DISP]
               k1[j] <- 0
         ELSE *DEST[i+63:i] <- remains unchanged*
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERDPD __m512d _mm512_i32gather_pd( __m256i vdx, void * base, int scale);
VGATHERDPD __m512d _mm512_mask_i32gather_pd(__m512d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERDPD __m256d _mm256_mmask_i32gather_pd(__m256d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPD __m128d _mm_mmask_i32gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_i32gather_ps( __m512i vdx, void * base, int scale);
VGATHERDPS __m512 _mm512_mask_i32gather_ps(__m512 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERDPS __m256 _mm256_mmask_i32gather_ps(__m256 s, __mmask8 k, __m256i vdx, void * base, int scale);
GATHERDPS __m128 _mm_mmask_i32gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12.






platform: x86_64
mnem: VGATHERPF0DPS
description:
VGATHERPF0DPS/VGATHERPF0QPS/VGATHERPF0DPD/VGATHERPF0QPD-Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint
 Opcode/                                   Op/   64/32         CPUID      Description
 Instruction                               En    bit Mode      Feature
                                                 Support       Flag
 EVEX.512.66.0F38.W0 C6 /1 /vsib           T1S   V/V           AVX512PF   Using signed dword indices, prefetch sparse byte
 VGATHERPF0DPS vm32z {k1}                                                 memory locations containing single-precision data
                                                                          using opmask k1 and T0 hint.
 EVEX.512.66.0F38.W0 C7 /1 /vsib           T1S   V/V           AVX512PF   Using signed qword indices, prefetch sparse byte
 VGATHERPF0QPS vm64z {k1}                                                 memory locations containing single-precision data
                                                                          using opmask k1 and T0 hint.
 EVEX.512.66.0F38.W1 C6 /1 /vsib           T1S   V/V           AVX512PF   Using signed dword indices, prefetch sparse byte
 VGATHERPF0DPD vm32y {k1}                                                 memory locations containing double-precision data
                                                                          using opmask k1 and T0 hint.
 EVEX.512.66.0F38.W1 C7 /1 /vsib           T1S   V/V           AVX512PF   Using signed qword indices, prefetch sparse byte
 VGATHERPF0QPD vm64z {k1}                                                 memory locations containing double-precision data
                                                                          using opmask k1 and T0 hint.



                                                 Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                  Operand 3                     Operand 4
    T1S          BaseReg (R): VSIB:base,               NA                        NA                            NA
                VectorReg(R): VSIB:index

Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T0):
. T0 (temporal data)-prefetch data into the first level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.





Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request
for exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.

VGATHERPF0DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 0)
    FI;
ENDFOR

VGATHERPF0DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 0)
    FI;
ENDFOR

VGATHERPF0QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 0)
    FI;
ENDFOR

VGATHERPF0QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 0)
    FI;
ENDFOR





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERPF0DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF0DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF0QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF0QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12NP.






platform: x86_64
mnem: VGATHERPF1DPS
description:
VGATHERPF1DPS/VGATHERPF1QPS/VGATHERPF1DPD/VGATHERPF1QPD-Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint
 Opcode/                                  Op/   64/32      CPUID      Description
 Instruction                              En    bit Mode   Feature
                                                Support    Flag
 EVEX.512.66.0F38.W0 C6 /2 /vsib          T1S   V/V        AVX512PF   Using signed dword indices, prefetch sparse byte
 VGATHERPF1DPS vm32z {k1}                                             memory locations containing single-precision data using
                                                                      opmask k1 and T1 hint.
 EVEX.512.66.0F38.W0 C7 /2 /vsib          T1S   V/V        AVX512PF   Using signed qword indices, prefetch sparse byte
 VGATHERPF1QPS vm64z {k1}                                             memory locations containing single-precision data using
                                                                      opmask k1 and T1 hint.
 EVEX.512.66.0F38.W1 C6 /2 /vsib          T1S   V/V        AVX512PF   Using signed dword indices, prefetch sparse byte
 VGATHERPF1DPD vm32y {k1}                                             memory locations containing double-precision data using
                                                                      opmask k1 and T1 hint.
 EVEX.512.66.0F38.W1 C7 /2 /vsib          T1S   V/V        AVX512PF   Using signed qword indices, prefetch sparse byte
 VGATHERPF1QPD vm64z {k1}                                             memory locations containing double-precision data using
                                                                      opmask k1 and T1 hint.



                                                 Instruction Operand Encoding
    Op/En            Operand 1                     Operand 2               Operand 3                      Operand 4
    T1S         BaseReg (R): VSIB:base,               NA                        NA                           NA
               VectorReg(R): VSIB:index

Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
Lines prefetched are loaded into to a location in the cache hierarchy specified by a locality hint (T1):
. T1 (temporal data)-prefetch data into the second level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.





Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request
for exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.

VGATHERPF1DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 0)
    FI;
ENDFOR

VGATHERPF1DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 0)
    FI;
ENDFOR

VGATHERPF1QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 0)
    FI;
ENDFOR

VGATHERPF1QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 0)
    FI;
ENDFOR





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERPF1DPD void _mm512_mask_prefetch_i32gather_pd(__m256i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF1DPS void _mm512_mask_prefetch_i32gather_ps(__m512i vdx, __mmask16 m, void * base, int scale, int hint);
VGATHERPF1QPD void _mm512_mask_prefetch_i64gather_pd(__m512i vdx, __mmask8 m, void * base, int scale, int hint);
VGATHERPF1QPS void _mm512_mask_prefetch_i64gather_ps(__m512i vdx, __mmask8 m, void * base, int scale, int hint);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12NP.






platform: x86_64
mnem: VGATHERQPS
description:
VGATHERQPS/VGATHERQPD-Gather Packed Single, Packed Double with Signed Qword Indices
    Opcode/                        Op/    64/32         CPUID          Description
    Instruction                    En     bit Mode      Feature
                                          Support       Flag
    EVEX.128.66.0F38.W0 93 /vsib   T1S    V/V           AVX512VL       Using signed qword indices, gather single-precision
    VGATHERQPS xmm1 {k1}, vm64x                         AVX512F        floating-point values from memory using k1 as completion
                                                                       mask.
    EVEX.256.66.0F38.W0 93 /vsib   T1S    V/V           AVX512VL       Using signed qword indices, gather single-precision
    VGATHERQPS xmm1 {k1}, vm64y                         AVX512F        floating-point values from memory using k1 as completion
                                                                       mask.
    EVEX.512.66.0F38.W0 93 /vsib   T1S    V/V           AVX512F        Using signed qword indices, gather single-precision
    VGATHERQPS ymm1 {k1}, vm64z                                        floating-point values from memory using k1 as completion
                                                                       mask.
    EVEX.128.66.0F38.W1 93 /vsib   T1S    V/V           AVX512VL       Using signed qword indices, gather float64 vector into
    VGATHERQPD xmm1 {k1}, vm64x                         AVX512F        float64 vector xmm1 using k1 as completion mask.
    EVEX.256.66.0F38.W1 93 /vsib   T1S    V/V           AVX512VL       Using signed qword indices, gather float64 vector into
    VGATHERQPD ymm1 {k1}, vm64y                         AVX512F        float64 vector ymm1 using k1 as completion mask.
    EVEX.512.66.0F38.W1 93 /vsib   T1S    V/V           AVX512F        Using signed qword indices, gather float64 vector into
    VGATHERQPD zmm1 {k1}, vm64z                                        float64 vector zmm1 using k1 as completion mask.



Instruction Operand Encoding
         Op/En             Operand 1                   Operand 2                     Operand 3                 Operand 4
                                                 BaseReg (R): VSIB:base,
          T1S            ModRM:reg (w)                                                  NA                         NA
                                                VectorReg(R): VSIB:index

Description
A set of 8 single-precision/double-precision faulting-point memory locations pointed by base address BASE_ADDR
and index vector V_INDEX with scale SCALE are gathered. The result is written into vector a register. The elements
are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be
loaded if their corresponding mask bit is one. If an element's mask bit is not set, the corresponding element of the
destination register is left unchanged. The entire mask register will be set to zero by this instruction unless it trig-
gers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
.     The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
      64 memory-ordering model.
.     Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
      elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
      closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
      in the conventional order.





.   Elements may be gathered in any order, but faults must be delivered in a right-to left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   Not valid with 16-bit effective addresses. Will deliver a #UD fault.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement

VGATHERQPS (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)
FOR j <- 0 TO KL-1

   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]
             k1[j] <- 0
        ELSE *DEST[i+31:i] <- remains unchanged*
   FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL/2] <- 0

VGATHERQPD (EVEX encoded version)

(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP]
               k1[j] <- 0
         ELSE *DEST[i+63:i] <- remains unchanged*
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VGATHERQPD __m512d _mm512_i64gather_pd( __m512i vdx, void * base, int scale);
VGATHERQPD __m512d _mm512_mask_i64gather_pd(__m512d s, __mmask8 k, __m512i vdx, void * base, int scale);
VGATHERQPD __m256d _mm256_mask_i64gather_pd(__m256d s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPD __m128d _mm_mask_i64gather_pd(__m128d s, __mmask8 k, __m128i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_i64gather_ps( __m512i vdx, void * base, int scale);
VGATHERQPS __m256 _mm512_mask_i64gather_ps(__m256 s, __mmask16 k, __m512i vdx, void * base, int scale);
VGATHERQPS __m128 _mm256_mask_i64gather_ps(__m128 s, __mmask8 k, __m256i vdx, void * base, int scale);
VGATHERQPS __m128 _mm_mask_i64gather_ps(__m128 s, __mmask8 k, __m128i vdx, void * base, int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12.






platform: x86_64
mnem: VPGATHERDD
description:
VPGATHERDD/VPGATHERQD - Gather Packed Dword Values Using Signed Dword/Qword
Indices
 Opcode/                                   Op/     64/32     CPUID      Description
 Instruction                               En      -bit      Feature
                                                   Mode      Flag
 VEX.DDS.128.66.0F38.W0 90 /r              RMV     V/V       AVX2       Using dword indices specified in vm32x, gather dword val-
 VPGATHERDD xmm1, vm32x, xmm2                                           ues from memory conditioned on mask specified by
                                                                        xmm2. Conditionally gathered elements are merged into
                                                                        xmm1.
 VEX.DDS.128.66.0F38.W0 91 /r              RMV     V/V       AVX2       Using qword indices specified in vm64x, gather dword val-
 VPGATHERQD xmm1, vm64x, xmm2                                           ues from memory conditioned on mask specified by
                                                                        xmm2. Conditionally gathered elements are merged into
                                                                        xmm1.
 VEX.DDS.256.66.0F38.W0 90 /r              RMV     V/V       AVX2       Using dword indices specified in vm32y, gather dword
 VPGATHERDD ymm1, vm32y, ymm2                                           from memory conditioned on mask specified by ymm2.
                                                                        Conditionally gathered elements are merged into ymm1.

 VEX.DDS.256.66.0F38.W0 91 /r              RMV     V/V       AVX2       Using qword indices specified in vm64y, gather dword val-
 VPGATHERQD xmm1, vm64y, xmm2                                           ues from memory conditioned on mask specified by
                                                                        xmm2. Conditionally gathered elements are merged into
                                                                        xmm1.



                                                 Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                     Operand 3                      Operand 4
   RMV           ModRM:reg (r,w)           BaseReg (R): VSIB:base,           VEX.vvvv (r, w)                     NA
                                          VectorReg(R): VSIB:index

Description
The instruction conditionally loads up to 4 or 8 dword values from memory addresses specified by the memory
operand (the second operand) and using dword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using qword indices, the instruction conditionally loads up to 2 or 4 qword values from the VSIB addressing
memory operand, and updates the lower half of the destination register. The upper 128 or 256 bits of the destina-
tion register are zero'ed with qword indices.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: For dword indices, the instruction will gather four dword values. For qword indices, the instruc-
tion will gather two values and zeroes the upper 64 bits of the destination.



VEX.256 version: For dword indices, the instruction will gather eight dword values. For qword indices, the instruc-
tion will gather four values and zeroes the upper 128 bits of the destination.
Note that:
.   If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
.   The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
    64 memory-ordering model.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
    to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
    conventional order.
.   Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   This instruction will cause a #UD if the address size attribute is 16-bit.
.   This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
.   This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
    is implementation specific, and some implementations may use loads larger than the data element size or load
    elements an indeterminate number of times.
.   The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
    bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
    bits are ignored.

Operation
DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;

VPGATHERDD (VEX.128 version)
FOR j<- 0 to 3
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 3
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)



VPGATHERQD (VEX.128 version)
FOR j<- 0 to 3
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 1
   k <- j * 64;
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
MASK[127:64] <- 0;
DEST[VLMAX-1:64] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)

VPGATHERDD (VEX.256 version)
FOR j<- 0 to 7
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 7
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)





VPGATHERQD (VEX.256 version)
FOR j<- 0 to 7
   i <- j * 32;
   IF MASK[31+i] THEN
        MASK[i +31:i] <- FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +31:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   k <- j * 64;
   i <- j * 32;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
   IF MASK[31+i] THEN
        DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +31:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)

Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index, const int scale);
VPGATHERDD: __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const * base, __m256i index, __m256i mask, const int
scale);
VPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const int scale);
VPGATHERQD: __m128i _mm_mask_i64gather_epi32 (__m128i src, int const * base, __m128i index, __m128i mask, const int scale);
VPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index, const int scale);
VPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const * base, __m256i index, __m128i mask, const int
scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 12.






platform: x86_64
mnem: VPGATHERDD
description:
VPGATHERDD/VPGATHERDQ-Gather Packed Dword, Packed Qword with Signed Dword Indices
    Opcode/                            Op/   64/32       CPUID          Description
    Instruction                        En    bit Mode    Feature
                                             Support     Flag
    EVEX.128.66.0F38.W0 90 /vsib       T1S   V/V         AVX512VL       Using signed dword indices, gather dword values from
    VPGATHERDD xmm1 {k1}, vm32x                          AVX512F        memory using writemask k1 for merging-masking.
    EVEX.256.66.0F38.W0 90 /vsib       T1S   V/V         AVX512VL       Using signed dword indices, gather dword values from
    VPGATHERDD ymm1 {k1}, vm32y                          AVX512F        memory using writemask k1 for merging-masking.
    EVEX.512.66.0F38.W0 90 /vsib       T1S   V/V         AVX512F        Using signed dword indices, gather dword values from
    VPGATHERDD zmm1 {k1}, vm32z                                         memory using writemask k1 for merging-masking.
    EVEX.128.66.0F38.W1 90 /vsib       T1S   V/V         AVX512VL       Using signed dword indices, gather quadword values from
    VPGATHERDQ xmm1 {k1}, vm32x                          AVX512F        memory using writemask k1 for merging-masking.
    EVEX.256.66.0F38.W1 90 /vsib       T1S   V/V         AVX512VL       Using signed dword indices, gather quadword values from
    VPGATHERDQ ymm1 {k1}, vm32x                          AVX512F        memory using writemask k1 for merging-masking.
    EVEX.512.66.0F38.W1 90 /vsib       T1S   V/V         AVX512F        Using signed dword indices, gather quadword values from
    VPGATHERDQ zmm1 {k1}, vm32y                                         memory using writemask k1 for merging-masking.



                                               Instruction Operand Encoding
        Op/En            Operand 1                  Operand 2                   Operand 3                    Operand 4
                                              BaseReg (R): VSIB:base,
         T1S           ModRM:reg (w)                                                  NA                        NA
                                             VectorReg(R): VSIB:index

Description
A set of 16 or 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into vector zmm1. The elements are specified via the
VSIB (i.e., the index register is a zmm, holding packed indices). Elements will only be loaded if their corresponding
mask bit is one. If an element's mask bit is not set, the corresponding element of the destination register (zmm1)
is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
.     The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
      64 memory-ordering model.
.     Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
      elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
      closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
      in the conventional order.
.     Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
      the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
      instruction is repeatable - given the same input values and architectural state, the same set of elements to the
      left of the faulting one will be gathered.
.     This instruction does not perform AC checks, and so will never deliver an AC fault.
.     Not valid with 16-bit effective addresses. Will deliver a #UD fault.
.     These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.


Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement

VPGATHERDD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         THEN DEST[i+31:i] <- MEM[BASE_ADDR +
                         SignExtend(VINDEX[i+31:i]) * SCALE + DISP]), 1)
               k1[j] <- 0
         ELSE *DEST[i+31:i] <- remains unchanged*             ; Only merging masking is allowed
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0

VPGATHERDQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         THEN DEST[i+63:i] <-
               MEM[BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP])
               k1[j] <- 0
         ELSE *DEST[i+63:i] <- remains unchanged*       ; Only merging masking is allowed
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDD __m512i _mm512_i32gather_epi32( __m512i vdx, void * base, int scale);
VPGATHERDD __m512i _mm512_mask_i32gather_epi32(__m512i s, __mmask16 k, __m512i vdx, void * base, int scale);
VPGATHERDD __m256i _mm256_mmask_i32gather_epi32(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDD __m128i _mm_mmask_i32gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_i32logather_epi64( __m256i vdx, void * base, int scale);
VPGATHERDQ __m512i _mm512_mask_i32logather_epi64(__m512i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERDQ __m256i _mm256_mmask_i32logather_epi64(__m256i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERDQ __m128i _mm_mmask_i32gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12.






