# instructions

platform: x86_64
mnem: CMPXCHG
description:
CMPXCHG-Compare and Exchange
Opcode/                                Op/    64-Bit       Compat/ Description
Instruction                            En     Mode         Leg Mode
0F B0/r                                MR     Valid        Valid*      Compare AL with r/m8. If equal, ZF is set and r8 is loaded into
CMPXCHG r/m8, r8                                                       r/m8. Else, clear ZF and load r/m8 into AL.

REX + 0F B0/r                          MR     Valid        N.E.        Compare AL with r/m8. If equal, ZF is set and r8 is loaded into
CMPXCHG r/m8**,r8                                                      r/m8. Else, clear ZF and load r/m8 into AL.

0F B1/r                                MR     Valid        Valid*      Compare AX with r/m16. If equal, ZF is set and r16 is loaded
CMPXCHG r/m16, r16                                                     into r/m16. Else, clear ZF and load r/m16 into AX.
0F B1/r                                MR     Valid        Valid*      Compare EAX with r/m32. If equal, ZF is set and r32 is loaded
CMPXCHG r/m32, r32                                                     into r/m32. Else, clear ZF and load r/m32 into EAX.

REX.W + 0F B1/r                        MR     Valid        N.E.        Compare RAX with r/m64. If equal, ZF is set and r64 is loaded
CMPXCHG r/m64, r64                                                     into r/m64. Else, clear ZF and load r/m64 into RAX.

NOTES:
* See the IA-32 Architecture Compatibility section below.
** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                 Instruction Operand Encoding
  Op/En               Operand 1                         Operand 2                     Operand 3                    Operand 4
    MR             ModRM:r/m (r, w)                    ModRM:reg (r)                     NA                            NA

Description
Compares the value in the AL, AX, EAX, or RAX register with the first operand (destination operand). If the two
values are equal, the second operand (source operand) is loaded into the destination operand. Otherwise, the
destination operand is loaded into the AL, AX, EAX or RAX register. RAX register is available only in 64-bit mode.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the
interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is
written into the destination. (The processor never produces a locked read without also producing a locked write.)
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.

IA-32 Architecture Compatibility
This instruction is not supported on Intel processors earlier than the Intel486 processors.

Operation
(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or quadword comparison is being performed *)
TEMP <- DEST
IF accumulator = TEMP
    THEN
        ZF <- 1;
        DEST <- SRC;
    ELSE
        ZF <- 0;
        accumulator <- TEMP;
        DEST <- TEMP;
FI;



Flags Affected
The ZF flag is set if the values in the destination operand and register AL, AX, or EAX are equal; otherwise it is
cleared. The CF, PF, AF, SF, and OF flags are set according to the results of the comparison operation.

Protected Mode Exceptions
#GP(0)               If the destination is located in a non-writable segment.
                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                  If a memory operand effective address is outside the SS segment limit.
#UD                  If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.
#UD                  If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the memory address is in a non-canonical form.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: CMPXCHG8B
description:
CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes
Opcode/                                Op/    64-Bit          Compat/ Description
Instruction                            En     Mode            Leg Mode
0F C7 /1 m64                           M      Valid           Valid*   Compare EDX:EAX with m64. If equal, set ZF and load
CMPXCHG8B m64                                                          ECX:EBX into m64. Else, clear ZF and load m64 into EDX:EAX.

REX.W + 0F C7 /1 m128                  M      Valid           N.E.     Compare RDX:RAX with m128. If equal, set ZF and load
CMPXCHG16B m128                                                        RCX:RBX into m128. Else, clear ZF and load m128 into
                                                                       RDX:RAX.
NOTES:
*See IA-32 Architecture Compatibility section below.



                                                Instruction Operand Encoding
  Op/En              Operand 1                        Operand 2                  Operand 3                    Operand 4
    M            ModRM:r/m (r, w)                        NA                         NA                            NA

Description
Compares the 64-bit value in EDX:EAX (or 128-bit value in RDX:RAX if operand size is 128 bits) with the operand
(destination operand). If the values are equal, the 64-bit value in ECX:EBX (or 128-bit value in RCX:RBX) is stored
in the destination operand. Otherwise, the value in the destination operand is loaded into EDX:EAX (or RDX:RAX).
The destination operand is an 8-byte memory location (or 16-byte memory location if operand size is 128 bits). For
the EDX:EAX and ECX:EBX register pairs, EDX and ECX contain the high-order 32 bits and EAX and EBX contain the
low-order 32 bits of a 64-bit value. For the RDX:RAX and RCX:RBX register pairs, RDX and RCX contain the high-
order 64 bits and RAX and RBX contain the low-order 64bits of a 128-bit value.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically. To simplify the
interface to the processor's bus, the destination operand receives a write cycle without regard to the result of the
comparison. The destination operand is written back if the comparison fails; otherwise, the source operand is
written into the destination. (The processor never produces a locked read without also producing a locked write.)
In 64-bit mode, default operation size is 64 bits. Use of the REX.W prefix promotes operation to 128 bits. Note that
CMPXCHG16B requires that the destination (memory) operand be 16-byte aligned. See the summary chart at the
beginning of this section for encoding data and limits. For information on the CPUID flag that indicates
CMPXCHG16B, see page 3-206.

IA-32 Architecture Compatibility
This instruction encoding is not supported on Intel processors earlier than the Pentium processors.





Operation
IF (64-Bit Mode and OperandSize = 64)
    THEN
         TEMP128 <- DEST
         IF (RDX:RAX = TEMP128)
              THEN
                  ZF <- 1;
                  DEST <- RCX:RBX;
              ELSE
                  ZF <- 0;
                  RDX:RAX <- TEMP128;
                  DEST <- TEMP128;
                  FI;
         FI
    ELSE
         TEMP64 <- DEST;
         IF (EDX:EAX = TEMP64)
              THEN
                  ZF <- 1;
                  DEST <- ECX:EBX;
              ELSE
                  ZF <- 0;
                  EDX:EAX <- TEMP64;
                  DEST <- TEMP64;
                  FI;
         FI;
FI;

Flags Affected
The ZF flag is set if the destination operand and EDX:EAX are equal; otherwise it is cleared. The CF, PF, AF, SF, and
OF flags are unaffected.

Protected Mode Exceptions
#UD                  If the destination is not a memory operand.
#GP(0)               If the destination is located in a non-writable segment.
                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.

Real-Address Mode Exceptions
#UD                  If the destination operand is not a memory location.
#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                  If a memory operand effective address is outside the SS segment limit.





Virtual-8086 Mode Exceptions
#UD                  If the destination operand is not a memory location.
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the memory address is in a non-canonical form.
                     If memory operand for CMPXCHG16B is not aligned on a 16-byte boundary.
                     If CPUID.01H:ECX.CMPXCHG16B[bit 13] = 0.
#UD                  If the destination operand is not a memory location.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.






platform: x86_64
mnem: COMISD
description:
COMISD-Compare Scalar Ordered Double-Precision Floating-Point Values and Set EFLAGS
 Opcode/                              Op /    64/32        CPUID         Description
 Instruction                          En      bit Mode     Feature
                                              Support      Flag
 66 0F 2F /r                          RM      V/V          SSE2          Compare low double-precision floating-point values in
 COMISD xmm1, xmm2/m64                                                   xmm1 and xmm2/mem64 and set the EFLAGS flags
                                                                         accordingly.
 VEX.128.66.0F.WIG 2F /r              RM      V/V          AVX           Compare low double-precision floating-point values in
 VCOMISD xmm1, xmm2/m64                                                  xmm1 and xmm2/mem64 and set the EFLAGS flags
                                                                         accordingly.
 EVEX.LIG.66.0F.W1 2F /r              T1S     V/V          AVX512F       Compare low double-precision floating-point values in
 VCOMISD xmm1, xmm2/m64{sae}                                             xmm1 and xmm2/mem64 and set the EFLAGS flags
                                                                         accordingly.



                                             Instruction Operand Encoding
      Op/En            Operand 1                    Operand 2                   Operand 3                      Operand 4
       RM            ModRM:reg (w)              ModRM:r/m (r)                       NA                            NA
       T1S           ModRM:reg (w)              ModRM:r/m (r)                       NA                            NA

Description
Compares the double-precision floating-point values in the low quadwords of operand 1 (first operand) and
operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-
dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-
dered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location. The COMISD instruction differs from the UCOMISD instruction in that it signals a SIMD floating-point
invalid operation exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISD instruction signals
an invalid numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
COMISD (all versions)
RESULT <- OrderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
    UNORDERED: ZF,PF,CF <- 111;
    GREATER_THAN: ZF,PF,CF <- 000;
    LESS_THAN: ZF,PF,CF <- 001;
    EQUAL: ZF,PF,CF <- 100;
ESAC;
OF, AF, SF <-0; }





Intel C/C++ Compiler Intrinsic Equivalent
VCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
VCOMISD int _mm_comieq_sd (__m128d a, __m128d b)
VCOMISD int _mm_comilt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comile_sd (__m128d a, __m128d b)
VCOMISD int _mm_comigt_sd (__m128d a, __m128d b)
VCOMISD int _mm_comige_sd (__m128d a, __m128d b)
VCOMISD int _mm_comineq_sd (__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: COMISS
description:
COMISS-Compare Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS
 Opcode/                              Op /    64/32         CPUID          Description
 Instruction                          En      bit Mode      Feature
                                              Support       Flag
 0F 2F /r                             RM      V/V           SSE            Compare low single-precision floating-point values in
 COMISS xmm1, xmm2/m32                                                     xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                           accordingly.
 VEX.128.0F.WIG 2F /r                 RM      V/V           AVX            Compare low single-precision floating-point values in
 VCOMISS xmm1, xmm2/m32                                                    xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                           accordingly.
 EVEX.LIG.0F.W0 2F /r                 T1S     V/V           AVX512F        Compare low single-precision floating-point values in
 VCOMISS xmm1, xmm2/m32{sae}                                               xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                           accordingly.



                                             Instruction Operand Encoding
     Op/En             Operand 1                    Operand 2                      Operand 3                     Operand 4
       RM            ModRM:reg (w)              ModRM:r/m (r)                          NA                            NA
      T1S            ModRM:reg (w)              ModRM:r/m (r)                          NA                            NA

Description
Compares the single-precision floating-point values in the low quadwords of operand 1 (first operand) and operand
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unordered,
greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result
is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.
The COMISS instruction differs from the UCOMISS instruction in that it signals a SIMD floating-point invalid opera-
tion exception (#I) when a source operand is either a QNaN or SNaN. The UCOMISS instruction signals an invalid
numeric exception only if a source operand is an SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
COMISS (all versions)
RESULT <- OrderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
    UNORDERED: ZF,PF,CF <- 111;
    GREATER_THAN: ZF,PF,CF <- 000;
    LESS_THAN: ZF,PF,CF <- 001;
    EQUAL: ZF,PF,CF <- 100;
ESAC;
OF, AF, SF <- 0; }





Intel C/C++ Compiler Intrinsic Equivalent
VCOMISS int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
VCOMISS int _mm_comieq_ss (__m128 a, __m128 b)
VCOMISS int _mm_comilt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comile_ss (__m128 a, __m128 b)
VCOMISS int _mm_comigt_ss (__m128 a, __m128 b)
VCOMISS int _mm_comige_ss (__m128 a, __m128 b)
VCOMISS int _mm_comineq_ss (__m128 a, __m128 b)

SIMD Floating-Point Exceptions
Invalid (if SNaN or QNaN operands), Denormal.

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CPUID
description:
CPUID-CPU Identification
Opcode                    Instruction                  Op/   64-Bit      Compat/ Description
                                                       En    Mode        Leg Mode
0F A2                     CPUID                        NP    Valid       Valid       Returns processor identification and feature
                                                                                     information to the EAX, EBX, ECX, and EDX
                                                                                     registers, as determined by input entered in
                                                                                     EAX (in some cases, ECX as well).



                                                Instruction Operand Encoding
  Op/En               Operand 1                     Operand 2                     Operand 3                    Operand 4
    NP                   NA                             NA                            NA                           NA

Description
The ID flag (bit 21) in the EFLAGS register indicates support for the CPUID instruction. If a software procedure can
set and clear this flag, the processor executing the procedure supports the CPUID instruction. This instruction oper-
ates the same in non-64-bit modes and 64-bit mode.
CPUID returns processor identification and feature information in the EAX, EBX, ECX, and EDX registers.1 The
instruction's output is dependent on the contents of the EAX register upon execution (in some cases, ECX as well).
For example, the following pseudocode loads EAX with 00H and causes CPUID to return a Maximum Return Value
and the Vendor Identification String in the appropriate registers:

   MOV EAX, 00H
   CPUID
Table 3-8 shows information returned, depending on the initial value loaded into the EAX register.
Two types of information are returned: basic and extended function information. If a value entered for CPUID.EAX
is higher than the maximum input value for basic or extended function for that processor then the data for the
highest basic information leaf is returned. For example, using the Intel Core i7 processor, the following is true:
   CPUID.EAX = 05H (* Returns MONITOR/MWAIT leaf. *)
   CPUID.EAX = 0AH (* Returns Architectural Performance Monitoring leaf. *)
   CPUID.EAX = 0BH (* Returns Extended Topology Enumeration leaf. *)
   CPUID.EAX = 0CH (* INVALID: Returns the same information as CPUID.EAX = 0BH. *)
   CPUID.EAX = 80000008H (* Returns linear/physical address size data. *)
   CPUID.EAX = 8000000AH (* INVALID: Returns same information as CPUID.EAX = 0BH. *)
If a value entered for CPUID.EAX is less than or equal to the maximum input value and the leaf is not supported on
that processor then 0 is returned in all the registers.
When CPUID returns the highest basic leaf information as a result of an invalid input EAX value, any dependence
on input ECX value in the basic leaf is honored.
CPUID can be executed at any privilege level to serialize instruction execution. Serializing instruction execution
guarantees that any modifications to flags, registers, and memory for previous instructions are completed before
the next instruction is fetched and executed.
See also:
"Serializing Instructions" in Chapter 8, "Multiple-Processor Management," in the Intel 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A.
"Caching Translation Information" in Chapter 4, "Paging," in the Intel 64 and IA-32 Architectures Software Devel-
oper's Manual, Volume 3A.




1. On Intel 64 processors, CPUID clears the high 32 bits of the RAX/RBX/RCX/RDX registers in all modes.



                                     Table 3-8. Information Returned by CPUID Instruction
  Initial EAX
     Value                                          Information Provided about the Processor
                 Basic CPUID Information
      0H         EAX        Maximum Input Value for Basic CPUID Information.
                 EBX        "Genu"
                 ECX        "ntel"
                 EDX        "ineI"
      01H        EAX        Version Information: Type, Family, Model, and Stepping ID (see Figure 3-6).
                 EBX        Bits 07 - 00: Brand Index.
                            Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size in bytes; used also by CLFLUSHOPT).
                            Bits 23 - 16: Maximum number of addressable IDs for logical processors in this physical package*.
                            Bits 31 - 24: Initial APIC ID.
                 ECX        Feature Information (see Figure 3-7 and Table 3-10).
                 EDX        Feature Information (see Figure 3-8 and Table 3-11).
                            NOTES:
                            * The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APIC
                              IDs reserved for addressing different logical processors in a physical package. This field is only valid if
                              CPUID.1.EDX.HTT[bit 28]= 1.
      02H        EAX        Cache and TLB Information (see Table 3-12).
                 EBX        Cache and TLB Information.
                 ECX        Cache and TLB Information.
                 EDX        Cache and TLB Information.
      03H        EAX        Reserved.
                 EBX        Reserved.
                 ECX        Bits 00 - 31 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
                            value in this register is reserved.)
                 EDX        Bits 32 - 63 of 96 bit processor serial number. (Available in Pentium III processor only; otherwise, the
                            value in this register is reserved.)
                            NOTES:
                              Processor serial number (PSN) is not supported in the Pentium 4 processor or later. On all models, use
                              the PSN flag (returned using CPUID) to check for PSN support before accessing the feature.
 CPUID leaves above 2 and below 80000000H are visible only when IA32_MISC_ENABLE[bit 22] has its default value of 0.
                 Deterministic Cache Parameters Leaf
      04H                   NOTES:
                              Leaf 04H output depends on the initial value in ECX.*
                              See also: "INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level" on page 214.

                 EAX        Bits 04 - 00: Cache Type Field.
                              0 = Null - No more caches.
                              1 = Data Cache.
                              2 = Instruction Cache.
                              3 = Unified Cache.
                              4-31 = Reserved.





                           Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                         Information Provided about the Processor
                         Bits 07 - 05: Cache Level (starts at 1).
                         Bit 08: Self Initializing cache level (does not need SW initialization).
                         Bit 09: Fully Associative cache.
                         Bits 13 - 10: Reserved.
                         Bits 25 - 14: Maximum number of addressable IDs for logical processors sharing this cache**, ***.
                         Bits 31 - 26: Maximum number of addressable IDs for processor cores in the physical
                         package**, ****, *****.
                EBX      Bits 11 - 00: L = System Coherency Line Size**.
                         Bits 21 - 12: P = Physical Line partitions**.
                         Bits 31 - 22: W = Ways of associativity**.
                ECX      Bits 31-00: S = Number of Sets**.
                EDX      Bit 00: Write-Back Invalidate/Invalidate.
                           0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this
                           cache.
                           1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing
                           this cache.
                         Bit 01: Cache Inclusiveness.
                           0 = Cache is not inclusive of lower cache levels.
                           1 = Cache is inclusive of lower cache levels.
                         Bit 02: Complex Cache Indexing.
                           0 = Direct mapped cache.
                           1 = A complex function is used to index the cache, potentially using all address bits.
                         Bits 31 - 03: Reserved = 0.
                         NOTES:
                         * If ECX contains an invalid sub leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n+1 is invalid if sub-
                            leaf n returns EAX[4:0] as 0.
                         ** Add one to the return value to get the result.
                         ***The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique ini-
                            tial APIC IDs reserved for addressing different logical processors sharing this cache.
                         **** The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique
                            Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of
                            bits of the initial APIC ID.
                         ***** The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.
                MONITOR/MWAIT Leaf
     05H        EAX      Bits 15 - 00: Smallest monitor-line size in bytes (default is processor's monitor granularity).
                         Bits 31 - 16: Reserved = 0.
                EBX      Bits 15 - 00: Largest monitor-line size in bytes (default is processor's monitor granularity).
                         Bits 31 - 16: Reserved = 0.
                ECX      Bit 00: Enumeration of Monitor-Mwait extensions (beyond EAX and EBX registers) supported.
                         Bit 01: Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.
                         Bits 31 - 02: Reserved.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                         Information Provided about the Processor
                 EDX       Bits 03 - 00: Number of C0* sub C-states supported using MWAIT.
                           Bits 07 - 04: Number of C1* sub C-states supported using MWAIT.
                           Bits 11 - 08: Number of C2* sub C-states supported using MWAIT.
                           Bits 15 - 12: Number of C3* sub C-states supported using MWAIT.
                           Bits 19 - 16: Number of C4* sub C-states supported using MWAIT.
                           Bits 23 - 20: Number of C5* sub C-states supported using MWAIT.
                           Bits 27 - 24: Number of C6* sub C-states supported using MWAIT.
                           Bits 31 - 28: Number of C7* sub C-states supported using MWAIT.
                           NOTE:
                           * The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-
                              states.
                 Thermal and Power Management Leaf
      06H        EAX       Bit 00: Digital temperature sensor is supported if set.
                           Bit 01: Intel Turbo Boost Technology Available (see description of IA32_MISC_ENABLE[38]).
                           Bit 02: ARAT. APIC-Timer-always-running feature is supported if set.
                           Bit 03: Reserved.
                           Bit 04: PLN. Power limit notification controls are supported if set.
                           Bit 05: ECMD. Clock modulation duty cycle extension is supported if set.
                           Bit 06: PTM. Package thermal management is supported if set.
                           Bit 07: HWP. HWP base registers (IA32_PM_ENABLE[bit 0], IA32_HWP_CAPABILITIES,
                           IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.
                           Bit 08: HWP_Notification. IA32_HWP_INTERRUPT MSR is supported if set.
                           Bit 09: HWP_Activity_Window. IA32_HWP_REQUEST[bits 41:32] is supported if set.
                           Bit 10: HWP_Energy_Performance_Preference. IA32_HWP_REQUEST[bits 31:24] is supported if set.
                           Bit 11: HWP_Package_Level_Request. IA32_HWP_REQUEST_PKG MSR is supported if set.
                           Bit 12: Reserved.
                           Bit 13: HDC. HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are
                           supported if set.
                           Bits 31 - 15: Reserved.
                 EBX       Bits 03 - 00: Number of Interrupt Thresholds in Digital Thermal Sensor.
                           Bits 31 - 04: Reserved.
                 ECX       Bit 00: Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The
                           capability to provide a measure of delivered processor performance (since last reset of the counters), as
                           a percentage of the expected processor performance when running at the TSC frequency.
                           Bits 02 - 01: Reserved = 0.
                           Bit 03: The processor supports performance-energy bias preference if CPUID.06H:ECX.SETBH[bit 3] is set
                           and it also implies the presence of a new architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).
                           Bits 31 - 04: Reserved = 0.
                 EDX       Reserved = 0.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                         Information Provided about the Processor
                Structured Extended Feature Flags Enumeration Leaf (Output depends on ECX input value)
     07H                     Sub-leaf 0 (Input ECX = 0). *


                EAX        Bits 31 - 00: Reports the maximum input value for supported leaf 7 sub-leaves.
                EBX        Bit 00: FSGSBASE. Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.
                           Bit 01: IA32_TSC_ADJUST MSR is supported if 1.
                           Bit 02: SGX. Supports Intel Software Guard Extensions (Intel SGX Extensions) if 1.
                           Bit 03: BMI1.
                           Bit 04: HLE.
                           Bit 05: AVX2.
                           Bit 06: FDP_EXCPTN_ONLY. x87 FPU Data Pointer updated only on x87 exceptions if 1.
                           Bit 07: SMEP. Supports Supervisor-Mode Execution Prevention if 1.
                           Bit 08: BMI2.
                           Bit 09: Supports Enhanced REP MOVSB/STOSB if 1.
                           Bit 10: INVPCID. If 1, supports INVPCID instruction for system software that manages process-context
                           identifiers.
                           Bit 11: RTM.
                           Bit 12: RDT-M. Supports Intel Resource Director Technology (Intel RDT) Monitoring capability if 1.
                           Bit 13: Deprecates FPU CS and FPU DS values if 1.
                           Bit 14: MPX. Supports Intel Memory Protection Extensions if 1.
                           Bit 15: RDT-A. Supports Intel Resource Director Technology (Intel RDT) Allocation capability if 1.
                           Bits 17:16: Reserved.
                           Bit 18: RDSEED.
                           Bit 19: ADX.
                           Bit 20: SMAP. Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.
                           Bits 22 - 21: Reserved.
                           Bit 23: CLFLUSHOPT.
                           Bit 24: CLWB.
                           Bit 25: Intel Processor Trace.
                           Bits 28 - 26: Reserved.
                           Bit 29: SHA. supports Intel Secure Hash Algorithm Extensions (Intel SHA Extensions) if 1.
                           Bits 31 - 30: Reserved.
                ECX        Bit 00: PREFETCHWT1.
                           Bit 01: Reserved.
                           Bit 02: UMIP. Supports user-mode instruction prevention if 1.
                           Bit 03: PKU. Supports protection keys for user-mode pages if 1.
                           Bit 04: OSPKE. If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instruc-
                           tions).
                           Bits 16 - 5: Reserved.
                           Bits 21 - 17: The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.
                           Bit 22: RDPID. Supports Read Processor ID if 1.
                           Bits 29 - 23: Reserved.
                           Bit 30: SGX_LC. Supports SGX Launch Configuration if 1.
                           Bit 31: Reserved.
                EDX        Reserved.

                           NOTE:
                           * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf index n is invalid if n
                              exceeds the value that sub-leaf 0 returns in EAX.





                              Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                           Information Provided about the Processor
                 Direct Cache Access Information Leaf
      09H        EAX        Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).
                 EBX        Reserved.
                 ECX        Reserved.
                 EDX        Reserved.
                 Architectural Performance Monitoring Leaf
      0AH        EAX        Bits 07 - 00: Version ID of architectural performance monitoring.
                            Bits 15 - 08: Number of general-purpose performance monitoring counter per logical processor.
                            Bits 23 - 16: Bit width of general-purpose, performance monitoring counter.
                            Bits 31 - 24: Length of EBX bit vector to enumerate architectural performance monitoring events.
                 EBX        Bit 00: Core cycle event not available if 1.
                            Bit 01: Instruction retired event not available if 1.
                            Bit 02: Reference cycles event not available if 1.
                            Bit 03: Last-level cache reference event not available if 1.
                            Bit 04: Last-level cache misses event not available if 1.
                            Bit 05: Branch instruction retired event not available if 1.
                            Bit 06: Branch mispredict retired event not available if 1.
                            Bits 31 - 07: Reserved = 0.
                 ECX        Reserved = 0.
                 EDX        Bits 04 - 00: Number of fixed-function performance counters (if Version ID > 1).
                            Bits 12 - 05: Bit width of fixed-function performance counters (if Version ID > 1).
                            Reserved = 0.
                 Extended Topology Enumeration Leaf
      0BH                   NOTES:
                              Most of Leaf 0BH output depends on the initial value in ECX.
                              The EDX output of leaf 0BH is always valid and does not vary with input value in ECX.
                              Output value in ECX[7:0] always equals input value in ECX[7:0].
                              For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0.
                              If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8], other input values with ECX >
                              n also return 0 in ECX[15:8].


                 EAX        Bits 04 - 00: Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type*.
                            All logical processors with the same next level ID share current level.
                            Bits 31 - 05: Reserved.
                 EBX        Bits 15 - 00: Number of logical processors at this level type. The number reflects configuration as shipped
                            by Intel**.
                            Bits 31- 16: Reserved.
                 ECX        Bits 07 - 00: Level number. Same value in ECX input.
                            Bits 15 - 08: Level type***.
                            Bits 31 - 16: Reserved.
                 EDX        Bits 31- 00: x2APIC ID the current logical processor.
                            NOTES:
                            * Software should use this field (EAX[4:0]) to enumerate processor topology of the system.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                          Information Provided about the Processor
                           ** Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this
                           field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors
                           available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software
                           and platform hardware configurations.

                           *** The value of the "level type" field is not related to level numbers in any way, higher "level type" val-
                           ues do not mean higher levels. Level type field has the following encoding:
                           0: Invalid.
                           1: SMT.
                           2: Core.
                           3-255: Reserved.
                Processor Extended State Enumeration Main Leaf (EAX = 0DH, ECX = 0)
     0DH                   NOTES:
                             Leaf 0DH main leaf (ECX = 0).
                EAX        Bits 31 - 00: Reports the supported bits of the lower 32 bits of XCR0. XCR0[n] can be set to 1 only if
                           EAX[n] is 1.
                           Bit 00: x87 state.
                           Bit 01: SSE state.
                           Bit 02: AVX state.
                           Bits 04 - 03: MPX state.
                           Bits 07 - 05: AVX-512 state.
                           Bit 08: Used for IA32_XSS.
                           Bit 09: PKRU state.
                           Bits 31 - 10: Reserved.
                EBX        Bits 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) required by
                           enabled features in XCR0. May be different than ECX if some features at the end of the XSAVE save area
                           are not enabled.
                ECX        Bit 31 - 00: Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save area) of the
                           XSAVE/XRSTOR save area required by all supported features in the processor, i.e., all the valid bit fields in
                           XCR0.
                EDX        Bit 31 - 00: Reports the supported bits of the upper 32 bits of XCR0. XCR0[n+32] can be set to 1 only if
                           EDX[n] is 1.
                           Bits 31 - 00: Reserved.
                Processor Extended State Enumeration Sub-leaf (EAX = 0DH, ECX = 1)
     0DH        EAX        Bit 00: XSAVEOPT is available.
                           Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set.
                           Bit 02: Supports XGETBV with ECX = 1 if set.
                           Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set.
                           Bits 31 - 04: Reserved.
                EBX        Bits 31 - 00: The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
                ECX        Bits 31 - 00: Reports the supported bits of the lower 32 bits of the IA32_XSS MSR. IA32_XSS[n] can be
                           set to 1 only if ECX[n] is 1.
                           Bits 07 - 00: Used for XCR0.
                           Bit 08: PT state.
                           Bit 09: Used for XCR0.
                           Bits 31 - 10: Reserved.
                EDX        Bits 31 - 00: Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n+32] can
                           be set to 1 only if EDX[n] is 1.
                           Bits 31 - 00: Reserved.




                              Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                            Information Provided about the Processor
                 Processor Extended State Enumeration Sub-leaves (EAX = 0DH, ECX = n, n > 1)
      0DH                   NOTES:
                              Leaf 0DH output depends on the initial value in ECX.
                              Each sub-leaf index (starting at position 2) is supported if it corresponds to a supported bit in either the
                              XCR0 register or the IA32_XSS MSR.
                             * If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf n (0 <= n <= 31) is invalid
                               if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1 returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if
                               sub-leaf 0 returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].
                 EAX        Bits 31 - 0: The size in bytes (from the offset specified in EBX) of the save area for an extended state
                            feature associated with a valid sub-leaf index, n.
                 EBX        Bits 31 - 0: The offset in bytes of this extended state component's save area from the beginning of the
                            XSAVE/XRSTOR area.
                            This field reports 0 if the sub-leaf index, n, does not map to a valid bit in the XCR0 register*.
                 ECX        Bit 00 is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear
                            if bit n is instead supported in XCR0.
                            Bit 01 is set if, when the compacted format of an XSAVE area is used, this extended state component
                            located on the next 64-byte boundary following the preceding state component (otherwise, it is located
                            immediately following the preceding state component).
                            Bits 31 - 02 are reserved.
                            This field reports 0 if the sub-leaf index, n, is invalid*.
                 EDX        This field reports 0 if the sub-leaf index, n, is invalid*; otherwise it is reserved.
                 Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Sub-leaf (EAX = 0FH, ECX = 0)
      0FH                   NOTES:
                              Leaf 0FH output depends on the initial value in ECX.
                              Sub-leaf index 0 reports valid resource type starting at bit position 1 of EDX.
                 EAX        Reserved.
                 EBX        Bits 31 - 00: Maximum range (zero-based) of RMID within this physical processor of all types.
                 ECX        Reserved.
                 EDX        Bit 00: Reserved.
                            Bit 01: Supports L3 Cache Intel RDT Monitoring if 1.
                            Bits 31 - 02: Reserved.
                 L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf (EAX = 0FH, ECX = 1)
      0FH                   NOTES:
                              Leaf 0FH output depends on the initial value in ECX.
                 EAX        Reserved.
                 EBX        Bits 31 - 00: Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).
                 ECX        Maximum range (zero-based) of RMID of this resource type.
                 EDX        Bit 00: Supports L3 occupancy monitoring if 1.
                            Bit 01: Supports L3 Total Bandwidth monitoring if 1.
                            Bit 02: Supports L3 Local Bandwidth monitoring if 1.
                            Bits 31 - 03: Reserved.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                           Information Provided about the Processor
                Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf (EAX = 10H, ECX = 0)
     10H                   NOTES:
                             Leaf 10H output depends on the initial value in ECX.
                             Sub-leaf index 0 reports valid resource identification (ResID) starting at bit position 1 of EBX.
                EAX        Reserved.
                EBX        Bit 00: Reserved.
                           Bit 01: Supports L3 Cache Allocation Technology if 1.
                           Bit 02: Supports L2 Cache Allocation Technology if 1.
                           Bits 31 - 03: Reserved.
                ECX        Reserved.
                EDX        Reserved.
                L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =1)
     10H                   NOTES:
                             Leaf 10H output depends on the initial value in ECX.
                EAX        Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
                           Bits 31 - 05: Reserved.
                EBX        Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
                ECX        Bit 00: Reserved.
                           Bit 01: Updates of COS should be infrequent if 1.
                           Bit 02: Code and Data Prioritization Technology supported if 1.
                           Bits 31 - 03: Reserved.
                EDX        Bits 15 - 00: Highest COS number supported for this ResID.
                           Bits 31 - 16: Reserved.
                L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID =2)
     10H                   NOTES:
                             Leaf 10H output depends on the initial value in ECX.
                EAX        Bits 4 - 00: Length of the capacity bit mask for the corresponding ResID using minus-one notation.
                           Bits 31 - 05: Reserved.
                EBX        Bits 31 - 00: Bit-granular map of isolation/contention of allocation units.
                ECX        Bits 31 - 00: Reserved.
                EDX        Bits 15 - 00: Highest COS number supported for this ResID.
                           Bits 31 - 16: Reserved.
                Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0)
     12H                   NOTES:
                             Leaf 12H sub-leaf 0 (ECX = 0) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
                EAX        Bit 00: SGX1. If 1, Indicates Intel SGX supports the collection of SGX1 leaf functions.
                           Bit 01: SGX2. If 1, Indicates Intel SGX supports the collection of SGX2 leaf functions.
                           Bit 31 - 02: Reserved.
                EBX        Bit 31 - 00: MISCSELECT. Bit vector of supported extended SGX features.
                ECX        Bit 31 - 00: Reserved.





                              Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                           Information Provided about the Processor
                 EDX        Bit 07 - 00: MaxEnclaveSize_Not64. The maximum supported enclave size in non-64-bit mode is
                            2^(EDX[7:0]).
                            Bit 15 - 08: MaxEnclaveSize_64. The maximum supported enclave size in 64-bit mode is 2^(EDX[15:8]).
                            Bits 31 - 16: Reserved.
                 Intel SGX Attributes Enumeration Leaf, sub-leaf 1 (EAX = 12H, ECX = 1)
      12H                   NOTES:
                              Leaf 12H sub-leaf 1 (ECX = 1) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
                 EAX        Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[31:0] that software can set with ECREATE.
                 EBX        Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[63:32] that software can set with ECREATE.
                 ECX        Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[95:64] that software can set with ECREATE.
                 EDX        Bit 31 - 00: Reports the valid bits of SECS.ATTRIBUTES[127:96] that software can set with ECREATE.
                 Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
      12H                   NOTES:
                              Leaf 12H sub-leaf 2 or higher (ECX >= 2) is supported if CPUID.(EAX=07H, ECX=0H):EBX[SGX] = 1.
                              For sub-leaves (ECX = 2 or higher), definition of EDX,ECX,EBX,EAX[31:4] depends on the sub-leaf type
                              listed below.
                 EAX        Bit 03 - 00: Sub-leaf Type
                              0000b: Indicates this sub-leaf is invalid.
                              0001b: This sub-leaf enumerates an EPC section. EBX:EAX and EDX:ECX provide information on the
                              Enclave Page Cache (EPC) section.
                              All other type encodings are reserved.
                 Type       0000b. This sub-leaf is invalid.
                              EDX:ECX:EBX:EAX return 0.
                 Type       0001b. This sub-leaf enumerates an EPC sections with EDX:ECX, EBX:EAX defined as follows.
                              EAX[11:04]: Reserved (enumerate 0).
                              EAX[31:12]: Bits 31:12 of the physical address of the base of the EPC section.

                              EBX[19:00]: Bits 51:32 of the physical address of the base of the EPC section.
                              EBX[31:20]: Reserved.

                              ECX[03:00]: EPC section property encoding defined as follows:
                               If EAX[3:0] 0000b, then all bits of the EDX:ECX pair are enumerated as 0.
                               If EAX[3:0] 0001b, then this section has confidentiality and integrity protection.
                               All other encodings are reserved.
                              ECX[11:04]: Reserved (enumerate 0).
                              ECX[31:12]: Bits 31:12 of the size of the corresponding EPC section within the Processor Reserved
                              Memory.

                              EDX[19:00]: Bits 51:32 of the size of the corresponding EPC section within the Processor Reserved
                              Memory.
                              EDX[31:20]: Reserved.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                           Information Provided about the Processor
                Intel Processor Trace Enumeration Main Leaf (EAX = 14H, ECX = 0)
     14H                   NOTES:
                             Leaf 14H main leaf (ECX = 0).
                EAX        Bits 31 - 00: Reports the maximum sub-leaf supported in leaf 14H.
                EBX        Bit 00: If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH
                           MSR can be accessed.
                           Bit 01: If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.
                           Bit 02: If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across
                           warm reset.
                           Bit 03: If 1, indicates support of MTC timing packet and suppression of COFI-based packets.
                           Bit 04: If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and
                           IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.
                           Bit 05: If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn),
                           enabling Power Event Trace packet generation.
                           Bit 31 - 06: Reserved.
                ECX        Bit 00: If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output
                           scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.
                           Bit 01: If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the Mas-
                           kOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.
                           Bit 02: If 1, indicates support of Single-Range Output scheme.
                           Bit 03: If 1, indicates support of output to Trace Transport subsystem.
                           Bit 30 - 04: Reserved.
                           Bit 31: If 1, generated packets which contain IP payloads have LIP values, which include the CS base com-
                           ponent.
                EDX        Bits 31 - 00: Reserved.
                Intel Processor Trace Enumeration Sub-leaf (EAX = 14H, ECX = 1)
     14H        EAX        Bits 02 - 00: Number of configurable Address Ranges for filtering.
                           Bits 15 - 03: Reserved.
                           Bits 31 - 16: Bitmap of supported MTC period encodings.
                EBX        Bits 15 - 00: Bitmap of supported Cycle Threshold value encodings.
                           Bit 31 - 16: Bitmap of supported Configurable PSB frequency encodings.
                ECX        Bits 31 - 00: Reserved.
                EDX        Bits 31 - 00: Reserved.
                Time Stamp Counter and Nominal Core Crystal Clock Information Leaf
     15H                   NOTES:
                             If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.
                             EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core crystal clock frequency.
                             If ECX is 0, the nominal core crystal clock frequency is not enumerated.
                             "TSC frequency" = "core crystal clock frequency" * EBX/EAX.
                            The core crystal clock may differ from the reference clock, bus clock, or core clock frequencies.
                EAX        Bits 31 - 00: An unsigned integer which is the denominator of the TSC/"core crystal clock" ratio.
                EBX        Bits 31 - 00: An unsigned integer which is the numerator of the TSC/"core crystal clock" ratio.
                ECX        Bits 31 - 00: An unsigned integer which is the nominal frequency of the core crystal clock in Hz.
                EDX        Bits 31 - 00: Reserved = 0.





                              Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                          Information Provided about the Processor
                 Processor Frequency Information Leaf
      16H        EAX        Bits 15 - 00: Processor Base Frequency (in MHz).
                            Bits 31 - 16: Reserved =0.
                 EBX        Bits 15 - 00: Maximum Frequency (in MHz).
                            Bits 31 - 16: Reserved = 0.
                 ECX        Bits 15 - 00: Bus (Reference) Frequency (in MHz).
                            Bits 31 - 16: Reserved = 0.
                 EDX        Reserved.
                            NOTES:
                            * Data is returned from this interface in accordance with the processor's specification and does not reflect
                            actual values. Suitable use of this data includes the display of processor information in like manner to the
                            processor brand string and for determining the appropriate range to use when displaying processor
                            information e.g. frequency history graphs. The returned information should not be used for any other
                            purpose as the returned information does not accurately correlate to information / counters returned by
                            other processor interfaces.

                            While a processor may support the Processor Frequency Information leaf, fields that return a value of
                            zero are not supported.
                 System-On-Chip Vendor Attribute Enumeration Main Leaf (EAX = 17H, ECX = 0)
      17H                   NOTES:
                              Leaf 17H main leaf (ECX = 0).
                              Leaf 17H output depends on the initial value in ECX.
                              Leaf 17H sub-leaves 1 through 3 reports SOC Vendor Brand String.
                             Leaf 17H is valid if MaxSOCID_Index >= 3.
                             Leaf 17H sub-leaves 4 and above are reserved.


                 EAX        Bits 31 - 00: MaxSOCID_Index. Reports the maximum input value of supported sub-leaf in leaf 17H.
                 EBX        Bits 15 - 00: SOC Vendor ID.
                            Bit 16: IsVendorScheme. If 1, the SOC Vendor ID field is assigned via an industry standard enumeration
                            scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.
                            Bits 31 - 17: Reserved = 0.
                 ECX        Bits 31 - 00: Project ID. A unique number an SOC vendor assigns to its SOC projects.
                 EDX        Bits 31 - 00: Stepping ID. A unique number within an SOC project that an SOC vendor assigns.
                 System-On-Chip Vendor Attribute Enumeration Sub-leaf (EAX = 17H, ECX = 1..3)
      17H        EAX        Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
                 EBX        Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
                 ECX        Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
                 EDX        Bit 31 - 00: SOC Vendor Brand String. UTF-8 encoded string.
                            NOTES:
                             Leaf 17H output depends on the initial value in ECX.
                             SOC Vendor Brand String is a UTF-8 encoded string padded with trailing bytes of 00H.
                             The complete SOC Vendor Brand String is constructed by concatenating in ascending order of
                             EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                          Information Provided about the Processor
                System-On-Chip Vendor Attribute Enumeration Sub-leaves (EAX = 17H, ECX > MaxSOCID_Index)
     17H                   NOTES:
                            Leaf 17H output depends on the initial value in ECX.


                EAX        Bits 31 - 00: Reserved = 0.
                EBX        Bits 31 - 00: Reserved = 0.
                ECX        Bits 31 - 00: Reserved = 0.
                EDX        Bits 31 - 00: Reserved = 0.
                Unimplemented CPUID Leaf Functions
 40000000H                 Invalid. No existing or future CPU will return processor identification or feature information if the initial
     -                     EAX value is in the range 40000000H to 4FFFFFFFH.
 4FFFFFFFH
                Extended Function CPUID Information
 80000000H EAX             Maximum Input Value for Extended Function CPUID Information.
                EBX        Reserved.
                ECX        Reserved.
                EDX        Reserved.
 80000001H EAX             Extended Processor Signature and Feature Bits.
                EBX        Reserved.
                ECX        Bit 00: LAHF/SAHF available in 64-bit mode.
                           Bits 04 - 01: Reserved.
                           Bit 05: LZCNT.
                           Bits 07 - 06: Reserved.
                           Bit 08: PREFETCHW.
                           Bits 31 - 09: Reserved.
                EDX        Bits 10 - 00: Reserved.
                           Bit 11: SYSCALL/SYSRET available in 64-bit mode.
                           Bits 19 - 12: Reserved = 0.
                           Bit 20: Execute Disable Bit available.
                           Bits 25 - 21: Reserved = 0.
                           Bit 26: 1-GByte pages are available if 1.
                           Bit 27: RDTSCP and IA32_TSC_AUX are available if 1.
                           Bit 28: Reserved = 0.
                           Bit 29: Intel 64 Architecture available if 1.
                           Bits 31 - 30: Reserved = 0.
 80000002H EAX             Processor Brand String.
           EBX             Processor Brand String Continued.
           ECX             Processor Brand String Continued.
           EDX             Processor Brand String Continued.
 80000003H EAX             Processor Brand String Continued.
           EBX             Processor Brand String Continued.
           ECX             Processor Brand String Continued.
           EDX             Processor Brand String Continued.





                             Table 3-8. Information Returned by CPUID Instruction (Contd.)
  Initial EAX
     Value                                          Information Provided about the Processor
 80000004H EAX             Processor Brand String Continued.
           EBX             Processor Brand String Continued.
           ECX             Processor Brand String Continued.
           EDX             Processor Brand String Continued.
 80000005H EAX             Reserved = 0.
           EBX             Reserved = 0.
           ECX             Reserved = 0.
           EDX             Reserved = 0.
 80000006H EAX             Reserved = 0.
           EBX             Reserved = 0.
                 ECX       Bits 07 - 00: Cache Line size in bytes.
                           Bits 11 - 08: Reserved.
                           Bits 15 - 12: L2 Associativity field *.
                           Bits 31 - 16: Cache size in 1K units.
                 EDX       Reserved = 0.
                           NOTES:
                           * L2 associativity field encodings:
                              00H - Disabled.
                              01H - Direct mapped.
                              02H - 2-way.
                              04H - 4-way.
                              06H - 8-way.
                              08H - 16-way.
                              0FH - Fully associative.
 80000007H EAX             Reserved = 0.
           EBX             Reserved = 0.
           ECX             Reserved = 0.
           EDX             Bits 07 - 00: Reserved = 0.
                           Bit 08: Invariant TSC available if 1.
                           Bits 31 - 09: Reserved = 0.
 80000008H EAX             Linear/Physical Address size.
                           Bits 07 - 00: #Physical Address Bits*.
                           Bits 15 - 08: #Linear Address Bits.
                           Bits 31 - 16: Reserved = 0.
                 EBX       Reserved = 0.
                 ECX       Reserved = 0.
                 EDX       Reserved = 0.

                           NOTES:
                           * If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should
                             come from this field.


INPUT EAX = 0: Returns CPUID's Highest Value for Basic Processor Information and the Vendor Identification String
When CPUID executes with EAX set to 0, the processor returns the highest value the CPUID recognizes for
returning basic processor information. The value is returned in the EAX register and is processor specific.





A vendor identification string is also returned in EBX, EDX, and ECX. For Intel processors, the string is "Genuin-
eIntel" and is expressed:
    EBX <- 756e6547h (* "Genu", with G in the low eight bits of BL *)
    EDX <- 49656e69h (* "ineI", with i in the low eight bits of DL *)
    ECX <- 6c65746eh (* "ntel", with n in the low eight bits of CL *)

INPUT EAX = 80000000H: Returns CPUID's Highest Value for Extended Processor Information
When CPUID executes with EAX set to 80000000H, the processor returns the highest value the processor recog-
nizes for returning extended processor information. The value is returned in the EAX register and is processor
specific.

IA32_BIOS_SIGN_ID Returns Microcode Update Signature
For processors that support the microcode update facility, the IA32_BIOS_SIGN_ID MSR is loaded with the update
signature whenever CPUID executes. The signature is returned in the upper DWORD. For details, see Chapter 9 in
the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

INPUT EAX = 01H: Returns Model, Family, Stepping Information
When CPUID executes with EAX set to 01H, version information is returned in EAX (see Figure 3-6). For example:
model, family, and processor type for the Intel Xeon processor 5100 series is as follows:
.   Model - 1111B
.   Family - 0101B
.   Processor Type - 00B
See Table 3-9 for available processor type values. Stepping IDs are provided as needed.




                            31     28 27                20 19      16 15 14 13 12 11    8 7           4   3        0


                                           Extended        Extended                Family                 Stepping
                     EAX                                                                      Model
                                           Family ID       Model ID                  ID                      ID


                    Extended Family ID (0)
                    Extended Model ID (0)
                    Processor Type
                    Family (0FH for the Pentium 4 Processor Family)
                    Model

                           Reserved
                                                                                                              OM16525


                                 Figure 3-6. Version Information Returned by CPUID in EAX





                                                   Table 3-9. Processor Type Field
                                Type                                                      Encoding
 Original OEM Processor                                                                     00B
                  
 Intel OverDrive Processor                                                                  01B
 Dual processor (not applicable to Intel486 processors)                                     10B
 Intel reserved                                                                             11B

                                                                   NOTE
         See Chapter 19 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1,
         for information on identifying earlier IA-32 processors.


The Extended Family ID needs to be examined only when the Family ID is 0FH. Integrate the fields into a display
using the following rule:

    IF Family_ID != 0FH
         THEN DisplayFamily = Family_ID;
         ELSE DisplayFamily = Extended_Family_ID + Family_ID;
         (* Right justify and zero-extend 4-bit field. *)
    FI;
    (* Show DisplayFamily as HEX field. *)
The Extended Model ID needs to be examined only when the Family ID is 06H or 0FH. Integrate the field into a
display using the following rule:

    IF (Family_ID = 06H or Family_ID = 0FH)
         THEN DisplayModel = (Extended_Model_ID << 4) + Model_ID;
         (* Right justify and zero-extend 4-bit field; display Model_ID as HEX field.*)
         ELSE DisplayModel = Model_ID;
    FI;
    (* Show DisplayModel as HEX field. *)

INPUT EAX = 01H: Returns Additional Information in EBX
When CPUID executes with EAX set to 01H, additional information is returned to the EBX register:
.   Brand index (low byte of EBX) - this number provides an entry into a brand string table that contains brand
    strings for IA-32 processors. More information about this field is provided later in this section.
.   CLFLUSH instruction cache line size (second byte of EBX) - this number indicates the size of the cache line
    flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the
    Pentium 4 processor.
.   Local APIC ID (high byte of EBX) - this number is the 8-bit ID that is assigned to the local APIC on the
    processor during power up. This field was introduced in the Pentium 4 processor.

INPUT EAX = 01H: Returns Feature Information in ECX and EDX
When CPUID executes with EAX set to 01H, feature information is returned in ECX and EDX.
.   Figure 3-7 and Table 3-10 show encodings for ECX.
.   Figure 3-8 and Table 3-11 show encodings for EDX.
For all feature flags, a 1 indicates that the feature is supported. Use Intel to properly interpret feature flags.

                                                                   NOTE
         Software must confirm that a processor feature is present using feature flags returned by CPUID
         prior to using the feature. Software should not depend on future offerings retaining all features.





                                        31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4   3 2 1   0



                                 ECX
                                        0


                        RDRAND
                        F16C
                        AVX
                        OSXSAVE
                        XSAVE
                        AES
                        TSC-Deadline
                        POPCNT
                        MOVBE
                        x2APIC
                        SSE4_2 - SSE4.2
                        SSE4_1 - SSE4.1
                        DCA - Direct Cache Access
                        PCID - Process-context Identifiers
                        PDCM - Perf/Debug Capability MSR
                        xTPR Update Control
                        CMPXCHG16B
                        FMA - Fused Multiply Add
                        SDBG
                        CNXT-ID - L1 Context ID
                        SSSE3 - SSSE3 Extensions
                        TM2 - Thermal Monitor 2
                        EIST - Enhanced Intel SpeedStep Technology
                        SMX - Safer Mode Extensions
                        VMX - Virtual Machine Extensions
                        DS-CPL - CPL Qualified Debug Store
                        MONITOR - MONITOR/MWAIT
                        DTES64 - 64-bit DS Area
                        PCLMULQDQ - Carryless Multiplication
                        SSE3 - SSE3 Extensions
                                                                                                                          OM16524b
                          Reserved

                                 Figure 3-7. Feature Information Returned in the ECX Register


                                Table 3-10. Feature Information Returned in the ECX Register
 Bit #          Mnemonic             Description
 0              SSE3                 Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this
                                     technology.
 1              PCLMULQDQ            PCLMULQDQ. A value of 1 indicates the processor supports the PCLMULQDQ instruction.
 2              DTES64               64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.
 3              MONITOR              MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.
 4              DS-CPL               CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the
                                     Debug Store feature to allow for branch message storage qualified by CPL.
 5              VMX                  Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.
 6              SMX                  Safer Mode Extensions. A value of 1 indicates that the processor supports this technology. See
                                     Chapter 6, "Safer Mode Extensions Reference".
 7              EIST                 Enhanced Intel SpeedStep technology. A value of 1 indicates that the processor supports this
                                     technology.
 8              TM2                  Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology.
 9              SSSE3                A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A
                                     value of 0 indicates the instruction extensions are not present in the processor.



                           Table 3-10. Feature Information Returned in the ECX Register (Contd.)
  Bit #        Mnemonic           Description
  10           CNXT-ID            L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode
                                  or shared mode. A value of 0 indicates this feature is not supported. See definition of the
                                  IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details.
  11           SDBG               A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug.
  12           FMA                A value of 1 indicates the processor supports FMA extensions using YMM state.
  13           CMPXCHG16B         CMPXCHG16B Available. A value of 1 indicates that the feature is available. See the
                                  "CMPXCHG8B/CMPXCHG16B-Compare and Exchange Bytes" section in this chapter for a
                                  description.
  14           xTPR Update        xTPR Update Control. A value of 1 indicates that the processor supports changing
               Control            IA32_MISC_ENABLE[bit 23].
  15           PDCM               Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance
                                  and debug feature indication MSR IA32_PERF_CAPABILITIES.
  16           Reserved           Reserved
  17           PCID               Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that
                                  software may set CR4.PCIDE to 1.
  18           DCA                A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped
                                  device.
  19           SSE4.1             A value of 1 indicates that the processor supports SSE4.1.
  20           SSE4.2             A value of 1 indicates that the processor supports SSE4.2.
  21           x2APIC             A value of 1 indicates that the processor supports x2APIC feature.
  22           MOVBE              A value of 1 indicates that the processor supports MOVBE instruction.
  23           POPCNT             A value of 1 indicates that the processor supports the POPCNT instruction.
  24           TSC-Deadline       A value of 1 indicates that the processor's local APIC timer supports one-shot operation using a
                                  TSC deadline value.
  25           AESNI              A value of 1 indicates that the processor supports the AESNI instruction extensions.
  26           XSAVE              A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states
                                  feature, the XSETBV/XGETBV instructions, and XCR0.
  27           OSXSAVE            A value of 1 indicates that the OS has set CR4.OSXSAVE[bit 18] to enable XSETBV/XGETBV
                                  instructions to access XCR0 and to support processor extended state management using
                                  XSAVE/XRSTOR.
  28           AVX                A value of 1 indicates the processor supports the AVX instruction extensions.
  29           F16C               A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.
  30           RDRAND             A value of 1 indicates that processor supports RDRAND instruction.
  31           Not Used           Always returns 0.





                                  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1    0


                           EDX


                PBE-Pend. Brk. EN.
                TM-Therm. Monitor
                HTT-Multi-threading
                SS-Self Snoop
                SSE2-SSE2 Extensions
                SSE-SSE Extensions
                FXSR-FXSAVE/FXRSTOR
                MMX-MMX Technology
                ACPI-Thermal Monitor and Clock Ctrl
                DS-Debug Store
                CLFSH-CLFLUSH instruction
                PSN-Processor Serial Number
                PSE-36 - Page Size Extension
                PAT-Page Attribute Table
                CMOV-Conditional Move/Compare Instruction
                MCA-Machine Check Architecture
                PGE-PTE Global Bit
                MTRR-Memory Type Range Registers
                SEP-SYSENTER and SYSEXIT
                APIC-APIC on Chip
                CX8-CMPXCHG8B Inst.
                MCE-Machine Check Exception
                PAE-Physical Address Extensions
                MSR-RDMSR and WRMSR Support
                TSC-Time Stamp Counter
                PSE-Page Size Extensions
                DE-Debugging Extensions
                VME-Virtual-8086 Mode Enhancement
                FPU-x87 FPU on Chip

                     Reserved
                                                                                                                 OM16523



                          Figure 3-8. Feature Information Returned in the EDX Register





                             Table 3-11. More on Feature Information Returned in the EDX Register
 Bit #    Mnemonic         Description
    0     FPU              Floating Point Unit On-Chip. The processor contains an x87 FPU.
    1     VME              Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the
                           feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS
                           with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.
    2     DE               Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional
                           trapping of accesses to DR4 and DR5.
    3     PSE              Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the
                           feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and
                           PTEs.
    4     TSC              Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.
    5     MSR              Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are
                           supported. Some of the MSRs are implementation dependent.
    6     PAE              Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table
                           entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of
                           4 Mbyte pages if PAE bit is 1.
    7     MCE              Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the
                           feature. This feature does not define the model-specific implementations of machine-check error logging,
                           reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor
                           version to do model specific processing of the exception, or test for the presence of the Machine Check feature.
    8     CX8              CMPXCHG8B Instruction. The compare-and-exchange 8 bytes (64 bits) instruction is supported (implicitly
                           locked and atomic).
    9     APIC             APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to
                           memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some
                           processors permit the APIC to be relocated).
   10     Reserved         Reserved
   11     SEP              SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.
   12     MTRR             Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe
                           what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are
                           supported.
   13     PGE              Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries
                           that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.
   14     MCA              Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine
                           errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting
                           MSRs are supported.
   15     CMOV             Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is
                           present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported
   16     PAT              Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range
                           Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear
                           address on a 4KB granularity.
   17     PSE-36           36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with
                           32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in
                           bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to
                           40 bits in size.
   18     PSN              Processor Serial Number. The processor supports the 96-bit processor identification number feature and the
                           feature is enabled.
   19     CLFSH            CLFLUSH Instruction. CLFLUSH Instruction is supported.
   20     Reserved         Reserved



                    Table 3-11. More on Feature Information Returned in the EDX Register (Contd.)
 Bit #   Mnemonic    Description
    21   DS          Debug Store. The processor supports the ability to write debug information into a memory resident buffer.
                     This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities (see
                     Chapter 23, "Introduction to Virtual-Machine Extensions," in the Intel 64 and IA-32 Architectures Software
                     Developer's Manual, Volume 3C).
    22   ACPI        Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that
                     allow processor temperature to be monitored and processor performance to be modulated in predefined duty
                     cycles under software control.
    23   MMX         Intel MMX Technology. The processor supports the Intel MMX technology.
    24   FXSR        FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and
                     restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an
                     operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.
    25   SSE         SSE. The processor supports the SSE extensions.
    26   SSE2        SSE2. The processor supports the SSE2 extensions.
    27   SS          Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its
                     own cache structure for transactions issued to the bus.
    28   HTT         Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in
                     the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the
                     value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is
                     valid for the package.
    29   TM          Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).
    30   Reserved    Reserved
    31   PBE         Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the
                     stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the
                     processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the
                     IA32_MISC_ENABLE MSR enables this capability.



INPUT EAX = 02H: TLB/Cache/Prefetch Information Returned in EAX, EBX, ECX, EDX
When CPUID executes with EAX set to 02H, the processor returns information about the processor's internal TLBs,
cache and prefetch hardware in the EAX, EBX, ECX, and EDX registers. The information is reported in encoded form
and fall into the following categories:
.    The least-significant byte in register EAX (register AL) will always return 01H. Software should ignore this value
     and not interpret it as an informational descriptor.
.    The most significant bit (bit 31) of each register indicates whether the register contains valid information (set
     to 0) or is reserved (set to 1).
.    If a register contains valid information, the information is contained in 1 byte descriptors. There are four types
     of encoding values for the byte descriptor, the encoding type is noted in the second column of Table 3-12. Table
     3-12 lists the encoding of these descriptors. Note that the order of descriptors in the EAX, EBX, ECX, and EDX
     registers is not defined; that is, specific bytes are not designated to contain descriptors for specific cache,
     prefetch, or TLB types. The descriptors may appear in any order. Note also a processor may report a general
     descriptor type (FFH) and not report any byte descriptor of "cache type" via CPUID leaf 2.





                                      Table 3-12. Encoding of CPUID Leaf 2 Descriptors
  Value      Type                                                           Description
  00H       General    Null descriptor, this byte contains no information
  01H         TLB      Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries
  02H         TLB      Instruction TLB: 4 MByte pages, fully associative, 2 entries
  03H         TLB      Data TLB: 4 KByte pages, 4-way set associative, 64 entries
  04H         TLB      Data TLB: 4 MByte pages, 4-way set associative, 8 entries
  05H         TLB      Data TLB1: 4 MByte pages, 4-way set associative, 32 entries
  06H        Cache     1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size
  08H        Cache     1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size
  09H        Cache     1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size
  0AH        Cache     1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size
  0BH         TLB      Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries
  0CH        Cache     1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size
  0DH        Cache     1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size
  0EH        Cache     1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size
  1DH        Cache     2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size
  21H        Cache     2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size
  22H        Cache     3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector
  23H        Cache     3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
  24H        Cache     2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size
  25H        Cache     3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
  29H        Cache     3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector
  2CH        Cache     1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size
  30H        Cache     1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size
  40H        Cache     No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache
  41H        Cache     2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size
  42H        Cache     2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size
  43H        Cache     2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size
  44H        Cache     2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size
  45H        Cache     2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size
  46H        Cache     3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size
  47H        Cache     3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size
  48H        Cache     2nd-level cache: 3MByte, 12-way set associative, 64 byte line size
  49H        Cache     3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model
                       06H);
                       2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size
  4AH        Cache     3rd-level cache: 6MByte, 12-way set associative, 64 byte line size
  4BH        Cache     3rd-level cache: 8MByte, 16-way set associative, 64 byte line size
  4CH        Cache     3rd-level cache: 12MByte, 12-way set associative, 64 byte line size
  4DH        Cache     3rd-level cache: 16MByte, 16-way set associative, 64 byte line size
  4EH        Cache     2nd-level cache: 6MByte, 24-way set associative, 64 byte line size
  4FH         TLB      Instruction TLB: 4 KByte pages, 32 entries




                              Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
 Value      Type                                                         Description
  50H       TLB     Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries
  51H       TLB     Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries
  52H       TLB     Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries
  55H       TLB     Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries
  56H       TLB     Data TLB0: 4 MByte pages, 4-way set associative, 16 entries
  57H       TLB     Data TLB0: 4 KByte pages, 4-way associative, 16 entries
  59H       TLB     Data TLB0: 4 KByte pages, fully associative, 16 entries
  5AH       TLB     Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries
  5BH       TLB     Data TLB: 4 KByte and 4 MByte pages, 64 entries
  5CH       TLB     Data TLB: 4 KByte and 4 MByte pages,128 entries
  5DH       TLB     Data TLB: 4 KByte and 4 MByte pages,256 entries
  60H       Cache   1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size
  61H       TLB     Instruction TLB: 4 KByte pages, fully associative, 48 entries
  63H       TLB     Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte
                    pages, 4-way set associative, 4 entries
  64H       TLB     Data TLB: 4 KByte pages, 4-way set associative, 512 entries
  66H       Cache   1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size
  67H       Cache   1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size
  68H       Cache   1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size
  6AH       Cache   uTLB: 4 KByte pages, 8-way set associative, 64 entries
  6BH       Cache   DTLB: 4 KByte pages, 8-way set associative, 256 entries
  6CH       Cache   DTLB: 2M/4M pages, 8-way set associative, 128 entries
  6DH       Cache   DTLB: 1 GByte pages, fully associative, 16 entries
  70H       Cache   Trace cache: 12 K-muop, 8-way set associative
  71H       Cache   Trace cache: 16 K-muop, 8-way set associative
  72H       Cache   Trace cache: 32 K-muop, 8-way set associative
  76H       TLB     Instruction TLB: 2M/4M pages, fully associative, 8 entries
  78H       Cache   2nd-level cache: 1 MByte, 4-way set associative, 64byte line size
  79H       Cache   2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
  7AH       Cache   2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
  7BH       Cache   2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector
  7CH       Cache   2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector
  7DH       Cache   2nd-level cache: 2 MByte, 8-way set associative, 64byte line size
  7FH       Cache   2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size
  80H       Cache   2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size
  82H       Cache   2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size
  83H       Cache   2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size
  84H       Cache   2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size
  85H       Cache   2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size
  86H       Cache   2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size
  87H       Cache   2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size




                                 Table 3-12. Encoding of CPUID Leaf 2 Descriptors (Contd.)
  Value      Type                                                        Description
  A0H        DTLB      DTLB: 4k pages, fully associative, 32 entries
  B0H         TLB      Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries
  B1H         TLB      Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries
  B2H         TLB      Instruction TLB: 4KByte pages, 4-way set associative, 64 entries
  B3H         TLB      Data TLB: 4 KByte pages, 4-way set associative, 128 entries
  B4H         TLB      Data TLB1: 4 KByte pages, 4-way associative, 256 entries
  B5H         TLB      Instruction TLB: 4KByte pages, 8-way set associative, 64 entries
  B6H         TLB      Instruction TLB: 4KByte pages, 8-way set associative, 128 entries
  BAH         TLB      Data TLB1: 4 KByte pages, 4-way associative, 64 entries
  C0H         TLB      Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries
  C1H        STLB      Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries
  C2H        DTLB      DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries
  C3H        STLB      Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way,
                       16 entries.
  C4H        DTLB      DTLB: 2M/4M Byte pages, 4-way associative, 32 entries
  CAH        STLB      Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries
  D0H        Cache     3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size
  D1H        Cache     3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size
  D2H        Cache     3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size
  D6H        Cache     3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size
  D7H        Cache     3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size
  D8H        Cache     3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size
  DCH        Cache     3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size
  DDH        Cache     3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size
  DEH        Cache     3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size
  E2H        Cache     3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size
  E3H        Cache     3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size
  E4H        Cache     3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size
  EAH        Cache     3rd-level cache: 12MByte, 24-way set associative, 64 byte line size
  EBH        Cache     3rd-level cache: 18MByte, 24-way set associative, 64 byte line size
  ECH        Cache     3rd-level cache: 24MByte, 24-way set associative, 64 byte line size
  F0H      Prefetch    64-Byte prefetching
  F1H      Prefetch    128-Byte prefetching
  FFH       General    CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters


Example 3-1. Example of Cache and TLB Interpretation
The first member of the family of Pentium 4 processors returns the following information about caches and TLBs
when the CPUID executes with an input value of 2:

   EAX       66 5B 50 01H
   EBX       0H
   ECX       0H
   EDX       00 7A 70 00H




Which means:
.   The least-significant byte (byte 0) of register EAX is set to 01H. This value should be ignored.
.   The most-significant bit of all four registers (EAX, EBX, ECX, and EDX) is set to 0, indicating that each register
    contains valid 1-byte descriptors.
.   Bytes 1, 2, and 3 of register EAX indicate that the processor has:
    - 50H - a 64-entry instruction TLB, for mapping 4-KByte and 2-MByte or 4-MByte pages.
    - 5BH - a 64-entry data TLB, for mapping 4-KByte and 4-MByte pages.
    - 66H - an 8-KByte 1st level data cache, 4-way set associative, with a 64-Byte cache line size.
.   The descriptors in registers EBX and ECX are valid, but contain NULL descriptors.
.   Bytes 0, 1, 2, and 3 of register EDX indicate that the processor has:
    - 00H - NULL descriptor.
    - 70H - Trace cache: 12 K-muop, 8-way set associative.
    - 7AH - a 256-KByte 2nd level cache, 8-way set associative, with a sectored, 64-byte cache line size.
    - 00H - NULL descriptor.

INPUT EAX = 04H: Returns Deterministic Cache Parameters for Each Level
When CPUID executes with EAX set to 04H and ECX contains an index value, the processor returns encoded data
that describe a set of deterministic cache parameters (for the cache level associated with the input in ECX). Valid
index values start from 0.
Software can enumerate the deterministic cache parameters for each level of the cache hierarchy starting with an
index value of 0, until the parameters report the value associated with the cache type field is 0. The architecturally
defined fields reported by deterministic cache parameters are documented in Table 3-8.
This Cache Size in Bytes
= (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1)
= (EBX[31:22] + 1) * (EBX[21:12] + 1) * (EBX[11:0] + 1) * (ECX + 1)


The CPUID leaf 04H also reports data that can be used to derive the topology of processor cores in a physical
package. This information is constant for all valid index values. Software can query the raw data reported by
executing CPUID with EAX=04H and ECX=0 and use it as part of the topology enumeration algorithm described in
Chapter 8, "Multiple-Processor Management," in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.

INPUT EAX = 05H: Returns MONITOR and MWAIT Features
When CPUID executes with EAX set to 05H, the processor returns information about features available to
MONITOR/MWAIT instructions. The MONITOR instruction is used for address-range monitoring in conjunction with
MWAIT instruction. The MWAIT instruction optionally provides additional extensions for advanced power manage-
ment. See Table 3-8.

INPUT EAX = 06H: Returns Thermal and Power Management Features
When CPUID executes with EAX set to 06H, the processor returns information about thermal and power manage-
ment features. See Table 3-8.

INPUT EAX = 07H: Returns Structured Extended Feature Enumeration Information
When CPUID executes with EAX set to 07H and ECX = 0, the processor returns information about the maximum
input value for sub-leaves that contain extended feature flags. See Table 3-8.
When CPUID executes with EAX set to 07H and the input value of ECX is invalid (see leaf 07H entry in Table 3-8),
the processor returns 0 in EAX/EBX/ECX/EDX. In subleaf 0, EAX returns the maximum input value of the highest
leaf 7 sub-leaf, and EBX, ECX & EDX contain information of extended feature flags.




INPUT EAX = 09H: Returns Direct Cache Access Information
When CPUID executes with EAX set to 09H, the processor returns information about Direct Cache Access capabili-
ties. See Table 3-8.

INPUT EAX = 0AH: Returns Architectural Performance Monitoring Features
When CPUID executes with EAX set to 0AH, the processor returns information about support for architectural
performance monitoring capabilities. Architectural performance monitoring is supported if the version ID (see
Table 3-8) is greater than Pn 0. See Table 3-8.
For each version of architectural performance monitoring capability, software must enumerate this leaf to discover
the programming facilities and the architectural performance events available in the processor. The details are
described in Chapter 23, "Introduction to Virtual-Machine Extensions," in the Intel 64 and IA-32 Architectures
Software Developer's Manual, Volume 3C.

INPUT EAX = 0BH: Returns Extended Topology Information
When CPUID executes with EAX set to 0BH, the processor returns information about extended topology enumera-
tion data. Software must detect the presence of CPUID leaf 0BH by verifying (a) the highest leaf index supported
by CPUID is >= 0BH, and (b) CPUID.0BH:EBX[15:0] reports a non-zero value. See Table 3-8.

INPUT EAX = 0DH: Returns Processor Extended States Enumeration Information
When CPUID executes with EAX set to 0DH and ECX = 0, the processor returns information about the bit-vector
representation of all processor state extensions that are supported in the processor and storage size requirements
of the XSAVE/XRSTOR area. See Table 3-8.
When CPUID executes with EAX set to 0DH and ECX = n (n > 1, and is a valid sub-leaf index), the processor returns
information about the size and offset of each processor extended state save area within the XSAVE/XRSTOR area.
See Table 3-8. Software can use the forward-extendable technique depicted below to query the valid sub-leaves
and obtain size and offset information for each processor extended state save area:

For i = 2 to 62 // sub-leaf 1 is reserved
   IF (CPUID.(EAX=0DH, ECX=0):VECTOR[i] = 1 ) // VECTOR is the 64-bit value of EDX:EAX
         Execute CPUID.(EAX=0DH, ECX = i) to examine size and offset for sub-leaf i;
   FI;

INPUT EAX = 0FH: Returns Intel Resource Director Technology (Intel RDT) Monitoring Enumeration Information
When CPUID executes with EAX set to 0FH and ECX = 0, the processor returns information about the bit-vector
representation of QoS monitoring resource types that are supported in the processor and maximum range of RMID
values the processor can use to monitor of any supported resource types. Each bit, starting from bit 1, corresponds
to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or ResID) that soft-
ware must use to query QoS monitoring capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 0FH and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-
mation software can use to program IA32_PQR_ASSOC, IA32_QM_EVTSEL MSRs before reading QoS data from the
IA32_QM_CTR MSR.

INPUT EAX = 10H: Returns Intel Resource Director Technology (Intel RDT) Allocation Enumeration Information
When CPUID executes with EAX set to 10H and ECX = 0, the processor returns information about the bit-vector
representation of QoS Enforcement resource types that are supported in the processor. Each bit, starting from bit
1, corresponds to a specific resource type if the bit is set. The bit position corresponds to the sub-leaf index (or
ResID) that software must use to query QoS enforcement capability available for that type. See Table 3-8.
When CPUID executes with EAX set to 10H and ECX = n (n >= 1, and is a valid ResID), the processor returns infor-
mation about available classes of service and range of QoS mask MSRs that software can use to configure each
class of services using capability bit masks in the QoS Mask registers, IA32_resourceType_Mask_n.





INPUT EAX = 12H: Returns Intel SGX Enumeration Information
When CPUID executes with EAX set to 12H and ECX = 0H, the processor returns information about Intel SGX capa-
bilities. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = 1H, the processor returns information about Intel SGX attri-
butes. See Table 3-8.
When CPUID executes with EAX set to 12H and ECX = n (n > 1), the processor returns information about Intel SGX
Enclave Page Cache. See Table 3-8.

INPUT EAX = 14H: Returns Intel Processor Trace Enumeration Information
When CPUID executes with EAX set to 14H and ECX = 0H, the processor returns information about Intel Processor
Trace extensions. See Table 3-8.
When CPUID executes with EAX set to 14H and ECX = n (n > 0 and less than the number of non-zero bits in
CPUID.(EAX=14H, ECX= 0H).EAX), the processor returns information about packet generation in Intel Processor
Trace. See Table 3-8.

INPUT EAX = 15H: Returns Time Stamp Counter and Nominal Core Crystal Clock Information
When CPUID executes with EAX set to 15H and ECX = 0H, the processor returns information about Time Stamp
Counter and Core Crystal Clock. See Table 3-8.

INPUT EAX = 16H: Returns Processor Frequency Information
When CPUID executes with EAX set to 16H, the processor returns information about Processor Frequency Informa-
tion. See Table 3-8.

INPUT EAX = 17H: Returns System-On-Chip Information
When CPUID executes with EAX set to 17H, the processor returns information about the System-On-Chip Vendor
Attribute Enumeration. See Table 3-8.

METHODS FOR RETURNING BRANDING INFORMATION
Use the following techniques to access branding information:
1. Processor brand string method.
2. Processor brand index; this method uses a software supplied brand string table.
These two methods are discussed in the following sections. For methods that are available in early processors, see
Section: "Identification of Earlier IA-32 Processors" in Chapter 19 of the Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1.

The Processor Brand String Method
Figure 3-9 describes the algorithm used for detection of the brand string. Processor brand identification software
should execute this algorithm on all Intel 64 and IA-32 processors.
This method (introduced with Pentium 4 processors) returns an ASCII brand identification string and the Processor
Base frequency of the processor to the EAX, EBX, ECX, and EDX registers.





                                Input: EAX=
                                0x80000000

                             CPUID


                                                          False          Processor Brand
                           IF (EAX & 0x80000000)                            String Not
                                                                            Supported


                              CPUID
                                       True >=
                            Function
                                       Extended
                           Supported

                            EAX Return Value =
                           Max. Extended CPUID
                              Function Index




                                                          True           Processor Brand
                            IF (EAX Return Value
                               >= 0x80000004)                             String Supported


                                                                                        OM15194



                           Figure 3-9. Determination of Support for the Processor Brand String


How Brand Strings Work
To use the brand string method, execute CPUID with EAX input of 8000002H through 80000004H. For each input
value, CPUID returns 16 ASCII characters using EAX, EBX, ECX, and EDX. The returned string will be NULL-termi-
nated.





Table 3-13 shows the brand string that is returned by the first processor in the Pentium 4 processor family.

                      Table 3-13. Processor Brand String Returned with Pentium 4 Processor
         EAX Input Value                               Return Values                                 ASCII Equivalent
 80000002H                         EAX = 20202020H                                     "   "
                                   EBX = 20202020H                                     " "
                                   ECX = 20202020H                                     " "
                                   EDX = 6E492020H                                     "nI "
 80000003H                         EAX = 286C6574H                                     "(let"
                                   EBX = 50202952H                                     "P )R"
                                   ECX = 69746E65H                                     "itne"
                                   EDX = 52286D75H                                     "R(mu"
 80000004H                         EAX = 20342029H                                     " 4 )"
                                   EBX = 20555043H                                     " UPC"
                                   ECX = 30303531H                                     "0051"
                                   EDX = 007A484DH                                     "\0zHM"



Extracting the Processor Frequency from Brand Strings
Figure 3-10 provides an algorithm which software can use to extract the Processor Base frequency from the
processor brand string.


                              Scan "Brand String" in
                               Reverse Byte Order

                              "zHM", or
                                           Match
                              "zHG", or
                                           Substring
                                 "zHT"


                                                              False
                              IF Substring Matched                         Report Error




                       Determine "Freq"    True                If "zHM"
                        and "Multiplier"                                   Multiplier = 1 x 106

                                                               If "zHG"
                                                                           Multiplier = 1 x 109
                              Determine "Multiplier"           If "zHT"
                                                                           Multiplier = 1 x 1012


                                                          Scan Digits
                                                          Until Blank        Reverse Digits
                                 Determine "Freq"
                                                        In Reverse Order    To Decimal Value




                                 Processor Base
                                  Frequency =
                                                                             "Freq" = X.YZ if
                               "Freq" x "Multiplier"
                                                                             Digits = "ZY.X"

                                                                                                   OM15195


                              Figure 3-10. Algorithm for Extracting Processor Frequency




The Processor Brand Index Method
The brand index method (introduced with Pentium III Xeon processors) provides an entry point into a brand
identification table that is maintained in memory by system software and is accessible from system- and user-level
code. In this table, each brand index is associate with an ASCII brand identification string that identifies the official
Intel family and model number of a processor.
When CPUID executes with EAX set to 1, the processor returns a brand index to the low byte in EBX. Software can
then use this index to locate the brand identification string for the processor in the brand identification table. The
first entry (brand index 0) in this table is reserved, allowing for backward compatibility with processors that do not
support the brand identification feature. Starting with processor signature family ID = 0FH, model = 03H, brand
index method is no longer supported. Use brand string method instead.
Table 3-14 shows brand indices that have identification strings associated with them.
                  Table 3-14. Mapping of Brand Indices; and Intel 64 and IA-32 Processor Brand Strings
    Brand Index                                                        Brand String
        00H           This processor does not support the brand identification feature
        01H           Intel(R) Celeron(R) processor1
        02H           Intel(R) Pentium(R) III processor1
        03H           Intel(R) Pentium(R) III Xeon(R) processor; If processor signature = 000006B1h, then Intel(R) Celeron(R)
                      processor
        04H           Intel(R) Pentium(R) III processor
        06H           Mobile Intel(R) Pentium(R) III processor-M
        07H           Mobile Intel(R) Celeron(R) processor1
        08H           Intel(R) Pentium(R) 4 processor
        09H           Intel(R) Pentium(R) 4 processor
        0AH           Intel(R) Celeron(R) processor1
        0BH           Intel(R) Xeon(R) processor; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor MP
        0CH           Intel(R) Xeon(R) processor MP
        0EH           Mobile Intel(R) Pentium(R) 4 processor-M; If processor signature = 00000F13h, then Intel(R) Xeon(R) processor
        0FH           Mobile Intel(R) Celeron(R) processor1
        11H           Mobile Genuine Intel(R) processor
        12H           Intel(R) Celeron(R) M processor
        13H           Mobile Intel(R) Celeron(R) processor1
        14H           Intel(R) Celeron(R) processor
        15H           Mobile Genuine Intel(R) processor
        16H           Intel(R) Pentium(R) M processor
        17H           Mobile Intel(R) Celeron(R) processor1
    18H - 0FFH        RESERVED
 NOTES:
 1. Indicates versions of these processors that were introduced after the Pentium III

IA-32 Architecture Compatibility
CPUID is not supported in early models of the Intel486 processor or in any IA-32 processor earlier than the
Intel486 processor.





Operation
IA32_BIOS_SIGN_ID MSR <- Update with installed microcode revision number;

CASE (EAX) OF
   EAX = 0:
       EAX <- Highest basic function input value understood by CPUID;
       EBX <- Vendor identification string;
       EDX <- Vendor identification string;
       ECX <- Vendor identification string;
   BREAK;
   EAX = 1H:
       EAX[3:0] <- Stepping ID;
       EAX[7:4] <- Model;
       EAX[11:8] <- Family;
       EAX[13:12] <- Processor type;
       EAX[15:14] <- Reserved;
       EAX[19:16] <- Extended Model;
       EAX[27:20] <- Extended Family;
       EAX[31:28] <- Reserved;
       EBX[7:0] <- Brand Index; (* Reserved if the value is zero. *)
       EBX[15:8] <- CLFLUSH Line Size;
       EBX[16:23] <- Reserved; (* Number of threads enabled = 2 if MT enable fuse set. *)
       EBX[24:31] <- Initial APIC ID;
       ECX <- Feature flags; (* See Figure 3-7. *)
       EDX <- Feature flags; (* See Figure 3-8. *)
   BREAK;
   EAX = 2H:
       EAX <- Cache and TLB information;
       EBX <- Cache and TLB information;
       ECX <- Cache and TLB information;
       EDX <- Cache and TLB information;
   BREAK;
   EAX = 3H:
       EAX <- Reserved;
       EBX <- Reserved;
       ECX <- ProcessorSerialNumber[31:0];
       (* Pentium III processors only, otherwise reserved. *)
       EDX <- ProcessorSerialNumber[63:32];
       (* Pentium III processors only, otherwise reserved. *
   BREAK
   EAX = 4H:
       EAX <- Deterministic Cache Parameters Leaf; (* See Table 3-8. *)
       EBX <- Deterministic Cache Parameters Leaf;
       ECX <- Deterministic Cache Parameters Leaf;
       EDX <- Deterministic Cache Parameters Leaf;
   BREAK;
   EAX = 5H:
       EAX <- MONITOR/MWAIT Leaf; (* See Table 3-8. *)
       EBX <- MONITOR/MWAIT Leaf;
       ECX <- MONITOR/MWAIT Leaf;
       EDX <- MONITOR/MWAIT Leaf;
   BREAK;





   EAX = 6H:
       EAX <- Thermal and Power Management Leaf; (* See Table 3-8. *)
       EBX <- Thermal and Power Management Leaf;
       ECX <- Thermal and Power Management Leaf;
       EDX <- Thermal and Power Management Leaf;
   BREAK;
   EAX = 7H:
       EAX <- Structured Extended Feature Flags Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Structured Extended Feature Flags Enumeration Leaf;
       ECX <- Structured Extended Feature Flags Enumeration Leaf;
       EDX <- Structured Extended Feature Flags Enumeration Leaf;
   BREAK;
   EAX = 8H:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Reserved = 0;
       EDX <- Reserved = 0;
   BREAK;
   EAX = 9H:
       EAX <- Direct Cache Access Information Leaf; (* See Table 3-8. *)
       EBX <- Direct Cache Access Information Leaf;
       ECX <- Direct Cache Access Information Leaf;
       EDX <- Direct Cache Access Information Leaf;
   BREAK;
   EAX = AH:
       EAX <- Architectural Performance Monitoring Leaf; (* See Table 3-8. *)
       EBX <- Architectural Performance Monitoring Leaf;
       ECX <- Architectural Performance Monitoring Leaf;
       EDX <- Architectural Performance Monitoring Leaf;
       BREAK
   EAX = BH:
       EAX <- Extended Topology Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Extended Topology Enumeration Leaf;
       ECX <- Extended Topology Enumeration Leaf;
       EDX <- Extended Topology Enumeration Leaf;
   BREAK;
   EAX = CH:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Reserved = 0;
       EDX <- Reserved = 0;
   BREAK;
   EAX = DH:
       EAX <- Processor Extended State Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Processor Extended State Enumeration Leaf;
       ECX <- Processor Extended State Enumeration Leaf;
       EDX <- Processor Extended State Enumeration Leaf;
   BREAK;
   EAX = EH:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Reserved = 0;
       EDX <- Reserved = 0;
   BREAK;



   EAX = FH:
       EAX <- Intel Resource Director Technology Monitoring Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Intel Resource Director Technology Monitoring Enumeration Leaf;
       ECX <- Intel Resource Director Technology Monitoring Enumeration Leaf;
       EDX <- Intel Resource Director Technology Monitoring Enumeration Leaf;
   BREAK;
   EAX = 10H:
       EAX <- Intel Resource Director Technology Allocation Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Intel Resource Director Technology Allocation Enumeration Leaf;
       ECX <- Intel Resource Director Technology Allocation Enumeration Leaf;
       EDX <- Intel Resource Director Technology Allocation Enumeration Leaf;
   BREAK;
       EAX = 12H:
       EAX <- Intel SGX Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Intel SGX Enumeration Leaf;
       ECX <- Intel SGX Enumeration Leaf;
       EDX <- Intel SGX Enumeration Leaf;
   BREAK;
   EAX = 14H:
       EAX <- Intel Processor Trace Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Intel Processor Trace Enumeration Leaf;
       ECX <- Intel Processor Trace Enumeration Leaf;
       EDX <- Intel Processor Trace Enumeration Leaf;
   BREAK;
   EAX = 15H:
       EAX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf; (* See Table 3-8. *)
       EBX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
       ECX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
       EDX <- Time Stamp Counter and Nominal Core Crystal Clock Information Leaf;
   BREAK;
   EAX = 16H:
       EAX <- Processor Frequency Information Enumeration Leaf; (* See Table 3-8. *)
       EBX <- Processor Frequency Information Enumeration Leaf;
       ECX <- Processor Frequency Information Enumeration Leaf;
       EDX <- Processor Frequency Information Enumeration Leaf;
   BREAK;
   EAX = 17H:
       EAX <- System-On-Chip Vendor Attribute Enumeration Leaf; (* See Table 3-8. *)
       EBX <- System-On-Chip Vendor Attribute Enumeration Leaf;
       ECX <- System-On-Chip Vendor Attribute Enumeration Leaf;
       EDX <- System-On-Chip Vendor Attribute Enumeration Leaf;
   BREAK;
   EAX = 80000000H:
       EAX <- Highest extended function input value understood by CPUID;
       EBX <- Reserved;
       ECX <- Reserved;
       EDX <- Reserved;
   BREAK;
   EAX = 80000001H:
       EAX <- Reserved;
       EBX <- Reserved;
       ECX <- Extended Feature Bits (* See Table 3-8.*);
       EDX <- Extended Feature Bits (* See Table 3-8. *);
   BREAK;



   EAX = 80000002H:
       EAX <- Processor Brand String;
       EBX <- Processor Brand String, continued;
       ECX <- Processor Brand String, continued;
       EDX <- Processor Brand String, continued;
   BREAK;
   EAX = 80000003H:
       EAX <- Processor Brand String, continued;
       EBX <- Processor Brand String, continued;
       ECX <- Processor Brand String, continued;
       EDX <- Processor Brand String, continued;
   BREAK;
   EAX = 80000004H:
       EAX <- Processor Brand String, continued;
       EBX <- Processor Brand String, continued;
       ECX <- Processor Brand String, continued;
       EDX <- Processor Brand String, continued;
   BREAK;
   EAX = 80000005H:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Reserved = 0;
       EDX <- Reserved = 0;
   BREAK;
   EAX = 80000006H:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Cache information;
       EDX <- Reserved = 0;
   BREAK;
   EAX = 80000007H:
       EAX <- Reserved = 0;
       EBX <- Reserved = 0;
       ECX <- Reserved = 0;
       EDX <- Reserved = Misc Feature Flags;
   BREAK;
   EAX = 80000008H:
       EAX <- Reserved = Physical Address Size Information;
       EBX <- Reserved = Virtual Address Size Information;
       ECX <- Reserved = 0;
       EDX <- Reserved = 0;
   BREAK;
   EAX >= 40000000H and EAX <= 4FFFFFFFH:
   DEFAULT: (* EAX = Value outside of recognized range for CPUID. *)
       (* If the highest basic information leaf data depend on ECX input value, ECX is honored.*)
       EAX <- Reserved; (* Information returned for highest basic information leaf. *)
       EBX <- Reserved; (* Information returned for highest basic information leaf. *)
       ECX <- Reserved; (* Information returned for highest basic information leaf. *)
       EDX <- Reserved; (* Information returned for highest basic information leaf. *)
   BREAK;
ESAC;

Flags Affected
None.



Exceptions (All Operating Modes)
#UD                 If the LOCK prefix is used.
                    In earlier IA-32 processors that do not support the CPUID instruction, execution of the instruc-
                    tion results in an invalid opcode (#UD) exception being generated.






platform: x86_64
mnem: CRC32
description:
CRC32 - Accumulate CRC32 Value
Opcode/                                                 Op/     64-Bit     Compat/ Description
Instruction                                             En      Mode       Leg Mode
F2 0F 38 F0 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m8.
CRC32 r32, r/m8
F2 REX 0F 38 F0 /r                                      RM      Valid      N.E.         Accumulate CRC32 on r/m8.
CRC32 r32, r/m8*
F2 0F 38 F1 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m16.
CRC32 r32, r/m16
F2 0F 38 F1 /r                                          RM      Valid      Valid        Accumulate CRC32 on r/m32.
CRC32 r32, r/m32
F2 REX.W 0F 38 F0 /r                                    RM      Valid      N.E.         Accumulate CRC32 on r/m8.
CRC32 r64, r/m8
F2 REX.W 0F 38 F1 /r                                    RM      Valid      N.E.         Accumulate CRC32 on r/m64.
CRC32 r64, r/m64
NOTES:
*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                 Instruction Operand Encoding
  Op/En              Operand 1                      Operand 2                      Operand 3                      Operand 4
    RM            ModRM:reg (r, w)                ModRM:r/m (r)                       NA                             NA

Description
Starting with an initial value in the first operand (destination operand), accumulates a CRC32 (polynomial
11EDC6F41H) value for the second operand (source operand) and stores the result in the destination operand. The
source operand can be a register or a memory location. The destination operand must be an r32 or r64 register. If
the destination is an r64 register, then the 32-bit result is stored in the least significant double word and
00000000H is stored in the most significant double word of the r64 register.
The initial value supplied in the destination operand is a double word integer stored in the r32 register or the least
significant double word of the r64 register. To incrementally accumulate a CRC32 value, software retains the result
of the previous CRC32 operation in the destination operand, then executes the CRC32 instruction again with new
input data in the source operand. Data contained in the source operand is processed in reflected bit order. This
means that the most significant bit of the source operand is treated as the least significant bit of the quotient, and
so on, for all the bits of the source operand. Likewise, the result of the CRC operation is stored in the destination
operand in reflected bit order. This means that the most significant bit of the resulting CRC (bit 31) is stored in the
least significant bit of the destination operand (bit 0), and so on, for all the bits of the CRC.

Operation

Notes:
   BIT_REFLECT64: DST[63-0] = SRC[0-63]
   BIT_REFLECT32: DST[31-0] = SRC[0-31]
   BIT_REFLECT16: DST[15-0] = SRC[0-15]
   BIT_REFLECT8: DST[7-0] = SRC[0-7]
   MOD2: Remainder from Polynomial division modulus 2





CRC32 instruction for 64-bit source operand and 64-bit destination operand:

   TEMP1[63-0] <- BIT_REFLECT64 (SRC[63-0])
   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])
   TEMP3[95-0] <- TEMP1[63-0] << 32
   TEMP4[95-0] <- TEMP2[31-0] << 64
   TEMP5[95-0] <- TEMP3[95-0] XOR TEMP4[95-0]
   TEMP6[31-0] <- TEMP5[95-0] MOD2 11EDC6F41H
   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])
   DEST[63-32] <- 00000000H
CRC32 instruction for 32-bit source operand and 32-bit destination operand:

   TEMP1[31-0] <- BIT_REFLECT32 (SRC[31-0])
   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])
   TEMP3[63-0] <- TEMP1[31-0] << 32
   TEMP4[63-0] <- TEMP2[31-0] << 32
   TEMP5[63-0] <- TEMP3[63-0] XOR TEMP4[63-0]
   TEMP6[31-0] <- TEMP5[63-0] MOD2 11EDC6F41H
   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 16-bit source operand and 32-bit destination operand:

   TEMP1[15-0] <- BIT_REFLECT16 (SRC[15-0])
   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])
   TEMP3[47-0] <- TEMP1[15-0] << 32
   TEMP4[47-0] <- TEMP2[31-0] << 16
   TEMP5[47-0] <- TEMP3[47-0] XOR TEMP4[47-0]
   TEMP6[31-0] <- TEMP5[47-0] MOD2 11EDC6F41H
   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])
CRC32 instruction for 8-bit source operand and 64-bit destination operand:

   TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])
   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])
   TEMP3[39-0] <- TEMP1[7-0] << 32
   TEMP4[39-0] <- TEMP2[31-0] << 8
   TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]
   TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H
   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])
   DEST[63-32] <- 00000000H
CRC32 instruction for 8-bit source operand and 32-bit destination operand:

   TEMP1[7-0] <- BIT_REFLECT8(SRC[7-0])
   TEMP2[31-0] <- BIT_REFLECT32 (DEST[31-0])
   TEMP3[39-0] <- TEMP1[7-0] << 32
   TEMP4[39-0] <- TEMP2[31-0] << 8
   TEMP5[39-0] <- TEMP3[39-0] XOR TEMP4[39-0]
   TEMP6[31-0] <- TEMP5[39-0] MOD2 11EDC6F41H
   DEST[31-0] <- BIT_REFLECT (TEMP6[31-0])

Flags Affected
None





Intel C/C++ Compiler Intrinsic Equivalent
unsigned int _mm_crc32_u8( unsigned int crc, unsigned char data )
unsigned int _mm_crc32_u16( unsigned int crc, unsigned short data )
unsigned int _mm_crc32_u32( unsigned int crc, unsigned int data )
unsinged __int64 _mm_crc32_u64( unsinged __int64 crc, unsigned __int64 data )

SIMD Floating Point Exceptions
None

Protected Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)       For a page fault.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
                       If LOCK prefix is used.

Real-Address Mode Exceptions
#GP(0)                 If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
                       If LOCK prefix is used.

Virtual 8086 Mode Exceptions
#GP(0)                 If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)       For a page fault.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
                       If LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in Protected Mode.

64-Bit Mode Exceptions
#GP(0)                 If the memory address is in a non-canonical form.
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)       For a page fault.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If CPUID.01H:ECX.SSE4_2 [Bit 20] = 0.
                       If LOCK prefix is used.






platform: x86_64
mnem: CVTDQ2PD
description:
CVTDQ2PD-Convert Packed Doubleword Integers to Packed Double-Precision Floating-Point
Values
 Opcode/                            Op /    64/32         CPUID          Description
 Instruction                        En      bit Mode      Feature
                                            Support       Flag
 F3 0F E6 /r                        RM      V/V           SSE2           Convert two packed signed doubleword integers from
 CVTDQ2PD xmm1, xmm2/m64                                                 xmm2/mem to two packed double-precision floating-
                                                                         point values in xmm1.
 VEX.128.F3.0F.WIG E6 /r            RM      V/V           AVX            Convert two packed signed doubleword integers from
 VCVTDQ2PD xmm1, xmm2/m64                                                xmm2/mem to two packed double-precision floating-
                                                                         point values in xmm1.
 VEX.256.F3.0F.WIG E6 /r            RM      V/V           AVX            Convert four packed signed doubleword integers from
 VCVTDQ2PD ymm1, xmm2/m128                                               xmm2/mem to four packed double-precision floating-
                                                                         point values in ymm1.
 EVEX.128.F3.0F.W0 E6 /r            HV      V/V           AVX512VL       Convert 2 packed signed doubleword integers from
 VCVTDQ2PD xmm1 {k1}{z},                                  AVX512F        xmm2/m128/m32bcst to eight packed double-precision
 xmm2/m128/m32bcst                                                       floating-point values in xmm1 with writemask k1.
 EVEX.256.F3.0F.W0 E6 /r            HV      V/V           AVX512VL       Convert 4 packed signed doubleword integers from
 VCVTDQ2PD ymm1 {k1}{z},                                  AVX512F        xmm2/m128/m32bcst to 4 packed double-precision
 xmm2/m128/m32bcst                                                       floating-point values in ymm1 with writemask k1.
 EVEX.512.F3.0F.W0 E6 /r            HV      V/V           AVX512F        Convert eight packed signed doubleword integers from
 VCVTDQ2PD zmm1 {k1}{z},                                                 ymm2/m256/m32bcst to eight packed double-precision
 ymm2/m256/m32bcst                                                       floating-point values in zmm1 with writemask k1.



                                             Instruction Operand Encoding
     Op/En            Operand 1                   Operand 2                     Operand 3                      Operand 4
       RM           ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA
       HV           ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA

Description
Converts two, four or eight packed signed doubleword integers in the source operand (the second operand) to two,
four or eight packed double-precision floating-point values in the destination operand (the first operand).
EVEX encoded versions: The source operand can be a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit
memory location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand
is a ZMM/YMM/XMM register conditionally updated with writemask k1. Attempt to encode this instruction with EVEX
embedded rounding is ignored.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.





                            SRC                                              X3         X2     X1        X0




                            DEST        X3                     X2                  X1               X0



                                      Figure 3-11. CVTDQ2PD (VEX.256 encoded version)


Operation
VCVTDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Integer_To_Double_Precision_Floating_Point(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTDQ2PD (VEX.256 encoded version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256] <- 0

VCVTDQ2PD (VEX.128 encoded version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] <- 0

CVTDQ2PD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PD __m512d _mm512_cvtepi32_pd( __m256i a);
VCVTDQ2PD __m512d _mm512_mask_cvtepi32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m512d _mm512_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_mask_cvtepi32_pd( __m256d s, __mmask8 k, __m256i a);
VCVTDQ2PD __m256d _mm256_maskz_cvtepi32_pd( __mmask8 k, __m256i a);
VCVTDQ2PD __m128d _mm_mask_cvtepi32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTDQ2PD __m128d _mm_maskz_cvtepi32_pd( __mmask8 k, __m128i a);
CVTDQ2PD __m256d _mm256_cvtepi32_pd (__m128i src)
CVTDQ2PD __m128d _mm_cvtepi32_pd (__m128i src)




Other Exceptions
VEX-encoded instructions, see Exceptions Type 5;
EVEX-encoded instructions, see Exceptions Type E5.
#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTDQ2PS
description:
CVTDQ2PS-Convert Packed Doubleword Integers to Packed Single-Precision Floating-Point
Values
 Opcode                               Op /    64/32         CPUID          Description
 Instruction                          En      bit Mode      Feature
                                              Support       Flag
 0F 5B /r                             RM      V/V           SSE2           Convert four packed signed doubleword integers from
 CVTDQ2PS xmm1, xmm2/m128                                                  xmm2/mem to four packed single-precision floating-
                                                                           point values in xmm1.
 VEX.128.0F.WIG 5B /r                 RM       V/V          AVX            Convert four packed signed doubleword integers from
 VCVTDQ2PS xmm1, xmm2/m128                                                 xmm2/mem to four packed single-precision floating-
                                                                           point values in xmm1.
 VEX.256.0F.WIG 5B /r                 RM       V/V          AVX            Convert eight packed signed doubleword integers from
 VCVTDQ2PS ymm1, ymm2/m256                                                 ymm2/mem to eight packed single-precision floating-
                                                                           point values in ymm1.
 EVEX.128.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert four packed signed doubleword integers from
 VCVTDQ2PS xmm1 {k1}{z},                                    AVX512F        xmm2/m128/m32bcst to four packed single-precision
 xmm2/m128/m32bcst                                                         floating-point values in xmm1with writemask k1.
 EVEX.256.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert eight packed signed doubleword integers from
 VCVTDQ2PS ymm1 {k1}{z},                                    AVX512F        ymm2/m256/m32bcst to eight packed single-precision
 ymm2/m256/m32bcst                                                         floating-point values in ymm1with writemask k1.
 EVEX.512.0F.W0 5B /r                 FV      V/V           AVX512F        Convert sixteen packed signed doubleword integers
 VCVTDQ2PS zmm1 {k1}{z},                                                   from zmm2/m512/m32bcst to sixteen packed single-
 zmm2/m512/m32bcst{er}                                                     precision floating-point values in zmm1with writemask
                                                                           k1.



                                              Instruction Operand Encoding
       Op/En            Operand 1                    Operand 2                    Operand 3                      Operand 4
        RM            ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA
        FV            ModRM:reg (w)               ModRM:r/m (r)                       NA                             NA

Description
Converts four, eight or sixteen packed signed doubleword integers in the source operand to four, eight or sixteen
packed single-precision floating-point values in the destination operand.
EVEX encoded versions: The source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding register destination are unmod-
ified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.





Operation
VCVTDQ2PS (EVEX encoded versions) when SRC operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);              ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference
    ELSE
         SET_RM(MXCSR.RM);             ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTDQ2PS (EVEX encoded versions) when SRC operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <-j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Integer_To_Single_Precision_Floating_Point(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTDQ2PS (VEX.256 encoded version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96)
DEST[159:128] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[159:128])
DEST[191:160] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[191:160])
DEST[223:192] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[223:192])
DEST[255:224] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[255:224)
DEST[MAX_VL-1:256] <- 0

VCVTDQ2PS (VEX.128 encoded version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] <- 0

CVTDQ2PS (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0])
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32])
DEST[95:64] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64])
DEST[127:96] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[127z:96)
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTDQ2PS __m512 _mm512_cvtepi32_ps( __m512i a);
VCVTDQ2PS __m512 _mm512_mask_cvtepi32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_maskz_cvtepi32_ps( __mmask16 k, __m512i a);
VCVTDQ2PS __m512 _mm512_cvt_roundepi32_ps( __m512i a, int r);
VCVTDQ2PS __m512 _mm512_mask_cvt_roundepi_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m512 _mm512_maskz_cvt_roundepi32_ps( __mmask16 k, __m512i a, int r);
VCVTDQ2PS __m256 _mm256_mask_cvtepi32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTDQ2PS __m256 _mm256_maskz_cvtepi32_ps( __mmask8 k, __m256i a);
VCVTDQ2PS __m128 _mm_mask_cvtepi32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTDQ2PS __m128 _mm_maskz_cvtepi32_ps( __mmask8 k, __m128i a);
CVTDQ2PS __m256 _mm256_cvtepi32_ps (__m256i src)
CVTDQ2PS __m128 _mm_cvtepi32_ps (__m128i src)

SIMD Floating-Point Exceptions
Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTPD2DQ
description:
CVTPD2DQ-Convert Packed Double-Precision Floating-Point Values to Packed Doubleword
Integers
 Opcode                                      Op /    64/32         CPUID         Description
 Instruction                                 En      bit Mode      Feature
                                                     Support       Flag
 F2 0F E6 /r                                 RM      V/V           SSE2          Convert two packed double-precision floating-point
 CVTPD2DQ xmm1, xmm2/m128                                                        values in xmm2/mem to two signed doubleword
                                                                                 integers in xmm1.
 VEX.128.F2.0F.WIG E6 /r                     RM      V/V           AVX           Convert two packed double-precision floating-point
 VCVTPD2DQ xmm1, xmm2/m128                                                       values in xmm2/mem to two signed doubleword
                                                                                 integers in xmm1.
 VEX.256.F2.0F.WIG E6 /r                     RM      V/V           AVX           Convert four packed double-precision floating-point
 VCVTPD2DQ xmm1, ymm2/m256                                                       values in ymm2/mem to four signed doubleword
                                                                                 integers in xmm1.
 EVEX.128.F2.0F.W1 E6 /r                     FV      V/V           AVX512VL      Convert two packed double-precision floating-point
 VCVTPD2DQ xmm1 {k1}{z},                                           AVX512F       values in xmm2/m128/m64bcst to two signed
 xmm2/m128/m64bcst                                                               doubleword integers in xmm1 subject to writemask k1.
 EVEX.256.F2.0F.W1 E6 /r                     FV      V/V           AVX512VL      Convert four packed double-precision floating-point
 VCVTPD2DQ xmm1 {k1}{z},                                           AVX512F       values in ymm2/m256/m64bcst to four signed
 ymm2/m256/m64bcst                                                               doubleword integers in xmm1 subject to writemask k1.
 EVEX.512.F2.0F.W1 E6 /r                     FV      V/V           AVX512F       Convert eight packed double-precision floating-point
 VCVTPD2DQ ymm1 {k1}{z},                                                         values in zmm2/m512/m64bcst to eight signed
 zmm2/m512/m64bcst{er}                                                           doubleword integers in ymm1 subject to writemask k1.



                                                    Instruction Operand Encoding
      Op/En                Operand 1                    Operand 2                      Operand 3                  Operand 4
       RM                ModRM:reg (w)                ModRM:r/m (r)                        NA                        NA
        FV               ModRM:reg (w)                ModRM:r/m (r)                        NA                        NA

Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed signed
doubleword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512-bit memory location, or a 512-bit
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register condi-
tionally updated with writemask k1. The upper bits (MAX_VL-1:256/128/64) of the corresponding destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.





                SRC        X3                   X2                   X1                  X0




                DEST                   0                      X3          X2       X1         X0



                                 Figure 3-12. VCVTPD2DQ (VEX.256 encoded version)


Operation
VCVTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





VCVTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1)
                    THEN
                         DEST[i+31:i] <-
               Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
                    ELSE
                         DEST[i+31:i] <-
               Convert_Double_Precision_Floating_Point_To_Integer(SRC[k+63:k])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

VCVTPD2DQ (VEX.256 encoded version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[191:128])
DEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[255:192)
DEST[MAX_VL-1:128]<-0

VCVTPD2DQ (VEX.128 encoded version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[MAX_VL-1:64]<-0

CVTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[127:64])
DEST[127:64] <-0
DEST[MAX_VL-1:128] (unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2DQ __m256i _mm512_cvtpd_epi32( __m512d a);
VCVTPD2DQ __m256i _mm512_mask_cvtpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_maskz_cvtpd_epi32( __mmask8 k, __m512d a);
VCVTPD2DQ __m256i _mm512_cvt_roundpd_epi32( __m512d a, int r);
VCVTPD2DQ __m256i _mm512_mask_cvt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m256i _mm512_maskz_cvt_roundpd_epi32( __mmask8 k, __m512d a, int r);
VCVTPD2DQ __m128i _mm256_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm256_maskz_cvtpd_epi32( __mmask8 k, __m256d a);
VCVTPD2DQ __m128i _mm_mask_cvtpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm_maskz_cvtpd_epi32( __mmask8 k, __m128d a);
VCVTPD2DQ __m128i _mm256_cvtpd_epi32 (__m256d src)
CVTPD2DQ __m128i _mm_cvtpd_epi32 (__m128d src)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
See Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD                  If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTPD2PI
description:
CVTPD2PI-Convert Packed Double-Precision FP Values to Packed Dword Integers
Opcode/                                                  Op/    64-Bit        Compat/ Description
Instruction                                              En     Mode          Leg Mode
66 0F 2D /r                                              RM     Valid         Valid     Convert two packed double-precision floating-
CVTPD2PI mm, xmm/m128                                                                   point values from xmm/m128 to two packed
                                                                                        signed doubleword integers in mm.



                                                   Instruction Operand Encoding
   Op/En               Operand 1                        Operand 2                     Operand 3                   Operand 4
    RM               ModRM:reg (w)                    ModRM:r/m (r)                      NA                          NA

Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-
nology register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid
exception is raised, and if this exception is masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[63:0]);
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent
CVTPD1PI:      __m64 _mm_cvtpd_pi32(__m128d a)

SIMD Floating-Point Exceptions
Invalid, Precision.

Other Exceptions
See Table 22-4, "Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-
ment," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTPD2PS
description:
CVTPD2PS-Convert Packed Double-Precision Floating-Point Values to Packed Single-Precision
Floating-Point Values
 Opcode/                                  Op /     64/32        CPUID          Description
 Instruction                              En       bit Mode     Feature
                                                   Support      Flag
 66 0F 5A /r                              RM       V/V          SSE2           Convert two packed double-precision floating-point
 CVTPD2PS xmm1, xmm2/m128                                                      values in xmm2/mem to two single-precision
                                                                               floating-point values in xmm1.
 VEX.128.66.0F.WIG 5A /r                  RM       V/V          AVX            Convert two packed double-precision floating-point
 VCVTPD2PS xmm1, xmm2/m128                                                     values in xmm2/mem to two single-precision
                                                                               floating-point values in xmm1.
 VEX.256.66.0F.WIG 5A /r                  RM       V/V          AVX            Convert four packed double-precision floating-point
 VCVTPD2PS xmm1, ymm2/m256                                                     values in ymm2/mem to four single-precision
                                                                               floating-point values in xmm1.
 EVEX.128.66.0F.W1 5A /r                  FV       V/V          AVX512VL       Convert two packed double-precision floating-point
 VCVTPD2PS xmm1 {k1}{z},                                        AVX512F        values in xmm2/m128/m64bcst to two single-
 xmm2/m128/m64bcst                                                             precision floating-point values in xmm1with
                                                                               writemask k1.
 EVEX.256.66.0F.W1 5A /r                  FV       V/V          AVX512VL       Convert four packed double-precision floating-point
 VCVTPD2PS xmm1 {k1}{z},                                        AVX512F        values in ymm2/m256/m64bcst to four single-
 ymm2/m256/m64bcst                                                             precision floating-point values in xmm1with
                                                                               writemask k1.
 EVEX.512.66.0F.W1 5A /r                  FV       V/V          AVX512F        Convert eight packed double-precision floating-point
 VCVTPD2PS ymm1 {k1}{z},                                                       values in zmm2/m512/m64bcst to eight single-
 zmm2/m512/m64bcst{er}                                                         precision floating-point values in ymm1with
                                                                               writemask k1.



                                                 Instruction Operand Encoding
      Op/En             Operand 1                        Operand 2                    Operand 3                      Operand 4
       RM             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA
       FV             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA

Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed single-precision floating-point values in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64-bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-
1:256/128/64) of the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. Bits[127:64] of the destination XMM register are zeroed. However, the upper Bits
(MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.




                   SRC         X3                      X2                   X1                   X0




                   DEST                      0                        X3         X2       X1          X0



                                      Figure 3-13. VCVTPD2PS (VEX.256 encoded version)


Operation
VCVTPD2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





VCVTPD2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[63:0])
                  ELSE
                       DEST[i+31:i] <- Convert_Double_Precision_Floating_Point_To_Single_Precision_Floating_Point(SRC[k+63:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

VCVTPD2PS (VEX.256 encoded version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[95:64] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[191:128])
DEST[127:96] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[255:192)
DEST[MAX_VL-1:128] <- 0

VCVTPD2PS (VEX.128 encoded version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[MAX_VL-1:64] <- 0

CVTPD2PS (128-bit Legacy SSE version)
DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0])
DEST[63:32] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[127:64])
DEST[127:64] <- 0
DEST[MAX_VL-1:128] (unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2PS __m256 _mm512_cvtpd_ps( __m512d a);
VCVTPD2PS __m256 _mm512_mask_cvtpd_ps( __m256 s, __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_maskz_cvtpd_ps( __mmask8 k, __m512d a);
VCVTPD2PS __m256 _mm512_cvt_roundpd_ps( __m512d a, int r);
VCVTPD2PS __m256 _mm512_mask_cvt_roundpd_ps( __m256 s, __mmask8 k, __m512d a, int r);
VCVTPD2PS __m256 _mm512_maskz_cvt_roundpd_ps( __mmask8 k, __m512d a, int r);
VCVTPD2PS __m128 _mm256_mask_cvtpd_ps( __m128 s, __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm256_maskz_cvtpd_ps( __mmask8 k, __m256d a);
VCVTPD2PS __m128 _mm_mask_cvtpd_ps( __m128 s, __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm_maskz_cvtpd_ps( __mmask8 k, __m128d a);
VCVTPD2PS __m128 _mm256_cvtpd_ps (__m256d a)
CVTPD2PS __m128 _mm_cvtpd_ps (__m128d a)

SIMD Floating-Point Exceptions
Invalid, Precision, Underflow, Overflow, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD                       If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTPI2PD
description:
CVTPI2PD-Convert Packed Dword Integers to Packed Double-Precision FP Values
Opcode/                                                 Op/    64-Bit       Compat/ Description
Instruction                                             En     Mode         Leg Mode
66 0F 2A /r                                             RM     Valid        Valid       Convert two packed signed doubleword
CVTPI2PD xmm, mm/m64*                                                                   integers from mm/mem64 to two packed
                                                                                        double-precision floating-point values in xmm.
NOTES:
*Operation is different for different operand sets; see the Description section.



                                                  Instruction Operand Encoding
    Op/En             Operand 1                      Operand 2                      Operand 3                      Operand 4
     RM             ModRM:reg (w)                  ModRM:r/m (r)                        NA                             NA

Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed double-
precision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. In addition, depending on the operand configuration:
.    For operands xmm, mm: the instruction causes a transition from x87 FPU to MMX technology operation (that
     is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this
     instruction is executed while an x87 FPU floating-point exception is pending, the exception is handled before
     the CVTPI2PD instruction is executed.
.    For operands xmm, m64: the instruction does not cause a transition to MMX technology and does not take
     x87 FPU exceptions.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PD:       __m128d _mm_cvtpi32_pd(__m64 a)

SIMD Floating-Point Exceptions
None

Other Exceptions
See Table 22-6, "Exception Conditions for Legacy SIMD/MMX Instructions with XMM and without FP Exception," in
the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTPI2PS
description:
CVTPI2PS-Convert Packed Dword Integers to Packed Single-Precision FP Values
Opcode/                                                    Op/    64-Bit      Compat/ Description
Instruction                                                En     Mode        Leg Mode
0F 2A /r                                                   RM     Valid       Valid       Convert two signed doubleword integers
CVTPI2PS xmm, mm/m64                                                                      from mm/m64 to two single-precision
                                                                                          floating-point values in xmm.



                                                    Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                       Operand 3                  Operand 4
    RM              ModRM:reg (w)                   ModRM:r/m (r)                        NA                          NA

Description
Converts two packed signed doubleword integers in the source operand (second operand) to two packed single-
precision floating-point values in the destination operand (first operand).
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
XMM register. The results are stored in the low quadword of the destination operand, and the high quadword
remains unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTPI2PS instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
(* High quadword of destination unchanged *)

Intel C/C++ Compiler Intrinsic Equivalent
CVTPI2PS:      __m128 _mm_cvtpi32_ps(__m128 a, __m64 b)

SIMD Floating-Point Exceptions
Precision

Other Exceptions
See Table 22-5, "Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception," in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTPS2DQ
description:
CVTPS2DQ-Convert Packed Single-Precision Floating-Point Values to Packed Signed
Doubleword Integer Values
 Opcode/                              Op /   64/32       CPUID          Description
 Instruction                          En     bit Mode    Feature
                                             Support     Flag
 66 0F 5B /r                          RM     V/V         SSE2           Convert four packed single-precision floating-point values
 CVTPS2DQ xmm1, xmm2/m128                                               from xmm2/mem to four packed signed doubleword
                                                                        values in xmm1.
 VEX.128.66.0F.WIG 5B /r              RM     V/V         AVX            Convert four packed single-precision floating-point values
 VCVTPS2DQ xmm1, xmm2/m128                                              from xmm2/mem to four packed signed doubleword
                                                                        values in xmm1.
 VEX.256.66.0F.WIG 5B /r              RM     V/V         AVX            Convert eight packed single-precision floating-point values
 VCVTPS2DQ ymm1, ymm2/m256                                              from ymm2/mem to eight packed signed doubleword
                                                                        values in ymm1.
 EVEX.128.66.0F.W0 5B /r              FV     V/V         AVX512VL       Convert four packed single precision floating-point values
 VCVTPS2DQ xmm1 {k1}{z},                                 AVX512F        from xmm2/m128/m32bcst to four packed signed
 xmm2/m128/m32bcst                                                      doubleword values in xmm1 subject to writemask k1.
 EVEX.256.66.0F.W0 5B /r              FV     V/V         AVX512VL       Convert eight packed single precision floating-point values
 VCVTPS2DQ ymm1 {k1}{z},                                 AVX512F        from ymm2/m256/m32bcst to eight packed signed
 ymm2/m256/m32bcst                                                      doubleword values in ymm1 subject to writemask k1.
 EVEX.512.66.0F.W0 5B /r              FV     V/V         AVX512F        Convert sixteen packed single-precision floating-point
 VCVTPS2DQ zmm1 {k1}{z},                                                values from zmm2/m512/m32bcst to sixteen packed
 zmm2/m512/m32bcst{er}                                                  signed doubleword values in zmm1 subject to writemask
                                                                        k1.



                                              Instruction Operand Encoding
     Op/En              Operand 1                   Operand 2                      Operand 3                     Operand 4
       RM             ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA
       FV             ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA

Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX encoded versions: The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPS2DQ (encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO 15
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTPS2DQ (VEX.256 encoded version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96)
DEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[159:128])
DEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[191:160])
DEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[223:192])
DEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[255:224])

VCVTPS2DQ (VEX.128 encoded version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] <-0

CVTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2DQ __m512i _mm512_cvtps_epi32( __m512 a);
VCVTPS2DQ __m512i _mm512_mask_cvtps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_maskz_cvtps_epi32( __mmask16 k, __m512 a);
VCVTPS2DQ __m512i _mm512_cvt_roundps_epi32( __m512 a, int r);
VCVTPS2DQ __m512i _mm512_mask_cvt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m512i _mm512_maskz_cvt_roundps_epi32( __mmask16 k, __m512 a, int r);
VCVTPS2DQ __m256i _mm256_mask_cvtps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2DQ __m256i _mm256_maskz_cvtps_epi32( __mmask8 k, __m256 a);
VCVTPS2DQ __m128i _mm_mask_cvtps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2DQ __m128i _mm_maskz_cvtps_epi32( __mmask8 k, __m128 a);
VCVTPS2DQ __ m256i _mm256_cvtps_epi32 (__m256 a)
CVTPS2DQ __m128i _mm_cvtps_epi32 (__m128 a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTPS2PD
description:
CVTPS2PD-Convert Packed Single-Precision Floating-Point Values to Packed Double-Precision
Floating-Point Values
 Opcode/                                  Op /    64/32         CPUID           Description
 Instruction                              En      bit Mode      Feature
                                                  Support       Flag
 0F 5A /r                                 RM      V/V           SSE2            Convert two packed single-precision floating-point values in
 CVTPS2PD xmm1, xmm2/m64                                                        xmm2/m64 to two packed double-precision floating-point
                                                                                values in xmm1.
 VEX.128.0F.WIG 5A /r                     RM      V/V           AVX             Convert two packed single-precision floating-point values in
 VCVTPS2PD xmm1, xmm2/m64                                                       xmm2/m64 to two packed double-precision floating-point
                                                                                values in xmm1.
 VEX.256.0F.WIG 5A /r                     RM      V/V           AVX             Convert four packed single-precision floating-point values
 VCVTPS2PD ymm1, xmm2/m128                                                      in xmm2/m128 to four packed double-precision floating-
                                                                                point values in ymm1.
 EVEX.128.0F.W0 5A /r                     HV      V/V           AVX512VL        Convert two packed single-precision floating-point values in
 VCVTPS2PD xmm1 {k1}{z},                                        AVX512F         xmm2/m64/m32bcst to packed double-precision floating-
 xmm2/m64/m32bcst                                                               point values in xmm1 with writemask k1.
 EVEX.256.0F.W0 5A /r                     HV      V/V           AVX512VL        Convert four packed single-precision floating-point values
 VCVTPS2PD ymm1 {k1}{z},                                                        in xmm2/m128/m32bcst to packed double-precision
 xmm2/m128/m32bcst                                                              floating-point values in ymm1 with writemask k1.
 EVEX.512.0F.W0 5A /r                     HV      V/V           AVX512F         Convert eight packed single-precision floating-point values
 VCVTPS2PD zmm1 {k1}{z},                                                        in ymm2/m256/b32bcst to eight packed double-precision
 ymm2/m256/m32bcst{sae}                                                         floating-point values in zmm1 with writemask k1.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                      Operand 3                      Operand 4
       RM                ModRM:reg (w)                   ModRM:r/m (r)                        NA                            NA
       HV                ModRM:reg (w)                   ModRM:r/m (r)                        NA                            NA

Description
Converts two, four or eight packed single-precision floating-point values in the source operand (second operand)
to two, four or eight packed double-precision floating-point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register, a 256/128/64-bit memory
location or a 256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a YMM register. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The source operand is an XMM register or 64- bit memory location. The destination
operand is a XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 64- bit memory location. The destination
operand is an XMM register. The upper Bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





                 SRC                                              X3         X2        X1         X0




                 DEST       X3                     X2                   X1                   X0




                                   Figure 3-14. CVTPS2PD (VEX.256 encoded version)


Operation
VCVTPS2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[k+31:k])
             FI;
        ELSE



              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
              FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2PD (VEX.256 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[191:128] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[95:64])
DEST[255:192] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[127:96)
DEST[MAX_VL-1:256] <- 0

VCVTPS2PD (VEX.128 encoded version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] <- 0

CVTPS2PD (128-bit Legacy SSE version)
DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0])
DEST[127:64] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[63:32])
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PD __m512d _mm512_cvtps_pd( __m256 a);
VCVTPS2PD __m512d _mm512_mask_cvtps_pd( __m512d s, __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_maskz_cvtps_pd( __mmask8 k, __m256 a);
VCVTPS2PD __m512d _mm512_cvt_roundps_pd( __m256 a, int sae);
VCVTPS2PD __m512d _mm512_mask_cvt_roundps_pd( __m512d s, __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m512d _mm512_maskz_cvt_roundps_pd( __mmask8 k, __m256 a, int sae);
VCVTPS2PD __m256d _mm256_mask_cvtps_pd( __m256d s, __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_maskz_cvtps_pd( __mmask8 k, __m128a);
VCVTPS2PD __m128d _mm_mask_cvtps_pd( __m128d s, __mmask8 k, __m128 a);
VCVTPS2PD __m128d _mm_maskz_cvtps_pd( __mmask8 k, __m128 a);
VCVTPS2PD __m256d _mm256_cvtps_pd (__m128 a)
CVTPS2PD __m128d _mm_cvtps_pd (__m128 a)

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3.
#UD                       If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTPS2PI
description:
CVTPS2PI-Convert Packed Single-Precision FP Values to Packed Dword Integers
 Opcode/                                             Op/   64-Bit      Compat/ Description
 Instruction                                         En    Mode        Leg Mode
 0F 2D /r                                            RM    Valid       Valid        Convert two packed single-precision floating-
 CVTPS2PI mm, xmm/m64                                                               point values from xmm/m64 to two packed
                                                                                    signed doubleword integers in mm.



                                              Instruction Operand Encoding
  Op/En              Operand 1                    Operand 2                      Operand 3                      Operand 4
    RM             ModRM:reg (w)                 ModRM:r/m (r)                       NA                             NA

Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The destination operand is an MMX tech-
nology register. When the source operand is an XMM register, the two single-precision floating-point values are
contained in the low quadword of the register. When a conversion is inexact, the value returned is rounded
according to the rounding control bits in the MXCSR register. If a converted result is larger than the maximum
signed doubleword integer, the floating-point invalid exception is raised, and if this exception is masked, the indef-
inite integer value (80000000H) is returned.
CVTPS2PI causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack pointer
is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU floating-
point exception is pending, the exception is handled before the CVTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent
CVTPS2PI:       __m64 _mm_cvtps_pi32(__m128 a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
See Table 22-5, "Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception," in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTSD2SI
description:
CVTSD2SI-Convert Scalar Double-Precision Floating-Point Value to Doubleword Integer
 Opcode/                                     Op /    64/32         CPUID          Description
 Instruction                                 En      bit Mode      Feature
                                                     Support       Flag
 F2 0F 2D /r                                 RM      V/V           SSE2           Convert one double-precision floating-point value from
 CVTSD2SI r32, xmm1/m64                                                           xmm1/m64 to one signed doubleword integer r32.
 F2 REX.W 0F 2D /r                           RM      V/N.E.        SSE2           Convert one double-precision floating-point value from
 CVTSD2SI r64, xmm1/m64                                                           xmm1/m64 to one signed quadword integer sign-
                                                                                  extended into r64.
 VEX.128.F2.0F.W0 2D /r                      RM      V/V           AVX            Convert one double-precision floating-point value from
 VCVTSD2SI r32, xmm1/m64                                                          xmm1/m64 to one signed doubleword integer r32.
 VEX.128.F2.0F.W1 2D /r                      RM      V/N.E.1       AVX            Convert one double-precision floating-point value from
 VCVTSD2SI r64, xmm1/m64                                                          xmm1/m64 to one signed quadword integer sign-
                                                                                  extended into r64.
 EVEX.LIG.F2.0F.W0 2D /r                     T1F     V/V           AVX512F        Convert one double-precision floating-point value from
 VCVTSD2SI r32, xmm1/m64{er}                                                      xmm1/m64 to one signed doubleword integer r32.
 EVEX.LIG.F2.0F.W1 2D /r                     T1F     V/N.E.1       AVX512F        Convert one double-precision floating-point value from
 VCVTSD2SI r64, xmm1/m64{er}                                                      xmm1/m64 to one signed quadword integer sign-
                                                                                  extended into r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                     Instruction Operand Encoding
       Op/En                  Operand 1                       Operand 2                   Operand 3                    Operand 4
         RM                ModRM:reg (w)                   ModRM:r/m (r)                        NA                        NA
        T1F                ModRM:reg (w)                   ModRM:r/m (r)                        NA                        NA

Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed double-
word integer in the destination operand (first operand). The source operand can be an XMM register or a 64-bit
memory location. The destination operand is a general-purpose register. When the source operand is an XMM
register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instruction: Use of the REX.W prefix promotes the instruction to produce 64-bit data in 64-bit mode.
See the summary chart at the beginning of this section for encoding data and limits.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSD2SI is encoded with VEX.L=0. Encoding VCVTSD2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VCVTSD2SI (EVEX encoded version)
IF SRC *is register* AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode and OperandSize = 64
    THEN      DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
    ELSE      DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI

(V)CVTSD2SI
IF 64-Bit Mode and OperandSize = 64
THEN
    DEST[63:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
ELSE
    DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer(SRC[63:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SI int _mm_cvtsd_i32(__m128d);
VCVTSD2SI int _mm_cvt_roundsd_i32(__m128d, int r);
VCVTSD2SI __int64 _mm_cvtsd_i64(__m128d);
VCVTSD2SI __int64 _mm_cvt_roundsd_i64(__m128d, int r);
CVTSD2SI __int64 _mm_cvtsd_si64(__m128d);
CVTSD2SI int _mm_cvtsd_si32(__m128d a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3;
EVEX-encoded instructions, see Exceptions Type E3NF.
#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTSD2SS
description:
CVTSD2SS-Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision
Floating-Point Value
 Opcode/                                      Op /     64/32         CPUID           Description
 Instruction                                  En       bit Mode      Feature
                                                       Support       Flag
 F2 0F 5A /r                                  RM       V/V           SSE2            Convert one double-precision floating-point value in
 CVTSD2SS xmm1, xmm2/m64                                                             xmm2/m64 to one single-precision floating-point value
                                                                                     in xmm1.
 VEX.NDS.128.F2.0F.WIG 5A /r                  RVM      V/V           AVX             Convert one double-precision floating-point value in
 VCVTSD2SS xmm1,xmm2,                                                                xmm3/m64 to one single-precision floating-point value
 xmm3/m64                                                                            and merge with high bits in xmm2.
 EVEX.NDS.LIG.F2.0F.W1 5A /r                  T1S      V/V           AVX512F         Convert one double-precision floating-point value in
 VCVTSD2SS xmm1 {k1}{z}, xmm2,                                                       xmm3/m64 to one single-precision floating-point value
 xmm3/m64{er}                                                                        and merge with high bits in xmm2 under writemask k1.



                                                      Instruction Operand Encoding
      Op/En                  Operand 1                        Operand 2                       Operand 3                      Operand 4
        RM                 ModRM:reg (w)                     ModRM:r/m (r)                         NA                           NA
       RVM                 ModRM:reg (w)                       VEX.vvvv                     ModRM:r/m (r)                       NA
       T1S                 ModRM:reg (w)                      EVEX.vvvv                     ModRM:r/m (r)                       NA

Description
Converts a double-precision floating-point value in the "convert-from" source operand (the second operand in
SSE2 version, otherwise the third operand) to a single-precision floating-point value in the destination operand.
When the "convert-from" operand is an XMM register, the double-precision floating-point value is contained in the
low quadword of the register. The result is stored in the low doubleword of the destination operand. When the
conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register.
128-bit Legacy SSE version: The "convert-from" source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged. The destina-
tion operand is an XMM register.
VEX.128 and EVEX encoded versions: The "convert-from" source operand (the third operand) can be an XMM
register or a 64-bit memory location. The first source and destination operands are XMM registers. Bits (127:32) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSD2SS is encoded with VEX.L=0. Encoding VCVTSD2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VCVTSD2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                   THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VCVTSD2SS (VEX.128 encoded version)
DEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC2[63:0]);
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

CVTSD2SS (128-bit Legacy SSE version)
DEST[31:0] <-Convert_Double_Precision_To_Single_Precision_Floating_Point(SRC[63:0]);
(* DEST[MAX_VL-1:32] Unmodified *)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2SS __m128 _mm_mask_cvtsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b);
VCVTSD2SS __m128 _mm_maskz_cvtsd_ss( __mmask8 k, __m128 a,__m128d b);
VCVTSD2SS __m128 _mm_cvt_roundsd_ss(__m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_mask_cvt_roundsd_ss(__m128 s, __mmask8 k, __m128 a, __m128d b, int r);
VCVTSD2SS __m128 _mm_maskz_cvt_roundsd_ss( __mmask8 k, __m128 a,__m128d b, int r);
CVTSD2SS __m128_mm_cvtsd_ss(__m128 a, __m128d b)

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: CVTSI2SD
description:
CVTSI2SD-Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
 Opcode/                                           Op /      64/32        CPUID        Description
 Instruction                                       En        bit Mode     Feature
                                                             Support      Flag
 F2 0F 2A /r                                       RM        V/V          SSE2         Convert one signed doubleword integer from
 CVTSI2SD xmm1, r32/m32                                                                r32/m32 to one double-precision floating-point
                                                                                       value in xmm1.
 F2 REX.W 0F 2A /r                                 RM        V/N.E.       SSE2         Convert one signed quadword integer from r/m64
 CVTSI2SD xmm1, r/m64                                                                  to one double-precision floating-point value in
                                                                                       xmm1.
 VEX.NDS.128.F2.0F.W0 2A /r                        RVM       V/V          AVX          Convert one signed doubleword integer from
 VCVTSI2SD xmm1, xmm2, r/m32                                                           r/m32 to one double-precision floating-point
                                                                                       value in xmm1.
 VEX.NDS.128.F2.0F.W1 2A /r                        RVM       V/N.E.1      AVX          Convert one signed quadword integer from r/m64
 VCVTSI2SD xmm1, xmm2, r/m64                                                           to one double-precision floating-point value in
                                                                                       xmm1.
 EVEX.NDS.LIG.F2.0F.W0 2A /r                       T1S       V/V          AVX512F      Convert one signed doubleword integer from
 VCVTSI2SD xmm1, xmm2, r/m32                                                           r/m32 to one double-precision floating-point
                                                                                       value in xmm1.
 EVEX.NDS.LIG.F2.0F.W1 2A /r                       T1S       V/N.E.1      AVX512F      Convert one signed quadword integer from r/m64
 VCVTSI2SD xmm1, xmm2, r/m64{er}                                                       to one double-precision floating-point value in
                                                                                       xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                   Operand 3                    Operand 4
        RM                ModRM:reg (w)                   ModRM:r/m (r)                    NA                          NA
       RVM                ModRM:reg (w)                     VEX.vvvv                  ModRM:r/m (r)                    NA
       T1S                ModRM:reg (w)                    EVEX.vvvv                  ModRM:r/m (r)                    NA

Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the "convert-from"
source operand to a double-precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand, and the high quadword left unchanged. When conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers.
128-bit Legacy SSE version: Use of the REX.W prefix promotes the instruction to 64-bit operands. The "convert-
from" source operand (the second operand) is a general-purpose register or memory location. The destination is
an XMM register Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The "convert-from" source operand (the third operand) can be a general-
purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:64)
of the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.
VEX.W1 and EVEX.W1 versions: promotes the instruction to use 64-bit input value in 64-bit mode.
Software should ensure VCVTSI2SD is encoded with VEX.L=0. Encoding VCVTSI2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VCVTSI2SD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
    DEST[63:0] <- Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VCVTSI2SD (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

CVTSI2SD
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:0]);
ELSE
    DEST[63:0] <-Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SD __m128d _mm_cvti32_sd(__m128d s, int a);
VCVTSI2SD __m128d _mm_cvt_roundi32_sd(__m128d s, int a, int r);
VCVTSI2SD __m128d _mm_cvti64_sd(__m128d s, __int64 a);
VCVTSI2SD __m128d _mm_cvt_roundi64_sd(__m128d s, __int64 a, int r);
CVTSI2SD __m128d _mm_cvtsi64_sd(__m128d s, __int64 a);
CVTSI2SD __m128d_mm_cvtsi32_sd(__m128d a, int b)

SIMD Floating-Point Exceptions
Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3 if W1, else Type 5.
EVEX-encoded instructions, see Exceptions Type E3NF if W1, else Type E10NF.






platform: x86_64
mnem: CVTSI2SS
description:
CVTSI2SS-Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
 Opcode/                                         Op /     64/32         CPUID         Description
 Instruction                                     En       bit Mode      Feature
                                                          Support       Flag
 F3 0F 2A /r                                     RM       V/V           SSE           Convert one signed doubleword integer from r/m32
 CVTSI2SS xmm1, r/m32                                                                 to one single-precision floating-point value in xmm1.
 F3 REX.W 0F 2A /r                               RM       V/N.E.        SSE           Convert one signed quadword integer from r/m64
 CVTSI2SS xmm1, r/m64                                                                 to one single-precision floating-point value in xmm1.
 VEX.NDS.128.F3.0F.W0 2A /r                      RVM      V/V           AVX           Convert one signed doubleword integer from r/m32
 VCVTSI2SS xmm1, xmm2, r/m32                                                          to one single-precision floating-point value in xmm1.
 VEX.NDS.128.F3.0F.W1 2A /r                      RVM      V/N.E.1       AVX           Convert one signed quadword integer from r/m64
 VCVTSI2SS xmm1, xmm2, r/m64                                                          to one single-precision floating-point value in xmm1.
 EVEX.NDS.LIG.F3.0F.W0 2A /r                     T1S      V/V           AVX512F       Convert one signed doubleword integer from r/m32
 VCVTSI2SS xmm1, xmm2, r/m32{er}                                                      to one single-precision floating-point value in xmm1.
 EVEX.NDS.LIG.F3.0F.W1 2A /r                     T1S      V/N.E.1       AVX512F       Convert one signed quadword integer from r/m64
 VCVTSI2SS xmm1, xmm2, r/m64{er}                                                      to one single-precision floating-point value in xmm1.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                      Instruction Operand Encoding
       Op/En                 Operand 1                      Operand 2                    Operand 3                     Operand 4
        RM                 ModRM:reg (w)                  ModRM:r/m (r)                      NA                            NA
       RVM                 ModRM:reg (w)                     VEX.vvvv                  ModRM:r/m (r)                       NA
        T1S                ModRM:reg (w)                    EVEX.vvvv                  ModRM:r/m (r)                       NA

Description
Converts a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the "convert-from"
source operand to a single-precision floating-point value in the destination operand (first operand). The "convert-
from" source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand, and the upper three doublewords
are left unchanged. When a conversion is inexact, the value returned is rounded according to the rounding control
bits in the MXCSR register or the embedded rounding control bits.
128-bit Legacy SSE version: In 64-bit mode, Use of the REX.W prefix promotes the instruction to use 64-bit input
value. The "convert-from" source operand (the second operand) is a general-purpose register or memory location.
Bits (MAX_VL-1:32) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: The "convert-from" source operand (the third operand) can be a general-
purpose register or a memory location. The first source and destination operands are XMM registers. Bits (127:32)
of the XMM register destination are copied from corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
EVEX encoded version: the converted result in written to the low doubleword element of the destination under the
writemask.
Software should ensure VCVTSI2SS is encoded with VEX.L=0. Encoding VCVTSI2SS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VCVTSI2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
    DEST[31:0] <- Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VCVTSI2SS (VEX.128 encoded version)
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

CVTSI2SS (128-bit Legacy SSE version)
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
    DEST[31:0] <-Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSI2SS __m128 _mm_cvti32_ss(__m128 s, int a);
VCVTSI2SS __m128 _mm_cvt_roundi32_ss(__m128 s, int a, int r);
VCVTSI2SS __m128 _mm_cvti64_ss(__m128 s, __int64 a);
VCVTSI2SS __m128 _mm_cvt_roundi64_ss(__m128 s, __int64 a, int r);
CVTSI2SS __m128 _mm_cvtsi64_ss(__m128 s, __int64 a);
CVTSI2SS __m128 _mm_cvtsi32_ss(__m128 a, int b);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: CVTSS2SD
description:
CVTSS2SD-Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision
Floating-Point Value
 Opcode/                                      Op /    64/32          CPUID          Description
 Instruction                                  En      bit Mode       Feature
                                                      Support        Flag
 F3 0F 5A /r                                  RM      V/V            SSE2           Convert one single-precision floating-point value in
 CVTSS2SD xmm1, xmm2/m32                                                            xmm2/m32 to one double-precision floating-point value
                                                                                    in xmm1.
 VEX.NDS.128.F3.0F.WIG 5A /r                  RVM      V/V           AVX            Convert one single-precision floating-point value in
 VCVTSS2SD xmm1, xmm2,                                                              xmm3/m32 to one double-precision floating-point value
 xmm3/m32                                                                           and merge with high bits of xmm2.
 EVEX.NDS.LIG.F3.0F.W0 5A /r                  T1S     V/V            AVX512F        Convert one single-precision floating-point value in
 VCVTSS2SD xmm1 {k1}{z}, xmm2,                                                      xmm3/m32 to one double-precision floating-point value
 xmm3/m32{sae}                                                                      and merge with high bits of xmm2 under writemask k1.



                                                      Instruction Operand Encoding
       Op/En                  Operand 1                       Operand 2                      Operand 3                      Operand 4
        RM                  ModRM:reg (w)                    ModRM:r/m (r)                        NA                           NA
        RVM                 ModRM:reg (w)                      VEX.vvvv                    ModRM:r/m (r)                       NA
        T1S                 ModRM:reg (w)                     EVEX.vvvv                    ModRM:r/m (r)                       NA

Description
Converts a single-precision floating-point value in the "convert-from" source operand to a double-precision
floating-point value in the destination operand. When the "convert-from" source operand is an XMM register, the
single-precision floating-point value is contained in the low doubleword of the register. The result is stored in the
low quadword of the destination operand.
128-bit Legacy SSE version: The "convert-from" source operand (the second operand) is an XMM register or
memory location. Bits (MAX_VL-1:64) of the corresponding destination register remain unchanged. The destina-
tion operand is an XMM register.
VEX.128 and EVEX encoded versions: The "convert-from" source operand (the third operand) can be an XMM
register or a 32-bit memory location. The first source and destination operands are XMM registers. Bits (127:64) of
the XMM register destination are copied from the corresponding bits in the first source operand. Bits (MAX_VL-
1:128) of the destination register are zeroed.
Software should ensure VCVTSS2SD is encoded with VEX.L=0. Encoding VCVTSS2SD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
VCVTSS2SD (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0]);
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] = 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





VCVTSS2SD (VEX.128 encoded version)
DEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC2[31:0])
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

CVTSS2SD (128-bit Legacy SSE version)
DEST[63:0] <-Convert_Single_Precision_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SD __m128d _mm_cvt_roundss_sd(__m128d a, __m128 b, int r);
VCVTSS2SD __m128d _mm_mask_cvt_roundss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b, int r);
VCVTSS2SD __m128d _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128d a, __m128 a, int r);
VCVTSS2SD __m128d _mm_mask_cvtss_sd(__m128d s, __mmask8 m, __m128d a,__m128 b);
VCVTSS2SD __m128d _mm_maskz_cvtss_sd(__mmask8 m, __m128d a,__m128 b);
CVTSS2SD __m128d_mm_cvtss_sd(__m128d a, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: CVTSS2SI
description:
CVTSS2SI-Convert Scalar Single-Precision Floating-Point Value to Doubleword Integer
 Opcode/                                    Op /     64/32          CPUID         Description
 Instruction                                En       bit Mode       Feature
                                                     Support        Flag
 F3 0F 2D /r                                RM       V/V            SSE           Convert one single-precision floating-point value from
 CVTSS2SI r32, xmm1/m32                                                           xmm1/m32 to one signed doubleword integer in r32.
 F3 REX.W 0F 2D /r                          RM       V/N.E.         SSE           Convert one single-precision floating-point value from
 CVTSS2SI r64, xmm1/m32                                                           xmm1/m32 to one signed quadword integer in r64.
 VEX.128.F3.0F.W0 2D /r                     RM       V/V            AVX           Convert one single-precision floating-point value from
 VCVTSS2SI r32, xmm1/m32                                                          xmm1/m32 to one signed doubleword integer in r32.
 VEX.128.F3.0F.W1 2D /r                     RM       V/N.E.1        AVX           Convert one single-precision floating-point value from
 VCVTSS2SI r64, xmm1/m32                                                          xmm1/m32 to one signed quadword integer in r64.
 EVEX.LIG.F3.0F.W0 2D /r                    T1F      V/V            AVX512F       Convert one single-precision floating-point value from
 VCVTSS2SI r32, xmm1/m32{er}                                                      xmm1/m32 to one signed doubleword integer in r32.
 EVEX.LIG.F3.0F.W1 2D /r                    T1F      V/N.E.1        AVX512F       Convert one single-precision floating-point value from
 VCVTSS2SI r64, xmm1/m32{er}                                                      xmm1/m32 to one signed quadword integer in r64.
NOTES:
1. VEX.W1/EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                     Instruction Operand Encoding
       Op/En                  Operand 1                        Operand 2                   Operand 3                    Operand 4
        RM                  ModRM:reg (w)                     ModRM:r/m (r)                     NA                          NA
        T1F                 ModRM:reg (w)                     ModRM:r/m (r)                     NA                          NA

Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed double-
word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a memory location. The destination operand is a general-purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to produce 64-bit data.
See the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTSS2SI is encoded with VEX.L=0. Encoding VCVTSS2SI with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VCVTSS2SI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;

(V)CVTSS2SI (Legacy and VEX.128 encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
    DEST[63:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
ELSE
    DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2SI int _mm_cvtss_i32( __m128 a);
VCVTSS2SI int _mm_cvt_roundss_i32( __m128 a, int r);
VCVTSS2SI __int64 _mm_cvtss_i64( __m128 a);
VCVTSS2SI __int64 _mm_cvt_roundss_i64( __m128 a, int r);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD                   If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: CVTTPD2DQ
description:
CVTTPD2DQ-Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Doubleword Integers
 Opcode/                                    Op /    64/32         CPUID          Description
 Instruction                                En      bit Mode      Feature
                                                    Support       Flag
 66 0F E6 /r                                RM      V/V           SSE2           Convert two packed double-precision floating-point
 CVTTPD2DQ xmm1, xmm2/m128                                                       values in xmm2/mem to two signed doubleword
                                                                                 integers in xmm1 using truncation.
 VEX.128.66.0F.WIG E6 /r                    RM      V/V           AVX            Convert two packed double-precision floating-point
 VCVTTPD2DQ xmm1, xmm2/m128                                                      values in xmm2/mem to two signed doubleword
                                                                                 integers in xmm1 using truncation.
 VEX.256.66.0F.WIG E6 /r                    RM      V/V           AVX            Convert four packed double-precision floating-point
 VCVTTPD2DQ xmm1, ymm2/m256                                                      values in ymm2/mem to four signed doubleword
                                                                                 integers in xmm1 using truncation.
 EVEX.128.66.0F.W1 E6 /r                    FV      V/V           AVX512VL       Convert two packed double-precision floating-point
 VCVTTPD2DQ xmm1 {k1}{z},                                         AVX512F        values in xmm2/m128/m64bcst to two signed
 xmm2/m128/m64bcst                                                               doubleword integers in xmm1 using truncation subject
                                                                                 to writemask k1.
 EVEX.256.66.0F.W1 E6 /r                    FV      V/V           AVX512VL       Convert four packed double-precision floating-point
 VCVTTPD2DQ xmm1 {k1}{z},                                         AVX512F        values in ymm2/m256/m64bcst to four signed
 ymm2/m256/m64bcst                                                               doubleword integers in xmm1 using truncation subject
                                                                                 to writemask k1.
 EVEX.512.66.0F.W1 E6 /r                    FV      V/V           AVX512F        Convert eight packed double-precision floating-point
 VCVTTPD2DQ ymm1 {k1}{z},                                                        values in zmm2/m512/m64bcst to eight signed
 zmm2/m512/m64bcst{sae}                                                          doubleword integers in ymm1 using truncation subject
                                                                                 to writemask k1.



                                                    Instruction Operand Encoding
      Op/En                Operand 1                      Operand 2                    Operand 3                   Operand 4
        RM               ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA
        FV               ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA

Description
Converts two, four or eight packed double-precision floating-point values in the source operand (second operand)
to two, four or eight packed signed doubleword integers in the destination operand (first operand).
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of
the corresponding destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:64) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.



                SRC        X3                     X2                  X1                  X0




                DEST                    0                       X3         X2       X1         X0




                                 Figure 3-15. VCVTTPD2DQ (VEX.256 encoded version)


Operation
VCVTTPD2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





VCVTTPD2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[k+63:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

VCVTTPD2DQ (VEX.256 encoded version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[95:64] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[191:128])
DEST[127:96] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[255:192)
DEST[MAX_VL-1:128]<-0

VCVTTPD2DQ (VEX.128 encoded version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[MAX_VL-1:64]<-0

CVTTPD2DQ (128-bit Legacy SSE version)
DEST[31:0] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0])
DEST[63:32] <-Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[127:64])
DEST[127:64] <-0
DEST[MAX_VL-1:128] (unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2DQ __m256i _mm512_cvttpd_epi32( __m512d a);
VCVTTPD2DQ __m256i _mm512_mask_cvttpd_epi32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_maskz_cvttpd_epi32( __mmask8 k, __m512d a);
VCVTTPD2DQ __m256i _mm512_cvtt_roundpd_epi32( __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_mask_cvtt_roundpd_epi32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m256i _mm512_maskz_cvtt_roundpd_epi32( __mmask8 k, __m512d a, int sae);
VCVTTPD2DQ __m128i _mm256_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm256_maskz_cvttpd_epi32( __mmask8 k, __m256d a);
VCVTTPD2DQ __m128i _mm_mask_cvttpd_epi32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm_maskz_cvttpd_epi32( __mmask8 k, __m128d a);
VCVTTPD2DQ __m128i _mm256_cvttpd_epi32 (__m256d src);
CVTTPD2DQ __m128i _mm_cvttpd_epi32 (__m128d src);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2;
EVEX-encoded instructions, see Exceptions Type E2.
#UD                  If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTTPD2PI
description:
CVTTPD2PI-Convert with Truncation Packed Double-Precision FP Values to Packed Dword
Integers
 Opcode/                                                  Op/   64-Bit       Compat/ Description
 Instruction                                              En    Mode         Leg Mode
 66 0F 2C /r                                              RM    Valid        Valid        Convert two packer double-precision floating-
 CVTTPD2PI mm, xmm/m128                                                                   point values from xmm/m128 to two packed
                                                                                          signed doubleword integers in mm using
                                                                                          truncation.



                                                   Instruction Operand Encoding
   Op/En              Operand 1                        Operand 2                      Operand 3                     Operand 4
    RM              ModRM:reg (w)                    ModRM:r/m (r)                        NA                           NA

Description
Converts two packed double-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 128-bit memory location. The destination operand is an MMX technology register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPD2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer32_Truncate(SRC[63:0]);
DEST[63:32] <- Convert_Double_Precision_Floating_Point_To_Integer32_
               Truncate(SRC[127:64]);

Intel C/C++ Compiler Intrinsic Equivalent
CVTTPD1PI:       __m64 _mm_cvttpd_pi32(__m128d a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Mode Exceptions
See Table 22-4, "Exception Conditions for Legacy SIMD/MMX Instructions with FP Exception and 16-Byte Align-
ment," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTTPS2DQ
description:
CVTTPS2DQ-Convert with Truncation Packed Single-Precision Floating-Point Values to Packed
Signed Doubleword Integer Values
 Opcode/                                 Op /    64/32         CPUID          Description
 Instruction                             En      bit Mode      Feature
                                                 Support       Flag
 F3 0F 5B /r                             RM      V/V           SSE2           Convert four packed single-precision floating-point
 CVTTPS2DQ xmm1, xmm2/m128                                                    values from xmm2/mem to four packed signed
                                                                              doubleword values in xmm1 using truncation.
 VEX.128.F3.0F.WIG 5B /r                 RM      V/V           AVX            Convert four packed single-precision floating-point
 VCVTTPS2DQ xmm1, xmm2/m128                                                   values from xmm2/mem to four packed signed
                                                                              doubleword values in xmm1 using truncation.
 VEX.256.F3.0F.WIG 5B /r                 RM      V/V           AVX            Convert eight packed single-precision floating-point
 VCVTTPS2DQ ymm1, ymm2/m256                                                   values from ymm2/mem to eight packed signed
                                                                              doubleword values in ymm1 using truncation.
 EVEX.128.F3.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert four packed single precision floating-point
 VCVTTPS2DQ xmm1 {k1}{z},                                      AVX512F        values from xmm2/m128/m32bcst to four packed
 xmm2/m128/m32bcst                                                            signed doubleword values in xmm1 using truncation
                                                                              subject to writemask k1.
 EVEX.256.F3.0F.W0 5B /r                 FV      V/V           AVX512VL       Convert eight packed single precision floating-point
 VCVTTPS2DQ ymm1 {k1}{z},                                      AVX512F        values from ymm2/m256/m32bcst to eight packed
 ymm2/m256/m32bcst                                                            signed doubleword values in ymm1 using truncation
                                                                              subject to writemask k1.
 EVEX.512.F3.0F.W0 5B /r                 FV      V/V           AVX512F        Convert sixteen packed single-precision floating-point
 VCVTTPS2DQ zmm1 {k1}{z},                                                     values from zmm2/m512/m32bcst to sixteen packed
 zmm2/m512/m32bcst {sae}                                                      signed doubleword values in zmm1 using truncation
                                                                              subject to writemask k1.



                                                Instruction Operand Encoding
     Op/En            Operand 1                     Operand 2                       Operand 3                       Operand 4
      RM            ModRM:reg (w)                  ModRM:r/m (r)                        NA                              NA
      FV            ModRM:reg (w)                  ModRM:r/m (r)                        NA                              NA

Description
Converts four, eight or sixteen packed single-precision floating-point values in the source operand to four, eight or
sixteen signed doubleword integers in the destination operand.
When a conversion is inexact, a truncated (round toward zero) value is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
VEX.256 encoded version: The source operand is a YMM register or 256- bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: The source operand is an XMM register or 128- bit memory location. The destination
operand is a XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The source operand is an XMM register or 128- bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.




Operation
VCVTTPS2DQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTTPS2DQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO 15
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTTPS2DQ (VEX.256 encoded version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96)
DEST[159:128] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[159:128])
DEST[191:160] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[191:160])
DEST[223:192] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[223:192])
DEST[255:224] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[255:224])



VCVTTPS2DQ (VEX.128 encoded version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] <-0

CVTTPS2DQ (128-bit Legacy SSE version)
DEST[31:0] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0])
DEST[63:32] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32])
DEST[95:64] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[95:64])
DEST[127:96] <-Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[127:96])
DEST[MAX_VL-1:128] (unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2DQ __m512i _mm512_cvttps_epi32( __m512 a);
VCVTTPS2DQ __m512i _mm512_mask_cvttps_epi32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_maskz_cvttps_epi32( __mmask16 k, __m512 a);
VCVTTPS2DQ __m512i _mm512_cvtt_roundps_epi32( __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_mask_cvtt_roundps_epi32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m512i _mm512_maskz_cvtt_roundps_epi32( __mmask16 k, __m512 a, int sae);
VCVTTPS2DQ __m256i _mm256_mask_cvttps_epi32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2DQ __m256i _mm256_maskz_cvttps_epi32( __mmask8 k, __m256 a);
VCVTTPS2DQ __m128i _mm_mask_cvttps_epi32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2DQ __m128i _mm_maskz_cvttps_epi32( __mmask8 k, __m128 a);
VCVTTPS2DQ __m256i _mm256_cvttps_epi32 (__m256 a)
CVTTPS2DQ __m128i _mm_cvttps_epi32 (__m128 a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2; additionally
EVEX-encoded instructions, see Exceptions Type E2.
#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: CVTTPS2PI
description:
CVTTPS2PI-Convert with Truncation Packed Single-Precision FP Values to Packed Dword
Integers
 Opcode/                                                   Op/    64-Bit       Compat/ Description
 Instruction                                               En     Mode         Leg Mode
 0F 2C /r                                                  RM     Valid        Valid       Convert two single-precision floating-point
 CVTTPS2PI mm, xmm/m64                                                                     values from xmm/m64 to two signed
                                                                                           doubleword signed integers in mm using
                                                                                           truncation.



                                                    Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                        Operand 3                     Operand 4
    RM              ModRM:reg (w)                   ModRM:r/m (r)                          NA                            NA

Description
Converts two packed single-precision floating-point values in the source operand (second operand) to two packed
signed doubleword integers in the destination operand (first operand). The source operand can be an XMM register
or a 64-bit memory location. The destination operand is an MMX technology register. When the source operand is
an XMM register, the two single-precision floating-point values are contained in the low quadword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger
than the maximum signed doubleword integer, the floating-point invalid exception is raised, and if this exception is
masked, the indefinite integer value (80000000H) is returned.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the CVTTPS2PI instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
DEST[63:32] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[63:32]);

Intel C/C++ Compiler Intrinsic Equivalent
CVTTPS2PI:        __m64 _mm_cvttps_pi32(__m128 a)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
See Table 22-5, "Exception Conditions for Legacy SIMD/MMX Instructions with XMM and FP Exception," in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: CVTTSD2SI
description:
CVTTSD2SI-Convert with Truncation Scalar Double-Precision Floating-Point Value to Signed
Integer
 Opcode/                              Op /    64/32         CPUID         Description
 Instruction                          En      bit Mode      Feature
                                              Support       Flag
 F2 0F 2C /r                          RM      V/V           SSE2          Convert one double-precision floating-point value from
 CVTTSD2SI r32, xmm1/m64                                                  xmm1/m64 to one signed doubleword integer in r32
                                                                          using truncation.
 F2 REX.W 0F 2C /r                    RM      V/N.E.        SSE2          Convert one double-precision floating-point value from
 CVTTSD2SI r64, xmm1/m64                                                  xmm1/m64 to one signed quadword integer in r64
                                                                          using truncation.
 VEX.128.F2.0F.W0 2C /r               RM      V/V           AVX           Convert one double-precision floating-point value from
 VCVTTSD2SI r32, xmm1/m64                                                 xmm1/m64 to one signed doubleword integer in r32
                                                                          using truncation.
 VEX.128.F2.0F.W1 2C /r               T1F     V/N.E.1       AVX           Convert one double-precision floating-point value from
 VCVTTSD2SI r64, xmm1/m64                                                 xmm1/m64 to one signed quadword integer in r64
                                                                          using truncation.
 EVEX.LIG.F2.0F.W0 2C /r              T1F     V/V           AVX512F       Convert one double-precision floating-point value from
 VCVTTSD2SI r32, xmm1/m64{sae}                                            xmm1/m64 to one signed doubleword integer in r32
                                                                          using truncation.
 EVEX.LIG.F2.0F.W1 2C /r              T1F     V/N.E.1       AVX512F       Convert one double-precision floating-point value from
 VCVTTSD2SI r64, xmm1/m64{sae}                                            xmm1/m64 to one signed quadword integer in r64
                                                                          using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-
  sion is used.



                                             Instruction Operand Encoding
     Op/En            Operand 1                 Operand 2                       Operand 3                       Operand 4
      RM            ModRM:reg (w)              ModRM:r/m (r)                        NA                              NA
      T1F           ModRM:reg (w)              ModRM:r/m (r)                        NA                              NA

Description
Converts a double-precision floating-point value in the source operand (the second operand) to a signed double-
word integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand).
The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general
purpose register. When the source operand is an XMM register, the double-precision floating-point value is
contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register.
If a converted result exceeds the range limits of signed doubleword integer (in non-64-bit modes or 64-bit mode
with REX.W/VEX.W/EVEX.W=0), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000H) is returned.
If a converted result exceeds the range limits of signed quadword integer (in 64-bit mode and
REX.W/VEX.W/EVEX.W = 1), the floating-point invalid exception is raised, and if this exception is masked, the
indefinite integer value (80000000_00000000H) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.




Software should ensure VCVTTSD2SI is encoded with VEX.L=0. Encoding VCVTTSD2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.

Operation
(V)CVTTSD2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
    DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
ELSE
    DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_Integer_Truncate(SRC[63:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2SI int _mm_cvttsd_i32( __m128d a);
VCVTTSD2SI int _mm_cvtt_roundsd_i32( __m128d a, int sae);
VCVTTSD2SI __int64 _mm_cvttsd_i64( __m128d a);
VCVTTSD2SI __int64 _mm_cvtt_roundsd_i64( __m128d a, int sae);
CVTTSD2SI int _mm_cvttsd_si32( __m128d a);
CVTTSD2SI __int64 _mm_cvttsd_si64( __m128d a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD                       If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: CVTTSS2SI
description:
CVTTSS2SI-Convert with Truncation Scalar Single-Precision Floating-Point Value to Integer
 Opcode/                              Op /    64/32        CPUID          Description
 Instruction                          En      bit Mode     Feature
                                              Support      Flag
 F3 0F 2C /r                          RM      V/V          SSE            Convert one single-precision floating-point value from
 CVTTSS2SI r32, xmm1/m32                                                  xmm1/m32 to one signed doubleword integer in r32
                                                                          using truncation.
 F3 REX.W 0F 2C /r                    RM      V/N.E.       SSE            Convert one single-precision floating-point value from
 CVTTSS2SI r64, xmm1/m32                                                  xmm1/m32 to one signed quadword integer in r64
                                                                          using truncation.
 VEX.128.F3.0F.W0 2C /r               RM      V/V          AVX            Convert one single-precision floating-point value from
 VCVTTSS2SI r32, xmm1/m32                                                 xmm1/m32 to one signed doubleword integer in r32
                                                                          using truncation.
 VEX.128.F3.0F.W1 2C /r               RM      V/N.E.1      AVX            Convert one single-precision floating-point value from
 VCVTTSS2SI r64, xmm1/m32                                                 xmm1/m32 to one signed quadword integer in r64
                                                                          using truncation.
 EVEX.LIG.F3.0F.W0 2C /r              T1F     V/V          AVX512F        Convert one single-precision floating-point value from
 VCVTTSS2SI r32, xmm1/m32{sae}                                            xmm1/m32 to one signed doubleword integer in r32
                                                                          using truncation.
 EVEX.LIG.F3.0F.W1 2C /r              T1F     V/N.E.1      AVX512F        Convert one single-precision floating-point value from
 VCVTTSS2SI r64, xmm1/m32{sae}                                            xmm1/m32 to one signed quadword integer in r64
                                                                          using truncation.
NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-
  sion is used.



                                             Instruction Operand Encoding
      Op/En             Operand 1                   Operand 2                     Operand 3                      Operand 4
       RM             ModRM:reg (w)             ModRM:r/m (r)                         NA                             NA
       T1F            ModRM:reg (w)             ModRM:r/m (r)                         NA                             NA

Description
Converts a single-precision floating-point value in the source operand (the second operand) to a signed doubleword
integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The
source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose
register. When the source operand is an XMM register, the single-precision floating-point value is contained in the
low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than
the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked,
the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See
the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may
encounter unpredictable behavior across different processor generations.





Operation
(V)CVTTSS2SI (All versions)
IF 64-Bit Mode and OperandSize = 64
THEN
    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
ELSE
    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2SI int _mm_cvttss_i32( __m128 a);
VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);
VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);
VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);
CVTTSS2SI int _mm_cvttss_si32( __m128 a);
CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
See Exceptions Type 3; additionally
#UD                       If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: CWD
description:
CWD/CDQ/CQO-Convert Word to Doubleword/Convert Doubleword to Quadword
Opcode                    Instruction                 Op/    64-Bit     Compat/ Description
                                                      En     Mode       Leg Mode
99                        CWD                         NP     Valid      Valid       DX:AX <- sign-extend of AX.
99                        CDQ                         NP     Valid      Valid       EDX:EAX <- sign-extend of EAX.
REX.W + 99                CQO                         NP     Valid      N.E.        RDX:RAX<- sign-extend of RAX.



                                                Instruction Operand Encoding
     Op/En             Operand 1                     Operand 2                   Operand 3                    Operand 4
      NP                  NA                            NA                           NA                          NA

Description
Doubles the size of the operand in register AX, EAX, or RAX (depending on the operand size) by means of sign
extension and stores the result in registers DX:AX, EDX:EAX, or RDX:RAX, respectively. The CWD instruction
copies the sign (bit 15) of the value in the AX register into every bit position in the DX register. The CDQ instruction
copies the sign (bit 31) of the value in the EAX register into every bit position in the EDX register. The CQO instruc-
tion (available in 64-bit mode only) copies the sign (bit 63) of the value in the RAX register into every bit position
in the RDX register.
The CWD instruction can be used to produce a doubleword dividend from a word before word division. The CDQ
instruction can be used to produce a quadword dividend from a doubleword before doubleword division. The CQO
instruction can be used to produce a double quadword dividend from a quadword before a quadword division.
The CWD and CDQ mnemonics reference the same opcode. The CWD instruction is intended for use when the
operand-size attribute is 16 and the CDQ instruction for when the operand-size attribute is 32. Some assemblers
may force the operand size to 16 when CWD is used and to 32 when CDQ is used. Others may treat these
mnemonics as synonyms (CWD/CDQ) and use the current setting of the operand-size attribute to determine the
size of values to be converted, regardless of the mnemonic used.
In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. The CQO mnemonics reference the same
opcode as CWD/CDQ. See the summary chart at the beginning of this section for encoding data and limits.

Operation

IF OperandSize = 16 (* CWD instruction *)
    THEN
        DX <- SignExtend(AX);
    ELSE IF OperandSize = 32 (* CDQ instruction *)
        EDX <- SignExtend(EAX); FI;
    ELSE IF 64-Bit Mode and OperandSize = 64 (* CQO instruction*)
        RDX <- SignExtend(RAX); FI;
FI;

Flags Affected
None

Exceptions (All Operating Modes)
#UD                    If the LOCK prefix is used.






platform: x86_64
mnem: DAA
description:
DAA-Decimal Adjust AL after Addition
 Opcode                     Instruction                Op/     64-Bit    Compat/ Description
                                                       En      Mode      Leg Mode
 27                         DAA                        NP      Invalid   Valid     Decimal adjust AL after addition.



                                                 Instruction Operand Encoding
      Op/En              Operand 1                    Operand 2                  Operand 3                    Operand 4
       NP                    NA                           NA                        NA                            NA

Description
Adjusts the sum of two packed BCD values to create a packed BCD result. The AL register is the implied source and
destination operand. The DAA instruction is only useful when it follows an ADD instruction that adds (binary addi-
tion) two 2-digit, packed BCD values and stores a byte result in the AL register. The DAA instruction then adjusts
the contents of the AL register to contain the correct 2-digit, packed BCD result. If a decimal carry is detected, the
CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation
IF 64-Bit Mode
    THEN
         #UD;
    ELSE
         old_AL <- AL;
         old_CF <- CF;
         CF <- 0;
         IF (((AL AND 0FH) > 9) or AF = 1)
                THEN
                    AL <- AL + 6;
                    CF <- old_CF or (Carry from AL <- AL + 6);
                    AF <- 1;
                ELSE
                    AF <- 0;
         FI;
         IF ((old_AL > 99H) or (old_CF = 1))
               THEN
                    AL <- AL + 60H;
                    CF <- 1;
               ELSE
                    CF <- 0;
         FI;
FI;

Example
ADD      AL, BL   Before: AL=79H BL=35H EFLAGS(OSZAPC)=XXXXXX
                  After: AL=AEH BL=35H EFLAGS(0SZAPC)=110000
DAA               Before: AL=AEH BL=35H EFLAGS(OSZAPC)=110000
                  After: AL=14H BL=35H EFLAGS(0SZAPC)=X00111
DAA               Before: AL=2EH BL=35H EFLAGS(OSZAPC)=110000
                  After: AL=34H BL=35H EFLAGS(0SZAPC)=X00101





Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal carry in either digit of the result (see
the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is undefined.

Protected Mode Exceptions
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                  If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#UD                  If the LOCK prefix is used.

Compatibility Mode Exceptions
#UD                  If the LOCK prefix is used.

64-Bit Mode Exceptions
#UD                  If in 64-bit mode.






platform: x86_64
mnem: DAS
description:
DAS-Decimal Adjust AL after Subtraction
 Opcode                     Instruction               Op/      64-Bit    Compat/ Description
                                                      En       Mode      Leg Mode
 2F                         DAS                       NP       Invalid   Valid      Decimal adjust AL after subtraction.



                                                Instruction Operand Encoding
      Op/En             Operand 1                  Operand 2                     Operand 3                    Operand 4
       NP                   NA                         NA                           NA                            NA

Description
Adjusts the result of the subtraction of two packed BCD values to create a packed BCD result. The AL register is the
implied source and destination operand. The DAS instruction is only useful when it follows a SUB instruction that
subtracts (binary subtraction) one 2-digit, packed BCD value from another and stores a byte result in the AL
register. The DAS instruction then adjusts the contents of the AL register to contain the correct 2-digit, packed BCD
result. If a decimal borrow is detected, the CF and AF flags are set accordingly.
This instruction executes as described above in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation
IF 64-Bit Mode
    THEN
         #UD;
    ELSE
         old_AL <- AL;
         old_CF <- CF;
         CF <- 0;
         IF (((AL AND 0FH) > 9) or AF = 1)
               THEN
                   AL <- AL - 6;
                   CF <- old_CF or (Borrow from AL <- AL - 6);
                   AF <- 1;
               ELSE
                   AF <- 0;
         FI;
         IF ((old_AL > 99H) or (old_CF = 1))
                THEN
                   AL <- AL - 60H;
                   CF <- 1;
         FI;
FI;

Example
SUB      AL, BL   Before: AL = 35H, BL = 47H, EFLAGS(OSZAPC) = XXXXXX
                  After: AL = EEH, BL = 47H, EFLAGS(0SZAPC) = 010111
DAA               Before: AL = EEH, BL = 47H, EFLAGS(OSZAPC) = 010111
                  After: AL = 88H, BL = 47H, EFLAGS(0SZAPC) = X10111

Flags Affected
The CF and AF flags are set if the adjustment of the value results in a decimal borrow in either digit of the result
(see the "Operation" section above). The SF, ZF, and PF flags are set according to the result. The OF flag is unde-
fined.



Protected Mode Exceptions
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
#UD                 If the LOCK prefix is used.

64-Bit Mode Exceptions
#UD                 If in 64-bit mode.






platform: x86_64
mnem: DEC
description:
DEC-Decrement by 1
 Opcode                    Instruction                  Op/      64-Bit    Compat/ Description
                                                        En       Mode      Leg Mode
 FE /1                     DEC r/m8                     M        Valid     Valid        Decrement r/m8 by 1.
                                      *
 REX + FE /1               DEC r/m8                     M        Valid     N.E.         Decrement r/m8 by 1.
 FF /1                     DEC r/m16                    M        Valid     Valid        Decrement r/m16 by 1.
 FF /1                     DEC r/m32                    M        Valid     Valid        Decrement r/m32 by 1.
 REX.W + FF /1             DEC r/m64                    M        Valid     N.E.         Decrement r/m64 by 1.
 48+rw                     DEC r16                      O        N.E.      Valid        Decrement r16 by 1.
 48+rd                     DEC r32                      O        N.E.      Valid        Decrement r32 by 1.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
    Op/En               Operand 1                       Operand 2                     Operand 3                    Operand 4
         M           ModRM:r/m (r, w)                       NA                            NA                           NA
         O           opcode + rd (r, w)                     NA                            NA                           NA

Description
Subtracts 1 from the destination operand, while preserving the state of the CF flag. The destination operand can be
a register or a memory location. This instruction allows a loop counter to be updated without disturbing the CF flag.
(To perform a decrement operation that updates the CF flag, use a SUB instruction with an immediate operand of
1.)
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, DEC r16 and DEC r32 are not encodable (because opcodes 48H through 4FH are REX prefixes).
Otherwise, the instruction's 64-bit mode default operation size is 32 bits. Use of the REX.R prefix permits access to
additional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
See the summary chart at the beginning of this section for encoding data and limits.

Operation
DEST <- DEST - 1;

Flags Affected
The CF flag is not affected. The OF, SF, ZF, AF, and PF flags are set according to the result.

Protected Mode Exceptions
#GP(0)                  If the destination operand is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.





Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: DIV
description:
DIV-Unsigned Divide
Opcode                     Instruction                  Op/    64-Bit      Compat/ Description
                                                        En     Mode        Leg Mode
F6 /6                      DIV r/m8                     M      Valid       Valid       Unsigned divide AX by r/m8, with result
                                                                                       stored in AL <- Quotient, AH <- Remainder.
REX + F6 /6                DIV r/m8*                    M      Valid       N.E.        Unsigned divide AX by r/m8, with result
                                                                                       stored in AL <- Quotient, AH <- Remainder.
F7 /6                      DIV r/m16                    M      Valid       Valid       Unsigned divide DX:AX by r/m16, with result
                                                                                       stored in AX <- Quotient, DX <- Remainder.
F7 /6                      DIV r/m32                    M      Valid       Valid       Unsigned divide EDX:EAX by r/m32, with
                                                                                       result stored in EAX <- Quotient, EDX <-
                                                                                       Remainder.
REX.W + F7 /6              DIV r/m64                    M      Valid       N.E.        Unsigned divide RDX:RAX by r/m64, with
                                                                                       result stored in RAX <- Quotient, RDX <-
                                                                                       Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En                Operand 1                   Operand 2                      Operand 3                      Operand 4
     M                ModRM:r/m (w)                     NA                             NA                             NA

Description
Divides unsigned the value in the AX, DX:AX, EDX:EAX, or RDX:RAX registers (dividend) by the source operand
(divisor) and stores the result in the AX (AH:AL), DX:AX, EDX:EAX, or RDX:RAX registers. The source operand can
be a general-purpose register or a memory location. The action of this instruction depends on the operand size
(dividend/divisor). Division using 64-bit operand is available only in 64-bit mode.
Non-integral results are truncated (chopped) towards 0. The remainder is always less than the divisor in magni-
tude. Overflow is indicated with the #DE (divide error) exception rather than with the CF flag.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. In 64-bit mode when REX.W is
applied, the instruction divides the unsigned value in RDX:RAX by the source operand and stores the quotient in
RAX, the remainder in RDX.
See the summary chart at the beginning of this section for encoding data and limits. See Table 3-15.
                                                    Table 3-15. DIV Action
                                                                                                                  Maximum
 Operand Size                          Dividend         Divisor         Quotient            Remainder             Quotient
 Word/byte                             AX               r/m8            AL                  AH                    255
 Doubleword/word                       DX:AX            r/m16           AX                  DX                    65,535
 Quadword/doubleword                   EDX:EAX          r/m32           EAX                 EDX                   232 - 1
 Doublequadword/                       RDX:RAX          r/m64           RAX                 RDX                   264 - 1
 quadword





Operation
IF SRC = 0
    THEN #DE; FI; (* Divide Error *)
IF OperandSize = 8 (* Word/Byte Operation *)
    THEN
        temp <- AX / SRC;
        IF temp > FFH
             THEN #DE; (* Divide error *)
             ELSE
                  AL <- temp;
                  AH <- AX MOD SRC;
        FI;
    ELSE IF OperandSize = 16 (* Doubleword/word operation *)
        THEN
             temp <- DX:AX / SRC;
             IF temp > FFFFH
                  THEN #DE; (* Divide error *)
             ELSE
                  AX <- temp;
                  DX <- DX:AX MOD SRC;
             FI;
        FI;
    ELSE IF Operandsize = 32 (* Quadword/doubleword operation *)
        THEN
             temp <- EDX:EAX / SRC;
             IF temp > FFFFFFFFH
                  THEN #DE; (* Divide error *)
             ELSE
                  EAX <- temp;
                  EDX <- EDX:EAX MOD SRC;
             FI;
        FI;
    ELSE IF 64-Bit Mode and Operandsize = 64 (* Doublequadword/quadword operation *)
        THEN
             temp <- RDX:RAX / SRC;
             IF temp > FFFFFFFFFFFFFFFFH
                  THEN #DE; (* Divide error *)
             ELSE
                  RAX <- temp;
                  RDX <- RDX:RAX MOD SRC;
             FI;
        FI;
FI;

Flags Affected
The CF, OF, SF, ZF, AF, and PF flags are undefined.





Protected Mode Exceptions
#DE                   If the source operand (divisor) is 0
                      If the quotient is too large for the designated register.
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                      If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.

Real-Address Mode Exceptions
#DE                   If the source operand (divisor) is 0.
                      If the quotient is too large for the designated register.
#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                      If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#UD                   If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#DE                   If the source operand (divisor) is 0.
                      If the quotient is too large for the designated register.
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.
#UD                   If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                If the memory address is in a non-canonical form.
#DE                   If the source operand (divisor) is 0
                      If the quotient is too large for the designated register.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: DIVPD
description:
DIVPD-Divide Packed Double-Precision Floating-Point Values
 Opcode/                              Op /   64/32        CPUID      Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 66 0F 5E /r                          RM     V/V          SSE2       Divide packed double-precision floating-point values
 DIVPD xmm1, xmm2/m128                                               in xmm1 by packed double-precision floating-point
                                                                     values in xmm2/mem.
 VEX.NDS.128.66.0F.WIG 5E /r          RVM    V/V          AVX        Divide packed double-precision floating-point values
 VDIVPD xmm1, xmm2, xmm3/m128                                        in xmm2 by packed double-precision floating-point
                                                                     values in xmm3/mem.
 VEX.NDS.256.66.0F.WIG 5E /r          RVM    V/V          AVX        Divide packed double-precision floating-point values
 VDIVPD ymm1, ymm2, ymm3/m256                                        in ymm2 by packed double-precision floating-point
                                                                     values in ymm3/mem.
 EVEX.NDS.128.66.0F.W1 5E /r          FV     V/V          AVX512VL   Divide packed double-precision floating-point values
 VDIVPD xmm1 {k1}{z}, xmm2,                               AVX512F    in xmm2 by packed double-precision floating-point
 xmm3/m128/m64bcst                                                   values in xmm3/m128/m64bcst and write results to
                                                                     xmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 5E /r          FV     V/V          AVX512VL   Divide packed double-precision floating-point values
 VDIVPD ymm1 {k1}{z}, ymm2,                               AVX512F    in ymm2 by packed double-precision floating-point
 ymm3/m256/m64bcst                                                   values in ymm3/m256/m64bcst and write results to
                                                                     ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 5E /r          FV     V/V          AVX512F    Divide packed double-precision floating-point values
 VDIVPD zmm1 {k1}{z}, zmm2,                                          in zmm2 by packed double-precision FP values in
 zmm3/m512/m64bcst{er}                                               zmm3/m512/m64bcst and write results to zmm1
                                                                     subject to writemask k1.



                                           Instruction Operand Encoding
     Op/En            Operand 1               Operand 2                  Operand 3                       Operand 4
      RM           ModRM:reg (r, w)          ModRM:r/m (r)                   NA                              NA
     RVM            ModRM:reg (w)              VEX.vvvv                ModRM:r/m (r)                         NA
      FV            ModRM:reg (w)             EVEX.vvvv                ModRM:r/m (r)                         NA

Description
Performs a SIMD divide of the double-precision floating-point values in the first source operand by the floating-
point values in the second source operand (the third operand). Results are written to the destination operand (the
first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand (the second operand) is a YMM register. The second source
operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper
bits (MAX_VL-1:256) of the corresponding destination are zeroed.
VEX.128 encoded version: The first source operand (the second operand) is a XMM register. The second source
operand can be a XMM register or a 128-bit memory location. The destination operand is a XMM register. The upper
bits (MAX_VL-1:128) of the corresponding destination are zeroed.
128-bit Legacy SSE version: The second source operand (the second operand) can be an XMM register or an 128-
bit memory location. The destination is the same as the first source operand. The upper bits (MAX_VL-1:128) of the
corresponding destination are unmodified.





Operation
VDIVPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);          ; refer to Table 2-4 in the Intel Architecture Instruction Set Extensions Programming Reference
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- SRC1[i+63:i] / SRC2[63:0]
                    ELSE
                         DEST[i+63:i] <- SRC1[i+63:i] / SRC2[i+63:i]
               FI;
         ELSE
               IF *merging-masking*                    ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                               ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VDIVPD (VEX.256 encoded version)
DEST[63:0] <-SRC1[63:0] / SRC2[63:0]
DEST[127:64] <-SRC1[127:64] / SRC2[127:64]
DEST[191:128] <-SRC1[191:128] / SRC2[191:128]
DEST[255:192] <-SRC1[255:192] / SRC2[255:192]
DEST[MAX_VL-1:256] <-0;

VDIVPD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0] / SRC2[63:0]
DEST[127:64] <-SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] <-0;

DIVPD (128-bit Legacy SSE version)
DEST[63:0] <-SRC1[63:0] / SRC2[63:0]
DEST[127:64] <-SRC1[127:64] / SRC2[127:64]
DEST[MAX_VL-1:128] (Unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VDIVPD __m512d _mm512_div_pd( __m512d a, __m512d b);
VDIVPD __m512d _mm512_mask_div_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VDIVPD __m512d _mm512_maskz_div_pd( __mmask8 k, __m512d a, __m512d b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPD __m512d _mm512_div_round_pd( __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_mask_div_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m512d _mm512_maskz_div_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VDIVPD __m256d _mm256_div_pd (__m256d a, __m256d b);
DIVPD __m128d _mm_div_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: DIVPS
description:
DIVPS-Divide Packed Single-Precision Floating-Point Values
 Opcode/                                          Op /       64/32        CPUID      Description
 Instruction                                      En         bit Mode     Feature
                                                             Support      Flag
 0F 5E /r                                         RM         V/V          SSE        Divide packed single-precision floating-point values
 DIVPS xmm1, xmm2/m128                                                               in xmm1 by packed single-precision floating-point
                                                                                     values in xmm2/mem.
 VEX.NDS.128.0F.WIG 5E /r                         RVM        V/V          AVX        Divide packed single-precision floating-point values
 VDIVPS xmm1, xmm2, xmm3/m128                                                        in xmm2 by packed single-precision floating-point
                                                                                     values in xmm3/mem.
 VEX.NDS.256.0F.WIG 5E /r                         RVM        V/V          AVX        Divide packed single-precision floating-point values
 VDIVPS ymm1, ymm2, ymm3/m256                                                        in ymm2 by packed single-precision floating-point
                                                                                     values in ymm3/mem.
 EVEX.NDS.128.0F.W0 5E /r                         FV         V/V          AVX512VL   Divide packed single-precision floating-point values
 VDIVPS xmm1 {k1}{z}, xmm2,                                               AVX512F    in xmm2 by packed single-precision floating-point
 xmm3/m128/m32bcst                                                                   values in xmm3/m128/m32bcst and write results to
                                                                                     xmm1 subject to writemask k1.
 EVEX.NDS.256.0F.W0 5E /r                         FV         V/V          AVX512VL   Divide packed single-precision floating-point values
 VDIVPS ymm1 {k1}{z}, ymm2,                                               AVX512F    in ymm2 by packed single-precision floating-point
 ymm3/m256/m32bcst                                                                   values in ymm3/m256/m32bcst and write results to
                                                                                     ymm1 subject to writemask k1.
 EVEX.NDS.512.0F.W0 5E /r                         FV         V/V          AVX512F    Divide packed single-precision floating-point values
 VDIVPS zmm1 {k1}{z}, zmm2,                                                          in zmm2 by packed single-precision floating-point
 zmm3/m512/m32bcst{er}                                                               values in zmm3/m512/m32bcst and write results to
                                                                                     zmm1 subject to writemask k1.



                                                       Instruction Operand Encoding
      Op/En                 Operand 1                         Operand 2                  Operand 3                    Operand 4
       RM               ModRM:reg (r, w)                     ModRM:r/m (r)                  NA                            NA
      RVM                ModRM:reg (w)                         VEX.vvvv                ModRM:r/m (r)                      NA
       FV                ModRM:reg (w)                        EVEX.vvvv                ModRM:r/m (r)                      NA

Description
Performs a SIMD divide of the four, eight or sixteen packed single-precision floating-point values in the first source
operand (the second operand) by the four, eight or sixteen packed single-precision floating-point values in the
second source operand (the third operand). Results are written to the destination operand (the first operand).
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.





Operation
VDIVPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC1[i+31:i] / SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC1[i+31:i] / SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                            ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VDIVPS (VEX.256 encoded version)
DEST[31:0] <-SRC1[31:0] / SRC2[31:0]
DEST[63:32] <-SRC1[63:32] / SRC2[63:32]
DEST[95:64] <-SRC1[95:64] / SRC2[95:64]
DEST[127:96] <-SRC1[127:96] / SRC2[127:96]
DEST[159:128] <-SRC1[159:128] / SRC2[159:128]
DEST[191:160]<-SRC1[191:160] / SRC2[191:160]
DEST[223:192] <-SRC1[223:192] / SRC2[223:192]
DEST[255:224] <-SRC1[255:224] / SRC2[255:224].
DEST[MAX_VL-1:256] <-0;

VDIVPS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0] / SRC2[31:0]
DEST[63:32] <-SRC1[63:32] / SRC2[63:32]
DEST[95:64] <-SRC1[95:64] / SRC2[95:64]
DEST[127:96] <-SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] <-0





DIVPS (128-bit Legacy SSE version)
DEST[31:0] <-SRC1[31:0] / SRC2[31:0]
DEST[63:32] <-SRC1[63:32] / SRC2[63:32]
DEST[95:64] <-SRC1[95:64] / SRC2[95:64]
DEST[127:96] <-SRC1[127:96] / SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VDIVPS __m512 _mm512_div_ps( __m512 a, __m512 b);
VDIVPS __m512 _mm512_mask_div_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VDIVPS __m512 _mm512_maskz_div_ps(__mmask16 k, __m512 a, __m512 b);
VDIVPD __m256d _mm256_mask_div_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VDIVPD __m256d _mm256_maskz_div_pd( __mmask8 k, __m256d a, __m256d b);
VDIVPD __m128d _mm_mask_div_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVPD __m128d _mm_maskz_div_pd( __mmask8 k, __m128d a, __m128d b);
VDIVPS __m512 _mm512_div_round_ps( __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_mask_div_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m512 _mm512_maskz_div_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VDIVPS __m256 _mm256_div_ps (__m256 a, __m256 b);
DIVPS __m128 _mm_div_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: DIVSD
description:
DIVSD-Divide Scalar Double-Precision Floating-Point Value
 Opcode/                                Op /     64/32        CPUID     Description
 Instruction                            En       bit Mode     Feature
                                                 Support      Flag
 F2 0F 5E /r                            RM       V/V          SSE2      Divide low double-precision floating-point value in
 DIVSD xmm1, xmm2/m64                                                   xmm1 by low double-precision floating-point value
                                                                        in xmm2/m64.
 VEX.NDS.128.F2.0F.WIG 5E /r            RVM      V/V          AVX       Divide low double-precision floating-point value in
 VDIVSD xmm1, xmm2, xmm3/m64                                            xmm2 by low double-precision floating-point value
                                                                        in xmm3/m64.
 EVEX.NDS.LIG.F2.0F.W1 5E /r            T1S      V/V          AVX512F   Divide low double-precision floating-point value in
 VDIVSD xmm1 {k1}{z}, xmm2,                                             xmm2 by low double-precision floating-point value
 xmm3/m64{er}                                                           in xmm3/m64.



                                              Instruction Operand Encoding
     Op/En             Operand 1                  Operand 2                Operand 3                       Operand 4
       RM           ModRM:reg (r, w)            ModRM:r/m (r)                  NA                              NA
      RVM            ModRM:reg (w)                VEX.vvvv               ModRM:r/m (r)                         NA
      T1S            ModRM:reg (w)               EVEX.vvvv               ModRM:r/m (r)                         NA

Description
Divides the low double-precision floating-point value in the first source operand by the low double-precision
floating-point value in the second source operand, and stores the double-precision floating-point result in the desti-
nation operand. The second source operand can be an XMM register or a 64-bit memory location. The first source
and destination are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:64) of the corresponding ZMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The quadword at bits
127:64 of the destination operand is copied from the corresponding quadword of the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The quadword
element of the destination operand at bits 127:64 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low quadword element of the destination is updated according to the writemask.
Software should ensure VDIVSD is encoded with VEX.L=0. Encoding VDIVSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VDIVSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC1[63:0] / SRC2[63:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VDIVSD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0] / SRC2[63:0]
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

DIVSD (128-bit Legacy SSE version)
DEST[63:0] <-DEST[63:0] / SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VDIVSD __m128d _mm_mask_div_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VDIVSD __m128d _mm_maskz_div_sd( __mmask8 k, __m128d a, __m128d b);
VDIVSD __m128d _mm_div_round_sd( __m128d a, __m128d b, int);
VDIVSD __m128d _mm_mask_div_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VDIVSD __m128d _mm_maskz_div_round_sd( __mmask8 k, __m128d a, __m128d b, int);
DIVSD __m128d _mm_div_sd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: DIVSS
description:
DIVSS-Divide Scalar Single-Precision Floating-Point Values
 Opcode/                                Op /     64/32         CPUID     Description
 Instruction                            En       bit Mode      Feature
                                                 Support       Flag
 F3 0F 5E /r                            RM       V/V           SSE       Divide low single-precision floating-point value in
 DIVSS xmm1, xmm2/m32                                                    xmm1 by low single-precision floating-point value in
                                                                         xmm2/m32.
 VEX.NDS.128.F3.0F.WIG 5E /r            RVM      V/V           AVX       Divide low single-precision floating-point value in
 VDIVSS xmm1, xmm2, xmm3/m32                                             xmm2 by low single-precision floating-point value in
                                                                         xmm3/m32.
 EVEX.NDS.LIG.F3.0F.W0 5E /r            T1S      V/V           AVX512F   Divide low single-precision floating-point value in
 VDIVSS xmm1 {k1}{z}, xmm2,                                              xmm2 by low single-precision floating-point value in
 xmm3/m32{er}                                                            xmm3/m32.



                                               Instruction Operand Encoding
     Op/En             Operand 1                   Operand 2                Operand 3                        Operand 4
      RM            ModRM:reg (r, w)             ModRM:r/m (r)                   NA                              NA
      RVM            ModRM:reg (w)                 VEX.vvvv                ModRM:r/m (r)                         NA
      T1S            ModRM:reg (w)                 EVEX.vvvv               ModRM:r/m (r)                         NA

Description
Divides the low single-precision floating-point value in the first source operand by the low single-precision floating-
point value in the second source operand, and stores the single-precision floating-point result in the destination
operand. The second source operand can be an XMM register or a 32-bit memory location.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three high-order
doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128) of the
destination register are zeroed.
EVEX.128 encoded version: The first source operand is an xmm register encoded by EVEX.vvvv. The doubleword
elements of the destination operand at bits 127:32 are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX version: The low doubleword element of the destination is updated according to the writemask.
Software should ensure VDIVSS is encoded with VEX.L=0. Encoding VDIVSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VDIVSS (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC1[31:0] / SRC2[31:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VDIVSS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0] / SRC2[31:0]
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

DIVSS (128-bit Legacy SSE version)
DEST[31:0] <-DEST[31:0] / SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VDIVSS __m128 _mm_mask_div_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_maskz_div_ss( __mmask8 k, __m128 a, __m128 b);
VDIVSS __m128 _mm_div_round_ss( __m128 a, __m128 b, int);
VDIVSS __m128 _mm_mask_div_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VDIVSS __m128 _mm_maskz_div_round_ss( __mmask8 k, __m128 a, __m128 b, int);
DIVSS __m128 _mm_div_ss(__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: DPPD
description:
DPPD - Dot Product of Packed Double Precision Floating-Point Values
 Opcode/                                         Op/      64/32-bit CPUID        Description
 Instruction                                     En       Mode      Feature
                                                                    Flag
 66 0F 3A 41 /r ib                               RMI      V/V       SSE4_1       Selectively multiply packed DP floating-point
 DPPD xmm1, xmm2/m128, imm8                                                      values from xmm1 with packed DP floating-
                                                                                 point values from xmm2, add and selectively
                                                                                 store the packed DP floating-point values to
                                                                                 xmm1.
 VEX.NDS.128.66.0F3A.WIG 41 /r ib                RVMI V/V           AVX          Selectively multiply packed DP floating-point
 VDPPD xmm1,xmm2, xmm3/m128, imm8                                                values from xmm2 with packed DP floating-
                                                                                 point values from xmm3, add and selectively
                                                                                 store the packed DP floating-point values to
                                                                                 xmm1.



                                           Instruction Operand Encoding
  Op/En               Operand 1            Operand 2                      Operand 3                         Operand 4
   RMI           ModRM:reg (r, w)         ModRM:r/m (r)                     imm8                                NA
   RVMI              ModRM:reg (w)         VEX.vvvv (r)                 ModRM:r/m (r)                          imm8

Description
Conditionally multiplies the packed double-precision floating-point values in the destination operand (first operand)
with the packed double-precision floating-point values in the source (second operand) depending on a mask
extracted from bits [5:4] of the immediate operand (third operand). If a condition mask bit is zero, the corre-
sponding multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 1.
The two resulting double-precision values are summed into an intermediate result. The intermediate result is
conditionally broadcasted to the destination using a broadcast mask specified by bits [1:0] of the immediate byte.
If a broadcast mask bit is "1", the intermediate result is copied to the corresponding qword element in the destina-
tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.
DPPD follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do
not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of
those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-
ated NaNs will have at least one NaN propagated to the destination.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
If VDPPD is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.





Operation
DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
     THEN Temp1[63:0] <- DEST[63:0] * SRC[63:0]; // update SIMD exception flags
     ELSE Temp1[63:0] <- +0.0; FI;
IF (imm8[5] = 1)
     THEN Temp1[127:64] <- DEST[127:64] * SRC[127:64]; // update SIMD exception flags
     ELSE Temp1[127:64] <- +0.0; FI;
/* if unmasked exception reported, execute exception handler*/

Temp2[63:0] <- Temp1[63:0] + Temp1[127:64]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/

IF (imm8[0] = 1)
     THEN DEST[63:0] <- Temp2[63:0];
     ELSE DEST[63:0] <- +0.0; FI;
IF (imm8[1] = 1)
     THEN DEST[127:64] <- Temp2[63:0];
     ELSE DEST[127:64] <- +0.0; FI;

DPPD (128-bit Legacy SSE version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)

VDPPD (VEX.128 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] <- 0

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
DPPD:     __m128d _mm_dp_pd ( __m128d a, __m128d b, const int mask);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Exceptions are determined separately for each add and multiply operation. Unmasked exceptions will leave the
destination untouched.

Other Exceptions
See Exceptions Type 2; additionally
#UD                       If VEX.L= 1.






platform: x86_64
mnem: DPPS
description:
DPPS - Dot Product of Packed Single Precision Floating-Point Values
 Opcode/                                        Op/    64/32-bit CPUID         Description
 Instruction                                    En     Mode      Feature
                                                                 Flag
 66 0F 3A 40 /r ib                              RMI    V/V       SSE4_1        Selectively multiply packed SP floating-point
 DPPS xmm1, xmm2/m128, imm8                                                    values from xmm1 with packed SP floating-
                                                                               point values from xmm2, add and selectively
                                                                               store the packed SP floating-point values or
                                                                               zero values to xmm1.
 VEX.NDS.128.66.0F3A.WIG 40 /r ib               RVMI V/V         AVX           Multiply packed SP floating point values from
 VDPPS xmm1,xmm2, xmm3/m128, imm8                                              xmm1 with packed SP floating point values
                                                                               from xmm2/mem selectively add and store to
                                                                               xmm1.
 VEX.NDS.256.66.0F3A.WIG 40 /r ib               RVMI V/V         AVX           Multiply packed single-precision floating-point
 VDPPS ymm1, ymm2, ymm3/m256, imm8                                             values from ymm2 with packed SP floating
                                                                               point values from ymm3/mem, selectively add
                                                                               pairs of elements and store to ymm1.



                                           Instruction Operand Encoding
   Op/En                Operand 1            Operand 2                   Operand 3                         Operand 4
    RMI              ModRM:reg (r, w)       ModRM:r/m (r)                   imm8                               NA
   RVMI              ModRM:reg (w)           VEX.vvvv (r)              ModRM:r/m (r)                          imm8

Description
Conditionally multiplies the packed single precision floating-point values in the destination operand (first operand)
with the packed single-precision floats in the source (second operand) depending on a mask extracted from the
high 4 bits of the immediate byte (third operand). If a condition mask bit in Imm8[7:4] is zero, the corresponding
multiplication is replaced by a value of 0.0 in the manner described by Section 12.8.4 of Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 1.
The four resulting single-precision values are summed into an intermediate result. The intermediate result is condi-
tionally broadcasted to the destination using a broadcast mask specified by bits [3:0] of the immediate byte.
If a broadcast mask bit is "1", the intermediate result is copied to the corresponding dword element in the destina-
tion operand. If a broadcast mask bit is zero, the corresponding element in the destination is set to zero.
DPPS follows the NaN forwarding rules stated in the Software Developer's Manual, vol. 1, table 4.7. These rules do
not cover horizontal prioritization of NaNs. Horizontal propagation of NaNs to the destination and the positioning of
those NaNs in the destination is implementation dependent. NaNs on the input sources or computationally gener-
ated NaNs will have at least one NaN propagated to the destination.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.





Operation
DP_primitive (SRC1, SRC2)
IF (imm8[4] = 1)
     THEN Temp1[31:0] <- DEST[31:0] * SRC[31:0]; // update SIMD exception flags
     ELSE Temp1[31:0] <- +0.0; FI;
IF (imm8[5] = 1)
     THEN Temp1[63:32] <- DEST[63:32] * SRC[63:32]; // update SIMD exception flags
     ELSE Temp1[63:32] <- +0.0; FI;
IF (imm8[6] = 1)
     THEN Temp1[95:64] <- DEST[95:64] * SRC[95:64]; // update SIMD exception flags
     ELSE Temp1[95:64] <- +0.0; FI;
IF (imm8[7] = 1)
     THEN Temp1[127:96] <- DEST[127:96] * SRC[127:96]; // update SIMD exception flags
     ELSE Temp1[127:96] <- +0.0; FI;

Temp2[31:0] <- Temp1[31:0] + Temp1[63:32]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp3[31:0] <- Temp1[95:64] + Temp1[127:96]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/
Temp4[31:0] <- Temp2[31:0] + Temp3[31:0]; // update SIMD exception flags
/* if unmasked exception reported, execute exception handler*/

IF (imm8[0] = 1)
     THEN DEST[31:0] <- Temp4[31:0];
     ELSE DEST[31:0] <- +0.0; FI;
IF (imm8[1] = 1)
     THEN DEST[63:32] <- Temp4[31:0];
     ELSE DEST[63:32] <- +0.0; FI;
IF (imm8[2] = 1)
     THEN DEST[95:64] <- Temp4[31:0];
     ELSE DEST[95:64] <- +0.0; FI;
IF (imm8[3] = 1)
     THEN DEST[127:96] <- Temp4[31:0];
     ELSE DEST[127:96] <- +0.0; FI;

DPPS (128-bit Legacy SSE version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] (Unmodified)

VDPPS (VEX.128 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[VLMAX-1:128] <- 0

VDPPS (VEX.256 encoded version)
DEST[127:0]<-DP_Primitive(SRC1[127:0], SRC2[127:0]);
DEST[255:128]<-DP_Primitive(SRC1[255:128], SRC2[255:128]);

Flags Affected
None





Intel C/C++ Compiler Intrinsic Equivalent
(V)DPPS:    __m128 _mm_dp_ps ( __m128 a, __m128 b, const int mask);

VDPPS:      __m256 _mm256_dp_ps ( __m256 a, __m256 b, const int mask);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal
Exceptions are determined separately for each add and multiply operation, in the order of their execution.
Unmasked exceptions will leave the destination operands unchanged.

Other Exceptions
See Exceptions Type 2.






platform: x86_64
mnem: EMMS
description:
EMMS-Empty MMX Technology State
Opcode                  Instruction                 Op/   64-Bit   Compat/ Description
                                                    En    Mode     Leg Mode
0F 77                   EMMS                        NP    Valid    Valid      Set the x87 FPU tag word to empty.



                                              Instruction Operand Encoding
    Op/En             Operand 1                  Operand 2                 Operand 3                  Operand 4
      NP                 NA                          NA                       NA                         NA

Description
Sets the values of all the tags in the x87 FPU tag word to empty (all 1s). This operation marks the x87 FPU data
registers (which are aliased to the MMX technology registers) as available for use by x87 FPU floating-point instruc-
tions. (See Figure 8-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for the
format of the x87 FPU tag word.) All other MMX instructions (other than the EMMS instruction) set all the tags in
x87 FPU tag word to valid (all 0s).
The EMMS instruction must be used to clear the MMX technology state at the end of all MMX technology procedures
or subroutines and before calling other procedures or subroutines that may execute x87 floating-point instructions.
If a floating-point instruction loads one of the registers in the x87 FPU data register stack before the x87 FPU tag
word has been reset by the EMMS instruction, an x87 floating-point register stack overflow can occur that will
result in an x87 floating-point exception or incorrect result.
EMMS operation is the same in non-64-bit modes and 64-bit mode.

Operation
x87FPUTagWord <- FFFFH;

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_empty()

Flags Affected
None

Protected Mode Exceptions
#UD                   If CR0.EM[bit 2] = 1.
#NM                   If CR0.TS[bit 3] = 1.
#MF                   If there is a pending FPU exception.
#UD                   If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.





platform: x86_64
mnem: ENTER
description:
ENTER-Make Stack Frame for Procedure Parameters
Opcode                 Instruction              Op/      64-Bit   Compat/ Description
                                                En       Mode     Leg Mode
C8 iw 00               ENTER imm16, 0           II       Valid    Valid       Create a stack frame for a procedure.
C8 iw 01               ENTER imm16,1            II       Valid    Valid       Create a stack frame with a nested pointer for
                                                                              a procedure.
C8 iw ib               ENTER imm16, imm8        II       Valid    Valid       Create a stack frame with nested pointers for
                                                                              a procedure.



                                           Instruction Operand Encoding
    Op/En          Operand 1                 Operand 2                    Operand 3                     Operand 4
      II              iw                       imm8                          NA                            NA

Description
Creates a stack frame (comprising of space for dynamic storage and 1-32 frame pointer storage) for a procedure.
The first operand (imm16) specifies the size of the dynamic storage in the stack frame (that is, the number of bytes
of dynamically allocated on the stack for the procedure). The second operand (imm8) gives the lexical nesting level
(0 to 31) of the procedure. The nesting level (imm8 mod 32) and the OperandSize attribute determine the size in
bytes of the storage space for frame pointers.
The nesting level determines the number of frame pointers that are copied into the "display area" of the new stack
frame from the preceding frame. The default size of the frame pointer is the StackAddrSize attribute, but can be
overridden using the 66H prefix. Thus, the OperandSize attribute determines the size of each frame pointer that
will be copied into the stack frame and the data being transferred from SP/ESP/RSP register into the BP/EBP/RBP
register.
The ENTER and companion LEAVE instructions are provided to support block structured languages. The ENTER
instruction (when used) is typically the first instruction in a procedure and is used to set up a new stack frame for
a procedure. The LEAVE instruction is then used at the end of the procedure (just before the RET instruction) to
release the stack frame.
If the nesting level is 0, the processor pushes the frame pointer from the BP/EBP/RBP register onto the stack,
copies the current stack pointer from the SP/ESP/RSP register into the BP/EBP/RBP register, and loads the
SP/ESP/RSP register with the current stack-pointer value minus the value in the size operand. For nesting levels of
1 or greater, the processor pushes additional frame pointers on the stack before adjusting the stack pointer. These
additional frame pointers provide the called procedure with access points to other nested frames on the stack. See
"Procedure Calls for Block-Structured Languages" in Chapter 6 of the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for more information about the actions of the ENTER instruction.
The ENTER instruction causes a page fault whenever a write using the final value of the stack pointer (within the
current stack segment) would do so.
In 64-bit mode, default operation size is 64 bits; 32-bit operation size cannot be encoded. Use of 66H prefix
changes frame pointer operand size to 16 bits.
When the 66H prefix is used and causing the OperandSize attribute to be less than the StackAddrSize, software is
responsible for the following:
.   The companion LEAVE instruction must also use the 66H prefix,
.   The value in the RBP/EBP register prior to executing "66H ENTER" must be within the same 16KByte region of
    the current stack pointer (RSP/ESP), such that the value of RBP/EBP after "66H ENTER" remains a valid address
    in the stack. This ensures "66H LEAVE" can restore 16-bits of data from the stack.





Operation
AllocSize <- imm16;
NestingLevel <- imm8 MOD 32;
IF (OperandSize = 64)
    THEN
         Push(RBP); (* RSP decrements by 8 *)
         FrameTemp <- RSP;
    ELSE IF OperandSize = 32
         THEN
             Push(EBP); (* (E)SP decrements by 4 *)
             FrameTemp <- ESP; FI;
    ELSE (* OperandSize = 16 *)
             Push(BP); (* RSP or (E)SP decrements by 2 *)
             FrameTemp <- SP;
FI;

IF NestingLevel = 0
    THEN GOTO CONTINUE;
FI;

IF (NestingLevel > 1)
    THEN FOR i <- 1 to (NestingLevel - 1)
         DO
             IF (OperandSize = 64)
                  THEN
                      RBP <- RBP - 8;
                      Push([RBP]); (* Quadword push *)
                  ELSE IF OperandSize = 32
                      THEN
                           IF StackSize = 32
                                EBP <- EBP - 4;
                                Push([EBP]); (* Doubleword push *)
                           ELSE (* StackSize = 16 *)
                                BP <- BP - 4;
                                Push([BP]); (* Doubleword push *)
                           FI;
                      FI;
                  ELSE (* OperandSize = 16 *)
                      IF StackSize = 32
                           THEN
                                EBP <- EBP - 2;
                                Push([EBP]); (* Word push *)
                           ELSE (* StackSize = 16 *)
                                BP <- BP - 2;
                                Push([BP]); (* Word push *)
                      FI;
                  FI;
    OD;
FI;

IF (OperandSize = 64) (* nestinglevel 1 *)
    THEN
        Push(FrameTemp); (* Quadword push and RSP decrements by 8 *)
    ELSE IF OperandSize = 32




          THEN
               Push(FrameTemp); FI; (* Doubleword push and (E)SP decrements by 4 *)
      ELSE (* OperandSize = 16 *)
               Push(FrameTemp); (* Word push and RSP|ESP|SP decrements by 2 *)
FI;

CONTINUE:
IF 64-Bit Mode (StackSize = 64)
    THEN
             RBP <- FrameTemp;
             RSP <- RSP - AllocSize;
    ELSE IF OperandSize = 32
         THEN
             EBP <- FrameTemp;
             ESP <- ESP - AllocSize; FI;
    ELSE (* OperandSize = 16 *)
             BP <- FrameTemp[15:1]; (* Bits 16 and above of applicable RBP/EBP are unmodified *)
             SP <- SP - AllocSize;
FI;

END;

Flags Affected
None.

Protected Mode Exceptions
#SS(0)                   If the new value of the SP or ESP register is outside the stack segment limit.
#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current
                         stack segment) would cause a page fault.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#SS                      If the new value of the SP or ESP register is outside the stack segment limit.
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#SS(0)                   If the new value of the SP or ESP register is outside the stack segment limit.
#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current
                         stack segment) would cause a page fault.
#UD                      If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                   If the stack address is in a non-canonical form.
#PF(fault-code)          If a page fault occurs or if a write using the final value of the stack pointer (within the current
                         stack segment) would cause a page fault.
#UD                      If the LOCK prefix is used.






platform: x86_64
mnem: EXTRACTPS
description:
EXTRACTPS-Extract Packed Floating-Point Values
 Opcode/                                         Op /    64/32         CPUID     Description
 Instruction                                     En      bit Mode      Feature
                                                         Support       Flag
 66 0F 3A 17 /r ib                               RMI     VV            SSE4_1    Extract one single-precision floating-point value
 EXTRACTPS reg/m32, xmm1, imm8                                                   from xmm1 at the offset specified by imm8 and
                                                                                 store the result in reg or m32. Zero extend the
                                                                                 results in 64-bit register if applicable.
 VEX.128.66.0F3A.WIG 17 /r ib                    RMI     V/V           AVX       Extract one single-precision floating-point value
 VEXTRACTPS reg/m32, xmm1, imm8                                                  from xmm1 at the offset specified by imm8 and
                                                                                 store the result in reg or m32. Zero extend the
                                                                                 results in 64-bit register if applicable.
 EVEX.128.66.0F3A.WIG 17 /r ib                   T1S     V/V           AVX512F   Extract one single-precision floating-point value
 VEXTRACTPS reg/m32, xmm1, imm8                                                  from xmm1 at the offset specified by imm8 and
                                                                                 store the result in reg or m32. Zero extend the
                                                                                 results in 64-bit register if applicable.



                                                       Instruction Operand Encoding
        Op/En                  Operand 1                        Operand 2               Operand 3                   Operand 4
         RMI                ModRM:r/m (w)                      ModRM:reg (r)              Imm8                          NA
         T1S                ModRM:r/m (w)                      ModRM:reg (r)              Imm8                          NA

Description
Extracts a single-precision floating-point value from the source operand (second operand) at the 32-bit offset spec-
ified from imm8. Immediate bits higher than the most significant offset for the vector length are ignored.
The extracted single-precision floating-point value is stored in the low 32-bits of the destination operand
In 64-bit mode, destination register operand has default operand size of 64 bits. The upper 32-bits of the register
are filled with zero. REX.W is ignored.
VEX.128 and EVEX encoded version: When VEX.W1 or EVEX.W1 form is used in 64-bit mode with a general
purpose register (GPR) as a destination operand, the packed single quantity is zero extended to 64 bits.
VEX.vvvv/EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
128-bit Legacy SSE version: When a REX.W prefix is used in 64-bit mode with a general purpose register (GPR) as
a destination operand, the packed single quantity is zero extended to 64 bits.
The source register is an XMM register. Imm8[1:0] determine the starting DWORD offset from which to extract the
32-bit floating-point value.
If VEXTRACTPS is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause
an #UD exception.

Operation
VEXTRACTPS (EVEX and VEX.128 encoded version)
SRC_OFFSET <- IMM8[1:0]
IF (64-Bit Mode and DEST is register)
    DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
    DEST[63:32] <- 0
ELSE
    DEST[31:0] <- (SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI





EXTRACTPS (128-bit Legacy SSE version)
SRC_OFFSET <-IMM8[1:0]
IF (64-Bit Mode and DEST is register)
    DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
    DEST[63:32] <-0
ELSE
    DEST[31:0] <-(SRC[127:0] >> (SRC_OFFSET*32)) AND 0FFFFFFFFh
FI

Intel C/C++ Compiler Intrinsic Equivalent
EXTRACTPS int _mm_extract_ps (__m128 a, const int nidx);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instructions, see Exceptions Type 5; Additionally
EVEX-encoded instructions, see Exceptions Type E9NF.
#UD                   IF VEX.L = 0.
#UD                   If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: F2XM1
description:
F2XM1-Compute 2x-1
Opcode                   Instruction              64-Bit      Compat/       Description
                                                  Mode        Leg Mode
D9 F0                    F2XM1                    Valid       Valid         Replace ST(0) with (2ST(0) - 1).



Description
Computes the exponential value of 2 to the power of the source operand minus 1. The source operand is located in
register ST(0) and the result is also stored in ST(0). The value of the source operand must lie in the range -1.0 to
+1.0. If the source value is outside this range, the result is undefined.
The following table shows the results obtained when computing the exponential value of various classes of
numbers, assuming that neither overflow nor underflow occurs.
                                         Table 3-16. Results Obtained from F2XM1
                           ST(0) SRC                                                   ST(0) DEST
                           - 1.0 to -0                                                 - 0.5 to - 0
                               -0                                                           -0
                               +0                                                           +0
                           + 0 to +1.0                                                  + 0 to 1.0

Values other than 2 can be exponentiated using the following formula:

     xy <- 2(y * log2x)


This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
ST(0) <- (2ST(0) - 1);

FPU Flags Affected
C1                       Set to 0 if stack underflow occurred.
                         Set if result was rounded up; cleared otherwise.
C0, C2, C3               Undefined.

Floating-Point Exceptions
#IS                      Stack underflow occurred.
#IA                      Source operand is an SNaN value or unsupported format.
#D                       Source is a denormal value.
#U                       Result is too small for destination format.
#P                       Value cannot be represented exactly in destination format.

Protected Mode Exceptions
#NM                      CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.



Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FABS
description:
FABS-Absolute Value
 Opcode                 Instruction               64-Bit   Compat/    Description
                                                  Mode     Leg Mode
 D9 E1                  FABS                      Valid    Valid      Replace ST with its absolute value.



Description
Clears the sign bit of ST(0) to create the absolute value of the operand. The following table shows the results
obtained when creating the absolute value of various classes of numbers.

                                        Table 3-17. Results Obtained from FABS
                            ST(0) SRC                                                ST(0) DEST
                               -inf                                                       +inf
                               -F                                                         +F
                               -0                                                         +0
                               +0                                                         +0
                               +F                                                         +F
                               +inf                                                       +inf
                               NaN                                                       NaN
 NOTES:
 F Means finite floating-point value.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
ST(0) <- |ST(0)|;

FPU Flags Affected
C1                      Set to 0.
C0, C2, C3              Undefined.

Floating-Point Exceptions
#IS                     Stack underflow occurred.

Protected Mode Exceptions
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.




platform: x86_64
mnem: FADD
description:
FADD/FADDP/FIADD-Add
Opcode              Instruction               64-Bit     Compat/     Description
                                              Mode       Leg Mode
D8 /0               FADD m32fp                Valid      Valid       Add m32fp to ST(0) and store result in ST(0).
DC /0               FADD m64fp                Valid      Valid       Add m64fp to ST(0) and store result in ST(0).
D8 C0+i             FADD ST(0), ST(i)         Valid      Valid       Add ST(0) to ST(i) and store result in ST(0).
DC C0+i             FADD ST(i), ST(0)         Valid      Valid       Add ST(i) to ST(0) and store result in ST(i).
DE C0+i             FADDP ST(i), ST(0)        Valid      Valid       Add ST(0) to ST(i), store result in ST(i), and pop the
                                                                     register stack.
DE C1               FADDP                     Valid      Valid       Add ST(0) to ST(1), store result in ST(1), and pop the
                                                                     register stack.
DA /0               FIADD m32int              Valid      Valid       Add m32int to ST(0) and store result in ST(0).
DE /0               FIADD m16int              Valid      Valid       Add m16int to ST(0) and store result in ST(0).



Description
Adds the destination and source operands and stores the sum in the destination location. The destination operand
is always an FPU register; the source operand can be a register or a memory location. Source operands in memory
can be in single-precision or double-precision floating-point format or in word or doubleword integer format.
The no-operand version of the instruction adds the contents of the ST(0) register to the ST(1) register. The one-
operand version adds the contents of a memory location (either a floating-point or an integer value) to the contents
of the ST(0) register. The two-operand version, adds the contents of the ST(0) register to the ST(i) register or vice
versa. The value in ST(0) can be doubled by coding:

   FADD ST(0), ST(0);
The FADDP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. (The no-operand version of the floating-point add instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FADD rather than FADDP.)
The FIADD instructions convert an integer source operand to double extended-precision floating-point format
before performing the addition.
The table on the following page shows the results obtained when adding various classes of numbers, assuming that
neither overflow nor underflow occurs.
When the sum of two operands with opposite signs is 0, the result is +0, except for the round toward -inf mode, in
which case the result is -0. When the source operand is an integer 0, it is treated as a +0.
When both operand are infinities of the same sign, the result is inf of the expected sign. If both operands are infini-
ties of opposite signs, an invalid-operation exception is generated. See Table 3-18.





                                            Table 3-18. FADD/FADDP/FIADD Results
                                                                          DEST
                               -inf           -F               -0             +0    +F               +inf           NaN
              -inf               -inf           -inf               -inf             -inf    -inf               *            NaN
              - F or - I       -inf           -F               SRC            SRC   +- F or +- 0       +inf           NaN
 SRC          -0               -inf           DEST             -0             +-0    DEST             +inf           NaN
              +0               -inf           DEST             +-0             +0    DEST             +inf           NaN
              + F or + I       -inf           +- F or +- 0       SRC            SRC   +F               +inf           NaN
              +inf               *            +inf               +inf             +inf    +inf               +inf           NaN
              NaN              NaN          NaN              NaN            NaN   NaN              NaN          NaN
 NOTES:
 F Means finite floating-point value.
 I Means integer.
 * Indicates floating-point invalid-arithmetic-operand (#IA) exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
IF Instruction = FIADD
     THEN
         DEST <- DEST + ConvertToDoubleExtendedPrecisionFP(SRC);
     ELSE (* Source operand is floating-point value *)
         DEST <- DEST + SRC;
FI;

IF Instruction = FADDP
     THEN
         PopRegisterStack;
FI;

FPU Flags Affected
C1                         Set to 0 if stack underflow occurred.
                           Set if result was rounded up; cleared otherwise.
C0, C2, C3                 Undefined.

Floating-Point Exceptions
#IS                        Stack underflow occurred.
#IA                        Operand is an SNaN value or unsupported format.
                           Operands are infinities of unlike sign.
#D                         Source operand is a denormal value.
#U                         Result is too small for destination format.
#O                         Result is too large for destination format.
#P                         Value cannot be represented exactly in destination format.





Protected Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                 If there is a pending x87 FPU exception.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: FBLD
description:
FBLD-Load Binary Coded Decimal
 Opcode                Instruction                64-Bit   Compat/    Description
                                                  Mode     Leg Mode
 DF /4                 FBLD m80dec                Valid    Valid      Convert BCD value to floating-point and push onto the
                                                                      FPU stack.



Description
Converts the BCD source operand into double extended-precision floating-point format and pushes the value onto
the FPU stack. The source operand is loaded without rounding errors. The sign of the source operand is preserved,
including that of -0.
The packed BCD digits are assumed to be in the range 0 through 9; the instruction does not check for invalid digits
(AH through FH). Attempting to load an invalid encoding produces an undefined result.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
TOP <- TOP - 1;
ST(0) <- ConvertToDoubleExtendedPrecisionFP(SRC);

FPU Flags Affected
C1                      Set to 1 if stack overflow occurred; otherwise, set to 0.
C0, C2, C3              Undefined.

Floating-Point Exceptions
#IS                     Stack overflow occurred.

Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.
#UD                     If the LOCK prefix is used.



Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                 If there is a pending x87 FPU exception.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: FBSTP
description:
FBSTP-Store BCD Integer and Pop
Opcode              Instruction                   64-Bit     Compat/    Description
                                                  Mode       Leg Mode
DF /6               FBSTP m80bcd                  Valid      Valid      Store ST(0) in m80bcd and pop ST(0).



Description
Converts the value in the ST(0) register to an 18-digit packed BCD integer, stores the result in the destination
operand, and pops the register stack. If the source value is a non-integral value, it is rounded to an integer value,
according to rounding mode specified by the RC field of the FPU control word. To pop the register stack, the
processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The destination operand specifies the address where the first byte destination value is to be stored. The BCD value
(including its sign bit) requires 10 bytes of space in memory.
The following table shows the results obtained when storing various classes of numbers in packed BCD format.
                                                     Table 3-19. FBSTP Results
                              ST(0)                                                           DEST
            - inf or Value Too Large for DEST Format                                              *
                              F<=-1                                                             -D
                            -1 < F < -0                                                         **
                                  -0                                                           -0
                                  +0                                                           +0
                           + 0 < F < +1                                                         **
                              F >= +1                                                           +D
            + inf or Value Too Large for DEST Format                                              *
                               NaN                                                              *
 NOTES:
 F Means finite floating-point value.
 D Means packed-BCD number.
 * Indicates floating-point invalid-operation (#IA) exception.
 ** +-0 or +-1, depending on the rounding mode.

If the converted value is too large for the destination format, or if the source operand is an inf, SNaN, QNAN, or is in
an unsupported format, an invalid-arithmetic-operand condition is signaled. If the invalid-operation exception is
not masked, an invalid-arithmetic-operand exception (#IA) is generated and no value is stored in the destination
operand. If the invalid-operation exception is masked, the packed BCD indefinite value is stored in memory.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
DEST <- BCD(ST(0));
PopRegisterStack;

FPU Flags Affected
C1                      Set to 0 if stack underflow occurred.
                        Set if result was rounded up; cleared otherwise.
C0, C2, C3              Undefined.





Floating-Point Exceptions
#IS                 Stack underflow occurred.
#IA                 Converted value that exceeds 18 BCD digits in length.
                    Source operand is an SNaN, QNaN, +-inf, or in an unsupported format.
#P                  Value cannot be represented exactly in destination format.

Protected Mode Exceptions
#GP(0)              If a segment register is being loaded with a segment selector that points to a non-writable
                    segment.
                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                 If there is a pending x87 FPU exception.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: FCHS
description:
FCHS-Change Sign
Opcode                 Instruction             64-Bit   Compat/    Description
                                               Mode     Leg Mode
D9 E0                  FCHS                    Valid    Valid      Complements sign of ST(0).



Description
Complements the sign bit of ST(0). This operation changes a positive value into a negative value of equal magni-
tude or vice versa. The following table shows the results obtained when changing the sign of various classes of
numbers.
                                                Table 3-20. FCHS Results
                            ST(0) SRC                                              ST(0) DEST
 -inf                                                        +inf
 -F                                                        +F
 -0                                                        +0
 +0                                                        -0
 +F                                                        -F
 +inf                                                        -inf
 NaN                                                       NaN
 NOTES:
 * F means finite floating-point value.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
SignBit(ST(0)) <- NOT (SignBit(ST(0)));

FPU Flags Affected
C1                      Set to 0.
C0, C2, C3              Undefined.

Floating-Point Exceptions
#IS                     Stack underflow occurred.

Protected Mode Exceptions
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FCLEX
description:
FCLEX/FNCLEX - Clear Exceptions
 Opcode*                Instruction             64-Bit   Compat/    Description
                                                Mode     Leg Mode
 9B DB E2               FCLEX                   Valid    Valid      Clear floating-point exception flags after checking for
                                                                    pending unmasked floating-point exceptions.
 DB E2                  FNCLEX*                 Valid    Valid      Clear floating-point exception flags without checking for
                                                                    pending unmasked floating-point exceptions.
 NOTES:
 * See IA-32 Architecture Compatibility section below.



Description
Clears the floating-point exception flags (PE, UE, OE, ZE, DE, and IE), the exception summary status flag (ES), the
stack fault flag (SF), and the busy flag (B) in the FPU status word. The FCLEX instruction checks for and handles
any pending unmasked floating-point exceptions before clearing the exception flags; the FNCLEX instruction does
not.
The assembler issues two instructions for the FCLEX instruction (an FWAIT instruction followed by an FNCLEX
instruction), and the processor executes each of these instructions separately. If an exception is generated for
either of these instructions, the save EIP points to the instruction that caused the exception.

IA-32 Architecture Compatibility
When operating a Pentium or Intel486 processor in MS-DOS* compatibility mode, it is possible (under unusual
circumstances) for an FNCLEX instruction to be interrupted prior to being executed to handle a pending FPU excep-
tion. See the section titled "No-Wait FPU Instructions Can Get FPU Interrupt in Window" in Appendix D of the Intel
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for a description of these circumstances. An
FNCLEX instruction cannot be interrupted in this way on later Intel processors, except for the Intel QuarkTM X1000
processor.
This instruction affects only the x87 FPU floating-point exception flags. It does not affect the SIMD floating-point
exception flags in the MXCRS register.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
FPUStatusWord[0:7] <- 0;
FPUStatusWord[15] <- 0;

FPU Flags Affected
The PE, UE, OE, ZE, DE, IE, ES, SF, and B flags in the FPU status word are cleared. The C0, C1, C2, and C3 flags are
undefined.

Floating-Point Exceptions
None

Protected Mode Exceptions
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.





Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FCMOVcc
description:
FCMOVcc-Floating-Point Conditional Move
Opcode*            Instruction                          64-Bit    Compat/   Description
                                                        Mode      Leg Mode*
DA C0+i            FCMOVB ST(0), ST(i)                  Valid     Valid     Move if below (CF=1).
DA C8+i            FCMOVE ST(0), ST(i)                  Valid     Valid     Move if equal (ZF=1).
DA D0+i            FCMOVBE ST(0), ST(i)                 Valid     Valid     Move if below or equal (CF=1 or ZF=1).
DA D8+i            FCMOVU ST(0), ST(i)                  Valid     Valid     Move if unordered (PF=1).
DB C0+i            FCMOVNB ST(0), ST(i)                 Valid     Valid     Move if not below (CF=0).
DB C8+i            FCMOVNE ST(0), ST(i)                 Valid     Valid     Move if not equal (ZF=0).
DB D0+i            FCMOVNBE ST(0), ST(i)                Valid     Valid     Move if not below or equal (CF=0 and ZF=0).
DB D8+i            FCMOVNU ST(0), ST(i)                 Valid     Valid     Move if not unordered (PF=0).
NOTES:
* See IA-32 Architecture Compatibility section below.



Description
Tests the status flags in the EFLAGS register and moves the source operand (second operand) to the destination
operand (first operand) if the given test condition is true. The condition for each mnemonic os given in the Descrip-
tion column above and in Chapter 8 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume
1. The source operand is always in the ST(i) register and the destination operand is always ST(0).
The FCMOVcc instructions are useful for optimizing small IF constructions. They also help eliminate branching
overhead for IF operations and the possibility of branch mispredictions by the processor.
A processor may not support the FCMOVcc instructions. Software can check if the FCMOVcc instructions are
supported by checking the processor's feature information with the CPUID instruction (see "COMISS-Compare
Scalar Ordered Single-Precision Floating-Point Values and Set EFLAGS" in this chapter). If both the CMOV and FPU
feature bits are set, the FCMOVcc instructions are supported.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility
The FCMOVcc instructions were introduced to the IA-32 Architecture in the P6 family processors and are not avail-
able in earlier IA-32 processors.

Operation
IF condition TRUE
    THEN ST(0) <- ST(i);
FI;

FPU Flags Affected
C1                        Set to 0 if stack underflow occurred.
C0, C2, C3                Undefined.

Floating-Point Exceptions
#IS                       Stack underflow occurred.

Integer Flags Affected
None.





Protected Mode Exceptions
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FCOM
description:
FCOM/FCOMP/FCOMPP-Compare Floating Point Values
 Opcode               Instruction                     64-Bit       Compat/       Description
                                                      Mode         Leg Mode
 D8 /2                FCOM m32fp                      Valid        Valid         Compare ST(0) with m32fp.
 DC /2                FCOM m64fp                      Valid        Valid         Compare ST(0) with m64fp.
 D8 D0+i              FCOM ST(i)                      Valid        Valid         Compare ST(0) with ST(i).
 D8 D1                FCOM                            Valid        Valid         Compare ST(0) with ST(1).
 D8 /3                FCOMP m32fp                     Valid        Valid         Compare ST(0) with m32fp and pop register stack.
 DC /3                FCOMP m64fp                     Valid        Valid         Compare ST(0) with m64fp and pop register stack.
 D8 D8+i              FCOMP ST(i)                     Valid        Valid         Compare ST(0) with ST(i) and pop register stack.
 D8 D9                FCOMP                           Valid        Valid         Compare ST(0) with ST(1) and pop register stack.
 DE D9                FCOMPP                          Valid        Valid         Compare ST(0) with ST(1) and pop register stack
                                                                                 twice.



Description
Compares the contents of register ST(0) and source value and sets condition code flags C0, C2, and C3 in the FPU
status word according to the results (see the table below). The source operand can be a data register or a memory
location. If no source operand is given, the value in ST(0) is compared with the value in ST(1). The sign of zero is
ignored, so that -0.0 is equal to +0.0.
                                          Table 3-21. FCOM/FCOMP/FCOMPP Results
                  Condition                               C3                            C2                          C0
                 ST(0) > SRC                               0                            0                            0
                 ST(0) < SRC                               0                            0                            1
                 ST(0) = SRC                               1                            0                            0
                 Unordered*                                1                            1                            1
 NOTES:
 * Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.

This instruction checks the class of the numbers being compared (see "FXAM-Examine Floating-Point" in this
chapter). If either operand is a NaN or is in an unsupported format, an invalid-arithmetic-operand exception (#IA)
is raised and, if the exception is masked, the condition flags are set to "unordered." If the invalid-arithmetic-
operand exception is unmasked, the condition code flags are not set.
The FCOMP instruction pops the register stack following the comparison operation and the FCOMPP instruction
pops the register stack twice following the comparison operation. To pop the register stack, the processor marks
the ST(0) register as empty and increments the stack pointer (TOP) by 1.
The FCOM instructions perform the same operation as the FUCOM instructions. The only difference is how they
handle QNaN operands. The FCOM instructions raise an invalid-arithmetic-operand exception (#IA) when either or
both of the operands is a NaN value or is in an unsupported format. The FUCOM instructions perform the same
operation as the FCOM instructions, except that they do not generate an invalid-arithmetic-operand exception for
QNaNs.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.





Operation
CASE (relation of operands) OF
   ST > SRC:          C3, C2, C0 <- 000;
   ST < SRC:          C3, C2, C0 <- 001;
   ST = SRC:          C3, C2, C0 <- 100;
ESAC;

IF ST(0) or SRC = NaN or unsupported format
    THEN
         #IA
         IF FPUControlWord.IM = 1
              THEN
                  C3, C2, C0 <- 111;
         FI;
FI;

IF Instruction = FCOMP
     THEN
         PopRegisterStack;
FI;

IF Instruction = FCOMPP
     THEN
         PopRegisterStack;
         PopRegisterStack;
FI;

FPU Flags Affected
C1                     Set to 0.
C0, C2, C3             See table on previous page.

Floating-Point Exceptions
#IS                    Stack underflow occurred.
#IA                    One or both operands are NaN values or have unsupported formats.
                       Register is marked empty.
#D                     One or both operands are denormal values.

Protected Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                    If a memory operand effective address is outside the SS segment limit.
#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                    If the LOCK prefix is used.


Virtual-8086 Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                    If there is a pending x87 FPU exception.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used.






platform: x86_64
mnem: FCOMI
description:
FCOMI/FCOMIP/ FUCOMI/FUCOMIP-Compare Floating Point Values and Set EFLAGS
 Opcode              Instruction                  64-Bit     Compat/       Description
                                                  Mode       Leg Mode
 DB F0+i             FCOMI ST, ST(i)              Valid      Valid         Compare ST(0) with ST(i) and set status flags accordingly.
 DF F0+i             FCOMIP ST, ST(i)             Valid      Valid         Compare ST(0) with ST(i), set status flags accordingly, and
                                                                           pop register stack.
 DB E8+i             FUCOMI ST, ST(i)             Valid      Valid        Compare ST(0) with ST(i), check for ordered values, and set
                                                                          status flags accordingly.
 DF E8+i             FUCOMIP ST, ST(i)            Valid      Valid         Compare ST(0) with ST(i), check for ordered values, set
                                                                           status flags accordingly, and pop register stack.



Description
Performs an unordered comparison of the contents of registers ST(0) and ST(i) and sets the status flags ZF, PF, and
CF in the EFLAGS register according to the results (see the table below). The sign of zero is ignored for compari-
sons, so that -0.0 is equal to +0.0.
                                   Table 3-22. FCOMI/FCOMIP/ FUCOMI/FUCOMIP Results
                     Comparison Results*                                    ZF                      PF                     CF
                           ST0 > ST(i)                                       0                       0                      0
                           ST0 < ST(i)                                       0                       0                      1
                           ST0 = ST(i)                                       1                       0                      0
                          Unordered**                                        1                       1                      1
 NOTES:
 * See the IA-32 Architecture Compatibility section below.
 ** Flags not set if unmasked invalid-arithmetic-operand (#IA) exception is generated.

An unordered comparison checks the class of the numbers being compared (see "FXAM-Examine Floating-Point"
in this chapter). The FUCOMI/FUCOMIP instructions perform the same operations as the FCOMI/FCOMIP instruc-
tions. The only difference is that the FUCOMI/FUCOMIP instructions raise the invalid-arithmetic-operand exception
(#IA) only when either or both operands are an SNaN or are in an unsupported format; QNaNs cause the condition
code flags to be set to unordered, but do not cause an exception to be generated. The FCOMI/FCOMIP instructions
raise an invalid-operation exception when either or both of the operands are a NaN value of any kind or are in an
unsupported format.
If the operation results in an invalid-arithmetic-operand exception being raised, the status flags in the EFLAGS
register are set only if the exception is masked.
The FCOMI/FCOMIP and FUCOMI/FUCOMIP instructions set the OF, SF and AF flags to zero in the EFLAGS register
(regardless of whether an invalid-operation exception is detected).
The FCOMIP and FUCOMIP instructions also pop the register stack following the comparison operation. To pop the
register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP) by 1.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility
The FCOMI/FCOMIP/FUCOMI/FUCOMIP instructions were introduced to the IA-32 Architecture in the P6 family
processors and are not available in earlier IA-32 processors.





Operation
CASE (relation of operands) OF
   ST(0) > ST(i):     ZF, PF, CF <- 000;
   ST(0) < ST(i):     ZF, PF, CF <- 001;
   ST(0) = ST(i):     ZF, PF, CF <- 100;
ESAC;

IF Instruction is FCOMI or FCOMIP
     THEN
         IF ST(0) or ST(i) = NaN or unsupported format
              THEN
                   #IA
                   IF FPUControlWord.IM = 1
                        THEN
                             ZF, PF, CF <- 111;
                   FI;
         FI;
FI;

IF Instruction is FUCOMI or FUCOMIP
    THEN
         IF ST(0) or ST(i) = QNaN, but not SNaN or unsupported format
              THEN
                   ZF, PF, CF <- 111;
              ELSE (* ST(0) or ST(i) is SNaN or unsupported format *)
                    #IA;
                   IF FPUControlWord.IM = 1
                         THEN
                             ZF, PF, CF <- 111;
                   FI;
         FI;
FI;

IF Instruction is FCOMIP or FUCOMIP
     THEN
         PopRegisterStack;
FI;

FPU Flags Affected
C1                      Set to 0.
C0, C2, C3              Not affected.

Floating-Point Exceptions
#IS                     Stack underflow occurred.
#IA                     (FCOMI or FCOMIP instruction) One or both operands are NaN values or have unsupported
                        formats.
                        (FUCOMI or FUCOMIP instruction) One or both operands are SNaN values (but not QNaNs) or
                        have undefined formats. Detection of a QNaN value does not raise an invalid-operand excep-
                        tion.





Protected Mode Exceptions
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                 If there is a pending x87 FPU exception.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FCOS
description:
FCOS- Cosine
Opcode                 Instruction                 64-Bit     Compat/     Description
                                                   Mode       Leg Mode
D9 FF                  FCOS                        Valid      Valid       Replace ST(0) with its approximate cosine.



Description
Computes the approximate cosine of the source operand in register ST(0) and stores the result in ST(0). The
source operand must be given in radians and must be within the range -263 to +263. The following table shows the
results obtained when taking the cosine of various classes of numbers.
                                                       Table 3-23. FCOS Results
                            ST(0) SRC                                                     ST(0) DEST
                               -inf                                                              *
                               -F                                                          -1 to +1
                               -0                                                             +1
                               +0                                                             +1
                               +F                                                          - 1 to + 1
                               +inf                                                              *
                               NaN                                                            NaN
 NOTES:
 F Means finite floating-point value.
 * Indicates floating-point invalid-arithmetic-operand (#IA) exception.

If the source operand is outside the acceptable range, the C2 flag in the FPU status word is set, and the value in
register ST(0) remains unchanged. The instruction does not raise an exception when the source operand is out of
range. It is up to the program to check the C2 flag for out-of-range conditions. Source values outside the range -
263 to +263 can be reduced to the range of the instruction by subtracting an appropriate integer multiple of 2pi.
However, even within the range -263 to +263, inaccurate results can occur because the finite approximation of pi
used internally for argument reduction is not sufficient in all cases. Therefore, for accurate results it is safe to apply
FCOS only to arguments reduced accurately in software, to a value smaller in absolute value than 3pi/8. See the
sections titled "Approximation of Pi" and "Transcendental Instruction Accuracy" in Chapter 8 of the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for a discussion of the proper value to use for pi in
performing such reductions.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
IF |ST(0)| < 263
THEN
     C2 <- 0;
     ST(0) <- FCOS(ST(0)); // approximation of cosine
ELSE (* Source operand is out-of-range *)
     C2 <- 1;
FI;





FPU Flags Affected
C1                   Set to 0 if stack underflow occurred.
                     Set if result was rounded up; cleared otherwise.
                     Undefined if C2 is 1.
C2                   Set to 1 if outside range (-263 < source operand < +263); otherwise, set to 0.
C0, C3               Undefined.

Floating-Point Exceptions
#IS                  Stack underflow occurred.
#IA                  Source operand is an SNaN value, inf, or unsupported format.
#D                   Source is a denormal value.
#P                   Value cannot be represented exactly in destination format.

Protected Mode Exceptions
#NM                  CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                  If there is a pending x87 FPU exception.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FDECSTP
description:
FDECSTP-Decrement Stack-Top Pointer
 Opcode                Instruction            64-Bit      Compat/       Description
                                              Mode        Leg Mode
 D9 F6                 FDECSTP                Valid       Valid         Decrement TOP field in FPU status word.



Description
Subtracts one from the TOP field of the FPU status word (decrements the top-of-stack pointer). If the TOP field
contains a 0, it is set to 7. The effect of this instruction is to rotate the stack by one position. The contents of the
FPU data registers and tag register are not affected.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
IF TOP = 0
    THEN TOP <- 7;
    ELSE TOP <- TOP - 1;
FI;

FPU Flags Affected
The C1 flag is set to 0. The C0, C2, and C3 flags are undefined.

Floating-Point Exceptions
None.

Protected Mode Exceptions
#NM                    CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                    If there is a pending x87 FPU exception.
#UD                    If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: FDIV
description:
FDIV/FDIVP/FIDIV-Divide
Opcode              Instruction                64-Bit   Compat/      Description
                                               Mode     Leg Mode
D8 /6               FDIV m32fp                 Valid    Valid        Divide ST(0) by m32fp and store result in ST(0).
DC /6               FDIV m64fp                 Valid    Valid        Divide ST(0) by m64fp and store result in ST(0).
D8 F0+i             FDIV ST(0), ST(i)          Valid    Valid        Divide ST(0) by ST(i) and store result in ST(0).
DC F8+i             FDIV ST(i), ST(0)          Valid    Valid        Divide ST(i) by ST(0) and store result in ST(i).
DE F8+i             FDIVP ST(i), ST(0)         Valid    Valid        Divide ST(i) by ST(0), store result in ST(i), and pop the
                                                                     register stack.
DE F9               FDIVP                      Valid    Valid        Divide ST(1) by ST(0), store result in ST(1), and pop
                                                                     the register stack.
DA /6               FIDIV m32int               Valid    Valid        Divide ST(0) by m32int and store result in ST(0).
DE /6               FIDIV m16int               Valid    Valid        Divide ST(0) by m16int and store result in ST(0).



Description
Divides the destination operand by the source operand and stores the result in the destination location. The desti-
nation operand (dividend) is always in an FPU register; the source operand (divisor) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision floating-point format, word or
doubleword integer format.
The no-operand version of the instruction divides the contents of the ST(1) register by the contents of the ST(0)
register. The one-operand version divides the contents of the ST(0) register by the contents of a memory location
(either a floating-point or an integer value). The two-operand version, divides the contents of the ST(0) register by
the contents of the ST(i) register or vice versa.
The FDIVP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. The no-operand version of the floating-point divide instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FDIV rather than FDIVP.
The FIDIV instructions convert an integer source operand to double extended-precision floating-point format
before performing the division. When the source operand is an integer 0, it is treated as a +0.
If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of
the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither
overflow nor underflow occurs.





                                             Table 3-24. FDIV/FDIVP/FIDIV Results
                                                                           DEST
                              -inf             -F              -0              +0    +F        +inf           NaN
               -inf             *              +0              +0              -0    -0        *            NaN
               -F             +inf             +F              +0              -0    -F        -inf           NaN
               -I             +inf             +F              +0              -0    -F        -inf           NaN
     SRC       -0             +inf             **              *               *     **        -inf           NaN
               +0             -inf             **              *               *     **        +inf           NaN
               +I             -inf             -F              -0              +0    +F        +inf           NaN
               +F             -inf             -F              -0              +0    +F        +inf           NaN
               +inf             *              -0              -0              +0    +0        *            NaN
               NaN            NaN            NaN             NaN             NaN   NaN       NaN          NaN
  NOTES:
  F Means finite floating-point value.
  I Means integer.
  * Indicates floating-point invalid-arithmetic-operand (#IA) exception.
  ** Indicates floating-point zero-divide (#Z) exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
IF SRC = 0
    THEN
        #Z;
    ELSE
        IF Instruction is FIDIV
              THEN
                  DEST <- DEST / ConvertToDoubleExtendedPrecisionFP(SRC);
              ELSE (* Source operand is floating-point value *)
                  DEST <- DEST / SRC;
        FI;
FI;

IF Instruction = FDIVP
     THEN
         PopRegisterStack;
FI;

FPU Flags Affected
C1                        Set to 0 if stack underflow occurred.
                          Set if result was rounded up; cleared otherwise.
C0, C2, C3                Undefined.





Floating-Point Exceptions
#IS                 Stack underflow occurred.
#IA                 Operand is an SNaN value or unsupported format.
                    +-inf / +-inf; +-0 / +-0
#D                  Source is a denormal value.
#Z                  DEST / +-0, where DEST is not equal to +-0.
#U                  Result is too small for destination format.
#O                  Result is too large for destination format.
#P                  Value cannot be represented exactly in destination format.

Protected Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#NM                 CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                 If there is a pending x87 FPU exception.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: FDIVR
description:
FDIVR/FDIVRP/FIDIVR-Reverse Divide
Opcode               Instruction             64-Bit   Compat/     Description
                                             Mode     Leg Mode
D8 /7                FDIVR m32fp             Valid    Valid       Divide m32fp by ST(0) and store result in ST(0).
DC /7                FDIVR m64fp             Valid    Valid       Divide m64fp by ST(0) and store result in ST(0).
D8 F8+i              FDIVR ST(0), ST(i)      Valid    Valid       Divide ST(i) by ST(0) and store result in ST(0).
DC F0+i              FDIVR ST(i), ST(0)      Valid    Valid       Divide ST(0) by ST(i) and store result in ST(i).
DE F0+i              FDIVRP ST(i), ST(0)     Valid    Valid       Divide ST(0) by ST(i), store result in ST(i), and pop the
                                                                  register stack.
DE F1                FDIVRP                  Valid    Valid       Divide ST(0) by ST(1), store result in ST(1), and pop the
                                                                  register stack.
DA /7                FIDIVR m32int           Valid    Valid       Divide m32int by ST(0) and store result in ST(0).
DE /7                FIDIVR m16int           Valid    Valid       Divide m16int by ST(0) and store result in ST(0).



Description
Divides the source operand by the destination operand and stores the result in the destination location. The desti-
nation operand (divisor) is always in an FPU register; the source operand (dividend) can be a register or a memory
location. Source operands in memory can be in single-precision or double-precision floating-point format, word or
doubleword integer format.
These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIV instructions. They are provided to
support more efficient coding.
The no-operand version of the instruction divides the contents of the ST(0) register by the contents of the ST(1)
register. The one-operand version divides the contents of a memory location (either a floating-point or an integer
value) by the contents of the ST(0) register. The two-operand version, divides the contents of the ST(i) register by
the contents of the ST(0) register or vice versa.
The FDIVRP instructions perform the additional operation of popping the FPU register stack after storing the result.
To pop the register stack, the processor marks the ST(0) register as empty and increments the stack pointer (TOP)
by 1. The no-operand version of the floating-point divide instructions always results in the register stack being
popped. In some assemblers, the mnemonic for this instruction is FDIVR rather than FDIVRP.
The FIDIVR instructions convert an integer source operand to double extended-precision floating-point format
before performing the division.
If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if the exception is masked, an inf of
the appropriate sign is stored in the destination operand.
The following table shows the results obtained when dividing various classes of numbers, assuming that neither
overflow nor underflow occurs.





                                          Table 3-25. FDIVR/FDIVRP/FIDIVR Results
                                                                          DEST
                                  -inf              -F              -0             +0    +F             +inf            NaN
                   -inf              *             +inf              +inf              -inf    -inf               *           NaN
     SRC           -F             +0              +F              **             **    -F              -0           NaN
                   -I             +0              +F              **             **    -F              -0           NaN
                   -0             +0              +0               *              *    -0              -0           NaN
                   +0             -0              -0               *              *    +0              +0           NaN
                   +I             -0              -F              **             **    +F              +0           NaN
                   +F             -0              -F              **             **    +F              +0           NaN
                   +inf              *              -inf             -inf              +inf    +inf               *           NaN
                  NaN            NaN             NaN             NaN             NaN   NaN            NaN           NaN
 NOTES:
 F Means finite floating-point value.
 I Means integer.
 * Indicates floating-point invalid-arithmetic-operand (#IA) exception.
 ** Indicates floating-point zero-divide (#Z) exception.

When the source operand is an integer 0, it is treated as a +0. This instruction's operation is the same in non-64-bit
modes and 64-bit mode.

Operation
IF DEST = 0
    THEN
        #Z;
    ELSE
        IF Instruction = FIDIVR
              THEN
                  DEST <- ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;
              ELSE (* Source operand is floating-point value *)
                  DEST <- SRC / DEST;
        FI;
FI;

IF Instruction = FDIVRP
     THEN
         PopRegisterStack;
FI;

FPU Flags Affected
C1                      Set to 0 if stack underflow occurred.
                        Set if result was rounded up; cleared otherwise.
C0, C2, C3              Undefined.





Floating-Point Exceptions
#IS                     Stack underflow occurred.
#IA                     Operand is an SNaN value or unsupported format.
                       +-inf / +-inf; +-0 / +-0
#D                      Source is a denormal value.
#Z                     SRC / +-0, where SRC is not equal to +-0.
#U                      Result is too small for destination format.
#O                      Result is too large for destination format.
#P                      Value cannot be represented exactly in destination format.

Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code)        If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#NM                     CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#MF                     If there is a pending x87 FPU exception.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                     If the LOCK prefix is used.






