# instructions

platform: x86_64
mnem: VPGATHERDQ
description:
VPGATHERDQ/VPGATHERQQ - Gather Packed Qword Values Using Signed Dword/Qword
Indices
 Opcode/                                Op/     64/32     CPUID     Description
 Instruction                            En      -bit      Feature
                                                Mode      Flag
 VEX.DDS.128.66.0F38.W1 90 /r           RMV     V/V       AVX2      Using dword indices specified in vm32x, gather qword val-
 VPGATHERDQ xmm1, vm32x, xmm2                                       ues from memory conditioned on mask specified by
                                                                    xmm2. Conditionally gathered elements are merged into
                                                                    xmm1.
 VEX.DDS.128.66.0F38.W1 91 /r           RMV     V/V       AVX2      Using qword indices specified in vm64x, gather qword val-
 VPGATHERQQ xmm1, vm64x, xmm2                                       ues from memory conditioned on mask specified by
                                                                    xmm2. Conditionally gathered elements are merged into
                                                                    xmm1.
 VEX.DDS.256.66.0F38.W1 90 /r           RMV     V/V       AVX2      Using dword indices specified in vm32x, gather qword val-
 VPGATHERDQ ymm1, vm32x, ymm2                                       ues from memory conditioned on mask specified by
                                                                    ymm2. Conditionally gathered elements are merged into
                                                                    ymm1.
 VEX.DDS.256.66.0F38.W1 91 /r           RMV     V/V       AVX2      Using qword indices specified in vm64y, gather qword val-
 VPGATHERQQ ymm1, vm64y, ymm2                                       ues from memory conditioned on mask specified by
                                                                    ymm2. Conditionally gathered elements are merged into
                                                                    ymm1.



                                            Instruction Operand Encoding
   Op/En           Operand 1                  Operand 2                    Operand 3                     Operand 4
     A           ModRM:reg (r,w)         BaseReg (R): VSIB:base,         VEX.vvvv (r, w)                     NA
                                        VectorReg(R): VSIB:index

Description
The instruction conditionally loads up to 2 or 4 qword values from memory addresses specified by the memory
operand (the second operand) and using qword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register for an array of indices relative
to the base and a constant scale factor.
The mask operand (the third operand) specifies the conditional load operation from each memory address and the
corresponding update of each data element of the destination operand (the first operand). Conditionality is speci-
fied by the most significant bit of each data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width of data element in the destination
register and mask register are identical. The entire mask register will be set to zero by this instruction unless the
instruction causes an exception.
Using dword indices in the lower half of the mask register, the instruction conditionally loads up to 2 or 4 qword
values from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask operand are partially updated; those elements that have been gathered are placed into the
destination register and have their mask bits set to zero. If any traps or interrupts are pending from already gath-
ered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
If the data size and index size are different, part of the destination register and part of the mask register do not
correspond to any elements being gathered. This instruction sets those parts to zero. It may do this to one or both
of those registers even if the instruction triggers an exception, and even if the instruction triggers the exception
before gathering any elements.
VEX.128 version: The instruction will gather two qword values. For dword indices, only the lower two indices in the
vector index register are used.




VEX.256 version: The instruction will gather four qword values. For dword indices, only the lower four indices in
the vector index register are used.
Note that:
.   If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault.
.   The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
    64 memory-ordering model.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination will be completed (and non-faulting). Individual elements closer
    to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered in the
    conventional order.
.   Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   This instruction will cause a #UD if the address size attribute is 16-bit.
.   This instruction will cause a #UD if the memory operand is encoded without the SIB byte.
.   This instruction should not be used to access memory mapped I/O as the ordering of the individual loads it does
    is implementation specific, and some implementations may use loads larger than the data element size or load
    elements an indeterminate number of times.
.   The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-
    bit mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address
    bits are ignored.





Operation
DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;

VPGATHERDQ (VEX.128 version)
FOR j<- 0 to 1
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 1
   k <- j * 32;
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)

VPGATHERQQ (VEX.128 version)
FOR j<- 0 to 1
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 1
   i <-j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element cleared)





VPGATHERQQ (VEX.256 version)
FOR j<- 0 to 3
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)

VPGATHERDQ (VEX.256 version)
FOR j<- 0 to 3
   i <- j * 64;
   IF MASK[63+i] THEN
        MASK[i +63:i] <- FFFFFFFF_FFFFFFFFH; // extend from most significant bit
   ELSE
        MASK[i +63:i] <- 0;
   FI;
ENDFOR
FOR j<- 0 to 3
   k <- j * 32;
   i <- j * 64;
   DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
   IF MASK[63+i] THEN
        DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
   FI;
   MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element cleared)





Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERDQ: __m128i _mm_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m128i _mm_mask_i32gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERDQ: __m256i _mm256_i32gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i src, __int64 const * base, __m128i index, __m256i mask, const
int scale);
VPGATHERQQ: __m128i _mm_i64gather_epi64 (__int64 const * base, __m128i index, const int scale);
VPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const * base, __m128i index, __m128i mask, const int
scale);
VPGATHERQQ: __m256i _mm256_i64gather_epi64 __(int64 const * base, __m256i index, const int scale);
VPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const * base, __m256i index, __m256i mask, const
int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 12.






platform: x86_64
mnem: VPGATHERQD
description:
VPGATHERQD/VPGATHERQQ-Gather Packed Dword, Packed Qword with Signed Qword Indices
    Opcode/                            Op/   64/32        CPUID           Description
    Instruction                        En    bit Mode     Feature
                                             Support      Flag
    EVEX.128.66.0F38.W0 91 /vsib       T1S   V/V          AVX512VL        Using signed qword indices, gather dword values from
    VPGATHERQD xmm1 {k1}, vm64x                           AVX512F         memory using writemask k1 for merging-masking.
    EVEX.256.66.0F38.W0 91 /vsib       T1S   V/V          AVX512VL        Using signed qword indices, gather dword values from
    VPGATHERQD xmm1 {k1}, vm64y                           AVX512F         memory using writemask k1 for merging-masking.
    EVEX.512.66.0F38.W0 91 /vsib       T1S   V/V          AVX512F         Using signed qword indices, gather dword values from
    VPGATHERQD ymm1 {k1}, vm64z                                           memory using writemask k1 for merging-masking.
    EVEX.128.66.0F38.W1 91 /vsib       T1S   V/V          AVX512VL        Using signed qword indices, gather quadword values from
    VPGATHERQQ xmm1 {k1}, vm64x                           AVX512F         memory using writemask k1 for merging-masking.
    EVEX.256.66.0F38.W1 91 /vsib       T1S   V/V          AVX512VL        Using signed qword indices, gather quadword values from
    VPGATHERQQ ymm1 {k1}, vm64y                           AVX512F         memory using writemask k1 for merging-masking.
    EVEX.512.66.0F38.W1 91 /vsib       T1S   V/V          AVX512F         Using signed qword indices, gather quadword values from
    VPGATHERQQ zmm1 {k1}, vm64z                                           memory using writemask k1 for merging-masking.



                                               Instruction Operand Encoding
         Op/En             Operand 1                  Operand 2                     Operand 3                  Operand 4
                                                BaseReg (R): VSIB:base,
         T1S             ModRM:reg (w)                                                  NA                         NA
                                               VectorReg(R): VSIB:index

Description
A set of 8 doubleword/quadword memory locations pointed to by base address BASE_ADDR and index vector
VINDEX with scale SCALE are gathered. The result is written into a vector register. The elements are specified via
the VSIB (i.e., the index register is a vector register, holding packed indices). Elements will only be loaded if their
corresponding mask bit is one. If an element's mask bit is not set, the corresponding element of the destination
register is left unchanged. The entire mask register will be set to zero by this instruction unless it triggers an excep-
tion.
This instruction can be suspended by an exception if at least one element is already gathered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated; those elements that have been gathered are placed into
the destination register and have their mask bits set to zero. If any traps or interrupts are pending from already
gathered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruc-
tion breakpoint is not re-triggered when the instruction is continued.
If the data element size is less than the index element size, the higher part of the destination register and the mask
register do not correspond to any elements being gathered. This instruction sets those higher parts to zero. It may
update these unused elements to one or both of those registers even if the instruction triggers an exception, and
even if the instruction triggers the exception before gathering any elements.
Note that:
.     The values may be read from memory in any order. Memory ordering with other instructions follows the Intel-
      64 memory-ordering model.
.     Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
      elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
      closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
      in the conventional order.
.     Elements may be gathered in any order, but faults must be delivered in a right-to-left order; thus, elements to
      the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
      instruction is repeatable - given the same input values and architectural state, the same set of elements to the
      left of the faulting one will be gathered.





.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   Not valid with 16-bit effective addresses. Will deliver a #UD fault.
.   These instructions do not accept zeroing-masking since the 0 values in k1 are used to determine completion.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has the same disp8*N and alignment rules as for scalar instructions (Tuple 1).
The instruction will #UD fault if the destination vector zmm1 is the same as index vector VINDEX. The instruction
will #UD fault if the k0 mask register is specified.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits are
ignored.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement

VPGATHERQD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 64
    IF k1[j]
         THEN DEST[i+31:i] <- MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP]), 1)
               k1[j] <- 0
         ELSE *DEST[i+31:i] <- remains unchanged*     ; Only merging masking is allowed
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL/2] <- 0

VPGATHERQQ (EVEX encoded version)
(KL, VL) = (2, 64), (4, 128), (8, 256)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j]
         THEN DEST[i+63:i] <-
               MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP])
               k1[j] <- 0
         ELSE *DEST[i+63:i] <- remains unchanged*         ; Only merging masking is allowed
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPGATHERQD __m256i _mm512_i64gather_epi32(__m512i vdx, void * base, int scale);
VPGATHERQD __m256i _mm512_mask_i64gather_epi32lo(__m256i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQD __m128i _mm256_mask_i64gather_epi32lo(__m128i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQD __m128i _mm_mask_i64gather_epi32(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_i64gather_epi64( __m512i vdx, void * base, int scale);
VPGATHERQQ __m512i _mm512_mask_i64gather_epi64(__m512i s, __mmask8 k, __m512i vdx, void * base, int scale);
VPGATHERQQ __m256i _mm256_mask_i64gather_epi64(__m256i s, __mmask8 k, __m256i vdx, void * base, int scale);
VPGATHERQQ __m128i _mm_mask_i64gather_epi64(__m128i s, __mmask8 k, __m128i vdx, void * base, int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12.






platform: x86_64
mnem: VGETEXPPD
description:
VGETEXPPD-Convert Exponents of Packed DP FP Values to DP FP Values
 Opcode/                      Op/        64/32        CPUID               Description
 Instruction                  En         bit Mode     Feature
                                         Support      Flag
 EVEX.128.66.0F38.W1 42 /r    FV         V/V          AVX512VL            Convert the exponent of packed double-precision floating-point
 VGETEXPPD xmm1 {k1}{z},                              AVX512F             values in the source operand to DP FP results representing
 xmm2/m128/m64bcst                                                        unbiased integer exponents and stores the results in the
                                                                          destination register.
 EVEX.256.66.0F38.W1 42 /r    FV         V/V          AVX512VL            Convert the exponent of packed double-precision floating-point
 VGETEXPPD ymm1 {k1}{z},                              AVX512F             values in the source operand to DP FP results representing
 ymm2/m256/m64bcst                                                        unbiased integer exponents and stores the results in the
                                                                          destination register.
 EVEX.512.66.0F38.W1 42 /r    FV         V/V          AVX512F             Convert the exponent of packed double-precision floating-point
 VGETEXPPD zmm1 {k1}{z},                                                  values in the source operand to DP FP results representing
 zmm2/m512/m64bcst{sae}                                                   unbiased integer exponents and stores the results in the
                                                                          destination under writemask k1.



                                                Instruction Operand Encoding
      Op/En             Operand 1                          Operand 2                       Operand 3                    Operand 4
        FV            ModRM:reg (w)                     ModRM:r/m (r)                          NA                          NA

Description
Extracts the biased exponents from the normalized DP FP representation of each qword data element of the source
operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input
data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to double-
precision FP value and written to the corresponding qword elements of the destination operand (the first operand)
as DP FP numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 64-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-
sentation). Special cases of input values are listed in Table 5-7.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for the greatest integer not exceeding real number x.

                                           Table 5-7. VGETEXPPD/SD Special Cases
                      Input Operand                 Result                                     Comments
                      src1 = NaN                    QNaN(src1)                                 No Exceptions
                      0 < |src1| < INF              floor(log2(|src1|))
                      | src1| = +INF                +INF
                      | src1| = 0                   -INF





Operation
NormalizeExpTinyDPFP(SRC[63:0])
{
   // Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
   Src.Jbit <- 0;
   Dst.exp <- 1;
   Dst.fraction <- SRC[51:0];
   WHILE(Src.Jbit = 0)
   {
         Src.Jbit <- Dst.fraction[51];             // Get the fraction MSB
         Dst.fraction <- Dst.fraction << 1 ;            // One bit shift left
         Dst.exp-- ;               // Decrement the exponent
   }
   Dst.fraction <- 0;               // zero out fraction bits
   Dst.sign <- 1;                   // Return negative sign
   TMP[63:0] <- MXCSR.DAZ? 0 : (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction) ;
   Return (TMP[63:0]);
}

ConvertExpDPFP(SRC[63:0])
{
   Src.sign <- 0;                // Zero out sign bit
   Src.exp <- SRC[62:52];
   Src.fraction <- SRC[51:0];
   // Check for NaN
   IF (SRC = NaN)
   {
        IF ( SRC = SNAN ) SET IE;
        Return QNAN(SRC);
   }
   // Check for +INF
   IF (SRC = +INF) Return (SRC);

    // check if zero operand
    IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
    }
    ELSE             // check if denormal operand (notice that MXCSR.DAZ = 0)
    {
          IF ((Src.exp = 0) AND (Src.fraction != 0))
          {
                TMP[63:0] <- NormalizeExpTinyDPFP(SRC[63:0]) ;           // Get Normalized Exponent
                Set #DE
          }
          ELSE            // exponent value is correct
          {
                Dst.fraction <- 0;            // zero out fraction bits
                TMP[63:0] <- (Src.sign << 63) OR (Src.exp << 52) OR (Src.fraction) ;
          }
          TMP <- SAR(TMP, 52) ;               // Shift Arithmetic Right
          TMP <- TMP - 1023;                  // Subtract Bias
          Return CvtI2D(TMP) ;               // Convert INT to Double-Precision FP number
    }
}




VGETEXPPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         DEST[i+63:i] <-
               ConvertExpDPFP(SRC[63:0])
                    ELSE
                         DEST[i+63:i] <-
               ConvertExpDPFP(SRC[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPD __m512d _mm512_getexp_pd(__m512d a);
VGETEXPPD __m512d _mm512_mask_getexp_pd(__m512d s, __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_maskz_getexp_pd( __mmask8 k, __m512d a);
VGETEXPPD __m512d _mm512_getexp_round_pd(__m512d a, int sae);
VGETEXPPD __m512d _mm512_mask_getexp_round_pd(__m512d s, __mmask8 k, __m512d a, int sae);
VGETEXPPD __m512d _mm512_maskz_getexp_round_pd( __mmask8 k, __m512d a, int sae);
VGETEXPPD __m256d _mm256_getexp_pd(__m256d a);
VGETEXPPD __m256d _mm256_mask_getexp_pd(__m256d s, __mmask8 k, __m256d a);
VGETEXPPD __m256d _mm256_maskz_getexp_pd( __mmask8 k, __m256d a);
VGETEXPPD __m128d _mm_getexp_pd(__m128d a);
VGETEXPPD __m128d _mm_mask_getexp_pd(__m128d s, __mmask8 k, __m128d a);
VGETEXPPD __m128d _mm_maskz_getexp_pd( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
See Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VGETEXPPS
description:
VGETEXPPS-Convert Exponents of Packed SP FP Values to SP FP Values
 Opcode/                             Op/      64/32         CPUID          Description
 Instruction                         En       bit Mode      Feature
                                              Support       Flag
 EVEX.128.66.0F38.W0 42 /r           FV       V/V           AVX512VL       Convert the exponent of packed single-precision floating-point
 VGETEXPPS xmm1 {k1}{z},                                    AVX512F        values in the source operand to SP FP results representing
 xmm2/m128/m32bcst                                                         unbiased integer exponents and stores the results in the
                                                                           destination register.
 EVEX.256.66.0F38.W0 42 /r           FV       V/V           AVX512VL       Convert the exponent of packed single-precision floating-point
 VGETEXPPS ymm1 {k1}{z},                                    AVX512F        values in the source operand to SP FP results representing
 ymm2/m256/m32bcst                                                         unbiased integer exponents and stores the results in the
                                                                           destination register.
 EVEX.512.66.0F38.W0 42 /r           FV       V/V           AVX512F        Convert the exponent of packed single-precision floating-point
 VGETEXPPS zmm1 {k1}{z},                                                   values in the source operand to SP FP results representing
 zmm2/m512/m32bcst{sae}                                                    unbiased integer exponents and stores the results in the
                                                                           destination register.



                                                     Instruction Operand Encoding
       Op/En                  Operand 1                        Operand 2                   Operand 3                   Operand 4
         FV                 ModRM:reg (w)                   ModRM:r/m (r)                      NA                          NA

Description
Extracts the biased exponents from the normalized SP FP representation of each dword element of the source
operand (the second operand) as unbiased signed integer value, or convert the denormal representation of input
data to unbiased negative integer values. Each integer value of the unbiased exponent is converted to single-preci-
sion FP value and written to the corresponding dword elements of the destination operand (the first operand) as SP
FP numbers.
The destination operand is a ZMM/YMM/XMM register and updated under the writemask. The source operand can
be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from
a 32-bit memory location.
EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-
sentation). Special cases of input values are listed in Table 5-8.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
FP exceptions.

                                                Table 5-8. VGETEXPPS/SS Special Cases
                             Input Operand        Result                              Comments
                             src1 = NaN           QNaN(src1)                          No Exceptions
                             0 < |src1| < INF     floor(log2(|src1|))
                             | src1| = +INF       +INF
                             | src1| = 0          -INF





Figure 5-14 illustrates the VGETEXPPS functionality on input values with normalized representation.



                                          31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
                                          s            exp                                         Fraction
                   Src = 2^1                0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

                   SAR Src, 23 = 080h      0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

                   -Bias                   1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1

                   Tmp - Bias = 1          0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

                   Cvt_PI2PS(01h) = 2^0    0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0




                                    Figure 5-14. VGETEXPPS Functionality On Normal Input values


Operation
NormalizeExpTinySPFP(SRC[31:0])
{
   // Jbit is the hidden integral bit of a FP number. In case of denormal number it has the value of ZERO.
   Src.Jbit <- 0;
   Dst.exp <- 1;
   Dst.fraction <- SRC[22:0];
   WHILE(Src.Jbit = 0)
   {
         Src.Jbit <- Dst.fraction[22];             // Get the fraction MSB
         Dst.fraction <- Dst.fraction << 1 ;       // One bit shift left
         Dst.exp-- ;               // Decrement the exponent
   }
   Dst.fraction <- 0;               // zero out fraction bits
   Dst.sign <- 1;                   // Return negative sign
   TMP[31:0] <- MXCSR.DAZ? 0 : (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction) ;
   Return (TMP[31:0]);
}
ConvertExpSPFP(SRC[31:0])
{
   Src.sign <- 0;                   // Zero out sign bit
   Src.exp <- SRC[30:23];
   Src.fraction <- SRC[22:0];
   // Check for NaN
   IF (SRC = NaN)
   {
         IF ( SRC = SNAN ) SET IE;
         Return QNAN(SRC);
   }
   // Check for +INF
   IF (SRC = +INF) Return (SRC);

   // check if zero operand
   IF ((Src.exp = 0) AND ((Src.fraction = 0) OR (MXCSR.DAZ = 1))) Return (-INF);
   }
   ELSE           // check if denormal operand (notice that MXCSR.DAZ = 0)
   {



        IF ((Src.exp = 0) AND (Src.fraction != 0))
        {
              TMP[31:0] <- NormalizeExpTinySPFP(SRC[31:0]) ;           // Get Normalized Exponent
              Set #DE
        }
        ELSE            // exponent value is correct
        {
              Dst.fraction <- 0;            // zero out fraction bits
              TMP[31:0] <- (Src.sign << 31) OR (Src.exp << 23) OR (Src.fraction) ;
        }
        TMP <- SAR(TMP, 23) ;               // Shift Arithmetic Right
        TMP <- TMP - 127;                   // Subtract Bias
        Return CvtI2D(TMP) ;               // Convert INT to Single-Precision FP number
    }
}

VGETEXPPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         DEST[i+31:i] <-
               ConvertExpSPFP(SRC[31:0])
                    ELSE
                         DEST[i+31:i] <-
               ConvertExpSPFP(SRC[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPPS __m512 _mm512_getexp_ps( __m512 a);
VGETEXPPS __m512 _mm512_mask_getexp_ps(__m512 s, __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_maskz_getexp_ps( __mmask16 k, __m512 a);
VGETEXPPS __m512 _mm512_getexp_round_ps( __m512 a, int sae);
VGETEXPPS __m512 _mm512_mask_getexp_round_ps(__m512 s, __mmask16 k, __m512 a, int sae);
VGETEXPPS __m512 _mm512_maskz_getexp_round_ps( __mmask16 k, __m512 a, int sae);
VGETEXPPS __m256 _mm256_getexp_ps(__m256 a);
VGETEXPPS __m256 _mm256_mask_getexp_ps(__m256 s, __mmask8 k, __m256 a);
VGETEXPPS __m256 _mm256_maskz_getexp_ps( __mmask8 k, __m256 a);
VGETEXPPS __m128 _mm_getexp_ps(__m128 a);
VGETEXPPS __m128 _mm_mask_getexp_ps(__m128 s, __mmask8 k, __m128 a);
VGETEXPPS __m128 _mm_maskz_getexp_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
See Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VGETEXPSD
description:
VGETEXPSD-Convert Exponents of Scalar DP FP Values to DP FP Value
 Opcode/                              Op/     64/32        CPUID         Description
 Instruction                          En      bit Mode     Feature
                                              Support      Flag
 EVEX.NDS.LIG.66.0F38.W1 43 /r        T1S     V/V          AVX512F       Convert the biased exponent (bits 62:52) of the low double-
 VGETEXPSD xmm1 {k1}{z},                                                 precision floating-point value in xmm3/m64 to a DP FP value
 xmm2, xmm3/m64{sae}                                                     representing unbiased integer exponent. Stores the result to
                                                                         the low 64-bit of xmm1 under the writemask k1 and merge
                                                                         with the other elements of xmm2.



                                                  Instruction Operand Encoding
       Op/En                Operand 1                     Operand 2                     Operand 3                   Operand 4
        T1S               ModRM:reg (w)                  EVEX.vvvv (r)                 ModRM:r/m (r)                   NA

Description
Extracts the biased exponent from the normalized DP FP representation of the low qword data element of the
source operand (the third operand) as unbiased signed integer value, or convert the denormal representation of
input data to unbiased negative integer values. The integer value of the unbiased exponent is converted to double-
precision FP value and written to the destination operand (the first operand) as DP FP numbers. Bits (127:64) of
the XMM register destination are copied from corresponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float64 memory location.
The low quadword element of the destination operand is conditionally updated with writemask k1.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-
sentation). Special cases of input values are listed in Table 5-7.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.

Operation
// NormalizeExpTinyDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD

// ConvertExpDPFP(SRC[63:0]) is defined in the Operation section of VGETEXPPD

VGETEXPSD (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[63:0] <-
              ConvertExpDPFP(SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[63:0] <- 0
         FI
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSD __m128d _mm_getexp_sd( __m128d a, __m128d b);
VGETEXPSD __m128d _mm_mask_getexp_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_maskz_getexp_sd( __mmask8 k, __m128d a, __m128d b);
VGETEXPSD __m128d _mm_getexp_round_sd( __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_mask_getexp_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int sae);
VGETEXPSD __m128d _mm_maskz_getexp_round_sd( __mmask8 k, __m128d a, __m128d b, int sae);

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VGETEXPSS
description:
VGETEXPSS-Convert Exponents of Scalar SP FP Values to SP FP Value
 Opcode/                                Op/    64/32         CPUID        Description
 Instruction                            En     bit Mode      Feature
                                               Support       Flag
 EVEX.NDS.LIG.66.0F38.W0 43 /r          T1S    V/V           AVX512F      Convert the biased exponent (bits 30:23) of the low single-
 VGETEXPSS xmm1 {k1}{z}, xmm2,                                            precision floating-point value in xmm3/m32 to a SP FP
 xmm3/m32{sae}                                                            value representing unbiased integer exponent. Stores the
                                                                          result to xmm1 under the writemask k1 and merge with the
                                                                          other elements of xmm2.



                                                   Instruction Operand Encoding
       Op/En                  Operand 1                    Operand 2                    Operand 3                  Operand 4
        T1S                 ModRM:reg (w)                 EVEX.vvvv (r)              ModRM:r/m (r)                     NA

Description
Extracts the biased exponent from the normalized SP FP representation of the low doubleword data element of the
source operand (the third operand) as unbiased signed integer value, or convert the denormal representation of
input data to unbiased negative integer values. The integer value of the unbiased exponent is converted to single-
precision FP value and written to the destination operand (the first operand) as SP FP numbers. Bits (127:32) of
the XMM register destination are copied from corresponding bits in the first source operand.
The destination must be a XMM register, the source operand can be a XMM register or a float32 memory location.
The the low doubleword element of the destination operand is conditionally updated with writemask k1.
Each GETEXP operation converts the exponent value into a FP number (permitting input value in denormal repre-
sentation). Special cases of input values are listed in Table 5-8.
The formula is:
GETEXP(x) = floor(log2(|x|))
Notation floor(x) stands for maximal integer not exceeding real number x.
Software usage of VGETEXPxx and VGETMANTxx instructions generally involve a combination of GETEXP operation
and GETMANT operation (see VGETMANTPD). Thus VGETEXPxx instruction do not require software to handle SIMD
FP exceptions.

Operation
// NormalizeExpTinySPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS

// ConvertExpSPFP(SRC[31:0]) is defined in the Operation section of VGETEXPPS

VGETEXPSS (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[31:0] <-
              ConvertExpDPFP(SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[31:0]<- 0
              FI
    FI;
ENDFOR
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VGETEXPSS __m128 _mm_getexp_ss( __m128 a, __m128 b);
VGETEXPSS __m128 _mm_mask_getexp_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_maskz_getexp_ss( __mmask8 k, __m128 a, __m128 b);
VGETEXPSS __m128 _mm_getexp_round_ss( __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_mask_getexp_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int sae);
VGETEXPSS __m128 _mm_maskz_getexp_round_ss( __mmask8 k, __m128 a, __m128 b, int sae);

SIMD Floating-Point Exceptions
Invalid, Denormal

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VGETMANTPD
description:
VGETMANTPD-Extract Float64 Vector of Normalized Mantissas from Float64 Vector
 Opcode/                                Op/      64/32               CPUID                 Description
 Instruction                            En       bit Mode            Feature
                                                 Support             Flag
 EVEX.128.66.0F3A.W1 26 /r ib           FV       V/V                 AVX512VL              Get Normalized Mantissa from float64 vector
 VGETMANTPD xmm1 {k1}{z},                                            AVX512F               xmm2/m128/m64bcst and store the result in xmm1, using
 xmm2/m128/m64bcst, imm8                                                                   imm8 for sign control and mantissa interval normalization,
                                                                                           under writemask.
 EVEX.256.66.0F3A.W1 26 /r ib           FV       V/V                 AVX512VL              Get Normalized Mantissa from float64 vector
 VGETMANTPD ymm1 {k1}{z},                                            AVX512F               ymm2/m256/m64bcst and store the result in ymm1, using
 ymm2/m256/m64bcst, imm8                                                                   imm8 for sign control and mantissa interval normalization,
                                                                                           under writemask.
 EVEX.512.66.0F3A.W1 26 /r ib           FV       V/V                 AVX512F               Get Normalized Mantissa from float64 vector
 VGETMANTPD zmm1 {k1}{z},                                                                  zmm2/m512/m64bcst and store the result in zmm1, using
 zmm2/m512/m64bcst{sae},                                                                   imm8 for sign control and mantissa interval normalization,
 imm8                                                                                      under writemask.



                                                           Instruction Operand Encoding
        Op/En                 Operand 1                               Operand 2                                        Operand 3                               Operand 4
         FVI                ModRM:reg (w)                          ModRM:r/m (r)                                         Imm8                                         NA

Description
Convert double-precision floating values in the source operand (the second operand) to DP FP values with the
mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.




                        7           6                 5                  4                 3                       2              1                   0

         imm8                        Must Be Zero                                              Sign Control (SC)                Normaiization Interval



                                                                                                                           Imm8[1:0] = 00b : Interval is [ 1, 2)
                                     Imm8[3:2] = 00b : sign(SRC)                                                           Imm8[1:0] = 01b : Interval is [1/2, 2)
                                     Imm8[3:2] = 01b : 0                                                                   Imm8[1:0] = 10b : Interval is [ 1/2, 1)
                                     Imm8[3] = 1b : qNan_Indefinite if sign(SRC) != 0, regardless of imm8[2].              Imm8[1:0] = 11b : Interval is [3/4, 3/2)



                                  Figure 5-15. Imm8 Controls for VGETMANTPD/SD/PS/SS


For each input DP FP value x, The conversion operation is:

         GetMant(x) = +-2k|x.significand|
where:

         1 <= |x.significand| < 2


Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.




If interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in
Figure 5-15.
Each converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b; otherwise instructions will #UD.

                                    Table 5-9. GetMant() Special Float Values Behavior
                Input      Result                                                 Exceptions / Comments
                NaN        QNaN(SRC)                                              Ignore interv
                                                                                  If (SRC = SNaN) then #IE
                +inf         1.0                                                    Ignore interv
                +0         1.0                                                    Ignore interv
                -0         IF (SC[0]) THEN +1.0                                   Ignore interv
                                       ELSE -1.0
                -inf         IF (SC[1]) THEN {QNaN_Indefinite}                      Ignore interv
                           ELSE {                                                 If (SC[1]) then #IE
                             IF (SC[0]) THEN +1.0
                                         ELSE -1.0
                negative   SC[1] ? QNaN_Indefinite : Getmant(SRC)                 If (SC[1]) then #IE





Operation
GetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0])
{
   // Extracting the SRC sign, exponent and mantissa fields
   Dst.sign <- SignCtrl[0] ? 0 : Src[63];                      // Get sign bit
   Dst.exp <- SRC[62:52]; ; Get original exponent value
   Dst.fraction <- SRC[51:0];; Get original fraction value
   ZeroOperand <- (Dst.exp = 0) AND (Dst.fraction = 0);
   DenormOperand <- (Dst.exp = 0h) AND (Dst.fraction != 0);
   InfiniteOperand <- (Dst.exp = 07FFh) AND (Dst.fraction = 0);
   NaNOperand <- (Dst.exp = 07FFh) AND (Dst.fraction != 0);
   // Check for NAN operand
   IF (NaNOperand)
   {     IF (SRC = SNaN) {Set #IE;}
         Return QNAN(SRC);
   }
   // Check for Zero and Infinite operands
   IF ((ZeroOperand) OR (InfiniteOperand)
   {     Dst.exp <- 03FFh;                          // Override exponent with BIAS
         Return ((Dst.sign<<63) | (Dst.exp<<52) | (Dst.fraction));
   }
   // Check for negative operand (including -0.0)
   IF ((Src[63] = 1) AND SignCtrl[1])
   {     Set #IE;
         Return QNaN_Indefinite;
   }
   // Checking for denormal operands
   IF (DenormOperand)
   {     IF (MXCSR.DAZ=1) Dst.fraction <- 0;// Zero out fraction
         ELSE
         {    // Jbit is the hidden integral bit. Zero in case of denormal operand.
              Src.Jbit <- 0;                   // Zero Src Jbit
              Dst.exp <- 03FFh;                // Override exponent with BIAS
              WHILE (Src.Jbit = 0) {          // normalize mantissa
                    Src.Jbit <- Dst.fraction[51];         // Get the fraction MSB
                    Dst.fraction <- (Dst.fraction << 1);             // Start normalizing the mantissa
                    Dst.exp-- ;    // Adjust the exponent
              }
              SET #DE;             // Set DE bit
         }
   }          // At this point, Dst.fraction is normalized.
   // Checking for exponent response
   Unbiased.exp <- Dst.exp - 03FFh;                 // subtract the bias from exponent
   IsOddExp <- Unbiased.exp[0];                     // recognized unbiased ODD exponent
   SignalingBit <- Dst.fraction[51];
   CASE (interv[1:0])
         00: Dst.exp <- 03FFh;                                 // This is the bias
         01: Dst.exp <- (IsOddExp) ? 03FEh : 03FFh;                  // either bias-1, or bias
         10: Dst.exp <- 03FEh;                                 // bias-1
         11: Dst.exp <- (SignalingBit) ? 03FEh : 03FFh;              // either bias-1, or bias
   ESCA
   // At this point Dst.exp has the correct result. Form the final destination
   DEST[63:0] <- (Dst.sign << 63) OR (Dst.exp << 52) OR (Dst.fraction);
   Return (DEST);



}

SignCtrl[1:0] <- IMM8[3:2];
Interv[1:0] <- IMM8[1:0];

VGETMANTPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         DEST[i+63:i] <- GetNormalizedMantissaDP(SRC[63:0], sc, interv)
                    ELSE
                         DEST[i+63:i] <- GetNormalizedMantissaDP(SRC[i+63:i], sc, interv)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPD __m512d _mm512_getmant_pd( __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_mask_getmant_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_maskz_getmant_pd( __mmask8 k, __m512d a, enum intv, enum sgn);
VGETMANTPD __m512d _mm512_getmant_round_pd( __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_mask_getmant_round_pd(__m512d s, __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m512d _mm512_maskz_getmant_round_pd( __mmask8 k, __m512d a, enum intv, enum sgn, int r);
VGETMANTPD __m256d _mm256_getmant_pd( __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_mask_getmant_pd(__m256d s, __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m256d _mm256_maskz_getmant_pd( __mmask8 k, __m256d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_getmant_pd( __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_mask_getmant_pd(__m128d s, __mmask8 k, __m128d a, enum intv, enum sgn);
VGETMANTPD __m128d _mm_maskz_getmant_pd( __mmask8 k, __m128d a, enum intv, enum sgn);

SIMD Floating-Point Exceptions
Denormal, Invalid

Other Exceptions
See Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VGETMANTPS
description:
VGETMANTPS-Extract Float32 Vector of Normalized Mantissas from Float32 Vector
 Opcode/                            Op/     64/32       CPUID          Description
 Instruction                        En      bit Mode    Feature
                                            Support     Flag
 EVEX.128.66.0F3A.W0 26 /r ib       FV      V/V         AVX512VL       Get normalized mantissa from float32 vector
 VGETMANTPS xmm1 {k1}{z},                               AVX512F        xmm2/m128/m32bcst and store the result in xmm1, using
 xmm2/m128/m32bcst, imm8                                               imm8 for sign control and mantissa interval normalization,
                                                                       under writemask.
 EVEX.256.66.0F3A.W0 26 /r ib       FV      V/V         AVX512VL       Get normalized mantissa from float32 vector
 VGETMANTPS ymm1 {k1}{z},                               AVX512F        ymm2/m256/m32bcst and store the result in ymm1, using
 ymm2/m256/m32bcst, imm8                                               imm8 for sign control and mantissa interval normalization,
                                                                       under writemask.
 EVEX.512.66.0F3A.W0 26 /r ib       FV      V/V          AVX512F       Get normalized mantissa from float32 vector
 VGETMANTPS zmm1 {k1}{z},                                              zmm2/m512/m32bcst and store the result in zmm1, using
 zmm2/m512/m32bcst{sae},                                               imm8 for sign control and mantissa interval normalization,
 imm8                                                                  under writemask.



                                                  Instruction Operand Encoding
      Op/En                 Operand 1                    Operand 2                    Operand 3                   Operand 4
       FVI               ModRM:reg (w)                 ModRM:r/m (r)                    Imm8                          NA

Description
Convert single-precision floating values in the source operand (the second operand) to SP FP values with the
mantissa normalization and sign control specified by the imm8 byte, see Figure 5-15. The converted results are
written to the destination operand (the first operand) using writemask k1. The normalized mantissa is specified by
interv (imm8[1:0]) and the sign control (sc) is specified by bits 3:2 of the immediate byte.
The destination operand is a ZMM/YMM/XMM register updated under the writemask. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-
bit memory location.
For each input SP FP value x, The conversion operation is:

         GetMant(x) = +-2k|x.significand|
where:

         1 <= |x.significand| < 2


Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.

if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown
in Figure 5-15.
Each converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into the destination. Elements in zmm1 with the corresponding bit clear in k1 retain their
previous values.
Note: EVEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions will #UD.





Operation
GetNormalizeMantissaSP(SRC[31:0] , SignCtrl[1:0], Interv[1:0])
{
   // Extracting the SRC sign, exponent and mantissa fields
   Dst.sign <- SignCtrl[0] ? 0 : Src[31];                      // Get sign bit
   Dst.exp <- SRC[30:23]; ; Get original exponent value
   Dst.fraction <- SRC[22:0];; Get original fraction value
   ZeroOperand <- (Dst.exp = 0) AND (Dst.fraction = 0);
   DenormOperand <- (Dst.exp = 0h) AND (Dst.fraction != 0);
   InfiniteOperand <- (Dst.exp = 0FFh) AND (Dst.fraction = 0);
   NaNOperand <- (Dst.exp = 0FFh) AND (Dst.fraction != 0);
   // Check for NAN operand
   IF (NaNOperand)
   {     IF (SRC = SNaN) {Set #IE;}
         Return QNAN(SRC);
   }
   // Check for Zero and Infinite operands
   IF ((ZeroOperand) OR (InfiniteOperand)
   {     Dst.exp <- 07Fh;                           // Override exponent with BIAS
         Return ((Dst.sign<<31) | (Dst.exp<<23) | (Dst.fraction));
   }
   // Check for negative operand (including -0.0)
   IF ((Src[31] = 1) AND SignCtrl[1])
   {     Set #IE;
         Return QNaN_Indefinite;
   }
   // Checking for denormal operands
   IF (DenormOperand)
   {     IF (MXCSR.DAZ=1) Dst.fraction <- 0;// Zero out fraction
         ELSE
         {    // Jbit is the hidden integral bit. Zero in case of denormal operand.
              Src.Jbit <- 0;                   // Zero Src Jbit
              Dst.exp <- 07Fh;                 // Override exponent with BIAS
              WHILE (Src.Jbit = 0) {          // normalize mantissa
                    Src.Jbit <- Dst.fraction[22];         // Get the fraction MSB
                    Dst.fraction <- (Dst.fraction << 1);             // Start normalizing the mantissa
                    Dst.exp-- ;    // Adjust the exponent
              }
              SET #DE;             // Set DE bit
         }
   }          // At this point, Dst.fraction is normalized.
   // Checking for exponent response
   Unbiased.exp <- Dst.exp - 07Fh;                  // subtract the bias from exponent
   IsOddExp <- Unbiased.exp[0];                     // recognized unbiased ODD exponent
   SignalingBit <- Dst.fraction[22];
   CASE (interv[1:0])
         00: Dst.exp <- 07Fh;                                  // This is the bias
         01: Dst.exp <- (IsOddExp) ? 07Eh : 07Fh;                    // either bias-1, or bias
         10: Dst.exp <- 07Eh;                                  // bias-1
         11: Dst.exp <- (SignalingBit) ? 07Eh : 07Fh;                // either bias-1, or bias
   ESCA

   // Form the final destination
   DEST[31:0] <- (Dst.sign << 31) OR (Dst.exp << 23) OR (Dst.fraction);



    Return (DEST);
}

SignCtrl[1:0] <- IMM8[3:2];
Interv[1:0] <- IMM8[1:0];

VGETMANTPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         DEST[i+31:i] <- GetNormalizedMantissaSP(SRC[31:0], sc, interv)
                    ELSE
                         DEST[i+31:i] <- GetNormalizedMantissaSP(SRC[i+31:i], sc, interv)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTPS __m512 _mm512_getmant_ps( __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_mask_getmant_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn;
VGETMANTPS __m512 _mm512_maskz_getmant_ps(__mmask16 k, __m512 a, enum intv, enum sgn);
VGETMANTPS __m512 _mm512_getmant_round_ps( __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_mask_getmant_round_ps(__m512 s, __mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m512 _mm512_maskz_getmant_round_ps(__mmask16 k, __m512 a, enum intv, enum sgn, int r);
VGETMANTPS __m256 _mm256_getmant_ps( __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_mask_getmant_ps(__m256 s, __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m256 _mm256_maskz_getmant_ps( __mmask8 k, __m256 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_getmant_ps( __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_mask_getmant_ps(__m128 s, __mmask8 k, __m128 a, enum intv, enum sgn);
VGETMANTPS __m128 _mm_maskz_getmant_ps( __mmask8 k, __m128 a, enum intv, enum sgn);

SIMD Floating-Point Exceptions
Denormal, Invalid

Other Exceptions
See Exceptions Type E2.
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VGETMANTSD
description:
VGETMANTSD-Extract Float64 of Normalized Mantissas from Float64 Scalar
 Opcode/                                Op/   64/32      CPUID        Description
 Instruction                            En    bit Mode   Feature
                                              Support    Flag
 EVEX.NDS.LIG.66.0F3A.W1 27 /r ib       T1S   V/V        AVX512F      Extract the normalized mantissa of the low float64
 VGETMANTSD xmm1 {k1}{z}, xmm2,                                       element in xmm3/m64 using imm8 for sign control and
 xmm3/m64{sae}, imm8                                                  mantissa interval normalization. Store the mantissa to
                                                                      xmm1 under the writemask k1 and merge with the
                                                                      other elements of xmm2.



                                              Instruction Operand Encoding
       Op/En              Operand 1                 Operand 2                   Operand 3                   Operand 4
         T1S            ModRM:reg (w)              EVEX.vvvv (r)              ModRM:r/m (r)                     NA

Description
Convert the double-precision floating values in the low quadword element of the second source operand (the third
operand) to DP FP value with the mantissa normalization and sign control specified by the imm8 byte, see
Figure 5-15. The converted result is written to the low quadword element of the destination operand (the first
operand) using writemask k1. Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control
(sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:

         GetMant(x) = +-2k|x.significand|
where:

         1 <= |x.significand| < 2


Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.
If interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown in
Figure 5-15.
The converted DP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values.





Operation
// GetNormalizeMantissaDP(SRC[63:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD

SignCtrl[1:0] <- IMM8[3:2];
Interv[1:0] <- IMM8[1:0];

VGETMANTSD (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[63:0] <-
             GetNormalizedMantissaDP(SRC2[63:0], sc, interv)
   ELSE
       IF *merging-masking*              ; merging-masking
            THEN *DEST[63:0] remains unchanged*
            ELSE                         ; zeroing-masking
                DEST[63:0] <- 0
       FI
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSD __m128d _mm_getmant_sd( __m128d a, __m128 b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_mask_getmant_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_maskz_getmant_sd( __mmask8 k, __m128 a, __m128d b, enum intv, enum sgn);
VGETMANTSD __m128d _mm_getmant_round_sd( __m128d a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_mask_getmant_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);
VGETMANTSD __m128d _mm_maskz_getmant_round_sd( __mmask8 k, __m128d a, __m128d b, enum intv, enum sgn, int r);

SIMD Floating-Point Exceptions
Denormal, Invalid

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VGETMANTSS
description:
VGETMANTSS-Extract Float32 Vector of Normalized Mantissa from Float32 Vector
 Opcode/                              Op/   64/32        CPUID         Description
 Instruction                          En    bit Mode     Feature
                                            Support      Flag
 EVEX.NDS.LIG.66.0F3A.W0 27 /r ib     T1S   V/V          AVX512F       Extract the normalized mantissa from the low float32
 VGETMANTSS xmm1 {k1}{z}, xmm2,                                        element of xmm3/m32 using imm8 for sign control and
 xmm3/m32{sae}, imm8                                                   mantissa interval normalization, store the mantissa to
                                                                       xmm1 under the writemask k1 and merge with the
                                                                       other elements of xmm2.



                                            Instruction Operand Encoding
      Op/En             Operand 1                 Operand 2                      Operand 3                     Operand 4
       T1S            ModRM:reg (w)              EVEX.vvvv (r)                 ModRM:r/m (r)                      NA

Description
Convert the single-precision floating values in the low doubleword element of the second source operand (the third
operand) to SP FP value with the mantissa normalization and sign control specified by the imm8 byte, see
Figure 5-15. The converted result is written to the low doubleword element of the destination operand (the first
operand) using writemask k1. Bits (127:32) of the XMM register destination are copied from corresponding
bits in the first source operand. The normalized mantissa is specified by interv (imm8[1:0]) and the sign control
(sc) is specified by bits 3:2 of the immediate byte.
The conversion operation is:

         GetMant(x) = +-2k|x.significand|
where:

         1 <= |x.significand| < 2


Unbiased exponent k depends on the interval range defined by interv and whether the exponent of the source is
even or odd. The sign of the final result is determined by sc and the source sign.

if interv != 0 then k = -1, otherwise K = 0. The encoded value of imm8[1:0] and sign control are shown
in Figure 5-15.
The converted SP FP result is encoded according to the sign control, the unbiased exponent k (adding bias) and a
mantissa normalized to the range specified by interv.
The GetMant() function follows Table 5-9 when dealing with floating-point special numbers.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values.





Operation
// GetNormalizeMantissaSP(SRC[31:0], SignCtrl[1:0], Interv[1:0]) is defined in the operation section of VGETMANTPD

SignCtrl[1:0] <- IMM8[3:2];
Interv[1:0] <- IMM8[1:0];

VGETMANTSS (EVEX encoded version)
IF k1[0] OR *no writemask*
    THEN DEST[31:0] <-
             GetNormalizedMantissaSP(SRC2[31:0], sc, interv)
   ELSE
       IF *merging-masking*              ; merging-masking
            THEN *DEST[31:0] remains unchanged*
            ELSE                         ; zeroing-masking
                DEST[31:0] <- 0
       FI
FI;
DEST[127:32] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VGETMANTSS __m128 _mm_getmant_ss( __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_mask_getmant_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_maskz_getmant_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn);
VGETMANTSS __m128 _mm_getmant_round_ss( __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_mask_getmant_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);
VGETMANTSS __m128 _mm_maskz_getmant_round_ss( __mmask8 k, __m128 a, __m128 b, enum intv, enum sgn, int r);

SIMD Floating-Point Exceptions
Denormal, Invalid

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VINSERTF128
description:
VINSERTF128/VINSERTF32x4/VINSERTF64x2/VINSERTF32x8/VINSERTF64x4-Insert Packed
Floating-Point Values
 Opcode/                                Op /     64/32       CPUID        Description
 Instruction                            En       bit Mode    Feature
                                                 Support     Flag
 VEX.NDS.256.66.0F3A.W0 18 /r ib        RVMI     V/V         AVX          Insert 128 bits of packed floating-point values from
 VINSERTF128 ymm1, ymm2,                                                  xmm3/m128 and the remaining values from ymm2
 xmm3/m128, imm8                                                          into ymm1.
 EVEX.NDS.256.66.0F3A.W0 18 /r ib       T4       V/V         AVX512VL     Insert 128 bits of packed single-precision floating-
 VINSERTF32X4 ymm1 {k1}{z}, ymm2,                            AVX512F      point values from xmm3/m128 and the remaining
 xmm3/m128, imm8                                                          values from ymm2 into ymm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W0 18 /r ib       T4       V/V         AVX512F      Insert 128 bits of packed single-precision floating-
 VINSERTF32X4 zmm1 {k1}{z}, zmm2,                                         point values from xmm3/m128 and the remaining
 xmm3/m128, imm8                                                          values from zmm2 into zmm1 under writemask k1.
 EVEX.NDS.256.66.0F3A.W1 18 /r ib       T2       V/V         AVX512VL     Insert 128 bits of packed double-precision floating-
 VINSERTF64X2 ymm1 {k1}{z}, ymm2,                            AVX512DQ     point values from xmm3/m128 and the remaining
 xmm3/m128, imm8                                                          values from ymm2 into ymm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W1 18 /r ib       T2       V/V         AVX512DQ     Insert 128 bits of packed double-precision floating-
 VINSERTF64X2 zmm1 {k1}{z}, zmm2,                                         point values from xmm3/m128 and the remaining
 xmm3/m128, imm8                                                          values from zmm2 into zmm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W0 1A /r ib       T8       V/V         AVX512DQ     Insert 256 bits of packed single-precision floating-
 VINSERTF32X8 zmm1 {k1}{z}, zmm2,                                         point values from ymm3/m256 and the remaining
 ymm3/m256, imm8                                                          values from zmm2 into zmm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W1 1A /r ib       T4       V/V         AVX512F      Insert 256 bits of packed double-precision floating-
 VINSERTF64X4 zmm1 {k1}{z}, zmm2,                                         point values from ymm3/m256 and the remaining
 ymm3/m256, imm8                                                          values from zmm2 into zmm1 under writemask k1.



                                               Instruction Operand Encoding
        Op/En             Operand 1                    Operand 2               Operand 3                    Operand 4
        RVMI            ModRM:reg (w)                  VEX.vvvv               ModRM:r/m (r)                   Imm8
      T2, T4, T8        ModRM:reg (w)                  EVEX.vvvv              ModRM:r/m (r)                   Imm8

Description
VINSERTF128/VINSERTF32x4 and VINSERTF64x2 insert 128-bits of packed floating-point values from the second
source operand (the third operand) into the destination operand (the first operand) at an 128-bit granularity offset
multiplied by imm8[0] (256-bit) or imm8[1:0]. The remaining portions of the destination operand are copied from
the corresponding fields of the first source operand (the second operand). The second source operand can be either
an XMM register or a 128-bit memory location. The destination and first source operands are vector registers.
VINSERTF32x4: The destination operand is a ZMM/YMM register and updated at 32-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF64x2: The destination operand is a ZMM/YMM register and updated at 64-bit granularity according to the
writemask. The high 6/7 bits of the immediate are ignored.
VINSERTF32x8 and VINSERTF64x4 inserts 256-bits of packed floating-point values from the second source operand
(the third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by
imm8[0]. The remaining portions of the destination are copied from the corresponding fields of the first source
operand (the second operand). The second source operand can be either an YMM register or a 256-bit memory
location. The high 7 bits of the immediate are ignored. The destination operand is a ZMM register and updated at
32/64-bit granularity according to the writemask.





Operation
VINSERTF32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC2[127:0]
         1: TMP_DEST[255:128] <- SRC2[127:0]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC2[127:0]
         01: TMP_DEST[255:128] <- SRC2[127:0]
         10: TMP_DEST[383:256] <- SRC2[127:0]
         11: TMP_DEST[511:384] <- SRC2[127:0]
    ESAC.
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTF64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC2[127:0]
         1: TMP_DEST[255:128] <- SRC2[127:0]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC2[127:0]
         01: TMP_DEST[255:128] <- SRC2[127:0]
         10: TMP_DEST[383:256] <- SRC2[127:0]
         11: TMP_DEST[511:384] <- SRC2[127:0]
    ESAC.
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE



            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTF32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC2[255:0]
   1: TMP_DEST[511:256] <- SRC2[255:0]
ESAC.

FOR j <- 0 TO 15
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTF64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC2[255:0]
   1: TMP_DEST[511:256] <- SRC2[255:0]
ESAC.

FOR j <- 0 TO 7
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VINSERTF128 (VEX encoded version)
TEMP[255:0] <-SRC1[255:0]
CASE (imm8[0]) OF
   0: TEMP[127:0] <-SRC2[127:0]
   1: TEMP[255:128] <-SRC2[127:0]
ESAC
DEST <-TEMP

Intel C/C++ Compiler Intrinsic Equivalent
VINSERTF32x4 __m512 _mm512_insertf32x4( __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_mask_insertf32x4(__m512 s, __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m512 _mm512_maskz_insertf32x4( __mmask16 k, __m512 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_insertf32x4( __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_mask_insertf32x4(__m256 s, __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x4 __m256 _mm256_maskz_insertf32x4( __mmask8 k, __m256 a, __m128 b, int imm);
VINSERTF32x8 __m512 _mm512_insertf32x8( __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_mask_insertf32x8(__m512 s, __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF32x8 __m512 _mm512_maskz_insertf32x8( __mmask16 k, __m512 a, __m256 b, int imm);
VINSERTF64x2 __m512d _mm512_insertf64x2( __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_mask_insertf64x2(__m512d s, __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m512d _mm512_maskz_insertf64x2( __mmask8 k, __m512d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_insertf64x2( __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_mask_insertf64x2(__m256d s, __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x2 __m256d _mm256_maskz_insertf64x2( __mmask8 k, __m256d a, __m128d b, int imm);
VINSERTF64x4 __m512d _mm512_insertf64x4( __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_mask_insertf64x4(__m512d s, __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF64x4 __m512d _mm512_maskz_insertf64x4( __mmask8 k, __m512d a, __m256d b, int imm);
VINSERTF128 __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int offset);
VINSERTF128 __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int offset);
VINSERTF128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instruction, see Exceptions Type 6; additionally
#UD                    If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E6NF.






platform: x86_64
mnem: VINSERTI128
description:
VINSERTI128/VINSERTI32x4/VINSERTI64x2/VINSERTI32x8/VINSERTI64x4-Insert Packed
Integer Values
 Opcode/                              Op /    64/32       CPUID          Description
 Instruction                          En      bit Mode    Feature
                                              Support     Flag
 VEX.NDS.256.66.0F3A.W0 38 /r ib      RVMI    V/V         AVX2           Insert 128 bits of integer data from xmm3/m128 and
 VINSERTI128 ymm1, ymm2,                                                 the remaining values from ymm2 into ymm1.
 xmm3/m128, imm8
 EVEX.NDS.256.66.0F3A.W0 38 /r ib     T4      V/V         AVX512VL       Insert 128 bits of packed doubleword integer values
 VINSERTI32X4 ymm1 {k1}{z}, ymm2,                         AVX512F        from xmm3/m128 and the remaining values from
 xmm3/m128, imm8                                                         ymm2 into ymm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W0 38 /r ib     T4      V/V         AVX512F        Insert 128 bits of packed doubleword integer values
 VINSERTI32X4 zmm1 {k1}{z}, zmm2,                                        from xmm3/m128 and the remaining values from
 xmm3/m128, imm8                                                         zmm2 into zmm1 under writemask k1.
 EVEX.NDS.256.66.0F3A.W1 38 /r ib     T2      V/V         AVX512VL       Insert 128 bits of packed quadword integer values
 VINSERTI64X2 ymm1 {k1}{z}, ymm2,                         AVX512DQ       from xmm3/m128 and the remaining values from
 xmm3/m128, imm8                                                         ymm2 into ymm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W1 38 /r ib     T2      V/V         AVX512DQ       Insert 128 bits of packed quadword integer values
 VINSERTI64X2 zmm1 {k1}{z}, zmm2,                                        from xmm3/m128 and the remaining values from
 xmm3/m128, imm8                                                         zmm2 into zmm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W0 3A /r ib     T8      V/V         AVX512DQ       Insert 256 bits of packed doubleword integer values
 VINSERTI32X8 zmm1 {k1}{z}, zmm2,                                        from ymm3/m256 and the remaining values from
 ymm3/m256, imm8                                                         zmm2 into zmm1 under writemask k1.
 EVEX.NDS.512.66.0F3A.W1 3A /r ib     T4      V/V         AVX512F        Insert 256 bits of packed quadword integer values
 VINSERTI64X4 zmm1 {k1}{z}, zmm2,                                        from ymm3/m256 and the remaining values from
 ymm3/m256, imm8                                                         zmm2 into zmm1 under writemask k1.



                                             Instruction Operand Encoding
        Op/En             Operand 1                   Operand 2                 Operand 3                   Operand 4
        RVMI            ModRM:reg (w)                 VEX.vvvv                ModRM:r/m (r)                   Imm8
      T2, T4, T8        ModRM:reg (w)                 EVEX.vvvv               ModRM:r/m (r)                   Imm8

Description
VINSERTI32x4 and VINSERTI64x2 inserts 128-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at an 128-bit granular offset multiplied by imm8[0]
(256-bit) or imm8[1:0]. The remaining portions of the destination are copied from the corresponding fields of the
first source operand (the second operand). The second source operand can be either an XMM register or a 128-bit
memory location. The high 6/7bits of the immediate are ignored. The destination operand is a ZMM/YMM register
and updated at 32 and 64-bit granularity according to the writemask.
VINSERTI32x8 and VINSERTI64x4 inserts 256-bits of packed integer values from the second source operand (the
third operand) into the destination operand (the first operand) at a 256-bit granular offset multiplied by imm8[0].
The remaining portions of the destination are copied from the corresponding fields of the first source operand (the
second operand). The second source operand can be either an YMM register or a 256-bit memory location. The
upper bits of the immediate are ignored. The destination operand is a ZMM register and updated at 32 and 64-bit
granularity according to the writemask.
VINSERTI128 inserts 128-bits of packed integer data from the second source operand (the third operand) into the
destination operand (the first operand) at a 128-bit granular offset multiplied by imm8[0]. The remaining portions
of the destination are copied from the corresponding fields of the first source operand (the second operand). The
second source operand can be either an XMM register or a 128-bit memory location. The high 7 bits of the imme-
diate are ignored. VEX.L must be 1, otherwise attempt to execute this instruction with VEX.L=0 will cause #UD.





Operation
VINSERTI32x4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC2[127:0]
         1: TMP_DEST[255:128] <- SRC2[127:0]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC2[127:0]
         01: TMP_DEST[255:128] <- SRC2[127:0]
         10: TMP_DEST[383:256] <- SRC2[127:0]
         11: TMP_DEST[511:384] <- SRC2[127:0]
    ESAC.
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTI64x2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC2[127:0]
         1: TMP_DEST[255:128] <- SRC2[127:0]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC2[127:0]
         01: TMP_DEST[255:128] <- SRC2[127:0]
         10: TMP_DEST[383:256] <- SRC2[127:0]
         11: TMP_DEST[511:384] <- SRC2[127:0]
    ESAC.
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE



            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTI32x8 (EVEX.U1.512 encoded version)
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC2[255:0]
   1: TMP_DEST[511:256] <- SRC2[255:0]
ESAC.

FOR j <- 0 TO 15
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VINSERTI64x4 (EVEX.512 encoded version)
VL = 512
TEMP_DEST[VL-1:0] <- SRC1[VL-1:0]
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC2[255:0]
   1: TMP_DEST[511:256] <- SRC2[255:0]
ESAC.

FOR j <- 0 TO 7
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VINSERTI128
TEMP[255:0] <-SRC1[255:0]
CASE (imm8[0]) OF
   0: TEMP[127:0] <-SRC2[127:0]
   1: TEMP[255:128] <-SRC2[127:0]
ESAC
DEST <-TEMP

Intel C/C++ Compiler Intrinsic Equivalent
VINSERTI32x4 _mm512i _inserti32x4( __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _mask_inserti32x4(__m512i s, __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 _mm512i _maskz_inserti32x4( __mmask16 k, __m512i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_inserti32x4( __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_mask_inserti32x4(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x4 __m256i _mm256_maskz_inserti32x4( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI32x8 __m512i _mm512_inserti32x8( __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_mask_inserti32x8(__m512i s, __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI32x8 __m512i _mm512_maskz_inserti32x8( __mmask16 k, __m512i a, __m256i b, int imm);
VINSERTI64x2 __m512i _mm512_inserti64x2( __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_mask_inserti64x2(__m512i s, __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m512i _mm512_maskz_inserti64x2( __mmask8 k, __m512i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_inserti64x2( __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_mask_inserti64x2(__m256i s, __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x2 __m256i _mm256_maskz_inserti64x2( __mmask8 k, __m256i a, __m128i b, int imm);
VINSERTI64x4 _mm512_inserti64x4( __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_mask_inserti64x4(__m512i s, __mmask8 k, __m512i a, __m256i b, int imm);
VINSERTI64x4 _mm512_maskz_inserti64x4( __mmask m, __m512i a, __m256i b, int imm);
VINSERTI128 __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int offset);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instruction, see Exceptions Type 6; additionally
#UD                    If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E6NF.






platform: x86_64
mnem: VMASKMOV
description:
VMASKMOV-Conditional SIMD Packed Loads and Stores
Opcode/                                 Op/     64/32-bit CPUID     Description
Instruction                             En      Mode      Feature
                                                          Flag
VEX.NDS.128.66.0F38.W0 2C /r            RVM V/V              AVX    Conditionally load packed single-precision values from
VMASKMOVPS xmm1, xmm2, m128                                         m128 using mask in xmm2 and store in xmm1.
VEX.NDS.256.66.0F38.W0 2C /r            RVM V/V              AVX    Conditionally load packed single-precision values from
VMASKMOVPS ymm1, ymm2, m256                                         m256 using mask in ymm2 and store in ymm1.

VEX.NDS.128.66.0F38.W0 2D /r            RVM V/V              AVX    Conditionally load packed double-precision values from
VMASKMOVPD xmm1, xmm2, m128                                         m128 using mask in xmm2 and store in xmm1.

VEX.NDS.256.66.0F38.W0 2D /r            RVM V/V              AVX    Conditionally load packed double-precision values from
VMASKMOVPD ymm1, ymm2, m256                                         m256 using mask in ymm2 and store in ymm1.

VEX.NDS.128.66.0F38.W0 2E /r            MVR V/V              AVX    Conditionally store packed single-precision values from
VMASKMOVPS m128, xmm1, xmm2                                         xmm2 using mask in xmm1.

VEX.NDS.256.66.0F38.W0 2E /r            MVR V/V              AVX    Conditionally store packed single-precision values from
VMASKMOVPS m256, ymm1, ymm2                                         ymm2 using mask in ymm1.
VEX.NDS.128.66.0F38.W0 2F /r            MVR V/V              AVX    Conditionally store packed double-precision values from
VMASKMOVPD m128, xmm1, xmm2                                         xmm2 using mask in xmm1.

VEX.NDS.256.66.0F38.W0 2F /r            MVR V/V              AVX    Conditionally store packed double-precision values from
VMASKMOVPD m256, ymm1, ymm2                                         ymm2 using mask in ymm1.



                                              Instruction Operand Encoding
   Op/En           Operand 1                   Operand 2                Operand 3                        Operand 4
   RVM           ModRM:reg (w)                VEX.vvvv (r)            ModRM:r/m (r)                         NA
   MVR           ModRM:r/m (w)                VEX.vvvv (r)            ModRM:reg (r)                         NA


Description
Conditionally moves packed data elements from the second source operand into the corresponding data element of
the destination operand, depending on the mask bits associated with each data element. The mask bits are speci-
fied in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instruction. The destination operand is
a memory address for the store form of these instructions. The other operands are both XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.
VMASKMOV should not be used to access memory mapped I/O and un-cached memory as the access and the
ordering of the individual loads or stores it does is implementation specific.





In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.

Operation
VMASKMOVPS -128-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] <- 0

VMASKMOVPS - 256-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0

VMASKMOVPD - 128-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] <- 0

VMASKMOVPD - 256-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0

VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]

VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
IF (SRC1[159]) DEST[159:128] <-SRC2[159:128]
IF (SRC1[191]) DEST[191:160] <- SRC2[191:160]
IF (SRC1[223]) DEST[223:192] <- SRC2[223:192]
IF (SRC1[255]) DEST[255:224] <- SRC2[255:224]





VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]

VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]
IF (SRC1[191]) DEST[191:128] <- SRC2[191:128]
IF (SRC1[255]) DEST[255:192] <- SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent
__m256 _mm256_maskload_ps(float const *a, __m256i mask)
void _mm256_maskstore_ps(float *a, __m256i mask, __m256 b)
__m256d _mm256_maskload_pd(double *a, __m256i mask);
void _mm256_maskstore_pd(double *a, __m256i mask, __m256d b);
__m128 _mm128_maskload_ps(float const *a, __m128i mask)
void _mm128_maskstore_ps(float *a, __m128i mask, __m128 b)
__m128d _mm128_maskload_pd(double *a, __m128i mask);
void _mm128_maskstore_pd(double *a, __m128i mask, __m128d b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 6 (No AC# reported for any mask bit combinations);
additionally
#UD                  If VEX.W = 1.






platform: x86_64
mnem: VPBLENDD
description:
VPBLENDD - Blend Packed Dwords
 Opcode/                                       Op/      64/32   CPUID      Description
 Instruction                                   En       -bit    Feature
                                                        Mode    Flag
 VEX.NDS.128.66.0F3A.W0 02 /r ib               RVMI     V/V     AVX2       Select dwords from xmm2 and xmm3/m128 from
 VPBLENDD xmm1, xmm2, xmm3/m128, imm8                                      mask specified in imm8 and store the values into
                                                                           xmm1.
 VEX.NDS.256.66.0F3A.W0 02 /r ib               RVMI     V/V     AVX2       Select dwords from ymm2 and ymm3/m256 from
 VPBLENDD ymm1, ymm2, ymm3/m256, imm8                                      mask specified in imm8 and store the values into
                                                                           ymm1.



                                            Instruction Operand Encoding
   Op/En            Operand 1                Operand 2                    Operand 3                     Operand 4
   RVMI           ModRM:reg (w)              VEX.vvvv                  ModRM:r/m (r)                      Imm8

Description
Dword elements from the source operand (second operand) are conditionally written to the destination operand
(first operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a
mask that determines whether the corresponding word in the destination is copied from the source. If a bit in the
mask, corresponding to a word, is "1", then the word is copied, else the word is unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.

Operation
VPBLENDD (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]
ELSE DEST[31:0] <- SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]
ELSE DEST[63:32] <- SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]
ELSE DEST[95:64] <- SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]
ELSE DEST[127:96] <- SRC1[127:96]
IF (imm8[4] == 1) THEN DEST[159:128] <- SRC2[159:128]
ELSE DEST[159:128] <- SRC1[159:128]
IF (imm8[5] == 1) THEN DEST[191:160] <- SRC2[191:160]
ELSE DEST[191:160] <- SRC1[191:160]
IF (imm8[6] == 1) THEN DEST[223:192] <- SRC2[223:192]
ELSE DEST[223:192] <- SRC1[223:192]
IF (imm8[7] == 1) THEN DEST[255:224] <- SRC2[255:224]
ELSE DEST[255:224] <- SRC1[255:224]





VPBLENDD (VEX.128 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]
ELSE DEST[31:0] <- SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]
ELSE DEST[63:32] <- SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]
ELSE DEST[95:64] <- SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]
ELSE DEST[127:96] <- SRC1[127:96]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDD:       __m128i _mm_blend_epi32 (__m128i v1, __m128i v2, const int mask)
VPBLENDD:       __m256i _mm256_blend_epi32 (__m256i v1, __m256i v2, const int mask)

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 4; additionally
#UD                  If VEX.W = 1.






platform: x86_64
mnem: VPBLENDMB
description:
VPBLENDMB/VPBLENDMW-Blend Byte/Word Vectors Using an Opmask Control
 Opcode/                            Op /     64/32      CPUID         Description
 Instruction                        En       bit Mode   Feature
                                             Support    Flag
 EVEX.NDS.128.66.0F38.W0 66 /r      FVM      V/V        AVX512VL      Blend byte integer vector xmm2 and byte vector
 VPBLENDMB xmm1 {k1}{z},                                AVX512BW      xmm3/m128 and store the result in xmm1, under control
 xmm2, xmm3/m128                                                      mask.
 EVEX.NDS.256.66.0F38.W0 66 /r      FVM      V/V        AVX512VL      Blend byte integer vector ymm2 and byte vector
 VPBLENDMB ymm1 {k1}{z},                                AVX512BW      ymm3/m256 and store the result in ymm1, under control
 ymm2, ymm3/m256                                                      mask.
 EVEX.NDS.512.66.0F38.W0 66 /r      FVM      V/V        AVX512BW      Blend byte integer vector zmm2 and byte vector
 VPBLENDMB zmm1 {k1}{z},                                              zmm3/m512 and store the result in zmm1, under control
 zmm2, zmm3/m512                                                      mask.
 EVEX.NDS.128.66.0F38.W1 66 /r      FVM      V/V        AVX512VL      Blend word integer vector xmm2 and word vector
 VPBLENDMW xmm1 {k1}{z},                                AVX512BW      xmm3/m128 and store the result in xmm1, under control
 xmm2, xmm3/m128                                                      mask.
 EVEX.NDS.256.66.0F38.W1 66 /r      FVM      V/V        AVX512VL      Blend word integer vector ymm2 and word vector
 VPBLENDMW ymm1 {k1}{z},                                AVX512BW      ymm3/m256 and store the result in ymm1, under control
 ymm2, ymm3/m256                                                      mask.
 EVEX.NDS.512.66.0F38.W1 66 /r      FVM      V/V        AVX512BW      Blend word integer vector zmm2 and word vector
 VPBLENDMW zmm1 {k1}{z},                                              zmm3/m512 and store the result in zmm1, under control
 zmm2, zmm3/m512                                                      mask.



                                                Instruction Operand Encoding
          Op/En                  Operand 1                   Operand 2                  Operand 3             Operand 4
           FVM                 ModRM:reg (w)                 EVEX.vvvv                 ModRM:r/m (r)              NA

Description
Performs an element-by-element blending of byte/word elements between the first source operand byte vector
register and the second source operand byte vector from memory or register, using the instruction mask as
selector. The result is written into the destination byte vector register.
The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit memory location.
The mask is not used as a writemask for this instruction. Instead, the mask is used as an element selector: every
element of the destination is conditionally selected between first source or second source using the value of the
related mask bit (0 for first source, 1 for second source).





Operation
VPBLENDMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- SRC2[i+7:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN DEST[i+7:i] <- SRC1[i+7:i]
                  ELSE                           ; zeroing-masking
                       DEST[i+7:i] <- 0
             FI;
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0;

VPBLENDMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC2[i+15:i]
         ELSE
               IF *merging-masking*               ; merging-masking
                    THEN DEST[i+15:i] <- SRC1[i+15:i]
                    ELSE                          ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMB __m512i _mm512_mask_blend_epi8(__mmask64 m, __m512i a, __m512i b);
VPBLENDMB __m256i _mm256_mask_blend_epi8(__mmask32 m, __m256i a, __m256i b);
VPBLENDMB __m128i _mm_mask_blend_epi8(__mmask16 m, __m128i a, __m128i b);
VPBLENDMW __m512i _mm512_mask_blend_epi16(__mmask32 m, __m512i a, __m512i b);
VPBLENDMW __m256i _mm256_mask_blend_epi16(__mmask16 m, __m256i a, __m256i b);
VPBLENDMW __m128i _mm_mask_blend_epi16(__mmask8 m, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VPBLENDMD
description:
VPBLENDMD/VPBLENDMQ-Blend Int32/Int64 Vectors Using an OpMask Control
 Opcode/                               Op /   64/32       CPUID         Description
 Instruction                           En     bit Mode    Feature
                                              Support     Flag
 EVEX.NDS.128.66.0F38.W0 64 /r         FV     V/V         AVX512VL      Blend doubleword integer vector xmm2 and doubleword
 VPBLENDMD xmm1 {k1}{z},                                  AVX512F       vector xmm3/m128/m32bcst and store the result in
 xmm2, xmm3/m128/m32bcst                                                xmm1, under control mask.
 EVEX.NDS.256.66.0F38.W0 64 /r         FV     V/V         AVX512VL      Blend doubleword integer vector ymm2 and doubleword
 VPBLENDMD ymm1 {k1}{z}, ymm2,                            AVX512F       vector ymm3/m256/m32bcst and store the result in
 ymm3/m256/m32bcst                                                      ymm1, under control mask.
 EVEX.NDS.512.66.0F38.W0 64 /r         FV     V/V         AVX512F       Blend doubleword integer vector zmm2 and doubleword
 VPBLENDMD zmm1 {k1}{z}, zmm2,                                          vector zmm3/m512/m32bcst and store the result in
 zmm3/m512/m32bcst                                                      zmm1, under control mask.
 EVEX.NDS.128.66.0F38.W1 64 /r         FV     V/V         AVX512VL      Blend quadword integer vector xmm2 and quadword
 VPBLENDMQ xmm1 {k1}{z},                                  AVX512F       vector xmm3/m128/m64bcst and store the result in
 xmm2, xmm3/m128/m64bcst                                                xmm1, under control mask.
 EVEX.NDS.256.66.0F38.W1 64 /r         FV     V/V         AVX512VL      Blend quadword integer vector ymm2 and quadword
 VPBLENDMQ ymm1 {k1}{z},                                  AVX512F       vector ymm3/m256/m64bcst and store the result in
 ymm2, ymm3/m256/m64bcst                                                ymm1, under control mask.
 EVEX.NDS.512.66.0F38.W1 64 /r         FV     V/V         AVX512F       Blend quadword integer vector zmm2 and quadword
 VPBLENDMQ zmm1 {k1}{z}, zmm2,                                          vector zmm3/m512/m64bcst and store the result in
 zmm3/m512/m64bcst                                                      zmm1, under control mask.



                                                Instruction Operand Encoding
     Op/En               Operand 1                   Operand 2                  Operand 3                  Operand 4
       FV              ModRM:reg (w)                 EVEX.vvvv                 ModRM:r/m (r)                   NA

Description
Performs an element-by-element blending of dword/qword elements between the first source operand (the second
operand) and the elements of the second source operand (the third operand) using an opmask register as select
control. The blended result is written into the destination.
The destination and first source operands are ZMM registers. The second source operand can be a ZMM register, a
512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element
selector: every element of the destination is conditionally selected between first source or second source using the
value of the related mask bit (0 for the first source operand, 1 for the second source operand).
If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.





Operation
VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no controlmask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                  ; merging-masking
                    THEN DEST[i+31:i] <- SRC1[i+31:i]
                    ELSE                             ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0;

VPBLENDMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no controlmask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                  ; merging-masking
                    THEN DEST[i+31:i] <- SRC1[i+31:i]
                    ELSE                             ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPBLENDMD __m512i _mm512_mask_blend_epi32(__mmask16 k, __m512i a, __m512i b);
VPBLENDMD __m256i _mm256_mask_blend_epi32(__mmask8 m, __m256i a, __m256i b);
VPBLENDMD __m128i _mm_mask_blend_epi32(__mmask8 m, __m128i a, __m128i b);
VPBLENDMQ __m512i _mm512_mask_blend_epi64(__mmask8 k, __m512i a, __m512i b);
VPBLENDMQ __m256i _mm256_mask_blend_epi64(__mmask8 m, __m256i a, __m256i b);
VPBLENDMQ __m128i _mm_mask_blend_epi64(__mmask8 m, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VPBROADCASTB
description:
VPBROADCASTB/VPBROADCASTW/VPBROADCASTD/VPBROADCASTQ - Load with Broadcast Integer Data from General Purpose Register
 Opcode/                              Op /   64/32        CPUID           Description
 Instruction                          En     bit          Feature
                                             Mode         Flag
                                             Support
 EVEX.128.66.0F38.W0 7A /r            T1S    V/V          AVX512VL        Broadcast an 8-bit value from a GPR to all bytes in the
 VPBROADCASTB xmm1 {k1}{z}, reg                           AVX512BW        128-bit destination subject to writemask k1.
 EVEX.256.66.0F38.W0 7A /r            T1S    V/V          AVX512VL        Broadcast an 8-bit value from a GPR to all bytes in the
 VPBROADCASTB ymm1 {k1}{z}, reg                           AVX512BW        256-bit destination subject to writemask k1.
 EVEX.512.66.0F38.W0 7A /r            T1S    V/V          AVX512BW        Broadcast an 8-bit value from a GPR to all bytes in the
 VPBROADCASTB zmm1 {k1}{z}, reg                                           512-bit destination subject to writemask k1.
 EVEX.128.66.0F38.W0 7B /r            T1S    V/V          AVX512VL        Broadcast a 16-bit value from a GPR to all words in the
 VPBROADCASTW xmm1 {k1}{z}, reg                           AVX512BW        128-bit destination subject to writemask k1.
 EVEX.256.66.0F38.W0 7B /r            T1S    V/V          AVX512VL        Broadcast a 16-bit value from a GPR to all words in the
 VPBROADCASTW ymm1 {k1}{z}, reg                           AVX512BW        256-bit destination subject to writemask k1.
 EVEX.512.66.0F38.W0 7B /r            T1S    V/V          AVX512BW        Broadcast a 16-bit value from a GPR to all words in the
 VPBROADCASTW zmm1 {k1}{z}, reg                                           512-bit destination subject to writemask k1.
 EVEX.128.66.0F38.W0 7C /r            T1S    V/V          AVX512VL        Broadcast a 32-bit value from a GPR to all double-words
 VPBROADCASTD xmm1 {k1}{z}, r32                           AVX512F         in the 128-bit destination subject to writemask k1.
 EVEX.256.66.0F38.W0 7C /r            T1S    V/V          AVX512VL        Broadcast a 32-bit value from a GPR to all double-words
 VPBROADCASTD ymm1 {k1}{z}, r32                           AVX512F         in the 256-bit destination subject to writemask k1.
 EVEX.512.66.0F38.W0 7C /r            T1S    V/V          AVX512F         Broadcast a 32-bit value from a GPR to all double-words
 VPBROADCASTD zmm1 {k1}{z}, r32                                           in the 512-bit destination subject to writemask k1.
 EVEX.128.66.0F38.W1 7C /r            T1S    V/N.E.1      AVX512VL        Broadcast a 64-bit value from a GPR to all quad-words in
 VPBROADCASTQ xmm1 {k1}{z}, r64                           AVX512F         the 128-bit destination subject to writemask k1.
 EVEX.256.66.0F38.W1 7C /r            T1S    V/N.E.1      AVX512VL        Broadcast a 64-bit value from a GPR to all quad-words in
 VPBROADCASTQ ymm1 {k1}{z}, r64                           AVX512F         the 256-bit destination subject to writemask k1.
 EVEX.512.66.0F38.W1 7C /r            T1S    V/N.E.1      AVX512F         Broadcast a 64-bit value from a GPR to all quad-words in
 VPBROADCASTQ zmm1 {k1}{z}, r64                                           the 512-bit destination subject to writemask k1.
NOTES:
1. EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                             Instruction Operand Encoding
      Op/En             Operand 1                      Operand 2                   Operand 3                    Operand 4
       T1S            ModRM:reg (w)                 ModRM:r/m (r)                       NA                         NA

Description
Broadcasts a 8-bit, 16-bit, 32-bit or 64-bit value from a general-purpose register (the second operand) to all the
locations in the destination vector register (the first operand) using the writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i <-j * 8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SRC[7:0]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <-j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC[15:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <-j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[31:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <-j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[63:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_mask_set1_epi8(__m512i s, __mmask64 k, int a);
VPBROADCASTB __m512i _mm512_maskz_set1_epi8( __mmask64 k, int a);
VPBROADCASTB __m256i _mm256_mask_set1_epi8(__m256i s, __mmask32 k, int a);
VPBROADCASTB __m256i _mm256_maskz_set1_epi8( __mmask32 k, int a);
VPBROADCASTB __m128i _mm_mask_set1_epi8(__m128i s, __mmask16 k, int a);
VPBROADCASTB __m128i _mm_maskz_set1_epi8( __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_mask_set1_epi32(__m512i s, __mmask16 k, int a);
VPBROADCASTD __m512i _mm512_maskz_set1_epi32( __mmask16 k, int a);
VPBROADCASTD __m256i _mm256_mask_set1_epi32(__m256i s, __mmask8 k, int a);
VPBROADCASTD __m256i _mm256_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTD __m128i _mm_mask_set1_epi32(__m128i s, __mmask8 k, int a);
VPBROADCASTD __m128i _mm_maskz_set1_epi32( __mmask8 k, int a);
VPBROADCASTQ __m512i _mm512_mask_set1_epi64(__m512i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m512i _mm512_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_mask_set1_epi64(__m256i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m256i _mm256_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_mask_set1_epi64(__m128i s, __mmask8 k, __int64 a);
VPBROADCASTQ __m128i _mm_maskz_set1_epi64( __mmask8 k, __int64 a);
VPBROADCASTW __m512i _mm512_mask_set1_epi16(__m512i s, __mmask32 k, int a);
VPBROADCASTW __m512i _mm512_maskz_set1_epi16( __mmask32 k, int a);
VPBROADCASTW __m256i _mm256_mask_set1_epi16(__m256i s, __mmask16 k, int a);
VPBROADCASTW __m256i _mm256_maskz_set1_epi16( __mmask16 k, int a);
VPBROADCASTW __m128i _mm_mask_set1_epi16(__m128i s, __mmask8 k, int a);
VPBROADCASTW __m128i _mm_maskz_set1_epi16( __mmask8 k, int a);

Exceptions
EVEX-encoded instructions, see Exceptions Type E7NM.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPBROADCAST
description:
VPBROADCAST-Load Integer and Broadcast
 Opcode/                                  Op /   64/32      CPUID      Description
 Instruction                              En     bit Mode   Feature
                                                 Support    Flag
 VEX.128.66.0F38.W0 78 /r                 RM     V/V        AVX2       Broadcast a byte integer in the source operand
 VPBROADCASTB xmm1, xmm2/m8                                            to sixteen locations in xmm1.
 VEX.256.66.0F38.W0 78 /r                 RM     V/V        AVX2       Broadcast a byte integer in the source operand
 VPBROADCASTB ymm1, xmm2/m8                                            to thirty-two locations in ymm1.
 EVEX.128.66.0F38.W0 78 /r                T1S    V/V        AVX512VL   Broadcast a byte integer in the source operand
 VPBROADCASTB xmm1{k1}{z}, xmm2/m8                          AVX512BW   to locations in xmm1 subject to writemask k1.
 EVEX.256.66.0F38.W0 78 /r                T1S    V/V        AVX512VL   Broadcast a byte integer in the source operand
 VPBROADCASTB ymm1{k1}{z}, xmm2/m8                          AVX512BW   to locations in ymm1 subject to writemask k1.
 EVEX.512.66.0F38.W0 78 /r                T1S    V/V        AVX512BW   Broadcast a byte integer in the source operand
 VPBROADCASTB zmm1{k1}{z}, xmm2/m8                                     to 64 locations in zmm1 subject to writemask
                                                                       k1.
 VEX.128.66.0F38.W0 79 /r                 RM     V/V        AVX2       Broadcast a word integer in the source
 VPBROADCASTW xmm1, xmm2/m16                                           operand to eight locations in xmm1.
 VEX.256.66.0F38.W0 79 /r                 RM     V/V        AVX2       Broadcast a word integer in the source
 VPBROADCASTW ymm1, xmm2/m16                                           operand to sixteen locations in ymm1.
 EVEX.128.66.0F38.W0 79 /r                T1S    V/V        AVX512VL   Broadcast a word integer in the source
 VPBROADCASTW xmm1{k1}{z}, xmm2/m16                         AVX512BW   operand to locations in xmm1 subject to
                                                                       writemask k1.
 EVEX.256.66.0F38.W0 79 /r                T1S    V/V        AVX512VL   Broadcast a word integer in the source
 VPBROADCASTW ymm1{k1}{z}, xmm2/m16                         AVX512BW   operand to locations in ymm1 subject to
                                                                       writemask k1.
 EVEX.512.66.0F38.W0 79 /r                T1S    V/V        AVX512BW   Broadcast a word integer in the source
 VPBROADCASTW zmm1{k1}{z}, xmm2/m16                                    operand to 32 locations in zmm1 subject to
                                                                       writemask k1.
 VEX.128.66.0F38.W0 58 /r                 RM     V/V        AVX2       Broadcast a dword integer in the source
 VPBROADCASTD xmm1, xmm2/m32                                           operand to four locations in xmm1.
 VEX.256.66.0F38.W0 58 /r                 RM     V/V        AVX2       Broadcast a dword integer in the source
 VPBROADCASTD ymm1, xmm2/m32                                           operand to eight locations in ymm1.
 EVEX.128.66.0F38.W0 58 /r                T1S    V/V        AVX512VL   Broadcast a dword integer in the source
 VPBROADCASTD xmm1 {k1}{z}, xmm2/m32                        AVX512F    operand to locations in xmm1 subject to
                                                                       writemask k1.
 EVEX.256.66.0F38.W0 58 /r                T1S    V/V        AVX512VL   Broadcast a dword integer in the source
 VPBROADCASTD ymm1 {k1}{z}, xmm2/m32                        AVX512F    operand to locations in ymm1 subject to
                                                                       writemask k1.
 EVEX.512.66.0F38.W0 58 /r                T1S    V/V        AVX512F    Broadcast a dword integer in the source
 VPBROADCASTD zmm1 {k1}{z}, xmm2/m32                                   operand to locations in zmm1 subject to
                                                                       writemask k1.
 VEX.128.66.0F38.W0 59 /r                 RM     V/V        AVX2       Broadcast a qword element in source operand
 VPBROADCASTQ xmm1, xmm2/m64                                           to two locations in xmm1.
 VEX.256.66.0F38.W0 59 /r                 RM     V/V        AVX2       Broadcast a qword element in source operand
 VPBROADCASTQ ymm1, xmm2/m64                                           to four locations in ymm1.
 EVEX.128.66.0F38.W1 59 /r                T1S    V/V        AVX512VL   Broadcast a qword element in source operand
 VPBROADCASTQ xmm1 {k1}{z}, xmm2/m64                        AVX512F    to locations in xmm1 subject to writemask k1.
 EVEX.256.66.0F38.W1 59 /r                T1S    V/V        AVX512VL   Broadcast a qword element in source operand
 VPBROADCASTQ ymm1 {k1}{z}, xmm2/m64                        AVX512F    to locations in ymm1 subject to writemask k1.
 EVEX.512.66.0F38.W1 59 /r                T1S    V/V        AVX512F    Broadcast a qword element in source operand
 VPBROADCASTQ zmm1 {k1}{z}, xmm2/m64                                   to locations in zmm1 subject to writemask k1.
 EVEX.128.66.0F38.W0 59 /r                T2     V/V        AVX512VL   Broadcast two dword elements in source
 VBROADCASTI32x2 xmm1 {k1}{z}, xmm2/m64                     AVX512DQ   operand to locations in xmm1 subject to
                                                                       writemask k1.



 Opcode/                                   Op /     64/32         CPUID      Description
 Instruction                               En       bit Mode      Feature
                                                    Support       Flag
 EVEX.256.66.0F38.W0 59 /r                 T2       V/V           AVX512VL   Broadcast two dword elements in source
 VBROADCASTI32x2 ymm1 {k1}{z}, xmm2/m64                           AVX512DQ   operand to locations in ymm1 subject to
                                                                             writemask k1.
 EVEX.512.66.0F38.W0 59 /r                 T2       V/V           AVX512DQ   Broadcast two dword elements in source
 VBROADCASTI32x2 zmm1 {k1}{z}, xmm2/m64                                      operand to locations in zmm1 subject to
                                                                             writemask k1.
 VEX.256.66.0F38.W0 5A /r                  RM       V/V           AVX2       Broadcast 128 bits of integer data in mem to
 VBROADCASTI128 ymm1, m128                                                   low and high 128-bits in ymm1.
 EVEX.256.66.0F38.W0 5A /r                 T4       V/V           AVX512VL   Broadcast 128 bits of 4 doubleword integer
 VBROADCASTI32X4 ymm1 {k1}{z}, m128                               AVX512F    data in mem to locations in ymm1 using
                                                                             writemask k1.
 EVEX.512.66.0F38.W0 5A /r                 T4       V/V           AVX512F    Broadcast 128 bits of 4 doubleword integer
 VBROADCASTI32X4 zmm1 {k1}{z}, m128                                          data in mem to locations in zmm1 using
                                                                             writemask k1.
 EVEX.256.66.0F38.W1 5A /r                 T2       V/V           AVX512VL   Broadcast 128 bits of 2 quadword integer data
 VBROADCASTI64X2 ymm1 {k1}{z}, m128                               AVX512DQ   in mem to locations in ymm1 using writemask
                                                                             k1.
 EVEX.512.66.0F38.W1 5A /r                 T2       V/V           AVX512DQ   Broadcast 128 bits of 2 quadword integer data
 VBROADCASTI64X2 zmm1 {k1}{z}, m128                                          in mem to locations in zmm1 using writemask
                                                                             k1.
 EVEX.512.66.0F38.W0 5B /r                 T8       V/V           AVX512DQ   Broadcast 256 bits of 8 doubleword integer
 VBROADCASTI32X8 zmm1 {k1}{z}, m256                                          data in mem to locations in zmm1 using
                                                                             writemask k1.
 EVEX.512.66.0F38.W1 5B /r                 T4       V/V           AVX512F    Broadcast 256 bits of 4 quadword integer data
 VBROADCASTI64X4 zmm1 {k1}{z}, m256                                          in mem to locations in zmm1 using writemask
                                                                             k1.


                                          Instruction Operand Encoding
       Op/En             Operand 1                 Operand 2                 Operand 3                  Operand 4
        RM             ModRM:reg (w)              ModRM:r/m (r)                 NA                          NA
  T1S, T2, T4, T8      ModRM:reg (w)              ModRM:r/m (r)                 NA                          NA

Description
Load integer data from the source operand (the second operand) and broadcast to all elements of the destination
operand (the first operand).
VEX256-encoded VPBROADCASTB/W/D/Q: The source operand is 8-bit, 16-bit, 32-bit, 64-bit memory location or
the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. The destination operand is a YMM register.
VPBROADCASTI128 support the source operand of 128-bit memory location. Register source encodings for
VPBROADCASTI128 is reserved and will #UD. Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX-encoded VPBROADCASTD/Q: The source operand is a 32-bit, 64-bit memory location or the low 32-bit, 64-
bit data in an XMM register. The destination operand is a ZMM/YMM/XMM register and updated according to the
writemask k1.
VPBROADCASTI32X4 and VPBROADCASTI64X4: The destination operand is a ZMM register and updated according
to the writemask k1. The source operand is 128-bit or 256-bit memory location. Register source encodings for
VBROADCASTI32X4 and VBROADCASTI64X4 are reserved and will #UD.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VPBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.





                                                                                     m32             X0




                    DEST     X0          X0       X0        X0     X0          X0          X0        X0



                           Figure 5-16. VPBROADCASTD Operation (VEX.256 encoded version)




                                                                                     m32             X0




                    DEST     0           0        0         0      X0          X0          X0        X0



                                  Figure 5-17. VPBROADCASTD Operation (128-bit version)




                                                                         m64                    X0




                   DEST           X0                   X0               X0                      X0



                                  Figure 5-18. VPBROADCASTQ Operation (256-bit version)




                                                            m128                X0




                    DEST                     X0                                 X0



                                 Figure 5-19. VBROADCASTI128 Operation (256-bit version)


                                                         m256          X0




                    DEST                 X0                            X0



                               Figure 5-20. VBROADCASTI256 Operation (512-bit version)


Operation
VPBROADCASTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i <-j * 8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SRC[7:0]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <-j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC[15:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTD (128 bit version)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[MAX_VL-1:128] <- 0




VPBROADCASTD (VEX.256 encoded version)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[159:128] <- temp
DEST[191:160] <- temp
DEST[223:192] <- temp
DEST[255:224] <- temp
DEST[MAX_VL-1:256] <- 0

VPBROADCASTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <-j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[31:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTQ (VEX.256 encoded version)
temp <- SRC[63:0]
DEST[63:0] <- temp
DEST[127:64] <- temp
DEST[191:128] <- temp
DEST[255:192] <- temp
DEST[MAX_VL-1:256] <- 0

VPBROADCASTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <-j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[63:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0
VBROADCASTI32x2 (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)



FOR j <- 0 TO KL-1
   i <- j * 32
   n <- (j mod 2) * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- SRC[n+31:n]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTI128 (VEX.256 encoded version)
temp <- SRC[127:0]
DEST[127:0] <- temp
DEST[255:128] <- temp
DEST[MAX_VL-1:256] <- 0

VBROADCASTI32X4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j* 32
    n <- (j modulo 4) * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[n+31:n]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTI64X2 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    n <-(j modulo 2) * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[n+63:n]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+63:i] = 0
               FI
    FI;
ENDFOR;




VBROADCASTI32X8 (EVEX.U1.512 encoded version)
FOR j <- 0 TO 15
   i <- j * 32
   n <-(j modulo 8) * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- SRC[n+31:n]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTI64X4 (EVEX.512 encoded version)
FOR j <- 0 TO 7
   i <- j * 64
   n <- (j modulo 4) * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- SRC[n+63:n]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPBROADCASTB __m512i _mm512_broadcastb_epi8( __m128i a);
VPBROADCASTB __m512i _mm512_mask_broadcastb_epi8(__m512i s, __mmask64 k, __m128i a);
VPBROADCASTB __m512i _mm512_maskz_broadcastb_epi8( __mmask64 k, __m128i a);
VPBROADCASTB __m256i _mm256_broadcastb_epi8(__m128i a);
VPBROADCASTB __m256i _mm256_mask_broadcastb_epi8(__m256i s, __mmask32 k, __m128i a);
VPBROADCASTB __m256i _mm256_maskz_broadcastb_epi8( __mmask32 k, __m128i a);
VPBROADCASTB __m128i _mm_mask_broadcastb_epi8(__m128i s, __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_maskz_broadcastb_epi8( __mmask16 k, __m128i a);
VPBROADCASTB __m128i _mm_broadcastb_epi8(__m128i a);
VPBROADCASTD __m512i _mm512_broadcastd_epi32( __m128i a);
VPBROADCASTD __m512i _mm512_mask_broadcastd_epi32(__m512i s, __mmask16 k, __m128i a);
VPBROADCASTD __m512i _mm512_maskz_broadcastd_epi32( __mmask16 k, __m128i a);
VPBROADCASTD __m256i _mm256_broadcastd_epi32( __m128i a);
VPBROADCASTD __m256i _mm256_mask_broadcastd_epi32(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTD __m256i _mm256_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_broadcastd_epi32(__m128i a);
VPBROADCASTD __m128i _mm_mask_broadcastd_epi32(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTD __m128i _mm_maskz_broadcastd_epi32( __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_broadcastq_epi64( __m128i a);
VPBROADCASTQ __m512i _mm512_mask_broadcastq_epi64(__m512i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m512i _mm512_maskz_broadcastq_epi64( __mmask8 k, __m128i a);



VPBROADCASTQ __m256i _mm256_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m256i _mm256_mask_broadcastq_epi64(__m256i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m256i _mm256_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_broadcastq_epi64(__m128i a);
VPBROADCASTQ __m128i _mm_mask_broadcastq_epi64(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTQ __m128i _mm_maskz_broadcastq_epi64( __mmask8 k, __m128i a);
VPBROADCASTW __m512i _mm512_broadcastw_epi16(__m128i a);
VPBROADCASTW __m512i _mm512_mask_broadcastw_epi16(__m512i s, __mmask32 k, __m128i a);
VPBROADCASTW __m512i _mm512_maskz_broadcastw_epi16( __mmask32 k, __m128i a);
VPBROADCASTW __m256i _mm256_broadcastw_epi16(__m128i a);
VPBROADCASTW __m256i _mm256_mask_broadcastw_epi16(__m256i s, __mmask16 k, __m128i a);
VPBROADCASTW __m256i _mm256_maskz_broadcastw_epi16( __mmask16 k, __m128i a);
VPBROADCASTW __m128i _mm_broadcastw_epi16(__m128i a);
VPBROADCASTW __m128i _mm_mask_broadcastw_epi16(__m128i s, __mmask8 k, __m128i a);
VPBROADCASTW __m128i _mm_maskz_broadcastw_epi16( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_broadcast_i32x2( __m128i a);
VBROADCASTI32x2 __m512i _mm512_mask_broadcast_i32x2(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x2 __m512i _mm512_maskz_broadcast_i32x2( __mmask16 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_broadcast_i32x2( __m128i a);
VBROADCASTI32x2 __m256i _mm256_mask_broadcast_i32x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m256i _mm256_maskz_broadcast_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_broadcastq_i32x2(__m128i a);
VBROADCASTI32x2 __m128i _mm_mask_broadcastq_i32x2(__m128i s, __mmask8 k, __m128i a);
VBROADCASTI32x2 __m128i _mm_maskz_broadcastq_i32x2( __mmask8 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m512i _mm512_mask_broadcast_i32x4(__m512i s, __mmask16 k, __m128i a);
VBROADCASTI32x4 __m512i _mm512_maskz_broadcast_i32x4( __mmask16 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_broadcast_i32x4( __m128i a);
VBROADCASTI32x4 __m256i _mm256_mask_broadcast_i32x4(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI32x4 __m256i _mm256_maskz_broadcast_i32x4( __mmask8 k, __m128i a);
VBROADCASTI32x8 __m512i _mm512_broadcast_i32x8( __m256i a);
VBROADCASTI32x8 __m512i _mm512_mask_broadcast_i32x8(__m512i s, __mmask16 k, __m256i a);
VBROADCASTI32x8 __m512i _mm512_maskz_broadcast_i32x8( __mmask16 k, __m256i a);
VBROADCASTI64x2 __m512i _mm512_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m512i _mm512_mask_broadcast_i64x2(__m512i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m512i _mm512_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_broadcast_i64x2( __m128i a);
VBROADCASTI64x2 __m256i _mm256_mask_broadcast_i64x2(__m256i s, __mmask8 k, __m128i a);
VBROADCASTI64x2 __m256i _mm256_maskz_broadcast_i64x2( __mmask8 k, __m128i a);
VBROADCASTI64x4 __m512i _mm512_broadcast_i64x4( __m256i a);
VBROADCASTI64x4 __m512i _mm512_mask_broadcast_i64x4(__m512i s, __mmask8 k, __m256i a);
VBROADCASTI64x4 __m512i _mm512_maskz_broadcast_i64x4( __mmask8 k, __m256i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, syntax with reg/mem operand, see Exceptions Type E6.
#UD                  If VEX.L = 0 for VPBROADCASTQ, VPBROADCASTI128.
                     If EVEX.L'L = 0 for VBROADCASTI32X4/VBROADCASTI64X2.
                     If EVEX.L'L < 10b for VBROADCASTI32X8/VBROADCASTI64X4.





platform: x86_64
mnem: VPCMPB
description:
VPCMPB/VPCMPUB-Compare Packed Byte Values Into Mask
 Opcode/                              Op/    64/32        CPUID      Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 EVEX.NDS.128.66.0F3A.W0 3F /r ib     FVM    V/V          AVX512VL   Compare packed signed byte values in xmm3/m128 and
                                                          AVX512BW   xmm2 using bits 2:0 of imm8 as a comparison predicate
 VPCMPB k1 {k2}, xmm2,                                               with writemask k2 and leave the result in mask register
 xmm3/m128, imm8                                                     k1.
 EVEX.NDS.256.66.0F3A.W0 3F /r ib     FVM    V/V          AVX512VL   Compare packed signed byte values in ymm3/m256 and
                                                          AVX512BW   ymm2 using bits 2:0 of imm8 as a comparison predicate
 VPCMPB k1 {k2}, ymm2,                                               with writemask k2 and leave the result in mask register
 ymm3/m256, imm8                                                     k1.
 EVEX.NDS.512.66.0F3A.W0 3F /r ib     FVM    V/V          AVX512BW   Compare packed signed byte values in zmm3/m512 and
 VPCMPB k1 {k2}, zmm2,                                               zmm2 using bits 2:0 of imm8 as a comparison predicate
 zmm3/m512, imm8                                                     with writemask k2 and leave the result in mask register
                                                                     k1.
 EVEX.NDS.128.66.0F3A.W0 3E /r ib     FVM    V/V          AVX512VL   Compare packed unsigned byte values in xmm3/m128
                                                          AVX512BW   and xmm2 using bits 2:0 of imm8 as a comparison
 VPCMPUB k1 {k2}, xmm2,                                              predicate with writemask k2 and leave the result in mask
 xmm3/m128, imm8                                                     register k1.
 EVEX.NDS.256.66.0F3A.W0 3E /r ib     FVM    V/V          AVX512VL   Compare packed unsigned byte values in ymm3/m256
                                                          AVX512BW   and ymm2 using bits 2:0 of imm8 as a comparison
 VPCMPUB k1 {k2}, ymm2,                                              predicate with writemask k2 and leave the result in mask
 ymm3/m256, imm8                                                     register k1.
 EVEX.NDS.512.66.0F3A.W0 3E /r ib     FVM    V/V          AVX512BW   Compare packed unsigned byte values in zmm3/m512
 VPCMPUB k1 {k2}, zmm2,                                              and zmm2 using bits 2:0 of imm8 as a comparison
 zmm3/m512, imm8                                                     predicate with writemask k2 and leave the result in mask
                                                                     register k1.



                                               Instruction Operand Encoding
       Op/En                Operand 1                   Operand 2               Operand 3                   Operand 4
        FVM               ModRM:reg (w)                  vvvv (r)             ModRM:r/m (r)                    NA

Description
Performs a SIMD compare of the packed byte values in the second source operand and the first source operand and
returns the results of the comparison to the mask destination operand. The comparison predicate operand (imme-
diate byte) specifies the type of comparison performed on each pair of packed values in the two source operands.
The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPB performs a comparison between pairs of signed byte values.
VPCMPUB performs a comparison between pairs of unsigned byte values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 64/32/16 comparisons are performed with results written to the destination operand under the
writemask k2.





The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-10.


                                    Table 5-10. Pseudo-Op and VPCMP* Implementation
:




                  Pseudo-Op                                         PCMPM Implementation
                  VPCMPEQ* reg1, reg2, reg3                         VPCMP* reg1, reg2, reg3, 0
                  VPCMPLT* reg1, reg2, reg3                         VPCMP*reg1, reg2, reg3, 1
                  VPCMPLE* reg1, reg2, reg3                         VPCMP* reg1, reg2, reg3, 2
                  VPCMPNEQ* reg1, reg2, reg3                        VPCMP* reg1, reg2, reg3, 4
                  VPPCMPNLT* reg1, reg2, reg3                       VPCMP* reg1, reg2, reg3, 5
                  VPCMPNLE* reg1, reg2, reg3                        VPCMP* reg1, reg2, reg3, 6

Operation
CASE (COMPARISON PREDICATE) OF
   0: OP <- EQ;
   1: OP <- LT;
   2: OP <- LE;
   3: OP <- FALSE;
   4: OP <- NEQ ;
   5: OP <- NLT;
   6: OP <- NLE;
   7: OP <- TRUE;
ESAC;

VPCMPB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k2[j] OR *no writemask*
         THEN
              CMP <- SRC1[i+7:i] OP SRC2[i+7:i];
              IF CMP = TRUE
                   THEN DEST[j] <- 1;
                   ELSE DEST[j] <- 0; FI;
         ELSE      DEST[j] = 0               ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





VPCMPUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k2[j] OR *no writemask*
         THEN
              CMP <- SRC1[i+7:i] OP SRC2[i+7:i];
              IF CMP = TRUE
                   THEN DEST[j] <- 1;
                   ELSE DEST[j] <- 0; FI;
         ELSE      DEST[j] = 0               ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPCMPB __mmask64 _mm512_cmp_epi8_mask( __m512i a, __m512i b, int cmp);
VPCMPB __mmask64 _mm512_mask_cmp_epi8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPB __mmask32 _mm256_cmp_epi8_mask( __m256i a, __m256i b, int cmp);
VPCMPB __mmask32 _mm256_mask_cmp_epi8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPB __mmask16 _mm_cmp_epi8_mask( __m128i a, __m128i b, int cmp);
VPCMPB __mmask16 _mm_mask_cmp_epi8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m512i a, __m512i b);
VPCMPB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask64 m, __m512i a, __m512i b);
VPCMPB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m256i a, __m256i b);
VPCMPB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask32 m, __m256i a, __m256i b);
VPCMPB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __m128i a, __m128i b);
VPCMPB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi8_mask( __mmask16 m, __m128i a, __m128i b);
VPCMPUB __mmask64 _mm512_cmp_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);
VPCMPUB __mmask64 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m512i a, __m512i b, int cmp);
VPCMPUB __mmask64 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask64 m, __m512i a, __m512i b, int cmp);
VPCMPUB __mmask32 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m256i a, __m256i b, int cmp);
VPCMPUB __mmask32 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask32 m, __m256i a, __m256i b, int cmp);
VPCMPUB __mmask16 _mm_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __m128i a, __m128i b, int cmp);
VPCMPUB __mmask16 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu8_mask( __mmask16 m, __m128i a, __m128i b, int cmp);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPCMPD
description:
VPCMPD/VPCMPUD-Compare Packed Integer Values into Mask
 Opcode/                             Op/   64/32        CPUID      Description
 Instruction                         En    bit Mode     Feature
                                           Support      Flag
 EVEX.NDS.128.66.0F3A.W0 1F /r ib    FV    V/V          AVX512VL   Compare packed signed doubleword integer values in
 VPCMPD k1 {k2}, xmm2,                                  AVX512F    xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
 xmm3/m128/m32bcst, imm8                                           as a comparison predicate with writemask k2 and leave
                                                                   the result in mask register k1.
 EVEX.NDS.256.66.0F3A.W0 1F /r ib    FV    V/V          AVX512VL   Compare packed signed doubleword integer values in
 VPCMPD k1 {k2}, ymm2,                                  AVX512F    ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
 ymm3/m256/m32bcst, imm8                                           as a comparison predicate with writemask k2 and leave
                                                                   the result in mask register k1.
 EVEX.NDS.512.66.0F3A.W0 1F /r ib    FV    V/V          AVX512F    Compare packed signed doubleword integer values in
 VPCMPD k1 {k2}, zmm2,                                             zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
 zmm3/m512/m32bcst, imm8                                           as a comparison predicate. The comparison results are
                                                                   written to the destination k1 under writemask k2.
 EVEX.NDS.128.66.0F3A.W0 1E /r ib    FV    V/V          AVX512VL   Compare packed unsigned doubleword integer values in
 VPCMPUD k1 {k2}, xmm2,                                 AVX512F    xmm3/m128/m32bcst and xmm2 using bits 2:0 of imm8
 xmm3/m128/m32bcst, imm8                                           as a comparison predicate with writemask k2 and leave
                                                                   the result in mask register k1.
 EVEX.NDS.256.66.0F3A.W0 1E /r ib    FV    V/V          AVX512VL   Compare packed unsigned doubleword integer values in
 VPCMPUD k1 {k2}, ymm2,                                 AVX512F    ymm3/m256/m32bcst and ymm2 using bits 2:0 of imm8
 ymm3/m256/m32bcst, imm8                                           as a comparison predicate with writemask k2 and leave
                                                                   the result in mask register k1.
 EVEX.NDS.512.66.0F3A.W0 1E /r ib    FV    V/V          AVX512F    Compare packed unsigned doubleword integer values in
 VPCMPUD k1 {k2}, zmm2,                                            zmm2 and zmm3/m512/m32bcst using bits 2:0 of imm8
 zmm3/m512/m32bcst, imm8                                           as a comparison predicate. The comparison results are
                                                                   written to the destination k1 under writemask k2.



                                            Instruction Operand Encoding
      Op/En              Operand 1                    Operand 2              Operand 3                   Operand 4
        FV             ModRM:reg (w)             EVEX.vvvv (r)             ModRM:r/m (r)                   Imm8

Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPD/VPCMPUD performs a comparison between pairs of signed/unsigned doubleword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 16/8/4 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-10.





Operation
CASE (COMPARISON PREDICATE) OF
   0: OP <- EQ;
   1: OP <- LT;
   2: OP <- LE;
   3: OP <- FALSE;
   4: OP <- NEQ;
   5: OP <- NLT;
   6: OP <- NLE;
   7: OP <- TRUE;
ESAC;

VPCMPD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k2[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP <- SRC1[i+31:i] OP SRC2[31:0];
                    ELSE CMP <- SRC1[i+31:i] OP SRC2[i+31:i];
               FI;
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPCMPUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k2[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP <- SRC1[i+31:i] OP SRC2[31:0];
                    ELSE CMP <- SRC1[i+31:i] OP SRC2[i+31:i];
               FI;
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPCMPD __mmask16 _mm512_cmp_epi32_mask( __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_mask_cmp_epi32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m512i a, __m512i b);
VPCMPD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_cmp_epu32_mask( __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_mask_cmp_epu32_mask(__mmask16 k, __m512i a, __m512i b, int imm);
VPCMPUD __mmask16 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m512i a, __m512i b);
VPCMPUD __mmask16 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPD __mmask8 _mm256_cmp_epi32_mask( __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_mask_cmp_epi32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m256i a, __m256i b);
VPCMPD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_cmp_epu32_mask( __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_mask_cmp_epu32_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUD __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m256i a, __m256i b);
VPCMPUD __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPD __mmask8 _mm_cmp_epi32_mask( __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_mask_cmp_epi32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi32_mask( __m128i a, __m128i b);
VPCMPD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_cmp_epu32_mask( __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_mask_cmp_epu32_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUD __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu32_mask( __m128i a, __m128i b);
VPCMPUD __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu32_mask(__mmask8 k, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPCMPQ
description:
VPCMPQ/VPCMPUQ-Compare Packed Integer Values into Mask
 Opcode/                                Op/    64/32         CPUID      Description
 Instruction                            En     bit Mode      Feature
                                               Support       Flag
 EVEX.NDS.128.66.0F3A.W1 1F /r ib       FV     V/V           AVX512VL   Compare packed signed quadword integer values in
 VPCMPQ k1 {k2}, xmm2,                                       AVX512F    xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
 xmm3/m128/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.
 EVEX.NDS.256.66.0F3A.W1 1F /r ib       FV     V/V           AVX512VL   Compare packed signed quadword integer values in
 VPCMPQ k1 {k2}, ymm2,                                       AVX512F    ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
 ymm3/m256/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.
 EVEX.NDS.512.66.0F3A.W1 1F /r ib       FV     V/V           AVX512F    Compare packed signed quadword integer values in
 VPCMPQ k1 {k2}, zmm2,                                                  zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
 zmm3/m512/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.
 EVEX.NDS.128.66.0F3A.W1 1E /r ib       FV     V/V           AVX512VL   Compare packed unsigned quadword integer values in
 VPCMPUQ k1 {k2}, xmm2,                                      AVX512F    xmm3/m128/m64bcst and xmm2 using bits 2:0 of imm8
 xmm3/m128/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.
 EVEX.NDS.256.66.0F3A.W1 1E /r ib       FV     V/V           AVX512VL   Compare packed unsigned quadword integer values in
 VPCMPUQ k1 {k2}, ymm2,                                      AVX512F    ymm3/m256/m64bcst and ymm2 using bits 2:0 of imm8
 ymm3/m256/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.
 EVEX.NDS.512.66.0F3A.W1 1E /r ib       FV     V/V           AVX512F    Compare packed unsigned quadword integer values in
 VPCMPUQ k1 {k2}, zmm2,                                                 zmm3/m512/m64bcst and zmm2 using bits 2:0 of imm8
 zmm3/m512/m64bcst, imm8                                                as a comparison predicate with writemask k2 and leave
                                                                        the result in mask register k1.



                                               Instruction Operand Encoding
      Op/En                Operand 1                     Operand 2               Operand 3                  Operand 4
        FV              ModRM:reg (w)                EVEX.vvvv (r)             ModRM:r/m (r)                  Imm8

Description
Performs a SIMD compare of the packed integer values in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPQ/VPCMPUQ performs a comparison between pairs of signed/unsigned quadword integer values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand (first operand) is a mask register k1. Up to 8/4/2 comparisons are
performed with results written to the destination operand under the writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-10.





Operation
CASE (COMPARISON PREDICATE) OF
   0: OP <- EQ;
   1: OP <- LT;
   2: OP <- LE;
   3: OP <- FALSE;
   4: OP <- NEQ;
   5: OP <- NLT;
   6: OP <- NLE;
   7: OP <- TRUE;
ESAC;

VPCMPQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k2[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP <- SRC1[i+63:i] OP SRC2[63:0];
                    ELSE CMP <- SRC1[i+63:i] OP SRC2[i+63:i];
               FI;
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0            ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPCMPUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k2[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP <- SRC1[i+63:i] OP SRC2[63:0];
                    ELSE CMP <- SRC1[i+63:i] OP SRC2[i+63:i];
               FI;
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0            ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPCMPQ __mmask8 _mm512_cmp_epi64_mask( __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_mask_cmp_epi64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m512i a, __m512i b);
VPCMPQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_cmp_epu64_mask( __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_mask_cmp_epu64_mask(__mmask8 k, __m512i a, __m512i b, int imm);
VPCMPUQ __mmask8 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m512i a, __m512i b);
VPCMPUQ __mmask8 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPQ __mmask8 _mm256_cmp_epi64_mask( __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_mask_cmp_epi64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m256i a, __m256i b);
VPCMPQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_cmp_epu64_mask( __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_mask_cmp_epu64_mask(__mmask8 k, __m256i a, __m256i b, int imm);
VPCMPUQ __mmask8 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m256i a, __m256i b);
VPCMPUQ __mmask8 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPQ __mmask8 _mm_cmp_epi64_mask( __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_mask_cmp_epi64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi64_mask( __m128i a, __m128i b);
VPCMPQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi64_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_cmp_epu64_mask( __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_mask_cmp_epu64_mask(__mmask8 k, __m128i a, __m128i b, int imm);
VPCMPUQ __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu64_mask( __m128i a, __m128i b);
VPCMPUQ __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu64_mask(__mmask8 k, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPCMPW
description:
VPCMPW/VPCMPUW-Compare Packed Word Values Into Mask
 Opcode/                            Op/   64/32      CPUID       Description
 Instruction                        En    bit Mode   Feature
                                          Support    Flag
 EVEX.NDS.128.66.0F3A.W1 3F /r ib   FVM   V/V        AVX512VL    Compare packed signed word integers in xmm3/m128
                                                     AVX512BW    and xmm2 using bits 2:0 of imm8 as a comparison
 VPCMPW k1 {k2}, xmm2,                                           predicate with writemask k2 and leave the result in
 xmm3/m128, imm8                                                 mask register k1.
 EVEX.NDS.256.66.0F3A.W1 3F /r ib   FVM   V/V        AVX512VL    Compare packed signed word integers in ymm3/m256
                                                     AVX512BW    and ymm2 using bits 2:0 of imm8 as a comparison
 VPCMPW k1 {k2}, ymm2,                                           predicate with writemask k2 and leave the result in
 ymm3/m256, imm8                                                 mask register k1.
 EVEX.NDS.512.66.0F3A.W1 3F /r ib   FVM   V/V        AVX512BW    Compare packed signed word integers in zmm3/m512
 VPCMPW k1 {k2}, zmm2,                                           and zmm2 using bits 2:0 of imm8 as a comparison
 zmm3/m512, imm8                                                 predicate with writemask k2 and leave the result in
                                                                 mask register k1.
 EVEX.NDS.128.66.0F3A.W1 3E /r ib   FVM   V/V        AVX512VL    Compare packed unsigned word integers in xmm3/m128
                                                     AVX512BW    and xmm2 using bits 2:0 of imm8 as a comparison
 VPCMPUW k1 {k2}, xmm2,                                          predicate with writemask k2 and leave the result in
 xmm3/m128, imm8                                                 mask register k1.
 EVEX.NDS.256.66.0F3A.W1 3E /r ib   FVM   V/V        AVX512VL    Compare packed unsigned word integers in ymm3/m256
                                                     AVX512BW    and ymm2 using bits 2:0 of imm8 as a comparison
 VPCMPUW k1 {k2}, ymm2,                                          predicate with writemask k2 and leave the result in
 ymm3/m256, imm8                                                 mask register k1.
 VPCMPUW k1 {k2}, zmm2,             FVM   V/V        AVX512BW    Compare packed unsigned word integers in zmm3/m512
 zmm3/m512, imm8                                                 and zmm2 using bits 2:0 of imm8 as a comparison
                                                                 predicate with writemask k2 and leave the result in
                                                                 mask register k1.



                                           Instruction Operand Encoding
        Op/En              Operand 1                 Operand 2                  Operand 3             Operand 4
         FVM              ModRM:reg (w)               vvvv (r)                 ModRM:r/m (r)              NA

Description
Performs a SIMD compare of the packed integer word in the second source operand and the first source operand
and returns the results of the comparison to the mask destination operand. The comparison predicate operand
(immediate byte) specifies the type of comparison performed on each pair of packed values in the two source oper-
ands. The result of each comparison is a single mask bit result of 1 (comparison true) or 0 (comparison false).
VPCMPW performs a comparison between pairs of signed word values.
VPCMPUW performs a comparison between pairs of unsigned word values.
The first source operand (second operand) is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand (first operand) is a mask
register k1. Up to 32/16/8 comparisons are performed with results written to the destination operand under the
writemask k2.
The comparison predicate operand is an 8-bit immediate: bits 2:0 define the type of comparison to be performed.
Bits 3 through 7 of the immediate are reserved. Compiler can implement the pseudo-op mnemonic listed in Table
5-10.





Operation
CASE (COMPARISON PREDICATE) OF
   0: OP <- EQ;
   1: OP <- LT;
   2: OP <- LE;
   3: OP <- FALSE;
   4: OP <- NEQ ;
   5: OP <- NLT;
   6: OP <- NLE;
   7: OP <- TRUE;
ESAC;

VPCMPW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k2[j] OR *no writemask*
         THEN
               ICMP <- SRC1[i+15:i] OP SRC2[i+15:i];
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] = 0           ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPCMPUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k2[j] OR *no writemask*
         THEN
               CMP <- SRC1[i+15:i] OP SRC2[i+15:i];
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] = 0           ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPCMPW __mmask32 _mm512_cmp_epi16_mask( __m512i a, __m512i b, int cmp);
VPCMPW __mmask32 _mm512_mask_cmp_epi16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPW __mmask16 _mm256_cmp_epi16_mask( __m256i a, __m256i b, int cmp);
VPCMPW __mmask16 _mm256_mask_cmp_epi16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPW __mmask8 _mm_cmp_epi16_mask( __m128i a, __m128i b, int cmp);
VPCMPW __mmask8 _mm_mask_cmp_epi16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m512i a, __m512i b);
VPCMPW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask32 m, __m512i a, __m512i b);
VPCMPW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m256i a, __m256i b);
VPCMPW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask16 m, __m256i a, __m256i b);
VPCMPW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __m128i a, __m128i b);
VPCMPW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epi16_mask( __mmask8 m, __m128i a, __m128i b);
VPCMPUW __mmask32 _mm512_cmp_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);
VPCMPUW __mmask32 _mm512_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m512i a, __m512i b, int cmp);
VPCMPUW __mmask32 _mm512_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask32 m, __m512i a, __m512i b, int cmp);
VPCMPUW __mmask16 _mm256_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m256i a, __m256i b, int cmp);
VPCMPUW __mmask16 _mm256_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask16 m, __m256i a, __m256i b, int cmp);
VPCMPUW __mmask8 _mm_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __m128i a, __m128i b, int cmp);
VPCMPUW __mmask8 _mm_mask_cmp[eq|ge|gt|le|lt|neq]_epu16_mask( __mmask8 m, __m128i a, __m128i b, int cmp);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPCOMPRESSD
description:
VPCOMPRESSD-Store Sparse Packed Doubleword Integer Values into Dense Memory/Register
 Opcode/                                        Op/     64/32         CPUID        Description
 Instruction                                    En      bit Mode      Feature
                                                        Support       Flag
 EVEX.128.66.0F38.W0 8B /r                      T1S     V/V           AVX512VL     Compress packed doubleword integer values from
 VPCOMPRESSD xmm1/m128 {k1}{z}, xmm2                                  AVX512F      xmm2 to xmm1/m128 using controlmask k1.
 EVEX.256.66.0F38.W0 8B /r                      T1S     V/V           AVX512VL     Compress packed doubleword integer values from
 VPCOMPRESSD ymm1/m256 {k1}{z}, ymm2                                  AVX512F      ymm2 to ymm1/m256 using controlmask k1.
 EVEX.512.66.0F38.W0 8B /r                      T1S     V/V           AVX512F      Compress packed doubleword integer values from
 VPCOMPRESSD zmm1/m512 {k1}{z}, zmm2                                               zmm2 to zmm1/m512 using controlmask k1.



                                                 Instruction Operand Encoding
      Op/En                Operand 1                   Operand 2                       Operand 3               Operand 4
       T1S              ModRM:r/m (w)                 ModRM:reg (r)                       NA                       NA

Description
Compress (store) up to 16/8/4 doubleword integer values from the source operand (second operand) to the desti-
nation operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 16 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VPCOMPRESSD (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE <- 32
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no controlmask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+31:i]
               k <- k + SIZE
    FI;
ENDFOR;





VPCOMPRESSD (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE <- 32
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no controlmask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+31:i]
               k <- k + SIZE
    FI;
ENDFOR
IF *merging-masking*
           THEN *DEST[VL-1:k] remains unchanged*
           ELSE DEST[VL-1:k] <- 0
FI
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSD __m512i _mm512_mask_compress_epi32(__m512i s, __mmask16 c, __m512i a);
VPCOMPRESSD __m512i _mm512_maskz_compress_epi32( __mmask16 c, __m512i a);
VPCOMPRESSD void _mm512_mask_compressstoreu_epi32(void * a, __mmask16 c, __m512i s);
VPCOMPRESSD __m256i _mm256_mask_compress_epi32(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSD __m256i _mm256_maskz_compress_epi32( __mmask8 c, __m256i a);
VPCOMPRESSD void _mm256_mask_compressstoreu_epi32(void * a, __mmask8 c, __m256i s);
VPCOMPRESSD __m128i _mm_mask_compress_epi32(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSD __m128i _mm_maskz_compress_epi32( __mmask8 c, __m128i a);
VPCOMPRESSD void _mm_mask_compressstoreu_epi32(void * a, __mmask8 c, __m128i s);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPCOMPRESSQ
description:
VPCOMPRESSQ-Store Sparse Packed Quadword Integer Values into Dense Memory/Register
 Opcode/                                        Op/    64/32          CPUID          Description
 Instruction                                    En     bit Mode       Feature
                                                       Support        Flag
 EVEX.128.66.0F38.W1 8B /r                      T1S    V/V            AVX512VL       Compress packed quadword integer values from
 VPCOMPRESSQ xmm1/m128 {k1}{z}, xmm2                                  AVX512F        xmm2 to xmm1/m128 using controlmask k1.
 EVEX.256.66.0F38.W1 8B /r                      T1S    V/V            AVX512VL       Compress packed quadword integer values from
 VPCOMPRESSQ ymm1/m256 {k1}{z}, ymm2                                  AVX512F        ymm2 to ymm1/m256 using controlmask k1.
 EVEX.512.66.0F38.W1 8B /r                      T1S    V/V            AVX512F        Compress packed quadword integer values from
 VPCOMPRESSQ zmm1/m512 {k1}{z}, zmm2                                                 zmm2 to zmm1/m512 using controlmask k1.



                                                 Instruction Operand Encoding
      Op/En               Operand 1                    Operand 2                       Operand 3                  Operand 4
       T1S              ModRM:r/m (w)                 ModRM:reg (r)                       NA                         NA

Description
Compress (stores) up to 8/4/2 quadword integer values from the source operand (second operand) to the destina-
tion operand (first operand). The source operand is a ZMM/YMM/XMM register, the destination operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VPCOMPRESSQ (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <- 64
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no controlmask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+63:i]
               k <- k + SIZE
    FI;
ENFOR





VPCOMPRESSQ (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <- 64
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no controlmask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+63:i]
               k <- k + SIZE
    FI;
ENDFOR
IF *merging-masking*
           THEN *DEST[VL-1:k] remains unchanged*
           ELSE DEST[VL-1:k] <- 0
FI
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPCOMPRESSQ __m512i _mm512_mask_compress_epi64(__m512i s, __mmask8 c, __m512i a);
VPCOMPRESSQ __m512i _mm512_maskz_compress_epi64( __mmask8 c, __m512i a);
VPCOMPRESSQ void _mm512_mask_compressstoreu_epi64(void * a, __mmask8 c, __m512i s);
VPCOMPRESSQ __m256i _mm256_mask_compress_epi64(__m256i s, __mmask8 c, __m256i a);
VPCOMPRESSQ __m256i _mm256_maskz_compress_epi64( __mmask8 c, __m256i a);
VPCOMPRESSQ void _mm256_mask_compressstoreu_epi64(void * a, __mmask8 c, __m256i s);
VPCOMPRESSQ __m128i _mm_mask_compress_epi64(__m128i s, __mmask8 c, __m128i a);
VPCOMPRESSQ __m128i _mm_maskz_compress_epi64( __mmask8 c, __m128i a);
VPCOMPRESSQ void _mm_mask_compressstoreu_epi64(void * a, __mmask8 c, __m128i s);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPCONFLICTD
description:
VPCONFLICTD/VPCONFLICTQ-Detect Conflicts Within a Vector of Packed Dword/Qword Values into Dense
Memory/ Register
 Opcode/                                       Op/     64/32         CPUID          Description
 Instruction                                   En      bit Mode      Feature
                                                       Support       Flag
 EVEX.128.66.0F38.W0 C4 /r                     FV      V/V           AVX512VL       Detect duplicate double-word values in
 VPCONFLICTD xmm1 {k1}{z},                                           AVX512CD       xmm2/m128/m32bcst using writemask k1.
 xmm2/m128/m32bcst

 EVEX.256.66.0F38.W0 C4 /r                     FV      V/V           AVX512VL       Detect duplicate double-word values in
 VPCONFLICTD ymm1 {k1}{z},                                           AVX512CD       ymm2/m256/m32bcst using writemask k1.
 ymm2/m256/m32bcst

 EVEX.512.66.0F38.W0 C4 /r                     FV      V/V           AVX512CD       Detect duplicate double-word values in
 VPCONFLICTD zmm1 {k1}{z},                                                          zmm2/m512/m32bcst using writemask k1.
 zmm2/m512/m32bcst

 EVEX.128.66.0F38.W1 C4 /r                     FV      V/V           AVX512VL       Detect duplicate quad-word values in
 VPCONFLICTQ xmm1 {k1}{z},                                           AVX512CD       xmm2/m128/m64bcst using writemask k1.
 xmm2/m128/m64bcst

 EVEX.256.66.0F38.W1 C4 /r                     FV      V/V           AVX512VL       Detect duplicate quad-word values in
 VPCONFLICTQ ymm1 {k1}{z},                                           AVX512CD       ymm2/m256/m64bcst using writemask k1.
 ymm2/m256/m64bcst

 EVEX.512.66.0F38.W1 C4 /r                     FV      V/V           AVX512CD       Detect duplicate quad-word values in
 VPCONFLICTQ zmm1 {k1}{z},                                                          zmm2/m512/m64bcst using writemask k1.
 zmm2/m512/m64bcst



                                                    Instruction Operand Encoding
     Op/En                Operand 1                      Operand 2                      Operand 3                  Operand 4
       FV               ModRM:reg (w)                  ModRM:r/m (r)                       NA                         NA

Description
Test each dword/qword element of the source operand (the second operand) for equality with all other elements in
the source operand closer to the least significant element. Each element's comparison results form a bit vector,
which is then zero extended and written to the destination according to the writemask.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPCONFLICTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j*32
    IF MaskBit(j) OR *no writemask*THEN
         FOR k <- 0 TO j-1
               m <- k*32
               IF ((SRC[i+31:i] = SRC[m+31:m])) THEN
                     DEST[i+k] <- 1
               ELSE
                     DEST[i+k] <- 0
               FI
         ENDFOR
         DEST[i+31:i+j] <- 0
    ELSE
         IF *merging-masking* THEN
               *DEST[i+31:i] remains unchanged*
         ELSE
               DEST[i+31:i] <- 0
         FI
    FI
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPCONFLICTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
     i <- j*64
     IF MaskBit(j) OR *no writemask*THEN
         FOR k <- 0 TO j-1
             m <- k*64
                IF ((SRC[i+63:i] = SRC[m+63:m])) THEN
                     DEST[i+k] <- 1
                ELSE
                     DEST[i+k] <- 0
           FI
        ENDFOR
        DEST[i+63:i+j] <- 0
   ELSE
       IF *merging-masking* THEN
            *DEST[i+63:i] remains unchanged*
        ELSE
            DEST[i+63:i] <- 0
        FI
   FI
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent

VPCONFLICTD __m512i _mm512_conflict_epi32( __m512i a);
VPCONFLICTD __m512i _mm512_mask_conflict_epi32(__m512i s, __mmask16 m, __m512i a);
VPCONFLICTD __m512i _mm512_maskz_conflict_epi32(__mmask16 m, __m512i a);
VPCONFLICTQ __m512i _mm512_conflict_epi64( __m512i a);
VPCONFLICTQ __m512i _mm512_mask_conflict_epi64(__m512i s, __mmask8 m, __m512i a);
VPCONFLICTQ __m512i _mm512_maskz_conflict_epi64(__mmask8 m, __m512i a);
VPCONFLICTD __m256i _mm256_conflict_epi32( __m256i a);
VPCONFLICTD __m256i _mm256_mask_conflict_epi32(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTD __m256i _mm256_maskz_conflict_epi32(__mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_conflict_epi64( __m256i a);
VPCONFLICTQ __m256i _mm256_mask_conflict_epi64(__m256i s, __mmask8 m, __m256i a);
VPCONFLICTQ __m256i _mm256_maskz_conflict_epi64(__mmask8 m, __m256i a);
VPCONFLICTD __m128i _mm_conflict_epi32( __m128i a);
VPCONFLICTD __m128i _mm_mask_conflict_epi32(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTD __m128i _mm_maskz_conflict_epi32(__mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_conflict_epi64( __m128i a);
VPCONFLICTQ __m128i _mm_mask_conflict_epi64(__m128i s, __mmask8 m, __m128i a);
VPCONFLICTQ __m128i _mm_maskz_conflict_epi64(__mmask8 m, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPERM2F128
description:
VPERM2F128 - Permute Floating-Point Values
 Opcode/                                            Op/     64/32 bit   CPUID         Description
 Instruction                                        En      Mode        Feature
                                                            Support     Flag
 VEX.NDS.256.66.0F3A.W0 06 /r ib                    RVMI V/V            AVX           Permute 128-bit floating-point fields in ymm2
 VPERM2F128 ymm1, ymm2, ymm3/m256, imm8                                               and ymm3/mem using controls from imm8 and
                                                                                      store result in ymm1.



                                              Instruction Operand Encoding
    Op/En            Operand 1                     Operand 2                      Operand 3                       Operand 4
    RVMI           ModRM:reg (w)                VEX.vvvv (r)                  ModRM:r/m (r)                          imm8


Description
Permute 128 bit floating-point-containing fields from the first source operand (second operand) and second source
operand (third operand) using bits in the 8-bit immediate and store results in the destination operand (first
operand). The first source operand is a YMM register, the second source operand is a YMM register or a 256-bit
memory location, and the destination operand is a YMM register.




                       SRC2                   Y1                                         Y0




                       SRC1                   X1                                         X0




                       DEST             X0, X1, Y0, or Y1                         X0, X1, Y0, or Y1




                                         Figure 5-21. VPERM2F128 Operation

Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.





Operation
VPERM2F128
CASE IMM8[1:0] of
0: DEST[127:0] <- SRC1[127:0]
1: DEST[127:0] <- SRC1[255:128]
2: DEST[127:0] <- SRC2[127:0]
3: DEST[127:0] <- SRC2[255:128]
ESAC

CASE IMM8[5:4] of
0: DEST[255:128] <- SRC1[127:0]
1: DEST[255:128] <- SRC1[255:128]
2: DEST[255:128] <- SRC2[127:0]
3: DEST[255:128] <- SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] <- 0
FI

IF (imm8[7])
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent
VPERM2F128:          __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int control)
VPERM2F128:          __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int control)
VPERM2F128:          __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int control)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 6; additionally
#UD                     If VEX.L = 0
                        If VEX.W = 1.






platform: x86_64
mnem: VPERM2I128
description:
VPERM2I128 - Permute Integer Values
 Opcode/                                            Op/       64/32   CPUID       Description
 Instruction                                        En        -bit    Feature
                                                              Mode    Flag
 VEX.NDS.256.66.0F3A.W0 46 /r ib                    RVMI      V/V     AVX2        Permute 128-bit integer data in ymm2 and
 VPERM2I128 ymm1, ymm2, ymm3/m256, imm8                                           ymm3/mem using controls from imm8 and
                                                                                  store result in ymm1.



                                              Instruction Operand Encoding
   Op/En             Operand 1                     Operand 2                    Operand 3                         Operand 4
    RVMI           ModRM:reg (w)                   VEX.vvvv                 ModRM:r/m (r)                           Imm8

Description
Permute 128 bit integer data from the first source operand (second operand) and second source operand (third
operand) using bits in the 8-bit immediate and store results in the destination operand (first operand). The first
source operand is a YMM register, the second source operand is a YMM register or a 256-bit memory location, and
the destination operand is a YMM register.




                       SRC2                   Y1                                       Y0




                       SRC1                   X1                                       X0




                       DEST             X0, X1, Y0, or Y1                       X0, X1, Y0, or Y1




                                         Figure 5-22. VPERM2I128 Operation

Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4] select the source for the second
destination field. If imm8[3] is set, the low 128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.





Operation
VPERM2I128
CASE IMM8[1:0] of
0: DEST[127:0] <- SRC1[127:0]
1: DEST[127:0] <- SRC1[255:128]
2: DEST[127:0] <- SRC2[127:0]
3: DEST[127:0] <- SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] <- SRC1[127:0]
1: DEST[255:128] <- SRC1[255:128]
2: DEST[255:128] <- SRC2[127:0]
3: DEST[255:128] <- SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] <- 0
FI

IF (imm8[7])
DEST[255:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent
VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 6; additionally
#UD                    If VEX.L = 0,
                       If VEX.W = 1.






platform: x86_64
mnem: VPERMD
description:
VPERMD/VPERMW-Permute Packed Doublewords/Words Elements
 Opcode/                               Op /   64/32      CPUID         Description
 Instruction                           En     bit Mode   Feature
                                              Support    Flag
 VEX.NDS.256.66.0F38.W0 36 /r          RVM    V/V        AVX2          Permute doublewords in ymm3/m256 using indices in
 VPERMD ymm1, ymm2, ymm3/m256                                          ymm2 and store the result in ymm1.
 EVEX.NDS.256.66.0F38.W0 36 /r         FV     V/V        AVX512VL      Permute doublewords in ymm3/m256/m32bcst using
 VPERMD ymm1 {k1}{z}, ymm2,                              AVX512F       indexes in ymm2 and store the result in ymm1 using
 ymm3/m256/m32bcst                                                     writemask k1.
 EVEX.NDS.512.66.0F38.W0 36 /r         FV     V/V        AVX512F       Permute doublewords in zmm3/m512/m32bcst using
 VPERMD zmm1 {k1}{z}, zmm2,                                            indices in zmm2 and store the result in zmm1 using
 zmm3/m512/m32bcst                                                     writemask k1.
 EVEX.NDS.128.66.0F38.W1 8D /r         FVM    V/V        AVX512VL      Permute word integers in xmm3/m128 using indexes
                                                         AVX512BW      in xmm2 and store the result in xmm1 using writemask
 VPERMW xmm1 {k1}{z}, xmm2,                                            k1.
 xmm3/m128
 EVEX.NDS.256.66.0F38.W1 8D /r         FVM    V/V        AVX512VL      Permute word integers in ymm3/m256 using indexes
                                                         AVX512BW      in ymm2 and store the result in ymm1 using writemask
 VPERMW ymm1 {k1}{z}, ymm2,                                            k1.
 ymm3/m256
 EVEX.NDS.512.66.0F38.W1 8D /r         FVM    V/V        AVX512BW     Permute word integers in zmm3/m512 using indexes
 VPERMW zmm1 {k1}{z}, zmm2,                                           in zmm2 and store the result in zmm1 using writemask
 zmm3/m512                                                            k1.



                                              Instruction Operand Encoding
       Op/En             Operand 1                  Operand 2                 Operand 3                  Operand 4
       RVM             ModRM:reg (w)                VEX.vvvv                ModRM:r/m (r)                    NA
        FV             ModRM:reg (w)                EVEX.vvvv               ModRM:r/m (r)                    NA
       FVM             ModRM:reg (w)                VEX.vvvv                ModRM:r/m (r)                    NA

Description
Copies doublewords (or words) from the second source operand (the third operand) to the destination operand (the
first operand) according to the indices in the first source operand (the second operand). Note that this instruction
permits a doubleword (word) in the source operand to be copied to more than one location in the destination
operand.
VEX.256 encoded VPERMD: The first and second operands are YMM registers, the third operand can be a YMM
register or memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded VPERMD: The first and second operands are ZMM/YMM registers, the third operand can be a
ZMM/YMM register, a 512/256-bit memory location or a 512/256-bit vector broadcasted from a 32-bit memory
location. The elements in the destination are updated using the writemask k1.
VPERMW: first and second operands are ZMM/YMM/XMM registers, the third operand can be a ZMM/YMM/XMM
register, or a 512/256/128-bit memory location. The destination is updated using the writemask k1.
EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.





Operation
VPERMD (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
IF VL = 256 THEN n <- 2; FI;
IF VL = 512 THEN n <- 3; FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    id <- 32*SRC1[i+n:i]
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC2[31:0];
                    ELSE DEST[i+31:i] <- SRC2[id+31:id];
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMD (VEX.256 encoded version)
DEST[31:0] <- (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] <- (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] <- (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] <- (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] <- (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] <- (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] <- (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] <- (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAX_VL-1:256] <- 0

VPERMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128 THEN n <- 2; FI;
IF VL = 256 THEN n <- 3; FI;
IF VL = 512 THEN n <- 4; FI;
FOR j <- 0 TO KL-1
    i <- j * 16
    id <- 16*SRC1[i+n:i]
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC2[id+15:id]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



Intel C/C++ Compiler Intrinsic Equivalent
VPERMD __m512i _mm512_permutexvar_epi32( __m512i idx, __m512i a);
VPERMD __m512i _mm512_mask_permutexvar_epi32(__m512i s, __mmask16 k, __m512i idx, __m512i a);
VPERMD __m512i _mm512_maskz_permutexvar_epi32( __mmask16 k, __m512i idx, __m512i a);
VPERMD __m256i _mm256_permutexvar_epi32( __m256i idx, __m256i a);
VPERMD __m256i _mm256_mask_permutexvar_epi32(__m256i s, __mmask8 k, __m256i idx, __m256i a);
VPERMD __m256i _mm256_maskz_permutexvar_epi32( __mmask8 k, __m256i idx, __m256i a);
VPERMW __m512i _mm512_permutexvar_epi16( __m512i idx, __m512i a);
VPERMW __m512i _mm512_mask_permutexvar_epi16(__m512i s, __mmask32 k, __m512i idx, __m512i a);
VPERMW __m512i _mm512_maskz_permutexvar_epi16( __mmask32 k, __m512i idx, __m512i a);
VPERMW __m256i _mm256_permutexvar_epi16( __m256i idx, __m256i a);
VPERMW __m256i _mm256_mask_permutexvar_epi16(__m256i s, __mmask16 k, __m256i idx, __m256i a);
VPERMW __m256i _mm256_maskz_permutexvar_epi16( __mmask16 k, __m256i idx, __m256i a);
VPERMW __m128i _mm_permutexvar_epi16( __m128i idx, __m128i a);
VPERMW __m128i _mm_mask_permutexvar_epi16(__m128i s, __mmask8 k, __m128i idx, __m128i a);
VPERMW __m128i _mm_maskz_permutexvar_epi16( __mmask8 k, __m128i idx, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPERMD, see Exceptions Type E4NF.
EVEX-encoded VPERMW, see Exceptions Type E4NF.nb.
#UD                    If VEX.L = 0.
                       If EVEX.L'L = 0 for VPERMD.






platform: x86_64
mnem: VPERMI2W
description:
VPERMI2W/VPERMI2D/VPERMI2Q/VPERMI2PS/VPERMI2PD-Full Permute From Two Tables Overwriting the Index
 Opcode/                                    Op /   64/32        CPUID      Description
 Instruction                                En     bit Mode     Feature
                                                   Support      Flag
 EVEX.DDS.128.66.0F38.W1 75 /r              FVM    V/V          AVX512VL   Permute word integers from two tables in
 VPERMI2W xmm1 {k1}{z}, xmm2,                                   AVX512BW   xmm3/m128 and xmm2 using indexes in xmm1 and
 xmm3/m128                                                                 store the result in xmm1 using writemask k1.
 EVEX.DDS.256.66.0F38.W1 75 /r              FVM    V/V          AVX512VL   Permute word integers from two tables in
 VPERMI2W ymm1 {k1}{z}, ymm2,                                   AVX512BW   ymm3/m256 and ymm2 using indexes in ymm1 and
 ymm3/m256                                                                 store the result in ymm1 using writemask k1.
 EVEX.DDS.512.66.0F38.W1 75 /r              FVM    V/V          AVX512BW   Permute word integers from two tables in
 VPERMI2W zmm1 {k1}{z}, zmm2,                                              zmm3/m512 and zmm2 using indexes in zmm1 and
 zmm3/m512                                                                 store the result in zmm1 using writemask k1.
 EVEX.DDS.128.66.0F38.W0 76 /r              FV     V/V          AVX512VL   Permute double-words from two tables in
 VPERMI2D xmm1 {k1}{z}, xmm2,                                   AVX512F    xmm3/m128/m32bcst and xmm2 using indexes in
 xmm3/m128/m32bcst                                                         xmm1 and store the result in xmm1 using writemask
                                                                           k1.
 EVEX.DDS.256.66.0F38.W0 76 /r              FV     V/V          AVX512VL   Permute double-words from two tables in
 VPERMI2D ymm1 {k1}{z}, ymm2,                                   AVX512F    ymm3/m256/m32bcst and ymm2 using indexes in
 ymm3/m256/m32bcst                                                         ymm1 and store the result in ymm1 using writemask
                                                                           k1.
 EVEX.DDS.512.66.0F38.W0 76 /r              FV     V/V          AVX512F    Permute double-words from two tables in
 VPERMI2D zmm1 {k1}{z}, zmm2,                                              zmm3/m512/m32bcst and zmm2 using indices in
 zmm3/m512/m32bcst                                                         zmm1 and store the result in zmm1 using writemask
                                                                           k1.
 EVEX.DDS.128.66.0F38.W1 76 /r              FV     V/V          AVX512VL   Permute quad-words from two tables in
 VPERMI2Q xmm1 {k1}{z}, xmm2,                                   AVX512F    xmm3/m128/m64bcst and xmm2 using indexes in
 xmm3/m128/m64bcst                                                         xmm1 and store the result in xmm1 using writemask
                                                                           k1.
 EVEX.DDS.256.66.0F38.W1 76 /r              FV     V/V          AVX512VL   Permute quad-words from two tables in
 VPERMI2Q ymm1 {k1}{z}, ymm2,                                   AVX512F    ymm3/m256/m64bcst and ymm2 using indexes in
 ymm3/m256/m64bcst                                                         ymm1 and store the result in ymm1 using writemask
                                                                           k1.
 EVEX.DDS.512.66.0F38.W1 76 /r              FV     V/V          AVX512F    Permute quad-words from two tables in
 VPERMI2Q zmm1 {k1}{z}, zmm2,                                              zmm3/m512/m64bcst and zmm2 using indices in
 zmm3/m512/m64bcst                                                         zmm1 and store the result in zmm1 using writemask
                                                                           k1.
 EVEX.DDS.128.66.0F38.W0 77 /r              FV     V/V          AVX512VL   Permute single-precision FP values from two tables in
 VPERMI2PS xmm1 {k1}{z}, xmm2,                                  AVX512F    xmm3/m128/m32bcst and xmm2 using indexes in
 xmm3/m128/m32bcst                                                         xmm1 and store the result in xmm1 using writemask
                                                                           k1.
 EVEX.DDS.256.66.0F38.W0 77 /r              FV     V/V          AVX512VL   Permute single-precision FP values from two tables in
 VPERMI2PS ymm1 {k1}{z}, ymm2,                                  AVX512F    ymm3/m256/m32bcst and ymm2 using indexes in
 ymm3/m256/m32bcst                                                         ymm1 and store the result in ymm1 using writemask
                                                                           k1.
 EVEX.DDS.512.66.0F38.W0 77 /r              FV     V/V          AVX512F    Permute single-precision FP values from two tables in
 VPERMI2PS zmm1 {k1}{z}, zmm2,                                             zmm3/m512/m32bcst and zmm2 using indices in
 zmm3/m512/m32bcst                                                         zmm1 and store the result in zmm1 using writemask
                                                                           k1.




 Opcode/                                 Op /    64/32       CPUID          Description
 Instruction                             En      bit Mode    Feature
                                                 Support     Flag
 EVEX.DDS.128.66.0F38.W1 77 /r           FV      V/V         AVX512VL       Permute double-precision FP values from two tables in
 VPERMI2PD xmm1 {k1}{z}, xmm2,                               AVX512F        xmm3/m128/m64bcst and xmm2 using indexes in
 xmm3/m128/m64bcst                                                          xmm1 and store the result in xmm1 using writemask
                                                                            k1.
 EVEX.DDS.256.66.0F38.W1 77 /r           FV      V/V         AVX512VL       Permute double-precision FP values from two tables in
 VPERMI2PD ymm1 {k1}{z}, ymm2,                               AVX512F        ymm3/m256/m64bcst and ymm2 using indexes in
 ymm3/m256/m64bcst                                                          ymm1 and store the result in ymm1 using writemask
                                                                            k1.
 EVEX.DDS.512.66.0F38.W1 77 /r           FV      V/V         AVX512F        Permute double-precision FP values from two tables in
 VPERMI2PD zmm1 {k1}{z}, zmm2,                                              zmm3/m512/m64bcst and zmm2 using indices in
 zmm3/m512/m64bcst                                                          zmm1 and store the result in zmm1 using writemask
                                                                            k1.


                                                Instruction Operand Encoding
      Op/En              Operand 1                     Operand 2                  Operand 3                    Operand 4
       FVM            ModRM:reg (r,w)              EVEX.vvvv (r)                ModRM:r/m (r)                      NA
        FV            ModRM:reg (r, w)             EVEX.vvvv (r)                ModRM:r/m (r)                      NA

Description
Permutes 16-bit/32-bit/64-bit values in the second operand (the first source operand) and the third operand (the
second source operand) using indices in the first operand to select elements from the second and third operands.
The selected elements are written to the destination operand (the first operand) according to the writemask k1.
The first and second operands are ZMM/YMM/XMM registers. The first operand contains input indices to select
elements from the two input tables in the 2nd and 3rd operands. The first operand is also the destination of the
result.
D/Q/PS/PD element versions: The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. Broadcast from the
low 32/64-bit memory location is performed if EVEX.b and the id bit for table selection are set (selecting table_2).
Dword/PS versions: The id bit for table selection is bit 4/3/2, depending on VL=512, 256, 128. Bits
[3:0]/[2:0]/[1:0] of each element in the input index vector select an element within the two source operands, If
the id bit is 0, table_1 (the first source) is selected; otherwise the second source operand is selected.
Qword/PD versions: The id bit for table selection is bit 3/2/1, and bits [2:0]/[1:0] /bit 0 selects element within each
input table.
Word element versions: The second source operand can be a ZMM/YMM/XMM register, or a 512/256/128-bit
memory location. The id bit for table selection is bit 5/4/3, and bits [4:0]/[3:0]/[2:0] selects element within each
input table.
Note that these instructions permit a 16-bit/32-bit/64-bit value in the source operands to be copied to more than
one location in the destination operand. Note also that in this case, the same table can be reused for example for a
second iteration, while the index elements are overwritten.
Bits (MAX_VL-1:256/128) of the destination are zeroed for VL=256,128.





Operation
VPERMI2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    id <- 2
FI;
IF VL = 256
    id <- 3
FI;
IF VL = 512
    id <- 4
FI;
TMP_DEST<- DEST
FOR j <- 0 TO KL-1
    i <- j * 16
    off <- 16*TMP_DEST[i+id:i]
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+15:i]=TMP_DEST[i+id+1] ? SRC2[off+15:off]
                       : SRC1[off+15:off]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMI2D/VPERMI2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
    id <- 1
FI;
IF VL = 256
    id <- 2
FI;
IF VL = 512
    id <- 3
FI;
TMP_DEST<- DEST
FOR j <- 0 TO KL-1
    i <- j * 32
    off <- 32*TMP_DEST[i+id:i]
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- TMP_DEST[i+id+1] ? SRC2[31:0]
                        : SRC1[off+31:off]
               ELSE
                    DEST[i+31:i] <- TMP_DEST[i+id+1] ? SRC2[off+31:off]
                        : SRC1[off+31:off]



            FI
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+31:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMI2Q/VPERMI2PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8 512)
IF VL = 128
    id <- 0
FI;
IF VL = 256
    id <- 1
FI;
IF VL = 512
    id <- 2
FI;
TMP_DEST<- DEST
FOR j <- 0 TO KL-1
    i <- j * 64
    off <- 64*TMP_DEST[i+id:i]
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- TMP_DEST[i+id+1] ? SRC2[63:0]
                        : SRC1[off+63:off]
               ELSE
                    DEST[i+63:i] <- TMP_DEST[i+id+1] ? SRC2[off+63:off]
                        : SRC1[off+63:off]
               FI
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent

VPERMI2D __m512i _mm512_permutex2var_epi32(__m512i a, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask_permutex2var_epi32(__m512i a, __mmask16 k, __m512i idx, __m512i b);
VPERMI2D __m512i _mm512_mask2_permutex2var_epi32(__m512i a, __m512i idx, __mmask16 k, __m512i b);
VPERMI2D __m512i _mm512_maskz_permutex2var_epi32(__mmask16 k, __m512i a, __m512i idx, __m512i b);
VPERMI __m256i _mm256_permutex2var_epi32(__m256i a, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask_permutex2var_epi32(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2D __m256i _mm256_mask2_permutex2var_epi32(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2D __m256i _mm256_maskz_permutex2var_epi32(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2D __m128i _mm_permutex2var_epi32(__m128i a, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask_permutex2var_epi32(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2D __m128i _mm_mask2_permutex2var_epi32(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2D __m128i _mm_maskz_permutex2var_epi32(__mmask8 k, __m128i a, __m128i idx, __m128i b);
VPERMI2PD __m512d _mm512_permutex2var_pd(__m512d a, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask_permutex2var_pd(__m512d a, __mmask8 k, __m512i idx, __m512d b);
VPERMI2PD __m512d _mm512_mask2_permutex2var_pd(__m512d a, __m512i idx, __mmask8 k, __m512d b);
VPERMI2PD __m512d _mm512_maskz_permutex2var_pd(__mmask8 k, __m512d a, __m512i idx, __m512d b);
VPERMI2PD __m256d _mm256_permutex2var_pd(__m256d a, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask_permutex2var_pd(__m256d a, __mmask8 k, __m256i idx, __m256d b);
VPERMI2PD __m256d _mm256_mask2_permutex2var_pd(__m256d a, __m256i idx, __mmask8 k, __m256d b);
VPERMI2PD __m256d _mm256_maskz_permutex2var_pd(__mmask8 k, __m256d a, __m256i idx, __m256d b);
VPERMI2PD __m128d _mm_permutex2var_pd(__m128d a, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask_permutex2var_pd(__m128d a, __mmask8 k, __m128i idx, __m128d b);
VPERMI2PD __m128d _mm_mask2_permutex2var_pd(__m128d a, __m128i idx, __mmask8 k, __m128d b);
VPERMI2PD __m128d _mm_maskz_permutex2var_pd(__mmask8 k, __m128d a, __m128i idx, __m128d b);
VPERMI2PS __m512 _mm512_permutex2var_ps(__m512 a, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask_permutex2var_ps(__m512 a, __mmask16 k, __m512i idx, __m512 b);
VPERMI2PS __m512 _mm512_mask2_permutex2var_ps(__m512 a, __m512i idx, __mmask16 k, __m512 b);
VPERMI2PS __m512 _mm512_maskz_permutex2var_ps(__mmask16 k, __m512 a, __m512i idx, __m512 b);
VPERMI2PS __m256 _mm256_permutex2var_ps(__m256 a, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask_permutex2var_ps(__m256 a, __mmask8 k, __m256i idx, __m256 b);
VPERMI2PS __m256 _mm256_mask2_permutex2var_ps(__m256 a, __m256i idx, __mmask8 k, __m256 b);
VPERMI2PS __m256 _mm256_maskz_permutex2var_ps(__mmask8 k, __m256 a, __m256i idx, __m256 b);
VPERMI2PS __m128 _mm_permutex2var_ps(__m128 a, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask_permutex2var_ps(__m128 a, __mmask8 k, __m128i idx, __m128 b);
VPERMI2PS __m128 _mm_mask2_permutex2var_ps(__m128 a, __m128i idx, __mmask8 k, __m128 b);
VPERMI2PS __m128 _mm_maskz_permutex2var_ps(__mmask8 k, __m128 a, __m128i idx, __m128 b);
VPERMI2Q __m512i _mm512_permutex2var_epi64(__m512i a, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask_permutex2var_epi64(__m512i a, __mmask8 k, __m512i idx, __m512i b);
VPERMI2Q __m512i _mm512_mask2_permutex2var_epi64(__m512i a, __m512i idx, __mmask8 k, __m512i b);
VPERMI2Q __m512i _mm512_maskz_permutex2var_epi64(__mmask8 k, __m512i a, __m512i idx, __m512i b);
VPERMI2Q __m256i _mm256_permutex2var_epi64(__m256i a, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask_permutex2var_epi64(__m256i a, __mmask8 k, __m256i idx, __m256i b);
VPERMI2Q __m256i _mm256_mask2_permutex2var_epi64(__m256i a, __m256i idx, __mmask8 k, __m256i b);
VPERMI2Q __m256i _mm256_maskz_permutex2var_epi64(__mmask8 k, __m256i a, __m256i idx, __m256i b);
VPERMI2Q __m128i _mm_permutex2var_epi64(__m128i a, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask_permutex2var_epi64(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2Q __m128i _mm_mask2_permutex2var_epi64(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2Q __m128i _mm_maskz_permutex2var_epi64(__mmask8 k, __m128i a, __m128i idx, __m128i b);


VPERMI2W __m512i _mm512_permutex2var_epi16(__m512i a, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask_permutex2var_epi16(__m512i a, __mmask32 k, __m512i idx, __m512i b);
VPERMI2W __m512i _mm512_mask2_permutex2var_epi16(__m512i a, __m512i idx, __mmask32 k, __m512i b);
VPERMI2W __m512i _mm512_maskz_permutex2var_epi16(__mmask32 k, __m512i a, __m512i idx, __m512i b);
VPERMI2W __m256i _mm256_permutex2var_epi16(__m256i a, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask_permutex2var_epi16(__m256i a, __mmask16 k, __m256i idx, __m256i b);
VPERMI2W __m256i _mm256_mask2_permutex2var_epi16(__m256i a, __m256i idx, __mmask16 k, __m256i b);
VPERMI2W __m256i _mm256_maskz_permutex2var_epi16(__mmask16 k, __m256i a, __m256i idx, __m256i b);
VPERMI2W __m128i _mm_permutex2var_epi16(__m128i a, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask_permutex2var_epi16(__m128i a, __mmask8 k, __m128i idx, __m128i b);
VPERMI2W __m128i _mm_mask2_permutex2var_epi16(__m128i a, __m128i idx, __mmask8 k, __m128i b);
VPERMI2W __m128i _mm_maskz_permutex2var_epi16(__mmask8 k, __m128i a, __m128i idx, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
VPERMI2D/Q/PS/PD: See Exceptions Type E4NF.
VPERMI2W: See Exceptions Type E4NF.nb.






platform: x86_64
mnem: VPERMILPD
description:
VPERMILPD-Permute In-Lane of Pairs of Double-Precision Floating-Point Values
 Opcode/                                        Op / En     64/32         CPUID      Description
 Instruction                                                bit Mode      Feature
                                                            Support       Flag
 VEX.NDS.128.66.0F38.W0 0D /r                   RVM         V/V           AVX        Permute double-precision floating-point values in
 VPERMILPD xmm1, xmm2, xmm3/m128                                                     xmm2 using controls from xmm3/m128 and store
                                                                                     result in xmm1.
 VEX.NDS.256.66.0F38.W0 0D /r                   RVM         V/V           AVX        Permute double-precision floating-point values in
 VPERMILPD ymm1, ymm2, ymm3/m256                                                     ymm2 using controls from ymm3/m256 and store
                                                                                     result in ymm1.
 EVEX.NDS.128.66.0F38.W1 0D /r                  FV-RVM      V/V           AVX512VL   Permute double-precision floating-point values in
 VPERMILPD xmm1 {k1}{z}, xmm2,                                            AVX512F    xmm2 using control from xmm3/m128/m64bcst
 xmm3/m128/m64bcst                                                                   and store the result in xmm1 using writemask k1.
 EVEX.NDS.256.66.0F38.W1 0D /r                  FV-RVM      V/V           AVX512VL   Permute double-precision floating-point values in
 VPERMILPD ymm1 {k1}{z}, ymm2,                                            AVX512F    ymm2 using control from ymm3/m256/m64bcst
 ymm3/m256/m64bcst                                                                   and store the result in ymm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W1 0D /r                  FV-RVM      V/V           AVX512F    Permute double-precision floating-point values in
 VPERMILPD zmm1 {k1}{z}, zmm2,                                                       zmm2 using control from zmm3/m512/m64bcst
 zmm3/m512/m64bcst                                                                   and store the result in zmm1 using writemask k1.
 VEX.128.66.0F3A.W0 05 /r ib                    RM          V/V           AVX        Permute double-precision floating-point values in
 VPERMILPD xmm1, xmm2/m128, imm8                                                     xmm2/m128 using controls from imm8.
 VEX.256.66.0F3A.W0 05 /r ib                    RM          V/V           AVX        Permute double-precision floating-point values in
 VPERMILPD ymm1, ymm2/m256, imm8                                                     ymm2/m256 using controls from imm8.
 EVEX.128.66.0F3A.W1 05 /r ib                   FV-RM       V/V           AVX512VL   Permute double-precision floating-point values in
 VPERMILPD xmm1 {k1}{z},                                                  AVX512F    xmm2/m128/m64bcst using controls from imm8
 xmm2/m128/m64bcst, imm8                                                             and store the result in xmm1 using writemask k1.
 EVEX.256.66.0F3A.W1 05 /r ib                   FV-RM       V/V           AVX512VL   Permute double-precision floating-point values in
 VPERMILPD ymm1 {k1}{z},                                                  AVX512F    ymm2/m256/m64bcst using controls from imm8
 ymm2/m256/m64bcst, imm8                                                             and store the result in ymm1 using writemask k1.
 EVEX.512.66.0F3A.W1 05 /r ib                   FV-RM       V/V           AVX512F    Permute double-precision floating-point values in
 VPERMILPD zmm1 {k1}{z},                                                             zmm2/m512/m64bcst using controls from imm8
 zmm2/m512/m64bcst, imm8                                                             and store the result in zmm1 using writemask k1.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                  Operand 3                    Operand 4
       RVM                ModRM:reg (w)                   VEX.vvvv (r)               ModRM:r/m (r)                    NA
        RM                ModRM:reg (w)                   ModRM:r/m (r)                   NA                          NA
     FV-RVM               ModRM:reg (w)                   EVEX.vvvv (r)              ModRM:r/m (r)                    NA
      FV-RM               ModRM:reg (w)                   ModRM:r/m (r)                   NA                          NA





Description
(variable control version)
Permute pairs of double-precision floating-point values in the first source operand (second operand), each using a
1-bit control field residing in the corresponding quadword element of the second source operand (third operand).
Permuted results are stored in the destination operand (first operand).
The control bits are located at bit 0 of each quadword element (see Figure 5-24). Each control determines which of
the source element in an input pair is selected for the destination element. Each pair of source elements must lie in
the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are
written to the destination under the writemask.




                      SRC1            X3                    X2                    X1                      X0




                      DEST            X2..X3                X2..X3                X0..X1                  X0..X1



                                                 Figure 5-23. VPERMILPD Operation


VEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.



                                                                                                                         Bit
                255            194 193                     127             66    65              63         2       1
                                           ignored




                                                                                       ignored




                                                                                                                         ignored
                       ignored      sel              ...           ignored      sel                   ignored      sel


                             Control Field 4                           Control Field 2                   Control Field1

                                           Figure 5-24. VPERMILPD Shuffle Control


(immediate control version)
Permute pairs of double-precision floating-point values in the first source operand (second operand), each pair
using a 1-bit control field in the imm8 byte. Each element in the destination operand (first operand) use a separate
control bit of the imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register. Imm8 byte provides the lower 4/2 bit as permute control fields.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. Permuted results are written to
the destination under the writemask. Imm8 byte provides the lower 8/4/2 bit as permute control fields.
Note: For the imm8 versions, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.





Operation
VPERMILPD (EVEX immediate versions)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
     i <- j * 64
     IF (EVEX.b = 1) AND (SRC1 *is memory*)
           THEN TMP_SRC1[i+63:i] <- SRC1[63:0];
           ELSE TMP_SRC1[i+63:i] <- SRC1[i+63:i];
     FI;
ENDFOR;
IF (imm8[0] = 0) THEN TMP_DEST[63:0] <- SRC1[63:0]; FI;
IF (imm8[0] = 1) THEN TMP_DEST[63:0] <- TMP_SRC1[127:64]; FI;
IF (imm8[1] = 0) THEN TMP_DEST[127:64] <- TMP_SRC1[63:0]; FI;
IF (imm8[1] = 1) THEN TMP_DEST[127:64] <- TMP_SRC1[127:64]; FI;
IF VL >= 256
     IF (imm8[2] = 0) THEN TMP_DEST[191:128] <- TMP_SRC1[191:128]; FI;
     IF (imm8[2] = 1) THEN TMP_DEST[191:128] <- TMP_SRC1[255:192]; FI;
     IF (imm8[3] = 0) THEN TMP_DEST[255:192] <- TMP_SRC1[191:128]; FI;
     IF (imm8[3] = 1) THEN TMP_DEST[255:192] <- TMP_SRC1[255:192]; FI;
FI;
IF VL >= 512
     IF (imm8[4] = 0) THEN TMP_DEST[319:256] <- TMP_SRC1[319:256]; FI;
     IF (imm8[4] = 1) THEN TMP_DEST[319:256] <- TMP_SRC1[383:320]; FI;
     IF (imm8[5] = 0) THEN TMP_DEST[383:320] <- TMP_SRC1[319:256]; FI;
     IF (imm8[5] = 1) THEN TMP_DEST[383:320] <- TMP_SRC1[383:320]; FI;
     IF (imm8[6] = 0) THEN TMP_DEST[447:384] <- TMP_SRC1[447:384]; FI;
     IF (imm8[6] = 1) THEN TMP_DEST[447:384] <- TMP_SRC1[511:448]; FI;
     IF (imm8[7] = 0) THEN TMP_DEST[511:448] <- TMP_SRC1[447:384]; FI;
     IF (imm8[7] = 1) THEN TMP_DEST[511:448] <- TMP_SRC1[511:448]; FI;
FI;
FOR j <- 0 TO KL-1
     i <- j * 64
     IF k1[j] OR *no writemask*
           THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
           ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
     FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMILPD (256-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]
IF (imm8[2] = 0) THEN DEST[191:128]<-SRC1[191:128]
IF (imm8[2] = 1) THEN DEST[191:128]<-SRC1[255:192]
IF (imm8[3] = 0) THEN DEST[255:192]<-SRC1[191:128]
IF (imm8[3] = 1) THEN DEST[255:192]<-SRC1[255:192]
DEST[MAX_VL-1:256]<-0



VPERMILPD (128-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]
DEST[MAX_VL-1:128]<-0

VPERMILPD (EVEX variable versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0];
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];
    FI;
ENDFOR;

IF (TMP_SRC2[1] = 0) THEN TMP_DEST[63:0] <- SRC1[63:0]; FI;
IF (TMP_SRC2[1] = 1) THEN TMP_DEST[63:0] <- SRC1[127:64]; FI;
IF (TMP_SRC2[65] = 0) THEN TMP_DEST[127:64] <- SRC1[63:0]; FI;
IF (TMP_SRC2[65] = 1) THEN TMP_DEST[127:64] <- SRC1[127:64]; FI;
IF VL >= 256
    IF (TMP_SRC2[129] = 0) THEN TMP_DEST[191:128] <- SRC1[191:128]; FI;
    IF (TMP_SRC2[129] = 1) THEN TMP_DEST[191:128] <- SRC1[255:192]; FI;
    IF (TMP_SRC2[193] = 0) THEN TMP_DEST[255:192] <- SRC1[191:128]; FI;
    IF (TMP_SRC2[193] = 1) THEN TMP_DEST[255:192] <- SRC1[255:192]; FI;
FI;
IF VL >= 512
    IF (TMP_SRC2[257] = 0) THEN TMP_DEST[319:256] <- SRC1[319:256]; FI;
    IF (TMP_SRC2[257] = 1) THEN TMP_DEST[319:256] <- SRC1[383:320]; FI;
    IF (TMP_SRC2[321] = 0) THEN TMP_DEST[383:320] <- SRC1[319:256]; FI;
    IF (TMP_SRC2[321] = 1) THEN TMP_DEST[383:320] <- SRC1[383:320]; FI;
    IF (TMP_SRC2[385] = 0) THEN TMP_DEST[447:384] <- SRC1[447:384]; FI;
    IF (TMP_SRC2[385] = 1) THEN TMP_DEST[447:384] <- SRC1[511:448]; FI;
    IF (TMP_SRC2[449] = 0) THEN TMP_DEST[511:448] <- SRC1[447:384]; FI;
    IF (TMP_SRC2[449] = 1) THEN TMP_DEST[511:448] <- SRC1[511:448]; FI;
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPERMILPD (256-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]
IF (SRC2[129] = 0) THEN DEST[191:128]<-SRC1[191:128]
IF (SRC2[129] = 1) THEN DEST[191:128]<-SRC1[255:192]
IF (SRC2[193] = 0) THEN DEST[255:192]<-SRC1[191:128]
IF (SRC2[193] = 1) THEN DEST[255:192]<-SRC1[255:192]
DEST[MAX_VL-1:256]<-0

VPERMILPD (128-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]
DEST[MAX_VL-1:128]<-0

Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPD __m512d _mm512_permute_pd( __m512d a, int imm);
VPERMILPD __m512d _mm512_mask_permute_pd(__m512d s, __mmask8 k, __m512d a, int imm);
VPERMILPD __m512d _mm512_maskz_permute_pd( __mmask8 k, __m512d a, int imm);
VPERMILPD __m256d _mm256_mask_permute_pd(__m256d s, __mmask8 k, __m256d a, int imm);
VPERMILPD __m256d _mm256_maskz_permute_pd( __mmask8 k, __m256d a, int imm);
VPERMILPD __m128d _mm_mask_permute_pd(__m128d s, __mmask8 k, __m128d a, int imm);
VPERMILPD __m128d _mm_maskz_permute_pd( __mmask8 k, __m128d a, int imm);
VPERMILPD __m512d _mm512_permutevar_pd( __m512i i, __m512d a);
VPERMILPD __m512d _mm512_mask_permutevar_pd(__m512d s, __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m512d _mm512_maskz_permutevar_pd( __mmask8 k, __m512i i, __m512d a);
VPERMILPD __m256d _mm256_mask_permutevar_pd(__m256d s, __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m256d _mm256_maskz_permutevar_pd( __mmask8 k, __m256d i, __m256d a);
VPERMILPD __m128d _mm_mask_permutevar_pd(__m128d s, __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_maskz_permutevar_pd( __mmask8 k, __m128d i, __m128d a);
VPERMILPD __m128d _mm_permute_pd (__m128d a, int control)
VPERMILPD __m256d _mm256_permute_pd (__m256d a, int control)
VPERMILPD __m128d _mm_permutevar_pd (__m128d a, __m128i control);
VPERMILPD __m256d _mm256_permutevar_pd (__m256d a, __m256i control);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD                      If VEX.W = 1.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD                      If either (E)VEX.vvvv != 1111B and with imm8.






platform: x86_64
mnem: VPERMILPS
description:
VPERMILPS-Permute In-Lane of Quadruples of Single-Precision Floating-Point Values
 Opcode/                              Op / En    64/32          CPUID        Description
 Instruction                                     bit Mode       Feature
                                                 Support        Flag
 VEX.NDS.128.66.0F38.W0 0C /r         RVM        V/V            AVX          Permute single-precision floating-point values in
 VPERMILPS xmm1, xmm2, xmm3/m128                                             xmm2 using controls from xmm3/m128 and
                                                                             store result in xmm1.
 VEX.128.66.0F3A.W0 04 /r ib          RM         V/V            AVX          Permute single-precision floating-point values in
 VPERMILPS xmm1, xmm2/m128, imm8                                             xmm2/m128 using controls from imm8 and store
                                                                             result in xmm1.
 VEX.NDS.256.66.0F38.W0 0C /r         RVM        V/V            AVX          Permute single-precision floating-point values in
 VPERMILPS ymm1, ymm2, ymm3/m256                                             ymm2 using controls from ymm3/m256 and
                                                                             store result in ymm1.
 VEX.256.66.0F3A.W0 04 /r ib          RM         V/V            AVX          Permute single-precision floating-point values in
 VPERMILPS ymm1, ymm2/m256, imm8                                             ymm2/m256 using controls from imm8 and store
                                                                             result in ymm1.
 EVEX.NDS.128.66.0F38.W0 0C /r        FV-RVM     V/V            AVX512VL     Permute single-precision floating-point values
 VPERMILPS xmm1 {k1}{z}, xmm2,                                  AVX512F      xmm2 using control from xmm3/m128/m32bcst
 xmm3/m128/m32bcst                                                           and store the result in xmm1 using writemask k1.
 EVEX.NDS.256.66.0F38.W0 0C /r        FV-RVM     V/V            AVX512VL     Permute single-precision floating-point values
 VPERMILPS ymm1 {k1}{z}, ymm2,                                  AVX512F      ymm2 using control from ymm3/m256/m32bcst
 ymm3/m256/m32bcst                                                           and store the result in ymm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W0 0C /r        FV-RVM     V/V            AVX512F      Permute single-precision floating-point values
 VPERMILPS zmm1 {k1}{z}, zmm2,                                               zmm2 using control from zmm3/m512/m32bcst
 zmm3/m512/m32bcst                                                           and store the result in zmm1 using writemask k1.
 EVEX.128.66.0F3A.W0 04 /r ib         FV-RM      V/V            AVX512VL     Permute single-precision floating-point values
 VPERMILPS xmm1 {k1}{z},                                        AVX512F      xmm2/m128/m32bcst using controls from imm8
 xmm2/m128/m32bcst, imm8                                                     and store the result in xmm1 using writemask k1.
 EVEX.256.66.0F3A.W0 04 /r ib         FV-RM      V/V            AVX512VL     Permute single-precision floating-point values
 VPERMILPS ymm1 {k1}{z},                                        AVX512F      ymm2/m256/m32bcst using controls from imm8
 ymm2/m256/m32bcst, imm8                                                     and store the result in ymm1 using writemask k1.
 EVEX.512.66.0F3A.W0 04 /r            FV-RM      V/V            AVX512F      Permute single-precision floating-point values
 ibVPERMILPS zmm1 {k1}{z},                                                   zmm2/m512/m32bcst using controls from imm8
 zmm2/m512/m32bcst, imm8                                                     and store the result in zmm1 using writemask k1.



                                            Instruction Operand Encoding
      Op/En            Operand 1                 Operand 2                     Operand 3                      Operand 4
       RVM            ModRM:reg (w)             VEX.vvvv (r)                 ModRM:r/m (r)                        NA
       RM             ModRM:reg (w)             ModRM:r/m (r)                      NA                             NA
     FV-RVM           ModRM:reg (w)             EVEX.vvvv (r)                ModRM:r/m (r)                        NA
     FV-RM           ModRM:reg (w)              ModRM:r/m (r)                      NA                             NA





Description
(variable control version)
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the corresponding dword element of the second source operand. Permuted
results are stored in the destination operand (first operand).
The 2-bit control fields are located at the low two bits of each dword element (see Figure 5-26). Each control deter-
mines which of the source element in an input quadruple is selected for the destination element. Each quadruple of
source elements must lie in the same 128-bit region as the destination.
EVEX version: The second source operand (third operand) is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are
written to the destination under the writemask.




                   SRC1      X7         X6          X5          X4        X3          X2          X1           X0




                   DEST X7 .. X4    X7 .. X4       X7 .. X4    X7 .. X4 X3 ..X0     X3 ..X0     X3 .. X0     X3 .. X0




                                                    Figure 5-25. VPERMILPS Operation




                                                                                                                                  Bit
                       255                   226 225 224             63                    34   33 32   31                    1     0


                              ignored              sel        ...           ignored              sel            ignored           sel


                                   Control Field 7                                Control Field 2                   Control Field 1

                                                 Figure 5-26. VPERMILPS Shuffle Control


(immediate control version)
Permute quadruples of single-precision floating-point values in the first source operand (second operand), each
quadruplet using a 2-bit control field in the imm8 byte. Each 128-bit lane in the destination operand (first operand)
use the four control fields of the same imm8 byte.
VEX version: The source operand is a YMM/XMM register or a 256/128-bit memory location and the destination
operand is a YMM/XMM register.
EVEX version: The source operand (second operand) is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location or a 512/256/128-bit vector broadcasted from a 32-bit memory location. Permuted results are written to
the destination under the writemask.
Note: For the imm8 version, VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will
#UD.




Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
   0: TMP <-SRC[31:0];
   1: TMP <-SRC[63:32];
   2: TMP <-SRC[95:64];
   3: TMP <-SRC[127:96];
ESAC;
RETURN TMP
}

VPERMILPS (EVEX immediate versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC1 *is memory*)
         THEN TMP_SRC1[i+31:i] <- SRC1[31:0];
         ELSE TMP_SRC1[i+31:i] <- SRC1[i+31:i];
    FI;
ENDFOR;

TMP_DEST[31:0] <- Select4(TMP_SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] <- Select4(TMP_SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] <- Select4(TMP_SRC1[127:0], imm8[5:4]);
TMP_DEST[127:96] <- Select4(TMP_SRC1[127:0], imm8[7:6]); FI;
IF VL >= 256
    TMP_DEST[159:128] <- Select4(TMP_SRC1[255:128], imm8[1:0]); FI;
    TMP_DEST[191:160] <- Select4(TMP_SRC1[255:128], imm8[3:2]); FI;
    TMP_DEST[223:192] <- Select4(TMP_SRC1[255:128], imm8[5:4]); FI;
    TMP_DEST[255:224] <- Select4(TMP_SRC1[255:128], imm8[7:6]); FI;
FI;
IF VL >= 512
    TMP_DEST[287:256] <- Select4(TMP_SRC1[383:256], imm8[1:0]); FI;
    TMP_DEST[319:288] <- Select4(TMP_SRC1[383:256], imm8[3:2]); FI;
    TMP_DEST[351:320] <- Select4(TMP_SRC1[383:256], imm8[5:4]); FI;
    TMP_DEST[383:352] <- Select4(TMP_SRC1[383:256], imm8[7:6]); FI;
    TMP_DEST[415:384] <- Select4(TMP_SRC1[511:384], imm8[1:0]); FI;
    TMP_DEST[447:416] <- Select4(TMP_SRC1[511:384], imm8[3:2]); FI;
    TMP_DEST[479:448] <- Select4(TMP_SRC1[511:384], imm8[5:4]); FI;
    TMP_DEST[511:480] <- Select4(TMP_SRC1[511:384], imm8[7:6]); FI;
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE DEST[i+31:i] <- 0              ;zeroing-masking
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VPERMILPS (256-bit immediate version)
DEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <-Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] <-Select4(SRC1[127:0], imm8[7:6]);
DEST[159:128] <-Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] <-Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] <-Select4(SRC1[255:128], imm8[5:4]);
DEST[255:224] <-Select4(SRC1[255:128], imm8[7:6]);

VPERMILPS (128-bit immediate version)
DEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <-Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] <-Select4(SRC1[127:0], imm8[7:6]);
DEST[MAX_VL-1:128]<-0

VPERMILPS (EVEX variable versions)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0];
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i];
    FI;
ENDFOR;
TMP_DEST[31:0] <- Select4(SRC1[127:0], TMP_SRC2[1:0]);
TMP_DEST[63:32] <- Select4(SRC1[127:0], TMP_SRC2[33:32]);
TMP_DEST[95:64] <- Select4(SRC1[127:0], TMP_SRC2[65:64]);
TMP_DEST[127:96] <- Select4(SRC1[127:0], TMP_SRC2[97:96]);
IF VL >= 256
    TMP_DEST[159:128] <- Select4(SRC1[255:128], TMP_SRC2[129:128]);
    TMP_DEST[191:160] <- Select4(SRC1[255:128], TMP_SRC2[161:160]);
    TMP_DEST[223:192] <- Select4(SRC1[255:128], TMP_SRC2[193:192]);
    TMP_DEST[255:224] <- Select4(SRC1[255:128], TMP_SRC2[225:224]);
FI;
IF VL >= 512
    TMP_DEST[287:256] <- Select4(SRC1[383:256], TMP_SRC2[257:256]);
    TMP_DEST[319:288] <- Select4(SRC1[383:256], TMP_SRC2[289:288]);
    TMP_DEST[351:320] <- Select4(SRC1[383:256], TMP_SRC2[321:320]);
    TMP_DEST[383:352] <- Select4(SRC1[383:256], TMP_SRC2[353:352]);
    TMP_DEST[415:384] <- Select4(SRC1[511:384], TMP_SRC2[385:384]);
    TMP_DEST[447:416] <- Select4(SRC1[511:384], TMP_SRC2[417:416]);
    TMP_DEST[479:448] <- Select4(SRC1[511:384], TMP_SRC2[449:448]);
    TMP_DEST[511:480] <- Select4(SRC1[511:384], TMP_SRC2[481:480]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE DEST[i+31:i] <- 0              ;zeroing-masking



          FI;
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMILPS (256-bit variable version)
DEST[31:0] <-Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] <-Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] <-Select4(SRC1[127:0], SRC2[97:96]);
DEST[159:128] <-Select4(SRC1[255:128], SRC2[129:128]);
DEST[191:160] <-Select4(SRC1[255:128], SRC2[161:160]);
DEST[223:192] <-Select4(SRC1[255:128], SRC2[193:192]);
DEST[255:224] <-Select4(SRC1[255:128], SRC2[225:224]);
DEST[MAX_VL-1:256]<-0

VPERMILPS (128-bit variable version)
DEST[31:0] <-Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] <-Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] <-Select4(SRC1[127:0], SRC2[97:96]);
DEST[MAX_VL-1:128]<-0

Intel C/C++ Compiler Intrinsic Equivalent
VPERMILPS __m512 _mm512_permute_ps( __m512 a, int imm);
VPERMILPS __m512 _mm512_mask_permute_ps(__m512 s, __mmask16 k, __m512 a, int imm);
VPERMILPS __m512 _mm512_maskz_permute_ps( __mmask16 k, __m512 a, int imm);
VPERMILPS __m256 _mm256_mask_permute_ps(__m256 s, __mmask8 k, __m256 a, int imm);
VPERMILPS __m256 _mm256_maskz_permute_ps( __mmask8 k, __m256 a, int imm);
VPERMILPS __m128 _mm_mask_permute_ps(__m128 s, __mmask8 k, __m128 a, int imm);
VPERMILPS __m128 _mm_maskz_permute_ps( __mmask8 k, __m128 a, int imm);
VPERMILPS __m512 _mm512_permutevar_ps( __m512i i, __m512 a);
VPERMILPS __m512 _mm512_mask_permutevar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m512 _mm512_maskz_permutevar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMILPS __m256 _mm256_mask_permutevar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m256 _mm256_maskz_permutevar_ps( __mmask8 k, __m256 i, __m256 a);
VPERMILPS __m128 _mm_mask_permutevar_ps(__m128 s, __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_maskz_permutevar_ps( __mmask8 k, __m128 i, __m128 a);
VPERMILPS __m128 _mm_permute_ps (__m128 a, int control);
VPERMILPS __m256 _mm256_permute_ps (__m256 a, int control);
VPERMILPS __m128 _mm_permutevar_ps (__m128 a, __m128i control);
VPERMILPS __m256 _mm256_permutevar_ps (__m256 a, __m256i control);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
#UD                    If VEX.W = 1.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD                    If either (E)VEX.vvvv != 1111B and with imm8.






platform: x86_64
mnem: VPERMPD
description:
VPERMPD-Permute Double-Precision Floating-Point Elements
 Opcode/                                   Op / En     64/32        CPUID      Description
 Instruction                                           bit Mode     Feature
                                                       Support      Flag
 VEX.256.66.0F3A.W1 01 /r ib               RMI         V/V          AVX2       Permute double-precision floating-point elements in
 VPERMPD ymm1, ymm2/m256, imm8                                                 ymm2/m256 using indices in imm8 and store the
                                                                               result in ymm1.
 EVEX.256.66.0F3A.W1 01 /r ib              FV-RM       V/V          AVX512VL   Permute double-precision floating-point elements in
 VPERMPD ymm1 {k1}{z},                                              AVX512F    ymm2/m256/m64bcst using indexes in imm8 and
 ymm2/m256/m64bcst, imm8                                                       store the result in ymm1 subject to writemask k1.
 EVEX.512.66.0F3A.W1 01 /r ib              FV-RMI      V/V          AVX512F    Permute double-precision floating-point elements in
 VPERMPD zmm1 {k1}{z},                                                         zmm2/m512/m64bcst using indices in imm8 and
 zmm2/m512/m64bcst, imm8                                                       store the result in zmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F38.W1 16 /r             FV-RVM      V/V          AVX512VL   Permute double-precision floating-point elements in
 VPERMPD ymm1 {k1}{z}, ymm2,                                        AVX512F    ymm3/m256/m64bcst using indexes in ymm2 and
 ymm3/m256/m64bcst                                                             store the result in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F38.W1 16 /r             FV-RVM      V/V          AVX512F    Permute double-precision floating-point elements in
 VPERMPD zmm1 {k1}{z}, zmm2,                                                   zmm3/m512/m64bcst using indices in zmm2 and
 zmm3/m512/m64bcst                                                             store the result in zmm1 subject to writemask k1.



                                                   Instruction Operand Encoding
        Op/En                  Operand 1                     Operand 2              Operand 3                   Operand 4
         RMI                 ModRM:reg (w)                 ModRM:r/m (r)              Imm8                         NA
       FV-RMI                ModRM:reg (w)                 ModRM:r/m (r)              Imm8                         NA
       FV-RVM                ModRM:reg (w)                 EVEX.vvvv (r)          ModRM:r/m (r)                    NA

Description
The imm8 version: Copies quadword elements of double-precision floating-point values from the source operand
(the second operand) to the destination operand (the first operand) according to the indices specified by the imme-
diate operand (the third operand). Each two-bit value in the immediate byte selects a qword element in the source
operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corre-
sponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
The imm8 versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The vector control version: Copies quadword elements of double-precision floating-point values from the second
source operand (the third operand) to the destination operand (the first operand) according to the indices in the
first source operand (the second operand). The first 3 bits of each 64 bit element in the index operand selects
which quadword in the second source operand to copy. The first and second operands are ZMM registers, the third
operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit memory
location. The elements in the destination are updated using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destina-
tion operand.
If VPERMPD is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.





Operation
VPERMPD (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC *is memory*)
         THEN TMP_SRC[i+63:i] <- SRC[63:0];
         ELSE TMP_SRC[i+63:i] <- SRC[i+63:i];
    FI;
ENDFOR;

TMP_DEST[63:0] <- (TMP_SRC[256:0] >> (IMM8[1:0] * 64))[63:0];
TMP_DEST[127:64] <- (TMP_SRC[256:0] >> (IMM8[3:2] * 64))[63:0];
TMP_DEST[191:128] <- (TMP_SRC[256:0] >> (IMM8[5:4] * 64))[63:0];
TMP_DEST[255:192] <- (TMP_SRC[256:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
    TMP_DEST[319:256] <- (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
    TMP_DEST[383:320] <- (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
    TMP_DEST[447:384] <- (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
    TMP_DEST[511:448] <- (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0                    ;zeroing-masking
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0


VPERMPD (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0];
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];
    FI;
ENDFOR;

IF VL = 256
    TMP_DEST[63:0] <- (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
    TMP_DEST[127:64] <- (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
    TMP_DEST[191:128] <- (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
    TMP_DEST[255:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
    TMP_DEST[63:0] <- (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];




   TMP_DEST[127:64] <- (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
   TMP_DEST[191:128] <- (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
   TMP_DEST[255:192] <- (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];
   TMP_DEST[319:256] <- (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
   TMP_DEST[383:320] <- (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
   TMP_DEST[447:384] <- (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
   TMP_DEST[511:448] <- (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0                    ;zeroing-masking
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMPD (VEX.256 encoded version)
DEST[63:0] <-(SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] <-(SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] <-(SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] <-(SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAX_VL-1:256] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPERMPD __m512d _mm512_permutex_pd( __m512d a, int imm);
VPERMPD __m512d _mm512_mask_permutex_pd(__m512d s, __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_maskz_permutex_pd( __mmask16 k, __m512d a, int imm);
VPERMPD __m512d _mm512_permutexvar_pd( __m512i i, __m512d a);
VPERMPD __m512d _mm512_mask_permutexvar_pd(__m512d s, __mmask16 k, __m512i i, __m512d a);
VPERMPD __m512d _mm512_maskz_permutexvar_pd( __mmask16 k, __m512i i, __m512d a);
VPERMPD __m256d _mm256_permutex_epi64( __m256d a, int imm);
VPERMPD __m256d _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_maskz_permutex_epi64( __mmask8 k, __m256d a, int imm);
VPERMPD __m256d _mm256_permutexvar_epi64( __m256i i, __m256d a);
VPERMPD __m256d _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i i, __m256d a);
VPERMPD __m256d _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i i, __m256d a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD                     If VEX.L = 0.
                        If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD                     If encoded with EVEX.128.
                        If EVEX.vvvv != 1111B and with imm8.




platform: x86_64
mnem: VPERMPS
description:
VPERMPS-Permute Single-Precision Floating-Point Elements
 Opcode/                              Op /   64/32         CPUID       Description
 Instruction                          En     bit Mode      Feature
                                             Support       Flag
 VEX.256.66.0F38.W0 16 /r             RVM    V/V           AVX2        Permute single-precision floating-point elements in
 VPERMPS ymm1, ymm2,                                                   ymm3/m256 using indices in ymm2 and store the result in
 ymm3/m256                                                             ymm1.
 EVEX.NDS.256.66.0F38.W0 16 /r        FV     V/V           AVX512VL    Permute single-precision floating-point elements in
 VPERMPS ymm1 {k1}{z}, ymm2,                               AVX512F     ymm3/m256/m32bcst using indexes in ymm2 and store
 ymm3/m256/m32bcst                                                     the result in ymm1 subject to write mask k1.
 EVEX.NDS.512.66.0F38.W0 16 /r        FV     V/V           AVX512F     Permute single-precision floating-point values in
 VPERMPS zmm1 {k1}{z}, zmm2,                                           zmm3/m512/m32bcst using indices in zmm2 and store the
 zmm3/m512/m32bcst                                                     result in zmm1 subject to write mask k1.



                                                 Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                    Operand 3                  Operand 4
       RVM              ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                       NA
       FV               ModRM:reg (w)                EVEX.vvvv (r)              ModRM:r/m (r)                       NA

Description
Copies doubleword elements of single-precision floating-point values from the second source operand (the third
operand) to the destination operand (the first operand) according to the indices in the first source operand (the
second operand). Note that this instruction permits a doubleword in the source operand to be copied to more than
one location in the destination operand.
VEX.256 versions: The first and second operands are YMM registers, the third operand can be a YMM register or
memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded version: The first and second operands are ZMM registers, the third operand can be a ZMM register,
a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The elements in the
destination are updated using the writemask k1.
If VPERMPS is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will cause an
#UD exception.

Operation
VPERMPS (EVEX forms)
(KL, VL) (8, 256),= (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0];
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i];
    FI;
ENDFOR;

IF VL = 256
    TMP_DEST[31:0] <- (TMP_SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
    TMP_DEST[63:32] <- (TMP_SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
    TMP_DEST[95:64] <- (TMP_SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
    TMP_DEST[127:96] <- (TMP_SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
    TMP_DEST[159:128] <- (TMP_SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
    TMP_DEST[191:160] <- (TMP_SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
    TMP_DEST[223:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 32))[31:0];
    TMP_DEST[255:224] <- (TMP_SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];



FI;
IF VL = 512
    TMP_DEST[31:0] <- (TMP_SRC2[511:0] >> (SRC1[3:0] * 32))[31:0];
    TMP_DEST[63:32] <- (TMP_SRC2[511:0] >> (SRC1[35:32] * 32))[31:0];
    TMP_DEST[95:64] <- (TMP_SRC2[511:0] >> (SRC1[67:64] * 32))[31:0];
    TMP_DEST[127:96] <- (TMP_SRC2[511:0] >> (SRC1[99:96] * 32))[31:0];
    TMP_DEST[159:128] <- (TMP_SRC2[511:0] >> (SRC1[131:128] * 32))[31:0];
    TMP_DEST[191:160] <- (TMP_SRC2[511:0] >> (SRC1[163:160] * 32))[31:0];
    TMP_DEST[223:192] <- (TMP_SRC2[511:0] >> (SRC1[195:192] * 32))[31:0];
    TMP_DEST[255:224] <- (TMP_SRC2[511:0] >> (SRC1[227:224] * 32))[31:0];
    TMP_DEST[287:256] <- (TMP_SRC2[511:0] >> (SRC1[259:256] * 32))[31:0];
    TMP_DEST[319:288] <- (TMP_SRC2[511:0] >> (SRC1[291:288] * 32))[31:0];
    TMP_DEST[351:320] <- (TMP_SRC2[511:0] >> (SRC1[323:320] * 32))[31:0];
    TMP_DEST[383:352] <- (TMP_SRC2[511:0] >> (SRC1[355:352] * 32))[31:0];
    TMP_DEST[415:384] <- (TMP_SRC2[511:0] >> (SRC1[387:384] * 32))[31:0];
    TMP_DEST[447:416] <- (TMP_SRC2[511:0] >> (SRC1[419:416] * 32))[31:0];
    TMP_DEST[479:448] <-(TMP_SRC2[511:0] >> (SRC1[451:448] * 32))[31:0];
    TMP_DEST[511:480] <- (TMP_SRC2[511:0] >> (SRC1[483:480] * 32))[31:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0                    ;zeroing-masking
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMPS (VEX.256 encoded version)
DEST[31:0] <-(SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] <-(SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] <-(SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] <-(SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] <-(SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] <-(SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] <-(SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] <-(SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];
DEST[MAX_VL-1:256] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPERMPS __m512 _mm512_permutexvar_ps(__m512i i, __m512 a);
VPERMPS __m512 _mm512_mask_permutexvar_ps(__m512 s, __mmask16 k, __m512i i, __m512 a);
VPERMPS __m512 _mm512_maskz_permutexvar_ps( __mmask16 k, __m512i i, __m512 a);
VPERMPS __m256 _mm256_permutexvar_ps(__m256 i, __m256 a);
VPERMPS __m256 _mm256_mask_permutexvar_ps(__m256 s, __mmask8 k, __m256 i, __m256 a);
VPERMPS __m256 _mm256_maskz_permutexvar_ps( __mmask8 k, __m256 i, __m256 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD                    If VEX.L = 0.
EVEX-encoded instruction, see Exceptions Type E4NF.






platform: x86_64
mnem: VPERMQ
description:
VPERMQ-Qwords Element Permutation
 Opcode/                                Op / En   64/32         CPUID      Description
 Instruction                                      bit Mode      Feature
                                                  Support       Flag
 VEX.256.66.0F3A.W1 00 /r ib            RMI       V/V           AVX2       Permute qwords in ymm2/m256 using indices in
 VPERMQ ymm1, ymm2/m256, imm8                                              imm8 and store the result in ymm1.
 EVEX.256.66.0F3A.W1 00 /r ib           FV-RM     V/V           AVX512VL   Permute qwords in ymm2/m256/m64bcst using
 VPERMQ ymm1 {k1}{z},                                           AVX512F    indexes in imm8 and store the result in ymm1.
 ymm2/m256/m64bcst, imm8
 EVEX.512.66.0F3A.W1 00 /r ib           FV-RMI    V/V           AVX512F    Permute qwords in zmm2/m512/m64bcst using
 VPERMQ zmm1 {k1}{z},                                                      indices in imm8 and store the result in zmm1.
 zmm2/m512/m64bcst, imm8
 EVEX.NDS.256.66.0F38.W1 36 /r          FV-RVM    V/V           AVX512VL   Permute qwords in ymm3/m256/m64bcst using
 VPERMQ ymm1 {k1}{z}, ymm2,                                     AVX512F    indexes in ymm2 and store the result in ymm1.
 ymm3/m256/m64bcst
 EVEX.NDS.512.66.0F38.W1 36 /r          FV-RVM    V/V           AVX512F    Permute qwords in zmm3/m512/m64bcst using
 VPERMQ zmm1 {k1}{z}, zmm2,                                                indices in zmm2 and store the result in zmm1.
 zmm3/m512/m64bcst



                                              Instruction Operand Encoding
     Op/En                Operand 1                 Operand 2                Operand 3                   Operand 4
       RMI              ModRM:reg (w)             ModRM:r/m (r)                 Imm8                        NA
     FV-RMI             ModRM:reg (w)             ModRM:r/m (r)                 Imm8                        NA
     FV-RVM             ModRM:reg (w)             EVEX.vvvv (r)             ModRM:r/m (r)                   NA

Description
The imm8 version: Copies quadwords from the source operand (the second operand) to the destination operand
(the first operand) according to the indices specified by the immediate operand (the third operand). Each two-bit
value in the immediate byte selects a qword element in the source operand.
VEX version: The source operand can be a YMM register or a memory location. Bits (MAX_VL-1:256) of the corre-
sponding destination register are zeroed.
In EVEX.512 encoded version, The elements in the destination are updated using the writemask k1 and the imm8
bits are reused as control bits for the upper 256-bit half when the control bits are coming from immediate. The
source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location.
Immediate control versions: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will
#UD.
The vector control version: Copies quadwords from the second source operand (the third operand) to the destina-
tion operand (the first operand) according to the indices in the first source operand (the second operand). The first
3 bits of each 64 bit element in the index operand selects which quadword in the second source operand to copy.
The first and second operands are ZMM registers, the third operand can be a ZMM register, a 512-bit memory loca-
tion or a 512-bit vector broadcasted from a 64-bit memory location. The elements in the destination are updated
using the writemask k1.
Note that this instruction permits a qword in the source operand to be copied to multiple locations in the destina-
tion operand.
If VPERMPQ is encoded with VEX.L= 0 or EVEX.128, an attempt to execute the instruction will cause an #UD excep-
tion.





Operation
VPERMQ (EVEX - imm8 control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC *is memory*)
         THEN TMP_SRC[i+63:i] <- SRC[63:0];
         ELSE TMP_SRC[i+63:i] <- SRC[i+63:i];
    FI;
ENDFOR;
    TMP_DEST[63:0] <- (TMP_SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
    TMP_DEST[127:64] <- (TMP_SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
    TMP_DEST[191:128] <- (TMP_SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
    TMP_DEST[255:192] <- (TMP_SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
IF VL >= 512
    TMP_DEST[319:256] <- (TMP_SRC[511:256] >> (IMM8[1:0] * 64))[63:0];
    TMP_DEST[383:320] <- (TMP_SRC[511:256] >> (IMM8[3:2] * 64))[63:0];
    TMP_DEST[447:384] <- (TMP_SRC[511:256] >> (IMM8[5:4] * 64))[63:0];
    TMP_DEST[511:448] <- (TMP_SRC[511:256] >> (IMM8[7:6] * 64))[63:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0                    ;zeroing-masking
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMQ (EVEX - vector control forms)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0];
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i];
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[63:0] <- (TMP_SRC2[255:0] >> (SRC1[1:0] * 64))[63:0];
    TMP_DEST[127:64] <- (TMP_SRC2[255:0] >> (SRC1[65:64] * 64))[63:0];
    TMP_DEST[191:128] <- (TMP_SRC2[255:0] >> (SRC1[129:128] * 64))[63:0];
    TMP_DEST[255:192] <- (TMP_SRC2[255:0] >> (SRC1[193:192] * 64))[63:0];
FI;
IF VL = 512
    TMP_DEST[63:0] <- (TMP_SRC2[511:0] >> (SRC1[2:0] * 64))[63:0];
    TMP_DEST[127:64] <- (TMP_SRC2[511:0] >> (SRC1[66:64] * 64))[63:0];
    TMP_DEST[191:128] <- (TMP_SRC2[511:0] >> (SRC1[130:128] * 64))[63:0];
    TMP_DEST[255:192] <- (TMP_SRC2[511:0] >> (SRC1[194:192] * 64))[63:0];



   TMP_DEST[319:256] <- (TMP_SRC2[511:0] >> (SRC1[258:256] * 64))[63:0];
   TMP_DEST[383:320] <- (TMP_SRC2[511:0] >> (SRC1[322:320] * 64))[63:0];
   TMP_DEST[447:384] <- (TMP_SRC2[511:0] >> (SRC1[386:384] * 64))[63:0];
   TMP_DEST[511:448] <- (TMP_SRC2[511:0] >> (SRC1[450:448] * 64))[63:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+63:i] <- 0                    ;zeroing-masking
              FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPERMQ (VEX.256 encoded version)
DEST[63:0] <-(SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] <-(SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] <-(SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] <-(SRC[255:0] >> (IMM8[7:6] * 64))[63:0];
DEST[MAX_VL-1:256] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPERMQ __m512i _mm512_permutex_epi64( __m512i a, int imm);
VPERMQ __m512i _mm512_mask_permutex_epi64(__m512i s, __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_maskz_permutex_epi64( __mmask8 k, __m512i a, int imm);
VPERMQ __m512i _mm512_permutexvar_epi64( __m512i a, __m512i b);
VPERMQ __m512i _mm512_mask_permutexvar_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPERMQ __m512i _mm512_maskz_permutexvar_epi64( __mmask8 k, __m512i a, __m512i b);
VPERMQ __m256i _mm256_permutex_epi64( __m256i a, int imm);
VPERMQ __m256i _mm256_mask_permutex_epi64(__m256i s, __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_maskz_permutex_epi64( __mmask8 k, __m256i a, int imm);
VPERMQ __m256i _mm256_permutexvar_epi64( __m256i a, __m256i b);
VPERMQ __m256i _mm256_mask_permutexvar_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPERMQ __m256i _mm256_maskz_permutexvar_epi64( __mmask8 k, __m256i a, __m256i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4; additionally
#UD                    If VEX.L = 0.
                       If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD                    If encoded with EVEX.128.
                       If EVEX.vvvv != 1111B and with imm8.






platform: x86_64
mnem: VPEXPANDD
description:
VPEXPANDD-Load Sparse Packed Doubleword Integer Values from Dense Memory / Register
 Opcode/                                Op/     64/32       CPUID         Description
 Instruction                            En      bit Mode    Feature
                                                Support     Flag
 EVEX.128.66.0F38.W0 89 /r              T1S     V/V         AVX512VL      Expand packed double-word integer values from
 VPEXPANDD xmm1 {k1}{z},                                    AVX512F       xmm2/m128 to xmm1 using writemask k1.
 xmm2/m128
 EVEX.256.66.0F38.W0 89 /r              T1S     V/V         AVX512VL      Expand packed double-word integer values from
 VPEXPANDD ymm1 {k1}{z},                                    AVX512F       ymm2/m256 to ymm1 using writemask k1.
 ymm2/m256
 EVEX.512.66.0F38.W0 89 /r              T1S     V/V         AVX512F       Expand packed double-word integer values from
 VPEXPANDD zmm1 {k1}{z},                                                  zmm2/m512 to zmm1 using writemask k1.
 zmm2/m512



                                                 Instruction Operand Encoding
      Op/En                Operand 1                   Operand 2                    Operand 3                    Operand 4
       T1S              ModRM:reg (w)                 ModRM:r/m (r)                     NA                          NA

Description
Expand (load) up to 16 contiguous doubleword integer values of the input vector in the source operand (the second
operand) to sparse elements in the destination operand (the first operand), selected by the writemask k1. The
destination operand is a ZMM register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-
tion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VPEXPANDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+31:i] <- SRC[k+31:k];
               k <- k + 32
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDD __m512i _mm512_mask_expandloadu_epi32(__m512i s, __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_maskz_expandloadu_epi32( __mmask16 k, void * a);
VPEXPANDD __m512i _mm512_mask_expand_epi32(__m512i s, __mmask16 k, __m512i a);
VPEXPANDD __m512i _mm512_maskz_expand_epi32( __mmask16 k, __m512i a);
VPEXPANDD __m256i _mm256_mask_expandloadu_epi32(__m256i s, __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m256i _mm256_mask_expand_epi32(__m256i s, __mmask8 k, __m256i a);
VPEXPANDD __m256i _mm256_maskz_expand_epi32( __mmask8 k, __m256i a);
VPEXPANDD __m128i _mm_mask_expandloadu_epi32(__m128i s, __mmask8 k, void * a);
VPEXPANDD __m128i _mm_maskz_expandloadu_epi32( __mmask8 k, void * a);
VPEXPANDD __m128i _mm_mask_expand_epi32(__m128i s, __mmask8 k, __m128i a);
VPEXPANDD __m128i _mm_maskz_expand_epi32( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPEXPANDQ
description:
VPEXPANDQ-Load Sparse Packed Quadword Integer Values from Dense Memory / Register
 Opcode/                                      Op/     64/32         CPUID        Description
 Instruction                                  En      bit Mode      Feature
                                                      Support       Flag
 EVEX.128.66.0F38.W1 89 /r                    T1S     V/V           AVX512VL     Expand packed quad-word integer values from
 VPEXPANDQ xmm1 {k1}{z}, xmm2/m128                                  AVX512F      xmm2/m128 to xmm1 using writemask k1.
 EVEX.256.66.0F38.W1 89 /r                    T1S     V/V           AVX512VL     Expand packed quad-word integer values from
 VPEXPANDQ ymm1 {k1}{z}, ymm2/m256                                  AVX512F      ymm2/m256 to ymm1 using writemask k1.
 EVEX.512.66.0F38.W1 89 /r                    T1S     V/V           AVX512F      Expand packed quad-word integer values from
 VPEXPANDQ zmm1 {k1}{z}, zmm2/m512                                               zmm2/m512 to zmm1 using writemask k1.



                                                 Instruction Operand Encoding
      Op/En               Operand 1                   Operand 2                   Operand 3                     Operand 4
       T1S              ModRM:reg (w)               ModRM:r/m (r)                     NA                           NA

Description
Expand (load) up to 8 quadword integer values from the source operand (the second operand) to sparse elements
in the destination operand (the first operand), selected by the writemask k1. The destination operand is a ZMM
register, the source operand can be a ZMM register or memory location.
The input vector starts from the lowest element in the source operand. The opmask register k1 selects the destina-
tion elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VPEXPANDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+63:i] <- SRC[k+63:k];
               k <- k + 64
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPEXPANDQ __m512i _mm512_mask_expandloadu_epi64(__m512i s, __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m512i _mm512_mask_expand_epi64(__m512i s, __mmask8 k, __m512i a);
VPEXPANDQ __m512i _mm512_maskz_expand_epi64( __mmask8 k, __m512i a);
VPEXPANDQ __m256i _mm256_mask_expandloadu_epi64(__m256i s, __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m256i _mm256_mask_expand_epi64(__m256i s, __mmask8 k, __m256i a);
VPEXPANDQ __m256i _mm256_maskz_expand_epi64( __mmask8 k, __m256i a);
VPEXPANDQ __m128i _mm_mask_expandloadu_epi64(__m128i s, __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_maskz_expandloadu_epi64( __mmask8 k, void * a);
VPEXPANDQ __m128i _mm_mask_expand_epi64(__m128i s, __mmask8 k, __m128i a);
VPEXPANDQ __m128i _mm_maskz_expand_epi64( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPLZCNTD
description:
VPLZCNTD/VPLZCNTQ-Count the Number of Leading Zero Bits for Packed Dword, Packed Qword Values
 Opcode/                          Op/   64/32         CPUID           Description
 Instruction                      En    bit Mode      Feature
                                        Support       Flag
 EVEX.128.66.0F38.W0 44 /r        FV    V/V           AVX512VL        Count the number of leading zero bits in each dword
 VPLZCNTD xmm1 {k1}{z},                               AVX512CD        element of xmm2/m128/m32bcst using writemask k1.
 xmm2/m128/m32bcst

 EVEX.256.66.0F38.W0 44 /r        FV    V/V           AVX512VL        Count the number of leading zero bits in each dword
 VPLZCNTD ymm1 {k1}{z},                               AVX512CD        element of ymm2/m256/m32bcst using writemask k1.
 ymm2/m256/m32bcst

 EVEX.512.66.0F38.W0 44 /r        FV    V/V           AVX512CD        Count the number of leading zero bits in each dword
 VPLZCNTD zmm1 {k1}{z},                                               element of zmm2/m512/m32bcst using writemask k1.
 zmm2/m512/m32bcst

 EVEX.128.66.0F38.W1 44 /r        FV    V/V           AVX512VL        Count the number of leading zero bits in each qword
 VPLZCNTQ xmm1 {k1}{z},                               AVX512CD        element of xmm2/m128/m64bcst using writemask k1.
 xmm2/m128/m64bcst

 EVEX.256.66.0F38.W1 44 /r        FV    V/V           AVX512VL        Count the number of leading zero bits in each qword
 VPLZCNTQ ymm1 {k1}{z},                               AVX512CD        element of ymm2/m256/m64bcst using writemask k1.
 ymm2/m256/m64bcst

 EVEX.512.66.0F38.W1 44 /r        FV    V/V           AVX512CD        Count the number of leading zero bits in each qword
 VPLZCNTQ zmm1 {k1}{z},                                               element of zmm2/m512/m64bcst using writemask k1.
 zmm2/m512/m64bcst



                                              Instruction Operand Encoding
     Op/En            Operand 1                    Operand 2                     Operand 3                     Operand 4
      FV            ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA

Description
Counts the number of leading most significant zero bits in each dword or qword element of the source operand (the
second operand) and stores the results in the destination register (the first operand) according to the writemask.
If an element is zero, the result for that element is the operand size of the element.
EVEX.512 encoded version: The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a ZMM register, conditionally updated
using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a YMM register, conditionally updated
using writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32/64-bit memory location. The destination operand is a XMM register, conditionally updated
using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPLZCNTD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j*32
    IF MaskBit(j) OR *no writemask*
         THEN
               temp <- 32
               DEST[i+31:i] <- 0
               WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
               DO
                   temp <- temp - 1
                   DEST[i+31:i] <- DEST[i+31:i] + 1
               OD
         ELSE
           IF *merging-masking*
               THEN *DEST[i+31:i] remains unchanged*
               ELSE DEST[i+31:i] <- 0
           FI
    FI
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPLZCNTQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j*64
    IF MaskBit(j) OR *no writemask*
         THEN
               temp <- 64
               DEST[i+63:i] <- 0
               WHILE (temp > 0) AND (SRC[i+temp-1] = 0)
               DO
                   temp <- temp - 1
                   DEST[i+63:i] <- DEST[i+63:i] + 1
               OD
         ELSE
           IF *merging-masking*
               THEN *DEST[i+63:i] remains unchanged*
               ELSE DEST[i+63:i] <- 0
           FI
    FI
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent

VPLZCNTD __m512i _mm512_lzcnt_epi32(__m512i a);
VPLZCNTD __m512i _mm512_mask_lzcnt_epi32(__m512i s, __mmask16 m, __m512i a);
VPLZCNTD __m512i _mm512_maskz_lzcnt_epi32( __mmask16 m, __m512i a);
VPLZCNTQ __m512i _mm512_lzcnt_epi64(__m512i a);
VPLZCNTQ __m512i _mm512_mask_lzcnt_epi64(__m512i s, __mmask8 m, __m512i a);
VPLZCNTQ __m512i _mm512_maskz_lzcnt_epi64(__mmask8 m, __m512i a);
VPLZCNTD __m256i _mm256_lzcnt_epi32(__m256i a);
VPLZCNTD __m256i _mm256_mask_lzcnt_epi32(__m256i s, __mmask8 m, __m256i a);
VPLZCNTD __m256i _mm256_maskz_lzcnt_epi32( __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_lzcnt_epi64(__m256i a);
VPLZCNTQ __m256i _mm256_mask_lzcnt_epi64(__m256i s, __mmask8 m, __m256i a);
VPLZCNTQ __m256i _mm256_maskz_lzcnt_epi64(__mmask8 m, __m256i a);
VPLZCNTD __m128i _mm_lzcnt_epi32(__m128i a);
VPLZCNTD __m128i _mm_mask_lzcnt_epi32(__m128i s, __mmask8 m, __m128i a);
VPLZCNTD __m128i _mm_maskz_lzcnt_epi32( __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_lzcnt_epi64(__m128i a);
VPLZCNTQ __m128i _mm_mask_lzcnt_epi64(__m128i s, __mmask8 m, __m128i a);
VPLZCNTQ __m128i _mm_maskz_lzcnt_epi64(__mmask8 m, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPMASKMOV
description:
VPMASKMOV - Conditional SIMD Integer Packed Loads and Stores
 Opcode/                                         Op/     64/32     CPUID     Description
 Instruction                                     En      -bit      Feature
                                                         Mode      Flag
 VEX.NDS.128.66.0F38.W0 8C /rVPMASK-             RVM     V/V       AVX2      Conditionally load dword values from m128 using mask
 MOVD xmm1, xmm2, m128                                                       in xmm2 and store in xmm1.
 VEX.NDS.256.66.0F38.W0 8C /r                    RVM     V/V       AVX2      Conditionally load dword values from m256 using mask
 VPMASKMOVD ymm1, ymm2, m256                                                 in ymm2 and store in ymm1.
 VEX.NDS.128.66.0F38.W1 8C /r                    RVM     V/V       AVX2      Conditionally load qword values from m128 using mask
 VPMASKMOVQ xmm1, xmm2, m128                                                 in xmm2 and store in xmm1.
 VEX.NDS.256.66.0F38.W1 8C /r                    RVM     V/V       AVX2      Conditionally load qword values from m256 using mask
 VPMASKMOVQ ymm1, ymm2, m256                                                 in ymm2 and store in ymm1.
 VEX.NDS.128.66.0F38.W0 8E /r                    MVR     V/V       AVX2      Conditionally store dword values from xmm2 using
 VPMASKMOVD m128, xmm1, xmm2                                                 mask in xmm1.
 VEX.NDS.256.66.0F38.W0 8E /r                    MVR     V/V       AVX2      Conditionally store dword values from ymm2 using
 VPMASKMOVD m256, ymm1, ymm2                                                 mask in ymm1.
 VEX.NDS.128.66.0F38.W1 8E /r                    MVR     V/V       AVX2      Conditionally store qword values from xmm2 using
 VPMASKMOVQ m128, xmm1, xmm2                                                 mask in xmm1.
 VEX.NDS.256.66.0F38.W1 8E /r                    MVR     V/V       AVX2      Conditionally store qword values from ymm2 using
 VPMASKMOVQ m256, ymm1, ymm2                                                 mask in ymm1.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                       Operand 2                  Operand 3                    Operand 4
    RVM              ModRM:reg (w)                     VEX.vvvv                 ModRM:r/m (r)                     NA
    MVR              ModRM:r/m (w)                     VEX.vvvv                 ModRM:reg (r)                     NA

Description
Conditionally moves packed data elements from the second source operand into the corresponding data element
of the destination operand, depending on the mask bits associated with each data element. The mask bits are
specified in the first source operand.
The mask bit for each data element is the most significant bit of that element in the first source operand. If a mask
is 1, the corresponding data element is copied from the second source operand to the destination operand. If the
mask is 0, the corresponding data element is set to zero in the load form of these instructions, and unmodified in
the store form.
The second source operand is a memory address for the load form of these instructions. The destination operand
is a memory address for the store form of these instructions. The other operands are either XMM registers (for
VEX.128 version) or YMM registers (for VEX.256 version).
Faults occur only due to mask-bit required memory accesses that caused the faults. Faults will not occur due to
referencing any memory location if the corresponding mask bit for that memory location is 0. For example, no
faults will be detected if the mask bits are all zero.
Unlike previous MASKMOV instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.
Instruction behavior on alignment check reporting with mask bits of less than all 1s are the same as with mask bits
of all 1s.





VMASKMOV should not be used to access memory mapped I/O as the ordering of the individual loads or stores it
does is implementation specific.
In cases where mask bits indicate data should not be loaded or stored paging A and D bits will be set in an imple-
mentation dependent way. However, A and D bits are always set for pages where data is actually loaded/stored.
Note: for load forms, the first source (the mask) is encoded in VEX.vvvv; the second source is encoded in rm_field,
and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the second source register is encoded in
reg_field, and the destination memory location is encoded in rm_field.

Operation
VPMASKMOVD - 256-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0

VPMASKMOVD -128-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] <- 0

VPMASKMOVQ - 256-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0

VPMASKMOVQ - 128-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] <- 0


VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
IF (SRC1[159]) DEST[159:128] <-SRC2[159:128]
IF (SRC1[191]) DEST[191:160] <- SRC2[191:160]
IF (SRC1[223]) DEST[223:192] <- SRC2[223:192]
IF (SRC1[255]) DEST[255:224] <- SRC2[255:224]





VPMASKMOVD - 128-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]

VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]
IF (SRC1[191]) DEST[191:128] <- SRC2[191:128]
IF (SRC1[255]) DEST[255:192] <- SRC2[255:192]

VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]

Intel C/C++ Compiler Intrinsic Equivalent
VPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)
VPMASKMOVD: void _mm256_maskstore_epi32(int *a, __m256i mask, __m256i b)
VPMASKMOVQ: __m256i _mm256_maskload_epi64(__int64 const *a, __m256i mask);
VPMASKMOVQ: void _mm256_maskstore_epi64(__int64 *a, __m256i mask, __m256d b);
VPMASKMOVD: __m128i _mm_maskload_epi32(int const *a, __m128i mask)
VPMASKMOVD: void _mm_maskstore_epi32(int *a, __m128i mask, __m128 b)
VPMASKMOVQ: __m128i _mm_maskload_epi64(__int cont *a, __m128i mask);
VPMASKMOVQ: void _mm_maskstore_epi64(__int64 *a, __m128i mask, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 6 (No AC# reported for any mask bit combinations).






platform: x86_64
mnem: VPMOVM2B
description:
VPMOVM2B/VPMOVM2W/VPMOVM2D/VPMOVM2Q-Convert a Mask Register to a Vector
Register
 Opcode/                          Op/    64/32      CPUID          Description
 Instruction                      En     bit Mode   Feature
                                         Support    Flag
 EVEX.128.F3.0F38.W0 28 /r        RM     V/V        AVX512VL       Sets each byte in XMM1 to all 1's or all 0's based on the value
 VPMOVM2B xmm1, k1                                  AVX512BW       of the corresponding bit in k1.
 EVEX.256.F3.0F38.W0 28 /r        RM     V/V        AVX512VL       Sets each byte in YMM1 to all 1's or all 0's based on the value
 VPMOVM2B ymm1, k1                                  AVX512BW       of the corresponding bit in k1.
 EVEX.512.F3.0F38.W0 28 /r        RM     V/V        AVX512BW       Sets each byte in ZMM1 to all 1's or all 0's based on the value
 VPMOVM2B zmm1, k1                                                 of the corresponding bit in k1.
 EVEX.128.F3.0F38.W1 28 /r        RM     V/V        AVX512VL       Sets each word in XMM1 to all 1's or all 0's based on the value
 VPMOVM2W xmm1, k1                                  AVX512BW       of the corresponding bit in k1.
 EVEX.256.F3.0F38.W1 28 /r        RM     V/V        AVX512VL       Sets each word in YMM1 to all 1's or all 0's based on the value
 VPMOVM2W ymm1, k1                                  AVX512BW       of the corresponding bit in k1.
 EVEX.512.F3.0F38.W1 28 /r        RM     V/V        AVX512BW       Sets each word in ZMM1 to all 1's or all 0's based on the value
 VPMOVM2W zmm1, k1                                                 of the corresponding bit in k1.
 EVEX.128.F3.0F38.W0 38 /r        RM     V/V        AVX512VL       Sets each doubleword in XMM1 to all 1's or all 0's based on the
 VPMOVM2D xmm1, k1                                  AVX512DQ       value of the corresponding bit in k1.
 EVEX.256.F3.0F38.W0 38 /r        RM     V/V        AVX512VL       Sets each doubleword in YMM1 to all 1's or all 0's based on the
 VPMOVM2D ymm1, k1                                  AVX512DQ       value of the corresponding bit in k1.
 EVEX.512.F3.0F38.W0 38 /r        RM     V/V        AVX512DQ       Sets each doubleword in ZMM1 to all 1's or all 0's based on the
 VPMOVM2D zmm1, k1                                                 value of the corresponding bit in k1.
 EVEX.128.F3.0F38.W1 38 /r        RM     V/V        AVX512VL       Sets each quadword in XMM1 to all 1's or all 0's based on the
 VPMOVM2Q xmm1, k1                                  AVX512DQ       value of the corresponding bit in k1.
 EVEX.256.F3.0F38.W1 38 /r        RM     V/V        AVX512VL       Sets each quadword in YMM1 to all 1's or all 0's based on the
 VPMOVM2Q ymm1, k1                                  AVX512DQ       value of the corresponding bit in k1.
 EVEX.512.F3.0F38.W1 38 /r        RM     V/V        AVX512DQ       Sets each quadword in ZMM1 to all 1's or all 0's based on the
 VPMOVM2Q zmm1, k1                                                 value of the corresponding bit in k1.



                                               Instruction Operand Encoding
        Op/En                Operand 1                 Operand 2                        Operand 3                Operand 4
         RM             ModRM:reg (w)                 ModRM:r/m (r)                         NA                       NA

Description
Converts a mask register to a vector register. Each element in the destination register is set to all 1's or all 0's
depending on the value of the corresponding bit in the source mask register.
The source operand is a mask register. The destination operand is a ZMM/YMM/XMM register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPMOVM2B (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF SRC[j]
         THEN     DEST[i+7:i] <- -1
         ELSE     DEST[i+7:i] <- 0
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVM2W (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF SRC[j]
         THEN     DEST[i+15:i] <- -1
         ELSE     DEST[i+15:i] <- 0
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVM2D (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF SRC[j]
         THEN     DEST[i+31:i] <- -1
         ELSE     DEST[i+31:i] <- 0
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVM2Q (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF SRC[j]
         THEN     DEST[i+63:i] <- -1
         ELSE     DEST[i+63:i] <- 0
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVM2B __m512i _mm512_movm_epi8(__mmask64 );
VPMOVM2D __m512i _mm512_movm_epi32(__mmask8 );
VPMOVM2Q __m512i _mm512_movm_epi64(__mmask16 );
VPMOVM2W __m512i _mm512_movm_epi16(__mmask32 );
VPMOVM2B __m256i _mm256_movm_epi8(__mmask32 );
VPMOVM2D __m256i _mm256_movm_epi32(__mmask8 );
VPMOVM2Q __m256i _mm256_movm_epi64(__mmask8 );
VPMOVM2W __m256i _mm256_movm_epi16(__mmask16 );
VPMOVM2B __m128i _mm_movm_epi8(__mmask16 );
VPMOVM2D __m128i _mm_movm_epi32(__mmask8 );
VPMOVM2Q __m128i _mm_movm_epi64(__mmask8 );
VPMOVM2W __m128i _mm_movm_epi16(__mmask8 );

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E7NM
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVB2M
description:
VPMOVB2M/VPMOVW2M/VPMOVD2M/VPMOVQ2M-Convert a Vector Register to a Mask
 Opcode/                      Op/      64/32      CPUID           Description
 Instruction                  En       bit Mode   Feature
                                       Support    Flag
 EVEX.128.F3.0F38.W0 29 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVB2M k1, xmm1                                AVX512BW        significant bit of the corresponding byte in XMM1.
 EVEX.256.F3.0F38.W0 29 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVB2M k1, ymm1                                AVX512BW        significant bit of the corresponding byte in YMM1.
 EVEX.512.F3.0F38.W0 29 /r    RM       V/V        AVX512BW        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVB2M k1, zmm1                                                significant bit of the corresponding byte in ZMM1.
 EVEX.128.F3.0F38.W1 29 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVW2M k1, xmm1                                AVX512BW        significant bit of the corresponding word in XMM1.
 EVEX.256.F3.0F38.W1 29 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVW2M k1, ymm1                                AVX512BW        significant bit of the corresponding word in YMM1.
 EVEX.512.F3.0F38.W1 29 /r    RM       V/V        AVX512BW        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVW2M k1, zmm1                                                significant bit of the corresponding word in ZMM1.
 EVEX.128.F3.0F38.W0 39 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVD2M k1, xmm1                                AVX512DQ        significant bit of the corresponding doubleword in XMM1.
 EVEX.256.F3.0F38.W0 39 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVD2M k1, ymm1                                AVX512DQ        significant bit of the corresponding doubleword in YMM1.
 EVEX.512.F3.0F38.W0 39 /r    RM       V/V        AVX512DQ        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVD2M k1, zmm1                                                significant bit of the corresponding doubleword in ZMM1.
 EVEX.128.F3.0F38.W1 39 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVQ2M k1, xmm1                                AVX512DQ        significant bit of the corresponding quadword in XMM1.
 EVEX.256.F3.0F38.W1 39 /r    RM       V/V        AVX512VL        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVQ2M k1, ymm1                                AVX512DQ        significant bit of the corresponding quadword in YMM1.
 EVEX.512.F3.0F38.W1 39 /r    RM       V/V        AVX512DQ        Sets each bit in k1 to 1 or 0 based on the value of the most
 VPMOVQ2M k1, zmm1                                                significant bit of the corresponding quadword in ZMM1.



                                             Instruction Operand Encoding
      Op/En              Operand 1                 Operand 2                      Operand 3                    Operand 4
       RM              ModRM:reg (w)              ModRM:r/m (r)                      NA                            NA

Description
Converts a vector register to a mask register. Each element in the destination register is set to 1 or 0 depending on
the value of most significant bit of the corresponding element in the source register.
The source operand is a ZMM/YMM/XMM register. The destination operand is a mask register.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPMOVB2M (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF SRC[i+7]
         THEN     DEST[j] <- 1
         ELSE     DEST[j] <- 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPMOVW2M (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF SRC[i+15]
         THEN      DEST[j] <- 1
         ELSE      DEST[j] <- 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPMOVD2M (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF SRC[i+31]
         THEN      DEST[j] <- 1
         ELSE      DEST[j] <- 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPMOVQ2M (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF SRC[i+63]
         THEN     DEST[j] <- 1
         ELSE     DEST[j] <- 0
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalents
VPMPOVB2M __mmask64 _mm512_movepi8_mask( __m512i );
VPMPOVD2M __mmask16 _mm512_movepi32_mask( __m512i );
VPMPOVQ2M __mmask8 _mm512_movepi64_mask( __m512i );
VPMPOVW2M __mmask32 _mm512_movepi16_mask( __m512i );
VPMPOVB2M __mmask32 _mm256_movepi8_mask( __m256i );
VPMPOVD2M __mmask8 _mm256_movepi32_mask( __m256i );
VPMPOVQ2M __mmask8 _mm256_movepi64_mask( __m256i );
VPMPOVW2M __mmask16 _mm256_movepi16_mask( __m256i );
VPMPOVB2M __mmask16 _mm_movepi8_mask( __m128i );
VPMPOVD2M __mmask8 _mm_movepi32_mask( __m128i );
VPMPOVQ2M __mmask8 _mm_movepi64_mask( __m128i );
VPMPOVW2M __mmask8 _mm_movepi16_mask( __m128i );

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E7NM
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVQB
description:
VPMOVQB/VPMOVSQB/VPMOVUSQB-Down Convert QWord to Byte
 Opcode/                              Op /     64/32       CPUID       Description
 Instruction                          En       bit Mode    Feature
                                               Support     Flag
 EVEX.128.F3.0F38.W0 32 /r            OVM      V/V         AVX512VL    Converts 2 packed quad-word integers from xmm2
 VPMOVQB xmm1/m16 {k1}{z}, xmm2                            AVX512F     into 2 packed byte integers in xmm1/m16 with
                                                                       truncation under writemask k1.
 EVEX.128.F3.0F38.W0 22 /r            OVM      V/V         AVX512VL    Converts 2 packed signed quad-word integers from
 VPMOVSQB xmm1/m16 {k1}{z}, xmm2                           AVX512F     xmm2 into 2 packed signed byte integers in
                                                                       xmm1/m16 using signed saturation under writemask
                                                                       k1.
 EVEX.128.F3.0F38.W0 12 /r            OVM      V/V         AVX512VL    Converts 2 packed unsigned quad-word integers
 VPMOVUSQB xmm1/m16 {k1}{z}, xmm2                          AVX512F     from xmm2 into 2 packed unsigned byte integers in
                                                                       xmm1/m16 using unsigned saturation under
                                                                       writemask k1.
 EVEX.256.F3.0F38.W0 32 /r            OVM      V/V         AVX512VL    Converts 4 packed quad-word integers from ymm2
 VPMOVQB xmm1/m32 {k1}{z}, ymm2                            AVX512F     into 4 packed byte integers in xmm1/m32 with
                                                                       truncation under writemask k1.
 EVEX.256.F3.0F38.W0 22 /r            OVM      V/V         AVX512VL    Converts 4 packed signed quad-word integers from
 VPMOVSQB xmm1/m32 {k1}{z}, ymm2                           AVX512F     ymm2 into 4 packed signed byte integers in
                                                                       xmm1/m32 using signed saturation under writemask
                                                                       k1.
 EVEX.256.F3.0F38.W0 12 /r            OVM      V/V         AVX512VL    Converts 4 packed unsigned quad-word integers
 VPMOVUSQB xmm1/m32 {k1}{z}, ymm2                          AVX512F     from ymm2 into 4 packed unsigned byte integers in
                                                                       xmm1/m32 using unsigned saturation under
                                                                       writemask k1.
 EVEX.512.F3.0F38.W0 32 /r            OVM      V/V         AVX512F     Converts 8 packed quad-word integers from zmm2
 VPMOVQB xmm1/m64 {k1}{z}, zmm2                                        into 8 packed byte integers in xmm1/m64 with
                                                                       truncation under writemask k1.
 EVEX.512.F3.0F38.W0 22 /r            OVM      V/V         AVX512F     Converts 8 packed signed quad-word integers from
 VPMOVSQB xmm1/m64 {k1}{z}, zmm2                                       zmm2 into 8 packed signed byte integers in
                                                                       xmm1/m64 using signed saturation under writemask
                                                                       k1.
 EVEX.512.F3.0F38.W0 12 /r            OVM      V/V         AVX512F     Converts 8 packed unsigned quad-word integers
 VPMOVUSQB xmm1/m64 {k1}{z}, zmm2                                      from zmm2 into 8 packed unsigned byte integers in
                                                                       xmm1/m64 using unsigned saturation under
                                                                       writemask k1.



                                             Instruction Operand Encoding
       Op/En            Operand 1                 Operand 2                 Operand 3                 Operand 4
        OVM           ModRM:r/m (w)              ModRM:reg (r)                 NA                         NA

Description
VPMOVQB down converts 64-bit integer elements in the source operand (the second operand) into packed byte
elements using truncation. VPMOVSQB converts signed 64-bit integers into packed signed bytes using signed satu-
ration. VPMOVUSQB convert unsigned quad-word values into unsigned byte values using unsigned saturation. The
source operand is a vector register. The destination operand is an XMM register or a memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-1:64) of the
destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPMOVQB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/8] <- 0;

VPMOVQB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateQuadWordToByte (SRC[m+63:m])
            ELSE
                  *DEST[i+7:i] remains unchanged*    ; merging-masking
       FI;
  ENDFOR

VPMOVSQB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/8] <- 0;





VPMOVSQB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedQuadWordToByte (SRC[m+63:m])
            ELSE
                  *DEST[i+7:i] remains unchanged*     ; merging-masking
       FI;
  ENDFOR

VPMOVUSQB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/8] <- 0;

VPMOVUSQB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedQuadWordToByte (SRC[m+63:m])
            ELSE
                  *DEST[i+7:i] remains unchanged*    ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQB __m128i _mm512_cvtepi64_epi8( __m512i a);
VPMOVQB __m128i _mm512_mask_cvtepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVQB __m128i _mm512_maskz_cvtepi64_epi8( __mmask8 k, __m512i a);
VPMOVQB void _mm512_mask_cvtepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_cvtsepi64_epi8( __m512i a);
VPMOVSQB __m128i _mm512_mask_cvtsepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVSQB __m128i _mm512_maskz_cvtsepi64_epi8( __mmask8 k, __m512i a);
VPMOVSQB void _mm512_mask_cvtsepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_cvtusepi64_epi8( __m512i a);
VPMOVUSQB __m128i _mm512_mask_cvtusepi64_epi8(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm512_maskz_cvtusepi64_epi8( __mmask8 k, __m512i a);
VPMOVUSQB void _mm512_mask_cvtusepi64_storeu_epi8(void * d, __mmask8 k, __m512i a);
VPMOVUSQB __m128i _mm256_cvtusepi64_epi8(__m256i a);
VPMOVUSQB __m128i _mm256_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm256_maskz_cvtusepi64_epi8( __mmask8 k, __m256i b);
VPMOVUSQB void _mm256_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSQB __m128i _mm_cvtusepi64_epi8(__m128i a);
VPMOVUSQB __m128i _mm_mask_cvtusepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQB __m128i _mm_maskz_cvtusepi64_epi8( __mmask8 k, __m128i b);
VPMOVUSQB void _mm_mask_cvtusepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm256_cvtsepi64_epi8(__m256i a);
VPMOVSQB __m128i _mm256_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm256_maskz_cvtsepi64_epi8( __mmask8 k, __m256i b);
VPMOVSQB void _mm256_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSQB __m128i _mm_cvtsepi64_epi8(__m128i a);
VPMOVSQB __m128i _mm_mask_cvtsepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSQB __m128i _mm_maskz_cvtsepi64_epi8( __mmask8 k, __m128i b);
VPMOVSQB void _mm_mask_cvtsepi64_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVQB __m128i _mm256_cvtepi64_epi8(__m256i a);
VPMOVQB __m128i _mm256_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVQB __m128i _mm256_maskz_cvtepi64_epi8( __mmask8 k, __m256i b);
VPMOVQB void _mm256_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVQB __m128i _mm_cvtepi64_epi8(__m128i a);
VPMOVQB __m128i _mm_mask_cvtepi64_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVQB __m128i _mm_maskz_cvtepi64_epi8( __mmask8 k, __m128i b);
VPMOVQB void _mm_mask_cvtepi64_storeu_epi8(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVQW
description:
VPMOVQW/VPMOVSQW/VPMOVUSQW-Down Convert QWord to Word
 Opcode/                              Op /     64/32      CPUID        Description
 Instruction                          En       bit Mode   Feature
                                               Support    Flag
 EVEX.128.F3.0F38.W0 34 /r            QVM      V/V        AVX512VL     Converts 2 packed quad-word integers from xmm2
 VPMOVQW xmm1/m32 {k1}{z}, xmm2                           AVX512F      into 2 packed word integers in xmm1/m32 with
                                                                       truncation under writemask k1.
 EVEX.128.F3.0F38.W0 24 /r            QVM      V/V        AVX512VL     Converts 8 packed signed quad-word integers from
 VPMOVSQW xmm1/m32 {k1}{z}, xmm2                          AVX512F      zmm2 into 8 packed signed word integers in
                                                                       xmm1/m32 using signed saturation under writemask
                                                                       k1.
 EVEX.128.F3.0F38.W0 14 /r            QVM      V/V        AVX512VL     Converts 2 packed unsigned quad-word integers from
 VPMOVUSQW xmm1/m32 {k1}{z}, xmm2                         AVX512F      xmm2 into 2 packed unsigned word integers in
                                                                       xmm1/m32 using unsigned saturation under
                                                                       writemask k1.
 EVEX.256.F3.0F38.W0 34 /r            QVM      V/V        AVX512VL     Converts 4 packed quad-word integers from ymm2
 VPMOVQW xmm1/m64 {k1}{z}, ymm2                           AVX512F      into 4 packed word integers in xmm1/m64 with
                                                                       truncation under writemask k1.
 EVEX.256.F3.0F38.W0 24 /r            QVM      V/V        AVX512VL     Converts 4 packed signed quad-word integers from
 VPMOVSQW xmm1/m64 {k1}{z}, ymm2                          AVX512F      ymm2 into 4 packed signed word integers in
                                                                       xmm1/m64 using signed saturation under writemask
                                                                       k1.
 EVEX.256.F3.0F38.W0 14 /r            QVM      V/V        AVX512VL     Converts 4 packed unsigned quad-word integers from
 VPMOVUSQW xmm1/m64 {k1}{z}, ymm2                         AVX512F      ymm2 into 4 packed unsigned word integers in
                                                                       xmm1/m64 using unsigned saturation under
                                                                       writemask k1.
 EVEX.512.F3.0F38.W0 34 /r            QVM      V/V        AVX512F      Converts 8 packed quad-word integers from zmm2
 VPMOVQW xmm1/m128 {k1}{z}, zmm2                                       into 8 packed word integers in xmm1/m128 with
                                                                       truncation under writemask k1.
 EVEX.512.F3.0F38.W0 24 /r            QVM      V/V        AVX512F      Converts 8 packed signed quad-word integers from
 VPMOVSQW xmm1/m128 {k1}{z}, zmm2                                      zmm2 into 8 packed signed word integers in
                                                                       xmm1/m128 using signed saturation under
                                                                       writemask k1.
 EVEX.512.F3.0F38.W0 14 /r            QVM      V/V        AVX512F      Converts 8 packed unsigned quad-word integers from
 VPMOVUSQW xmm1/m128 {k1}{z},                                          zmm2 into 8 packed unsigned word integers in
 zmm2                                                                  xmm1/m128 using unsigned saturation under
                                                                       writemask k1.



                                             Instruction Operand Encoding
      Op/En            Operand 1                 Operand 2                  Operand 3                  Operand 4
       QVM           ModRM:r/m (w)              ModRM:reg (r)                  NA                         NA

Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSQW converts signed 64-bit integers into packed signed words using signed saturation.
VPMOVUSQW convert unsigned quad-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL-
1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.




Operation
VPMOVQW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- TruncateQuadWordToWord (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;

VPMOVQW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- TruncateQuadWordToWord (SRC[m+63:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVSQW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateSignedQuadWordToWord (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;





VPMOVSQW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateSignedQuadWordToWord (SRC[m+63:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVUSQW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateUnsignedQuadWordToWord (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;

VPMOVUSQW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateUnsignedQuadWordToWord (SRC[m+63:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQW __m128i _mm512_cvtepi64_epi16( __m512i a);
VPMOVQW __m128i _mm512_mask_cvtepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVQW __m128i _mm512_maskz_cvtepi64_epi16( __mmask8 k, __m512i a);
VPMOVQW void _mm512_mask_cvtepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_cvtsepi64_epi16( __m512i a);
VPMOVSQW __m128i _mm512_mask_cvtsepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVSQW __m128i _mm512_maskz_cvtsepi64_epi16( __mmask8 k, __m512i a);
VPMOVSQW void _mm512_mask_cvtsepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_cvtusepi64_epi16( __m512i a);
VPMOVUSQW __m128i _mm512_mask_cvtusepi64_epi16(__m128i s, __mmask8 k, __m512i a);
VPMOVUSQW __m128i _mm512_maskz_cvtusepi64_epi16( __mmask8 k, __m512i a);
VPMOVUSQW void _mm512_mask_cvtusepi64_storeu_epi16(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVQD
description:
VPMOVQD/VPMOVSQD/VPMOVUSQD-Down Convert QWord to DWord
 Opcode/                               Op /   64/32      CPUID         Description
 Instruction                           En     bit Mode   Feature
                                              Support    Flag
 EVEX.128.F3.0F38.W0 35 /r             A      V/V        AVX512VL      Converts 2 packed quad-word integers from xmm2
 VPMOVQD xmm1/m128 {k1}{z}, xmm2                         AVX512F       into 2 packed double-word integers in xmm1/m128
                                                                       with truncation subject to writemask k1.
 EVEX.128.F3.0F38.W0 25 /r             A      V/V        AVX512VL      Converts 2 packed signed quad-word integers from
 VPMOVSQD xmm1/m64 {k1}{z}, xmm2                         AVX512F       xmm2 into 2 packed signed double-word integers
                                                                       in xmm1/m64 using signed saturation subject to
                                                                       writemask k1.
 EVEX.128.F3.0F38.W0 15 /r             A      V/V        AVX512VL      Converts 2 packed unsigned quad-word integers
 VPMOVUSQD xmm1/m64 {k1}{z}, xmm2                        AVX512F       from xmm2 into 2 packed unsigned double-word
                                                                       integers in xmm1/m64 using unsigned saturation
                                                                       subject to writemask k1.
 EVEX.256.F3.0F38.W0 35 /r             A      V/V        AVX512VL      Converts 4 packed quad-word integers from ymm2
 VPMOVQD xmm1/m128 {k1}{z}, ymm2                         AVX512F       into 4 packed double-word integers in xmm1/m128
                                                                       with truncation subject to writemask k1.
 EVEX.256.F3.0F38.W0 25 /r             A      V/V        AVX512VL      Converts 4 packed signed quad-word integers from
 VPMOVSQD xmm1/m128 {k1}{z}, ymm2                        AVX512F       ymm2 into 4 packed signed double-word integers in
                                                                       xmm1/m128 using signed saturation subject to
                                                                       writemask k1.
 EVEX.256.F3.0F38.W0 15 /r             A      V/V        AVX512VL      Converts 4 packed unsigned quad-word integers
 VPMOVUSQD xmm1/m128 {k1}{z}, ymm2                       AVX512F       from ymm2 into 4 packed unsigned double-word
                                                                       integers in xmm1/m128 using unsigned saturation
                                                                       subject to writemask k1.
 EVEX.512.F3.0F38.W0 35 /r             HVM    V/V        AVX512F       Converts 8 packed quad-word integers from zmm2
 VPMOVQD ymm1/m256 {k1}{z}, zmm2                                       into 8 packed double-word integers in ymm1/m256
                                                                       with truncation subject to writemask k1.
 EVEX.512.F3.0F38.W0 25 /r             HVM    V/V        AVX512F       Converts 8 packed signed quad-word integers from
 VPMOVSQD ymm1/m256 {k1}{z}, zmm2                                      zmm2 into 8 packed signed double-word integers in
                                                                       ymm1/m256 using signed saturation subject to
                                                                       writemask k1.
 EVEX.512.F3.0F38.W0 15 /r             HVM    V/V        AVX512F       Converts 8 packed unsigned quad-word integers
 VPMOVUSQD ymm1/m256 {k1}{z}, zmm2                                     from zmm2 into 8 packed unsigned double-word
                                                                       integers in ymm1/m256 using unsigned saturation
                                                                       subject to writemask k1.



                                           Instruction Operand Encoding
       Op/En             Operand 1               Operand 2                  Operand 3                  Operand 4
        HVM            ModRM:r/m (w)           ModRM:reg (r)                   NA                          NA

Description
VPMOVQW down converts 64-bit integer elements in the source operand (the second operand) into packed double-
words using truncation. VPMOVSQW converts signed 64-bit integers into packed signed doublewords using signed
saturation. VPMOVUSQW convert unsigned quad-word values into unsigned double-word values using unsigned
saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted doubleword elements are written to the destination operand (the first operand) from the least-
significant doubleword. Doubleword elements of the destination operand are updated according to the writemask.
Bits (MAX_VL-1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.



Operation
VPMOVQD instruction (EVEX encoded version) reg-reg form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- TruncateQuadWordToDWord (SRC[m+63:m])
            ELSE *zeroing-masking*           ; zeroing-masking
                            DEST[i+31:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVQD instruction (EVEX encoded version) memory form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- TruncateQuadWordToDWord (SRC[m+63:m])
            ELSE *DEST[i+31:i] remains unchanged*   ; merging-masking
       FI;
  ENDFOR

VPMOVSQD instruction (EVEX encoded version) reg-reg form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- SaturateSignedQuadWordToDWord (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+31:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+31:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;





VPMOVSQD instruction (EVEX encoded version) memory form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- SaturateSignedQuadWordToDWord (SRC[m+63:m])
            ELSE *DEST[i+31:i] remains unchanged*    ; merging-masking
       FI;
  ENDFOR

VPMOVUSQD instruction (EVEX encoded version) reg-reg form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+31:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+31:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVUSQD instruction (EVEX encoded version) memory form
  (KL, VL) = (2, 128), (4, 256), (8, 512)
  FOR j <- 0 TO KL-1
       i <- j * 32
       m <- j * 64
       IF k1[j] OR *no writemask*
            THEN DEST[i+31:i] <- SaturateUnsignedQuadWordToDWord (SRC[m+63:m])
            ELSE *DEST[i+31:i] remains unchanged*    ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVQD __m256i _mm512_cvtepi64_epi32( __m512i a);
VPMOVQD __m256i _mm512_mask_cvtepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVQD __m256i _mm512_maskz_cvtepi64_epi32( __mmask8 k, __m512i a);
VPMOVQD void _mm512_mask_cvtepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_cvtsepi64_epi32( __m512i a);
VPMOVSQD __m256i _mm512_mask_cvtsepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVSQD __m256i _mm512_maskz_cvtsepi64_epi32( __mmask8 k, __m512i a);
VPMOVSQD void _mm512_mask_cvtsepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_cvtusepi64_epi32( __m512i a);
VPMOVUSQD __m256i _mm512_mask_cvtusepi64_epi32(__m256i s, __mmask8 k, __m512i a);
VPMOVUSQD __m256i _mm512_maskz_cvtusepi64_epi32( __mmask8 k, __m512i a);
VPMOVUSQD void _mm512_mask_cvtusepi64_storeu_epi32(void * d, __mmask8 k, __m512i a);
VPMOVUSQD __m128i _mm256_cvtusepi64_epi32(__m256i a);
VPMOVUSQD __m128i _mm256_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm256_maskz_cvtusepi64_epi32( __mmask8 k, __m256i b);
VPMOVUSQD void _mm256_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVUSQD __m128i _mm_cvtusepi64_epi32(__m128i a);
VPMOVUSQD __m128i _mm_mask_cvtusepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVUSQD __m128i _mm_maskz_cvtusepi64_epi32( __mmask8 k, __m128i b);
VPMOVUSQD void _mm_mask_cvtusepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm256_cvtsepi64_epi32(__m256i a);
VPMOVSQD __m128i _mm256_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm256_maskz_cvtsepi64_epi32( __mmask8 k, __m256i b);
VPMOVSQD void _mm256_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVSQD __m128i _mm_cvtsepi64_epi32(__m128i a);
VPMOVSQD __m128i _mm_mask_cvtsepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSQD __m128i _mm_maskz_cvtsepi64_epi32( __mmask8 k, __m128i b);
VPMOVSQD void _mm_mask_cvtsepi64_storeu_epi32(void * , __mmask8 k, __m128i b);
VPMOVQD __m128i _mm256_cvtepi64_epi32(__m256i a);
VPMOVQD __m128i _mm256_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m256i b);
VPMOVQD __m128i _mm256_maskz_cvtepi64_epi32( __mmask8 k, __m256i b);
VPMOVQD void _mm256_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m256i b);
VPMOVQD __m128i _mm_cvtepi64_epi32(__m128i a);
VPMOVQD __m128i _mm_mask_cvtepi64_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVQD __m128i _mm_maskz_cvtepi64_epi32( __mmask8 k, __m128i b);
VPMOVQD void _mm_mask_cvtepi64_storeu_epi32(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVDB
description:
VPMOVDB/VPMOVSDB/VPMOVUSDB-Down Convert DWord to Byte
 Opcode/                              Op /     64/32       CPUID      Description
 Instruction                          En       bit Mode    Feature
                                               Support     Flag
 EVEX.128.F3.0F38.W0 31 /r            QVM      V/V         AVX512VL   Converts 4 packed double-word integers from xmm2
 VPMOVDB xmm1/m32 {k1}{z}, xmm2                            AVX512F    into 4 packed byte integers in xmm1/m32 with
                                                                      truncation under writemask k1.
 EVEX.128.F3.0F38.W0 21 /r            QVM      V/V         AVX512VL   Converts 4 packed signed double-word integers from
 VPMOVSDB xmm1/m32 {k1}{z}, xmm2                           AVX512F    xmm2 into 4 packed signed byte integers in
                                                                      xmm1/m32 using signed saturation under writemask
                                                                      k1.
 EVEX.128.F3.0F38.W0 11 /r            QVM      V/V         AVX512VL   Converts 4 packed unsigned double-word integers
 VPMOVUSDB xmm1/m32 {k1}{z},                               AVX512F    from xmm2 into 4 packed unsigned byte integers in
 xmm2                                                                 xmm1/m32 using unsigned saturation under
                                                                      writemask k1.
 EVEX.256.F3.0F38.W0 31 /r            QVM      V/V         AVX512VL   Converts 8 packed double-word integers from ymm2
 VPMOVDB xmm1/m64 {k1}{z}, ymm2                            AVX512F    into 8 packed byte integers in xmm1/m64 with
                                                                      truncation under writemask k1.
 EVEX.256.F3.0F38.W0 21 /r            QVM      V/V         AVX512VL   Converts 8 packed signed double-word integers from
 VPMOVSDB xmm1/m64 {k1}{z}, ymm2                           AVX512F    ymm2 into 8 packed signed byte integers in
                                                                      xmm1/m64 using signed saturation under writemask
                                                                      k1.
 EVEX.256.F3.0F38.W0 11 /r            QVM      V/V         AVX512VL   Converts 8 packed unsigned double-word integers
 VPMOVUSDB xmm1/m64 {k1}{z}, ymm2                          AVX512F    from ymm2 into 8 packed unsigned byte integers in
                                                                      xmm1/m64 using unsigned saturation under
                                                                      writemask k1.
 EVEX.512.F3.0F38.W0 31 /r            QVM      V/V         AVX512F    Converts 16 packed double-word integers from zmm2
 VPMOVDB xmm1/m128 {k1}{z}, zmm2                                      into 16 packed byte integers in xmm1/m128 with
                                                                      truncation under writemask k1.
 EVEX.512.F3.0F38.W0 21 /r            QVM      V/V         AVX512F    Converts 16 packed signed double-word integers
 VPMOVSDB xmm1/m128 {k1}{z}, zmm2                                     from zmm2 into 16 packed signed byte integers in
                                                                      xmm1/m128 using signed saturation under
                                                                      writemask k1.
 EVEX.512.F3.0F38.W0 11 /r            QVM      V/V         AVX512F    Converts 16 packed unsigned double-word integers
 VPMOVUSDB xmm1/m128 {k1}{z},                                         from zmm2 into 16 packed unsigned byte integers in
 zmm2                                                                 xmm1/m128 using unsigned saturation under
                                                                      writemask k1.



                                             Instruction Operand Encoding
      Op/En             Operand 1                    Operand 2              Operand 3                  Operand 4
       QVM            ModRM:r/m (w)              ModRM:reg (r)                 NA                         NA

Description
VPMOVDB down converts 32-bit integer elements in the source operand (the second operand) into packed bytes
using truncation. VPMOVSDB converts signed 32-bit integers into packed signed bytes using signed saturation.
VPMOVUSDB convert unsigned double-word values into unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a XMM register or a 128/64/32-bit
memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-
1:128/64/32) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.




Operation
VPMOVDB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateDoubleWordToByte (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;

VPMOVDB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateDoubleWordToByte (SRC[m+31:m])
            ELSE *DEST[i+7:i] remains unchanged*     ; merging-masking
       FI;
  ENDFOR

VPMOVSDB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedDoubleWordToByte (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;





VPMOVSDB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedDoubleWordToByte (SRC[m+31:m])
            ELSE *DEST[i+7:i] remains unchanged*      ; merging-masking
       FI;
  ENDFOR

VPMOVUSDB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/4] <- 0;

VPMOVUSDB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i<-j*8
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedDoubleWordToByte (SRC[m+31:m])
            ELSE *DEST[i+7:i] remains unchanged*      ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDB __m128i _mm512_cvtepi32_epi8( __m512i a);
VPMOVDB __m128i _mm512_mask_cvtepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVDB __m128i _mm512_maskz_cvtepi32_epi8( __mmask16 k, __m512i a);
VPMOVDB void _mm512_mask_cvtepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_cvtsepi32_epi8( __m512i a);
VPMOVSDB __m128i _mm512_mask_cvtsepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVSDB __m128i _mm512_maskz_cvtsepi32_epi8( __mmask16 k, __m512i a);
VPMOVSDB void _mm512_mask_cvtsepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_cvtusepi32_epi8( __m512i a);
VPMOVUSDB __m128i _mm512_mask_cvtusepi32_epi8(__m128i s, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm512_maskz_cvtusepi32_epi8( __mmask16 k, __m512i a);
VPMOVUSDB void _mm512_mask_cvtusepi32_storeu_epi8(void * d, __mmask16 k, __m512i a);
VPMOVUSDB __m128i _mm256_cvtusepi32_epi8(__m256i a);
VPMOVUSDB __m128i _mm256_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm256_maskz_cvtusepi32_epi8( __mmask8 k, __m256i b);
VPMOVUSDB void _mm256_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVUSDB __m128i _mm_cvtusepi32_epi8(__m128i a);
VPMOVUSDB __m128i _mm_mask_cvtusepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDB __m128i _mm_maskz_cvtusepi32_epi8( __mmask8 k, __m128i b);
VPMOVUSDB void _mm_mask_cvtusepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm256_cvtsepi32_epi8(__m256i a);
VPMOVSDB __m128i _mm256_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm256_maskz_cvtsepi32_epi8( __mmask8 k, __m256i b);
VPMOVSDB void _mm256_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVSDB __m128i _mm_cvtsepi32_epi8(__m128i a);
VPMOVSDB __m128i _mm_mask_cvtsepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSDB __m128i _mm_maskz_cvtsepi32_epi8( __mmask8 k, __m128i b);
VPMOVSDB void _mm_mask_cvtsepi32_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVDB __m128i _mm256_cvtepi32_epi8(__m256i a);
VPMOVDB __m128i _mm256_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m256i b);
VPMOVDB __m128i _mm256_maskz_cvtepi32_epi8( __mmask8 k, __m256i b);
VPMOVDB void _mm256_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m256i b);
VPMOVDB __m128i _mm_cvtepi32_epi8(__m128i a);
VPMOVDB __m128i _mm_mask_cvtepi32_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVDB __m128i _mm_maskz_cvtepi32_epi8( __mmask8 k, __m128i b);
VPMOVDB void _mm_mask_cvtepi32_storeu_epi8(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVDW
description:
VPMOVDW/VPMOVSDW/VPMOVUSDW-Down Convert DWord to Word
 Opcode/                              Op /      64/32         CPUID      Description
 Instruction                          En        bit Mode      Feature
                                                Support       Flag
 EVEX.128.F3.0F38.W0 33 /r            HVM       V/V           AVX512VL   Converts 4 packed double-word integers from
 VPMOVDW xmm1/m64 {k1}{z}, xmm2                               AVX512F    xmm2 into 4 packed word integers in xmm1/m64
                                                                         with truncation under writemask k1.
 EVEX.128.F3.0F38.W0 23 /r            HVM       V/V           AVX512VL   Converts 4 packed signed double-word integers
 VPMOVSDW xmm1/m64 {k1}{z}, xmm2                              AVX512F    from xmm2 into 4 packed signed word integers in
                                                                         ymm1/m64 using signed saturation under
                                                                         writemask k1.
 EVEX.128.F3.0F38.W0 13 /r            HVM       V/V           AVX512VL   Converts 4 packed unsigned double-word integers
 VPMOVUSDW xmm1/m64 {k1}{z}, xmm2                             AVX512F    from xmm2 into 4 packed unsigned word integers
                                                                         in xmm1/m64 using unsigned saturation under
                                                                         writemask k1.
 EVEX.256.F3.0F38.W0 33 /r            HVM       V/V           AVX512VL   Converts 8 packed double-word integers from
 VPMOVDW xmm1/m128 {k1}{z}, ymm2                              AVX512F    ymm2 into 8 packed word integers in xmm1/m128
                                                                         with truncation under writemask k1.
 EVEX.256.F3.0F38.W0 23 /r            HVM       V/V           AVX512VL   Converts 8 packed signed double-word integers
 VPMOVSDW xmm1/m128 {k1}{z}, ymm2                             AVX512F    from ymm2 into 8 packed signed word integers in
                                                                         xmm1/m128 using signed saturation under
                                                                         writemask k1.
 EVEX.256.F3.0F38.W0 13 /r            HVM       V/V           AVX512VL   Converts 8 packed unsigned double-word integers
 VPMOVUSDW xmm1/m128 {k1}{z},                                 AVX512F    from ymm2 into 8 packed unsigned word integers
 ymm2                                                                    in xmm1/m128 using unsigned saturation under
                                                                         writemask k1.
 EVEX.512.F3.0F38.W0 33 /r            HVM       V/V           AVX512F    Converts 16 packed double-word integers from
 VPMOVDW ymm1/m256 {k1}{z}, zmm2                                         zmm2 into 16 packed word integers in
                                                                         ymm1/m256 with truncation under writemask k1.
 EVEX.512.F3.0F38.W0 23 /r            HVM       V/V           AVX512F    Converts 16 packed signed double-word integers
 VPMOVSDW ymm1/m256 {k1}{z}, zmm2                                        from zmm2 into 16 packed signed word integers in
                                                                         ymm1/m256 using signed saturation under
                                                                         writemask k1.
 EVEX.512.F3.0F38.W0 13 /r            HVM       V/V           AVX512F    Converts 16 packed unsigned double-word integers
 VPMOVUSDW ymm1/m256 {k1}{z},                                            from zmm2 into 16 packed unsigned word integers
 zmm2                                                                    in ymm1/m256 using unsigned saturation under
                                                                         writemask k1.



                                             Instruction Operand Encoding
      Op/En            Operand 1                  Operand 2                 Operand 3                  Operand 4
       HVM           ModRM:r/m (w)              ModRM:reg (r)                   NA                         NA

Description
VPMOVDW down converts 32-bit integer elements in the source operand (the second operand) into packed words
using truncation. VPMOVSDW converts signed 32-bit integers into packed signed words using signed saturation.
VPMOVUSDW convert unsigned double-word values into unsigned word values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted word elements are written to the destination operand (the first operand) from the least-significant
word. Word elements of the destination operand are updated according to the writemask. Bits (MAX_VL-
1:256/128/64) of the register destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.




Operation
VPMOVDW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- TruncateDoubleWordToWord (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVDW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- TruncateDoubleWordToWord (SRC[m+31:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVSDW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateSignedDoubleWordToWord (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;





VPMOVSDW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateSignedDoubleWordToWord (SRC[m+31:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVUSDW instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+15:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+15:i] <- 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVUSDW instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (4, 128), (8, 256), (16, 512)
  FOR j <- 0 TO KL-1
       i <- j * 16
       m <- j * 32
       IF k1[j] OR *no writemask*
            THEN DEST[i+15:i] <- SaturateUnsignedDoubleWordToWord (SRC[m+31:m])
            ELSE
                  *DEST[i+15:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVDW __m256i _mm512_cvtepi32_epi16( __m512i a);
VPMOVDW __m256i _mm512_mask_cvtepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVDW __m256i _mm512_maskz_cvtepi32_epi16( __mmask16 k, __m512i a);
VPMOVDW void _mm512_mask_cvtepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_cvtsepi32_epi16( __m512i a);
VPMOVSDW __m256i _mm512_mask_cvtsepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVSDW __m256i _mm512_maskz_cvtsepi32_epi16( __mmask16 k, __m512i a);
VPMOVSDW void _mm512_mask_cvtsepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_cvtusepi32_epi16 __m512i a);
VPMOVUSDW __m256i _mm512_mask_cvtusepi32_epi16(__m256i s, __mmask16 k, __m512i a);
VPMOVUSDW __m256i _mm512_maskz_cvtusepi32_epi16( __mmask16 k, __m512i a);
VPMOVUSDW void _mm512_mask_cvtusepi32_storeu_epi16(void * d, __mmask16 k, __m512i a);
VPMOVUSDW __m128i _mm256_cvtusepi32_epi16(__m256i a);
VPMOVUSDW __m128i _mm256_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm256_maskz_cvtusepi32_epi16( __mmask8 k, __m256i b);
VPMOVUSDW void _mm256_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVUSDW __m128i _mm_cvtusepi32_epi16(__m128i a);
VPMOVUSDW __m128i _mm_mask_cvtusepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVUSDW __m128i _mm_maskz_cvtusepi32_epi16( __mmask8 k, __m128i b);
VPMOVUSDW void _mm_mask_cvtusepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm256_cvtsepi32_epi16(__m256i a);
VPMOVSDW __m128i _mm256_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm256_maskz_cvtsepi32_epi16( __mmask8 k, __m256i b);
VPMOVSDW void _mm256_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVSDW __m128i _mm_cvtsepi32_epi16(__m128i a);
VPMOVSDW __m128i _mm_mask_cvtsepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSDW __m128i _mm_maskz_cvtsepi32_epi16( __mmask8 k, __m128i b);
VPMOVSDW void _mm_mask_cvtsepi32_storeu_epi16(void * , __mmask8 k, __m128i b);
VPMOVDW __m128i _mm256_cvtepi32_epi16(__m256i a);
VPMOVDW __m128i _mm256_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m256i b);
VPMOVDW __m128i _mm256_maskz_cvtepi32_epi16( __mmask8 k, __m256i b);
VPMOVDW void _mm256_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m256i b);
VPMOVDW __m128i _mm_cvtepi32_epi16(__m128i a);
VPMOVDW __m128i _mm_mask_cvtepi32_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVDW __m128i _mm_maskz_cvtepi32_epi16( __mmask8 k, __m128i b);
VPMOVDW void _mm_mask_cvtepi32_storeu_epi16(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VPMOVWB
description:
VPMOVWB/VPMOVSWB/VPMOVUSWB-Down Convert Word to Byte
 Opcode/                               Op /    64/32        CPUID          Description
 Instruction                           En      bit Mode     Feature
                                               Support      Flag
 EVEX.128.F3.0F38.W0 30 /r             HVM     V/V          AVX512VL       Converts 8 packed word integers from xmm2 into 8
 VPMOVWB xmm1/m64 {k1}{z}, xmm2                             AVX512BW       packed bytes in xmm1/m64 with truncation under
                                                                           writemask k1.
 EVEX.128.F3.0F38.W0 20 /r             HVM     V/V          AVX512VL       Converts 8 packed signed word integers from xmm2
 VPMOVSWB xmm1/m64 {k1}{z},                                 AVX512BW       into 8 packed signed bytes in xmm1/m64 using
 xmm2                                                                      signed saturation under writemask k1.
 EVEX.128.F3.0F38.W0 10 /r             HVM     V/V          AVX512VL       Converts 8 packed unsigned word integers from
 VPMOVUSWB xmm1/m64 {k1}{z},                                AVX512BW       xmm2 into 8 packed unsigned bytes in 8mm1/m64
 xmm2                                                                      using unsigned saturation under writemask k1.
 EVEX.256.F3.0F38.W0 30 /r             HVM     V/V          AVX512VL       Converts 16 packed word integers from ymm2 into
 VPMOVWB xmm1/m128 {k1}{z},                                 AVX512BW       16 packed bytes in xmm1/m128 with truncation
 ymm2                                                                      under writemask k1.
 EVEX.256.F3.0F38.W0 20 /r             HVM     V/V          AVX512VL       Converts 16 packed signed word integers from ymm2
 VPMOVSWB xmm1/m128 {k1}{z},                                AVX512BW       into 16 packed signed bytes in xmm1/m128 using
 ymm2                                                                      signed saturation under writemask k1.
 EVEX.256.F3.0F38.W0 10 /r             HVM     V/V          AVX512VL       Converts 16 packed unsigned word integers from
 VPMOVUSWB xmm1/m128 {k1}{z},                               AVX512BW       ymm2 into 16 packed unsigned bytes in xmm1/m128
 ymm2                                                                      using unsigned saturation under writemask k1.
 EVEX.512.F3.0F38.W0 30 /r             HVM     V/V          AVX512BW       Converts 32 packed word integers from zmm2 into
 VPMOVWB ymm1/m256 {k1}{z},                                                32 packed bytes in ymm1/m256 with truncation
 zmm2                                                                      under writemask k1.
 EVEX.512.F3.0F38.W0 20 /r             HVM     V/V          AVX512BW       Converts 32 packed signed word integers from zmm2
 VPMOVSWB ymm1/m256 {k1}{z},                                               into 32 packed signed bytes in ymm1/m256 using
 zmm2                                                                      signed saturation under writemask k1.
 EVEX.512.F3.0F38.W0 10 /r             HVM     V/V          AVX512BW       Converts 32 packed unsigned word integers from
 VPMOVUSWB ymm1/m256 {k1}{z},                                              zmm2 into 32 packed unsigned bytes in ymm1/m256
 zmm2                                                                      using unsigned saturation under writemask k1.



                                              Instruction Operand Encoding
         Op/En             Operand 1                       Operand 2                     Operand 3             Operand 4
         HVM             ModRM:r/m (w)                    ModRM:reg (r)                     NA                    NA

Description
VPMOVWB down converts 16-bit integers into packed bytes using truncation. VPMOVSWB converts signed 16-bit
integers into packed signed bytes using signed saturation. VPMOVUSWB convert unsigned word values into
unsigned byte values using unsigned saturation.
The source operand is a ZMM/YMM/XMM register. The destination operand is a YMM/XMM/XMM register or a
256/128/64-bit memory location.
Down-converted byte elements are written to the destination operand (the first operand) from the least-significant
byte. Byte elements of the destination operand are updated according to the writemask. Bits (MAX_VL-
1:256/128/64) of the register destination are zeroed.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VPMOVWB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateWordToByte (SRC[m+15:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] = 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVWB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- TruncateWordToByte (SRC[m+15:m])
            ELSE
                  *DEST[i+7:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVSWB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedWordToByte (SRC[m+15:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] = 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;





VPMOVSWB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateSignedWordToByte (SRC[m+15:m])
            ELSE
                  *DEST[i+7:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR

VPMOVUSWB instruction (EVEX encoded versions) when dest is a register
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedWordToByte (SRC[m+15:m])
            ELSE
                  IF *merging-masking*                ; merging-masking
                       THEN *DEST[i+7:i] remains unchanged*
                       ELSE *zeroing-masking*              ; zeroing-masking
                            DEST[i+7:i] = 0
                  FI
       FI;
  ENDFOR
  DEST[MAX_VL-1:VL/2] <- 0;

VPMOVUSWB instruction (EVEX encoded versions) when dest is memory
  (KL, VL) = (8, 128), (16, 256), (32, 512)
  FOR j <- 0 TO Kl-1
       i<-j*8
       m <- j * 16
       IF k1[j] OR *no writemask*
            THEN DEST[i+7:i] <- SaturateUnsignedWordToByte (SRC[m+15:m])
            ELSE
                  *DEST[i+7:i] remains unchanged* ; merging-masking
       FI;
  ENDFOR





Intel C/C++ Compiler Intrinsic Equivalents
VPMOVUSWB __m256i _mm512_cvtusepi16_epi8(__m512i a);
VPMOVUSWB __m256i _mm512_mask_cvtusepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVUSWB __m256i _mm512_maskz_cvtusepi16_epi8( __mmask32 k, __m512i b);
VPMOVUSWB void _mm512_mask_cvtusepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_cvtsepi16_epi8(__m512i a);
VPMOVSWB __m256i _mm512_mask_cvtsepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVSWB __m256i _mm512_maskz_cvtsepi16_epi8( __mmask32 k, __m512i b);
VPMOVSWB void _mm512_mask_cvtsepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_cvtepi16_epi8(__m512i a);
VPMOVWB __m256i _mm512_mask_cvtepi16_epi8(__m256i a, __mmask32 k, __m512i b);
VPMOVWB __m256i _mm512_maskz_cvtepi16_epi8( __mmask32 k, __m512i b);
VPMOVWB void _mm512_mask_cvtepi16_storeu_epi8(void * , __mmask32 k, __m512i b);
VPMOVUSWB __m128i _mm256_cvtusepi16_epi8(__m256i a);
VPMOVUSWB __m128i _mm256_mask_cvtusepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm256_maskz_cvtusepi16_epi8( __mmask16 k, __m256i b);
VPMOVUSWB void _mm256_mask_cvtusepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVUSWB __m128i _mm_cvtusepi16_epi8(__m128i a);
VPMOVUSWB __m128i _mm_mask_cvtusepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVUSWB __m128i _mm_maskz_cvtusepi16_epi8( __mmask8 k, __m128i b);
VPMOVUSWB void _mm_mask_cvtusepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm256_cvtsepi16_epi8(__m256i a);
VPMOVSWB __m128i _mm256_mask_cvtsepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm256_maskz_cvtsepi16_epi8( __mmask16 k, __m256i b);
VPMOVSWB void _mm256_mask_cvtsepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVSWB __m128i _mm_cvtsepi16_epi8(__m128i a);
VPMOVSWB __m128i _mm_mask_cvtsepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVSWB __m128i _mm_maskz_cvtsepi16_epi8( __mmask8 k, __m128i b);
VPMOVSWB void _mm_mask_cvtsepi16_storeu_epi8(void * , __mmask8 k, __m128i b);
VPMOVWB __m128i _mm256_cvtepi16_epi8(__m256i a);
VPMOVWB __m128i _mm256_mask_cvtepi16_epi8(__m128i a, __mmask16 k, __m256i b);
VPMOVWB __m128i _mm256_maskz_cvtepi16_epi8( __mmask16 k, __m256i b);
VPMOVWB void _mm256_mask_cvtepi16_storeu_epi8(void * , __mmask16 k, __m256i b);
VPMOVWB __m128i _mm_cvtepi16_epi8(__m128i a);
VPMOVWB __m128i _mm_mask_cvtepi16_epi8(__m128i a, __mmask8 k, __m128i b);
VPMOVWB __m128i _mm_maskz_cvtepi16_epi8( __mmask8 k, __m128i b);
VPMOVWB void _mm_mask_cvtepi16_storeu_epi8(void * , __mmask8 k, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6NF
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: PROLD
description:
PROLD/PROLVD/PROLQ/PROLVQ-Bit Rotate Left
 Opcode/                                  Op / En   64/32      CPUID      Description
 Instruction                                        bit Mode   Feature
                                                    Support    Flag
 EVEX.NDS.128.66.0F38.W0 15 /r            FV-RVM    V/V        AVX512VL   Rotate doublewords in xmm2 left by count in the
 VPROLVD xmm1 {k1}{z}, xmm2,                                   AVX512F    corresponding element of xmm3/m128/m32bcst.
 xmm3/m128/m32bcst                                                        Result written to xmm1 under writemask k1.
 EVEX.NDD.128.66.0F.W0 72 /1 ib           FV-VMI    V/V        AVX512VL   Rotate doublewords in xmm2/m128/m32bcst left
 VPROLD xmm1 {k1}{z},                                          AVX512F    by imm8. Result written to xmm1 using
 xmm2/m128/m32bcst, imm8                                                  writemask k1.
 EVEX.NDS.128.66.0F38.W1 15 /r            FV-RVM    V/V        AVX512VL   Rotate quadwords in xmm2 left by count in the
 VPROLVQ xmm1 {k1}{z}, xmm2,                                   AVX512F    corresponding element of xmm3/m128/m64bcst.
 xmm3/m128/m64bcst                                                        Result written to xmm1 under writemask k1.
 EVEX.NDD.128.66.0F.W1 72 /1 ib           FV-VMI    V/V        AVX512VL   Rotate quadwords in xmm2/m128/m64bcst left
 VPROLQ xmm1 {k1}{z},                                          AVX512F    by imm8. Result written to xmm1 using
 xmm2/m128/m64bcst, imm8                                                  writemask k1.
 EVEX.NDS.256.66.0F38.W0 15 /r            FV-RVM    V/V        AVX512VL   Rotate doublewords in ymm2 left by count in the
 VPROLVD ymm1 {k1}{z}, ymm2,                                   AVX512F    corresponding element of ymm3/m256/m32bcst.
 ymm3/m256/m32bcst                                                        Result written to ymm1 under writemask k1.
 EVEX.NDD.256.66.0F.W0 72 /1 ib           FV-VMI    V/V        AVX512VL   Rotate doublewords in ymm2/m256/m32bcst left
 VPROLD ymm1 {k1}{z},                                          AVX512F    by imm8. Result written to ymm1 using
 ymm2/m256/m32bcst, imm8                                                  writemask k1.
 EVEX.NDS.256.66.0F38.W1 15 /r            FV-RVM    V/V        AVX512VL   Rotate quadwords in ymm2 left by count in the
 VPROLVQ ymm1 {k1}{z}, ymm2,                                   AVX512F    corresponding element of ymm3/m256/m64bcst.
 ymm3/m256/m64bcst                                                        Result written to ymm1 under writemask k1.
 EVEX.NDD.256.66.0F.W1 72 /1 ib           FV-VMI    V/V        AVX512VL   Rotate quadwords in ymm2/m256/m64bcst left
 VPROLQ ymm1 {k1}{z},                                          AVX512F    by imm8. Result written to ymm1 using
 ymm2/m256/m64bcst, imm8                                                  writemask k1.
 EVEX.NDS.512.66.0F38.W0 15 /r            FV-RVM    V/V        AVX512F    Rotate left of doublewords in zmm2 by count in
 VPROLVD zmm1 {k1}{z}, zmm2,                                              the corresponding element of
 zmm3/m512/m32bcst                                                        zmm3/m512/m32bcst. Result written to zmm1
                                                                          using writemask k1.
 EVEX.NDD.512.66.0F.W0 72 /1 ib           FV-VMI    V/V        AVX512F    Rotate left of doublewords in
 VPROLD zmm1 {k1}{z},                                                     zmm3/m512/m32bcst by imm8. Result written to
 zmm2/m512/m32bcst, imm8                                                  zmm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W1 15 /r            FV-RVM    V/V        AVX512F    Rotate quadwords in zmm2 left by count in the
 VPROLVQ zmm1 {k1}{z}, zmm2,                                              corresponding element of zmm3/m512/m64bcst.
 zmm3/m512/m64bcst                                                        Result written to zmm1under writemask k1.
 EVEX.NDD.512.66.0F.W1 72 /1 ib           FV-VMI    V/V        AVX512F    Rotate quadwords in zmm2/m512/m64bcst left
 VPROLQ zmm1 {k1}{z},                                                     by imm8. Result written to zmm1 using
 zmm2/m512/m64bcst, imm8                                                  writemask k1.



                                               Instruction Operand Encoding
        Op/En               Operand 1                  Operand 2               Operand 3                Operand 4
       FV-VMI              VEX.vvvv (w)              ModRM:r/m (R)               Imm8                       NA
       FV-RVM             ModRM:reg (w)              EVEX.vvvv (r)            ModRM:r/m (r)                 NA





Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the left
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.

Operation
LEFT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC modulo 32;
DEST[31:0] <- (SRC << COUNT) | (SRC >> (32 - COUNT));

LEFT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC modulo 64;
DEST[63:0] <- (SRC << COUNT) | (SRC >> (64 - COUNT));

VPROLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[31:0], imm8)
                    ELSE DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPROLVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
                    ELSE DEST[i+31:i] <- LEFT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPROLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[63:0], imm8)
                    ELSE DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPROLVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
                    ELSE DEST[i+63:i] <- LEFT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPROLD __m512i _mm512_rol_epi32(__m512i a, int imm);
VPROLD __m512i _mm512_mask_rol_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPROLD __m512i _mm512_maskz_rol_epi32( __mmask16 k, __m512i a, int imm);
VPROLD __m256i _mm256_rol_epi32(__m256i a, int imm);
VPROLD __m256i _mm256_mask_rol_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLD __m256i _mm256_maskz_rol_epi32( __mmask8 k, __m256i a, int imm);
VPROLD __m128i _mm_rol_epi32(__m128i a, int imm);
VPROLD __m128i _mm_mask_rol_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLD __m128i _mm_maskz_rol_epi32( __mmask8 k, __m128i a, int imm);
VPROLQ __m512i _mm512_rol_epi64(__m512i a, int imm);
VPROLQ __m512i _mm512_mask_rol_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPROLQ __m512i _mm512_maskz_rol_epi64(__mmask8 k, __m512i a, int imm);
VPROLQ __m256i _mm256_rol_epi64(__m256i a, int imm);
VPROLQ __m256i _mm256_mask_rol_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPROLQ __m256i _mm256_maskz_rol_epi64( __mmask8 k, __m256i a, int imm);
VPROLQ __m128i _mm_rol_epi64(__m128i a, int imm);
VPROLQ __m128i _mm_mask_rol_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPROLQ __m128i _mm_maskz_rol_epi64( __mmask8 k, __m128i a, int imm);
VPROLVD __m512i _mm512_rolv_epi32(__m512i a, __m512i cnt);
VPROLVD __m512i _mm512_mask_rolv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPROLVD __m512i _mm512_maskz_rolv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPROLVD __m256i _mm256_rolv_epi32(__m256i a, __m256i cnt);
VPROLVD __m256i _mm256_mask_rolv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVD __m256i _mm256_maskz_rolv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPROLVD __m128i _mm_rolv_epi32(__m128i a, __m128i cnt);
VPROLVD __m128i _mm_mask_rolv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVD __m128i _mm_maskz_rolv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPROLVQ __m512i _mm512_rolv_epi64(__m512i a, __m512i cnt);
VPROLVQ __m512i _mm512_mask_rolv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPROLVQ __m512i _mm512_maskz_rolv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPROLVQ __m256i _mm256_rolv_epi64(__m256i a, __m256i cnt);
VPROLVQ __m256i _mm256_mask_rolv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPROLVQ __m256i _mm256_maskz_rolv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPROLVQ __m128i _mm_rolv_epi64(__m128i a, __m128i cnt);
VPROLVQ __m128i _mm_mask_rolv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPROLVQ __m128i _mm_maskz_rolv_epi64(__mmask8 k, __m128i a, __m128i cnt);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PRORD
description:
PRORD/PRORVD/PRORQ/PRORVQ-Bit Rotate Right
 Opcode/                                 Op / En   64/32        CPUID      Description
 Instruction                                       bit Mode     Feature
                                                   Support      Flag
 EVEX.NDS.128.66.0F38.W0 14 /r           FV-RVM    V/V          AVX512VL   Rotate doublewords in xmm2 right by count in
 VPRORVD xmm1 {k1}{z}, xmm2,                                    AVX512F    the corresponding element of
 xmm3/m128/m32bcst                                                         xmm3/m128/m32bcst, store result using
                                                                           writemask k1.
 EVEX.NDD.128.66.0F.W0 72 /0 ib          FV-VMI    V/V          AVX512VL   Rotate doublewords in xmm2/m128/m32bcst
 VPRORD xmm1 {k1}{z},                                           AVX512F    right by imm8, store result using writemask k1.
 xmm2/m128/m32bcst, imm8
 EVEX.NDS.128.66.0F38.W1 14 /r           FV-RVM    V/V          AVX512VL   Rotate quadwords in xmm2 right by count in the
 VPRORVQ xmm1 {k1}{z}, xmm2,                                    AVX512F    corresponding element of xmm3/m128/m64bcst,
 xmm3/m128/m64bcst                                                         store result using writemask k1.
 EVEX.NDD.128.66.0F.W1 72 /0 ib          FV-VMI    V/V          AVX512VL   Rotate quadwords in xmm2/m128/m64bcst right
 VPRORQ xmm1 {k1}{z},                                           AVX512F    by imm8, store result using writemask k1.
 xmm2/m128/m64bcst, imm8
 EVEX.NDS.256.66.0F38.W0 14 /r           FV-RVM    V/V          AVX512VL   Rotate doublewords in ymm2 right by count in
 VPRORVD ymm1 {k1}{z}, ymm2,                                    AVX512F    the corresponding element of
 ymm3/m256/m32bcst                                                         ymm3/m256/m32bcst, store using result
                                                                           writemask k1.
 EVEX.NDD.256.66.0F.W0 72 /0 ib          FV-VMI    V/V          AVX512VL   Rotate doublewords in ymm2/m256/m32bcst
 VPRORD ymm1 {k1}{z},                                           AVX512F    right by imm8, store result using writemask k1.
 ymm2/m256/m32bcst, imm8
 EVEX.NDS.256.66.0F38.W1 14 /r           FV-RVM    V/V          AVX512VL   Rotate quadwords in ymm2 right by count in the
 VPRORVQ ymm1 {k1}{z}, ymm2,                                    AVX512F    corresponding element of ymm3/m256/m64bcst,
 ymm3/m256/m64bcst                                                         store result using writemask k1.
 EVEX.NDD.256.66.0F.W1 72 /0 ib          FV-VMI    V/V          AVX512VL   Rotate quadwords in ymm2/m256/m64bcst right
 VPRORQ ymm1 {k1}{z},                                           AVX512F    by imm8, store result using writemask k1.
 ymm2/m256/m64bcst, imm8
 EVEX.NDS.512.66.0F38.W0 14 /r           FV-RVM    V/V          AVX512F    Rotate doublewords in zmm2 right by count in
 VPRORVD zmm1 {k1}{z}, zmm2,                                               the corresponding element of
 zmm3/m512/m32bcst                                                         zmm3/m512/m32bcst, store result using
                                                                           writemask k1.
 EVEX.NDD.512.66.0F.W0 72 /0 ib          FV-VMI    V/V          AVX512F    Rotate doublewords in zmm2/m512/m32bcst
 VPRORD zmm1 {k1}{z},                                                      right by imm8, store result using writemask k1.
 zmm2/m512/m32bcst, imm8
 EVEX.NDS.512.66.0F38.W1 14 /r           FV-RVM    V/V          AVX512F    Rotate quadwords in zmm2 right by count in the
 VPRORVQ zmm1 {k1}{z}, zmm2,                                               corresponding element of zmm3/m512/m64bcst,
 zmm3/m512/m64bcst                                                         store result using writemask k1.
 EVEX.NDD.512.66.0F.W1 72 /0 ib          FV-VMI    V/V          AVX512F    Rotate quadwords in zmm2/m512/m64bcst right
 VPRORQ zmm1 {k1}{z},                                                      by imm8, store result using writemask k1.
 zmm2/m512/m64bcst, imm8



                                             Instruction Operand Encoding
       Op/En               Operand 1                Operand 2                Operand 3                   Operand 4
      FV-VMI              VEX.vvvv (w)             ModRM:r/m (R)               Imm8                          NA
      FV-RVM             ModRM:reg (w)             EVEX.vvvv (r)            ModRM:r/m (r)                    NA





Description
Rotates the bits in the individual data elements (doublewords, or quadword) in the first source operand to the right
by the number of bits specified in the count operand. If the value specified by the count operand is greater than 31
(for doublewords), or 63 (for a quadword), then the count operand modulo the data size (32 or 64) is used.
EVEX.128 encoded version: The destination operand is a XMM register. The source operand is a XMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
EVEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location (for immediate form). The count operand can come either from an XMM register or a memory
location or an 8-bit immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX.512 encoded version: The destination operand is a ZMM register updated according to the writemask. For the
count operand in immediate form, the source operand can be a ZMM register, a 512-bit memory location or a 512-
bit vector broadcasted from a 32/64-bit memory location, the count operand is an 8-bit immediate. For the count
operand in variable form, the first source operand (the second operand) is a ZMM register and the counter operand
(the third operand) is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location.

Operation
RIGHT_ROTATE_DWORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC modulo 32;
DEST[31:0] <- (SRC >> COUNT) | (SRC << (32 - COUNT));

RIGHT_ROTATE_QWORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC modulo 64;
DEST[63:0] <- (SRC >> COUNT) | (SRC << (64 - COUNT));

VPRORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+31:i] <- RIGHT_ROTATE_DWORDS( SRC1[31:0], imm8)
                    ELSE DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPRORVD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[31:0])
                    ELSE DEST[i+31:i] <- RIGHT_ROTATE_DWORDS(SRC1[i+31:i], SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPRORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[63:0], imm8)
                    ELSE DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], imm8])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPRORVQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[63:0])
                    ELSE DEST[i+63:i] <- RIGHT_ROTATE_QWORDS(SRC1[i+63:i], SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPRORD __m512i _mm512_ror_epi32(__m512i a, int imm);
VPRORD __m512i _mm512_mask_ror_epi32(__m512i a, __mmask16 k, __m512i b, int imm);
VPRORD __m512i _mm512_maskz_ror_epi32( __mmask16 k, __m512i a, int imm);
VPRORD __m256i _mm256_ror_epi32(__m256i a, int imm);
VPRORD __m256i _mm256_mask_ror_epi32(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORD __m256i _mm256_maskz_ror_epi32( __mmask8 k, __m256i a, int imm);
VPRORD __m128i _mm_ror_epi32(__m128i a, int imm);
VPRORD __m128i _mm_mask_ror_epi32(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORD __m128i _mm_maskz_ror_epi32( __mmask8 k, __m128i a, int imm);
VPRORQ __m512i _mm512_ror_epi64(__m512i a, int imm);
VPRORQ __m512i _mm512_mask_ror_epi64(__m512i a, __mmask8 k, __m512i b, int imm);
VPRORQ __m512i _mm512_maskz_ror_epi64(__mmask8 k, __m512i a, int imm);
VPRORQ __m256i _mm256_ror_epi64(__m256i a, int imm);
VPRORQ __m256i _mm256_mask_ror_epi64(__m256i a, __mmask8 k, __m256i b, int imm);
VPRORQ __m256i _mm256_maskz_ror_epi64( __mmask8 k, __m256i a, int imm);
VPRORQ __m128i _mm_ror_epi64(__m128i a, int imm);
VPRORQ __m128i _mm_mask_ror_epi64(__m128i a, __mmask8 k, __m128i b, int imm);
VPRORQ __m128i _mm_maskz_ror_epi64( __mmask8 k, __m128i a, int imm);
VPRORVD __m512i _mm512_rorv_epi32(__m512i a, __m512i cnt);
VPRORVD __m512i _mm512_mask_rorv_epi32(__m512i a, __mmask16 k, __m512i b, __m512i cnt);
VPRORVD __m512i _mm512_maskz_rorv_epi32(__mmask16 k, __m512i a, __m512i cnt);
VPRORVD __m256i _mm256_rorv_epi32(__m256i a, __m256i cnt);
VPRORVD __m256i _mm256_mask_rorv_epi32(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVD __m256i _mm256_maskz_rorv_epi32(__mmask8 k, __m256i a, __m256i cnt);
VPRORVD __m128i _mm_rorv_epi32(__m128i a, __m128i cnt);
VPRORVD __m128i _mm_mask_rorv_epi32(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVD __m128i _mm_maskz_rorv_epi32(__mmask8 k, __m128i a, __m128i cnt);
VPRORVQ __m512i _mm512_rorv_epi64(__m512i a, __m512i cnt);
VPRORVQ __m512i _mm512_mask_rorv_epi64(__m512i a, __mmask8 k, __m512i b, __m512i cnt);
VPRORVQ __m512i _mm512_maskz_rorv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPRORVQ __m256i _mm256_rorv_epi64(__m256i a, __m256i cnt);
VPRORVQ __m256i _mm256_mask_rorv_epi64(__m256i a, __mmask8 k, __m256i b, __m256i cnt);
VPRORVQ __m256i _mm256_maskz_rorv_epi64(__mmask8 k, __m256i a, __m256i cnt);
VPRORVQ __m128i _mm_rorv_epi64(__m128i a, __m128i cnt);
VPRORVQ __m128i _mm_mask_rorv_epi64(__m128i a, __mmask8 k, __m128i b, __m128i cnt);
VPRORVQ __m128i _mm_maskz_rorv_epi64(__mmask8 k, __m128i a, __m128i cnt);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPSCATTERDD
description:
VPSCATTERDD/VPSCATTERDQ/VPSCATTERQD/VPSCATTERQQ-Scatter Packed Dword, Packed
Qword with Signed Dword, Signed Qword Indices
    Opcode/                              Op/     64/32       CPUID        Description
    Instruction                          En      bit Mode    Feature
                                                 Support     Flag
    EVEX.128.66.0F38.W0 A0 /vsib         T1S     V/V         AVX512VL     Using signed dword indices, scatter dword values to
    VPSCATTERDD vm32x {k1}, xmm1                             AVX512F      memory using writemask k1.
    EVEX.256.66.0F38.W0 A0 /vsib         T1S     V/V         AVX512VL     Using signed dword indices, scatter dword values to
    VPSCATTERDD vm32y {k1}, ymm1                             AVX512F      memory using writemask k1.
    EVEX.512.66.0F38.W0 A0 /vsib         T1S     V/V         AVX512F      Using signed dword indices, scatter dword values to
    VPSCATTERDD vm32z {k1}, zmm1                                          memory using writemask k1.
    EVEX.128.66.0F38.W1 A0 /vsib         T1S     V/V         AVX512VL     Using signed dword indices, scatter qword values to
    VPSCATTERDQ vm32x {k1}, xmm1                             AVX512F      memory using writemask k1.
    EVEX.256.66.0F38.W1 A0 /vsib         T1S     V/V         AVX512VL     Using signed dword indices, scatter qword values to
    VPSCATTERDQ vm32x {k1}, ymm1                             AVX512F      memory using writemask k1.
    EVEX.512.66.0F38.W1 A0 /vsib         T1S     V/V         AVX512F      Using signed dword indices, scatter qword values to
    VPSCATTERDQ vm32y {k1}, zmm1                                          memory using writemask k1.
    EVEX.128.66.0F38.W0 A1 /vsib         T1S     V/V         AVX512VL     Using signed qword indices, scatter dword values to
    VPSCATTERQD vm64x {k1}, xmm1                             AVX512F      memory using writemask k1.
    EVEX.256.66.0F38.W0 A1 /vsib         T1S     V/V         AVX512VL     Using signed qword indices, scatter dword values to
    VPSCATTERQD vm64y {k1}, xmm1                             AVX512F      memory using writemask k1.
    EVEX.512.66.0F38.W0 A1 /vsib         T1S     V/V         AVX512F      Using signed qword indices, scatter dword values to
    VPSCATTERQD vm64z {k1}, ymm1                                          memory using writemask k1.
    EVEX.128.66.0F38.W1 A1 /vsib         T1S     V/V         AVX512VL     Using signed qword indices, scatter qword values to
    VPSCATTERQQ vm64x {k1}, xmm1                             AVX512F      memory using writemask k1.
    EVEX.256.66.0F38.W1 A1 /vsib         T1S     V/V         AVX512VL     Using signed qword indices, scatter qword values to
    VPSCATTERQQ vm64y {k1}, ymm1                             AVX512F      memory using writemask k1.
    EVEX.512.66.0F38.W1 A1 /vsib         T1S     V/V         AVX512F      Using signed qword indices, scatter qword values to
    VPSCATTERQQ vm64z {k1}, zmm1                                          memory using writemask k1.



                                                Instruction Operand Encoding
         Op/En              Operand 1                   Operand 2                 Operand 3                    Operand 4
                      BaseReg (R): VSIB:base,
          T1S                                          ModRM:reg (r)                    NA                        NA
                     VectorReg(R): VSIB:index

Description
Stores up to 16 elements (8 elements for qword indices) in doubleword vector or 8 elements in quadword vector to
the memory locations pointed by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The
elements are specified via the VSIB (i.e., the index register is a vector register, holding packed indices). Elements
will only be stored if their corresponding mask bit is one. The entire mask register will be set to zero by this instruc-
tion unless it triggers an exception.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register are partially updated. If any traps or interrupts are pending from already scattered
elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction break-
point is not re-triggered when the instruction is continued.
Note that:
.     Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
      MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
      overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
      ordering model. Note that this does not account for non-overlapping indices that map into the same physical
      address locations.



.   If two or more destination indices completely overlap, the "earlier" write(s) may be skipped.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination ZMM will be completed (and non-faulting). Individual elements
    closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
    in the conventional order.
.   Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   Not valid with 16-bit effective addresses. Will deliver a #UD fault.
.   If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
    the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
    instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the k0 mask register is specified.
The instruction will #UD fault if EVEX.Z = 1.





Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement





VPSCATTERDD (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] <- SRC[i+31:i]
              k1[j] <- 0

   FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VPSCATTERDQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] <- SRC[i+63:i]
              k1[j] <- 0
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VPSCATTERQD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 64
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] <- SRC[i+31:i]
              k1[j] <- 0

   FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VPSCATTERQQ (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR + (VINDEX[j+63:j]) * SCALE + DISP] <- SRC[i+63:i]
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPSCATTERDD void _mm512_i32scatter_epi32(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_i32scatter_epi32(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_i32scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDD void _mm512_mask_i32scatter_epi32(void * base, __mmask16 k, __m512i vdx, __m512i a, int scale);
VPSCATTERDD void _mm256_mask_i32scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERDD void _mm_mask_i32scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_i32scatter_epi64(void * base, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_i32scatter_epi64(void * base, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_i32scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERDQ void _mm512_mask_i32scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m512i a, int scale);
VPSCATTERDQ void _mm256_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m256i a, int scale);
VPSCATTERDQ void _mm_mask_i32scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_i64scatter_epi32(void * base, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_i64scatter_epi32(void * base, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_i64scatter_epi32(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQD void _mm512_mask_i64scatter_epi32(void * base, __mmask8 k, __m512i vdx, __m256i a, int scale);
VPSCATTERQD void _mm256_mask_i64scatter_epi32(void * base, __mmask8 k, __m256i vdx, __m128i a, int scale);
VPSCATTERQD void _mm_mask_i64scatter_epi32(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_i64scatter_epi64(void * base, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_i64scatter_epi64(void * base, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_i64scatter_epi64(void * base, __m128i vdx, __m128i a, int scale);
VPSCATTERQQ void _mm512_mask_i64scatter_epi64(void * base, __mmask8 k, __m512i vdx, __m512i a, int scale);
VPSCATTERQQ void _mm256_mask_i64scatter_epi64(void * base, __mmask8 k, __m256i vdx, __m256i a, int scale);
VPSCATTERQQ void _mm_mask_i64scatter_epi64(void * base, __mmask8 k, __m128i vdx, __m128i a, int scale);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12.






