# instructions

platform: x86_64
mnem: MUL
description:
MUL-Unsigned Multiply
 Opcode                    Instruction                   Op/   64-Bit          Compat/ Description
                                                         En    Mode            Leg Mode
 F6 /4                     MUL r/m8                      M     Valid           Valid         Unsigned multiply (AX <- AL * r/m8).
 REX + F6 /4               MUL r/m8*                     M     Valid           N.E.          Unsigned multiply (AX <- AL * r/m8).
 F7 /4                     MUL r/m16                     M     Valid           Valid         Unsigned multiply (DX:AX <- AX * r/m16).
 F7 /4                     MUL r/m32                     M     Valid           Valid         Unsigned multiply (EDX:EAX <- EAX * r/m32).
 REX.W + F7 /4             MUL r/m64                     M     Valid           N.E.          Unsigned multiply (RDX:RAX <- RAX * r/m64).
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                           Operand 3                    Operand 4
     M              ModRM:r/m (r)                        NA                                 NA                           NA


Description
Performs an unsigned multiplication of the first operand (destination operand) and the second operand (source
operand) and stores the result in the destination operand. The destination operand is an implied operand located in
register AL, AX or EAX (depending on the size of the operand); the source operand is located in a general-purpose
register or a memory location. The action of this instruction and the location of the result depends on the opcode
and the operand size as shown in Table 4-9.
The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX (depending on the operand size),
with the high-order bits of the product contained in register AH, DX, or EDX, respectively. If the high-order bits of
the product are 0, the CF and OF flags are cleared; otherwise, the flags are set.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits.
See the summary chart at the beginning of this section for encoding data and limits.


                                                     Table 4-9. MUL Results
           Operand Size                       Source 1                                Source 2                      Destination
 Byte                             AL                                   r/m8                               AX
 Word                             AX                                   r/m16                              DX:AX
 Doubleword                       EAX                                  r/m32                              EDX:EAX
 Quadword                         RAX                                  r/m64                              RDX:RAX





Operation
IF (Byte operation)
    THEN
         AX <- AL * SRC;
    ELSE (* Word or doubleword operation *)
         IF OperandSize = 16
              THEN
                  DX:AX <- AX * SRC;
              ELSE IF OperandSize = 32
                  THEN EDX:EAX <- EAX * SRC; FI;
              ELSE (* OperandSize = 64 *)
                  RDX:RAX <- RAX * SRC;
         FI;
FI;

Flags Affected
The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise, they are set to 1. The SF, ZF, AF, and
PF flags are undefined.

Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                  If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                  If the memory address is in a non-canonical form.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.




platform: x86_64
mnem: MULPD
description:
MULPD-Multiply Packed Double-Precision Floating-Point Values
 Opcode/                                Op /    64/32        CPUID      Description
 Instruction                            En      bit Mode     Feature
                                                Support      Flag
 66 0F 59 /r                            RM      V/V          SSE2       Multiply packed double-precision floating-point values
 MULPD xmm1, xmm2/m128                                                  in xmm2/m128 with xmm1 and store result in xmm1.
 VEX.NDS.128.66.0F.WIG 59 /r            RVM     V/V          AVX        Multiply packed double-precision floating-point values
 VMULPD xmm1,xmm2, xmm3/m128                                            in xmm3/m128 with xmm2 and store result in xmm1.
 VEX.NDS.256.66.0F.WIG 59 /r            RVM     V/V          AVX        Multiply packed double-precision floating-point values
 VMULPD ymm1, ymm2, ymm3/m256                                           in ymm3/m256 with ymm2 and store result in ymm1.
 EVEX.NDS.128.66.0F.W1 59 /r            FV      V/V          AVX512VL   Multiply packed double-precision floating-point values
 VMULPD xmm1 {k1}{z}, xmm2,                                  AVX512F    from xmm3/m128/m64bcst to xmm2 and store result
 xmm3/m128/m64bcst                                                      in xmm1.
 EVEX.NDS.256.66.0F.W1 59 /r            FV      V/V          AVX512VL   Multiply packed double-precision floating-point values
 VMULPD ymm1 {k1}{z}, ymm2,                                  AVX512F    from ymm3/m256/m64bcst to ymm2 and store result
 ymm3/m256/m64bcst                                                      in ymm1.
 EVEX.NDS.512.66.0F.W1 59 /r            FV      V/V          AVX512F    Multiply packed double-precision floating-point values
 VMULPD zmm1 {k1}{z}, zmm2,                                             in zmm3/m512/m64bcst with zmm2 and store result
 zmm3/m512/m64bcst{er}                                                  in zmm1.



                                               Instruction Operand Encoding
      Op/En             Operand 1                      Operand 2                Operand 3                      Operand 4
        RM           ModRM:reg (r, w)                 ModRM:r/m (r)                 NA                            NA
       RVM            ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                       NA
        FV            ModRM:reg (w)                   EVEX.vvvv (r)           ModRM:r/m (r)                       NA

Description
Multiply packed double-precision floating-point values from the first source operand with corresponding values in
the second source operand, and stores the packed double-precision floating-point results in the destination
operand.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the
corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the destination YMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.





Operation
VMULPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- SRC1[i+63:i] * SRC2[63:0]
                    ELSE
                         DEST[i+63:i] <- SRC1[i+63:i] * SRC2[i+63:i]
               FI;
         ELSE
               IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                            ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMULPD (VEX.256 encoded version)
DEST[63:0] <-SRC1[63:0] * SRC2[63:0]
DEST[127:64] <-SRC1[127:64] * SRC2[127:64]
DEST[191:128] <-SRC1[191:128] * SRC2[191:128]
DEST[255:192] <-SRC1[255:192] * SRC2[255:192]
DEST[MAX_VL-1:256] <-0;
.
VMULPD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0] * SRC2[63:0]
DEST[127:64] <-SRC1[127:64] * SRC2[127:64]
DEST[MAX_VL-1:128] <-0

MULPD (128-bit Legacy SSE version)
DEST[63:0] <-DEST[63:0] * SRC[63:0]
DEST[127:64] <-DEST[127:64] * SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VMULPD __m512d _mm512_mul_pd( __m512d a, __m512d b);
VMULPD __m512d _mm512_mask_mul_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VMULPD __m512d _mm512_maskz_mul_pd( __mmask8 k, __m512d a, __m512d b);
VMULPD __m512d _mm512_mul_round_pd( __m512d a, __m512d b, int);
VMULPD __m512d _mm512_mask_mul_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMULPD __m512d _mm512_maskz_mul_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMULPD __m256d _mm256_mul_pd (__m256d a, __m256d b);
MULPD __m128d _mm_mul_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MULPS
description:
MULPS-Multiply Packed Single-Precision Floating-Point Values
 Opcode/                                     Op /     64/32         CPUID      Description
 Instruction                                 En       bit Mode      Feature
                                                      Support       Flag
 0F 59 /r                                    RM       V/V           SSE        Multiply packed single-precision floating-point values in
 MULPS xmm1, xmm2/m128                                                         xmm2/m128 with xmm1 and store result in xmm1.
 VEX.NDS.128.0F.WIG 59 /r                    RVM      V/V           AVX        Multiply packed single-precision floating-point values in
 VMULPS xmm1,xmm2, xmm3/m128                                                   xmm3/m128 with xmm2 and store result in xmm1.
 VEX.NDS.256.0F.WIG 59 /r                    RVM      V/V           AVX        Multiply packed single-precision floating-point values in
 VMULPS ymm1, ymm2, ymm3/m256                                                  ymm3/m256 with ymm2 and store result in ymm1.
 EVEX.NDS.128.0F.W0 59 /r                    FV       V/V           AVX512VL   Multiply packed single-precision floating-point values
 VMULPS xmm1 {k1}{z}, xmm2,                                         AVX512F    from xmm3/m128/m32bcst to xmm2 and store result in
 xmm3/m128/m32bcst                                                             xmm1.
 EVEX.NDS.256.0F.W0 59 /r                    FV       V/V           AVX512VL   Multiply packed single-precision floating-point values
 VMULPS ymm1 {k1}{z}, ymm2,                                         AVX512F    from ymm3/m256/m32bcst to ymm2 and store result in
 ymm3/m256/m32bcst                                                             ymm1.
 EVEX.NDS.512.0F.W0 59 /r                    FV       V/V           AVX512F    Multiply packed single-precision floating-point values in
 VMULPS zmm1 {k1}{z}, zmm2,                                                    zmm3/m512/m32bcst with zmm2 and store result in
 zmm3/m512/m32bcst {er}                                                        zmm1.



                                                     Instruction Operand Encoding
        Op/En                   Operand 1                       Operand 2                Operand 3                   Operand 4
          RM                 ModRM:reg (r, w)                  ModRM:r/m (r)                 NA                          NA
         RVM                  ModRM:reg (w)                    VEX.vvvv (r)            ModRM:r/m (r)                     NA
          FV                  ModRM:reg (w)                    EVEX.vvvv (r)           ModRM:r/m (r)                     NA

Description
Multiply the packed single-precision floating-point values from the first source operand with the corresponding
values in the second source operand, and stores the packed double-precision floating-point results in the destina-
tion operand.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Bits (MAX_VL-1:256) of the
corresponding destination ZMM register are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the destination YMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.





Operation
VMULPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC1[i+31:i] * SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC1[i+31:i] * SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                            ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMULPS (VEX.256 encoded version)
DEST[31:0] <-SRC1[31:0] * SRC2[31:0]
DEST[63:32] <-SRC1[63:32] * SRC2[63:32]
DEST[95:64] <-SRC1[95:64] * SRC2[95:64]
DEST[127:96] <-SRC1[127:96] * SRC2[127:96]
DEST[159:128] <-SRC1[159:128] * SRC2[159:128]
DEST[191:160]<-SRC1[191:160] * SRC2[191:160]
DEST[223:192] <-SRC1[223:192] * SRC2[223:192]
DEST[255:224] <-SRC1[255:224] * SRC2[255:224].
DEST[MAX_VL-1:256] <-0;

VMULPS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0] * SRC2[31:0]
DEST[63:32] <-SRC1[63:32] * SRC2[63:32]
DEST[95:64] <-SRC1[95:64] * SRC2[95:64]
DEST[127:96] <-SRC1[127:96] * SRC2[127:96]
DEST[MAX_VL-1:128] <-0

MULPS (128-bit Legacy SSE version)
DEST[31:0] <-SRC1[31:0] * SRC2[31:0]
DEST[63:32] <-SRC1[63:32] * SRC2[63:32]
DEST[95:64] <-SRC1[95:64] * SRC2[95:64]
DEST[127:96] <-SRC1[127:96] * SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)




Intel C/C++ Compiler Intrinsic Equivalent
VMULPS __m512 _mm512_mul_ps( __m512 a, __m512 b);
VMULPS __m512 _mm512_mask_mul_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMULPS __m512 _mm512_maskz_mul_ps(__mmask16 k, __m512 a, __m512 b);
VMULPS __m512 _mm512_mul_round_ps( __m512 a, __m512 b, int);
VMULPS __m512 _mm512_mask_mul_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMULPS __m512 _mm512_maskz_mul_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VMULPS __m256 _mm256_mask_mul_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMULPS __m256 _mm256_maskz_mul_ps(__mmask8 k, __m256 a, __m256 b);
VMULPS __m128 _mm_mask_mul_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULPS __m128 _mm_maskz_mul_ps(__mmask8 k, __m128 a, __m128 b);
VMULPS __m256 _mm256_mul_ps (__m256 a, __m256 b);
MULPS __m128 _mm_mul_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MULSD
description:
MULSD-Multiply Scalar Double-Precision Floating-Point Value
 Opcode/                                Op /    64/32       CPUID     Description
 Instruction                            En      bit Mode    Feature
                                                Support     Flag
 F2 0F 59 /r                            RM      V/V         SSE2      Multiply the low double-precision floating-point value in
 MULSD xmm1,xmm2/m64                                                  xmm2/m64 by low double-precision floating-point
                                                                      value in xmm1.
 VEX.NDS.128.F2.0F.WIG 59 /r            RVM     V/V         AVX       Multiply the low double-precision floating-point value in
 VMULSD xmm1,xmm2, xmm3/m64                                           xmm3/m64 by low double-precision floating-point
                                                                      value in xmm2.
 EVEX.NDS.LIG.F2.0F.W1 59 /r            T1S     V/V         AVX512F   Multiply the low double-precision floating-point value in
 VMULSD xmm1 {k1}{z}, xmm2,                                           xmm3/m64 by low double-precision floating-point
 xmm3/m64 {er}                                                        value in xmm2.



                                               Instruction Operand Encoding
       Op/En              Operand 1                    Operand 2               Operand 3                     Operand 4
        RM             ModRM:reg (r, w)               ModRM:r/m (r)                 NA                           NA
       RVM              ModRM:reg (w)                 VEX.vvvv (r)            ModRM:r/m (r)                      NA
        T1S             ModRM:reg (w)                 EVEX.vvvv (r)           ModRM:r/m (r)                      NA

Description
Multiplies the low double-precision floating-point value in the second source operand by the low double-precision
floating-point value in the first source operand, and stores the double-precision floating-point result in the destina-
tion operand. The second source operand can be an XMM register or a 64-bit memory location. The first source
operand and the destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:64) of the corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The quadword at bits 127:64 of the destination operand is copied from the
same bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMULSD is encoded with VEX.L=0. Encoding VMULSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VMULSD (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC1[63:0] * SRC2[63:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
              FI
    FI;
ENDFOR
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VMULSD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0] * SRC2[63:0]
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

MULSD (128-bit Legacy SSE version)
DEST[63:0] <-DEST[63:0] * SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMULSD __m128d _mm_mask_mul_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMULSD __m128d _mm_maskz_mul_sd( __mmask8 k, __m128d a, __m128d b);
VMULSD __m128d _mm_mul_round_sd( __m128d a, __m128d b, int);
VMULSD __m128d _mm_mask_mul_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMULSD __m128d _mm_maskz_mul_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MULSD __m128d _mm_mul_sd (__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: MULSS
description:
MULSS-Multiply Scalar Single-Precision Floating-Point Values
 Opcode/                              Op /   64/32       CPUID      Description
 Instruction                          En     bit Mode    Feature
                                             Support     Flag
 F3 0F 59 /r                          RM     V/V         SSE        Multiply the low single-precision floating-point value in
 MULSS xmm1,xmm2/m32                                                xmm2/m32 by the low single-precision floating-point
                                                                    value in xmm1.
 VEX.NDS.128.F3.0F.WIG 59 /r          RVM    V/V         AVX        Multiply the low single-precision floating-point value in
 VMULSS xmm1,xmm2, xmm3/m32                                         xmm3/m32 by the low single-precision floating-point
                                                                    value in xmm2.
 EVEX.NDS.LIG.F3.0F.W0 59 /r          T1S    V/V         AVX512F    Multiply the low single-precision floating-point value in
 VMULSS xmm1 {k1}{z}, xmm2,                                         xmm3/m32 by the low single-precision floating-point
 xmm3/m32 {er}                                                      value in xmm2.



                                             Instruction Operand Encoding
       Op/En              Operand 1                 Operand 2                 Operand 3                     Operand 4
        RM             ModRM:reg (r, w)            ModRM:r/m (r)                  NA                            NA
        RVM             ModRM:reg (w)              VEX.vvvv (r)             ModRM:r/m (r)                       NA
        T1S             ModRM:reg (w)              EVEX.vvvv (r)            ModRM:r/m (r)                       NA

Description
Multiplies the low single-precision floating-point value from the second source operand by the low single-precision
floating-point value in the first source operand, and stores the single-precision floating-point result in the destina-
tion operand. The second source operand can be an XMM register or a 32-bit memory location. The first source
operand and the destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. The three
high-order doublewords of the destination operand are copied from the first source operand. Bits (MAX_VL-1:128)
of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMULSS is encoded with VEX.L=0. Encoding VMULSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VMULSS (EVEX encoded version)
IF (EVEX.b = 1) AND SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC1[31:0] * SRC2[31:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
              FI
    FI;
ENDFOR
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VMULSS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0] * SRC2[31:0]
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

MULSS (128-bit Legacy SSE version)
DEST[31:0] <-DEST[31:0] * SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMULSS __m128 _mm_mask_mul_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_maskz_mul_ss( __mmask8 k, __m128 a, __m128 b);
VMULSS __m128 _mm_mul_round_ss( __m128 a, __m128 b, int);
VMULSS __m128 _mm_mask_mul_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMULSS __m128 _mm_maskz_mul_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MULSS __m128 _mm_mul_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
Underflow, Overflow, Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: MULX
description:
MULX - Unsigned Multiply Without Affecting Flags
 Opcode/                         Op/    64/32    CPUID     Description
 Instruction                     En     -bit     Feature
                                        Mode     Flag
 VEX.NDD.LZ.F2.0F38.W0 F6 /r     RVM    V/V      BMI2      Unsigned multiply of r/m32 with EDX without affecting arithmetic
 MULX r32a, r32b, r/m32                                    flags.
 VEX.NDD.LZ.F2.0F38.W1 F6 /r     RVM    V/N.E.   BMI2      Unsigned multiply of r/m64 with RDX without affecting arithmetic
 MULX r64a, r64b, r/m64                                    flags.



                                             Instruction Operand Encoding
  Op/En           Operand 1                  Operand 2                    Operand 3                       Operand 4
                                                                                                RDX/EDX is implied 64/32 bits
   RVM           ModRM:reg (w)              VEX.vvvv (w)                 ModRM:r/m (r)
                                                                                                           source


Description
Performs an unsigned multiplication of the implicit source operand (EDX/RDX) and the specified source operand
(the third operand) and stores the low half of the result in the second destination (second operand), the high half
of the result in the first destination operand (first operand), without reading or writing the arithmetic flags. This
enables efficient programming where the software can interleave add with carry operations and multiplications.
If the first and second operand are identical, it will contain the high half of the multiplication result.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation
// DEST1: ModRM:reg
// DEST2: VEX.vvvv
IF (OperandSize = 32)
    SRC1 <- EDX;
    DEST2 <- (SRC1*SRC2)[31:0];
    DEST1 <- (SRC1*SRC2)[63:32];
ELSE IF (OperandSize = 64)
    SRC1 <- RDX;
         DEST2 <- (SRC1*SRC2)[63:0];
         DEST1 <- (SRC1*SRC2)[127:64];
FI

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language when possible.
unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);
unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64 * hi);

SIMD Floating-Point Exceptions
None





Other Exceptions
See Section 2.5.1, "Exception Conditions for VEX-Encoded GPR Instructions", Table 2-29; additionally
#UD                      If VEX.W = 1.






platform: x86_64
mnem: MWAIT
description:
MWAIT-Monitor Wait
 Opcode                Instruction              Op/   64-Bit     Compat/ Description
                                                En    Mode       Leg Mode
 0F 01 C9              MWAIT                    NP    Valid      Valid      A hint that allow the processor to stop
                                                                            instruction execution and enter an
                                                                            implementation-dependent optimized state
                                                                            until occurrence of a class of events.



                                           Instruction Operand Encoding
   Op/En           Operand 1                 Operand 2                   Operand 3                  Operand 4
    NP                NA                        NA                          NA                         NA


Description
MWAIT instruction provides hints to allow the processor to enter an implementation-dependent optimized state.
There are two principal targeted usages: address-range monitor and advanced power management. Both usages
of MWAIT require the use of the MONITOR instruction.
CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,
MWAIT may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode
exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE
MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-
tion.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
ECX specifies optional extensions for the MWAIT instruction. EAX may contain hints such as the preferred optimized
state the processor should enter. The first processors to implement MWAIT supported only the zero value for EAX
and ECX. Later processors allowed setting ECX[0] to enable masked interrupts as break events for MWAIT (see
below). Software can use the CPUID instruction to determine the extensions and hints supported by the processor.

MWAIT for Address Range Monitoring
For address-range monitoring, the MWAIT instruction operates with the MONITOR instruction. The two instructions
allow the definition of an address at which to wait (MONITOR) and a implementation-dependent-optimized opera-
tion to commence at the wait address (MWAIT). The execution of MWAIT is a hint to the processor that it can enter
an implementation-dependent-optimized state while waiting for an event or a store operation to the address range
armed by MONITOR.
The following cause the processor to exit the implementation-dependent-optimized state: a store to the address
range armed by the MONITOR instruction, an NMI or SMI, a debug exception, a machine check exception, the
BINIT# signal, the INIT# signal, and the RESET# signal. Other implementation-dependent events may also cause
the processor to exit the implementation-dependent-optimized state.
In addition, an external interrupt causes the processor to exit the implementation-dependent-optimized state
either (1) if the interrupt would be delivered to software (e.g., as it would be if HLT had been executed instead of
MWAIT); or (2) if ECX[0] = 1. Software can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1.
(Implementation-specific conditions may result in an interrupt causing the processor to exit the implementation-
dependent-optimized state even if interrupts are masked and ECX[0] = 0.)
Following exit from the implementation-dependent-optimized state, control passes to the instruction following the
MWAIT instruction. A pending interrupt that is not masked (including an NMI or an SMI) may be delivered before
execution of that instruction. Unlike the HLT instruction, the MWAIT instruction does not support a restart at the
MWAIT instruction following the handling of an SMI.
If the preceding MONITOR instruction did not successfully arm an address range or if the MONITOR instruction has
not been executed prior to executing MWAIT, then the processor will not enter the implementation-dependent-opti-
mized state. Execution will resume at the instruction following the MWAIT.





MWAIT for Power Management
MWAIT accepts a hint and optional extension to the processor that it can enter a specified target C state while
waiting for an event or a store operation to the address range armed by MONITOR. Support for MWAIT extensions
for power management is indicated by CPUID.05H:ECX[bit 0] reporting 1.
EAX and ECX are used to communicate the additional information to the MWAIT instruction, such as the kind of
optimized state the processor should enter. ECX specifies optional extensions for the MWAIT instruction. EAX may
contain hints such as the preferred optimized state the processor should enter. Implementation-specific conditions
may cause a processor to ignore the hint and enter a different optimized state. Future processor implementations
may implement several optimized "waiting" states and will select among those states based on the hint argument.
Table 4-10 describes the meaning of ECX and EAX registers for MWAIT extensions.


                                         Table 4-10. MWAIT Extension Register (ECX)
         Bits                                                             Description
 0                     Treat interrupts as break events even if masked (e.g., even if EFLAGS.IF=0). May be set only if
                       CPUID.05H:ECX[bit 1] = 1.
 31: 1                 Reserved



                                           Table 4-11. MWAIT Hints Register (EAX)
         Bits                                                             Description
 3:0                   Sub C-state within a C-state, indicated by bits [7:4]
 7:4                   Target C-state*
                       Value of 0 means C1; 1 means C2 and so on
                       Value of 01111B means C0


                       Note: Target C states for MWAIT extensions are processor-specific C-states, not ACPI C-states
 31: 8                 Reserved

Note that if MWAIT is used to enter any of the C-states that are numerically higher than C1, a store to the address
range armed by the MONITOR instruction will cause the processor to exit MWAIT only if the store was originated by
other processor agents. A store from non-processor agent might not cause the processor to exit MWAIT in such
cases.
For additional details of MWAIT extensions, see Chapter 14, "Power and Thermal Management," of Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.

Operation
(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension
MWAIT EAX, ECX *)
{
WHILE ( ("Monitor Hardware is in armed state")) {
    implementation_dependent_optimized_state(EAX, ECX); }
Set the state of Monitor Hardware as triggered;
}

Intel C/C++ Compiler Intrinsic Equivalent
MWAIT:          void _mm_mwait(unsigned extensions, unsigned hints)





Example
MONITOR/MWAIT instruction pair must be coded in the same loop because execution of the MWAIT instruction will
trigger the monitor hardware. It is not a proper usage to execute MONITOR once and then execute MWAIT in a
loop. Setting up MONITOR without executing MWAIT has no adverse effects.
Typically the MONITOR/MWAIT pair is used in a sequence, such as:

EAX = Logical Address(Trigger)
ECX = 0 (*Hints *)
EDX = 0 (* Hints *)

IF ( !trigger_store_happened) {
     MONITOR EAX, ECX, EDX
     IF ( !trigger_store_happened ) {
            MWAIT EAX, ECX
     }
}
The above code sequence makes sure that a triggering store does not happen between the first check of the trigger
and the execution of the monitor instruction. Without the second check that triggering store would go un-noticed.
Typical usage of MONITOR and MWAIT would have the above code sequence within a loop.

Numeric Exceptions
None

Protected Mode Exceptions
#GP(0)                   If ECX[31:1] != 0.
                         If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD                      If CPUID.01H:ECX.MONITOR[bit 3] = 0.
                         If current privilege level is not 0.

Real Address Mode Exceptions
#GP                      If ECX[31:1] != 0.
                         If ECX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD                      If CPUID.01H:ECX.MONITOR[bit 3] = 0.

Virtual 8086 Mode Exceptions
#UD                      The MWAIT instruction is not recognized in virtual-8086 mode (even if
                         CPUID.01H:ECX.MONITOR[bit 3] = 1).

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                   If RCX[63:1] != 0.
                         If RCX[0] = 1 and CPUID.05H:ECX[bit 1] = 0.
#UD                      If the current privilege level is not 0.
                         If CPUID.01H:ECX.MONITOR[bit 3] = 0.






platform: x86_64
mnem: NEG
description:
NEG-Two's Complement Negation
 Opcode                   Instruction                   Op/   64-Bit       Compat/ Description
                                                        En    Mode         Leg Mode
 F6 /3                    NEG r/m8                      M     Valid        Valid       Two's complement negate r/m8.
 REX + F6 /3              NEG r/m8*                     M     Valid        N.E.        Two's complement negate r/m8.
 F7 /3                    NEG r/m16                     M     Valid        Valid       Two's complement negate r/m16.
 F7 /3                    NEG r/m32                     M     Valid        Valid       Two's complement negate r/m32.
 REX.W + F7 /3            NEG r/m64                     M     Valid        N.E.        Two's complement negate r/m64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
  Op/En              Operand 1                      Operand 2                      Operand 3                      Operand 4
     M            ModRM:r/m (r, w)                      NA                             NA                             NA


Description
Replaces the value of operand (the destination operand) with its two's complement. (This operation is equivalent
to subtracting the operand from 0.) The destination operand is located in a general-purpose register or a memory
location.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.

Operation
IF DEST = 0
    THEN CF <- 0;
    ELSE CF <- 1;
FI;
DEST <- [- (DEST)]

Flags Affected
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The OF, SF, ZF, AF, and PF flags are set
according to the result.

Protected Mode Exceptions
#GP(0)                  If the destination is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.





Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     For a page fault.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: NOP
description:
NOP-No Operation
 Opcode                  Instruction                 Op/     64-Bit   Compat/ Description
                                                     En      Mode     Leg Mode
 90                      NOP                         NP      Valid    Valid       One byte no-operation instruction.
 0F 1F /0                NOP r/m16                   M       Valid    Valid       Multi-byte no-operation instruction.
 0F 1F /0                NOP r/m32                   M       Valid    Valid       Multi-byte no-operation instruction.



                                             Instruction Operand Encoding
     Op/En          Operand 1                    Operand 2                    Operand 3                     Operand 4
      NP                NA                           NA                          NA                             NA
       M           ModRM:r/m (r)                     NA                          NA                             NA


Description
This instruction performs no operation. It is a one-byte or multi-byte NOP that takes up space in the instruction
stream but does not impact machine context, except for the EIP register.
The multi-byte form of NOP is available on processors with model encoding:
.     CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B
The multi-byte NOP instruction does not alter the content of a register and will not issue a memory operation. The
instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode
exception on processors that do not support the multi-byte NOP instruction.
The memory operand form of the instruction allows software to create a byte sequence of "no operation" as one
instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and
64-bit mode) are:


                         Table 4-12. Recommended Multi-Byte Sequence of NOP Instruction
    Length           Assembly                                                         Byte Sequence
    2 bytes          66 NOP                                                           66 90H
    3 bytes          NOP DWORD ptr [EAX]                                              0F 1F 00H
    4 bytes          NOP DWORD ptr [EAX + 00H]                                        0F 1F 40 00H
    5 bytes          NOP DWORD ptr [EAX + EAX*1 + 00H]                                0F 1F 44 00 00H
    6 bytes          66 NOP DWORD ptr [EAX + EAX*1 + 00H]                             66 0F 1F 44 00 00H
    7 bytes          NOP DWORD ptr [EAX + 00000000H]                                  0F 1F 80 00 00 00 00H
    8 bytes          NOP DWORD ptr [EAX + EAX*1 + 00000000H]                          0F 1F 84 00 00 00 00 00H
    9 bytes          66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]                       66 0F 1F 84 00 00 00 00 00H


Flags Affected
None

Exceptions (All Operating Modes)
#UD                    If the LOCK prefix is used.






platform: x86_64
mnem: NOT
description:
NOT-One's Complement Negation
 Opcode                    Instruction                  Op/    64-Bit      Compat/ Description
                                                        En     Mode        Leg Mode
 F6 /2                     NOT r/m8                     M      Valid       Valid        Reverse each bit of r/m8.
 REX + F6 /2               NOT r/m8*                    M      Valid       N.E.         Reverse each bit of r/m8.
 F7 /2                     NOT r/m16                    M      Valid       Valid        Reverse each bit of r/m16.
 F7 /2                     NOT r/m32                    M      Valid       Valid        Reverse each bit of r/m32.
 REX.W + F7 /2             NOT r/m64                    M      Valid       N.E.         Reverse each bit of r/m64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En             Operand 1                     Operand 2                       Operand 3                        Operand 4
      M           ModRM:r/m (r, w)                     NA                             NA                               NA


Description
Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1) on the destination operand and stores
the result in the destination operand location. The destination operand can be a register or a memory location.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.

Operation
DEST <- NOT DEST;

Flags Affected
None

Protected Mode Exceptions
#GP(0)                  If the destination operand points to a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.





Virtual-8086 Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: OR
description:
OR-Logical Inclusive OR
 Opcode                    Instruction                  Op/     64-Bit      Compat/ Description
                                                        En      Mode        Leg Mode
 0C ib                     OR AL, imm8                  I       Valid       Valid       AL OR imm8.
 0D iw                     OR AX, imm16                 I       Valid       Valid       AX OR imm16.
 0D id                     OR EAX, imm32                I       Valid       Valid       EAX OR imm32.
 REX.W + 0D id             OR RAX, imm32                I       Valid       N.E.        RAX OR imm32 (sign-extended).
 80 /1 ib                  OR r/m8, imm8                MI      Valid       Valid       r/m8 OR imm8.
 REX + 80 /1 ib            OR r/m8*, imm8               MI      Valid       N.E.        r/m8 OR imm8.
 81 /1 iw                  OR r/m16, imm16              MI      Valid       Valid        r/m16 OR imm16.
 81 /1 id                  OR r/m32, imm32              MI      Valid       Valid        r/m32 OR imm32.
 REX.W + 81 /1 id          OR r/m64, imm32              MI      Valid       N.E.         r/m64 OR imm32 (sign-extended).
 83 /1 ib                  OR r/m16, imm8               MI      Valid       Valid       r/m16 OR imm8 (sign-extended).
 83 /1 ib                  OR r/m32, imm8               MI      Valid       Valid       r/m32 OR imm8 (sign-extended).
 REX.W + 83 /1 ib          OR r/m64, imm8               MI      Valid       N.E.        r/m64 OR imm8 (sign-extended).
 08 /r                     OR r/m8, r8                  MR      Valid       Valid       r/m8 OR r8.
 REX + 08 /r               OR r/m8*, r8*                MR      Valid       N.E.        r/m8 OR r8.
 09 /r                     OR r/m16, r16                MR      Valid       Valid       r/m16 OR r16.
 09 /r                     OR r/m32, r32                MR      Valid       Valid       r/m32 OR r32.
 REX.W + 09 /r             OR r/m64, r64                MR      Valid       N.E.        r/m64 OR r64.
 0A /r                     OR r8, r/m8                  RM      Valid       Valid       r8 OR r/m8.
 REX + 0A /r               OR r8*, r/m8*                RM      Valid       N.E.        r8 OR r/m8.
 0B /r                     OR r16, r/m16                RM      Valid       Valid       r16 OR r/m16.
 0B /r                     OR r32, r/m32                RM      Valid       Valid       r32 OR r/m32.
 REX.W + 0B /r             OR r64, r/m64                RM      Valid       N.E.        r64 OR r/m64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                    Operand 2                       Operand 3                     Operand 4
     I              AL/AX/EAX/RAX                  imm8/16/32                          NA                             NA
    MI              ModRM:r/m (r, w)               imm8/16/32                          NA                             NA
    MR              ModRM:r/m (r, w)               ModRM:reg (r)                       NA                             NA
    RM              ModRM:reg (r, w)               ModRM:r/m (r)                       NA                             NA


Description
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores
the result in the destination operand location. The source operand can be an immediate, a register, or a memory
location; the destination operand can be a register or a memory location. (However, two memory operands cannot
be used in one instruction.) Each bit of the result of the OR instruction is set to 0 if both corresponding bits of the
first and second operands are 0; otherwise, each bit is set to 1.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.





In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.

Operation
DEST <- DEST OR SRC;

Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.

Protected Mode Exceptions
#GP(0)                    If the destination operand points to a non-writable segment.
                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the
                          current privilege level is 3.
#UD                       If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                       If a memory operand effective address is outside the SS segment limit.
#UD                       If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made.
#UD                       If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#SS(0)                    If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                    If the memory address is in a non-canonical form.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the
                          current privilege level is 3.
#UD                       If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: ORPD
description:
ORPD-Bitwise Logical OR of Packed Double Precision Floating-Point Values
 Opcode/                            Op /      64/32      CPUID           Description
 Instruction                        En        bit Mode   Feature
                                              Support    Flag
 66 0F 56/r                         RM        V/V        SSE2            Return the bitwise logical OR of packed double-precision
 ORPD xmm1, xmm2/m128                                                    floating-point values in xmm1 and xmm2/mem.
 VEX.NDS.128.66.0F 56 /r            RVM       V/V        AVX             Return the bitwise logical OR of packed double-precision
 VORPD xmm1,xmm2, xmm3/m128                                              floating-point values in xmm2 and xmm3/mem.
 VEX.NDS.256.66.0F 56 /r            RVM       V/V        AVX             Return the bitwise logical OR of packed double-precision
 VORPD ymm1, ymm2, ymm3/m256                                             floating-point values in ymm2 and ymm3/mem.
 EVEX.NDS.128.66.0F.W1 56 /r        FV        V/V        AVX512VL        Return the bitwise logical OR of packed double-precision
 VORPD xmm1 {k1}{z}, xmm2,                               AVX512DQ        floating-point values in xmm2 and xmm3/m128/m64bcst
 xmm3/m128/m64bcst                                                       subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 56 /r        FV        V/V        AVX512VL        Return the bitwise logical OR of packed double-precision
 VORPD ymm1 {k1}{z}, ymm2,                               AVX512DQ        floating-point values in ymm2 and ymm3/m256/m64bcst
 ymm3/m256/m64bcst                                                       subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 56 /r        FV        V/V        AVX512DQ        Return the bitwise logical OR of packed double-precision
 VORPD zmm1 {k1}{z}, zmm2,                                               floating-point values in zmm2 and zmm3/m512/m64bcst
 zmm3/m512/m64bcst                                                       subject to writemask k1.



                                              Instruction Operand Encoding
          Op/En               Operand 1                    Operand 2                       Operand 3                 Operand 4
              RM           ModRM:reg (r, w)              ModRM:r/m (r)                         NA                        NA
           RVM              ModRM:reg (w)                 VEX.vvvv (r)                   ModRM:r/m (r)                   NA
              FV            ModRM:reg (w)                EVEX.vvvv (r)                   ModRM:r/m (r)                   NA

Description
Performs a bitwise logical OR of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.





Operation
VORPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1) AND (SRC2 *is memory*)
                  THEN
                       DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[63:0]
                  ELSE
                       DEST[i+63:i] <- SRC1[i+63:i] BITWISE OR SRC2[i+63:i]
             FI;
        ELSE
             IF *merging-masking*                 ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*               ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VORPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[191:128] <- SRC1[191:128] BITWISE OR SRC2[191:128]
DEST[255:192] <- SRC1[255:192] BITWISE OR SRC2[255:192]
DEST[MAX_VL-1:256] <- 0

VORPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[MAX_VL-1:128] <- 0

ORPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]
DEST[127:64] <- DEST[127:64] BITWISE OR SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VORPD __m512d _mm512_or_pd ( __m512d a, __m512d b);
VORPD __m512d _mm512_mask_or_pd ( __m512d s, __mmask8 k, __m512d a, __m512d b);
VORPD __m512d _mm512_maskz_or_pd (__mmask8 k, __m512d a, __m512d b);
VORPD __m256d _mm256_mask_or_pd (__m256d s, ___mmask8 k, __m256d a, __m256d b);
VORPD __m256d _mm256_maskz_or_pd (__mmask8 k, __m256d a, __m256d b);
VORPD __m128d _mm_mask_or_pd ( __m128d s, __mmask8 k, __m128d a, __m128d b);
VORPD __m128d _mm_maskz_or_pd (__mmask8 k, __m128d a, __m128d b);
VORPD __m256d _mm256_or_pd (__m256d a, __m256d b);
ORPD __m128d _mm_or_pd (__m128d a, __m128d b);





SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: ORPS
description:
ORPS-Bitwise Logical OR of Packed Single Precision Floating-Point Values
 Opcode/                                   Op /      64/32        CPUID        Description
 Instruction                               En        bit Mode     Feature
                                                     Support      Flag
 0F 56 /r                                  RM        V/V          SSE          Return the bitwise logical OR of packed single-precision
 ORPS xmm1, xmm2/m128                                                          floating-point values in xmm1 and xmm2/mem.
 VEX.NDS.128.0F 56 /r                      RVM       V/V           AVX         Return the bitwise logical OR of packed single-precision
 VORPS xmm1,xmm2, xmm3/m128                                                    floating-point values in xmm2 and xmm3/mem.
 VEX.NDS.256.0F 56 /r                      RVM       V/V           AVX         Return the bitwise logical OR of packed single-precision
 VORPS ymm1, ymm2, ymm3/m256                                                   floating-point values in ymm2 and ymm3/mem.
 EVEX.NDS.128.0F.W0 56 /r                  FV        V/V          AVX512VL     Return the bitwise logical OR of packed single-precision
 VORPS xmm1 {k1}{z}, xmm2,                                        AVX512DQ     floating-point values in xmm2 and xmm3/m128/m32bcst
 xmm3/m128/m32bcst                                                             subject to writemask k1.
 EVEX.NDS.256.0F.W0 56 /r                  FV        V/V          AVX512VL     Return the bitwise logical OR of packed single-precision
 VORPS ymm1 {k1}{z}, ymm2,                                        AVX512DQ     floating-point values in ymm2 and ymm3/m256/m32bcst
 ymm3/m256/m32bcst                                                             subject to writemask k1.
 EVEX.NDS.512.0F.W0 56 /r                  FV        V/V           AVX512DQ    Return the bitwise logical OR of packed single-precision
 VORPS zmm1 {k1}{z}, zmm2,                                                     floating-point values in zmm2 and zmm3/m512/m32bcst
 zmm3/m512/m32bcst                                                             subject to writemask k1.



                                                      Instruction Operand Encoding
        Op/En                    Operand 1                      Operand 2                 Operand 3                   Operand 4
          RM                 ModRM:reg (r, w)                 ModRM:r/m (r)                   NA                         NA
         RVM                   ModRM:reg (w)                    VEX.vvvv (r)            ModRM:r/m (r)                    NA
          FV                   ModRM:reg (w)                  EVEX.vvvv (r)             ModRM:r/m (r)                    NA

Description
Performs a bitwise logical OR of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.





Operation
VORPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*               ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VORPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[159:128] <- SRC1[159:128] BITWISE OR SRC2[159:128]
DEST[191:160] <- SRC1[191:160] BITWISE OR SRC2[191:160]
DEST[223:192] <- SRC1[223:192] BITWISE OR SRC2[223:192]
DEST[255:224] <- SRC1[255:224] BITWISE OR SRC2[255:224].
DEST[MAX_VL-1:256] <- 0

VORPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[MAX_VL-1:128] <- 0

ORPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VORPS __m512 _mm512_or_ps ( __m512 a, __m512 b);
VORPS __m512 _mm512_mask_or_ps ( __m512 s, __mmask16 k, __m512 a, __m512 b);
VORPS __m512 _mm512_maskz_or_ps (__mmask16 k, __m512 a, __m512 b);
VORPS __m256 _mm256_mask_or_ps (__m256 s, ___mmask8 k, __m256 a, __m256 b);
VORPS __m256 _mm256_maskz_or_ps (__mmask8 k, __m256 a, __m256 b);
VORPS __m128 _mm_mask_or_ps ( __m128 s, __mmask8 k, __m128 a, __m128 b);
VORPS __m128 _mm_maskz_or_ps (__mmask8 k, __m128 a, __m128 b);
VORPS __m256 _mm256_or_ps (__m256 a, __m256 b);
ORPS __m128 _mm_or_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: OUT
description:
OUT-Output to Port
 Opcode*                  Instruction                    Op/   64-Bit   Compat/ Description
                                                         En    Mode     Leg Mode
 E6 ib                    OUT imm8, AL                   I     Valid    Valid       Output byte in AL to I/O port address imm8.
 E7 ib                    OUT imm8, AX                   I     Valid    Valid       Output word in AX to I/O port address imm8.
 E7 ib                    OUT imm8, EAX                  I     Valid    Valid       Output doubleword in EAX to I/O port address
                                                                                    imm8.
 EE                       OUT DX, AL                     NP    Valid    Valid       Output byte in AL to I/O port address in DX.
 EF                       OUT DX, AX                     NP    Valid    Valid       Output word in AX to I/O port address in DX.
 EF                       OUT DX, EAX                    NP    Valid    Valid       Output doubleword in EAX to I/O port address
                                                                                    in DX.
 NOTES:
 * See IA-32 Architecture Compatibility section below.



                                                 Instruction Operand Encoding
  Op/En              Operand 1                     Operand 2                    Operand 3                     Operand 4
      I                imm8                              NA                        NA                            NA
      NP                NA                               NA                        NA                            NA


Description
Copies the value from the second operand (source operand) to the I/O port specified with the destination operand
(first operand). The source operand can be register AL, AX, or EAX, depending on the size of the port being
accessed (8, 16, or 32 bits, respectively); the destination operand can be a byte-immediate or the DX register.
Using a byte immediate allows I/O port addresses 0 to 255 to be accessed; using the DX register as a source
operand allows I/O ports from 0 to 65,535 to be accessed.
The size of the I/O port being accessed is determined by the opcode for an 8-bit I/O port or by the operand-size
attribute of the instruction for a 16- or 32-bit I/O port.
At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits
of the port address will be 0.
This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 18,
"Input/Output," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more infor-
mation on accessing I/O ports in the I/O address space.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility
After executing an OUT instruction, the Pentium processor ensures that the EWBE# pin has been sampled active
before it begins to execute the next instruction. (Note that the instruction can be prefetched if EWBE# is not active,
but it will not be executed until the EWBE# pin is sampled active.) Only the Pentium processor family has the
EWBE# pin.





Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
     THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
         IF (Any I/O Permission Bit for I/O port being accessed = 1)
              THEN (* I/O operation is not allowed *)
                   #GP(0);
              ELSE ( * I/O operation is allowed *)
                   DEST <- SRC; (* Writes to selected I/O port *)
         FI;
     ELSE (Real Mode or Protected Mode with CPL <= IOPL *)
         DEST <- SRC; (* Writes to selected I/O port *)
FI;

Flags Affected
None

Protected Mode Exceptions
#GP(0)                 If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
                       corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
#UD                    If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                    If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                 If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)        If a page fault occurs.
#UD                    If the LOCK prefix is used.

Compatibility Mode Exceptions
Same as protected mode exceptions.

64-Bit Mode Exceptions
Same as protected mode exceptions.






platform: x86_64
mnem: OUTS
description:
OUTS/OUTSB/OUTSW/OUTSD-Output String to Port
 Opcode*                   Instruction                   Op/    64-Bit       Compat/ Description
                                                         En     Mode         Leg Mode
 6E                        OUTS DX, m8                    NP    Valid        Valid        Output byte from memory location specified
                                                                                          in DS:(E)SI or RSI to I/O port specified in DX**.
 6F                        OUTS DX, m16                   NP    Valid        Valid        Output word from memory location specified
                                                                                          in DS:(E)SI or RSI to I/O port specified in DX**.
 6F                        OUTS DX, m32                   NP    Valid        Valid        Output doubleword from memory location
                                                                                          specified in DS:(E)SI or RSI to I/O port specified
                                                                                          in DX**.
 6E                        OUTSB                         NP     Valid        Valid        Output byte from memory location specified
                                                                                          in DS:(E)SI or RSI to I/O port specified in DX**.
 6F                        OUTSW                         NP     Valid        Valid        Output word from memory location specified
                                                                                          in DS:(E)SI or RSI to I/O port specified in DX**.
 6F                        OUTSD                         NP     Valid        Valid        Output doubleword from memory location
                                                                                          specified in DS:(E)SI or RSI to I/O port specified
                                                                                          in DX**.
 NOTES:
 * See IA-32 Architecture Compatibility section below.
 ** In 64-bit mode, only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit mode, only 32-bit (ESI) and 16-bit (SI)
    address sizes are supported.



                                                   Instruction Operand Encoding
  Op/En               Operand 1                       Operand 2                       Operand 3                        Operand 4
      NP                  NA                              NA                              NA                               NA


Description
Copies data from the source operand (second operand) to the I/O port specified with the destination operand (first
operand). The source operand is a memory location, the address of which is read from either the DS:SI, DS:ESI or
the RSI registers (depending on the address-size attribute of the instruction, 16, 32 or 64, respectively). (The DS
segment may be overridden with a segment override prefix.) The destination operand is an I/O port address (from
0 to 65,535) that is read from the DX register. The size of the I/O port being accessed (that is, the size of the source
and destination operands) is determined by the opcode for an 8-bit I/O port or by the operand-size attribute of the
instruction for a 16- or 32-bit I/O port.
At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-
operands" form. The explicit-operands form (specified with the OUTS mnemonic) allows the source and destination
operands to be specified explicitly. Here, the source operand should be a symbol that indicates the size of the I/O
port and the source address, and the destination operand must be DX. This explicit-operands form is provided to
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the
source operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword), but it does
not have to specify the correct location. The location is always specified by the DS:(E)SI or RSI registers, which
must be loaded correctly before the OUTS instruction is executed.
The no-operands form provides "short forms" of the byte, word, and doubleword versions of the OUTS instructions.
Here also DS:(E)SI is assumed to be the source operand and DX is assumed to be the destination operand. The size
of the I/O port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or OUTSD (doubleword).
After the byte, word, or doubleword is transferred from the memory location to the I/O port, the SI/ESI/RSI
register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI register is decremented.)
The SI/ESI/RSI register is incremented or decremented by 1 for byte operations, by 2 for word operations, and by
4 for doubleword operations.




The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix for block input of ECX
bytes, words, or doublewords. See "REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix" in this
chapter for a description of the REP prefix. This instruction is only useful for accessing I/O ports located in the
processor's I/O address space. See Chapter 18, "Input/Output," in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for more information on accessing I/O ports in the I/O address space.
In 64-bit mode, the default operand size is 32 bits; operand size is not promoted by the use of REX.W. In 64-bit
mode, the default address size is 64 bits, and 64-bit address is specified using RSI by default. 32-bit address using
ESI is support using the prefix 67H, but 16-bit address is not supported in 64-bit mode.

IA-32 Architecture Compatibility
After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor ensures that the EWBE#
pin has been sampled active before it begins to execute the next instruction. (Note that the instruction can be
prefetched if EWBE# is not active, but it will not be executed until the EWBE# pin is sampled active.) Only the
Pentium processor family has the EWBE# pin.
For the Pentium 4, Intel Xeon, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or OUTSD
instruction, the processor will not execute the next instruction until the data phase of the transaction is complete.

Operation
IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
     THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
         IF (Any I/O Permission Bit for I/O port being accessed = 1)
              THEN (* I/O operation is not allowed *)
                   #GP(0);
              ELSE (* I/O operation is allowed *)
                   DEST <- SRC; (* Writes to I/O port *)
         FI;
     ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL <= IOPL *)
         DEST <- SRC; (* Writes to I/O port *)
FI;

Byte transfer:
   IF 64-bit mode
        Then
             IF 64-Bit Address Size
                  THEN
                       IF DF = 0
                            THEN RSI <- RSI RSI + 1;
                            ELSE RSI <- RSI or - 1;
                       FI;
                  ELSE (* 32-Bit Address Size *)
                       IF DF = 0
                            THEN      ESI <- ESI + 1;
                            ELSE      ESI <- ESI - 1;
                       FI;
             FI;
        ELSE
             IF DF = 0
                  THEN      (E)SI <- (E)SI + 1;
                  ELSE (E)SI <- (E)SI - 1;
             FI;
   FI;
Word transfer:
   IF 64-bit mode



        Then
            IF 64-Bit Address Size
                 THEN
                      IF DF = 0
                           THEN RSI <- RSI RSI + 2;
                           ELSE RSI <- RSI or - 2;
                      FI;
                 ELSE (* 32-Bit Address Size *)
                      IF DF = 0
                           THEN      ESI <- ESI + 2;
                           ELSE      ESI <- ESI - 2;
                      FI;
            FI;
        ELSE
            IF DF = 0
                 THEN      (E)SI <- (E)SI + 2;
                 ELSE (E)SI <- (E)SI - 2;
            FI;
   FI;
Doubleword transfer:
   IF 64-bit mode
        Then
             IF 64-Bit Address Size
                  THEN
                       IF DF = 0
                            THEN RSI <- RSI RSI + 4;
                            ELSE RSI <- RSI or - 4;
                       FI;
                  ELSE (* 32-Bit Address Size *)
                       IF DF = 0
                            THEN      ESI <- ESI + 4;
                            ELSE      ESI <- ESI - 4;
                       FI;
             FI;
        ELSE
             IF DF = 0
                  THEN      (E)SI <- (E)SI + 4;
                  ELSE (E)SI <- (E)SI - 4;
             FI;
   FI;

Flags Affected
None





Protected Mode Exceptions
#GP(0)                If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
                      corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
                      If a memory operand effective address is outside the limit of the CS, DS, ES, FS, or GS
                      segment.
                      If the segment register contains a NULL segment selector.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                   If a memory operand effective address is outside the SS segment limit.
#UD                   If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                If any of the I/O permission bits in the TSS for the I/O port being accessed is 1.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.
#UD                   If the LOCK prefix is used.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                If the CPL is greater than (has less privilege) the I/O privilege level (IOPL) and any of the
                      corresponding I/O permission bits in TSS for the I/O port being accessed is 1.
                      If the memory address is in a non-canonical form.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: PABSB
description:
PABSB/PABSW/PABSD/PABSQ - Packed Absolute Value
Opcode/                          Op/   64/32 bit   CPUID        Description
Instruction                      En    Mode        Feature
                                       Support     Flag
0F 38 1C /r1                     RM    V/V         SSSE3        Compute the absolute value of bytes in
PABSB mm1, mm2/m64                                              mm2/m64 and store UNSIGNED result in mm1.

66 0F 38 1C /r                   RM    V/V         SSSE3        Compute the absolute value of bytes in
PABSB xmm1, xmm2/m128                                           xmm2/m128 and store UNSIGNED result in
                                                                xmm1.
0F 38 1D /r1                     RM    V/V         SSSE3        Compute the absolute value of 16-bit integers
PABSW mm1, mm2/m64                                              in mm2/m64 and store UNSIGNED result in
                                                                mm1.
66 0F 38 1D /r                   RM    V/V         SSSE3        Compute the absolute value of 16-bit integers
PABSW xmm1, xmm2/m128                                           in xmm2/m128 and store UNSIGNED result in
                                                                xmm1.
0F 38 1E /r1                     RM    V/V         SSSE3        Compute the absolute value of 32-bit integers
PABSD mm1, mm2/m64                                              in mm2/m64 and store UNSIGNED result in
                                                                mm1.
66 0F 38 1E /r                   RM    V/V         SSSE3        Compute the absolute value of 32-bit integers
PABSD xmm1, xmm2/m128                                           in xmm2/m128 and store UNSIGNED result in
                                                                xmm1.
VEX.128.66.0F38.WIG 1C /r        RM    V/V         AVX          Compute the absolute value of bytes in
VPABSB xmm1, xmm2/m128                                          xmm2/m128 and store UNSIGNED result in
                                                                xmm1.
VEX.128.66.0F38.WIG 1D /r        RM    V/V         AVX          Compute the absolute value of 16- bit
VPABSW xmm1, xmm2/m128                                          integers in xmm2/m128 and store UNSIGNED
                                                                result in xmm1.
VEX.128.66.0F38.WIG 1E /r        RM    V/V         AVX          Compute the absolute value of 32- bit
VPABSD xmm1, xmm2/m128                                          integers in xmm2/m128 and store UNSIGNED
                                                                result in xmm1.
VEX.256.66.0F38.WIG 1C /r        RM    V/V         AVX2         Compute the absolute value of bytes in
VPABSB ymm1, ymm2/m256                                          ymm2/m256 and store UNSIGNED result in
                                                                ymm1.
VEX.256.66.0F38.WIG 1D /r        RM    V/V         AVX2         Compute the absolute value of 16-bit integers
VPABSW ymm1, ymm2/m256                                          in ymm2/m256 and store UNSIGNED result in
                                                                ymm1.
VEX.256.66.0F38.WIG 1E /r        RM    V/V         AVX2         Compute the absolute value of 32-bit integers
VPABSD ymm1, ymm2/m256                                          in ymm2/m256 and store UNSIGNED result in
                                                                ymm1.
EVEX.128.66.0F38.WIG 1C /r       FVM V/V           AVX512VL Compute the absolute value of bytes in
VPABSB xmm1 {k1}{z}, xmm2/m128                     AVX512BW xmm2/m128 and store UNSIGNED result in
                                                            xmm1 using writemask k1.
EVEX.256.66.0F38.WIG 1C /r       FVM V/V           AVX512VL Compute the absolute value of bytes in
VPABSB ymm1 {k1}{z}, ymm2/m256                     AVX512BW ymm2/m256 and store UNSIGNED result in
                                                            ymm1 using writemask k1.
EVEX.512.66.0F38.WIG 1C /r       FVM V/V           AVX512BW Compute the absolute value of bytes in
VPABSB zmm1 {k1}{z}, zmm2/m512                              zmm2/m512 and store UNSIGNED result in
                                                            zmm1 using writemask k1.
EVEX.128.66.0F38.WIG 1D /r       FVM V/V           AVX512VL Compute the absolute value of 16-bit integers
VPABSW xmm1 {k1}{z}, xmm2/m128                     AVX512BW in xmm2/m128 and store UNSIGNED result in
                                                            xmm1 using writemask k1.




EVEX.256.66.0F38.WIG 1D /r                           FVM V/V          AVX512VL Compute the absolute value of 16-bit integers
VPABSW ymm1 {k1}{z}, ymm2/m256                                        AVX512BW in ymm2/m256 and store UNSIGNED result in
                                                                               ymm1 using writemask k1.
EVEX.512.66.0F38.WIG 1D /r                           FVM V/V          AVX512BW Compute the absolute value of 16-bit integers
VPABSW zmm1 {k1}{z}, zmm2/m512                                                 in zmm2/m512 and store UNSIGNED result in
                                                                               zmm1 using writemask k1.
EVEX.128.66.0F38.W0 1E /r                            FV    V/V        AVX512VL Compute the absolute value of 32-bit integers
VPABSD xmm1 {k1}{z}, xmm2/m128/m32bcst                                AVX512F  in xmm2/m128/m32bcst and store UNSIGNED
                                                                               result in xmm1 using writemask k1.
EVEX.256.66.0F38.W0 1E /r                            FV    V/V        AVX512VL Compute the absolute value of 32-bit integers
VPABSD ymm1 {k1}{z}, ymm2/m256/m32bcst                                AVX512F  in ymm2/m256/m32bcst and store UNSIGNED
                                                                               result in ymm1 using writemask k1.
VPABSD zmm1 {k1}{z}, zmm2/m512/m32bcst               FV    V/V        AVX512F      Compute the absolute value of 32-bit integers
                                                                                   in zmm2/m512/m32bcst and store UNSIGNED
                                                                                   result in zmm1 using writemask k1.
EVEX.128.66.0F38.W1 1F /r                            FV    V/V        AVX512VL Compute the absolute value of 64-bit integers
VPABSQ xmm1 {k1}{z}, xmm2/m128/m64bcst                                AVX512F  in xmm2/m128/m64bcst and store UNSIGNED
                                                                               result in xmm1 using writemask k1.
EVEX.256.66.0F38.W1 1F /r                            FV    V/V        AVX512VL Compute the absolute value of 64-bit integers
VPABSQ ymm1 {k1}{z}, ymm2/m256/m64bcst                                AVX512F  in ymm2/m256/m64bcst and store UNSIGNED
                                                                               result in ymm1 using writemask k1.
EVEX.512.66.0F38.W1 1F /r                            FV    V/V        AVX512F      Compute the absolute value of 64-bit integers
VPABSQ zmm1 {k1}{z}, zmm2/m512/m64bcst                                             in zmm2/m512/m64bcst and store UNSIGNED
                                                                                   result in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En             Operand 1                     Operand 2                   Operand 3                    Operand 4
     RM            ModRM:reg (w)                  ModRM:r/m (r)                    NA                           NA
    FVM            ModRM:reg (w)                  ModRM:r/m (r)                    NA                           NA
     FV            ModRM:reg (w)                  ModRM:r/m (r)                    NA                           NA


Description
PABSB/W/D computes the absolute value of each data element of the source operand (the second operand) and
stores the UNSIGNED results in the destination operand (the first operand). PABSB operates on signed bytes,
PABSW operates on signed 16-bit words, and PABSD operates on signed 32-bit integers.
EVEX encoded VPABSD/Q: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location,
or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
EVEX encoded VPABSB/W: The source operand is a ZMM/YMM/XMM register, or a 512/256/128-bit memory loca-
tion. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded versions: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding register destination are zeroed.
VEX.128 encoded versions: The source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding register destination are zeroed.





128-bit Legacy SSE version: The source operand can be an XMM register or an 128-bit memory location. The desti-
nation is an XMM register. The upper bits (VL_MAX-1:128) of the corresponding register destination are unmodi-
fied.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation
PABSB with 128 bit operands:
  Unsigned DEST[7:0] <-ABS(SRC[7: 0])
  Repeat operation for 2nd through 15th bytes
  Unsigned DEST[127:120] <-ABS(SRC[127:120])

VPABSB with 128 bit operands:
  Unsigned DEST[7:0] <-ABS(SRC[7: 0])
  Repeat operation for 2nd through 15th bytes
  Unsigned DEST[127:120]<-ABS(SRC[127:120])

VPABSB with 256 bit operands:
  Unsigned DEST[7:0]<-ABS(SRC[7: 0])
  Repeat operation for 2nd through 31st bytes
  Unsigned DEST[255:248]<-ABS(SRC[255:248])

VPABSB (EVEX encoded versions)
  (KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN
             Unsigned DEST[i+7:i] <- ABS(SRC[i+7:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PABSW with 128 bit operands:
  Unsigned DEST[15:0]<-ABS(SRC[15:0])
  Repeat operation for 2nd through 7th 16-bit words
  Unsigned DEST[127:112]<-ABS(SRC[127:112])

VPABSW with 128 bit operands:
  Unsigned DEST[15:0] <-ABS(SRC[15:0])
  Repeat operation for 2nd through 7th 16-bit words
  Unsigned DEST[127:112]<-ABS(SRC[127:112])

VPABSW with 256 bit operands:
  Unsigned DEST[15:0]<-ABS(SRC[15:0])
  Repeat operation for 2nd through 15th 16-bit words
  Unsigned DEST[255:240] <-ABS(SRC[255:240])




VPABSW (EVEX encoded versions)
  (KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN
             Unsigned DEST[i+15:i] <- ABS(SRC[i+15:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PABSD with 128 bit operands:
  Unsigned DEST[31:0]<-ABS(SRC[31:0])
  Repeat operation for 2nd through 3rd 32-bit double words
  Unsigned DEST[127:96]<-ABS(SRC[127:96])

VPABSD with 128 bit operands:
  Unsigned DEST[31:0]<-ABS(SRC[31:0])
  Repeat operation for 2nd through 3rd 32-bit double words
  Unsigned DEST[127:96]<-ABS(SRC[127:96])

VPABSD with 256 bit operands:
  Unsigned DEST[31:0] <-ABS(SRC[31:0])
  Repeat operation for 2nd through 7th 32-bit double words
  Unsigned DEST[255:224] <-ABS(SRC[255:224])

VPABSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         Unsigned DEST[i+31:i] <- ABS(SRC[31:0])
                    ELSE
                         Unsigned DEST[i+31:i] <- ABS(SRC[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0



VPABSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN
                         Unsigned DEST[i+63:i] <- ABS(SRC[63:0])
                    ELSE
                         Unsigned DEST[i+63:i] <- ABS(SRC[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPABSB__m512i _mm512_abs_epi8 ( __m512i a)
VPABSW__m512i _mm512_abs_epi16 ( __m512i a)
VPABSB__m512i _mm512_mask_abs_epi8 ( __m512i s, __mmask64 m, __m512i a)
VPABSW__m512i _mm512_mask_abs_epi16 ( __m512i s, __mmask32 m, __m512i a)
VPABSB__m512i _mm512_maskz_abs_epi8 (__mmask64 m, __m512i a)
VPABSW__m512i _mm512_maskz_abs_epi16 (__mmask32 m, __m512i a)
VPABSB__m256i _mm256_mask_abs_epi8 (__m256i s, __mmask32 m, __m256i a)
VPABSW__m256i _mm256_mask_abs_epi16 (__m256i s, __mmask16 m, __m256i a)
VPABSB__m256i _mm256_maskz_abs_epi8 (__mmask32 m, __m256i a)
VPABSW__m256i _mm256_maskz_abs_epi16 (__mmask16 m, __m256i a)
VPABSB__m128i _mm_mask_abs_epi8 (__m128i s, __mmask16 m, __m128i a)
VPABSW__m128i _mm_mask_abs_epi16 (__m128i s, __mmask8 m, __m128i a)
VPABSB__m128i _mm_maskz_abs_epi8 (__mmask16 m, __m128i a)
VPABSW__m128i _mm_maskz_abs_epi16 (__mmask8 m, __m128i a)
VPABSD __m256i _mm256_mask_abs_epi32(__m256i s, __mmask8 k, __m256i a);
VPABSD __m256i _mm256_maskz_abs_epi32( __mmask8 k, __m256i a);
VPABSD __m128i _mm_mask_abs_epi32(__m128i s, __mmask8 k, __m128i a);
VPABSD __m128i _mm_maskz_abs_epi32( __mmask8 k, __m128i a);
VPABSD __m512i _mm512_abs_epi32( __m512i a);
VPABSD __m512i _mm512_mask_abs_epi32(__m512i s, __mmask16 k, __m512i a);
VPABSD __m512i _mm512_maskz_abs_epi32( __mmask16 k, __m512i a);
VPABSQ __m512i _mm512_abs_epi64( __m512i a);
VPABSQ __m512i _mm512_mask_abs_epi64(__m512i s, __mmask8 k, __m512i a);
VPABSQ __m512i _mm512_maskz_abs_epi64( __mmask8 k, __m512i a);
VPABSQ __m256i _mm256_mask_abs_epi64(__m256i s, __mmask8 k, __m256i a);
VPABSQ __m256i _mm256_maskz_abs_epi64( __mmask8 k, __m256i a);
VPABSQ __m128i _mm_mask_abs_epi64(__m128i s, __mmask8 k, __m128i a);
VPABSQ __m128i _mm_maskz_abs_epi64( __mmask8 k, __m128i a);
PABSB __m128i _mm_abs_epi8 (__m128i a)
VPABSB __m128i _mm_abs_epi8 (__m128i a)



VPABSB __m256i _mm256_abs_epi8 (__m256i a)
PABSW __m128i _mm_abs_epi16 (__m128i a)
VPABSW __m128i _mm_abs_epi16 (__m128i a)
VPABSW __m256i _mm256_abs_epi16 (__m256i a)
PABSD __m128i _mm_abs_epi32 (__m128i a)
VPABSD __m128i _mm_abs_epi32 (__m128i a)
VPABSD __m256i _mm256_abs_epi32 (__m256i a)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPABSD/Q, see Exceptions Type E4.
EVEX-encoded VPABSB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PACKSSWB
description:
PACKSSWB/PACKSSDW-Pack with Signed Saturation
Opcode/                                   Op/   64/32 bit   CPUID        Description
Instruction                               En    Mode        Feature Flag
                                                Support
0F 63 /r1                                 RM    V/V         MMX          Converts 4 packed signed word integers from
PACKSSWB mm1, mm2/m64                                                    mm1 and from mm2/m64 into 8 packed
                                                                         signed byte integers in mm1 using signed
                                                                         saturation.
66 0F 63 /r                               RM    V/V         SSE2         Converts 8 packed signed word integers from
PACKSSWB xmm1, xmm2/m128                                                 xmm1 and from xxm2/m128 into 16 packed
                                                                         signed byte integers in xxm1 using signed
                                                                         saturation.
0F 6B /r1                                 RM    V/V         MMX          Converts 2 packed signed doubleword
PACKSSDW mm1, mm2/m64                                                    integers from mm1 and from mm2/m64 into 4
                                                                         packed signed word integers in mm1 using
                                                                         signed saturation.
66 0F 6B /r                               RM    V/V         SSE2         Converts 4 packed signed doubleword
PACKSSDW xmm1, xmm2/m128                                                 integers from xmm1 and from xxm2/m128
                                                                         into 8 packed signed word integers in xxm1
                                                                         using signed saturation.
VEX.NDS.128.66.0F.WIG 63 /r               RVM V/V           AVX          Converts 8 packed signed word integers from
VPACKSSWB xmm1,xmm2, xmm3/m128                                           xmm2 and from xmm3/m128 into 16 packed
                                                                         signed byte integers in xmm1 using signed
                                                                         saturation.
VEX.NDS.128.66.0F.WIG 6B /r               RVM V/V           AVX          Converts 4 packed signed doubleword
VPACKSSDW xmm1,xmm2, xmm3/m128                                           integers from xmm2 and from xmm3/m128
                                                                         into 8 packed signed word integers in xmm1
                                                                         using signed saturation.
VEX.NDS.256.66.0F.WIG 63 /r               RVM V/V           AVX2         Converts 16 packed signed word integers
VPACKSSWB ymm1, ymm2, ymm3/m256                                          from ymm2 and from ymm3/m256 into 32
                                                                         packed signed byte integers in ymm1 using
                                                                         signed saturation.
VEX.NDS.256.66.0F.WIG 6B /r               RVM V/V           AVX2         Converts 8 packed signed doubleword
VPACKSSDW ymm1, ymm2, ymm3/m256                                          integers from ymm2 and from ymm3/m256
                                                                         into 16 packed signed word integers in
                                                                         ymm1using signed saturation.
EVEX.NDS.128.66.0F.WIG 63 /r              FVM V/V           AVX512VL     Converts packed signed word integers from
VPACKSSWB xmm1 {k1}{z}, xmm2, xmm3/m128                     AVX512BW     xmm2 and from xmm3/m128 into packed
                                                                         signed byte integers in xmm1 using signed
                                                                         saturation under writemask k1.
EVEX.NDS.256.66.0F.WIG 63 /r              FVM V/V           AVX512VL     Converts packed signed word integers from
VPACKSSWB ymm1 {k1}{z}, ymm2, ymm3/m256                     AVX512BW     ymm2 and from ymm3/m256 into packed
                                                                         signed byte integers in ymm1 using signed
                                                                         saturation under writemask k1.
EVEX.NDS.512.66.0F.WIG 63 /r              FVM V/V           AVX512BW     Converts packed signed word integers from
VPACKSSWB zmm1 {k1}{z}, zmm2, zmm3/m512                                  zmm2 and from zmm3/m512 into packed
                                                                         signed byte integers in zmm1 using signed
                                                                         saturation under writemask k1.
EVEX.NDS.128.66.0F.W0 6B /r               FV    V/V         AVX512VL     Converts packed signed doubleword integers
VPACKSSDW xmm1 {k1}{z}, xmm2,                               AVX512BW     from xmm2 and from xmm3/m128/m32bcst
xmm3/m128/m32bcst                                                        into packed signed word integers in xmm1
                                                                         using signed saturation under writemask k1.





EVEX.NDS.256.66.0F.W0 6B /r                             FV            V/V         AVX512VL           Converts packed signed doubleword integers
VPACKSSDW ymm1 {k1}{z}, ymm2,                                                     AVX512BW           from ymm2 and from ymm3/m256/m32bcst
ymm3/m256/m32bcst                                                                                    into packed signed word integers in ymm1
                                                                                                     using signed saturation under writemask k1.
EVEX.NDS.512.66.0F.W0 6B /r                             FV            V/V         AVX512BW           Converts packed signed doubleword integers
VPACKSSDW zmm1 {k1}{z}, zmm2,                                                                        from zmm2 and from zmm3/m512/m32bcst
zmm3/m512/m32bcst                                                                                    into packed signed word integers in zmm1
                                                                                                     using signed saturation under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                    Instruction Operand Encoding
  Op/En             Operand 1                        Operand 2                              Operand 3                        Operand 4
    RM           ModRM:reg (r, w)               ModRM:r/m (r)                                   NA                              NA
   RVM            ModRM:reg (w)                     VEX.vvvv (r)                           ModRM:r/m (r)                        NA
   FVM            ModRM:reg (w)                     EVEX.vvvv (r)                          ModRM:r/m (r)                        NA
    FV            ModRM:reg (w)                     EVEX.vvvv (r)                          ModRM:r/m (r)                        NA


Description
Converts packed signed word integers into packed signed byte integers (PACKSSWB) or converts packed signed
doubleword integers into packed signed word integers (PACKSSDW), using saturation to handle overflow condi-
tions. See Figure 4-6 for an example of the packing operation.


                                             64-Bit SRC                                64-Bit DEST
                                                D            C                         B        A



                                                                 D'     C'   B'   A'
                                                                      64-Bit DEST

                      Figure 4-6. Operation of the PACKSSDW Instruction Using 64-bit Operands

PACKSSWB converts packed signed word integers in the first and second source operands into packed signed byte
integers using signed saturation to handle overflow conditions beyond the range of signed byte integers. If the
signed doubleword value is beyond the range of an unsigned word (i.e. greater than 7FH or less than 80H), the
saturated signed byte integer value of 7FH or 80H, respectively, is stored in the destination. PACKSSDW converts
packed signed doubleword integers in the first and second source operands into packed signed word integers using
signed saturation to handle overflow conditions beyond 7FFFH and 8000H.
EVEX encoded PACKSSWB: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register, updated conditional under the writemask k1.
EVEX encoded PACKSSDW: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-
bit memory location. The destination operand is a ZMM/YMM/XMM register, updated conditional under the
writemask k1.





VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM destination register destination are unmodified.

Operation
PACKSSWB instruction (128-bit Legacy SSE version)
  DEST[7:0] <- SaturateSignedWordToSignedByte (DEST[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (DEST[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (DEST[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (DEST[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (DEST[79:64]);
  DEST[47:40] <- SaturateSignedWordToSignedByte (DEST[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (DEST[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (DEST[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC[127:112]);
  DEST[MAX_VL-1:128] (Unmodified)

PACKSSDW instruction (128-bit Legacy SSE version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (DEST[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (DEST[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (DEST[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (DEST[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC[127:96]);
  DEST[MAX_VL-1:128] (Unmodified)





VPACKSSWB instruction (VEX.128 encoded version)
  DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);
  DEST[MAX_VL-1:128] <- 0;

VPACKSSDW instruction (VEX.128 encoded version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);
  DEST[MAX_VL-1:128] <- 0;

VPACKSSWB instruction (VEX.256 encoded version)
  DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);
  DEST[135:128] <- SaturateSignedWordToSignedByte (SRC1[143:128]);
  DEST[143:136] <- SaturateSignedWordToSignedByte (SRC1[159:144]);
  DEST[151:144] <- SaturateSignedWordToSignedByte (SRC1[175:160]);
  DEST[159:152] <- SaturateSignedWordToSignedByte (SRC1[191:176]);
  DEST[167:160] <- SaturateSignedWordToSignedByte (SRC1[207:192]);
  DEST[175:168] <- SaturateSignedWordToSignedByte (SRC1[223:208]);
  DEST[183:176] <- SaturateSignedWordToSignedByte (SRC1[239:224]);



   DEST[191:184] <- SaturateSignedWordToSignedByte (SRC1[255:240]);
   DEST[199:192] <- SaturateSignedWordToSignedByte (SRC2[143:128]);
   DEST[207:200] <- SaturateSignedWordToSignedByte (SRC2[159:144]);
   DEST[215:208] <- SaturateSignedWordToSignedByte (SRC2[175:160]);
   DEST[223:216] <- SaturateSignedWordToSignedByte (SRC2[191:176]);
   DEST[231:224] <- SaturateSignedWordToSignedByte (SRC2[207:192]);
   DEST[239:232] <- SaturateSignedWordToSignedByte (SRC2[223:208]);
   DEST[247:240] <- SaturateSignedWordToSignedByte (SRC2[239:224]);
   DEST[255:248] <- SaturateSignedWordToSignedByte (SRC2[255:240]);
   DEST[MAX_VL-1:256] <- 0;

VPACKSSDW instruction (VEX.256 encoded version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);
  DEST[143:128] <- SaturateSignedDwordToSignedWord (SRC1[159:128]);
  DEST[159:144] <- SaturateSignedDwordToSignedWord (SRC1[191:160]);
  DEST[175:160] <- SaturateSignedDwordToSignedWord (SRC1[223:192]);
  DEST[191:176] <- SaturateSignedDwordToSignedWord (SRC1[255:224]);
  DEST[207:192] <- SaturateSignedDwordToSignedWord (SRC2[159:128]);
  DEST[223:208] <- SaturateSignedDwordToSignedWord (SRC2[191:160]);
  DEST[239:224] <- SaturateSignedDwordToSignedWord (SRC2[223:192]);
  DEST[255:240] <- SaturateSignedDwordToSignedWord (SRC2[255:224]);
  DEST[MAX_VL-1:256] <- 0;

VPACKSSWB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
TMP_DEST[7:0] <- SaturateSignedWordToSignedByte (SRC1[15:0]);
TMP_DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);
TMP_DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);
TMP_DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);
TMP_DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);
TMP_DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);
TMP_DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);
TMP_DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);
TMP_DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);
TMP_DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);
TMP_DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);
TMP_DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);
TMP_DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);
TMP_DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);
TMP_DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);
TMP_DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);
IF VL >= 256
    TMP_DEST[135:128]<- SaturateSignedWordToSignedByte (SRC1[143:128]);
    TMP_DEST[143:136] <- SaturateSignedWordToSignedByte (SRC1[159:144]);
    TMP_DEST[151:144] <- SaturateSignedWordToSignedByte (SRC1[175:160]);
    TMP_DEST[159:152] <- SaturateSignedWordToSignedByte (SRC1[191:176]);
    TMP_DEST[167:160] <- SaturateSignedWordToSignedByte (SRC1[207:192]);



   TMP_DEST[175:168] <- SaturateSignedWordToSignedByte (SRC1[223:208]);
   TMP_DEST[183:176] <- SaturateSignedWordToSignedByte (SRC1[239:224]);
   TMP_DEST[191:184] <- SaturateSignedWordToSignedByte (SRC1[255:240]);
   TMP_DEST[199:192] <- SaturateSignedWordToSignedByte (SRC2[143:128]);
   TMP_DEST[207:200] <- SaturateSignedWordToSignedByte (SRC2[159:144]);
   TMP_DEST[215:208] <- SaturateSignedWordToSignedByte (SRC2[175:160]);
   TMP_DEST[223:216] <- SaturateSignedWordToSignedByte (SRC2[191:176]);
   TMP_DEST[231:224] <- SaturateSignedWordToSignedByte (SRC2[207:192]);
   TMP_DEST[239:232] <- SaturateSignedWordToSignedByte (SRC2[223:208]);
   TMP_DEST[247:240] <- SaturateSignedWordToSignedByte (SRC2[239:224]);
   TMP_DEST[255:248] <- SaturateSignedWordToSignedByte (SRC2[255:240]);
FI;
IF VL >= 512
    TMP_DEST[263:256] <- SaturateSignedWordToSignedByte (SRC1[271:256]);
    TMP_DEST[271:264] <- SaturateSignedWordToSignedByte (SRC1[287:272]);
    TMP_DEST[279:272] <- SaturateSignedWordToSignedByte (SRC1[303:288]);
    TMP_DEST[287:280] <- SaturateSignedWordToSignedByte (SRC1[319:304]);
    TMP_DEST[295:288] <- SaturateSignedWordToSignedByte (SRC1[335:320]);
    TMP_DEST[303:296] <- SaturateSignedWordToSignedByte (SRC1[351:336]);
    TMP_DEST[311:304] <- SaturateSignedWordToSignedByte (SRC1[367:352]);
    TMP_DEST[319:312] <- SaturateSignedWordToSignedByte (SRC1[383:368]);

   TMP_DEST[327:320] <- SaturateSignedWordToSignedByte (SRC2[271:256]);
   TMP_DEST[335:328] <- SaturateSignedWordToSignedByte (SRC2[287:272]);
   TMP_DEST[343:336] <- SaturateSignedWordToSignedByte (SRC2[303:288]);
   TMP_DEST[351:344] <- SaturateSignedWordToSignedByte (SRC2[319:304]);
   TMP_DEST[359:352] <- SaturateSignedWordToSignedByte (SRC2[335:320]);
   TMP_DEST[367:360] <- SaturateSignedWordToSignedByte (SRC2[351:336]);
   TMP_DEST[375:368] <- SaturateSignedWordToSignedByte (SRC2[367:352]);
   TMP_DEST[383:376] <- SaturateSignedWordToSignedByte (SRC2[383:368]);

   TMP_DEST[391:384] <- SaturateSignedWordToSignedByte (SRC1[399:384]);
   TMP_DEST[399:392] <- SaturateSignedWordToSignedByte (SRC1[415:400]);
   TMP_DEST[407:400] <- SaturateSignedWordToSignedByte (SRC1[431:416]);
   TMP_DEST[415:408] <- SaturateSignedWordToSignedByte (SRC1[447:432]);
   TMP_DEST[423:416] <- SaturateSignedWordToSignedByte (SRC1[463:448]);
   TMP_DEST[431:424] <- SaturateSignedWordToSignedByte (SRC1[479:464]);
   TMP_DEST[439:432] <- SaturateSignedWordToSignedByte (SRC1[495:480]);
   TMP_DEST[447:440] <- SaturateSignedWordToSignedByte (SRC1[511:496]);

   TMP_DEST[455:448] <- SaturateSignedWordToSignedByte (SRC2[399:384]);
   TMP_DEST[463:456] <- SaturateSignedWordToSignedByte (SRC2[415:400]);
   TMP_DEST[471:464] <- SaturateSignedWordToSignedByte (SRC2[431:416]);
   TMP_DEST[479:472] <- SaturateSignedWordToSignedByte (SRC2[447:432]);
   TMP_DEST[487:480] <- SaturateSignedWordToSignedByte (SRC2[463:448]);
   TMP_DEST[495:488] <- SaturateSignedWordToSignedByte (SRC2[479:464]);
   TMP_DEST[503:496] <- SaturateSignedWordToSignedByte (SRC2[495:480]);
   TMP_DEST[511:504] <- SaturateSignedWordToSignedByte (SRC2[511:496]);
FI;
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN
              DEST[i+7:i] <- TMP_DEST[i+7:i]



        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+7:i] remains unchanged*
                 ELSE *zeroing-masking*              ; zeroing-masking
                     DEST[i+7:i] <- 0
            FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPACKSSDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO ((KL/2) - 1)
    i <- j * 32

   IF (EVEX.b == 1) AND (SRC2 *is memory*)
        THEN
            TMP_SRC2[i+31:i] <- SRC2[31:0]
        ELSE
            TMP_SRC2[i+31:i] <- SRC2[i+31:i]
   FI;
ENDFOR;

TMP_DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);
TMP_DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);
TMP_DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);
TMP_DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);
TMP_DEST[79:64] <- SaturateSignedDwordToSignedWord (TMP_SRC2[31:0]);
TMP_DEST[95:80] <- SaturateSignedDwordToSignedWord (TMP_SRC2[63:32]);
TMP_DEST[111:96] <- SaturateSignedDwordToSignedWord (TMP_SRC2[95:64]);
TMP_DEST[127:112] <- SaturateSignedDwordToSignedWord (TMP_SRC2[127:96]);
IF VL >= 256
    TMP_DEST[143:128] <- SaturateSignedDwordToSignedWord (SRC1[159:128]);
    TMP_DEST[159:144] <- SaturateSignedDwordToSignedWord (SRC1[191:160]);
    TMP_DEST[175:160] <- SaturateSignedDwordToSignedWord (SRC1[223:192]);
    TMP_DEST[191:176] <- SaturateSignedDwordToSignedWord (SRC1[255:224]);
    TMP_DEST[207:192] <- SaturateSignedDwordToSignedWord (TMP_SRC2[159:128]);
    TMP_DEST[223:208] <- SaturateSignedDwordToSignedWord (TMP_SRC2[191:160]);
    TMP_DEST[239:224] <- SaturateSignedDwordToSignedWord (TMP_SRC2[223:192]);
    TMP_DEST[255:240] <- SaturateSignedDwordToSignedWord (TMP_SRC2[255:224]);
FI;
IF VL >= 512
    TMP_DEST[271:256] <- SaturateSignedDwordToSignedWord (SRC1[287:256]);
    TMP_DEST[287:272] <- SaturateSignedDwordToSignedWord (SRC1[319:288]);
    TMP_DEST[303:288] <- SaturateSignedDwordToSignedWord (SRC1[351:320]);
    TMP_DEST[319:304] <- SaturateSignedDwordToSignedWord (SRC1[383:352]);
    TMP_DEST[335:320] <- SaturateSignedDwordToSignedWord (TMP_SRC2[287:256]);
    TMP_DEST[351:336] <- SaturateSignedDwordToSignedWord (TMP_SRC2[319:288]);
    TMP_DEST[367:352] <- SaturateSignedDwordToSignedWord (TMP_SRC2[351:320]);
    TMP_DEST[383:368] <- SaturateSignedDwordToSignedWord (TMP_SRC2[383:352]);

   TMP_DEST[399:384] <- SaturateSignedDwordToSignedWord (SRC1[415:384]);
   TMP_DEST[415:400] <- SaturateSignedDwordToSignedWord (SRC1[447:416]);
   TMP_DEST[431:416] <- SaturateSignedDwordToSignedWord (SRC1[479:448]);



   TMP_DEST[447:432] <- SaturateSignedDwordToSignedWord (SRC1[511:480]);
   TMP_DEST[463:448] <- SaturateSignedDwordToSignedWord (TMP_SRC2[415:384]);
   TMP_DEST[479:464] <- SaturateSignedDwordToSignedWord (TMP_SRC2[447:416]);
   TMP_DEST[495:480] <- SaturateSignedDwordToSignedWord (TMP_SRC2[479:448]);
   TMP_DEST[511:496] <- SaturateSignedDwordToSignedWord (TMP_SRC2[511:480]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+15:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPACKSSDW__m512i _mm512_packs_epi32(__m512i m1, __m512i m2);
VPACKSSDW__m512i _mm512_mask_packs_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKSSDW__m512i _mm512_maskz_packs_epi32( __mmask32 k, __m512i m1, __m512i m2);
VPACKSSDW__m256i _mm256_mask_packs_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKSSDW__m256i _mm256_maskz_packs_epi32( __mmask16 k, __m256i m1, __m256i m2);
VPACKSSDW__m128i _mm_mask_packs_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKSSDW__m128i _mm_maskz_packs_epi32( __mmask8 k, __m128i m1, __m128i m2);
VPACKSSWB__m512i _mm512_packs_epi16(__m512i m1, __m512i m2);
VPACKSSWB__m512i _mm512_mask_packs_epi16(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKSSWB__m512i _mm512_maskz_packs_epi16( __mmask32 k, __m512i m1, __m512i m2);
VPACKSSWB__m256i _mm256_mask_packs_epi16( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKSSWB__m256i _mm256_maskz_packs_epi16( __mmask16 k, __m256i m1, __m256i m2);
VPACKSSWB__m128i _mm_mask_packs_epi16( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKSSWB__m128i _mm_maskz_packs_epi16( __mmask8 k, __m128i m1, __m128i m2);
PACKSSWB __m128i _mm_packs_epi16(__m128i m1, __m128i m2)
PACKSSDW __m128i _mm_packs_epi32(__m128i m1, __m128i m2)
VPACKSSWB __m256i _mm256_packs_epi16(__m256i m1, __m256i m2)
VPACKSSDW __m256i _mm256_packs_epi32(__m256i m1, __m256i m2)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPACKSSDW, see Exceptions Type E4NF.
EVEX-encoded VPACKSSWB, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PACKUSDW
description:
PACKUSDW-Pack with Unsigned Saturation
 Opcode/                            Op /     64/32        CPUID             Description
 Instruction                        En       bit Mode     Feature
                                             Support      Flag
 66 0F 38 2B /r                     RM       V/V          SSE4_1            Convert 4 packed signed doubleword integers from xmm1
 PACKUSDW xmm1, xmm2/m128                                                   and 4 packed signed doubleword integers from
                                                                            xmm2/m128 into 8 packed unsigned word integers in
                                                                            xmm1 using unsigned saturation.
 VEX.NDS.128.66.0F38 2B /r          RVM      V/V          AVX               Convert 4 packed signed doubleword integers from xmm2
 VPACKUSDW xmm1,xmm2,                                                       and 4 packed signed doubleword integers from
 xmm3/m128                                                                  xmm3/m128 into 8 packed unsigned word integers in
                                                                            xmm1 using unsigned saturation.
 VEX.NDS.256.66.0F38 2B /r          RVM      V/V          AVX2              Convert 8 packed signed doubleword integers from ymm2
 VPACKUSDW ymm1, ymm2,                                                      and 8 packed signed doubleword integers from
 ymm3/m256                                                                  ymm3/m256 into 16 packed unsigned word integers in
                                                                            ymm1 using unsigned saturation.
 EVEX.NDS.128.66.0F38.W0 2B /r      FV       V/V          AVX512VL          Convert packed signed doubleword integers from xmm2
 VPACKUSDW xmm1{k1}{z},                                   AVX512BW          and packed signed doubleword integers from
 xmm2, xmm3/m128/m32bcst                                                    xmm3/m128/m32bcst into packed unsigned word integers
                                                                            in xmm1 using unsigned saturation under writemask k1.
 EVEX.NDS.256.66.0F38.W0 2B /r      FV       V/V          AVX512VL          Convert packed signed doubleword integers from ymm2
                                                          AVX512BW          and packed signed doubleword integers from
                                                                            ymm3/m256/m32bcst into packed unsigned word integers
                                                                            in ymm1 using unsigned saturation under writemask k1.
 EVEX.NDS.512.66.0F38.W0 2B /r      FV       V/V          AVX512BW          Convert packed signed doubleword integers from zmm2
 VPACKUSDW zmm1{k1}{z},                                                     and packed signed doubleword integers from
 zmm2, zmm3/m512/m32bcst                                                    zmm3/m512/m32bcst into packed unsigned word integers
                                                                            in zmm1 using unsigned saturation under writemask k1.



                                                   Instruction Operand Encoding
          Op/En                 Operand 1                       Operand 2                    Operand 3              Operand 4
           RM                ModRM:reg (r, w)               ModRM:r/m (r)                       NA                     NA
          RVM                ModRM:reg (w)                   VEX.vvvv (r)                  ModRM:r/m (r)               NA
              FV             ModRM:reg (w)                  EVEX.vvvv (r)                  ModRM:r/m (r)               NA

Description
Converts packed signed doubleword integers in the first and second source operands into packed unsigned word
integers using unsigned saturation to handle overflow conditions. If the signed doubleword value is beyond the
range of an unsigned word (that is, greater than FFFFH or less than 0000H), the saturated unsigned word integer
value of FFFFH or 0000H, respectively, is stored in the destination.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted from a 32-
bit memory location. The destination operand is a ZMM register, updated conditionally under the writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding destination register destination are unmodified.




Operation
PACKUSDW (Legacy SSE instruction)
TMP[15:0] <- (DEST[31:0] < 0) ? 0 : DEST[15:0];
DEST[15:0] <- (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (DEST[63:32] < 0) ? 0 : DEST[47:32];
DEST[31:16] <- (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (DEST[95:64] < 0) ? 0 : DEST[79:64];
DEST[47:32] <- (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (DEST[127:96] < 0) ? 0 : DEST[111:96];
DEST[63:48] <- (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC[31:0] < 0) ? 0 : SRC[15:0];
DEST[79:64] <- (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC[63:32] < 0) ? 0 : SRC[47:32];
DEST[95:80] <- (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC[95:64] < 0) ? 0 : SRC[79:64];
DEST[111:96] <- (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (SRC[127:96] < 0) ? 0 : SRC[111:96];
DEST[127:112] <- (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
DEST[MAX_VL-1:128] (Unmodified)

PACKUSDW (VEX.128 encoded version)
TMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[79:64] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[127:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];
DEST[MAX_VL-1:128] <- 0;

VPACKUSDW (VEX.256 encoded version)
TMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[79:64] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;



TMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[127:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
TMP[143:128] <- (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
DEST[143:128] <- (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
TMP[159:144] <- (SRC1[191:160] < 0) ? 0 : SRC1[175:160];
DEST[159:144] <- (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;
TMP[175:160] <- (SRC1[223:192] < 0) ? 0 : SRC1[207:192];
DEST[175:160] <- (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
TMP[191:176] <- (SRC1[255:224] < 0) ? 0 : SRC1[239:224];
DEST[191:176] <- (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;
TMP[207:192] <- (SRC2[159:128] < 0) ? 0 : SRC2[143:128];
DEST[207:192] <- (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;
TMP[223:208] <- (SRC2[191:160] < 0) ? 0 : SRC2[175:160];
DEST[223:208] <- (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;
TMP[239:224] <- (SRC2[223:192] < 0) ? 0 : SRC2[207:192];
DEST[239:224] <- (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;
TMP[255:240] <- (SRC2[255:224] < 0) ? 0 : SRC2[239:224];
DEST[255:240] <- (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;
DEST[MAX_VL-1:256] <- 0;

VPACKUSDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO ((KL/2) - 1)
    i <- j * 32

   IF (EVEX.b == 1) AND (SRC2 *is memory*)
        THEN
            TMP_SRC2[i+31:i] <- SRC2[31:0]
        ELSE
            TMP_SRC2[i+31:i] <- SRC2[i+31:i]
   FI;
ENDFOR;

TMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (TMP_SRC2[31:0] < 0) ? 0 : TMP_SRC2[15:0];
DEST[79:64] <- (TMP_SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (TMP_SRC2[63:32] < 0) ? 0 : TMP_SRC2[47:32];
DEST[95:80] <- (TMP_SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (TMP_SRC2[95:64] < 0) ? 0 : TMP_SRC2[79:64];
DEST[111:96] <- (TMP_SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (TMP_SRC2[127:96] < 0) ? 0 : TMP_SRC2[111:96];
DEST[127:112] <- (TMP_SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
IF VL >= 256
    TMP[143:128] <- (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
    DEST[143:128] <- (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
    TMP[159:144] <- (SRC1[191:160] < 0) ? 0 : SRC1[175:160];
    DEST[159:144] <- (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;



   TMP[175:160] <- (SRC1[223:192] < 0) ? 0 : SRC1[207:192];
   DEST[175:160] <- (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
   TMP[191:176] <- (SRC1[255:224] < 0) ? 0 : SRC1[239:224];
   DEST[191:176] <- (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;
   TMP[207:192] <- (TMP_SRC2[159:128] < 0) ? 0 : TMP_SRC2[143:128];
   DEST[207:192] <- (TMP_SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;
   TMP[223:208] <- (TMP_SRC2[191:160] < 0) ? 0 : TMP_SRC2[175:160];
   DEST[223:208] <- (TMP_SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;
   TMP[239:224] <- (TMP_SRC2[223:192] < 0) ? 0 : TMP_SRC2[207:192];
   DEST[239:224] <- (TMP_SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;
   TMP[255:240] <- (TMP_SRC2[255:224] < 0) ? 0 : TMP_SRC2[239:224];
   DEST[255:240] <- (TMP_SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;
FI;
IF VL >= 512
    TMP[271:256] <- (SRC1[287:256] < 0) ? 0 : SRC1[271:256];
    DEST[271:256] <- (SRC1[287:256] > FFFFH) ? FFFFH : TMP[271:256] ;
    TMP[287:272] <- (SRC1[319:288] < 0) ? 0 : SRC1[303:288];
    DEST[287:272] <- (SRC1[319:288] > FFFFH) ? FFFFH : TMP[287:272] ;
    TMP[303:288] <- (SRC1[351:320] < 0) ? 0 : SRC1[335:320];
    DEST[303:288] <- (SRC1[351:320] > FFFFH) ? FFFFH : TMP[303:288] ;
    TMP[319:304] <- (SRC1[383:352] < 0) ? 0 : SRC1[367:352];
    DEST[319:304] <- (SRC1[383:352] > FFFFH) ? FFFFH : TMP[319:304] ;
    TMP[335:320] <- (TMP_SRC2[287:256] < 0) ? 0 : TMP_SRC2[271:256];
    DEST[335:304] <- (TMP_SRC2[287:256] > FFFFH) ? FFFFH : TMP[79:64] ;
    TMP[351:336] <- (TMP_SRC2[319:288] < 0) ? 0 : TMP_SRC2[303:288];
    DEST[351:336] <- (TMP_SRC2[319:288] > FFFFH) ? FFFFH : TMP[351:336] ;
    TMP[367:352] <- (TMP_SRC2[351:320] < 0) ? 0 : TMP_SRC2[315:320];
    DEST[367:352] <- (TMP_SRC2[351:320] > FFFFH) ? FFFFH : TMP[367:352] ;
    TMP[383:368] <- (TMP_SRC2[383:352] < 0) ? 0 : TMP_SRC2[367:352];
    DEST[383:368] <- (TMP_SRC2[383:352] > FFFFH) ? FFFFH : TMP[383:368] ;
    TMP[399:384] <- (SRC1[415:384] < 0) ? 0 : SRC1[399:384];
    DEST[399:384] <- (SRC1[415:384] > FFFFH) ? FFFFH : TMP[399:384] ;
    TMP[415:400] <- (SRC1[447:416] < 0) ? 0 : SRC1[431:416];
    DEST[415:400] <- (SRC1[447:416] > FFFFH) ? FFFFH : TMP[415:400] ;
    TMP[431:416] <- (SRC1[479:448] < 0) ? 0 : SRC1[463:448];
    DEST[431:416] <- (SRC1[479:448] > FFFFH) ? FFFFH : TMP[431:416] ;
    TMP[447:432] <- (SRC1[511:480] < 0) ? 0 : SRC1[495:480];
    DEST[447:432] <- (SRC1[511:480] > FFFFH) ? FFFFH : TMP[447:432] ;
    TMP[463:448] <- (TMP_SRC2[415:384] < 0) ? 0 : TMP_SRC2[399:384];
    DEST[463:448] <- (TMP_SRC2[415:384] > FFFFH) ? FFFFH : TMP[463:448] ;
    TMP[475:464] <- (TMP_SRC2[447:416] < 0) ? 0 : TMP_SRC2[431:416];
    DEST[475:464] <- (TMP_SRC2[447:416] > FFFFH) ? FFFFH : TMP[475:464] ;
    TMP[491:476] <- (TMP_SRC2[479:448] < 0) ? 0 : TMP_SRC2[463:448];
    DEST[491:476] <- (TMP_SRC2[479:448] > FFFFH) ? FFFFH : TMP[491:476] ;
    TMP[511:492] <- (TMP_SRC2[511:480] < 0) ? 0 : TMP_SRC2[495:480];
    DEST[511:492] <- (TMP_SRC2[511:480] > FFFFH) ? FFFFH : TMP[511:492] ;
FI;
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN
              DEST[i+15:i] <- TMP_DEST[i+15:i]
         ELSE
              IF *merging-masking*             ; merging-masking



                 THEN *DEST[i+15:i] remains unchanged*
                 ELSE *zeroing-masking*             ; zeroing-masking
                     DEST[i+15:i] <- 0
          FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPACKUSDW__m512i _mm512_packus_epi32(__m512i m1, __m512i m2);
VPACKUSDW__m512i _mm512_mask_packus_epi32(__m512i s, __mmask32 k, __m512i m1, __m512i m2);
VPACKUSDW__m512i _mm512_maskz_packus_epi32( __mmask32 k, __m512i m1, __m512i m2);
VPACKUSDW__m256i _mm256_mask_packus_epi32( __m256i s, __mmask16 k, __m256i m1, __m256i m2);
VPACKUSDW__m256i _mm256_maskz_packus_epi32( __mmask16 k, __m256i m1, __m256i m2);
VPACKUSDW__m128i _mm_mask_packus_epi32( __m128i s, __mmask8 k, __m128i m1, __m128i m2);
VPACKUSDW__m128i _mm_maskz_packus_epi32( __mmask8 k, __m128i m1, __m128i m2);
PACKUSDW__m128i _mm_packus_epi32(__m128i m1, __m128i m2);
VPACKUSDW__m256i _mm256_packus_epi32(__m256i m1, __m256i m2);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.






platform: x86_64
mnem: PACKUSWB
description:
PACKUSWB-Pack with Unsigned Saturation
Opcode/                                             Op/   64/32 bit    CPUID        Description
Instruction                                         En    Mode         Feature Flag
                                                          Support
0F 67 /r1                                           RM    V/V          MMX            Converts 4 signed word integers from mm and
PACKUSWB mm, mm/m64                                                                   4 signed word integers from mm/m64 into 8
                                                                                      unsigned byte integers in mm using unsigned
                                                                                      saturation.
66 0F 67 /r                                         RM    V/V          SSE2           Converts 8 signed word integers from xmm1
PACKUSWB xmm1, xmm2/m128                                                              and 8 signed word integers from xmm2/m128
                                                                                      into 16 unsigned byte integers in xmm1 using
                                                                                      unsigned saturation.
VEX.NDS.128.66.0F.WIG 67 /r                         RVM V/V            AVX            Converts 8 signed word integers from xmm2
VPACKUSWB xmm1, xmm2, xmm3/m128                                                       and 8 signed word integers from xmm3/m128
                                                                                      into 16 unsigned byte integers in xmm1 using
                                                                                      unsigned saturation.
VEX.NDS.256.66.0F.WIG 67 /r                         RVM V/V            AVX2           Converts 16 signed word integers from ymm2
VPACKUSWB ymm1, ymm2, ymm3/m256                                                       and 16signed word integers from
                                                                                      ymm3/m256 into 32 unsigned byte integers
                                                                                      in ymm1 using unsigned saturation.
EVEX.NDS.128.66.0F.WIG 67 /r                        FVM V/V            AVX512VL       Converts signed word integers from xmm2
VPACKUSWB xmm1{k1}{z}, xmm2, xmm3/m128                                 AVX512BW       and signed word integers from xmm3/m128
                                                                                      into unsigned byte integers in xmm1 using
                                                                                      unsigned saturation under writemask k1.
EVEX.NDS.256.66.0F.WIG 67 /r                        FVM V/V            AVX512VL       Converts signed word integers from ymm2
VPACKUSWB ymm1{k1}{z}, ymm2, ymm3/m256                                 AVX512BW       and signed word integers from ymm3/m256
                                                                                      into unsigned byte integers in ymm1 using
                                                                                      unsigned saturation under writemask k1.
EVEX.NDS.512.66.0F.WIG 67 /r                        FVM V/V            AVX512BW       Converts signed word integers from zmm2
VPACKUSWB zmm1{k1}{z}, zmm2, zmm3/m512                                                and signed word integers from zmm3/m512
                                                                                      into unsigned byte integers in zmm1 using
                                                                                      unsigned saturation under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers" in
the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                    Operand 3                      Operand 4
    RM             ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA
    RVM             ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                       NA
    FVM             ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                      NA


Description
Converts 4, 8, 16 or 32 signed word integers from the destination operand (first operand) and 4, 8, 16 or 32 signed
word integers from the source operand (second operand) into 8, 16, 32 or 64 unsigned byte integers and stores the
result in the destination operand. (See Figure 4-6 for an example of the packing operation.) If a signed word
integer value is beyond the range of an unsigned byte integer (that is, greater than FFH or less than 00H), the satu-
rated unsigned byte integer value of FFH or 00H, respectively, is stored in the destination.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register or a 512-bit memory location. The destination operand is a ZMM register.



VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register. The upper bits
(MAX_VL-1:256) of the corresponding ZMM register destination are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.

Operation
PACKUSWB (with 64-bit operands)
  DEST[7:0] <- SaturateSignedWordToUnsignedByte DEST[15:0];
  DEST[15:8] <- SaturateSignedWordToUnsignedByte DEST[31:16];
  DEST[23:16] <- SaturateSignedWordToUnsignedByte DEST[47:32];
  DEST[31:24] <- SaturateSignedWordToUnsignedByte DEST[63:48];
  DEST[39:32] <- SaturateSignedWordToUnsignedByte SRC[15:0];
  DEST[47:40] <- SaturateSignedWordToUnsignedByte SRC[31:16];
  DEST[55:48] <- SaturateSignedWordToUnsignedByte SRC[47:32];
  DEST[63:56] <- SaturateSignedWordToUnsignedByte SRC[63:48];

PACKUSWB (Legacy SSE instruction)
  DEST[7:0]<-SaturateSignedWordToUnsignedByte (DEST[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (DEST[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (DEST[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (DEST[63:48]);
  DEST[39:32] <- SaturateSignedWordToUnsignedByte (DEST[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (DEST[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (DEST[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (DEST[127:112]);
  DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC[95:80]);
  DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC[111:96]);
  DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC[127:112]);

PACKUSWB (VEX.128 encoded version)
  DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToUnsignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);



   DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);
   DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);
   DEST[VLMAX-1:128] <- 0;

VPACKUSWB (VEX.256 encoded version)
  DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);
  DEST[39:32] <-SaturateSignedWordToUnsignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);
  DEST[71:64] <-SaturateSignedWordToUnsignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);
  DEST[135:128]<- SaturateSignedWordToUnsignedByte (SRC1[143:128]);
  DEST[143:136] <-SaturateSignedWordToUnsignedByte (SRC1[159:144]);
  DEST[151:144] <-SaturateSignedWordToUnsignedByte (SRC1[175:160]);
  DEST[159:152] <-SaturateSignedWordToUnsignedByte (SRC1[191:176]);
  DEST[167:160] <- SaturateSignedWordToUnsignedByte (SRC1[207:192]);
  DEST[175:168] <- SaturateSignedWordToUnsignedByte (SRC1[223:208]);
  DEST[183:176] <- SaturateSignedWordToUnsignedByte (SRC1[239:224]);
  DEST[191:184] <- SaturateSignedWordToUnsignedByte (SRC1[255:240]);
  DEST[199:192] <- SaturateSignedWordToUnsignedByte (SRC2[143:128]);
  DEST[207:200] <- SaturateSignedWordToUnsignedByte (SRC2[159:144]);
  DEST[215:208] <- SaturateSignedWordToUnsignedByte (SRC2[175:160]);
  DEST[223:216] <- SaturateSignedWordToUnsignedByte (SRC2[191:176]);
  DEST[231:224] <- SaturateSignedWordToUnsignedByte (SRC2[207:192]);
  DEST[239:232] <- SaturateSignedWordToUnsignedByte (SRC2[223:208]);
  DEST[247:240] <- SaturateSignedWordToUnsignedByte (SRC2[239:224]);
  DEST[255:248] <- SaturateSignedWordToUnsignedByte (SRC2[255:240]);

VPACKUSWB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
TMP_DEST[7:0] <- SaturateSignedWordToUnsignedByte (SRC1[15:0]);
TMP_DEST[15:8] <- SaturateSignedWordToUnsignedByte (SRC1[31:16]);
TMP_DEST[23:16] <- SaturateSignedWordToUnsignedByte (SRC1[47:32]);
TMP_DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);
TMP_DEST[39:32] <- SaturateSignedWordToUnsignedByte (SRC1[79:64]);
TMP_DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);
TMP_DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);
TMP_DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);
TMP_DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC2[15:0]);
TMP_DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);
TMP_DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);
TMP_DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);
TMP_DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);
TMP_DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);



TMP_DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);
TMP_DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);
IF VL >= 256
    TMP_DEST[135:128]<- SaturateSignedWordToUnsignedByte (SRC1[143:128]);
    TMP_DEST[143:136] <- SaturateSignedWordToUnsignedByte (SRC1[159:144]);
    TMP_DEST[151:144] <- SaturateSignedWordToUnsignedByte (SRC1[175:160]);
    TMP_DEST[159:152] <- SaturateSignedWordToUnsignedByte (SRC1[191:176]);
    TMP_DEST[167:160] <- SaturateSignedWordToUnsignedByte (SRC1[207:192]);
    TMP_DEST[175:168] <- SaturateSignedWordToUnsignedByte (SRC1[223:208]);
    TMP_DEST[183:176] <- SaturateSignedWordToUnsignedByte (SRC1[239:224]);
    TMP_DEST[191:184] <- SaturateSignedWordToUnsignedByte (SRC1[255:240]);
    TMP_DEST[199:192] <- SaturateSignedWordToUnsignedByte (SRC2[143:128]);
    TMP_DEST[207:200] <- SaturateSignedWordToUnsignedByte (SRC2[159:144]);
    TMP_DEST[215:208] <- SaturateSignedWordToUnsignedByte (SRC2[175:160]);
    TMP_DEST[223:216] <- SaturateSignedWordToUnsignedByte (SRC2[191:176]);
    TMP_DEST[231:224] <- SaturateSignedWordToUnsignedByte (SRC2[207:192]);
    TMP_DEST[239:232] <- SaturateSignedWordToUnsignedByte (SRC2[223:208]);
    TMP_DEST[247:240] <- SaturateSignedWordToUnsignedByte (SRC2[239:224]);
    TMP_DEST[255:248] <- SaturateSignedWordToUnsignedByte (SRC2[255:240]);
FI;
IF VL >= 512
    TMP_DEST[263:256] <- SaturateSignedWordToUnsignedByte (SRC1[271:256]);
    TMP_DEST[271:264] <- SaturateSignedWordToUnsignedByte (SRC1[287:272]);
    TMP_DEST[279:272] <- SaturateSignedWordToUnsignedByte (SRC1[303:288]);
    TMP_DEST[287:280] <- SaturateSignedWordToUnsignedByte (SRC1[319:304]);
    TMP_DEST[295:288] <- SaturateSignedWordToUnsignedByte (SRC1[335:320]);
    TMP_DEST[303:296] <- SaturateSignedWordToUnsignedByte (SRC1[351:336]);
    TMP_DEST[311:304] <- SaturateSignedWordToUnsignedByte (SRC1[367:352]);
    TMP_DEST[319:312] <- SaturateSignedWordToUnsignedByte (SRC1[383:368]);

   TMP_DEST[327:320] <- SaturateSignedWordToUnsignedByte (SRC2[271:256]);
   TMP_DEST[335:328] <- SaturateSignedWordToUnsignedByte (SRC2[287:272]);
   TMP_DEST[343:336] <- SaturateSignedWordToUnsignedByte (SRC2[303:288]);
   TMP_DEST[351:344] <- SaturateSignedWordToUnsignedByte (SRC2[319:304]);
   TMP_DEST[359:352] <- SaturateSignedWordToUnsignedByte (SRC2[335:320]);
   TMP_DEST[367:360] <- SaturateSignedWordToUnsignedByte (SRC2[351:336]);
   TMP_DEST[375:368] <- SaturateSignedWordToUnsignedByte (SRC2[367:352]);
   TMP_DEST[383:376] <- SaturateSignedWordToUnsignedByte (SRC2[383:368]);

   TMP_DEST[391:384] <- SaturateSignedWordToUnsignedByte (SRC1[399:384]);
   TMP_DEST[399:392] <- SaturateSignedWordToUnsignedByte (SRC1[415:400]);
   TMP_DEST[407:400] <- SaturateSignedWordToUnsignedByte (SRC1[431:416]);
   TMP_DEST[415:408] <- SaturateSignedWordToUnsignedByte (SRC1[447:432]);
   TMP_DEST[423:416] <- SaturateSignedWordToUnsignedByte (SRC1[463:448]);
   TMP_DEST[431:424] <- SaturateSignedWordToUnsignedByte (SRC1[479:464]);
   TMP_DEST[439:432] <- SaturateSignedWordToUnsignedByte (SRC1[495:480]);
   TMP_DEST[447:440] <- SaturateSignedWordToUnsignedByte (SRC1[511:496]);

   TMP_DEST[455:448] <- SaturateSignedWordToUnsignedByte (SRC2[399:384]);
   TMP_DEST[463:456] <- SaturateSignedWordToUnsignedByte (SRC2[415:400]);
   TMP_DEST[471:464] <- SaturateSignedWordToUnsignedByte (SRC2[431:416]);
   TMP_DEST[479:472] <- SaturateSignedWordToUnsignedByte (SRC2[447:432]);
   TMP_DEST[487:480] <- SaturateSignedWordToUnsignedByte (SRC2[463:448]);
   TMP_DEST[495:488] <- SaturateSignedWordToUnsignedByte (SRC2[479:464]);



   TMP_DEST[503:496] <- SaturateSignedWordToUnsignedByte (SRC2[495:480]);
   TMP_DEST[511:504] <- SaturateSignedWordToUnsignedByte (SRC2[511:496]);
FI;
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN
              DEST[i+7:i] <- TMP_DEST[i+7:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPACKUSWB__m512i _mm512_packus_epi16(__m512i m1, __m512i m2);
VPACKUSWB__m512i _mm512_mask_packus_epi16(__m512i s, __mmask64 k, __m512i m1, __m512i m2);
VPACKUSWB__m512i _mm512_maskz_packus_epi16(__mmask64 k, __m512i m1, __m512i m2);
VPACKUSWB__m256i _mm256_mask_packus_epi16(__m256i s, __mmask32 k, __m256i m1, __m256i m2);
VPACKUSWB__m256i _mm256_maskz_packus_epi16(__mmask32 k, __m256i m1, __m256i m2);
VPACKUSWB__m128i _mm_mask_packus_epi16(__m128i s, __mmask16 k, __m128i m1, __m128i m2);
VPACKUSWB__m128i _mm_maskz_packus_epi16(__mmask16 k, __m128i m1, __m128i m2);
PACKUSWB:       __m64 _mm_packs_pu16(__m64 m1, __m64 m2)
(V)PACKUSWB: __m128i _mm_packus_epi16(__m128i m1, __m128i m2)
VPACKUSWB:       __m256i _mm256_packus_epi16(__m256i m1, __m256i m2);

Flags Affected
None

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PADDB
description:
PADDB/PADDW/PADDD/PADDQ-Add Packed Integers
 Opcode/                         Op /   64/32      CPUID      Description
 Instruction                     En     bit Mode   Feature
                                        Support    Flag
 0F FC /r1                       RM     V/V        MMX        Add packed byte integers from mm/m64 and mm.
 PADDB mm, mm/m64
 0F FD /r1                       RM     V/V        MMX        Add packed word integers from mm/m64 and mm.
 PADDW mm, mm/m64
 66 0F FC /r                     RM     V/V        SSE2       Add packed byte integers from xmm2/m128 and
 PADDB xmm1, xmm2/m128                                        xmm1.
 66 0F FD /r                     RM     V/V        SSE2       Add packed word integers from xmm2/m128 and
 PADDW xmm1, xmm2/m128                                        xmm1.
 66 0F FE /r                     RM     V/V        SSE2       Add packed doubleword integers from xmm2/m128
 PADDD xmm1, xmm2/m128                                        and xmm1.
 66 0F D4 /r                     RM     V/V        SSE2       Add packed quadword integers from xmm2/m128
 PADDQ xmm1, xmm2/m128                                        and xmm1.
 VEX.NDS.128.66.0F.WIG FC /r     RVM    V/V        AVX        Add packed byte integers from xmm2, and
 VPADDB xmm1, xmm2, xmm3/m128                                 xmm3/m128 and store in xmm1.
 VEX.NDS.128.66.0F.WIG FD /r     RVM    V/V        AVX        Add packed word integers from xmm2, xmm3/m128
 VPADDW xmm1, xmm2, xmm3/m128                                 and store in xmm1.
 VEX.NDS.128.66.0F.WIG FE /r     RVM    V/V        AVX        Add packed doubleword integers from xmm2,
 VPADDD xmm1, xmm2, xmm3/m128                                 xmm3/m128 and store in xmm1.
 VEX.NDS.128.66.0F.WIG D4 /r     RVM    V/V        AVX        Add packed quadword integers from xmm2,
 VPADDQ xmm1, xmm2, xmm3/m128                                 xmm3/m128 and store in xmm1.
 VEX.NDS.256.66.0F.WIG FC /r     RVM    V/V        AVX2       Add packed byte integers from ymm2, and
 VPADDB ymm1, ymm2, ymm3/m256                                 ymm3/m256 and store in ymm1.
 VEX.NDS.256.66.0F.WIG FD /r     RVM    V/V        AVX2       Add packed word integers from ymm2, ymm3/m256
 VPADDW ymm1, ymm2, ymm3/m256                                 and store in ymm1.
 VEX.NDS.256.66.0F.WIG FE /r     RVM    V/V        AVX2       Add packed doubleword integers from ymm2,
 VPADDD ymm1, ymm2, ymm3/m256                                 ymm3/m256 and store in ymm1.
 VEX.NDS.256.66.0F.WIG D4 /r     RVM    V/V        AVX2       Add packed quadword integers from ymm2,
 VPADDQ ymm1, ymm2, ymm3/m256                                 ymm3/m256 and store in ymm1.
 EVEX.NDS.128.66.0F.WIG FC /r    FVM    V/V        AVX512VL   Add packed byte integers from xmm2, and
 VPADDB xmm1 {k1}{z}, xmm2,                        AVX512BW   xmm3/m128 and store in xmm1 using writemask k1.
 xmm3/m128
 EVEX.NDS.128.66.0F.WIG FD /r    FVM    V/V        AVX512VL   Add packed word integers from xmm2, and
 VPADDW xmm1 {k1}{z}, xmm2,                        AVX512BW   xmm3/m128 and store in xmm1 using writemask k1.
 xmm3/m128
 EVEX.NDS.128.66.0F.W0 FE /r     FV     V/V        AVX512VL   Add packed doubleword integers from xmm2, and
 VPADDD xmm1 {k1}{z}, xmm2,                        AVX512F    xmm3/m128/m32bcst and store in xmm1 using
 xmm3/m128/m32bcst                                            writemask k1.
 EVEX.NDS.128.66.0F.W1 D4 /r     FV     V/V        AVX512VL   Add packed quadword integers from xmm2, and
 VPADDQ xmm1 {k1}{z}, xmm2,                        AVX512F    xmm3/m128/m64bcst and store in xmm1 using
 xmm3/m128/m64bcst                                            writemask k1.
 EVEX.NDS.256.66.0F.WIG FC /r    FVM    V/V        AVX512VL   Add packed byte integers from ymm2, and
 VPADDB ymm1 {k1}{z}, ymm2,                        AVX512BW   ymm3/m256 and store in ymm1 using writemask k1.
 ymm3/m256
 EVEX.NDS.256.66.0F.WIG FD /r    FVM    V/V        AVX512VL   Add packed word integers from ymm2, and
 VPADDW ymm1 {k1}{z}, ymm2,                        AVX512BW   ymm3/m256 and store in ymm1 using writemask k1.
 ymm3/m256
 EVEX.NDS.256.66.0F.W0 FE /r     FV     V/V        AVX512VL   Add packed doubleword integers from ymm2,
 VPADDD ymm1 {k1}{z}, ymm2,                        AVX512F    ymm3/m256/m32bcst and store in ymm1 using
 ymm3/m256/m32bcst                                            writemask k1.




 Opcode/                                   Op /    64/32        CPUID          Description
 Instruction                               En      bit Mode     Feature
                                                   Support      Flag
 EVEX.NDS.256.66.0F.W1 D4 /r               FV      V/V          AVX512VL       Add packed quadword integers from ymm2,
 VPADDQ ymm1 {k1}{z}, ymm2,                                     AVX512F        ymm3/m256/m64bcst and store in ymm1 using
 ymm3/m256/m64bcst                                                             writemask k1.
 EVEX.NDS.512.66.0F.WIG FC /r              FVM     V/V          AVX512BW       Add packed byte integers from zmm2, and
 VPADDB zmm1 {k1}{z}, zmm2,                                                    zmm3/m512 and store in zmm1 using writemask k1.
 zmm3/m512
 EVEX.NDS.512.66.0F.WIG FD /r              FVM     V/V          AVX512BW       Add packed word integers from zmm2, and
 VPADDW zmm1 {k1}{z}, zmm2,                                                    zmm3/m512 and store in zmm1 using writemask k1.
 zmm3/m512
 EVEX.NDS.512.66.0F.W0 FE /r               FV      V/V          AVX512F        Add packed doubleword integers from zmm2,
 VPADDD zmm1 {k1}{z}, zmm2,                                                    zmm3/m512/m32bcst and store in zmm1 using
 zmm3/m512/m32bcst                                                             writemask k1.
 EVEX.NDS.512.66.0F.W1 D4 /r               FV      V/V          AVX512F        Add packed quadword integers from zmm2,
 VPADDQ zmm1 {k1}{z}, zmm2,                                                    zmm3/m512/m64bcst and store in zmm1 using
 zmm3/m512/m64bcst                                                             writemask k1.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX
 Registers" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.


                                                  Instruction Operand Encoding
     Op/En                Operand 1                      Operand 2                   Operand 3                    Operand 4
       RM              ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA
      RVM               ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                      NA
      FVM               ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA
       FV               ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA

Description
Performs a SIMD add of the packed integers from the source operand (second operand) and the destination
operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with wraparound, as described in the following paragraphs.
The PADDB and VPADDB instructions add packed byte integers from the first source operand and second source
operand and store the packed integer results in the destination operand. When an individual result is too large to
be represented in 8 bits (overflow), the result is wrapped around and the low 8 bits are written to the destination
operand (that is, the carry is ignored).
The PADDW and VPADDW instructions add packed word integers from the first source operand and second source
operand and store the packed integer results in the destination operand. When an individual result is too large to
be represented in 16 bits (overflow), the result is wrapped around and the low 16 bits are written to the destination
operand (that is, the carry is ignored).
The PADDD and VPADDD instructions add packed doubleword integers from the first source operand and second
source operand and store the packed integer results in the destination operand. When an individual result is too
large to be represented in 32 bits (overflow), the result is wrapped around and the low 32 bits are written to the
destination operand (that is, the carry is ignored).
The PADDQ and VPADDQ instructions add packed quadword integers from the first source operand and second
source operand and store the packed integer results in the destination operand. When a quadword result is too
large to be represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the
destination operand (that is, the carry is ignored).




Note that the (V)PADDB, (V)PADDW, (V)PADDD and (V)PADDQ instructions can operate on either unsigned or
signed (two's complement notation) packed integers; however, it does not set bits in the EFLAGS register to indi-
cate overflow and/or a carry. To prevent undetected overflow conditions, software must control the ranges of
values operated on.
EVEX encoded VPADDD/Q: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the
writemask.
EVEX encoded VPADDB/W: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register updated according to the writemask.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. the upper bits (MAX_VL-1:256) of the
destination are cleared.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.

Operation
PADDB (with 64-bit operands)
  DEST[7:0] <- DEST[7:0] + SRC[7:0];
  (* Repeat add operation for 2nd through 7th byte *)
  DEST[63:56] <- DEST[63:56] + SRC[63:56];

PADDW (with 64-bit operands)
  DEST[15:0] <- DEST[15:0] + SRC[15:0];
  (* Repeat add operation for 2nd and 3th word *)
  DEST[63:48] <- DEST[63:48] + SRC[63:48];

PADDD (with 64-bit operands)
  DEST[31:0] <- DEST[31:0] + SRC[31:0];
  DEST[63:32] <- DEST[63:32] + SRC[63:32];
PADDQ (with 64-Bit operands)
  DEST[63:0] <- DEST[63:0] + SRC[63:0];

PADDB (Legacy SSE instruction)
  DEST[7:0]<- DEST[7:0] + SRC[7:0];
  (* Repeat add operation for 2nd through 15th byte *)
  DEST[127:120]<- DEST[127:120] + SRC[127:120];
  DEST[MAX_VL-1:128] (Unmodified)

PADDW (Legacy SSE instruction)
  DEST[15:0] <- DEST[15:0] + SRC[15:0];
  (* Repeat add operation for 2nd through 7th word *)
  DEST[127:112]<- DEST[127:112] + SRC[127:112];
  DEST[MAX_VL-1:128] (Unmodified)

PADDD (Legacy SSE instruction)
  DEST[31:0]<- DEST[31:0] + SRC[31:0];
  (* Repeat add operation for 2nd and 3th doubleword *)
  DEST[127:96]<- DEST[127:96] + SRC[127:96];



   DEST[MAX_VL-1:128] (Unmodified)

PADDQ (Legacy SSE instruction)
  DEST[63:0]<- DEST[63:0] + SRC[63:0];
  DEST[127:64]<- DEST[127:64] + SRC[127:64];
  DEST[MAX_VL-1:128] (Unmodified)

VPADDB (VEX.128 encoded instruction)
  DEST[7:0]<- SRC1[7:0] + SRC2[7:0];
  (* Repeat add operation for 2nd through 15th byte *)
  DEST[127:120]<- SRC1[127:120] + SRC2[127:120];
  DEST[MAX_VL-1:128] <- 0;

VPADDW (VEX.128 encoded instruction)
  DEST[15:0] <- SRC1[15:0] + SRC2[15:0];
  (* Repeat add operation for 2nd through 7th word *)
  DEST[127:112]<- SRC1[127:112] + SRC2[127:112];
  DEST[MAX_VL-1:128] <- 0;

VPADDD (VEX.128 encoded instruction)
  DEST[31:0]<- SRC1[31:0] + SRC2[31:0];
  (* Repeat add operation for 2nd and 3th doubleword *)
  DEST[127:96] <- SRC1[127:96] + SRC2[127:96];
  DEST[MAX_VL-1:128] <- 0;

VPADDQ (VEX.128 encoded instruction)
  DEST[63:0]<- SRC1[63:0] + SRC2[63:0];
  DEST[127:64] <- SRC1[127:64] + SRC2[127:64];
  DEST[MAX_VL-1:128] <- 0;

VPADDB (VEX.256 encoded instruction)
  DEST[7:0]<- SRC1[7:0] + SRC2[7:0];
  (* Repeat add operation for 2nd through 31th byte *)
  DEST[255:248]<- SRC1[255:248] + SRC2[255:248];

VPADDW (VEX.256 encoded instruction)
  DEST[15:0] <- SRC1[15:0] + SRC2[15:0];
  (* Repeat add operation for 2nd through 15th word *)
  DEST[255:240]<- SRC1[255:240] + SRC2[255:240];

VPADDD (VEX.256 encoded instruction)
  DEST[31:0]<- SRC1[31:0] + SRC2[31:0];
  (* Repeat add operation for 2nd and 7th doubleword *)
  DEST[255:224] <- SRC1[255:224] + SRC2[255:224];

VPADDQ (VEX.256 encoded instruction)
  DEST[63:0]<- SRC1[63:0] + SRC2[63:0];
  DEST[127:64] <- SRC1[127:64] + SRC2[127:64];
  DEST[191:128]<- SRC1[191:128] + SRC2[191:128];
  DEST[255:192] <- SRC1[255:192] + SRC2[255:192];

VPADDB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)




FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- SRC1[i+7:i] + SRC2[i+7:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPADDW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- SRC1[i+15:i] + SRC2[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPADDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] + SRC2[31:0]
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] + SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPADDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1



   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1) AND (SRC2 *is memory*)
                  THEN DEST[i+63:i] <- SRC1[i+63:i] + SRC2[63:0]
                  ELSE DEST[i+63:i] <- SRC1[i+63:i] + SRC2[i+63:i]
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPADDB__m512i _mm512_add_epi8 ( __m512i a, __m512i b)
VPADDW__m512i _mm512_add_epi16 ( __m512i a, __m512i b)
VPADDB__m512i _mm512_mask_add_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_mask_add_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDB__m512i _mm512_maskz_add_epi8 (__mmask64 m, __m512i a, __m512i b)
VPADDW__m512i _mm512_maskz_add_epi16 (__mmask32 m, __m512i a, __m512i b)
VPADDB__m256i _mm256_mask_add_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDW__m256i _mm256_mask_add_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDB__m256i _mm256_maskz_add_epi8 (__mmask32 m, __m256i a, __m256i b)
VPADDW__m256i _mm256_maskz_add_epi16 (__mmask16 m, __m256i a, __m256i b)
VPADDB__m128i _mm_mask_add_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDW__m128i _mm_mask_add_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDB__m128i _mm_maskz_add_epi8 (__mmask16 m, __m128i a, __m128i b)
VPADDW__m128i _mm_maskz_add_epi16 (__mmask8 m, __m128i a, __m128i b)
VPADDD __m512i _mm512_add_epi32( __m512i a, __m512i b);
VPADDD __m512i _mm512_mask_add_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPADDD __m512i _mm512_maskz_add_epi32( __mmask16 k, __m512i a, __m512i b);
VPADDD __m256i _mm256_mask_add_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPADDD __m256i _mm256_maskz_add_epi32( __mmask8 k, __m256i a, __m256i b);
VPADDD __m128i _mm_mask_add_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPADDD __m128i _mm_maskz_add_epi32( __mmask8 k, __m128i a, __m128i b);
VPADDQ __m512i _mm512_add_epi64( __m512i a, __m512i b);
VPADDQ __m512i _mm512_mask_add_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPADDQ __m512i _mm512_maskz_add_epi64( __mmask8 k, __m512i a, __m512i b);
VPADDQ __m256i _mm256_mask_add_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPADDQ __m256i _mm256_maskz_add_epi64( __mmask8 k, __m256i a, __m256i b);
VPADDQ __m128i _mm_mask_add_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPADDQ __m128i _mm_maskz_add_epi64( __mmask8 k, __m128i a, __m128i b);
PADDB __m128i _mm_add_epi8 (__m128i a,__m128i b );
PADDW __m128i _mm_add_epi16 ( __m128i a, __m128i b);
PADDD __m128i _mm_add_epi32 ( __m128i a, __m128i b);
PADDQ __m128i _mm_add_epi64 ( __m128i a, __m128i b);
VPADDB __m256i _mm256_add_epi8 (__m256ia,__m256i b );
VPADDW __m256i _mm256_add_epi16 ( __m256i a, __m256i b);
VPADDD __m256i _mm256_add_epi32 ( __m256i a, __m256i b);
VPADDQ __m256i _mm256_add_epi64 ( __m256i a, __m256i b);



PADDB __m64 _mm_add_pi8(__m64 m1, __m64 m2)
PADDW __m64 _mm_add_pi16(__m64 m1, __m64 m2)
PADDD __m64 _mm_add_pi32(__m64 m1, __m64 m2)
PADDQ __m64 _mm_add_pi64(__m64 m1, __m64 m2)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPADDD/Q, see Exceptions Type E4.
EVEX-encoded VPADDB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PADDSB
description:
PADDSB/PADDSW-Add Packed Signed Integers with Signed Saturation
Opcode/                                              Op/    64/32 bit   CPUID       Description
Instruction                                          En     Mode        Feature
                                                            Support     Flag
0F EC /r1                                            RM     V/V         MMX         Add packed signed byte integers from
PADDSB mm, mm/m64                                                                   mm/m64 and mm and saturate the results.

66 0F EC /r                                          RM     V/V         SSE2        Add packed signed byte integers from
PADDSB xmm1, xmm2/m128                                                              xmm2/m128 and xmm1 saturate the results.

0F ED /r1                                            RM     V/V         MMX         Add packed signed word integers from
PADDSW mm, mm/m64                                                                   mm/m64 and mm and saturate the results.

66 0F ED /r                                          RM     V/V         SSE2        Add packed signed word integers from
PADDSW xmm1, xmm2/m128                                                              xmm2/m128 and xmm1 and saturate the
                                                                                    results.
VEX.NDS.128.66.0F.WIG EC /r                          RVM V/V            AVX         Add packed signed byte integers from
VPADDSB xmm1, xmm2, xmm3/m128                                                       xmm3/m128 and xmm2 saturate the results.
VEX.NDS.128.66.0F.WIG ED /r                          RVM V/V            AVX         Add packed signed word integers from
VPADDSW xmm1, xmm2, xmm3/m128                                                       xmm3/m128 and xmm2 and saturate the
                                                                                    results.
VEX.NDS.256.66.0F.WIG EC /r                          RVM V/V            AVX2        Add packed signed byte integers from ymm2,
VPADDSB ymm1, ymm2, ymm3/m256                                                       and ymm3/m256 and store the saturated
                                                                                    results in ymm1.
VEX.NDS.256.66.0F.WIG ED /r                          RVM V/V            AVX2        Add packed signed word integers from ymm2,
VPADDSW ymm1, ymm2, ymm3/m256                                                       and ymm3/m256 and store the saturated
                                                                                    results in ymm1.
EVEX.NDS.128.66.0F.WIG EC /r                         FVM V/V            AVX512VL    Add packed signed byte integers from xmm2,
VPADDSB xmm1 {k1}{z}, xmm2, xmm3/m128                                   AVX512BW    and xmm3/m128 and store the saturated
                                                                                    results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG EC /r                         FVM V/V            AVX512VL    Add packed signed byte integers from ymm2,
VPADDSB ymm1 {k1}{z}, ymm2, ymm3/m256                                   AVX512BW    and ymm3/m256 and store the saturated
                                                                                    results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG EC /r                         FVM V/V            AVX512BW    Add packed signed byte integers from zmm2,
VPADDSB zmm1 {k1}{z}, zmm2, zmm3/m512                                               and zmm3/m512 and store the saturated
                                                                                    results in zmm1 under writemask k1.
EVEX.NDS.128.66.0F.WIG ED /r                         FVM V/V            AVX512VL    Add packed signed word integers from xmm2,
VPADDSW xmm1 {k1}{z}, xmm2, xmm3/m128                                   AVX512BW    and xmm3/m128 and store the saturated
                                                                                    results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG ED /r                         FVM V/V            AVX512VL    Add packed signed word integers from ymm2,
VPADDSW ymm1 {k1}{z}, ymm2, ymm3/m256                                   AVX512BW    and ymm3/m256 and store the saturated
                                                                                    results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG ED /r                         FVM V/V            AVX512BW    Add packed signed word integers from zmm2,
VPADDSW zmm1 {k1}{z}, zmm2, zmm3/m512                                               and zmm3/m512 and store the saturated
                                                                                    results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.





                                            Instruction Operand Encoding
   Op/En            Operand 1                  Operand 2                   Operand 3                     Operand 4
    RM           ModRM:reg (r, w)            ModRM:r/m (r)                     NA                            NA
   RVM            ModRM:reg (w)               VEX.vvvv (r)                ModRM:r/m (r)                      NA
   FVM            ModRM:reg (w)              EVEX.vvvv (r)                ModRM:r/m (r)                      NA


Description
Performs a SIMD add of the packed signed integers from the source operand (second operand) and the destination
operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with signed saturation, as described in the following paragraphs.
(V)PADDSB performs a SIMD add of the packed signed integers with saturation from the first source operand and
second source operand and stores the packed integer results in the destination operand. When an individual byte
result is beyond the range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value
of 7FH or 80H, respectively, is written to the destination operand.
(V)PADDSW performs a SIMD add of the packed signed word integers with saturation from the first source operand
and second source operand and stores the packed integer results in the destination operand. When an individual
word result is beyond the range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the satu-
rated value of 7FFFH or 8000H, respectively, is written to the destination operand.
EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an
ZMM/YMM/XMM register or a memory location. The destination operand is an ZMM/YMM/XMM register.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128) of
the corresponding register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.

Operation
PADDSB (with 64-bit operands)
  DEST[7:0] <- SaturateToSignedByte(DEST[7:0] + SRC (7:0]);
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToSignedByte(DEST[63:56] + SRC[63:56] );

PADDSB (with 128-bit operands)
  DEST[7:0] <-SaturateToSignedByte (DEST[7:0] + SRC[7:0]);
  (* Repeat add operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToSignedByte (DEST[111:120] + SRC[127:120]);

VPADDSB (VEX.128 encoded version)
  DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat subtract operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);
  DEST[VLMAX-1:128] <- 0

VPADDSB (VEX.256 encoded version)
  DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat add operation for 2nd through 31st bytes *)
  DEST[255:248]<- SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);




VPADDSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- SaturateToSignedByte (SRC1[i+7:i] + SRC2[i+7:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PADDSW (with 64-bit operands)
  DEST[15:0] <- SaturateToSignedWord(DEST[15:0] + SRC[15:0] );
  (* Repeat add operation for 2nd and 7th words *)
  DEST[63:48] <- SaturateToSignedWord(DEST[63:48] + SRC[63:48] );

PADDSW (with 128-bit operands)
  DEST[15:0] <- SaturateToSignedWord (DEST[15:0] + SRC[15:0]);
  (* Repeat add operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToSignedWord (DEST[127:112] + SRC[127:112]);

VPADDSW (VEX.128 encoded version)
  DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat subtract operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);
  DEST[VLMAX-1:128] <- 0

VPADDSW (VEX.256 encoded version)
  DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat add operation for 2nd through 15th words *)
  DEST[255:240] <- SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])

VPADDSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- SaturateToSignedWord (SRC1[i+15:i] + SRC2[i+15:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0




Intel C/C++ Compiler Intrinsic Equivalents
PADDSB:         __m64 _mm_adds_pi8(__m64 m1, __m64 m2)
(V)PADDSB:      __m128i _mm_adds_epi8 ( __m128i a, __m128i b)
VPADDSB:        __m256i _mm256_adds_epi8 ( __m256i a, __m256i b)
PADDSW:         __m64 _mm_adds_pi16(__m64 m1, __m64 m2)
(V)PADDSW:      __m128i _mm_adds_epi16 ( __m128i a, __m128i b)
VPADDSW:   __m256i _mm256_adds_epi16 ( __m256i a, __m256i b)
VPADDSB__m512i _mm512_adds_epi8 ( __m512i a, __m512i b)
VPADDSW__m512i _mm512_adds_epi16 ( __m512i a, __m512i b)
VPADDSB__m512i _mm512_mask_adds_epi8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDSW__m512i _mm512_mask_adds_epi16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDSB__m512i _mm512_maskz_adds_epi8 (__mmask64 m, __m512i a, __m512i b)
VPADDSW__m512i _mm512_maskz_adds_epi16 (__mmask32 m, __m512i a, __m512i b)
VPADDSB__m256i _mm256_mask_adds_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDSW__m256i _mm256_mask_adds_epi16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDSB__m256i _mm256_maskz_adds_epi8 (__mmask32 m, __m256i a, __m256i b)
VPADDSW__m256i _mm256_maskz_adds_epi16 (__mmask16 m, __m256i a, __m256i b)
VPADDSB__m128i _mm_mask_adds_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDSW__m128i _mm_mask_adds_epi16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDSB__m128i _mm_maskz_adds_epi8 (__mmask16 m, __m128i a, __m128i b)
VPADDSW__m128i _mm_maskz_adds_epi16 (__mmask8 m, __m128i a, __m128i b)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PADDUSB
description:
PADDUSB/PADDUSW-Add Packed Unsigned Integers with Unsigned Saturation
Opcode/                                             Op/   64/32 bit     CPUID        Description
Instruction                                         En    Mode          Feature Flag
                                                          Support
0F DC /r1                                           RM    V/V           MMX          Add packed unsigned byte integers from
PADDUSB mm, mm/m64                                                                   mm/m64 and mm and saturate the results.

66 0F DC /r                                         RM    V/V           SSE2         Add packed unsigned byte integers from
PADDUSB xmm1, xmm2/m128                                                              xmm2/m128 and xmm1 saturate the results.

0F DD /r1                                           RM    V/V           MMX          Add packed unsigned word integers from
PADDUSW mm, mm/m64                                                                   mm/m64 and mm and saturate the results.

66 0F DD /r                                         RM    V/V           SSE2         Add packed unsigned word integers from
PADDUSW xmm1, xmm2/m128                                                              xmm2/m128 to xmm1 and saturate the
                                                                                     results.
VEX.NDS.128.660F.WIG DC /r                          RVM V/V             AVX          Add packed unsigned byte integers from
VPADDUSB xmm1, xmm2, xmm3/m128                                                       xmm3/m128 to xmm2 and saturate the
                                                                                     results.
VEX.NDS.128.66.0F.WIG DD /r                         RVM V/V             AVX          Add packed unsigned word integers from
VPADDUSW xmm1, xmm2, xmm3/m128                                                       xmm3/m128 to xmm2 and saturate the
                                                                                     results.
VEX.NDS.256.66.0F.WIG DC /r                         RVM V/V             AVX2         Add packed unsigned byte integers from
VPADDUSB ymm1, ymm2, ymm3/m256                                                       ymm2, and ymm3/m256 and store the
                                                                                     saturated results in ymm1.
VEX.NDS.256.66.0F.WIG DD /r                         RVM V/V             AVX2         Add packed unsigned word integers from
VPADDUSW ymm1, ymm2, ymm3/m256                                                       ymm2, and ymm3/m256 and store the
                                                                                     saturated results in ymm1.
EVEX.NDS.128.66.0F.WIG DC /r                        FVM V/V             AVX512VL     Add packed unsigned byte integers from
VPADDUSB xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW     xmm2, and xmm3/m128 and store the
                                                                                     saturated results in xmm1 under writemask
                                                                                     k1.
EVEX.NDS.256.66.0F.WIG DC /r                        FVM V/V             AVX512VL     Add packed unsigned byte integers from
VPADDUSB ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW     ymm2, and ymm3/m256 and store the
                                                                                     saturated results in ymm1 under writemask
                                                                                     k1.
EVEX.NDS.512.66.0F.WIG DC /r                        FVM V/V             AVX512BW     Add packed unsigned byte integers from
VPADDUSB zmm1 {k1}{z}, zmm2, zmm3/m512                                               zmm2, and zmm3/m512 and store the
                                                                                     saturated results in zmm1 under writemask
                                                                                     k1.
EVEX.NDS.128.66.0F.WIG DD /r                        FVM V/V             AVX512VL     Add packed unsigned word integers from
VPADDUSW xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW     xmm2, and xmm3/m128 and store the
                                                                                     saturated results in xmm1 under writemask
                                                                                     k1.
EVEX.NDS.256.66.0F.WIG DD /r                        FVM V/V             AVX512VL     Add packed unsigned word integers from
VPADDUSW ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW     ymm2, and ymm3/m256 and store the
                                                                                     saturated results in ymm1 under writemask
                                                                                     k1.





EVEX.NDS.512.66.0F.WIG DD /r                       FVM V/V             AVX512BW       Add packed unsigned word integers from
VPADDUSW zmm1 {k1}{z}, zmm2, zmm3/m512                                                zmm2, and zmm3/m512 and store the
                                                                                      saturated results in zmm1 under writemask
                                                                                      k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                      Operand 3                      Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                        NA                             NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                   ModRM:r/m (r)                       NA
   FVM            ModRM:reg (w)                EVEX.vvvv (r)                   ModRM:r/m (r)                       NA


Description
Performs a SIMD add of the packed unsigned integers from the source operand (second operand) and the destina-
tion operand (first operand), and stores the packed integer results in the destination operand. See Figure 9-4 in the
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with unsigned saturation, as described in the following paragraphs.
(V)PADDUSB performs a SIMD add of the packed unsigned integers with saturation from the first source operand
and second source operand and stores the packed integer results in the destination operand. When an individual
byte result is beyond the range of an unsigned byte integer (that is, greater than FFH), the saturated value of FFH
is written to the destination operand.
(V)PADDUSW performs a SIMD add of the packed unsigned word integers with saturation from the first source
operand and second source operand and stores the packed integer results in the destination operand. When an
individual word result is beyond the range of an unsigned word integer (that is, greater than FFFFH), the saturated
value of FFFFH is written to the destination operand.
EVEX encoded versions: The first source operand is an ZMM/YMM/XMM register. The second source operand is an
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination is an ZMM/YMM/XMM register.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 encoded version: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding destination register destination are zeroed.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.

Operation
PADDUSB (with 64-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]

PADDUSB (with 128-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);
  (* Repeat add operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);





VPADDUSB (VEX.128 encoded version)
  DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat subtract operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);
  DEST[VLMAX-1:128] <- 0

VPADDUSB (VEX.256 encoded version)
  DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat add operation for 2nd through 31st bytes *)
  DEST[255:248]<- SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);

PADDUSW (with 64-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );
  (* Repeat add operation for 2nd and 3rd words *)
  DEST[63:48] <- SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );

PADDUSW (with 128-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);
  (* Repeat add operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);

VPADDUSW (VEX.128 encoded version)
  DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat subtract operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);
  DEST[VLMAX-1:128] <- 0

VPADDUSW (VEX.256 encoded version)
  DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat add operation for 2nd through 15th words *)
  DEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])

VPADDUSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- SaturateToUnsignedByte (SRC1[i+7:i] + SRC2[i+7:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPADDUSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*



        THEN DEST[i+15:i] <- SaturateToUnsignedWord (SRC1[i+15:i] + SRC2[i+15:i])
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+15:i] remains unchanged*
                 ELSE *zeroing-masking*              ; zeroing-masking
                     DEST[i+15:i] = 0
            FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
PADDUSB:        __m64 _mm_adds_pu8(__m64 m1, __m64 m2)
PADDUSW:        __m64 _mm_adds_pu16(__m64 m1, __m64 m2)
(V)PADDUSB:     __m128i _mm_adds_epu8 ( __m128i a, __m128i b)
(V)PADDUSW:     __m128i _mm_adds_epu16 ( __m128i a, __m128i b)
VPADDUSB:       __m256i _mm256_adds_epu8 ( __m256i a, __m256i b)
VPADDUSW:   __m256i _mm256_adds_epu16 ( __m256i a, __m256i b)
VPADDUSB__m512i _mm512_adds_epu8 ( __m512i a, __m512i b)
VPADDUSW__m512i _mm512_adds_epu16 ( __m512i a, __m512i b)
VPADDUSB__m512i _mm512_mask_adds_epu8 ( __m512i s, __mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_mask_adds_epu16 ( __m512i s, __mmask32 m, __m512i a, __m512i b)
VPADDUSB__m512i _mm512_maskz_adds_epu8 (__mmask64 m, __m512i a, __m512i b)
VPADDUSW__m512i _mm512_maskz_adds_epu16 (__mmask32 m, __m512i a, __m512i b)
VPADDUSB__m256i _mm256_mask_adds_epu8 (__m256i s, __mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_mask_adds_epu16 (__m256i s, __mmask16 m, __m256i a, __m256i b)
VPADDUSB__m256i _mm256_maskz_adds_epu8 (__mmask32 m, __m256i a, __m256i b)
VPADDUSW__m256i _mm256_maskz_adds_epu16 (__mmask16 m, __m256i a, __m256i b)
VPADDUSB__m128i _mm_mask_adds_epu8 (__m128i s, __mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_mask_adds_epu16 (__m128i s, __mmask8 m, __m128i a, __m128i b)
VPADDUSB__m128i _mm_maskz_adds_epu8 (__mmask16 m, __m128i a, __m128i b)
VPADDUSW__m128i _mm_maskz_adds_epu16 (__mmask8 m, __m128i a, __m128i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PALIGNR
description:
PALIGNR - Packed Align Right
Opcode/                                          Op/    64/32 bit   CPUID        Description
Instruction                                      En     Mode        Feature
                                                        Support     Flag
0F 3A 0F /r ib1                                  RMI    V/V         SSSE3        Concatenate destination and source operands,
PALIGNR mm1, mm2/m64, imm8                                                       extract byte-aligned result shifted to the right by
                                                                                 constant value in imm8 into mm1.
66 0F 3A 0F /r ib                                RMI    V/V         SSSE3        Concatenate destination and source operands,
PALIGNR xmm1, xmm2/m128, imm8                                                    extract byte-aligned result shifted to the right by
                                                                                 constant value in imm8 into xmm1.
VEX.NDS.128.66.0F3A.WIG 0F /r ib                 RVMI V/V           AVX          Concatenate xmm2 and xmm3/m128, extract
VPALIGNR xmm1, xmm2, xmm3/m128, imm8                                             byte aligned result shifted to the right by
                                                                                 constant value in imm8 and result is stored in
                                                                                 xmm1.
VEX.NDS.256.66.0F3A.WIG 0F /r ib                 RVMI V/V           AVX2         Concatenate pairs of 16 bytes in ymm2 and
VPALIGNR ymm1, ymm2, ymm3/m256, imm8                                             ymm3/m256 into 32-byte intermediate result,
                                                                                 extract byte-aligned, 16-byte result shifted to
                                                                                 the right by constant values in imm8 from each
                                                                                 intermediate result, and two 16-byte results are
                                                                                 stored in ymm1.
EVEX.NDS.128.66.0F3A.WIG 0F /r ib                FVM    V/V         AVX512VL Concatenate xmm2 and xmm3/m128 into a 32-
VPALIGNR xmm1 {k1}{z}, xmm2, xmm3/m128,                             AVX512BW byte intermediate result, extract byte aligned
imm8                                                                         result shifted to the right by constant value in
                                                                             imm8 and result is stored in xmm1.
EVEX.NDS.256.66.0F3A.WIG 0F /r ib                FVM    V/V         AVX512VL Concatenate pairs of 16 bytes in ymm2 and
VPALIGNR ymm1 {k1}{z}, ymm2, ymm3/m256,                             AVX512BW ymm3/m256 into 32-byte intermediate result,
imm8                                                                         extract byte-aligned, 16-byte result shifted to
                                                                             the right by constant values in imm8 from each
                                                                             intermediate result, and two 16-byte results are
                                                                             stored in ymm1.
EVEX.NDS.512.66.0F3A.WIG 0F /r ib                FVM    V/V         AVX512BW Concatenate pairs of 16 bytes in zmm2 and
VPALIGNR zmm1 {k1}{z}, zmm2, zmm3/m512,                                      zmm3/m512 into 32-byte intermediate result,
imm8                                                                         extract byte-aligned, 16-byte result shifted to
                                                                             the right by constant values in imm8 from each
                                                                             intermediate result, and four 16-byte results are
                                                                             stored in zmm1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En               Operand 1                 Operand 2                     Operand 3                       Operand 4
    RMI             ModRM:reg (r, w)            ModRM:r/m (r)                     imm8                             NA
   RVMI             ModRM:reg (w)               VEX.vvvv (r)                  ModRM:r/m (r)                      imm8
    FVM             ModRM:reg (w)               EVEX.vvvv (r)                 ModRM:r/m (r)                        NA


Description
(V)PALIGNR concatenates the destination operand (the first operand) and the source operand (the second
operand) into an intermediate composite, shifts the composite at byte granularity to the right by a constant imme-
diate, and extracts the right-aligned result into the destination. The first and the second operands can be an MMX,



XMM or a YMM register. The immediate value is considered unsigned. Immediate shift counts larger than the 2L
(i.e. 32 for 128-bit operands, or 16 for 64-bit operands) produce a zero result. Both operands can be MMX regis-
ters, XMM registers or YMM registers. When the source operand is a 128-bit memory operand, the operand must
be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded by VEX/EVEX prefix, use the REX prefix to access additional registers.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
EVEX.512 encoded version: The first source operand is a ZMM register and contains four 16-byte blocks. The
second source operand is a ZMM register or a 512-bit memory location containing four 16-byte block. The destina-
tion operand is a ZMM register and contain four 16-byte results. The imm8[7:0] is the common shift count
used for each of the four successive 16-byte block sources. The low 16-byte block of the two source operands
produce the low 16-byte result of the destination operand, the high 16-byte block of the two source operands
produce the high 16-byte result of the destination operand and so on for the blocks in the middle.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register and contains two 16-byte
blocks. The second source operand is a YMM register or a 256-bit memory location containing two 16-byte block.
The destination operand is a YMM register and contain two 16-byte results. The imm8[7:0] is the common shift
count used for the two lower 16-byte block sources and the two upper 16-byte block sources. The low 16-byte
block of the two source operands produce the low 16-byte result of the destination operand, the high 16-byte block
of the two source operands produce the high 16-byte result of the destination operand. The upper bits (MAX_VL-
1:256) of the corresponding ZMM register destination are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding ZMM register destination are zeroed.
Concatenation is done with 128-bit data in the first and second source operand for both 128-bit and 256-bit
instructions. The high 128-bits of the intermediate composite 256-bit result came from the 128-bit data from the
first source operand; the low 128-bits of the intermediate result came from the 128-bit data of the second source
operand.
Note: VEX.L must be 0, otherwise the instruction will #UD.


                                      127                          0 127                           0

                             SRC1                                                                      SRC2


                                                                                             Imm8[7:0]*8
                       255                           128 255                         128

                SRC1                                                                   SRC2


                                                                               Imm8[7:0]*8

                                255                            128 127                         0

                         DEST                                                                      DEST




                                      Figure 4-7. 256-bit VPALIGN Instruction Operation

Operation
PALIGNR (with 64-bit operands)
  temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)
  DEST[63:0] = temp1[63:0]





PALIGNR (with 128-bit operands)
temp1[255:0] <- ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);
DEST[127:0] <- temp1[127:0]
DEST[VLMAX-1:128] (Unmodified)

VPALIGNR (VEX.128 encoded version)
temp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);
DEST[127:0] <- temp1[127:0]
DEST[VLMAX-1:128] <- 0

VPALIGNR (VEX.256 encoded version)
temp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);
DEST[127:0] <- temp1[127:0]
temp1[255:0] <- ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);
DEST[MAX_VL-1:128] <- temp1[127:0]

VPALIGNR (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR l <- 0 TO VL-1 with increments of 128
   temp1[255:0] <- ((SRC1[l+127:l] << 128) OR SRC2[l+127:l])>>(imm8[7:0]*8);
   TMP_DEST[l+127:l] <- temp1[127:0]
ENDFOR;

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- TMP_DEST[i+7:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
PALIGNR:         __m64 _mm_alignr_pi8 (__m64 a, __m64 b, int n)
(V)PALIGNR:      __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int n)
VPALIGNR:     __m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int n)
VPALIGNR __m512i _mm512_alignr_epi8 (__m512i a, __m512i b, const int n)
VPALIGNR __m512i _mm512_mask_alignr_epi8 (__m512i s, __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m512i _mm512_maskz_alignr_epi8 ( __mmask64 m, __m512i a, __m512i b, const int n)
VPALIGNR __m256i _mm256_mask_alignr_epi8 (__m256i s, __mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m256i _mm256_maskz_alignr_epi8 (__mmask32 m, __m256i a, __m256i b, const int n)
VPALIGNR __m128i _mm_mask_alignr_epi8 (__m128i s, __mmask16 m, __m128i a, __m128i b, const int n)
VPALIGNR __m128i _mm_maskz_alignr_epi8 (__mmask16 m, __m128i a, __m128i b, const int n)

SIMD Floating-Point Exceptions
None.




Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PAND
description:
PAND-Logical AND
Opcode/                                            Op/   64/32 bit   CPUID        Description
Instruction                                        En    Mode        Feature Flag
                                                         Support
0F DB /r1                                          RM    V/V         MMX            Bitwise AND mm/m64 and mm.
PAND mm, mm/m64
66 0F DB /r                                        RM    V/V         SSE2           Bitwise AND of xmm2/m128 and xmm1.
PAND xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG DB /r                        RVM V/V           AVX            Bitwise AND of xmm3/m128 and xmm.
VPAND xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG DB /r                        RVM V/V           AVX2           Bitwise AND of ymm2, and ymm3/m256 and
VPAND ymm1, ymm2, ymm3/.m256                                                        store result in ymm1.

EVEX.NDS.128.66.0F.W0 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed doubleword integers in
VPANDD xmm1 {k1}{z}, xmm2,                                           AVX512F        xmm2 and xmm3/m128/m32bcst and store
xmm3/m128/m32bcst                                                                   result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed doubleword integers in
VPANDD ymm1 {k1}{z}, ymm2,                                           AVX512F        ymm2 and ymm3/m256/m32bcst and store
ymm3/m256/m32bcst                                                                   result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 DB /r                        FV    V/V         AVX512F        Bitwise AND of packed doubleword integers in
VPANDD zmm1 {k1}{z}, zmm2,                                                          zmm2 and zmm3/m512/m32bcst and store
zmm3/m512/m32bcst                                                                   result in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.W1 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed quadword integers in
VPANDQ xmm1 {k1}{z}, xmm2,                                           AVX512F        xmm2 and xmm3/m128/m64bcst and store
xmm3/m128/m64bcst                                                                   result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 DB /r                        FV    V/V         AVX512VL       Bitwise AND of packed quadword integers in
VPANDQ ymm1 {k1}{z}, ymm2,                                           AVX512F        ymm2 and ymm3/m256/m64bcst and store
ymm3/m256/m64bcst                                                                   result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 DB /r                        FV    V/V         AVX512F        Bitwise AND of packed quadword integers in
VPANDQ zmm1 {k1}{z}, zmm2,                                                          zmm2 and zmm3/m512/m64bcst and store
zmm3/m512/m64bcst                                                                   result in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En              Operand 1                   Operand 2                   Operand 3                     Operand 4
    RM             ModRM:reg (r, w)             ModRM:r/m (r)                     NA                            NA
   RVM             ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                      NA
    FV             ModRM:reg (w)                EVEX.vvvv (r)                ModRM:r/m (r)                      NA


Description
Performs a bitwise logical AND operation on the first source operand and second source operand and stores the
result in the destination operand. Each bit of the result is set to 1 if the corresponding bits of the first and second
operands are 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).





Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.
VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.

Operation
PAND (64-bit operand)
DEST <- DEST AND SRC


PAND (128-bit Legacy SSE version)
DEST <- DEST AND SRC
DEST[VLMAX-1:128] (Unmodified)

VPAND (VEX.128 encoded version)
DEST <- SRC1 AND SRC2
DEST[VLMAX-1:128] <- 0

VPAND (VEX.256 encoded instruction)
DEST[255:0] <- (SRC1[255:0] AND SRC2[255:0])
DEST[VLMAX-1:256] <- 0

VPANDD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[31:0]
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE AND SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPANDQ (EVEX encoded versions)



(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[63:0]
                    ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE AND SRC2[i+63:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPANDD __m512i _mm512_and_epi32( __m512i a, __m512i b);
VPANDD __m512i _mm512_mask_and_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDD __m512i _mm512_maskz_and_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_and_epi64( __m512i a, __m512i b);
VPANDQ __m512i _mm512_mask_and_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDQ __m512i _mm512_maskz_and_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_and_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_and_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_and_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_and_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m256i _mm256_mask_and_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_and_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_and_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_and_epi64( __mmask8 k, __m128i a, __m128i b);
PAND: __m64 _mm_and_si64 (__m64 m1, __m64 m2)
(V)PAND:__m128i _mm_and_si128 ( __m128i a, __m128i b)
VPAND:     __m256i _mm256_and_si256 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PANDN
description:
PANDN-Logical AND NOT
Opcode/                                             Op/   64/32 bit   CPUID            Description
Instruction                                         En    Mode        Feature
                                                          Support     Flag
0F DF /r1                                           RM    V/V         MMX              Bitwise AND NOT of mm/m64 and mm.
PANDN mm, mm/m64
66 0F DF /r                                         RM    V/V         SSE2             Bitwise AND NOT of xmm2/m128 and xmm1.
PANDN xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG DF /r                         RVM V/V           AVX              Bitwise AND NOT of xmm3/m128 and xmm2.
VPANDN xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG DF /r                         RVM V/V           AVX2             Bitwise AND NOT of ymm2, and ymm3/m256
VPANDN ymm1, ymm2, ymm3/m256                                                           and store result in ymm1.

EVEX.NDS.128.66.0F.W0 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed doubleword
VPANDND xmm1 {k1}{z}, xmm2,                                           AVX512F          integers in xmm2 and xmm3/m128/m32bcst
xmm3/m128/m32bcst                                                                      and store result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed doubleword
VPANDND ymm1 {k1}{z}, ymm2,                                           AVX512F          integers in ymm2 and ymm3/m256/m32bcst
ymm3/m256/m32bcst                                                                      and store result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 DF /r                         FV    V/V         AVX512F          Bitwise AND NOT of packed doubleword
VPANDND zmm1 {k1}{z}, zmm2,                                                            integers in zmm2 and zmm3/m512/m32bcst
zmm3/m512/m32bcst                                                                      and store result in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.W1 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed quadword
VPANDNQ xmm1 {k1}{z}, xmm2,                                           AVX512F          integers in xmm2 and xmm3/m128/m64bcst
xmm3/m128/m64bcst                                                                      and store result in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 DF /r                         FV    V/V         AVX512VL         Bitwise AND NOT of packed quadword
VPANDNQ ymm1 {k1}{z}, ymm2,                                           AVX512F          integers in ymm2 and ymm3/m256/m64bcst
ymm3/m256/m64bcst                                                                      and store result in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 DF /r                         FV    V/V         AVX512F          Bitwise AND NOT of packed quadword
VPANDNQ zmm1 {k1}{z}, zmm2,                                                            integers in zmm2 and zmm3/m512/m64bcst
zmm3/m512/m64bcst                                                                      and store result in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                    Operand 3                       Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                      NA                              NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                        NA
    FV            ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                        NA


Description
Performs a bitwise logical NOT operation on the first source operand, then performs bitwise AND with second
source operand and stores the result in the destination operand. Each bit of the result is set to 1 if the corre-
sponding bit in the first operand is 0 and the corresponding bit in the second operand is 1, otherwise it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).





Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are unmodified.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.
VEX.256 encoded versions: The first source operand is a YMM register. The second source operand is a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded versions: The first source operand is an XMM register. The second source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.

Operation
PANDN (64-bit operand)
DEST <- NOT(DEST) AND SRC


PANDN (128-bit Legacy SSE version)
DEST <- NOT(DEST) AND SRC
DEST[VLMAX-1:128] (Unmodified)

VPANDN (VEX.128 encoded version)
DEST <- NOT(SRC1) AND SRC2
DEST[VLMAX-1:128] <- 0

VPANDN (VEX.256 encoded instruction)
DEST[255:0] <- ((NOT SRC1[255:0]) AND SRC2[255:0])
DEST[VLMAX-1:256] <- 0

VPANDND (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[31:0])
                    ELSE DEST[i+31:i] <- ((NOT SRC1[i+31:i]) AND SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPANDNQ (EVEX encoded versions)



(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[63:0])
                    ELSE DEST[i+63:i] <- ((NOT SRC1[i+63:i]) AND SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPANDND __m512i _mm512_andnot_epi32( __m512i a, __m512i b);
VPANDND __m512i _mm512_mask_andnot_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPANDND __m512i _mm512_maskz_andnot_epi32( __mmask16 k, __m512i a, __m512i b);
VPANDND __m256i _mm256_mask_andnot_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDND __m256i _mm256_maskz_andnot_epi32( __mmask8 k, __m256i a, __m256i b);
VPANDND __m128i _mm_mask_andnot_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDND __m128i _mm_maskz_andnot_epi32( __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m512i _mm512_andnot_epi64( __m512i a, __m512i b);
VPANDNQ __m512i _mm512_mask_andnot_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m512i _mm512_maskz_andnot_epi64( __mmask8 k, __m512i a, __m512i b);
VPANDNQ __m256i _mm256_mask_andnot_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m256i _mm256_maskz_andnot_epi64( __mmask8 k, __m256i a, __m256i b);
VPANDNQ __m128i _mm_mask_andnot_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPANDNQ __m128i _mm_maskz_andnot_epi64( __mmask8 k, __m128i a, __m128i b);
PANDN: __m64 _mm_andnot_si64 (__m64 m1, __m64 m2)
(V)PANDN:__m128i _mm_andnot_si128 ( __m128i a, __m128i b)
VPANDN:       __m256i _mm256_andnot_si256 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PAUSE
description:
PAUSE-Spin Loop Hint
 Opcode                   Instruction                 Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 F3 90                    PAUSE                       NP    Valid    Valid       Gives hint to processor that improves
                                                                                 performance of spin-wait loops.



                                              Instruction Operand Encoding
   Op/En               Operand 1                Operand 2                    Operand 3                    Operand 4
    NP                    NA                          NA                        NA                            NA


Description
Improves the performance of spin-wait loops. When executing a "spin-wait loop," processors will suffer a severe
performance penalty when exiting the loop because it detects a possible memory order violation. The PAUSE
instruction provides a hint to the processor that the code sequence is a spin-wait loop. The processor uses this hint
to avoid the memory order violation in most situations, which greatly improves processor performance. For this
reason, it is recommended that a PAUSE instruction be placed in all spin-wait loops.
An additional function of the PAUSE instruction is to reduce the power consumed by a processor while executing a
spin loop. A processor can execute a spin-wait loop extremely quickly, causing the processor to consume a lot of
power while it waits for the resource it is spinning on to become available. Inserting a pause instruction in a spin-
wait loop greatly reduces the processor's power consumption.
This instruction was introduced in the Pentium 4 processors, but is backward compatible with all IA-32 processors.
In earlier IA-32 processors, the PAUSE instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon
processors implement the PAUSE instruction as a delay. The delay is finite and can be zero for some processors.
This instruction does not change the architectural state of the processor (that is, it performs essentially a delaying
no-op operation).
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
Execute_Next_Instruction(DELAY);

Numeric Exceptions
None.

Exceptions (All Operating Modes)
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: PAVGB
description:
PAVGB/PAVGW-Average Packed Integers
Opcode/                                             Op/   64/32 bit   CPUID        Description
Instruction                                         En    Mode        Feature
                                                          Support     Flag
0F E0 /r1                                           RM    V/V         SSE          Average packed unsigned byte integers from
PAVGB mm1, mm2/m64                                                                 mm2/m64 and mm1 with rounding.

66 0F E0, /r                                        RM    V/V         SSE2         Average packed unsigned byte integers from
PAVGB xmm1, xmm2/m128                                                              xmm2/m128 and xmm1 with rounding.

0F E3 /r1                                           RM    V/V         SSE          Average packed unsigned word integers from
PAVGW mm1, mm2/m64                                                                 mm2/m64 and mm1 with rounding.

66 0F E3 /r                                         RM    V/V         SSE2         Average packed unsigned word integers from
PAVGW xmm1, xmm2/m128                                                              xmm2/m128 and xmm1 with rounding.

VEX.NDS.128.66.0F.WIG E0 /r                         RVM V/V           AVX          Average packed unsigned byte integers from
VPAVGB xmm1, xmm2, xmm3/m128                                                       xmm3/m128 and xmm2 with rounding.

VEX.NDS.128.66.0F.WIG E3 /r                         RVM V/V           AVX          Average packed unsigned word integers from
VPAVGW xmm1, xmm2, xmm3/m128                                                       xmm3/m128 and xmm2 with rounding.

VEX.NDS.256.66.0F.WIG E0 /r                         RVM V/V           AVX2         Average packed unsigned byte integers from
VPAVGB ymm1, ymm2, ymm3/m256                                                       ymm2, and ymm3/m256 with rounding and
                                                                                   store to ymm1.
VEX.NDS.256.66.0F.WIG E3 /r                         RVM V/V           AVX2         Average packed unsigned word integers from
VPAVGW ymm1, ymm2, ymm3/m256                                                       ymm2, ymm3/m256 with rounding to ymm1.

EVEX.NDS.128.66.0F.WIG E0 /r                        FVM V/V           AVX512VL Average packed unsigned byte integers from
VPAVGB xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW xmm2, and xmm3/m128 with rounding and
                                                                               store to xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG E0 /r                        FVM V/V           AVX512VL Average packed unsigned byte integers from
VPAVGB ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW ymm2, and ymm3/m256 with rounding and
                                                                               store to ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG E0 /r                        FVM V/V           AVX512BW Average packed unsigned byte integers from
VPAVGB zmm1 {k1}{z}, zmm2, zmm3/m512                                           zmm2, and zmm3/m512 with rounding and
                                                                               store to zmm1 under writemask k1.
EVEX.NDS.128.66.0F.WIG E3 /r                        FVM V/V           AVX512VL Average packed unsigned word integers from
VPAVGW xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW xmm2, xmm3/m128 with rounding to xmm1
                                                                               under writemask k1.
EVEX.NDS.256.66.0F.WIG E3 /r                        FVM V/V           AVX512VL Average packed unsigned word integers from
VPAVGW ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW ymm2, ymm3/m256 with rounding to ymm1
                                                                               under writemask k1.
EVEX.NDS.512.66.0F.WIG E3 /r                        FVM V/V           AVX512BW Average packed unsigned word integers from
VPAVGW zmm1 {k1}{z}, zmm2, zmm3/m512                                           zmm2, zmm3/m512 with rounding to zmm1
                                                                               under writemask k1.

NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                    Operand 2                     Operand 3                     Operand 4
    RM          ModRM:reg (r, w)              ModRM:r/m (r)                      NA                             NA




  Op/En             Operand 1                     Operand 2                     Operand 3                Operand 4
   RVM            ModRM:reg (w)                  VEX.vvvv (r)                 ModRM:r/m (r)                  NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                  NA

Description
Performs a SIMD average of the packed unsigned integers from the source operand (second operand) and the
destination operand (first operand), and stores the results in the destination operand. For each corresponding pair
of data elements in the first and second operands, the elements are added together, a 1 is added to the temporary
sum, and that result is shifted right one bit position.
The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW instruction operates on packed
unsigned words.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source operand is an XMM register. The second operand can be an XMM
register or an 128-bit memory location. The destination is not distinct from the first source XMM register and the
upper bits (MAX_VL-1:128) of the corresponding register destination are unmodified.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register or a 512-bit memory location. The destination operand is a ZMM register.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits
(MAX_VL-1:128) of the corresponding register destination are zeroed.

Operation
PAVGB (with 64-bit operands)
  DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 6 *)
  DEST[63:56] <- (SRC[63:56] + DEST[63:56] + 1) >> 1;

PAVGW (with 64-bit operands)
  DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
  (* Repeat operation performed for words 2 and 3 *)
  DEST[63:48] <- (SRC[63:48] + DEST[63:48] + 1) >> 1;

PAVGB (with 128-bit operands)
  DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 14 *)
  DEST[127:120] <- (SRC[127:120] + DEST[127:120] + 1) >> 1;

PAVGW (with 128-bit operands)
  DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
  (* Repeat operation performed for words 2 through 6 *)
  DEST[127:112] <- (SRC[127:112] + DEST[127:112] + 1) >> 1;





VPAVGB (VEX.128 encoded version)
  DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1;
  (* Repeat operation performed for bytes 2 through 15 *)
  DEST[127:120] <- (SRC1[127:120] + SRC2[127:120] + 1) >> 1
  DEST[VLMAX-1:128] <- 0

VPAVGW (VEX.128 encoded version)
  DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1;
  (* Repeat operation performed for 16-bit words 2 through 7 *)
  DEST[127:112] <- (SRC1[127:112] + SRC2[127:112] + 1) >> 1
  DEST[VLMAX-1:128] <- 0

VPAVGB (VEX.256 encoded instruction)
  DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 31)
  DEST[255:248] <- (SRC1[255:248] + SRC2[255:248] + 1) >> 1;

VPAVGW (VEX.256 encoded instruction)
    DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
    (* Repeat operation performed for words 2 through 15)
    DEST[255:14]) <- (SRC1[255:240] + SRC2[255:240] + 1) >> 1;
VPAVGB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- (SRC1[i+7:i] + SRC2[i+7:i] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE *zeroing-masking*               ; zeroing-masking
                        DEST[i+7:i] = 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPAVGW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- (SRC1[i+15:i] + SRC2[i+15:i] + 1) >> 1
                                          ; (* Temp sum before shifting is 17 bits *)
         ELSE
               IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*               ; zeroing-masking
                        DEST[i+15:i] = 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0




Intel C/C++ Compiler Intrinsic Equivalents
VPAVGB __m512i _mm512_avg_epu8( __m512i a, __m512i b);
VPAVGW __m512i _mm512_avg_epu16( __m512i a, __m512i b);
VPAVGB __m512i _mm512_mask_avg_epu8(__m512i s, __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_mask_avg_epu16(__m512i s, __mmask32 m, __m512i a, __m512i b);
VPAVGB __m512i _mm512_maskz_avg_epu8( __mmask64 m, __m512i a, __m512i b);
VPAVGW __m512i _mm512_maskz_avg_epu16( __mmask32 m, __m512i a, __m512i b);
VPAVGB __m256i _mm256_mask_avg_epu8(__m256i s, __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_mask_avg_epu16(__m256i s, __mmask16 m, __m256i a, __m256i b);
VPAVGB __m256i _mm256_maskz_avg_epu8( __mmask32 m, __m256i a, __m256i b);
VPAVGW __m256i _mm256_maskz_avg_epu16( __mmask16 m, __m256i a, __m256i b);
VPAVGB __m128i _mm_mask_avg_epu8(__m128i s, __mmask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_mask_avg_epu16(__m128i s, __mmask8 m, __m128i a, __m128i b);
VPAVGB __m128i _mm_maskz_avg_epu8( __mmask16 m, __m128i a, __m128i b);
VPAVGW __m128i _mm_maskz_avg_epu16( __mmask8 m, __m128i a, __m128i b);
PAVGB: __m64 _mm_avg_pu8 (__m64 a, __m64 b)
PAVGW: __m64 _mm_avg_pu16 (__m64 a, __m64 b)
(V)PAVGB: __m128i _mm_avg_epu8 ( __m128i a, __m128i b)
(V)PAVGW: __m128i _mm_avg_epu16 ( __m128i a, __m128i b)
VPAVGB:        __m256i _mm256_avg_epu8 ( __m256i a, __m256i b)
VPAVGW:        __m256i _mm256_avg_epu16 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PBLENDVB
description:
PBLENDVB - Variable Blend Packed Bytes
Opcode/                                               Op/        64/32 bit   CPUID        Description
Instruction                                           En         Mode        Feature
                                                                 Support     Flag
66 0F 38 10 /r                                        RM         V/V         SSE4_1       Select byte values from xmm1 and
PBLENDVB xmm1, xmm2/m128, <XMM0>                                                          xmm2/m128 from mask specified in the high
                                                                                          bit of each byte in XMM0 and store the
                                                                                          values into xmm1.
VEX.NDS.128.66.0F3A.W0 4C /r /is4                     RVMR V/V               AVX          Select byte values from xmm2 and
VPBLENDVB xmm1, xmm2, xmm3/m128, xmm4                                                     xmm3/m128 using mask bits in the specified
                                                                                          mask register, xmm4, and store the values
                                                                                          into xmm1.
VEX.NDS.256.66.0F3A.W0 4C /r /is4                     RVMR V/V               AVX2         Select byte values from ymm2 and
VPBLENDVB ymm1, ymm2, ymm3/m256, ymm4                                                     ymm3/m256 from mask specified in the high
                                                                                          bit of each byte in ymm4 and store the
                                                                                          values into ymm1.



                                                 Instruction Operand Encoding
   Op/En            Operand 1                      Operand 2                        Operand 3                       Operand 4
    RM           ModRM:reg (r, w)                ModRM:r/m (r)                       <XMM0>                            NA
   RVMR           ModRM:reg (w)                   VEX.vvvv (r)                     ModRM:r/m (r)                    imm8[7:4]


Description
Conditionally copies byte elements from the source operand (second operand) to the destination operand (first
operand) depending on mask bits defined in the implicit third register argument, XMM0. The mask bits are the most
significant bit in each byte element of the XMM0 register.
If a mask bit is "1", then the corresponding byte element in the source operand is copied to the destination, else
the byte element in the destination operand is left unchanged.
The register assignment of the implicit third operand is defined to be the architectural register XMM0.
128-bit Legacy SSE version: The first source operand and the destination operand is the same. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. The mask register operand is implicitly defined
to be the architectural register XMM0. An attempt to execute PBLENDVB with a VEX prefix will cause #UD.
VEX.128 encoded version: The first source operand and the destination operand are XMM registers. The second
source operand is an XMM register or 128-bit memory location. The mask operand is the third source register, and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored. The upper bits (VLMAX-1:128) of the corresponding YMM register (destination register) are zeroed. VEX.L
must be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction will #UD.
VEX.256 encoded version: The first source operand and the destination operand are YMM registers. The second
source operand is an YMM register or 256-bit memory location. The third source register is an YMM register and
encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In 32-bit mode, imm8[7] is
ignored.
VPBLENDVB permits the mask to be any XMM or YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the
mask and do not support non-destructive destination operation. An attempt to execute PBLENDVB encoded with a
VEX prefix will cause a #UD exception.

Operation
PBLENDVB (128-bit Legacy SSE version)
MASK <- XMM0
IF (MASK[7] = 1) THEN DEST[7:0] <- SRC[7:0];
ELSE DEST[7:0] <- DEST[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] <- SRC[15:8];


ELSE DEST[15:8] <- DEST[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] <- SRC[23:16]
ELSE DEST[23:16] <- DEST[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] <- SRC[31:24]
ELSE DEST[31:24] <- DEST[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] <- SRC[39:32]
ELSE DEST[39:32] <- DEST[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] <- SRC[47:40]
ELSE DEST[47:40] <- DEST[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] <- SRC[55:48]
ELSE DEST[55:48] <- DEST[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] <- SRC[63:56]
ELSE DEST[63:56] <- DEST[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] <- SRC[71:64]
ELSE DEST[71:64] <- DEST[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] <- SRC[79:72]
ELSE DEST[79:72] <- DEST[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] <- SRC[87:80]
ELSE DEST[87:80] <- DEST[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] <- SRC[95:88]
ELSE DEST[95:88] <- DEST[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] <- SRC[103:96]
ELSE DEST[103:96] <- DEST[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] <- SRC[111:104]
ELSE DEST[111:104] <- DEST[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] <- SRC[119:112]
ELSE DEST[119:112] <- DEST[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] <- SRC[127:120]
ELSE DEST[127:120] <- DEST[127:120])
DEST[VLMAX-1:128] (Unmodified)

VPBLENDVB (VEX.128 encoded version)
MASK <- SRC3
IF (MASK[7] = 1) THEN DEST[7:0] <- SRC2[7:0];
ELSE DEST[7:0] <- SRC1[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] <- SRC2[15:8];
ELSE DEST[15:8] <- SRC1[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] <- SRC2[23:16]
ELSE DEST[23:16] <- SRC1[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] <- SRC2[31:24]
ELSE DEST[31:24] <- SRC1[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] <- SRC2[39:32]
ELSE DEST[39:32] <- SRC1[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] <- SRC2[47:40]
ELSE DEST[47:40] <- SRC1[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] <- SRC2[55:48]
ELSE DEST[55:48] <- SRC1[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] <- SRC2[63:56]
ELSE DEST[63:56] <- SRC1[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] <- SRC2[71:64]
ELSE DEST[71:64] <- SRC1[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] <- SRC2[79:72]
ELSE DEST[79:72] <- SRC1[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] <- SRC2[87:80]



ELSE DEST[87:80] <- SRC1[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] <- SRC2[95:88]
ELSE DEST[95:88] <- SRC1[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] <- SRC2[103:96]
ELSE DEST[103:96] <- SRC1[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] <- SRC2[111:104]
ELSE DEST[111:104] <- SRC1[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] <- SRC2[119:112]
ELSE DEST[119:112] <- SRC1[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] <- SRC2[127:120]
ELSE DEST[127:120] <- SRC1[127:120])
DEST[VLMAX-1:128] <- 0

VPBLENDVB (VEX.256 encoded version)
MASK <- SRC3
IF (MASK[7] == 1) THEN DEST[7:0] <- SRC2[7:0];
ELSE DEST[7:0] <- SRC1[7:0];
IF (MASK[15] == 1) THEN DEST[15:8] <-SRC2[15:8];
ELSE DEST[15:8] <- SRC1[15:8];
IF (MASK[23] == 1) THEN DEST[23:16] <-SRC2[23:16]
ELSE DEST[23:16] <- SRC1[23:16];
IF (MASK[31] == 1) THEN DEST[31:24] <- SRC2[31:24]
ELSE DEST[31:24] <- SRC1[31:24];
IF (MASK[39] == 1) THEN DEST[39:32] <- SRC2[39:32]
ELSE DEST[39:32] <- SRC1[39:32];
IF (MASK[47] == 1) THEN DEST[47:40] <- SRC2[47:40]
ELSE DEST[47:40] <- SRC1[47:40];
IF (MASK[55] == 1) THEN DEST[55:48] <- SRC2[55:48]
ELSE DEST[55:48] <- SRC1[55:48];
IF (MASK[63] == 1) THEN DEST[63:56] <-SRC2[63:56]
ELSE DEST[63:56] <- SRC1[63:56];
IF (MASK[71] == 1) THEN DEST[71:64] <-SRC2[71:64]
ELSE DEST[71:64] <- SRC1[71:64];
IF (MASK[79] == 1) THEN DEST[79:72] <- SRC2[79:72]
ELSE DEST[79:72] <- SRC1[79:72];
IF (MASK[87] == 1) THEN DEST[87:80] <- SRC2[87:80]
ELSE DEST[87:80] <- SRC1[87:80];
IF (MASK[95] == 1) THEN DEST[95:88] <- SRC2[95:88]
ELSE DEST[95:88] <- SRC1[95:88];
IF (MASK[103] == 1) THEN DEST[103:96] <- SRC2[103:96]
ELSE DEST[103:96] <- SRC1[103:96];
IF (MASK[111] == 1) THEN DEST[111:104] <- SRC2[111:104]
ELSE DEST[111:104] <- SRC1[111:104];
IF (MASK[119] == 1) THEN DEST[119:112] <- SRC2[119:112]
ELSE DEST[119:112] <- SRC1[119:112];
IF (MASK[127] == 1) THEN DEST[127:120] <- SRC2[127:120]
ELSE DEST[127:120] <- SRC1[127:120])
IF (MASK[135] == 1) THEN DEST[135:128] <- SRC2[135:128];
ELSE DEST[135:128] <- SRC1[135:128];
IF (MASK[143] == 1) THEN DEST[143:136] <- SRC2[143:136];
ELSE DEST[[143:136] <- SRC1[143:136];
IF (MASK[151] == 1) THEN DEST[151:144] <- SRC2[151:144]
ELSE DEST[151:144] <- SRC1[151:144];
IF (MASK[159] == 1) THEN DEST[159:152] <- SRC2[159:152]



ELSE DEST[159:152] <- SRC1[159:152];
IF (MASK[167] == 1) THEN DEST[167:160] <- SRC2[167:160]
ELSE DEST[167:160] <- SRC1[167:160];
IF (MASK[175] == 1) THEN DEST[175:168] <- SRC2[175:168]
ELSE DEST[175:168] <- SRC1[175:168];
IF (MASK[183] == 1) THEN DEST[183:176] <- SRC2[183:176]
ELSE DEST[183:176] <- SRC1[183:176];
IF (MASK[191] == 1) THEN DEST[191:184] <- SRC2[191:184]
ELSE DEST[191:184] <- SRC1[191:184];
IF (MASK[199] == 1) THEN DEST[199:192] <- SRC2[199:192]
ELSE DEST[199:192] <- SRC1[199:192];
IF (MASK[207] == 1) THEN DEST[207:200] <- SRC2[207:200]
ELSE DEST[207:200] <- SRC1[207:200]
IF (MASK[215] == 1) THEN DEST[215:208] <- SRC2[215:208]
ELSE DEST[215:208] <- SRC1[215:208];
IF (MASK[223] == 1) THEN DEST[223:216] <- SRC2[223:216]
ELSE DEST[223:216] <- SRC1[223:216];
IF (MASK[231] == 1) THEN DEST[231:224] <- SRC2[231:224]
ELSE DEST[231:224] <- SRC1[231:224];
IF (MASK[239] == 1) THEN DEST[239:232] <- SRC2[239:232]
ELSE DEST[239:232] <- SRC1[239:232];
IF (MASK[247] == 1) THEN DEST[247:240] <- SRC2[247:240]
ELSE DEST[247:240] <- SRC1[247:240];
IF (MASK[255] == 1) THEN DEST[255:248] <- SRC2[255:248]
ELSE DEST[255:248] <- SRC1[255:248]

Intel C/C++ Compiler Intrinsic Equivalent
(V)PBLENDVB:      __m128i _mm_blendv_epi8 (__m128i v1, __m128i v2, __m128i mask);
VPBLENDVB:        __m256i _mm256_blendv_epi8 (__m256i v1, __m256i v2, __m256i mask);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                     If VEX.W = 1.






platform: x86_64
mnem: PBLENDW
description:
PBLENDW - Blend Packed Words
Opcode/                                              Op/   64/32 bit   CPUID       Description
Instruction                                          En    Mode        Feature
                                                           Support     Flag
66 0F 3A 0E /r ib                                    RMI   V/V         SSE4_1      Select words from xmm1 and xmm2/m128
PBLENDW xmm1, xmm2/m128, imm8                                                      from mask specified in imm8 and store the
                                                                                   values into xmm1.
VEX.NDS.128.66.0F3A.WIG 0E /r ib                     RVMI V/V          AVX         Select words from xmm2 and xmm3/m128
VPBLENDW xmm1, xmm2, xmm3/m128, imm8                                               from mask specified in imm8 and store the
                                                                                   values into xmm1.
VEX.NDS.256.66.0F3A.WIG 0E /r ib                     RVMI V/V          AVX2        Select words from ymm2 and ymm3/m256
VPBLENDW ymm1, ymm2, ymm3/m256, imm8                                               from mask specified in imm8 and store the
                                                                                   values into ymm1.



                                            Instruction Operand Encoding
  Op/En            Operand 1                   Operand 2                      Operand 3                   Operand 4
    RMI         ModRM:reg (r, w)             ModRM:r/m (r)                       imm8                         NA
   RVMI          ModRM:reg (w)                VEX.vvvv (r)                   ModRM:r/m (r)                   imm8


Description
Words from the source operand (second operand) are conditionally written to the destination operand (first
operand) depending on bits in the immediate operand (third operand). The immediate bits (bits 7:0) form a mask
that determines whether the corresponding word in the destination is copied from the source. If a bit in the mask,
corresponding to a word, is "1", then the word is copied, else the word element in the destination operand is
unchanged.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.

Operation
PBLENDW (128-bit Legacy SSE version)
IF (imm8[0] = 1) THEN DEST[15:0] <- SRC[15:0]
ELSE DEST[15:0] <- DEST[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] <- SRC[31:16]
ELSE DEST[31:16] <- DEST[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] <- SRC[47:32]
ELSE DEST[47:32] <- DEST[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] <- SRC[63:48]
ELSE DEST[63:48] <- DEST[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] <- SRC[79:64]
ELSE DEST[79:64] <- DEST[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] <- SRC[95:80]
ELSE DEST[95:80] <- DEST[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] <- SRC[111:96]
ELSE DEST[111:96] <- DEST[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] <- SRC[127:112]



ELSE DEST[127:112] <- DEST[127:112]

VPBLENDW (VEX.128 encoded version)
IF (imm8[0] = 1) THEN DEST[15:0] <- SRC2[15:0]
ELSE DEST[15:0] <- SRC1[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] <- SRC2[31:16]
ELSE DEST[31:16] <- SRC1[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] <- SRC2[47:32]
ELSE DEST[47:32] <- SRC1[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] <- SRC2[63:48]
ELSE DEST[63:48] <- SRC1[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] <- SRC2[79:64]
ELSE DEST[79:64] <- SRC1[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] <- SRC2[95:80]
ELSE DEST[95:80] <- SRC1[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] <- SRC2[111:96]
ELSE DEST[111:96] <- SRC1[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] <- SRC2[127:112]
ELSE DEST[127:112] <- SRC1[127:112]
DEST[VLMAX-1:128] <- 0

VPBLENDW (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[15:0] <- SRC2[15:0]
ELSE DEST[15:0] <- SRC1[15:0]
IF (imm8[1] == 1) THEN DEST[31:16] <- SRC2[31:16]
ELSE DEST[31:16] <- SRC1[31:16]
IF (imm8[2] == 1) THEN DEST[47:32] <- SRC2[47:32]
ELSE DEST[47:32] <- SRC1[47:32]
IF (imm8[3] == 1) THEN DEST[63:48] <- SRC2[63:48]
ELSE DEST[63:48] <- SRC1[63:48]
IF (imm8[4] == 1) THEN DEST[79:64] <- SRC2[79:64]
ELSE DEST[79:64] <- SRC1[79:64]
IF (imm8[5] == 1) THEN DEST[95:80] <- SRC2[95:80]
ELSE DEST[95:80] <- SRC1[95:80]
IF (imm8[6] == 1) THEN DEST[111:96] <- SRC2[111:96]
ELSE DEST[111:96] <- SRC1[111:96]
IF (imm8[7] == 1) THEN DEST[127:112] <- SRC2[127:112]
ELSE DEST[127:112] <- SRC1[127:112]
IF (imm8[0] == 1) THEN DEST[143:128] <- SRC2[143:128]
ELSE DEST[143:128] <- SRC1[143:128]
IF (imm8[1] == 1) THEN DEST[159:144] <- SRC2[159:144]
ELSE DEST[159:144] <- SRC1[159:144]
IF (imm8[2] == 1) THEN DEST[175:160] <- SRC2[175:160]
ELSE DEST[175:160] <- SRC1[175:160]
IF (imm8[3] == 1) THEN DEST[191:176] <- SRC2[191:176]
ELSE DEST[191:176] <- SRC1[191:176]
IF (imm8[4] == 1) THEN DEST[207:192] <- SRC2[207:192]
ELSE DEST[207:192] <- SRC1[207:192]
IF (imm8[5] == 1) THEN DEST[223:208] <- SRC2[223:208]
ELSE DEST[223:208] <- SRC1[223:208]
IF (imm8[6] == 1) THEN DEST[239:224] <- SRC2[239:224]
ELSE DEST[239:224] <- SRC1[239:224]
IF (imm8[7] == 1) THEN DEST[255:240] <- SRC2[255:240]
ELSE DEST[255:240] <- SRC1[255:240]



Intel C/C++ Compiler Intrinsic Equivalent
(V)PBLENDW:      __m128i _mm_blend_epi16 (__m128i v1, __m128i v2, const int mask);
VPBLENDW:        __m256i _mm256_blend_epi16 (__m256i v1, __m256i v2, const int mask)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                    If VEX.L = 1 and AVX2 = 0.






platform: x86_64
mnem: PCLMULQDQ
description:
PCLMULQDQ - Carry-Less Multiplication Quadword
 Opcode/                                                Op/    64/32 bit   CPUID       Description
 Instruction                                            En     Mode        Feature
                                                               Support     Flag
 66 0F 3A 44 /r ib                                      RMI    V/V         PCLMUL-     Carry-less multiplication of one quadword of
 PCLMULQDQ xmm1, xmm2/m128, imm8                                           QDQ         xmm1 by one quadword of xmm2/m128,
                                                                                       stores the 128-bit result in xmm1. The imme-
                                                                                       diate is used to determine which quadwords
                                                                                       of xmm1 and xmm2/m128 should be used.
 VEX.NDS.128.66.0F3A.WIG 44 /r ib                       RVMI V/V           Both PCL-   Carry-less multiplication of one quadword of
 VPCLMULQDQ xmm1, xmm2, xmm3/m128, imm8                                    MULQDQ      xmm2 by one quadword of xmm3/m128,
                                                                           and AVX     stores the 128-bit result in xmm1. The imme-
                                                                           flags       diate is used to determine which quadwords
                                                                                       of xmm2 and xmm3/m128 should be used.



                                                  Instruction Operand Encoding
     Op/En            Operand 1                     Operand2                      Operand3                      Operand4
     RMI           ModRM:reg (r, w)               ModRM:r/m (r)                      imm8                          NA
     RVMI           ModRM:reg (w)                  VEX.vvvv (r)                  ModRM:r/m (r)                    imm8


Description
Performs a carry-less multiplication of two quadwords, selected from the first source and second source operand
according to the value of the immediate byte. Bits 4 and 0 are used to select which 64-bit half of each operand to
use according to Table 4-13, other bits of the immediate byte are ignored.

                              Table 4-13. PCLMULQDQ Quadword Selection of Immediate Byte
        Imm[4]               Imm[0]                                         PCLMULQDQ Operation
                                                          1
 0                     0                     CL_MUL( SRC2 [63:0], SRC1[63:0] )
 0                     1                     CL_MUL( SRC2[63:0], SRC1[127:64] )
 1                     0                     CL_MUL( SRC2[127:64], SRC1[63:0] )
 1                     1                     CL_MUL( SRC2[127:64], SRC1[127:64] )
NOTES:
1. SRC2 denotes the second source operand, which can be a register or memory; SRC1 denotes the first source and destination oper-
   and.


 The first source operand and the destination operand are the same and must be an XMM register. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged.
Compilers and assemblers may implement the following pseudo-op syntax to simply programming and emit the
required encoding for Imm8.

                                   Table 4-14. Pseudo-Op and PCLMULQDQ Implementation
 Pseudo-Op                                                                                                 Imm8 Encoding
 PCLMULLQLQDQ xmm1, xmm2                                                                                   0000_0000B
 PCLMULHQLQDQ xmm1, xmm2                                                                                   0000_0001B
 PCLMULLQHQDQ xmm1, xmm2                                                                                   0001_0000B
 PCLMULHQHQDQ xmm1, xmm2                                                                                   0001_0001B



Operation
PCLMULQDQ
IF (Imm8[0] = 0 )
     THEN
          TEMP1 <- SRC1 [63:0];
     ELSE
          TEMP1 <- SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
     THEN
          TEMP2 <- SRC2 [63:0];
     ELSE
          TEMP2 <- SRC2 [127:64];
FI
For i = 0 to 63 {
     TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);
     For j = 1 to i {
          TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
     }
     DEST[ i ] <- TmpB[ i ];
}
For i = 64 to 126 {
     TmpB [ i ] <- 0;
     For j = i - 63 to 63 {
          TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
     }
     DEST[ i ] <- TmpB[ i ];
}
DEST[127] <- 0;
DEST[VLMAX-1:128] (Unmodified)

VPCLMULQDQ
IF (Imm8[0] = 0 )
     THEN
           TEMP1 <- SRC1 [63:0];
     ELSE
           TEMP1 <- SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
     THEN
           TEMP2 <- SRC2 [63:0];
     ELSE
           TEMP2 <- SRC2 [127:64];
FI
For i = 0 to 63 {
     TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);
     For j = 1 to i {
           TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
     }
     DEST[i] <- TmpB[i];
}
For i = 64 to 126 {
     TmpB [ i ] <- 0;
     For j = i - 63 to 63 {


       TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
   }
   DEST[i] <- TmpB[i];
}
DEST[VLMAX-1:127] <- 0;

Intel C/C++ Compiler Intrinsic Equivalent
(V)PCLMULQDQ:         __m128i _mm_clmulepi64_si128 (__m128i, __m128i, const int)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4, additionally
#UD                      If VEX.L = 1.






platform: x86_64
mnem: PCMPEQB
description:
PCMPEQB/PCMPEQW/PCMPEQD- Compare Packed Data for Equal
Opcode/                                     Op/   64/32 bit   CPUID     Description
Instruction                                 En    Mode        Feature
                                                  Support     Flag
0F 74 /r1                                   RM    V/V         MMX       Compare packed bytes in mm/m64 and mm
PCMPEQB mm, mm/m64                                                      for equality.

66 0F 74 /r                                 RM    V/V         SSE2      Compare packed bytes in xmm2/m128 and
PCMPEQB xmm1, xmm2/m128                                                 xmm1 for equality.

0F 75 /r1                                   RM    V/V         MMX       Compare packed words in mm/m64 and mm
PCMPEQW mm, mm/m64                                                      for equality.

66 0F 75 /r                                 RM    V/V         SSE2      Compare packed words in xmm2/m128 and
PCMPEQW xmm1, xmm2/m128                                                 xmm1 for equality.

0F 76 /r1                                   RM    V/V         MMX       Compare packed doublewords in mm/m64 and
PCMPEQD mm, mm/m64                                                      mm for equality.

66 0F 76 /r                                 RM    V/V         SSE2      Compare packed doublewords in xmm2/m128
PCMPEQD xmm1, xmm2/m128                                                 and xmm1 for equality.

VEX.NDS.128.66.0F.WIG 74 /r                 RVM V/V           AVX       Compare packed bytes in xmm3/m128 and
VPCMPEQB xmm1, xmm2, xmm3/m128                                          xmm2 for equality.

VEX.NDS.128.66.0F.WIG 75 /r                 RVM V/V           AVX       Compare packed words in xmm3/m128 and
VPCMPEQW xmm1, xmm2, xmm3/m128                                          xmm2 for equality.

VEX.NDS.128.66.0F.WIG 76 /r                 RVM V/V           AVX       Compare packed doublewords in xmm3/m128
VPCMPEQD xmm1, xmm2, xmm3/m128                                          and xmm2 for equality.

VEX.NDS.256.66.0F.WIG 74 /r                 RVM V/V           AVX2      Compare packed bytes in ymm3/m256 and
VPCMPEQB ymm1, ymm2, ymm3 /m256                                         ymm2 for equality.
VEX.NDS.256.66.0F.WIG 75 /r                 RVM V/V           AVX2      Compare packed words in ymm3/m256 and
VPCMPEQW ymm1, ymm2, ymm3 /m256                                         ymm2 for equality.

VEX.NDS.256.66.0F.WIG 76 /r                 RVM V/V           AVX2      Compare packed doublewords in ymm3/m256
VPCMPEQD ymm1, ymm2, ymm3 /m256                                         and ymm2 for equality.

EVEX.NDS.128.66.0F.W0 76 /r                 FV    V/V         AVX512V Compare Equal between int32 vector xmm2
VPCMPEQD k1 {k2}, xmm2, xmm3/m128/m32bcst                     L       and int32 vector xmm3/m128/m32bcst, and
                                                              AVX512F set vector mask k1 to reflect the
                                                                      zero/nonzero status of each element of the
                                                                      result, under writemask.
EVEX.NDS.256.66.0F.W0 76 /r                 FV    V/V         AVX512V Compare Equal between int32 vector ymm2
VPCMPEQD k1 {k2}, ymm2, ymm3/m256/m32bcst                     L       and int32 vector ymm3/m256/m32bcst, and
                                                              AVX512F set vector mask k1 to reflect the
                                                                      zero/nonzero status of each element of the
                                                                      result, under writemask.
EVEX.NDS.512.66.0F.W0 76 /r                 FV    V/V         AVX512F   Compare Equal between int32 vectors in
VPCMPEQD k1 {k2}, zmm2, zmm3/m512/m32bcst                               zmm2 and zmm3/m512/m32bcst, and set
                                                                        destination k1 according to the comparison
                                                                        results under writemask k2.
EVEX.NDS.128.66.0F.WIG 74 /r                FVM V/V           AVX512V   Compare packed bytes in xmm3/m128 and
VPCMPEQB k1 {k2}, xmm2, xmm3 /m128                            L         xmm2 for equality and set vector mask k1 to
                                                              AVX512B   reflect the zero/nonzero status of each
                                                              W         element of the result, under writemask.





EVEX.NDS.256.66.0F.WIG 74 /r                         FVM V/V            AVX512V     Compare packed bytes in ymm3/m256 and
VPCMPEQB k1 {k2}, ymm2, ymm3 /m256                                      L           ymm2 for equality and set vector mask k1 to
                                                                        AVX512B     reflect the zero/nonzero status of each
                                                                        W           element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 74 /r                         FVM V/V            AVX512B     Compare packed bytes in zmm3/m512 and
VPCMPEQB k1 {k2}, zmm2, zmm3 /m512                                      W           zmm2 for equality and set vector mask k1 to
                                                                                    reflect the zero/nonzero status of each
                                                                                    element of the result, under writemask.
EVEX.NDS.128.66.0F.WIG 75 /r                         FVM V/V            AVX512V     Compare packed words in xmm3/m128 and
VPCMPEQW k1 {k2}, xmm2, xmm3 /m128                                      L           xmm2 for equality and set vector mask k1 to
                                                                        AVX512B     reflect the zero/nonzero status of each
                                                                        W           element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 75 /r                         FVM V/V            AVX512V     Compare packed words in ymm3/m256 and
VPCMPEQW k1 {k2}, ymm2, ymm3 /m256                                      L           ymm2 for equality and set vector mask k1 to
                                                                        AVX512B     reflect the zero/nonzero status of each
                                                                        W           element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 75 /r                         FVM V/V            AVX512B     Compare packed words in zmm3/m512 and
VPCMPEQW k1 {k2}, zmm2, zmm3 /m512                                      W           zmm2 for equality and set vector mask k1 to
                                                                                    reflect the zero/nonzero status of each
                                                                                    element of the result, under writemask.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                    Operand 2                    Operand 3                      Operand 4
    RM          ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA
   RVM           ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                      NA
    FV           ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                      NA
   FVM           ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                      NA


Description
Performs a SIMD compare for equality of the packed bytes, words, or doublewords in the destination operand (first
operand) and the source operand (second operand). If a pair of data elements is equal, the corresponding data
element in the destination operand is set to all 1s; otherwise, it is set to all 0s.
The (V)PCMPEQB instruction compares the corresponding bytes in the destination and source operands; the
(V)PCMPEQW instruction compares the corresponding words in the destination and source operands; and the
(V)PCMPEQD instruction compares the corresponding doublewords in the destination and source operands.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.




VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPEQD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
EVEX encoded VPCMPEQB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand
(first operand) is a mask register updated according to the writemask k2.

Operation
PCMPEQB (with 64-bit operands)
  IF DEST[7:0] = SRC[7:0]
       THEN DEST[7:0) <- FFH;
       ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
  IF DEST[63:56] = SRC[63:56]
       THEN DEST[63:56] <- FFH;
       ELSE DEST[63:56] <- 0; FI;

COMPARE_BYTES_EQUAL (SRC1, SRC2)
    IF SRC1[7:0] = SRC2[7:0]
    THEN DEST[7:0] <-FFH;
    ELSE DEST[7:0] <-0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
    IF SRC1[127:120] = SRC2[127:120]
    THEN DEST[127:120] <-FFH;
    ELSE DEST[127:120] <-0; FI;

COMPARE_WORDS_EQUAL (SRC1, SRC2)
    IF SRC1[15:0] = SRC2[15:0]
    THEN DEST[15:0] <-FFFFH;
    ELSE DEST[15:0] <-0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
    IF SRC1[127:112] = SRC2[127:112]
    THEN DEST[127:112] <-FFFFH;
    ELSE DEST[127:112] <-0; FI;

COMPARE_DWORDS_EQUAL (SRC1, SRC2)
    IF SRC1[31:0] = SRC2[31:0]
    THEN DEST[31:0] <-FFFFFFFFH;
    ELSE DEST[31:0] <-0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
    IF SRC1[127:96] = SRC2[127:96]
    THEN DEST[127:96] <-FFFFFFFFH;
    ELSE DEST[127:96] <-0; FI;


PCMPEQB (with 128-bit operands)
DEST[127:0] <-COMPARE_BYTES_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPEQB (VEX.128 encoded version)
DEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])



DEST[VLMAX-1:128] <- 0

VPCMPEQB (VEX.256 encoded version)
DEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPEQB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)

FOR j <- 0 TO KL-1
   i<-j*8
   IF k2[j] OR *no writemask*
        THEN
             /* signed comparison */
             CMP <- SRC1[i+7:i] == SRC2[i+7:i];
             IF CMP = TRUE
                   THEN DEST[j] <- 1;
                   ELSE DEST[j] <- 0; FI;
        ELSE       DEST[j] <- 0              ; zeroing-masking onlyFI;
   FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

PCMPEQW (with 64-bit operands)
  IF DEST[15:0] = SRC[15:0]
       THEN DEST[15:0] <- FFFFH;
       ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
  IF DEST[63:48] = SRC[63:48]
       THEN DEST[63:48] <- FFFFH;
       ELSE DEST[63:48] <- 0; FI;

PCMPEQW (with 128-bit operands)
DEST[127:0] <-COMPARE_WORDS_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPEQW (VEX.128 encoded version)
DEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] <- 0

VPCMPEQW (VEX.256 encoded version)
DEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPEQW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k2[j] OR *no writemask*
         THEN
               /* signed comparison */
               CMP <- SRC1[i+15:i] == SRC2[i+15:i];
               IF CMP = TRUE



                 THEN DEST[j] <- 1;
                 ELSE DEST[j] <- 0; FI;
       ELSE      DEST[j] <- 0                  ; zeroing-masking onlyFI;
   FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

PCMPEQD (with 64-bit operands)
  IF DEST[31:0] = SRC[31:0]
       THEN DEST[31:0] <- FFFFFFFFH;
       ELSE DEST[31:0] <- 0; FI;
  IF DEST[63:32] = SRC[63:32]
       THEN DEST[63:32] <- FFFFFFFFH;
       ELSE DEST[63:32] <- 0; FI;

PCMPEQD (with 128-bit operands)
DEST[127:0] <-COMPARE_DWORDS_EQUAL(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPEQD (VEX.128 encoded version)
DEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] <- 0

VPCMPEQD (VEX.256 encoded version)
DEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPEQD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k2[j] OR *no writemask*
         THEN
               /* signed comparison */
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                     THEN CMP <- SRC1[i+31:i] = SRC2[31:0];
                     ELSE CMP <- SRC1[i+31:i] = SRC2[i+31:i];
               FI;
               IF CMP = TRUE
                     THEN DEST[j] <- 1;
                     ELSE DEST[j] <- 0; FI;
         ELSE        DEST[j] <- 0               ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPCMPEQB __mmask64 _mm512_cmpeq_epi8_mask(__m512i a, __m512i b);
VPCMPEQB __mmask64 _mm512_mask_cmpeq_epi8_mask(__mmask64 k, __m512i a, __m512i b);
VPCMPEQB __mmask32 _mm256_cmpeq_epi8_mask(__m256i a, __m256i b);
VPCMPEQB __mmask32 _mm256_mask_cmpeq_epi8_mask(__mmask32 k, __m256i a, __m256i b);
VPCMPEQB __mmask16 _mm_cmpeq_epi8_mask(__m128i a, __m128i b);
VPCMPEQB __mmask16 _mm_mask_cmpeq_epi8_mask(__mmask16 k, __m128i a, __m128i b);




VPCMPEQW __mmask32 _mm512_cmpeq_epi16_mask(__m512i a, __m512i b);
VPCMPEQW __mmask32 _mm512_mask_cmpeq_epi16_mask(__mmask32 k, __m512i a, __m512i b);
VPCMPEQW __mmask16 _mm256_cmpeq_epi16_mask(__m256i a, __m256i b);
VPCMPEQW __mmask16 _mm256_mask_cmpeq_epi16_mask(__mmask16 k, __m256i a, __m256i b);
VPCMPEQW __mmask8 _mm_cmpeq_epi16_mask(__m128i a, __m128i b);
VPCMPEQW __mmask8 _mm_mask_cmpeq_epi16_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPEQD __mmask16 _mm512_cmpeq_epi32_mask( __m512i a, __m512i b);
VPCMPEQD __mmask16 _mm512_mask_cmpeq_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPEQD __mmask8 _mm256_cmpeq_epi32_mask(__m256i a, __m256i b);
VPCMPEQD __mmask8 _mm256_mask_cmpeq_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQD __mmask8 _mm_cmpeq_epi32_mask(__m128i a, __m128i b);
VPCMPEQD __mmask8 _mm_mask_cmpeq_epi32_mask(__mmask8 k, __m128i a, __m128i b);
PCMPEQB: __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 m2)
PCMPEQW: __m64 _mm_cmpeq_pi16 (__m64 m1, __m64 m2)
PCMPEQD: __m64 _mm_cmpeq_pi32 (__m64 m1, __m64 m2)
(V)PCMPEQB: __m128i _mm_cmpeq_epi8 ( __m128i a, __m128i b)
(V)PCMPEQW: __m128i _mm_cmpeq_epi16 ( __m128i a, __m128i b)
(V)PCMPEQD: __m128i _mm_cmpeq_epi32 ( __m128i a, __m128i b)
VPCMPEQB:      __m256i _mm256_cmpeq_epi8 ( __m256i a, __m256i b)
VPCMPEQW:      __m256i _mm256_cmpeq_epi16 ( __m256i a, __m256i b)
VPCMPEQD:      __m256i _mm256_cmpeq_epi32 ( __m256i a, __m256i b)



Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPEQD, see Exceptions Type E4.
EVEX-encoded VPCMPEQB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PCMPEQQ
description:
PCMPEQQ - Compare Packed Qword Data for Equal
Opcode/                                        Op/      64/32 bit   CPUID       Description
Instruction                                    En       Mode        Feature
                                                        Support     Flag
66 0F 38 29 /r                                 RM       V/V         SSE4_1      Compare packed qwords in xmm2/m128 and
PCMPEQQ xmm1, xmm2/m128                                                         xmm1 for equality.
VEX.NDS.128.66.0F38.WIG 29 /r                  RVM V/V              AVX         Compare packed quadwords in xmm3/m128
VPCMPEQQ xmm1, xmm2, xmm3/m128                                                  and xmm2 for equality.
VEX.NDS.256.66.0F38.WIG 29 /r                  RVM V/V              AVX2        Compare packed quadwords in ymm3/m256
VPCMPEQQ ymm1, ymm2, ymm3 /m256                                                 and ymm2 for equality.
EVEX.NDS.128.66.0F38.W1 29 /r                  FV       V/V         AVX512VL Compare Equal between int64 vector xmm2
VPCMPEQQ k1 {k2}, xmm2, xmm3/m128/m64bcst                           AVX512F and int64 vector xmm3/m128/m64bcst, and
                                                                             set vector mask k1 to reflect the zero/nonzero
                                                                             status of each element of the result, under
                                                                             writemask.
EVEX.NDS.256.66.0F38.W1 29 /r                  FV       V/V         AVX512VL Compare Equal between int64 vector ymm2
VPCMPEQQ k1 {k2}, ymm2, ymm3/m256/m64bcst                           AVX512F and int64 vector ymm3/m256/m64bcst, and
                                                                             set vector mask k1 to reflect the zero/nonzero
                                                                             status of each element of the result, under
                                                                             writemask.
EVEX.NDS.512.66.0F38.W1 29 /r                  FV       V/V         AVX512F     Compare Equal between int64 vector zmm2
VPCMPEQQ k1 {k2}, zmm2, zmm3/m512/m64bcst                                       and int64 vector zmm3/m512/m64bcst, and
                                                                                set vector mask k1 to reflect the zero/nonzero
                                                                                status of each element of the result, under
                                                                                writemask.



                                          Instruction Operand Encoding
   Op/En           Operand 1                Operand 2                      Operand 3                       Operand 4
    RM          ModRM:reg (r, w)         ModRM:r/m (r)                         NA                              NA
    RVM         ModRM:reg (w)             VEX.vvvv (r)                    ModRM:r/m (r)                        NA
     FV         ModRM:reg (w)             EVEX.vvvv (r)                   ModRM:r/m (r)                        NA


Description
Performs an SIMD compare for equality of the packed quadwords in the destination operand (first operand) and the
source operand (second operand). If a pair of data elements is equal, the corresponding data element in the desti-
nation is set to all 1s; otherwise, it is set to 0s.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPEQQ: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.





Operation

PCMPEQQ (with 128-bit operands)
IF (DEST[63:0] = SRC[63:0])
    THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
    ELSE DEST[63:0] <- 0; FI;
IF (DEST[127:64] = SRC[127:64])
    THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
    ELSE DEST[127:64] <- 0; FI;
DEST[MAX_VL-1:128] (Unmodified)

COMPARE_QWORDS_EQUAL (SRC1, SRC2)
  IF SRC1[63:0] = SRC2[63:0]
  THEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <-0; FI;
  IF SRC1[127:64] = SRC2[127:64]
  THEN DEST[127:64] <-FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <-0; FI;

VPCMPEQQ (VEX.128 encoded version)
DEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0

VPCMPEQQ (VEX.256 encoded version)
DEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPEQQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k2[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN CMP <- SRC1[i+63:i] = SRC2[63:0];
                    ELSE CMP <- SRC1[i+63:i] = SRC2[i+63:i];
               FI;
               IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPCMPEQQ __mmask8 _mm512_cmpeq_epi64_mask( __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm512_mask_cmpeq_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPEQQ __mmask8 _mm256_cmpeq_epi64_mask( __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm256_mask_cmpeq_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPEQQ __mmask8 _mm_cmpeq_epi64_mask( __m128i a, __m128i b);
VPCMPEQQ __mmask8 _mm_mask_cmpeq_epi64_mask(__mmask8 k, __m128i a, __m128i b);
(V)PCMPEQQ:  __m128i _mm_cmpeq_epi64(__m128i a, __m128i b);



VPCMPEQQ:        __m256i _mm256_cmpeq_epi64( __m256i a, __m256i b);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPEQQ, see Exceptions Type E4.






platform: x86_64
mnem: PCMPESTRI
description:
PCMPESTRI - Packed Compare Explicit Length Strings, Return Index
Opcode/                                                     Op/    64/32 bit   CPUID        Description
Instruction                                                 En     Mode        Feature
                                                                   Support     Flag
66 0F 3A 61 /r imm8                                        RMI     V/V         SSE4_2       Perform a packed comparison of string data
PCMPESTRI xmm1, xmm2/m128, imm8                                                             with explicit lengths, generating an index, and
                                                                                            storing the result in ECX.
VEX.128.66.0F3A 61 /r ib                                   RMI     V/V         AVX          Perform a packed comparison of string data
VPCMPESTRI xmm1, xmm2/m128, imm8                                                            with explicit lengths, generating an index, and
                                                                                            storing the result in ECX.



                                                     Instruction Operand Encoding
      Op/En              Operand 1                      Operand 2                        Operand 3                     Operand 4
      RMI              ModRM:reg (r)                   ModRM:r/m (r)                       imm8                            NA


Description
The instruction compares and processes data from two string fragments based on the encoded value in the Imm8
Control Byte (see Section 4.1, "Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMP-
ISTRM"), and generates an index stored to the count register (ECX).
Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second
operand) which contains the data elements of the string (byte or word data). The second value is stored in an input
length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-
sents the number of bytes/words which are valid for the respective xmm/m128 data.
The length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-
value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value
in the length register is greater than 16 (8) or less than -16 (-8).
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 (see Section 4.1.4) is returned
in ECX. If no bits are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-
tion:

      CFlag - Reset if IntRes2 is equal to zero, set otherwise
      ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise
      SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise
      OFlag - IntRes2[0]
      AFlag - Reset
      PFlag - Reset

Effective Operand Size
 Operating mode/size                 Operand 1            Operand 2             Length 1             Length 2               Result
 16 bit                              xmm                  xmm/m128              EAX                  EDX                    ECX
 32 bit                              xmm                  xmm/m128              EAX                  EDX                    ECX
 64 bit                              xmm                  xmm/m128              EAX                  EDX                    ECX
 64 bit + REX.W                      xmm                  xmm/m128              RAX                  RDX                    ECX



Intel C/C++ Compiler Intrinsic Equivalent For Returning Index
int     _mm_cmpestri (__m128i a, int la, __m128i b, int lb, const int mode);




Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int   _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16
Byte boundary, and
#UD                     If VEX.L = 1.
                        If VEX.vvvv != 1111B.






platform: x86_64
mnem: PCMPESTRM
description:
PCMPESTRM - Packed Compare Explicit Length Strings, Return Mask
Opcode/                                                   Op/     64/32 bit   CPUID      Description
Instruction                                               En      Mode        Feature
                                                                  Support     Flag
66 0F 3A 60 /r imm8                                       RMI     V/V         SSE4_2     Perform a packed comparison of string data
PCMPESTRM xmm1, xmm2/m128, imm8                                                          with explicit lengths, generating a mask, and
                                                                                         storing the result in XMM0.
VEX.128.66.0F3A 60 /r ib                                  RMI     V/V         AVX        Perform a packed comparison of string data
VPCMPESTRM xmm1, xmm2/m128, imm8                                                         with explicit lengths, generating a mask, and
                                                                                         storing the result in XMM0.



                                                   Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                      Operand 3                      Operand 4
    RMI             ModRM:reg (r)                  ModRM:r/m (r)                        imm8                           NA


Description
The instruction compares data from two string fragments based on the encoded value in the imm8 contol byte (see
Section 4.1, "Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM"), and gener-
ates a mask stored to XMM0.
Each string fragment is represented by two values. The first value is an xmm (or possibly m128 for the second
operand) which contains the data elements of the string (byte or word data). The second value is stored in an input
length register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128). The length repre-
sents the number of bytes/words which are valid for the respective xmm/m128 data.
The length of each input is interpreted as being the absolute-value of the value in the length register. The absolute-
value computation saturates to 16 (for bytes) and 8 (for words), based on the value of imm8[bit3] when the value
in the length register is greater than 16 (8) or less than -16 (-8).
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero
extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-
tion:

   CFlag - Reset if IntRes2 is equal to zero, set otherwise
   ZFlag - Set if absolute-value of EDX is < 16 (8), reset otherwise
   SFlag - Set if absolute-value of EAX is < 16 (8), reset otherwise
   OFlag -IntRes2[0]
   AFlag - Reset
   PFlag - Reset


Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be
1111b, VEX.L must be 0, otherwise the instruction will #UD.





Effective Operand Size

 Operating mode/size       Operand1              Operand 2             Length1                   Length2            Result
 16 bit                    xmm                   xmm/m128              EAX                       EDX                XMM0
 32 bit                    xmm                   xmm/m128              EAX                       EDX                XMM0
 64 bit                    xmm                   xmm/m128              EAX                       EDX                XMM0
 64 bit + REX.W            xmm                   xmm/m128              RAX                       RDX                XMM0


Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode);

Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int   _mm_cmpestra (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrc (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestro (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrs (__m128i a, int la, __m128i b, int lb, const int mode);
int   _mm_cmpestrz (__m128i a, int la, __m128i b, int lb, const int mode);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to 16
Byte boundary, and
#UD                     If VEX.L = 1.
                        If VEX.vvvv != 1111B.






platform: x86_64
mnem: PCMPGTB
description:
PCMPGTB/PCMPGTW/PCMPGTD-Compare Packed Signed Integers for Greater Than
Opcode/                                         Op/   64/32 bit   CPUID      Description
Instruction                                     En    Mode        Feature
                                                      Support     Flag
0F 64 /r1                                       RM    V/V         MMX        Compare packed signed byte integers in mm and
PCMPGTB mm, mm/m64                                                           mm/m64 for greater than.

66 0F 64 /r                                     RM    V/V         SSE2       Compare packed signed byte integers in xmm1
PCMPGTB xmm1, xmm2/m128                                                      and xmm2/m128 for greater than.

0F 65 /r1                                       RM    V/V         MMX        Compare packed signed word integers in mm and
PCMPGTW mm, mm/m64                                                           mm/m64 for greater than.

66 0F 65 /r                                     RM    V/V         SSE2       Compare packed signed word integers in xmm1
PCMPGTW xmm1, xmm2/m128                                                      and xmm2/m128 for greater than.

0F 66 /r1                                       RM    V/V         MMX        Compare packed signed doubleword integers in
PCMPGTD mm, mm/m64                                                           mm and mm/m64 for greater than.

66 0F 66 /r                                     RM    V/V         SSE2       Compare packed signed doubleword integers in
PCMPGTD xmm1, xmm2/m128                                                      xmm1 and xmm2/m128 for greater than.

VEX.NDS.128.66.0F.WIG 64 /r                     RVM V/V           AVX        Compare packed signed byte integers in xmm2
VPCMPGTB xmm1, xmm2, xmm3/m128                                               and xmm3/m128 for greater than.

VEX.NDS.128.66.0F.WIG 65 /r                     RVM V/V           AVX        Compare packed signed word integers in xmm2
VPCMPGTW xmm1, xmm2, xmm3/m128                                               and xmm3/m128 for greater than.

VEX.NDS.128.66.0F.WIG 66 /r                     RVM V/V           AVX        Compare packed signed doubleword integers in
VPCMPGTD xmm1, xmm2, xmm3/m128                                               xmm2 and xmm3/m128 for greater than.

VEX.NDS.256.66.0F.WIG 64 /r                     RVM V/V           AVX2       Compare packed signed byte integers in ymm2
VPCMPGTB ymm1, ymm2, ymm3/m256                                               and ymm3/m256 for greater than.

VEX.NDS.256.66.0F.WIG 65 /r                     RVM V/V           AVX2       Compare packed signed word integers in ymm2
VPCMPGTW ymm1, ymm2, ymm3/m256                                               and ymm3/m256 for greater than.
VEX.NDS.256.66.0F.WIG 66 /r                     RVM V/V           AVX2       Compare packed signed doubleword integers in
VPCMPGTD ymm1, ymm2, ymm3/m256                                               ymm2 and ymm3/m256 for greater than.

EVEX.NDS.128.66.0F.W0 66 /r                     FV    V/V         AVX512VL   Compare Greater between int32 vector xmm2 and
VPCMPGTD k1 {k2}, xmm2,                                           AVX512F    int32 vector xmm3/m128/m32bcst, and set
xmm3/m128/m32bcst                                                            vector mask k1 to reflect the zero/nonzero status
                                                                             of each element of the result, under writemask.
EVEX.NDS.256.66.0F.W0 66 /r                     FV    V/V         AVX512VL   Compare Greater between int32 vector ymm2 and
VPCMPGTD k1 {k2}, ymm2,                                           AVX512F    int32 vector ymm3/m256/m32bcst, and set
ymm3/m256/m32bcst                                                            vector mask k1 to reflect the zero/nonzero status
                                                                             of each element of the result, under writemask.
EVEX.NDS.512.66.0F.W0 66 /r                     FV    V/V         AVX512F    Compare Greater between int32 elements in
VPCMPGTD k1 {k2}, zmm2,                                                      zmm2 and zmm3/m512/m32bcst, and set
zmm3/m512/m32bcst                                                            destination k1 according to the comparison results
                                                                             under writemask. k2.
EVEX.NDS.128.66.0F.WIG 64 /r                    FVM V/V           AVX512VL   Compare packed signed byte integers in xmm2
VPCMPGTB k1 {k2}, xmm2, xmm3/m128                                 AVX512BW   and xmm3/m128 for greater than, and set vector
                                                                             mask k1 to reflect the zero/nonzero status of each
                                                                             element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 64 /r                    FVM V/V           AVX512VL   Compare packed signed byte integers in ymm2
VPCMPGTB k1 {k2}, ymm2, ymm3/m256                                 AVX512BW   and ymm3/m256 for greater than, and set vector
                                                                             mask k1 to reflect the zero/nonzero status of each
                                                                             element of the result, under writemask.




EVEX.NDS.512.66.0F.WIG 64 /r                    FVM V/V           AVX512BW      Compare packed signed byte integers in zmm2 and
VPCMPGTB k1 {k2}, zmm2, zmm3/m512                                               zmm3/m512 for greater than, and set vector
                                                                                mask k1 to reflect the zero/nonzero status of each
                                                                                element of the result, under writemask.
EVEX.NDS.128.66.0F.WIG 65 /r                    FVM V/V           AVX512VL      Compare packed signed word integers in xmm2
VPCMPGTW k1 {k2}, xmm2, xmm3/m128                                 AVX512BW      and xmm3/m128 for greater than, and set vector
                                                                                mask k1 to reflect the zero/nonzero status of each
                                                                                element of the result, under writemask.
EVEX.NDS.256.66.0F.WIG 65 /r                    FVM V/V           AVX512VL      Compare packed signed word integers in ymm2
VPCMPGTW k1 {k2}, ymm2, ymm3/m256                                 AVX512BW      and ymm3/m256 for greater than, and set vector
                                                                                mask k1 to reflect the zero/nonzero status of each
                                                                                element of the result, under writemask.
EVEX.NDS.512.66.0F.WIG 65 /r                    FVM V/V           AVX512BW      Compare packed signed word integers in zmm2
VPCMPGTW k1 {k2}, zmm2, zmm3/m512                                               and zmm3/m512 for greater than, and set vector
                                                                                mask k1 to reflect the zero/nonzero status of each
                                                                                element of the result, under writemask.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                    Operand 3                      Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                      NA                             NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                        NA
    FV            ModRM:reg (w)                EVEX.vvvv (r)                ModRM:r/m (r)                        NA
   FVM            ModRM:reg (w)                EVEX.vvvv (r)                ModRM:r/m (r)                        NA


Description
Performs an SIMD signed compare for the greater value of the packed byte, word, or doubleword integers in the
destination operand (first operand) and the source operand (second operand). If a data element in the destination
operand is greater than the corresponding date element in the source operand, the corresponding data element in
the destination operand is set to all 1s; otherwise, it is set to all 0s.
The PCMPGTB instruction compares the corresponding signed byte integers in the destination and source oper-
ands; the PCMPGTW instruction compares the corresponding signed word integers in the destination and source
operands; and the PCMPGTD instruction compares the corresponding signed doubleword integers in the destina-
tion and source operands.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand can be an MMX technology register.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.




EVEX encoded VPCMPGTD: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.
EVEX encoded VPCMPGTB/W: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand
(first operand) is a mask register updated according to the writemask k2.

Operation
PCMPGTB (with 64-bit operands)
  IF DEST[7:0] > SRC[7:0]
       THEN DEST[7:0) <- FFH;
       ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
  IF DEST[63:56] > SRC[63:56]
       THEN DEST[63:56] <- FFH;
       ELSE DEST[63:56] <- 0; FI;

COMPARE_BYTES_GREATER (SRC1, SRC2)
    IF SRC1[7:0] > SRC2[7:0]
    THEN DEST[7:0] <-FFH;
    ELSE DEST[7:0] <-0; FI;
(* Continue comparison of 2nd through 15th bytes in SRC1 and SRC2 *)
    IF SRC1[127:120] > SRC2[127:120]
    THEN DEST[127:120] <-FFH;
    ELSE DEST[127:120] <-0; FI;

COMPARE_WORDS_GREATER (SRC1, SRC2)
    IF SRC1[15:0] > SRC2[15:0]
    THEN DEST[15:0] <-FFFFH;
    ELSE DEST[15:0] <-0; FI;
(* Continue comparison of 2nd through 7th 16-bit words in SRC1 and SRC2 *)
    IF SRC1[127:112] > SRC2[127:112]
    THEN DEST[127:112] <-FFFFH;
    ELSE DEST[127:112] <-0; FI;

COMPARE_DWORDS_GREATER (SRC1, SRC2)
    IF SRC1[31:0] > SRC2[31:0]
    THEN DEST[31:0] <-FFFFFFFFH;
    ELSE DEST[31:0] <-0; FI;
(* Continue comparison of 2nd through 3rd 32-bit dwords in SRC1 and SRC2 *)
    IF SRC1[127:96] > SRC2[127:96]
    THEN DEST[127:96] <-FFFFFFFFH;
    ELSE DEST[127:96] <-0; FI;


PCMPGTB (with 128-bit operands)
DEST[127:0] <-COMPARE_BYTES_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPGTB (VEX.128 encoded version)
DEST[127:0] <-COMPARE_BYTES_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0




VPCMPGTB (VEX.256 encoded version)
DEST[127:0] <-COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPGTB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k2[j] OR *no writemask*
         THEN
              /* signed comparison */
              CMP <- SRC1[i+7:i] > SRC2[i+7:i];
              IF CMP = TRUE
                    THEN DEST[j] <- 1;
                    ELSE DEST[j] <- 0; FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking onlyFI;
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0


PCMPGTW (with 64-bit operands)
  IF DEST[15:0] > SRC[15:0]
       THEN DEST[15:0] <- FFFFH;
       ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
  IF DEST[63:48] > SRC[63:48]
       THEN DEST[63:48] <- FFFFH;
       ELSE DEST[63:48] <- 0; FI;

PCMPGTW (with 128-bit operands)
DEST[127:0] <-COMPARE_WORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPGTW (VEX.128 encoded version)
DEST[127:0] <-COMPARE_WORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0

VPCMPGTW (VEX.256 encoded version)
DEST[127:0] <-COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPGTW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k2[j] OR *no writemask*
         THEN
               /* signed comparison */
               CMP <- SRC1[i+15:i] > SRC2[i+15:i];
               IF CMP = TRUE
                     THEN DEST[j] <- 1;
                     ELSE DEST[j] <- 0; FI;



       ELSE    DEST[j] <- 0                    ; zeroing-masking onlyFI;
   FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0


PCMPGTD (with 64-bit operands)
  IF DEST[31:0] > SRC[31:0]
       THEN DEST[31:0] <- FFFFFFFFH;
       ELSE DEST[31:0] <- 0; FI;
  IF DEST[63:32] > SRC[63:32]
       THEN DEST[63:32] <- FFFFFFFFH;
       ELSE DEST[63:32] <- 0; FI;

PCMPGTD (with 128-bit operands)
DEST[127:0] <-COMPARE_DWORDS_GREATER(DEST[127:0],SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

VPCMPGTD (VEX.128 encoded version)
DEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0

VPCMPGTD (VEX.256 encoded version)
DEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPGTD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k2[j] OR *no writemask*
         THEN
               /* signed comparison */
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                     THEN CMP <- SRC1[i+31:i] > SRC2[31:0];
                     ELSE CMP <- SRC1[i+31:i] > SRC2[i+31:i];
               FI;
               IF CMP = TRUE
                     THEN DEST[j] <- 1;
                     ELSE DEST[j] <- 0; FI;
         ELSE        DEST[j] <- 0               ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPCMPGTB __mmask64 _mm512_cmpgt_epi8_mask(__m512i a, __m512i b);
VPCMPGTB __mmask64 _mm512_mask_cmpgt_epi8_mask(__mmask64 k, __m512i a, __m512i b);
VPCMPGTB __mmask32 _mm256_cmpgt_epi8_mask(__m256i a, __m256i b);
VPCMPGTB __mmask32 _mm256_mask_cmpgt_epi8_mask(__mmask32 k, __m256i a, __m256i b);
VPCMPGTB __mmask16 _mm_cmpgt_epi8_mask(__m128i a, __m128i b);
VPCMPGTB __mmask16 _mm_mask_cmpgt_epi8_mask(__mmask16 k, __m128i a, __m128i b);
VPCMPGTD __mmask16 _mm512_cmpgt_epi32_mask(__m512i a, __m512i b);




VPCMPGTD __mmask16 _mm512_mask_cmpgt_epi32_mask(__mmask16 k, __m512i a, __m512i b);
VPCMPGTD __mmask8 _mm256_cmpgt_epi32_mask(__m256i a, __m256i b);
VPCMPGTD __mmask8 _mm256_mask_cmpgt_epi32_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPGTD __mmask8 _mm_cmpgt_epi32_mask(__m128i a, __m128i b);
VPCMPGTD __mmask8 _mm_mask_cmpgt_epi32_mask(__mmask8 k, __m128i a, __m128i b);
VPCMPGTW __mmask32 _mm512_cmpgt_epi16_mask(__m512i a, __m512i b);
VPCMPGTW __mmask32 _mm512_mask_cmpgt_epi16_mask(__mmask32 k, __m512i a, __m512i b);
VPCMPGTW __mmask16 _mm256_cmpgt_epi16_mask(__m256i a, __m256i b);
VPCMPGTW __mmask16 _mm256_mask_cmpgt_epi16_mask(__mmask16 k, __m256i a, __m256i b);
VPCMPGTW __mmask8 _mm_cmpgt_epi16_mask(__m128i a, __m128i b);
VPCMPGTW __mmask8 _mm_mask_cmpgt_epi16_mask(__mmask8 k, __m128i a, __m128i b);
PCMPGTB:__m64 _mm_cmpgt_pi8 (__m64 m1, __m64 m2)
PCMPGTW:__m64 _mm_pcmpgt_pi16 (__m64 m1, __m64 m2)
PCMPGTD:__m64 _mm_pcmpgt_pi32 (__m64 m1, __m64 m2)
(V)PCMPGTB:__m128i _mm_cmpgt_epi8 ( __m128i a, __m128i b)
(V)PCMPGTW:__m128i _mm_cmpgt_epi16 ( __m128i a, __m128i b)
(V)DCMPGTD:__m128i _mm_cmpgt_epi32 ( __m128i a, __m128i b)
VPCMPGTB:     __m256i _mm256_cmpgt_epi8 ( __m256i a, __m256i b)
VPCMPGTW:     __m256i _mm256_cmpgt_epi16 ( __m256i a, __m256i b)
VPCMPGTD:     __m256i _mm256_cmpgt_epi32 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPGTD, see Exceptions Type E4.
EVEX-encoded VPCMPGTB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PCMPGTQ
description:
PCMPGTQ - Compare Packed Data for Greater Than
Opcode/                                           Op/   64/32 bit   CPUID       Description
Instruction                                       En    Mode        Feature
                                                        Support     Flag
66 0F 38 37 /r                                    RM    V/V         SSE4_2      Compare packed signed qwords in xmm2/m128
PCMPGTQ xmm1,xmm2/m128                                                          and xmm1 for greater than.
VEX.NDS.128.66.0F38.WIG 37 /r                     RVM V/V           AVX         Compare packed signed qwords in xmm2 and
VPCMPGTQ xmm1, xmm2, xmm3/m128                                                  xmm3/m128 for greater than.
VEX.NDS.256.66.0F38.WIG 37 /r                     RVM V/V           AVX2        Compare packed signed qwords in ymm2 and
VPCMPGTQ ymm1, ymm2, ymm3/m256                                                  ymm3/m256 for greater than.
EVEX.NDS.128.66.0F38.W1 37 /r                     FV    V/V         AVX512VL Compare Greater between int64 vector xmm2 and
VPCMPGTQ k1 {k2}, xmm2,                                             AVX512F int64 vector xmm3/m128/m64bcst, and set
xmm3/m128/m64bcst                                                            vector mask k1 to reflect the zero/nonzero status
                                                                             of each element of the result, under writemask.
EVEX.NDS.256.66.0F38.W1 37 /r                     FV    V/V         AVX512VL Compare Greater between int64 vector ymm2 and
VPCMPGTQ k1 {k2}, ymm2,                                             AVX512F int64 vector ymm3/m256/m64bcst, and set
ymm3/m256/m64bcst                                                            vector mask k1 to reflect the zero/nonzero status
                                                                             of each element of the result, under writemask.
EVEX.NDS.512.66.0F38.W1 37 /r             FV            V/V         AVX512F     Compare Greater between int64 vector zmm2 and
VPCMPGTQ k1 {k2}, zmm2, zmm3/m512/m64bcst                                       int64 vector zmm3/m512/m64bcst, and set
                                                                                vector mask k1 to reflect the zero/nonzero status
                                                                                of each element of the result, under writemask.



                                                 Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                   Operand 3                     Operand 4
    RM             ModRM:reg (r, w)               ModRM:r/m (r)                    NA                           NA
    RVM             ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                     NA
     FV             ModRM:reg (w)                 EVEX.vvvv (r)               ModRM:r/m (r)                     NA


Description
Performs an SIMD signed compare for the packed quadwords in the destination operand (first operand) and the
source operand (second operand). If the data element in the first (destination) operand is greater than the
corresponding element in the second (source) operand, the corresponding data element in the destination is set
to all 1s; otherwise, it is set to 0s.
128-bit Legacy SSE version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or a 128-bit memory location. The
first source operand and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register.
EVEX encoded VPCMPGTD/Q: The first source operand (second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand (first operand) is a mask register updated
according to the writemask k2.





Operation
COMPARE_QWORDS_GREATER (SRC1, SRC2)
  IF SRC1[63:0] > SRC2[63:0]
  THEN DEST[63:0] <-FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <-0; FI;
  IF SRC1[127:64] > SRC2[127:64]
  THEN DEST[127:64] <-FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <-0; FI;

VPCMPGTQ (VEX.128 encoded version)
DEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0

VPCMPGTQ (VEX.256 encoded version)
DEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128])
DEST[VLMAX-1:256] <- 0

VPCMPGTQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k2[j] OR *no writemask*
         THEN
               /* signed comparison */
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                     THEN CMP <- SRC1[i+63:i] > SRC2[63:0];
                     ELSE CMP <- SRC1[i+63:i] > SRC2[i+63:i];
               FI;
               IF CMP = TRUE
                     THEN DEST[j] <- 1;
                     ELSE DEST[j] <- 0; FI;
         ELSE        DEST[j] <- 0               ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPCMPGTQ __mmask8 _mm512_cmpgt_epi64_mask( __m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm512_mask_cmpgt_epi64_mask(__mmask8 k, __m512i a, __m512i b);
VPCMPGTQ __mmask8 _mm256_cmpgt_epi64_mask( __m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm256_mask_cmpgt_epi64_mask(__mmask8 k, __m256i a, __m256i b);
VPCMPGTQ __mmask8 _mm_cmpgt_epi64_mask( __m128i a, __m128i b);
VPCMPGTQ __mmask8 _mm_mask_cmpgt_epi64_mask(__mmask8 k, __m128i a, __m128i b);
(V)PCMPGTQ:  __m128i _mm_cmpgt_epi64(__m128i a, __m128i b)
VPCMPGTQ:    __m256i _mm256_cmpgt_epi64( __m256i a, __m256i b);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.




Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPCMPGTQ, see Exceptions Type E4.






platform: x86_64
mnem: PCMPISTRI
description:
PCMPISTRI - Packed Compare Implicit Length Strings, Return Index
Opcode/                                                 Op/    64/32 bit     CPUID           Description
Instruction                                             En     Mode          Feature
                                                               Support       Flag
66 0F 3A 63 /r imm8                                     RM     V/V           SSE4_2          Perform a packed comparison of string data
PCMPISTRI xmm1, xmm2/m128, imm8                                                              with implicit lengths, generating an index, and
                                                                                             storing the result in ECX.
VEX.128.66.0F3A.WIG 63 /r ib                            RM     V/V           AVX             Perform a packed comparison of string data
VPCMPISTRI xmm1, xmm2/m128, imm8                                                             with implicit lengths, generating an index, and
                                                                                             storing the result in ECX.



                                                  Instruction Operand Encoding
      Op/En            Operand 1                     Operand 2                         Operand 3                        Operand 4
       RM             ModRM:reg (r)                 ModRM:r/m (r)                        imm8                               NA


Description
The instruction compares data from two strings based on the encoded value in the Imm8 Control Byte (see Section
4.1, "Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM"), and generates an
index stored to ECX.
Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which
contains the data elements of the string (byte or word data). Each input byte/word is augmented with a
valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null
byte/word. (The least significant null byte/word is also considered invalid.)
The comparison and aggregation operations are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). The index of the first (or last, according to imm8[6]) set bit of IntRes2 is returned in ECX. If no bits
are set in IntRes2, ECX is set to 16 (8).
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-
tion:

      CFlag - Reset if IntRes2 is equal to zero, set otherwise
      ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise
      SFlag - Set if any byte/word of xmm1 is null, reset otherwise
      OFlag -IntRes2[0]
      AFlag - Reset
      PFlag - Reset
Note: In VEX.128 encoded version, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD.

Effective Operand Size

  Operating mode/size                 Operand1             Operand 2                   Result

  16 bit                              xmm                  xmm/m128                    ECX

  32 bit                              xmm                  xmm/m128                    ECX

  64 bit                              xmm                  xmm/m128                    ECX




Intel C/C++ Compiler Intrinsic Equivalent For Returning Index
int     _mm_cmpistri (__m128i a, __m128i b, const int mode);



Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int   _mm_cmpistra (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrc (__m128i a, __m128i b, const int mode);
int   _mm_cmpistro (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrs (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrz (__m128i a, __m128i b, const int mode);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to
16 Byte boundary, and
#UD                       If VEX.L = 1.
                          If VEX.vvvv != 1111B.






platform: x86_64
mnem: PCMPISTRM
description:
PCMPISTRM - Packed Compare Implicit Length Strings, Return Mask
Opcode/                                              Op/   64/32 bit      CPUID        Description
Instruction                                          En    Mode           Feature
                                                           Support        Flag
66 0F 3A 62 /r imm8                                  RM    V/V            SSE4_2       Perform a packed comparison of string data
PCMPISTRM xmm1, xmm2/m128, imm8                                                        with implicit lengths, generating a mask, and
                                                                                       storing the result in XMM0.
VEX.128.66.0F3A.WIG 62 /r ib                         RM    V/V            AVX          Perform a packed comparison of string data
VPCMPISTRM xmm1, xmm2/m128, imm8                                                       with implicit lengths, generating a Mask, and
                                                                                       storing the result in XMM0.



                                               Instruction Operand Encoding
  Op/En             Operand 1                     Operand 2                         Operand 3                     Operand 4
    RM            ModRM:reg (r)                 ModRM:r/m (r)                         imm8                            NA


Description
The instruction compares data from two strings based on the encoded value in the imm8 byte (see Section 4.1,
"Imm8 Control Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM") generating a mask
stored to XMM0.
Each string is represented by a single value. The value is an xmm (or possibly m128 for the second operand) which
contains the data elements of the string (byte or word data). Each input byte/word is augmented with a
valid/invalid tag. A byte/word is considered valid only if it has a lower index than the least significant null
byte/word. (The least significant null byte/word is also considered invalid.)
The comparison and aggregation operation are performed according to the encoded value of Imm8 bit fields (see
Section 4.1). As defined by imm8[6], IntRes2 is then either stored to the least significant bits of XMM0 (zero
extended to 128 bits) or expanded into a byte/word-mask and then stored to XMM0.
Note that the Arithmetic Flags are written in a non-standard manner in order to supply the most relevant informa-
tion:

   CFlag - Reset if IntRes2 is equal to zero, set otherwise
   ZFlag - Set if any byte/word of xmm2/mem128 is null, reset otherwise
   SFlag - Set if any byte/word of xmm1 is null, reset otherwise
   OFlag - IntRes2[0]
   AFlag - Reset
   PFlag - Reset
Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv is reserved and must be
1111b, VEX.L must be 0, otherwise the instruction will #UD.

Effective Operand Size

 Operating mode/size                                 Operand1                   Operand 2                    Result
 16 bit                                              xmm                        xmm/m128                     XMM0
 32 bit                                              xmm                        xmm/m128                     XMM0
 64 bit                                              xmm                        xmm/m128                     XMM0


Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);





Intel C/C++ Compiler Intrinsics For Reading EFlag Results
int   _mm_cmpistra (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrc (__m128i a, __m128i b, const int mode);
int   _mm_cmpistro (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrs (__m128i a, __m128i b, const int mode);
int   _mm_cmpistrz (__m128i a, __m128i b, const int mode);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally, this instruction does not cause #GP if the memory operand is not aligned to
16 Byte boundary, and
#UD                      If VEX.L = 1.
                         If VEX.vvvv != 1111B.






platform: x86_64
mnem: PDEP
description:
PDEP - Parallel Bits Deposit
 Opcode/                            Op/   64/32      CPUID        Description
 Instruction                        En    -bit       Feature
                                          Mode       Flag
 VEX.NDS.LZ.F2.0F38.W0 F5 /r        RVM   V/V        BMI2         Parallel deposit of bits from r32b using mask in r/m32, result is writ-
 PDEP r32a, r32b, r/m32                                           ten to r32a.
 VEX.NDS.LZ.F2.0F38.W1 F5 /r        RVM   V/N.E.     BMI2         Parallel deposit of bits from r64b using mask in r/m64, result is writ-
 PDEP r64a, r64b, r/m64                                           ten to r64a.



                                                   Instruction Operand Encoding
     Op/En          Operand 1                       Operand 2                        Operand 3                        Operand 4
     RVM          ModRM:reg (w)                    VEX.vvvv (r)                     ModRM:r/m (r)                        NA


Description
PDEP uses a mask in the second source operand (the third operand) to transfer/scatter contiguous low order bits
in the first source operand (the second operand) into the destination (the first operand). PDEP takes the low bits
from the first source operand and deposit them in the destination operand at the corresponding bit locations that
are set in the second source operand (mask). All other bits (bits not set in mask) in destination are set to zero.



                    SRC1     S31 S30 S29 S28 S27                         S7 S6 S5         S4   S3    S2 S1    S0



                    SRC2   0          0   0   1     0                     1 0         1   0    0     1    0    0
                    (mask)


                    DEST        0    0    0   S3      0                  S2     0     S1 0       0   S0   0    0

                           bit 31                                                                             bit 0


                                                    Figure 4-8. PDEP Example

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation
TEMP <- SRC1;
MASK <- SRC2;
DEST <- 0 ;
m<- 0, k<- 0;
DO WHILE m< OperandSize

         IF MASK[ m] = 1 THEN
             DEST[ m] <- TEMP[ k];
             k <- k+ 1;
         FI
         m <- m+ 1;
OD




Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
PDEP:          unsigned __int32 _pdep_u32(unsigned __int32 src, unsigned __int32 mask);
PDEP:          unsigned __int64 _pdep_u64(unsigned __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Section 2.5.1, "Exception Conditions for VEX-Encoded GPR Instructions", Table 2-29; additionally
#UD                        If VEX.W = 1.






platform: x86_64
mnem: PEXT
description:
PEXT - Parallel Bits Extract
 Opcode/                            Op/       64/32         CPUID     Description
 Instruction                        En        -bit          Feature
                                              Mode          Flag
 VEX.NDS.LZ.F3.0F38.W0 F5 /r        RVM       V/V           BMI2      Parallel extract of bits from r32b using mask in r/m32, result is writ-
 PEXT r32a, r32b, r/m32                                               ten to r32a.
 VEX.NDS.LZ.F3.0F38.W1 F5 /r        RVM       V/N.E.        BMI2      Parallel extract of bits from r64b using mask in r/m64, result is writ-
 PEXT r64a, r64b, r/m64                                               ten to r64a.



                                                    Instruction Operand Encoding
  Op/En             Operand 1                          Operand 2                      Operand 3                          Operand 4
   RVM            ModRM:reg (w)                        VEX.vvvv (r)                 ModRM:r/m (r)                             NA


Description
PEXT uses a mask in the second source operand (the third operand) to transfer either contiguous or non-contig-
uous bits in the first source operand (the second operand) to contiguous low order bit positions in the destination
(the first operand). For each bit set in the MASK, PEXT extracts the corresponding bits from the first source operand
and writes them into contiguous lower bits of destination operand. The remaining upper bits of destination are
zeroed.



                    SRC1 S S
                          31 30 S29 S28 S27                                S7 S6 S5         S4   S3   S2 S1      S0



                    SRC2                                                                         0
                           0        0     0    1       0                     1 0       1    0          1    0     0
                    (mask)




                    DEST     0       0    0     0       0                    0 0        0    0   S28 S7     S5    S2

                           bit 31                                                                                bit 0


                                                        Figure 4-9. PEXT Example

This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation
TEMP <- SRC1;
MASK <- SRC2;
DEST <- 0 ;
m<- 0, k<- 0;
DO WHILE m< OperandSize

         IF MASK[ m] = 1 THEN
             DEST[ k] <- TEMP[ m];
             k <- k+ 1;
         FI



         m <- m+ 1;

OD

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
PEXT:          unsigned __int32 _pext_u32(unsigned __int32 src, unsigned __int32 mask);
PEXT:          unsigned __int64 _pext_u64(unsigned __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Section 2.5.1, "Exception Conditions for VEX-Encoded GPR Instructions", Table 2-29; additionally
#UD                        If VEX.W = 1.






platform: x86_64
mnem: PEXTRB
description:
PEXTRB/PEXTRD/PEXTRQ - Extract Byte/Dword/Qword
Opcode/                                       Op/ En     64/32 bit   CPUID         Description
Instruction                                              Mode        Feature
                                                         Support     Flag
66 0F 3A 14                                   MRI        V/V         SSE4_1        Extract a byte integer value from xmm2 at the
/r ib                                                                              source byte offset specified by imm8 into reg or
PEXTRB reg/m8, xmm2, imm8                                                          m8. The upper bits of r32 or r64 are zeroed.
66 0F 3A 16                                   MRI        V/V         SSE4_1        Extract a dword integer value from xmm2 at the
/r ib                                                                              source dword offset specified by imm8 into r/m32.
PEXTRD r/m32, xmm2, imm8
66 REX.W 0F 3A 16                             MRI        V/N.E.      SSE4_1        Extract a qword integer value from xmm2 at the
/r ib                                                                              source qword offset specified by imm8 into r/m64.
PEXTRQ r/m64, xmm2, imm8

VEX.128.66.0F3A.W0 14 /r ib                   MRI        V1/V         AVX          Extract a byte integer value from xmm2 at the
VPEXTRB reg/m8, xmm2, imm8                                                         source byte offset specified by imm8 into reg or
                                                                                   m8. The upper bits of r64/r32 is filled with zeros.
VEX.128.66.0F3A.W0 16 /r ib                   MRI        V/V         AVX           Extract a dword integer value from xmm2 at the
VPEXTRD r32/m32, xmm2, imm8                                                        source dword offset specified by imm8 into
                                                                                   r32/m32.
VEX.128.66.0F3A.W1 16 /r ib                   MRI        V/i         AVX           Extract a qword integer value from xmm2 at the
VPEXTRQ r64/m64, xmm2, imm8                                                        source dword offset specified by imm8 into
                                                                                   r64/m64.
EVEX.128.66.0F3A.WIG 14 /r ib                 T1S-MRI V/V             AVX512BW Extract a byte integer value from xmm2 at the
VPEXTRB reg/m8, xmm2, imm8                                                     source byte offset specified by imm8 into reg or
                                                                               m8. The upper bits of r64/r32 is filled with zeros.
EVEX.128.66.0F3A.W0 16 /r ib                  T1S-MRI V/V             AVX512DQ     Extract a dword integer value from xmm2 at the
VPEXTRD r32/m32, xmm2, imm8                                                        source dword offset specified by imm8 into
                                                                                   r32/m32.
EVEX.128.66.0F3A.W1 16 /r ib                  T1S-MRI V/N.E.1        AVX512DQ      Extract a qword integer value from xmm2 at the
VPEXTRQ r64/m64, xmm2, imm8                                                        source dword offset specified by imm8 into
                                                                                   r64/m64.


NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1 prefix in PEXTRB).
2. VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.




                                                    Instruction Operand Encoding
   Op/En              Operand 1                        Operand 2                    Operand 3                      Operand 4
    MRI             ModRM:r/m (w)                    ModRM:reg (r)                     imm8                            NA


Description
Extract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword offset determined
from imm8[3:0]. The destination can be a register or byte/dword/qword memory location. If the destination is a
register, the upper bits of the register are zero extended.
In legacy non-VEX encoded version and if the destination operand is a register, the default operand size in 64-bit
mode for PEXTRB/PEXTRD is 64 bits, the bits above the least significant byte/dword data are filled with zeros.
PEXTRQ is not encodable in non-64-bit modes and requires REX.W in 64-bit mode.




Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L"L must be
0, otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit
mode for VPEXTRB/VPEXTRD is 64 bits, the bits above the least significant byte/word/dword data are filled with
zeros. Attempt to execute VPEXTRQ in non-64-bit mode will cause #UD.

Operation
CASE of
   PEXTRB: SEL <- COUNT[3:0];
           TEMP <- (Src >> SEL*8) AND FFH;
           IF (DEST = Mem8)
                THEN
                Mem8 <- TEMP[7:0];
           ELSE IF (64-Bit Mode and 64-bit register selected)
                THEN
                     R64[7:0] <- TEMP[7:0];
                     r64[63:8] <- ZERO_FILL; };
           ELSE
                     R32[7:0] <- TEMP[7:0];
                     r32[31:8] <- ZERO_FILL; };
           FI;
   PEXTRD:SEL <- COUNT[1:0];
           TEMP <- (Src >> SEL*32) AND FFFF_FFFFH;
           DEST <- TEMP;
   PEXTRQ: SEL <- COUNT[0];
           TEMP <- (Src >> SEL*64);
           DEST <- TEMP;
EASC:

VPEXTRTD/VPEXTRQ
IF (64-Bit Mode and 64-bit dest operand)
THEN
    Src_Offset <- Imm8[0]
    r64/m64 <-(Src >> Src_Offset * 64)
ELSE
    Src_Offset <- Imm8[1:0]
    r32/m32 <- ((Src >> Src_Offset *32) AND 0FFFFFFFFh);
FI

VPEXTRB ( dest=m8)
SRC_Offset <- Imm8[3:0]
Mem8 <- (Src >> Src_Offset*8)

VPEXTRB ( dest=reg)
IF (64-Bit Mode )
THEN
    SRC_Offset <- Imm8[3:0]
    DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh)
    DEST[63:8] <- ZERO_FILL;
ELSE
    SRC_Offset <-. Imm8[3:0];
    DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh);
    DEST[31:8] <- ZERO_FILL;
FI



Intel C/C++ Compiler Intrinsic Equivalent
PEXTRB:         int _mm_extract_epi8 (__m128i src, const int ndx);
PEXTRD:         int _mm_extract_epi32 (__m128i src, const int ndx);
PEXTRQ:         __int64 _mm_extract_epi64 (__m128i src, const int ndx);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD                    If VEX.L = 1 or EVEX.L'L > 0.
                       If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.
                       If VPEXTRQ in non-64-bit mode, VEX.W=1.






platform: x86_64
mnem: PEXTRW
description:
PEXTRW-Extract Word
 Opcode/                                              Op/     64/32 bit   CPUID      Description
 Instruction                                          En      Mode        Feature
                                                              Support     Flag
 0F C5 /r ib1                                         RMI     V/V         SSE        Extract the word specified by imm8 from mm
 PEXTRW reg, mm, imm8                                                                and move it to reg, bits 15-0. The upper bits of
                                                                                     r32 or r64 is zeroed.
 66 0F C5 /r ib                                       RMI     V/V         SSE2       Extract the word specified by imm8 from xmm
 PEXTRW reg, xmm, imm8                                                               and move it to reg, bits 15-0. The upper bits of
                                                                                     r32 or r64 is zeroed.
 66 0F 3A 15                                          MRI     V/V         SSE4_1     Extract the word specified by imm8 from xmm
 /r ib                                                                               and copy it to lowest 16 bits of reg or m16.
 PEXTRW reg/m16, xmm, imm8                                                           Zero-extend the result in the destination, r32
                                                                                     or r64.
 VEX.128.66.0F.W0 C5 /r ib                            RMI     V2/V        AVX        Extract the word specified by imm8 from
 VPEXTRW reg, xmm1, imm8                                                             xmm1 and move it to reg, bits 15:0. Zero-
                                                                                     extend the result. The upper bits of r64/r32 is
                                                                                     filled with zeros.
 VEX.128.66.0F3A.W0 15 /r ib                          MRI     V/V         AVX        Extract a word integer value from xmm2 at
 VPEXTRW reg/m16, xmm2, imm8                                                         the source word offset specified by imm8 into
                                                                                     reg or m16. The upper bits of r64/r32 is filled
                                                                                     with zeros.
 EVEX.128.66.0F.WIG C5 /r ib                          RMI     V/V         AVX512B    Extract the word specified by imm8 from
 VPEXTRW reg, xmm1, imm8                                                  W          xmm1 and move it to reg, bits 15:0. Zero-
                                                                                     extend the result. The upper bits of r64/r32 is
                                                                                     filled with zeros.
 EVEX.128.66.0F3A.WIG 15 /r ib                        T1S- V/V            AVX512B    Extract a word integer value from xmm2 at
 VPEXTRW reg/m16, xmm2, imm8                          MRI                 W          the source word offset specified by imm8 into
                                                                                     reg or m16. The upper bits of r64/r32 is filled
                                                                                     with zeros.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.
 2. In 64-bit mode, VEX.W1 is ignored for VPEXTRW (similar to legacy REX.W=1 prefix in PEXTRW).



                                                Instruction Operand Encoding
  Op/En               Operand 1                   Operand 2                      Operand 3                      Operand 4
   RMI            ModRM:reg (w)                 ModRM:r/m (r)                       imm8                            NA
   MRI            ModRM:r/m (w)                 ModRM:reg (r)                       imm8                            NA


Description
Copies the word in the source operand (second operand) specified by the count operand (third operand) to the
destination operand (first operand). The source operand can be an MMX technology register or an XMM register.
The destination operand can be the low word of a general-purpose register or a 16-bit memory address. The count
operand is an 8-bit immediate. When specifying a word location in an MMX technology register, the 2 least-signifi-
cant bits of the count operand specify the location; for an XMM register, the 3 least-significant bits specify the loca-
tion. The content of the destination register above bit 16 is cleared (set to all 0s).
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15, R8-15). If the destination operand is a general-purpose register, the default operand size is 64-bits
in 64-bit mode.



Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD. In EVEX.128 encoded versions, EVEX.vvvv is reserved and must be 1111b, EVEX.L must be 0,
otherwise the instruction will #UD. If the destination operand is a register, the default operand size in 64-bit mode
for VPEXTRW is 64 bits, the bits above the least significant byte/word/dword data are filled with zeros.

Operation
IF (DEST = Mem16)
THEN
    SEL <- COUNT[2:0];
    TEMP <- (Src >> SEL*16) AND FFFFH;
    Mem16 <- TEMP[15:0];
ELSE IF (64-Bit Mode and destination is a general-purpose register)
    THEN
         FOR (PEXTRW instruction with 64-bit source operand)
           { SEL <- COUNT[1:0];
             TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
             r64[15:0] <- TEMP[15:0];
             r64[63:16] <- ZERO_FILL; };
         FOR (PEXTRW instruction with 128-bit source operand)
           { SEL <- COUNT[2:0];
             TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
             r64[15:0] <- TEMP[15:0];
             r64[63:16] <- ZERO_FILL; }
    ELSE
         FOR (PEXTRW instruction with 64-bit source operand)
          { SEL <- COUNT[1:0];
             TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
             r32[15:0] <- TEMP[15:0];
             r32[31:16] <- ZERO_FILL; };
         FOR (PEXTRW instruction with 128-bit source operand)
          { SEL <- COUNT[2:0];
             TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
             r32[15:0] <- TEMP[15:0];
             r32[31:16] <- ZERO_FILL; };
    FI;
FI;

VPEXTRW ( dest=m16)
SRC_Offset <- Imm8[2:0]
Mem16 <- (Src >> Src_Offset*16)

VPEXTRW ( dest=reg)
IF (64-Bit Mode )
THEN
    SRC_Offset <- Imm8[2:0]
    DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)
    DEST[63:16] <- ZERO_FILL;
ELSE
    SRC_Offset <- Imm8[2:0]
    DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)
    DEST[31:16] <- ZERO_FILL;
FI





Intel C/C++ Compiler Intrinsic Equivalent
PEXTRW:      int _mm_extract_pi16 (__m64 a, int n)
PEXTRW:      int _mm_extract_epi16 ( __m128i a, int imm)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD                   If VEX.L = 1 or EVEX.L'L > 0.
                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PHADDW
description:
PHADDW/PHADDD - Packed Horizontal Add
Opcode/                                              Op/     64/32 bit   CPUID       Description
Instruction                                          En      Mode        Feature
                                                             Support     Flag
0F 38 01 /r1                                         RM      V/V         SSSE3       Add 16-bit integers horizontally, pack to mm1.
PHADDW mm1, mm2/m64
66 0F 38 01 /r                                       RM      V/V         SSSE3       Add 16-bit integers horizontally, pack to
PHADDW xmm1, xmm2/m128                                                               xmm1.

0F 38 02 /r                                          RM      V/V         SSSE3       Add 32-bit integers horizontally, pack to mm1.
PHADDD mm1, mm2/m64
66 0F 38 02 /r                                       RM      V/V         SSSE3       Add 32-bit integers horizontally, pack to
PHADDD xmm1, xmm2/m128                                                               xmm1.

VEX.NDS.128.66.0F38.WIG 01 /r                        RVM V/V             AVX         Add 16-bit integers horizontally, pack to
VPHADDW xmm1, xmm2, xmm3/m128                                                        xmm1.

VEX.NDS.128.66.0F38.WIG 02 /r                        RVM V/V             AVX         Add 32-bit integers horizontally, pack to
VPHADDD xmm1, xmm2, xmm3/m128                                                        xmm1.

VEX.NDS.256.66.0F38.WIG 01 /r                        RVM V/V             AVX2        Add 16-bit signed integers horizontally, pack
VPHADDW ymm1, ymm2, ymm3/m256                                                        to ymm1.

VEX.NDS.256.66.0F38.WIG 02 /r                        RVM V/V             AVX2        Add 32-bit signed integers horizontally, pack
VPHADDD ymm1, ymm2, ymm3/m256                                                        to ymm1.

NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                       Operand 3                     Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                        NA                             NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                   ModRM:r/m (r)                       NA


Description
(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source and destination operands and
packs the 16-bit signed results to the destination operand (first operand). (V)PHADDD adds two adjacent 32-bit
signed integers horizontally from the source and destination operands and packs the 32-bit signed results to the
destination operand (first operand). When the source operand is a 128-bit memory operand, the operand must be
aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.
Note that these instructions can operate on either unsigned or signed (two's complement notation) integers;
however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected over-
flow conditions, software must control the ranges of the values operated on.
Legacy SSE instructions: Both operands can be MMX registers. The second source operand can be an MMX register
or a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.





VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM
register are zeroed.
VEX.256 encoded version: Horizontal addition of two adjacent data elements of the low 16-bytes of the first and
second source operands are packed into the low 16-bytes of the destination operand. Horizontal addition of two
adjacent data elements of the high 16-bytes of the first and second source operands are packed into the high 16-
bytes of the destination operand. The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.



                    SRC2 Y7 Y6       Y5 Y4   Y3 Y2   Y1 Y0   X7 X6   X5 X4   X3 X2   X1 X0    SRC1




                              S7        S3     S3     S4       S3     S2      S1        S0



                                               255                             0

                                             Dest




                                   Figure 4-10. 256-bit VPHADDD Instruction Operation

Operation
PHADDW (with 64-bit operands)
  mm1[15-0] = mm1[31-16] + mm1[15-0];
  mm1[31-16] = mm1[63-48] + mm1[47-32];
  mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
  mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];

PHADDW (with 128-bit operands)
  xmm1[15-0] = xmm1[31-16] + xmm1[15-0];
  xmm1[31-16] = xmm1[63-48] + xmm1[47-32];
  xmm1[47-32] = xmm1[95-80] + xmm1[79-64];
  xmm1[63-48] = xmm1[127-112] + xmm1[111-96];
  xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];
  xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];
  xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];
  xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];

VPHADDW (VEX.128 encoded version)
DEST[15:0] <- SRC1[31:16] + SRC1[15:0]
DEST[31:16] <- SRC1[63:48] + SRC1[47:32]
DEST[47:32] <- SRC1[95:80] + SRC1[79:64]
DEST[63:48] <- SRC1[127:112] + SRC1[111:96]
DEST[79:64] <- SRC2[31:16] + SRC2[15:0]
DEST[95:80] <- SRC2[63:48] + SRC2[47:32]
DEST[111:96] <- SRC2[95:80] + SRC2[79:64]
DEST[127:112] <- SRC2[127:112] + SRC2[111:96]
DEST[VLMAX-1:128] <- 0



VPHADDW (VEX.256 encoded version)
DEST[15:0] <- SRC1[31:16] + SRC1[15:0]
DEST[31:16] <- SRC1[63:48] + SRC1[47:32]
DEST[47:32] <- SRC1[95:80] + SRC1[79:64]
DEST[63:48] <- SRC1[127:112] + SRC1[111:96]
DEST[79:64] <- SRC2[31:16] + SRC2[15:0]
DEST[95:80] <- SRC2[63:48] + SRC2[47:32]
DEST[111:96] <- SRC2[95:80] + SRC2[79:64]
DEST[127:112] <- SRC2[127:112] + SRC2[111:96]
DEST[143:128] <- SRC1[159:144] + SRC1[143:128]
DEST[159:144] <- SRC1[191:176] + SRC1[175:160]
DEST[175:160] <- SRC1[223:208] + SRC1[207:192]
DEST[191:176] <- SRC1[255:240] + SRC1[239:224]
DEST[207:192] <- SRC2[127:112] + SRC2[143:128]
DEST[223:208] <- SRC2[159:144] + SRC2[175:160]
DEST[239:224] <- SRC2[191:176] + SRC2[207:192]
DEST[255:240] <- SRC2[223:208] + SRC2[239:224]

PHADDD (with 64-bit operands)
  mm1[31-0] = mm1[63-32] + mm1[31-0];
  mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];

PHADDD (with 128-bit operands)
  xmm1[31-0] = xmm1[63-32] + xmm1[31-0];
  xmm1[63-32] = xmm1[127-96] + xmm1[95-64];
  xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];
  xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];

VPHADDD (VEX.128 encoded version)
DEST[31-0] <- SRC1[63-32] + SRC1[31-0]
DEST[63-32] <- SRC1[127-96] + SRC1[95-64]
DEST[95-64] <- SRC2[63-32] + SRC2[31-0]
DEST[127-96] <- SRC2[127-96] + SRC2[95-64]
DEST[VLMAX-1:128] <- 0

VPHADDD (VEX.256 encoded version)
DEST[31-0] <- SRC1[63-32] + SRC1[31-0]
DEST[63-32] <- SRC1[127-96] + SRC1[95-64]
DEST[95-64] <- SRC2[63-32] + SRC2[31-0]
DEST[127-96] <- SRC2[127-96] + SRC2[95-64]
DEST[159-128] <- SRC1[191-160] + SRC1[159-128]
DEST[191-160] <- SRC1[255-224] + SRC1[223-192]
DEST[223-192] <- SRC2[191-160] + SRC2[159-128]
DEST[255-224] <- SRC2[255-224] + SRC2[223-192]

Intel C/C++ Compiler Intrinsic Equivalents
PHADDW:         __m64 _mm_hadd_pi16 (__m64 a, __m64 b)
PHADDD:         __m64 _mm_hadd_pi32 (__m64 a, __m64 b)
(V)PHADDW:      __m128i _mm_hadd_epi16 (__m128i a, __m128i b)
(V)PHADDD:      __m128i _mm_hadd_epi32 (__m128i a, __m128i b)
VPHADDW:        __m256i _mm256_hadd_epi16 (__m256i a, __m256i b)
VPHADDD:        __m256i _mm256_hadd_epi32 (__m256i a, __m256i b)



SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                   If VEX.L = 1.






platform: x86_64
mnem: PHADDSW
description:
PHADDSW - Packed Horizontal Add and Saturate
 Opcode/                                              Op/   64/32 bit   CPUID        Description
 Instruction                                          En    Mode        Feature
                                                            Support     Flag
 0F 38 03 /r1                                         RM    V/V         SSSE3        Add 16-bit signed integers horizontally, pack
 PHADDSW mm1, mm2/m64                                                                saturated integers to mm1.

 66 0F 38 03 /r                                       RM    V/V         SSSE3        Add 16-bit signed integers horizontally, pack
 PHADDSW xmm1, xmm2/m128                                                             saturated integers to xmm1.

 VEX.NDS.128.66.0F38.WIG 03 /r                        RVM V/V           AVX          Add 16-bit signed integers horizontally, pack
 VPHADDSW xmm1, xmm2, xmm3/m128                                                      saturated integers to xmm1.

 VEX.NDS.256.66.0F38.WIG 03 /r                        RVM V/V           AVX2         Add 16-bit signed integers horizontally, pack
 VPHADDSW ymm1, ymm2, ymm3/m256                                                      saturated integers to ymm1.

 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                      Operand 3                     Operand 4
     RM            ModRM:reg (r, w)              ModRM:r/m (r)                       NA                             NA
    RVM             ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                       NA


Description
(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source and destination operands and
saturates the signed results; packs the signed, saturated 16-bit results to the destination operand (first operand)
When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a
64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation
PHADDSW (with 64-bit operands)
  mm1[15-0] = SaturateToSignedWord((mm1[31-16] + mm1[15-0]);
  mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);
  mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);
  mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);





PHADDSW (with 128-bit operands)
  xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);
  xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);
  xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);
  xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);
  xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);
  xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);
  xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);
  xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);

VPHADDSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[VLMAX-1:128] <- 0

VPHADDSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])
DEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])
DEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])
DEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])
DEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])
DEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])
DEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])
DEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])

Intel C/C++ Compiler Intrinsic Equivalent
PHADDSW:         __m64 _mm_hadds_pi16 (__m64 a, __m64 b)
(V)PHADDSW:      __m128i _mm_hadds_epi16 (__m128i a, __m128i b)
VPHADDSW:        __m256i _mm256_hadds_epi16 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                     If VEX.L = 1.






platform: x86_64
mnem: PHMINPOSUW
description:
PHMINPOSUW - Packed Horizontal Word Minimum
 Opcode/                                      Op/   64/32 bit   CPUID        Description
 Instruction                                  En    Mode        Feature
                                                    Support     Flag
 66 0F 38 41 /r                               RM    V/V         SSE4_1       Find the minimum unsigned word in
 PHMINPOSUW xmm1, xmm2/m128                                                  xmm2/m128 and place its value in the low
                                                                             word of xmm1 and its index in the second-
                                                                             lowest word of xmm1.
 VEX.128.66.0F38.WIG 41 /r                    RM    V/V         AVX          Find the minimum unsigned word in
 VPHMINPOSUW xmm1, xmm2/m128                                                 xmm2/m128 and place its value in the low
                                                                             word of xmm1 and its index in the second-
                                                                             lowest word of xmm1.



                                         Instruction Operand Encoding
   Op/En           Operand 1                Operand 2                     Operand 3                   Operand 4
    RM           ModRM:reg (w)            ModRM:r/m (r)                      NA                           NA


Description
Determine the minimum unsigned word value in the source operand (second operand) and place the unsigned
word in the low word (bits 0-15) of the destination operand (first operand). The word index of the minimum value
is stored in bits 16-18 of the destination operand. The remaining upper bits of the destination are set to zero.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is reserved
and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.

Operation
PHMINPOSUW (128-bit Legacy SSE version)
INDEX <- 0;
MIN <- SRC[15:0]
IF (SRC[31:16] < MIN)
    THEN INDEX <- 1; MIN <- SRC[31:16]; FI;
IF (SRC[47:32] < MIN)
    THEN INDEX <- 2; MIN <- SRC[47:32]; FI;
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN)
    THEN INDEX <- 7; MIN <- SRC[127:112]; FI;
DEST[15:0] <- MIN;
DEST[18:16] <- INDEX;
DEST[127:19] <- 0000000000000000000000000000H;





VPHMINPOSUW (VEX.128 encoded version)
INDEX <- 0
MIN <- SRC[15:0]
IF (SRC[31:16] < MIN) THEN INDEX <- 1; MIN <- SRC[31:16]
IF (SRC[47:32] < MIN) THEN INDEX <- 2; MIN <- SRC[47:32]
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN) THEN INDEX <- 7; MIN <- SRC[127:112]
DEST[15:0] <- MIN
DEST[18:16] <- INDEX
DEST[127:19] <- 0000000000000000000000000000H
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
PHMINPOSUW:         __m128i _mm_minpos_epu16( __m128i packed_words);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                    If VEX.L = 1.
                       If VEX.vvvv != 1111B.






platform: x86_64
mnem: PHSUBW
description:
PHSUBW/PHSUBD - Packed Horizontal Subtract
Opcode/                                              Op/     64/32 bit   CPUID       Description
Instruction                                          En      Mode        Feature
                                                             Support     Flag
0F 38 05 /r1                                         RM      V/V         SSSE3       Subtract 16-bit signed integers horizontally,
PHSUBW mm1, mm2/m64                                                                  pack to mm1.

66 0F 38 05 /r                                       RM      V/V         SSSE3       Subtract 16-bit signed integers horizontally,
PHSUBW xmm1, xmm2/m128                                                               pack to xmm1.

0F 38 06 /r                                          RM      V/V         SSSE3       Subtract 32-bit signed integers horizontally,
PHSUBD mm1, mm2/m64                                                                  pack to mm1.

66 0F 38 06 /r                                       RM      V/V         SSSE3       Subtract 32-bit signed integers horizontally,
PHSUBD xmm1, xmm2/m128                                                               pack to xmm1.

VEX.NDS.128.66.0F38.WIG 05 /r                        RVM V/V             AVX         Subtract 16-bit signed integers horizontally,
VPHSUBW xmm1, xmm2, xmm3/m128                                                        pack to xmm1.

VEX.NDS.128.66.0F38.WIG 06 /r                        RVM V/V             AVX         Subtract 32-bit signed integers horizontally,
VPHSUBD xmm1, xmm2, xmm3/m128                                                        pack to xmm1.

VEX.NDS.256.66.0F38.WIG 05 /r                        RVM V/V             AVX2        Subtract 16-bit signed integers horizontally,
VPHSUBW ymm1, ymm2, ymm3/m256                                                        pack to ymm1.

VEX.NDS.256.66.0F38.WIG 06 /r                        RVM V/V             AVX2        Subtract 32-bit signed integers horizontally,
VPHSUBD ymm1, ymm2, ymm3/m256                                                        pack to ymm1.

NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                       Operand 3                     Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                        NA                             NA
   RVM           ModRM:reg (r, w)               VEX.vvvv (r)                   ModRM:r/m (r)                       NA


Description
(V)PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands, and packs
the signed 16-bit results to the destination operand (first operand). (V)PHSUBD performs horizontal subtraction on
each adjacent pair of 32-bit signed integers by subtracting the most significant doubleword from the least signifi-
cant doubleword of each pair, and packs the signed 32-bit result to the destination operand. When the source
operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or a
64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.




VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation
PHSUBW (with 64-bit operands)
  mm1[15-0] = mm1[15-0] - mm1[31-16];
  mm1[31-16] = mm1[47-32] - mm1[63-48];
  mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];
  mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48];

PHSUBW (with 128-bit operands)
  xmm1[15-0] = xmm1[15-0] - xmm1[31-16];
  xmm1[31-16] = xmm1[47-32] - xmm1[63-48];
  xmm1[47-32] = xmm1[79-64] - xmm1[95-80];
  xmm1[63-48] = xmm1[111-96] - xmm1[127-112];
  xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16];
  xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48];
  xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80];
  xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];

VPHSUBW (VEX.128 encoded version)
DEST[15:0] <- SRC1[15:0] - SRC1[31:16]
DEST[31:16] <- SRC1[47:32] - SRC1[63:48]
DEST[47:32] <- SRC1[79:64] - SRC1[95:80]
DEST[63:48] <- SRC1[111:96] - SRC1[127:112]
DEST[79:64] <- SRC2[15:0] - SRC2[31:16]
DEST[95:80] <- SRC2[47:32] - SRC2[63:48]
DEST[111:96] <- SRC2[79:64] - SRC2[95:80]
DEST[127:112] <- SRC2[111:96] - SRC2[127:112]
DEST[VLMAX-1:128] <- 0

VPHSUBW (VEX.256 encoded version)
DEST[15:0] <- SRC1[15:0] - SRC1[31:16]
DEST[31:16] <- SRC1[47:32] - SRC1[63:48]
DEST[47:32] <- SRC1[79:64] - SRC1[95:80]
DEST[63:48] <- SRC1[111:96] - SRC1[127:112]
DEST[79:64] <- SRC2[15:0] - SRC2[31:16]
DEST[95:80] <- SRC2[47:32] - SRC2[63:48]
DEST[111:96] <- SRC2[79:64] - SRC2[95:80]
DEST[127:112] <- SRC2[111:96] - SRC2[127:112]
DEST[143:128] <- SRC1[143:128] - SRC1[159:144]
DEST[159:144] <- SRC1[175:160] - SRC1[191:176]
DEST[175:160] <- SRC1[207:192] - SRC1[223:208]
DEST[191:176] <- SRC1[239:224] - SRC1[255:240]
DEST[207:192] <- SRC2[143:128] - SRC2[159:144]
DEST[223:208] <- SRC2[175:160] - SRC2[191:176]
DEST[239:224] <- SRC2[207:192] - SRC2[223:208]
DEST[255:240] <- SRC2[239:224] - SRC2[255:240]

PHSUBD (with 64-bit operands)
  mm1[31-0] = mm1[31-0] - mm1[63-32];
  mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];




PHSUBD (with 128-bit operands)
  xmm1[31-0] = xmm1[31-0] - xmm1[63-32];
  xmm1[63-32] = xmm1[95-64] - xmm1[127-96];
  xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];
  xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96];

VPHSUBD (VEX.128 encoded version)
DEST[31-0] <- SRC1[31-0] - SRC1[63-32]
DEST[63-32] <- SRC1[95-64] - SRC1[127-96]
DEST[95-64] <- SRC2[31-0] - SRC2[63-32]
DEST[127-96] <- SRC2[95-64] - SRC2[127-96]
DEST[VLMAX-1:128] <- 0

VPHSUBD (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC1[63:32]
DEST[63:32] <- SRC1[95:64] - SRC1[127:96]
DEST[95:64] <- SRC2[31:0] - SRC2[63:32]
DEST[127:96] <- SRC2[95:64] - SRC2[127:96]
DEST[159:128] <- SRC1[159:128] - SRC1[191:160]
DEST[191:160] <- SRC1[223:192] - SRC1[255:224]
DEST[223:192] <- SRC2[159:128] - SRC2[191:160]
DEST[255:224] <- SRC2[223:192] - SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalents
PHSUBW:         __m64 _mm_hsub_pi16 (__m64 a, __m64 b)
PHSUBD:         __m64 _mm_hsub_pi32 (__m64 a, __m64 b)
(V)PHSUBW:      __m128i _mm_hsub_epi16 (__m128i a, __m128i b)
(V)PHSUBD:      __m128i _mm_hsub_epi32 (__m128i a, __m128i b)
VPHSUBW:        __m256i _mm256_hsub_epi16 (__m256i a, __m256i b)
VPHSUBD:        __m256i _mm256_hsub_epi32 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                    If VEX.L = 1.






platform: x86_64
mnem: PHSUBSW
description:
PHSUBSW - Packed Horizontal Subtract and Saturate
 Opcode/                                                 Op/     64/32 bit   CPUID        Description
 Instruction                                             En      Mode        Feature
                                                                 Support     Flag
 0F 38 07 /r1                                            RM      V/V         SSSE3        Subtract 16-bit signed integer horizontally,
 PHSUBSW mm1, mm2/m64                                                                     pack saturated integers to mm1.

 66 0F 38 07 /r                                          RM      V/V         SSSE3        Subtract 16-bit signed integer horizontally,
 PHSUBSW xmm1, xmm2/m128                                                                  pack saturated integers to xmm1.

 VEX.NDS.128.66.0F38.WIG 07 /r                           RVM V/V             AVX          Subtract 16-bit signed integer horizontally,
 VPHSUBSW xmm1, xmm2, xmm3/m128                                                           pack saturated integers to xmm1.

 VEX.NDS.256.66.0F38.WIG 07 /r                           RVM V/V             AVX2         Subtract 16-bit signed integer horizontally,
 VPHSUBSW ymm1, ymm2, ymm3/m256                                                           pack saturated integers to ymm1.

 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                    Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                       Operand 3                      Operand 4
    RM            ModRM:reg (r, w)                  ModRM:r/m (r)                        NA                             NA
    RVM           ModRM:reg (r, w)                  VEX.vvvv (r)                    ModRM:r/m (r)                       NA


Description
(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed integers by subtracting the
most significant word from the least significant word of each pair in the source and destination operands. The
signed, saturated 16-bit results are packed to the destination operand (first operand). When the source operand is
a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception
(#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand can be an MMX register or
a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
In 64-bit mode, use the REX prefix to access additional registers.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand can be an YMM register or a 256-bit memory location.
Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation
PHSUBSW (with 64-bit operands)
  mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);
  mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);
  mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);
  mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);




PHSUBSW (with 128-bit operands)
  xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]);
  xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);
  xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);
  xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);
  xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]);
  xmm1[95-80] =SaturateToSignedWord(xmm2/m128[47-32] - xmm2/m128[63-48]);
  xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);
  xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);

VPHSUBSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[VLMAX-1:128] <- 0

VPHSUBSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[143:128]= SaturateToSignedWord(SRC1[143:128] - SRC1[159:144])
DEST[159:144] = SaturateToSignedWord(SRC1[175:160] - SRC1[191:176])
DEST[175:160] = SaturateToSignedWord(SRC1[207:192] - SRC1[223:208])
DEST[191:176] = SaturateToSignedWord(SRC1[239:224] - SRC1[255:240])
DEST[207:192] = SaturateToSignedWord(SRC2[143:128] - SRC2[159:144])
DEST[223:208] = SaturateToSignedWord(SRC2[175:160] - SRC2[191:176])
DEST[239:224] = SaturateToSignedWord(SRC2[207:192] - SRC2[223:208])
DEST[255:240] = SaturateToSignedWord(SRC2[239:224] - SRC2[255:240])

Intel C/C++ Compiler Intrinsic Equivalent
PHSUBSW:         __m64 _mm_hsubs_pi16 (__m64 a, __m64 b)
(V)PHSUBSW:      __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
VPHSUBSW:        __m256i _mm256_hsubs_epi16 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                  If VEX.L = 1.






platform: x86_64
mnem: PINSRB
description:
PINSRB/PINSRD/PINSRQ - Insert Byte/Dword/Qword
Opcode/                                            Op/ En 64/32 bit      CPUID        Description
Instruction                                               Mode           Feature
                                                          Support        Flag
66 0F 3A 20 /r ib                                  RMI       V/V         SSE4_1       Insert a byte integer value from r32/m8 into
PINSRB xmm1, r32/m8, imm8                                                             xmm1 at the destination element in xmm1
                                                                                      specified by imm8.
66 0F 3A 22 /r ib                                  RMI       V/V         SSE4_1       Insert a dword integer value from r/m32 into
PINSRD xmm1, r/m32, imm8                                                              the xmm1 at the destination element
                                                                                      specified by imm8.
66 REX.W 0F 3A 22 /r ib                            RMI       V/N. E.     SSE4_1       Insert a qword integer value from r/m64 into
PINSRQ xmm1, r/m64, imm8                                                              the xmm1 at the destination element
                                                                                      specified by imm8.
VEX.NDS.128.66.0F3A.W0 20 /r ib                    RVMI      V1/V        AVX          Merge a byte integer value from r32/m8 and
VPINSRB xmm1, xmm2, r32/m8, imm8                                                      rest from xmm2 into xmm1 at the byte offset
                                                                                      in imm8.
VEX.NDS.128.66.0F3A.W0 22 /r ib                    RVMI      V/V         AVX          Insert a dword integer value from r32/m32
VPINSRD xmm1, xmm2, r/m32, imm8                                                       and rest from xmm2 into xmm1 at the dword
                                                                                      offset in imm8.
VEX.NDS.128.66.0F3A.W1 22 /r ib                    RVMI      V/I         AVX          Insert a qword integer value from r64/m64
VPINSRQ xmm1, xmm2, r/m64, imm8                                                       and rest from xmm2 into xmm1 at the qword
                                                                                      offset in imm8.
EVEX.NDS.128.66.0F3A.WIG 20 /r ib                  T1S-      V/V         AVX512BW Merge a byte integer value from r32/m8 and
VPINSRB xmm1, xmm2, r32/m8, imm8                   RVMI                           rest from xmm2 into xmm1 at the byte offset
                                                                                  in imm8.
EVEX.NDS.128.66.0F3A.W0 22 /r ib                   T1S-      V/V         AVX512DQ     Insert a dword integer value from r32/m32
VPINSRD xmm1, xmm2, r32/m32, imm8                  RVMI                               and rest from xmm2 into xmm1 at the dword
                                                                                      offset in imm8.
EVEX.NDS.128.66.0F3A.W1 22 /r ib                   T1S-      V/N.E.1     AVX512DQ     Insert a qword integer value from r64/m64
VPINSRQ xmm1, xmm2, r64/m64, imm8                  RVMI                               and rest from xmm2 into xmm1 at the qword
                                                                                      offset in imm8.
NOTES:
1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1 prefix with PINSRB).



                                                 Instruction Operand Encoding
     Op/En                Operand 1                       Operand 2                    Operand 3                  Operand 4
      RMI               ModRM:reg (w)                  ModRM:r/m (r)                     imm8                         NA
     RVMI               ModRM:reg (w)                    VEX.vvvv (r)                ModRM:r/m (r)                  imm8
   T1S-RVMI             ModRM:reg (w)                    EVEX.vvvv (r)               ModRM:r/m (r)                  Imm8


Description
Copies a byte/dword/qword from the source operand (second operand) and inserts it in the destination operand
(first operand) at the location specified with the count operand (third operand). (The other elements in the desti-
nation register are left untouched.) The source operand can be a general-purpose register or a memory location.
(When the source operand is a general-purpose register, PINSRB copies the low byte of the register.) The destina-
tion operand is an XMM register. The count operand is an 8-bit immediate. When specifying a qword[dword, byte]
location in an XMM register, the [2, 4] least-significant bit(s) of the count operand specify the location.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15, R8-15). Use of REX.W permits the use of 64 bit general purpose regis-
ters.



128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. VEX.L must be 0, otherwise
the instruction will #UD. Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.
EVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L'L must be 0, other-
wise the instruction will #UD.

Operation
CASE OF
   PINSRB: SEL <- COUNT[3:0];
           MASK <- (0FFH << (SEL * 8));
           TEMP <- (((SRC[7:0] << (SEL *8)) AND MASK);
   PINSRD: SEL <- COUNT[1:0];
           MASK <- (0FFFFFFFFH << (SEL * 32));
           TEMP <- (((SRC << (SEL *32)) AND MASK) ;
   PINSRQ: SEL <- COUNT[0]
           MASK <- (0FFFFFFFFFFFFFFFFH << (SEL * 64));
           TEMP <- (((SRC << (SEL *64)) AND MASK) ;
ESAC;
       DEST <- ((DEST AND NOT MASK) OR TEMP);

VPINSRB (VEX/EVEX encoded version)
SEL <- imm8[3:0]
DEST[127:0] <- write_b_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

VPINSRD (VEX/EVEX encoded version)
SEL <- imm8[1:0]
DEST[127:0] <- write_d_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

VPINSRQ (VEX/EVEX encoded version)
SEL <- imm8[0]
DEST[127:0] <- write_q_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
PINSRB:         __m128i _mm_insert_epi8 (__m128i s1, int s2, const int ndx);
PINSRD:         __m128i _mm_insert_epi32 (__m128i s2, int s, const int ndx);
PINSRQ:         __m128i _mm_insert_epi64(__m128i s2, __int64 s, const int ndx);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.




#UD                    If VEX.L = 1 or EVEX.L'L > 0.
                       If VPINSRQ in non-64-bit mode with VEX.W=1.






platform: x86_64
mnem: PINSRW
description:
PINSRW-Insert Word
Opcode/                                            Op/ En 64/32 bit     CPUID         Description
Instruction                                               Mode          Feature
                                                          Support       Flag
0F C4 /r ib1                                       RMI      V/V         SSE           Insert the low word from r32 or from m16
PINSRW mm, r32/m16, imm8                                                              into mm at the word position specified by
                                                                                      imm8.
66 0F C4 /r ib                                     RMI      V/V         SSE2          Move the low word of r32 or from m16 into
PINSRW xmm, r32/m16, imm8                                                             xmm at the word position specified by imm8.

VEX.NDS.128.66.0F.W0 C4 /r ib                      RVMI     V2/V        AVX           Insert a word integer value from r32/m16
VPINSRW xmm1, xmm2, r32/m16, imm8                                                     and rest from xmm2 into xmm1 at the word
                                                                                      offset in imm8.
EVEX.NDS.128.66.0F.WIG C4 /r ib                    T1S-     V/V         AVX512BW Insert a word integer value from r32/m16 and
VPINSRW xmm1, xmm2, r32/m16, imm8                  RVMI                          rest from xmm2 into xmm1 at the word
                                                                                 offset in imm8.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.
2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar to legacy REX.W=1 prefix in PINSRW).



                                                Instruction Operand Encoding
    Op/En              Operand 1                     Operand 2                     Operand 3                    Operand 4
     RMI             ModRM:reg (w)                 ModRM:r/m (r)                      imm8                         NA
    RVMI             ModRM:reg (w)                  VEX.vvvv (r)                  ModRM:r/m (r)                   imm8
  T1S-RVMI           ModRM:reg (w)                  EVEX.vvvv (r)                 ModRM:r/m (r)                   Imm8


Description
Copies a word from the source operand (second operand) and inserts it in the destination operand (first operand)
at the location specified with the count operand (third operand). (The other words in the destination register are
left untouched.) The source operand can be a general-purpose register or a 16-bit memory location. (When the
source operand is a general-purpose register, the low word of the register is copied.) The destination operand can
be an MMX technology register or an XMM register. The count operand is an 8-bit immediate. When specifying a
word location in an MMX technology register, the 2 least-significant bits of the count operand specify the location;
for an XMM register, the 3 least-significant bits specify the location.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15, R8-15).
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.L must be 0, other-
wise the instruction will #UD.
EVEX.128 encoded version: Bits (VLMAX-1:128) of the destination register are zeroed. EVEX.L'L must be 0, other-
wise the instruction will #UD.

Operation
PINSRW (with 64-bit source operand)
   SEL <- COUNT AND 3H;
       CASE (Determine word position) OF
           SEL <- 0:     MASK <- 000000000000FFFFH;



           SEL <- 1:   MASK <- 00000000FFFF0000H;
           SEL <- 2:   MASK <- 0000FFFF00000000H;
           SEL <- 3:   MASK <- FFFF000000000000H;
   DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);

PINSRW (with 128-bit source operand)
   SEL <- COUNT AND 7H;
       CASE (Determine word position) OF
           SEL <- 0:     MASK <- 0000000000000000000000000000FFFFH;
           SEL <- 1:     MASK <- 000000000000000000000000FFFF0000H;
           SEL <- 2:     MASK <- 00000000000000000000FFFF00000000H;
           SEL <- 3:     MASK <- 0000000000000000FFFF000000000000H;
           SEL <- 4:     MASK <- 000000000000FFFF0000000000000000H;
           SEL <- 5:     MASK <- 00000000FFFF00000000000000000000H;
           SEL <- 6:     MASK <- 0000FFFF000000000000000000000000H;
           SEL <- 7:     MASK <- FFFF0000000000000000000000000000H;
   DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);

VPINSRW (VEX/EVEX encoded version)
SEL <- imm8[2:0]
DEST[127:0] <- write_w_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
PINSRW:         __m64 _mm_insert_pi16 (__m64 a, int d, int n)
PINSRW:         __m128i _mm_insert_epi16 ( __m128i a, int b, int imm)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD                   If VEX.L = 1 or EVEX.L'L > 0.






