# instructions

platform: x86
mnem: VFNMADD132SS
description:
VFNMADD132SS/VFNMADD213SS/VFNMADD231SS  -  Fused Negative Multiply-Add of Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W0 9D /r VFNMADD132SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm0 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and add to           
|                                              |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W0 AD /r VFNMADD213SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm0 and xmm1, negate the           
|                                              |      |                |                   | multiplication result and add to xmm2/mem      
|                                              |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W0 BD /r VFNMADD231SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm1 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and add to           
|                                              |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMADD132SS: Multiplies the low packed single-precision floating-point value
from the first source operand to the low packed single-precision floating-point
value in the third source operand, adds the negated infinite precision intermediate
result to the low packed single-precision floating-point value in the second
source operand, performs rounding and stores the resulting packed single-precision
floating-point value to the destination operand (first source operand). VFNMADD213SS:
Multiplies the low packed single-precision floating-point value from the second
source operand to the low packed single-precision floating-point value in the
first source operand, adds the negated infinite precision intermediate result
to the low packed single-precision floating-point value in the third source
operand, performs rounding and stores the resulting packed single-precision
floating-point value to the destination operand (first source operand). VFNMADD231SS:
Multiplies the low packed single-precision floating-point value from the second
source operand to the low packed single-precision floating-point value in the
third source operand, adds the negated infinite precision intermediate result
to the low packed single-precision floating-point value in the first source
operand, performs rounding and stores the resulting packed single-precision
floating-point value to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 32-bit
memory location and encoded in rm_field. The upper bits ([VLMAX-1:128]) of the
YMM destination register are zeroed. Compiler tools may optionally support a
complementary mnemonic for each instruction mnemonic listed in the opcode/instruction
column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined
in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction
Operand Order and Arithmetic Behavior” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMADD132SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) + SRC2[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFNMADD213SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) + SRC3[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFNMADD231SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[63:0]) + DEST[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMADD132SS: __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);

VFNMADD213SS: __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);

VFNMADD231SS: __m128 _mm_fnmadd_ss (__m128 a, __m128 b, __m128 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFNMSUB132PD
description:
VFNMSUB132PD/VFNMSUB213PD/VFNMSUB231PD  -  Fused Negative Multiply-Subtract of Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                       | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 9E /r VFNMSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W1 AE /r VFNMSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm1, negate the          
|                                          |      |                |                   | multiplication result and subtract xmm2/mem    
|                                          |      |                |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W1 BE /r VFNMSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm1 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W1 9E /r VFNMSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W1 AE /r VFNMSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm1, negate the          
|                                          |      |                |                   | multiplication result and subtract ymm2/mem    
|                                          |      |                |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.W1 BE /r VFNMSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm1 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMSUB132PD: Multiplies the two or four packed double-precision floating-point
values from the first source operand to the two or four packed double-precision
floating-point values in the third source operand. From negated infinite precision
intermediate results, subtracts the two or four packed double-precision floating-point
values in the second source operand, performs rounding and stores the resulting
two or four packed double-precision floating-point values to the destination
operand (first source operand). VFMSUB213PD: Multiplies the two or four packed
double-precision floating-point values from the second source operand to the
two or four packed double-precision floating-point values in the first source
operand. From negated infinite precision intermediate results, subtracts the
two or four packed double-precision floating-point values in the third source
operand, performs rounding and stores the resulting two or four packed double-precision
floatingpoint values to the destination operand (first source operand). VFMSUB231PD:
Multiplies the two or four packed double-precision floating-point values from
the second source to the two or four packed double-precision floating-point
values in the third source operand. From negated infinite precision intermediate
results, subtracts the two or four packed double-precision floating-point values
in the first source operand, performs rounding and stores the resulting two
or four packed double-precision floating-point values to the destination operand
(first source operand).

VEX.128 encoded version: The destination operand (also first source operand)
is a XMM register and encoded in reg_field. The second source operand is a XMM
register and encoded in VEX.vvvv. The third source operand is a

XMM register or a 128-bit memory location and encoded in rm_field. The upper
128 bits of the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMSUB132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR( - (DEST[n+63:n]*SRC3[n+63:n]) - SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFNMSUB213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*DEST[n+63:n]) - SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFNMSUB231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR( - (SRC2[n+63:n]*SRC3[n+63:n]) - DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMSUB132PD: __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);

VFNMSUB213PD: __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);

VFNMSUB231PD: __m128d _mm_fnmsub_pd (__m128d a, __m128d b, __m128d c);

VFNMSUB132PD: __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);

VFNMSUB213PD: __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);

VFNMSUB231PD: __m256d _mm256_fnmsub_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFNMSUB132PS
description:
VFNMSUB132PS/VFNMSUB213PS/VFNMSUB231PS  -  Fused Negative Multiply-Subtract of Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                       | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 9E /r VFNMSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W0 AE /r VFNMSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm1, negate the          
|                                          |      |                |                   | multiplication result and subtract xmm2/mem    
|                                          |      |                |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W0 BE /r VFNMSUB231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm1 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W0 9E /r VFNMSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W0 AE /r VFNMSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm1, negate the          
|                                          |      |                |                   | multiplication result and subtract ymm2/mem    
|                                          |      |                |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.0 BE /r VFNMSUB231PS | A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm1 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and subtract         
|                                          |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMSUB132PS: Multiplies the four or eight packed single-precision floating-point
values from the first source operand to the four or eight packed single-precision
floating-point values in the third source operand. From negated infinite precision
intermediate results, subtracts the four or eight packed single-precision floating-point
values in the second source operand, performs rounding and stores the resulting
four or eight packed single-precision floating-point values to the destination
operand (first source operand). VFNMSUB213PS: Multiplies the four or eight packed
single-precision floating-point values from the second source operand to the
four or eight packed single-precision floating-point values in the first source
operand. From negated infinite precision intermediate results, subtracts the
four or eight packed single-precision floating-point values in the third source
operand, performs rounding and stores the resulting four or eight packed single-precision
floatingpoint values to the destination operand (first source operand). VFNMSUB231PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source to the four or eight packed single-precision floating-point
values in the third source operand. From negated infinite precision intermediate
results, subtracts the four or eight packed single-precision floating-point
values in the first source operand, performs rounding and stores the resulting
four or eight packed single-precision floating-point values to the destination
operand (first source operand). VEX.128 encoded version: The destination operand
(also first source operand) is a XMM register and encoded in reg_field. The
second source operand is a XMM register and encoded in VEX.vvvv. The third source
operand is a

XMM register or a 128-bit memory location and encoded in rm_field. The upper
128 bits of the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMSUB132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR( - (DEST[n+31:n]*SRC3[n+31:n]) - SRC2[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFNMSUB213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*DEST[n+31:n]) - SRC3[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFNMSUB231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR( - (SRC2[n+31:n]*SRC3[n+31:n]) - DEST[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMSUB132PS: __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);

VFNMSUB213PS: __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);

VFNMSUB231PS: __m128 _mm_fnmsub_ps (__m128 a, __m128 b, __m128 c);

VFNMSUB132PS: __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);

VFNMSUB213PS: __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);

VFNMSUB231PS: __m256 _mm256_fnmsub_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFNMSUB132SD
description:
VFNMSUB132SD/VFNMSUB213SD/VFNMSUB231SD  -  Fused Negative Multiply-Subtract of Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W1 9F /r VFNMSUB132SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |              |                   | value from xmm0 and xmm2/mem, negate           
|                                              |      |              |                   | the multiplication result and subtract         
|                                              |      |              |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W1 AF /r VFNMSUB213SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |              |                   | value from xmm0 and xmm1, negate the           
|                                              |      |              |                   | multiplication result and subtract xmm2/mem    
|                                              |      |              |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W1 BF /r VFNMSUB231SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |              |                   | value from xmm1 and xmm2/mem, negate           
|                                              |      |              |                   | the multiplication result and subtract         
|                                              |      |              |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMSUB132SD: Multiplies the low packed double-precision floating-point value
from the first source operand to the low packed double-precision floating-point
value in the third source operand. From negated infinite precision intermediate
result, subtracts the low double-precision floating-point value in the second
source operand, performs rounding and stores the resulting packed double-precision
floating-point value to the destination operand (first source operand). VFNMSUB213SD:
Multiplies the low packed double-precision floating-point value from the second
source operand to the low packed double-precision floating-point value in the
first source operand. From negated infinite precision intermediate result, subtracts
the low double-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed double-precision floating-point value
to the destination operand (first source operand). VFNMSUB231SD: Multiplies
the low packed double-precision floating-point value from the second source
to the low packed double-precision floating-point value in the third source
operand. From negated infinite precision intermediate result, subtracts the
low double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value
to the destination operand (first source operand). VEX.128 encoded version:
The destination operand (also first source operand) is a XMM register and encoded
in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv.
The third source operand is a XMM register or a 64-bit memory location and encoded
in rm_field. The upper bits ([VLMAX-1:128]) of the YMM destination register
are zeroed. Compiler tools may optionally support a complementary mnemonic for
each instruction mnemonic listed in the opcode/instruction column of the summary
table. The behavior of the complementary mnemonic in situations involving NANs
are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic
Behavior” in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMSUB132SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) - SRC2[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFNMSUB213SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) - SRC3[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFNMSUB231SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) - DEST[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMSUB132SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

VFNMSUB213SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);

VFNMSUB231SD: __m128d _mm_fnmsub_sd (__m128d a, __m128d b, __m128d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFNMSUB132SS
description:
VFNMSUB132SS/VFNMSUB213SS/VFNMSUB231SS  -  Fused Negative Multiply-Subtract of Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W0 9F /r VFNMSUB132SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm0 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and subtract         
|                                              |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W0 AF /r VFNMSUB213SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm0 and xmm1, negate the           
|                                              |      |                |                   | multiplication result and subtract xmm2/mem    
|                                              |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W0 BF /r VFNMSUB231SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                         |      |                |                   | value from xmm1 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and subtract         
|                                              |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMSUB132SS: Multiplies the low packed single-precision floating-point value
from the first source operand to the low packed single-precision floating-point
value in the third source operand. From negated infinite precision intermediate
result, the low single-precision floating-point value in the second source operand,
performs rounding and stores the resulting packed single-precision floating-point
value to the destination operand (first source operand). VFNMSUB213SS: Multiplies
the low packed single-precision floating-point value from the second source
operand to the low packed single-precision floating-point value in the first
source operand. From negated infinite precision intermediate result, the low
single-precision floating-point value in the third source operand, performs
rounding and stores the resulting packed single-precision floating-point value
to the destination operand (first source operand). VFNMSUB231SS: Multiplies
the low packed single-precision floating-point value from the second source
to the low packed single-precision floating-point value in the third source
operand. From negated infinite precision intermediate result, the low single-precision
floating-point value in the first source operand, performs rounding and stores
the resulting packed single-precision floating-point value to the destination
operand (first source operand). VEX.128 encoded version: The destination operand
(also first source operand) is a XMM register and encoded in reg_field. The
second source operand is a XMM register and encoded in VEX.vvvv. The third source
operand is a XMM register or a 32-bit memory location and encoded in rm_field.
The upper bits ([VLMAX-1:128]) of the YMM destination register are zeroed. Compiler
tools may optionally support a complementary mnemonic for each instruction mnemonic
listed in the opcode/instruction column of the summary table. The behavior of
the complementary mnemonic in situations involving NANs are governed by the
definition of the instruction mnemonic defined in the opcode/instruction column.
See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMSUB132SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (DEST[31:0]*SRC3[31:0]) - SRC2[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFNMSUB213SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (SRC2[31:0]*DEST[31:0]) - SRC3[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFNMSUB231SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(- (SRC2[31:0]*SRC3[63:0]) - DEST[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMSUB132SS: __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);

VFNMSUB213SS: __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);

VFNMSUB231SS: __m128 _mm_fnmsub_ss (__m128 a, __m128 b, __m128 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VGATHERDPD
description:
VGATHERDPD/VGATHERQPD  -  Gather Packed DP FP Values Using Signed Dword/Qword Indices:
| Opcode/Instruction                     | Op/En| 64/3 2-bit Mode| CPUID Feature Flag| Description                             
| VEX.DDS.128.66.0F38.W1 92 /r VGATHERDPD| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x, 
| xmm1, vm32x, xmm2                      |      |                |                   | gather double-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by xmm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into xmm1.                   
| VEX.DDS.128.66.0F38.W1 93 /r VGATHERQPD| RMV  | V/V            | AVX2              | Using qword indices specified in vm64x, 
| xmm1, vm64x, xmm2                      |      |                |                   | gather double-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by xmm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into xmm1.                   
| VEX.DDS.256.66.0F38.W1 92 /r VGATHERDPD| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x, 
| ymm1, vm32x, ymm2                      |      |                |                   | gather double-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by ymm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into ymm1.                   
| VEX.DDS.256.66.0F38.W1 93 /r VGATHERQPD| RMV  | V/V            | AVX2              | Using qword indices specified in vm64y, 
| ymm1, vm64y, ymm2                      |      |                |                   | gather double-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by ymm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into ymm1.                   

Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2                            | Operand 3      | Operand 4
| RMV  | ModRM:reg (r,w)| BaseReg (R): VSIB:base, VectorReg(R):| VEX.vvvv (r, w)| NA       
|      |                | VSIB:index                           |                |          

Description:
The instruction conditionally loads up to 2 or 4 double-precision floating-point
values from memory addresses specified by the memory operand (the second operand)
and using qword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register
for an array of indices relative to the base and a constant scale factor. The
mask operand (the third operand) specifies the conditional load operation from
each memory address and the corresponding update of each data element of the
destination operand (the first operand). Conditionality is specified by the
most significant bit of each data element of the mask register. If an element's
mask bit is not set, the corresponding element of the destination register is
left unchanged. The width of data element in the destination register and mask
register are identical. The entire mask register will be set to zero by this
instruction unless the instruction causes an exception. Using dword indices
in the lower half of the mask register, the instruction conditionally loads
up to 2 or 4 doubleprecision floating-point values from the VSIB addressing
memory operand, and updates the destination register. This instruction can be
suspended by an exception if at least one element is already gathered (i.e.,
if the exception

| is triggered by an element other than       | When this happens, the destination If 
| the rightmost one with its mask bit         | any traps or interrupts are pending   
| set). register and the mask operand         | from already gathIt may do this to one
| are partially updated; those elements       | or both                               
| that have been gathered are placed into     |                                       
| the destination register and have their     |                                       
| mask bits set to zero. ered elements,       |                                       
| they will be delivered in lieu of the       |                                       
| exception; in this case, EFLAG.RF is        |                                       
| set to one so an instruction breakpoint     |                                       
| is not re-triggered when the instruction    |                                       
| is continued. If the data size and index    |                                       
| size are different, part of the destination |                                       
| register and part of the mask register      |                                       
| do not correspond to any elements being     |                                       
| gathered. of those registers even if        |                                       
| the instruction triggers an exception,      |                                       
| and even if the instruction triggers        |                                       
| the exception before gathering any elements.|                                       
| VEX.128 version: The instruction will       | For dword indices, only the           
| gather two double-precision floating-point  |                                       
| values.                                     |                                       
lower two indices in the vector index register are used.

| VEX.256 version: The instruction will        | For dword indices, only If any pair         
| gather four double-precision floating-point  | of the index, mask, or destination registers
| values. the lower four indices in the        | are the same, this instruction results      
| vector index register are used. Note         | a #UD fault.                                
| that: •                                      |                                             
| •64 memory-ordering model. •                 | Memory ordering with other instructions     
|                                              | follows the IntelThat is, if a fault        
|                                              | is triggered by an element and delivered,   
|                                              | all                                         
| elements closer to the LSB of the destination| Individual elements closer If a given       
| will be completed (and non-faulting).        | element triggers multiple faults, they      
| to the MSB may or may not be completed.      | are delivered in the Elements may be        
| conventional order. •                        | gathered in any order, but faults must      
|                                              | be delivered in a right-to-left order;      
|                                              | thus, elements to                           
| the left of a faulting one may be gathered   | A given implementation of this This         
| before the fault is delivered. instruction   | instruction does not perform AC checks,     
| is repeatable - given the same input         | and so will never deliver an AC fault.      
| values and architectural state, the          |                                             
| same set of elements to the left of          |                                             
| the faulting one will be gathered. •         |                                             
| •                                            | This instruction will cause a #UD if        
|                                              | the address size attribute is 16-bit.       
| •                                            | This instruction will cause a #UD if        
|                                              | the memory operand is encoded without       
|                                              | the SIB byte.                               
| •is implementation specific, and some        | This instruction should not be used         
| implementations may use loads larger         | to access memory mapped I/O as the ordering 
| than the data element size or load elements  | of the individual loads it does The         
| an indeterminate number of times. •          | scaled index may require more bits to       
|                                              | represent than the address bits used        
|                                              | by the processor (e.g., in 32-              
| bit mode, if the scale is greater than       | In this case, the most significant bits     
| one). bits are ignored.                      | beyond the number of address                
Operation:

DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;
VGATHERDPD (VEX.128 version)
FOR j<- 0 to 1
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 1
  k <- j * 32;
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63: i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VGATHERQPD (VEX.128 version)
FOR j<- 0 to 1
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 1
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits this instruction
  FI;
  MASK[i +63: i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VGATHERQPD (VEX.256 version)
FOR j<- 0 to 3
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63: i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element
VGATHERDPD (VEX.256 version)
FOR j<- 0 to 3
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  k <- j * 32;
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element

Intel C/C++ Compiler Intrinsic Equivalent:
VGATHERDPD: __m128d _mm_i32gather_pd (double const * base, __m128i index, const
int scale);

VGATHERDPD: __m128d _mm_mask_i32gather_pd (__m128d src, double const * base,
__m128i index, __m128d mask, const int scale);

VGATHERDPD: __m256d _mm256_i32gather_pd (double const * base, __m128i index,
const int scale);

VGATHERDPD: __m256d _mm256_mask_i32gather_pd (__m256d src, double const * base,
__m128i index, __m256d mask, const int scale);

VGATHERQPD: __m128d _mm_i64gather_pd (double const * base, __m128i index, const
int scale);

VGATHERQPD: __m128d _mm_mask_i64gather_pd (__m128d src, double const * base,
__m128i index, __m128d mask, const int scale);

VGATHERQPD: __m256d _mm256_i64gather_pd (double const * base, __m256i index,
const int scale);

VGATHERQPD: __m256d _mm256_mask_i64gather_pd (__m256d src, double const * base,
__m256i index, __m256d mask, const int scale);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 12


platform: x86
mnem: VGATHERDPS
description:
VGATHERDPS/VGATHERQPS  -  Gather Packed SP FP values Using Signed Dword/Qword Indices:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.DDS.128.66.0F38.W0 92 /r VGATHERDPS| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x, 
| xmm1, vm32x, xmm2                      |      |                |                   | gather single-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by xmm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into xmm1.                   
| VEX.DDS.128.66.0F38.W0 93 /r VGATHERQPS| RMV  | V/V            | AVX2              | Using qword indices specified in vm64x, 
| xmm1, vm64x, xmm2                      |      |                |                   | gather single-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by xmm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into xmm1.                   
| VEX.DDS.256.66.0F38.W0 92 /r VGATHERDPS| RMV  | V/V            | AVX2              | Using dword indices specified in vm32y, 
| ymm1, vm32y, ymm2                      |      |                |                   | gather single-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by ymm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into ymm1.                   
| VEX.DDS.256.66.0F38.W0 93 /r VGATHERQPS| RMV  | V/V            | AVX2              | Using qword indices specified in vm64y, 
| xmm1, vm64y, xmm2                      |      |                |                   | gather single-precision FP values from  
|                                        |      |                |                   | memory conditioned on mask specified    
|                                        |      |                |                   | by xmm2. Conditionally gathered elements
|                                        |      |                |                   | are merged into xmm1.                   

Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2                            | Operand 3      | Operand 4
| A    | ModRM:reg (r,w)| BaseReg (R): VSIB:base, VectorReg(R):| VEX.vvvv (r, w)| NA       
|      |                | VSIB:index                           |                |          

Description:
The instruction conditionally loads up to 4 or 8 single-precision floating-point
values from memory addresses specified by the memory operand (the second operand)
and using dword indices. The memory operand uses the VSIB form of the SIB byte
to specify a general purpose register operand as the common base, a vector register
for an array of indices relative to the base and a constant scale factor. The
mask operand (the third operand) specifies the conditional load operation from
each memory address and the corresponding update of each data element of the
destination operand (the first operand). Conditionality is specified by the
most significant bit of each data element of the mask register. If an element's
mask bit is not set, the corresponding element of the destination register is
left unchanged. The width of data element in the destination register and mask
register are identical. The entire mask register will be set to zero by this
instruction unless the instruction causes an exception. Using qword indices,
the instruction conditionally loads up to 2 or 4 single-precision floating-point
values from the VSIB addressing memory operand, and updates the lower half of
the destination register. The upper 128 or 256 bits of the destination register
are zero'ed with qword indices. This instruction can be suspended by an exception
if at least one element is already gathered (i.e., if the exception

| is triggered by an element other than            | When this happens, the destination If 
| the rightmost one with its mask bit              | any traps or interrupts are pending   
| set). register and the mask operand              | from already gathIt may do this to one
| are partially updated; those elements            | or both                               
| that have been gathered are placed into          |                                       
| the destination register and have their          |                                       
| mask bits set to zero. ered elements,            |                                       
| they will be delivered in lieu of the            |                                       
| exception; in this case, EFLAG.RF is             |                                       
| set to one so an instruction breakpoint          |                                       
| is not re-triggered when the instruction         |                                       
| is continued. If the data size and index         |                                       
| size are different, part of the destination      |                                       
| register and part of the mask register           |                                       
| do not correspond to any elements being          |                                       
| gathered. of those registers even if             |                                       
| the instruction triggers an exception,           |                                       
| and even if the instruction triggers             |                                       
| the exception before gathering any elements.     |                                       
| VEX.128 version: For dword indices,              | For                                   
| the instruction will gather four single-precision|                                       
| floating-point values.                           |                                       
qword indices, the instruction will gather two values and zeroes the upper 64
bits of the destination.

| VEX.256 version: For dword indices,               | For If any pair of the index, mask,        
| the instruction will gather eight single-precision| or destination registers are the same,     
| floating-point values. qword indices,             | this instruction results a UD fault.       
| the instruction will gather four values           |                                            
| and zeroes the upper 128 bits of the              |                                            
| destination. Note that: •                         |                                            
| •64 memory-ordering model. •                      | Memory ordering with other instructions    
|                                                   | follows the IntelThat is, if a fault       
|                                                   | is triggered by an element and delivered,  
|                                                   | all                                        
| elements closer to the LSB of the destination     | Individual elements closer If a given      
| will be completed (and non-faulting).             | element triggers multiple faults, they     
| to the MSB may or may not be completed.           | are delivered in the Elements may be       
| conventional order. •                             | gathered in any order, but faults must     
|                                                   | be delivered in a right-to-left order;     
|                                                   | thus, elements to                          
| the left of a faulting one may be gathered        | A given implementation of this This        
| before the fault is delivered. instruction        | instruction does not perform AC checks,    
| is repeatable - given the same input              | and so will never deliver an AC fault.     
| values and architectural state, the               |                                            
| same set of elements to the left of               |                                            
| the faulting one will be gathered. •              |                                            
| •                                                 | This instruction will cause a #UD if       
|                                                   | the address size attribute is 16-bit.      
| •                                                 | This instruction will cause a #UD if       
|                                                   | the memory operand is encoded without      
|                                                   | the SIB byte.                              
| •is implementation specific, and some             | This instruction should not be used        
| implementations may use loads larger              | to access memory mapped I/O as the ordering
| than the data element size or load elements       | of the individual loads it does The        
| an indeterminate number of times. •               | scaled index may require more bits to      
|                                                   | represent than the address bits used       
|                                                   | by the processor (e.g., in 32-             
| bit mode, if the scale is greater than            | In this case, the most significant bits    
| one). bits are ignored.                           | beyond the number of address               
Operation:

DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;
VGATHERDPS (VEX.128 version)
FOR j<- 0 to 3
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 3
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VGATHERQPS (VEX.128 version)
FOR j<- 0 to 3
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 1
  k <- j * 64;
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
MASK[127:64] <- 0;
DEST[VLMAX-1:64] <- 0;
(non-masked elements of the mask register have the content of respective element
VGATHERDPS (VEX.256 version)
FOR j<- 0 to 7
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 7
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element
VGATHERQPS (VEX.256 version)
FOR j<- 0 to 7
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  k <- j * 64;
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element

Intel C/C++ Compiler Intrinsic Equivalent:
| VGATHERDPS:        | __m128 _mm_i32gather_ps (float const    
|                    | * base, __m128i index, const int scale);
| VGATHERDPS:        | __m128 _mm_mask_i32gather_ps (__m128    
|                    | src, float const * base, __m128i index, 
|                    | __m128 mask, const int scale);          
| VGATHERDPS:        | __m256 _mm256_i32gather_ps (float const 
|                    | * base, __m256i index, const int scale);
| VGATHERDPS: scale);| __m256 _mm256_mask_i32gather_ps (__m256 
|                    | src, float const * base, __m256i index, 
|                    | __m256 mask, const int                  
| VGATHERQPS:        | __m128 _mm_i64gather_ps (float const    
|                    | * base, __m128i index, const int scale);
| VGATHERQPS:        | __m128 _mm_mask_i64gather_ps (__m128    
|                    | src, float const * base, __m128i index, 
|                    | __m128 mask, const int scale);          
| VGATHERQPS:        | __m128 _mm256_i64gather_ps (float const 
|                    | * base, __m256i index, const int scale);
| VGATHERQPS: scale);| __m128 _mm256_mask_i64gather_ps (__m128 
|                    | src, float const * base, __m256i index, 
|                    | __m128 mask, const int                  

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 12


platform: x86
mnem: VPGATHERDD
description:
VPGATHERDD/VPGATHERQD  -  Gather Packed Dword Values Using Signed Dword/Qword Indices:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                
| VEX.DDS.128.66.0F38.W0 90 /r VPGATHERDD| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x,    
| xmm1, vm32x, xmm2                      |      |                |                   | gather dword values from memory conditioned
|                                        |      |                |                   | on mask specified by xmm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into xmm1.    
| VEX.DDS.128.66.0F38.W0 91 /r VPGATHERQD| RMV  | V/V            | AVX2              | Using qword indices specified in vm64x,    
| xmm1, vm64x, xmm2                      |      |                |                   | gather dword values from memory conditioned
|                                        |      |                |                   | on mask specified by xmm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into xmm1.    
| VEX.DDS.256.66.0F38.W0 90 /r VPGATHERDD| RMV  | V/V            | AVX2              | Using dword indices specified in vm32y,    
| ymm1, vm32y, ymm2                      |      |                |                   | gather dword from memory conditioned       
|                                        |      |                |                   | on mask specified by ymm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into ymm1.    
| VEX.DDS.256.66.0F38.W0 91 /r VPGATHERQD| RMV  | V/V            | AVX2              | Using qword indices specified in vm64y,    
| xmm1, vm64y, xmm2                      |      |                |                   | gather dword values from memory conditioned
|                                        |      |                |                   | on mask specified by xmm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into xmm1.    

Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2                            | Operand 3      | Operand 4
| RMV  | ModRM:reg (r,w)| BaseReg (R): VSIB:base, VectorReg(R):| VEX.vvvv (r, w)| NA       
|      |                | VSIB:index                           |                |          

Description:
The instruction conditionally loads up to 4 or 8 dword values from memory addresses
specified by the memory operand (the second operand) and using dword indices.
The memory operand uses the VSIB form of the SIB byte to specify a general purpose
register operand as the common base, a vector register for an array of indices
relative to the base and a constant scale factor. The mask operand (the third
operand) specifies the conditional load operation from each memory address and
the corresponding update of each data element of the destination operand (the
first operand). Conditionality is specified by the most significant bit of each
data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width
of data element in the destination register and mask register are identical.
The entire mask register will be set to zero by this instruction unless the
instruction causes an exception. Using qword indices, the instruction conditionally
loads up to 2 or 4 dword values from the VSIB addressing memory operand, and
updates the lower half of the destination register. The upper 128 or 256 bits
of the destination register are zero'ed with qword indices. This instruction
can be suspended by an exception if at least one element is already gathered
(i.e., if the exception

| is triggered by an element other than       | When this happens, the destination If 
| the rightmost one with its mask bit         | any traps or interrupts are pending   
| set). register and the mask operand         | from already gathIt may do this to one
| are partially updated; those elements       | or both                               
| that have been gathered are placed into     |                                       
| the destination register and have their     |                                       
| mask bits set to zero. ered elements,       |                                       
| they will be delivered in lieu of the       |                                       
| exception; in this case, EFLAG.RF is        |                                       
| set to one so an instruction breakpoint     |                                       
| is not re-triggered when the instruction    |                                       
| is continued. If the data size and index    |                                       
| size are different, part of the destination |                                       
| register and part of the mask register      |                                       
| do not correspond to any elements being     |                                       
| gathered. of those registers even if        |                                       
| the instruction triggers an exception,      |                                       
| and even if the instruction triggers        |                                       
| the exception before gathering any elements.|                                       
| VEX.128 version: For dword indices,         | For qword indices, the instruc-       
| the instruction will gather four dword      |                                       
| values. tion will gather two values         |                                       
| and zeroes the upper 64 bits of the         |                                       
| destination.                                |                                       
| VEX.256 version: For dword indices,         | For qword indices, the instruc-       
| the instruction will gather eight dword     |                                       
| values.                                     |                                       
tion will gather four values and zeroes the upper 128 bits of the destination.
Note that:

 - If any pair of the index, mask, or destination registers are the same, this
instruction results a UD fault.
 - The values may be read from memory in any order. Memory ordering with other
instructions follows the Intel64 memory-ordering model.
 - Faults are delivered in a right-to-left manner. That is, if a fault is triggered
by an element and delivered, all elements closer to the LSB of the destination
will be completed (and non-faulting). Individual elements closer to the MSB
may or may not be completed. If a given element triggers multiple faults, they
are delivered in the conventional order.
 - Elements may be gathered in any order, but faults must be delivered in a right-to-left
order; thus, elements to the left of a faulting one may be gathered before the
fault is delivered. A given implementation of this instruction is repeatable
- given the same input values and architectural state, the same set of elements
to the left of the faulting one will be gathered.
 - This instruction does not perform AC checks, and so will never deliver an AC
fault.
 - This instruction will cause a #UD if the address size attribute is 16-bit.
 - This instruction will cause a #UD if the memory operand is encoded without the
SIB byte.
 - This instruction should not be used to access memory mapped I/O as the ordering
of the individual loads it does is implementation specific, and some implementations
may use loads larger than the data element size or load elements an indeterminate
number of times.
 - The scaled index may require more bits to represent than the address bits used
by the processor (e.g., in 32bit mode, if the scale is greater than one). In
this case, the most significant bits beyond the number of address bits are ignored.

Operation:

DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;
VPGATHERDD (VEX.128 version)
FOR j<- 0 to 3
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 3
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[i+31:i])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VPGATHERQD (VEX.128 version)
FOR j<- 0 to 3
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
MASK[VLMAX-1:128] <- 0;
FOR j<- 0 to 1
  k <- j * 64;
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
MASK[127:64] <- 0;
DEST[VLMAX-1:64] <- 0;
(non-masked elements of the mask register have the content of respective element
VPGATHERDD (VEX.256 version)
FOR j<- 0 to 7
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 7
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+31:i])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element
VPGATHERQD (VEX.256 version)
FOR j<- 0 to 7
  i <- j * 32;
  IF MASK[31+i] THEN
     MASK[i +31:i] <- 0xFFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +31:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  k <- j * 64;
  i <- j * 32;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+63:k])*SCALE + DISP;
  IF MASK[31+i] THEN
     DEST[i +31:i] <- FETCH_32BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +31:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element

Intel C/C++ Compiler Intrinsic Equivalent:
VPGATHERDD: __m128i _mm_i32gather_epi32 (int const * base, __m128i index, const
int scale);

VPGATHERDD: __m128i _mm_mask_i32gather_epi32 (__m128i src, int const * base,
__m128i index, __m128i mask, const int scale);

VPGATHERDD: __m256i _mm256_i32gather_epi32 ( int const * base, __m256i index,
const int scale);

VPGATHERDD: __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const * base,
__m256i index, __m256i mask, const int scale);

VPGATHERQD: __m128i _mm_i64gather_epi32 (int const * base, __m128i index, const
int scale);

VPGATHERQD: __m128i _mm_mask_i64gather_epi32 (__m128i src, int const * base,
__m128i index, __m128i mask, const int scale);

VPGATHERQD: __m128i _mm256_i64gather_epi32 (int const * base, __m256i index,
const int scale);

VPGATHERQD: __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const * base,
__m256i index, __m128i mask, const int scale);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 12


platform: x86
mnem: VPGATHERDQ
description:
VPGATHERDQ/VPGATHERQQ  -  Gather Packed Qword Values Using Signed Dword/Qword Indices:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                
| VEX.DDS.128.66.0F38.W1 90 /r VPGATHERDQ| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x,    
| xmm1, vm32x, xmm2                      |      |                |                   | gather qword values from memory conditioned
|                                        |      |                |                   | on mask specified by xmm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into xmm1.    
| VEX.DDS.128.66.0F38.W1 91 /r VPGATHERQQ| RMV  | V/V            | AVX2              | Using qword indices specified in vm64x,    
| xmm1, vm64x, xmm2                      |      |                |                   | gather qword values from memory conditioned
|                                        |      |                |                   | on mask specified by xmm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into xmm1.    
| VEX.DDS.256.66.0F38.W1 90 /r VPGATHERDQ| RMV  | V/V            | AVX2              | Using dword indices specified in vm32x,    
| ymm1, vm32x, ymm2                      |      |                |                   | gather qword values from memory conditioned
|                                        |      |                |                   | on mask specified by ymm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into ymm1.    
| VEX.DDS.256.66.0F38.W1 91 /r VPGATHERQQ| RMV  | V/V            | AVX2              | Using qword indices specified in vm64y,    
| ymm1, vm64y, ymm2                      |      |                |                   | gather qword values from memory conditioned
|                                        |      |                |                   | on mask specified by ymm2. Conditionally   
|                                        |      |                |                   | gathered elements are merged into ymm1.    

Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2                            | Operand 3      | Operand 4
| A    | ModRM:reg (r,w)| BaseReg (R): VSIB:base, VectorReg(R):| VEX.vvvv (r, w)| NA       
|      |                | VSIB:index                           |                |          

Description:
The instruction conditionally loads up to 2 or 4 qword values from memory addresses
specified by the memory operand (the second operand) and using qword indices.
The memory operand uses the VSIB form of the SIB byte to specify a general purpose
register operand as the common base, a vector register for an array of indices
relative to the base and a constant scale factor. The mask operand (the third
operand) specifies the conditional load operation from each memory address and
the corresponding update of each data element of the destination operand (the
first operand). Conditionality is specified by the most significant bit of each
data element of the mask register. If an element's mask bit is not set, the
corresponding element of the destination register is left unchanged. The width
of data element in the destination register and mask register are identical.
The entire mask register will be set to zero by this instruction unless the
instruction causes an exception. Using dword indices in the lower half of the
mask register, the instruction conditionally loads up to 2 or 4 qword values
from the VSIB addressing memory operand, and updates the destination register.
This instruction can be suspended by an exception if at least one element is
already gathered (i.e., if the exception

| is triggered by an element other than       | When this happens, the destination If 
| the rightmost one with its mask bit         | any traps or interrupts are pending   
| set). register and the mask operand         | from already gathIt may do this to one
| are partially updated; those elements       | or both                               
| that have been gathered are placed into     |                                       
| the destination register and have their     |                                       
| mask bits set to zero. ered elements,       |                                       
| they will be delivered in lieu of the       |                                       
| exception; in this case, EFLAG.RF is        |                                       
| set to one so an instruction breakpoint     |                                       
| is not re-triggered when the instruction    |                                       
| is continued. If the data size and index    |                                       
| size are different, part of the destination |                                       
| register and part of the mask register      |                                       
| do not correspond to any elements being     |                                       
| gathered. of those registers even if        |                                       
| the instruction triggers an exception,      |                                       
| and even if the instruction triggers        |                                       
| the exception before gathering any elements.|                                       
| VEX.128 version: The instruction will       | For dword indices, only the lower two 
| gather two qword values. vector index       | indices in the                        
| register are used.                          |                                       
| VEX.256 version: The instruction will       | For dword indices, only the lower four
| gather four qword values.                   | indices in                            
the vector index register are used. Note that:

 - If any pair of the index, mask, or destination registers are the same, this
instruction results a UD fault.
 - The values may be read from memory in any order. Memory ordering with other
instructions follows the Intel64 memory-ordering model.
 - Faults are delivered in a right-to-left manner. That is, if a fault is triggered
by an element and delivered, all elements closer to the LSB of the destination
will be completed (and non-faulting). Individual elements closer to the MSB
may or may not be completed. If a given element triggers multiple faults, they
are delivered in the conventional order.
 - Elements may be gathered in any order, but faults must be delivered in a right-to-left
order; thus, elements to the left of a faulting one may be gathered before the
fault is delivered. A given implementation of this instruction is repeatable
- given the same input values and architectural state, the same set of elements
to the left of the faulting one will be gathered.
 - This instruction does not perform AC checks, and so will never deliver an AC
fault.
 - This instruction will cause a #UD if the address size attribute is 16-bit.
 - This instruction will cause a #UD if the memory operand is encoded without the
SIB byte.
 - This instruction should not be used to access memory mapped I/O as the ordering
of the individual loads it does is implementation specific, and some implementations
may use loads larger than the data element size or load elements an indeterminate
number of times.
 - The scaled index may require more bits to represent than the address bits used
by the processor (e.g., in 32bit mode, if the scale is greater than one). In
this case, the most significant bits beyond the number of address bits are ignored.

Operation:

DEST <- SRC1;
BASE_ADDR: base register encoded in VSIB addressing;
VINDEX: the vector index register encoded by VSIB addressing;
SCALE: scale factor encoded by SIB:[7:6];
DISP: optional 1, 4 byte displacement;
MASK <- SRC3;
VPGATHERDQ (VEX.128 version)
FOR j<- 0 to 1
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 1
  k <- j * 32;
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX[k+31:k])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VPGATHERQQ (VEX.128 version)
FOR j<- 0 to 1
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 1
  i <-j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63:i] <- 0;
ENDFOR
MASK[VLMAX-1:128] <- 0;
DEST[VLMAX-1:128] <- 0;
(non-masked elements of the mask register have the content of respective element
VPGATHERQQ (VEX.256 version)
FOR j<- 0 to 3
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[i+63:i])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element
VPGATHERDQ (VEX.256 version)
FOR j<- 0 to 3
  i <- j * 64;
  IF MASK[63+i] THEN
     MASK[i +63:i] <- 0xFFFFFFFF_FFFFFFFF; // extend from most significant bit
  ELSE
     MASK[i +63:i] <- 0;
  FI;
ENDFOR
FOR j<- 0 to 3
  k <- j * 32;
  i <- j * 64;
  DATA_ADDR <- BASE_ADDR + (SignExtend(VINDEX1[k+31:k])*SCALE + DISP;
  IF MASK[63+i] THEN
     DEST[i +63:i] <- FETCH_64BITS(DATA_ADDR); // a fault exits the instruction
  FI;
  MASK[i +63:i] <- 0;
ENDFOR
(non-masked elements of the mask register have the content of respective element

Intel C/C++ Compiler Intrinsic Equivalent:
VPGATHERDQ: __m128i _mm_i32gather_epi64 (int64 const * base, __m128i index,
const int scale);

VPGATHERDQ: __m128i _mm_mask_i32gather_epi64 (__m128i src, int64 const * base,
__m128i index, __m128i mask, const int scale);

VPGATHERDQ: __m256i _mm256_i32gather_epi64 ( int64 const * base, __m128i index,
const int scale);

VPGATHERDQ: __m256i _mm256_mask_i32gather_epi64 (__m256i src, int64 const *
base, __m128i index, __m256i mask, const int scale);

VPGATHERQQ: __m128i _mm_i64gather_epi64 (int64 const * base, __m128i index,
const int scale);

VPGATHERQQ: __m128i _mm_mask_i64gather_epi64 (__m128i src, int64 const * base,
__m128i index, __m128i mask, const int scale);

VPGATHERQQ: __m256i _mm256_i64gather_epi64 (int64 const * base, __m256i index,
const int scale);

VPGATHERQQ: __m256i _mm256_mask_i64gather_epi64 (__m256i src, int64 const *
base, __m256i index, __m256i mask, const int scale);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 12


platform: x86
mnem: VINSERTF128
description:
VINSERTF128  -  Insert Packed Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                              
| VEX.NDS.256.66.0F3A.W0 18 /r ib VINSERTF128| RVM  | V/V           | AVX               | Insert a single precision floating-point 
| ymm1, ymm2, xmm3/m128, imm8                |      |               |                   | value selected by imm8 from xmm3/m128    
|                                            |      |               |                   | into ymm2 at the specified destination   
|                                            |      |               |                   | element specified by imm8 and zero out   
|                                            |      |               |                   | destination elements in ymm1 as indicated
|                                            |      |               |                   | in imm8.                                 

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2   | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs an insertion of 128-bits of packed floating-point values from the second
source operand (third operand) into an the destination operand (first operand)
at an 128-bit offset from imm8[0]. The remaining portions of the destination
are written by the corresponding fields of the first source operand (second
operand). The second source operand can be either an XMM register or a 128-bit
memory location. The high 7 bits of the immediate are ignored.

Operation:

TEMP[255:0] <- SRC1[255:0]
CASE (imm8[0]) OF
  0: TEMP[127:0] <- SRC2[127:0]
  1: TEMP[255:128] <- SRC2[127:0]
ESAC
DEST <-TEMP

Intel C/C++ Compiler Intrinsic Equivalent:
| INSERTF128:| __m256 _mm256_insertf128_ps (__m256     
|            | a, __m128 b, int offset);               
| INSERTF128:| __m256d _mm256_insertf128_pd (__m256d   
|            | a, __m128d b, int offset);              
| INSERTF128:| __m256i _mm256_insertf128_si256 (__m256i
|            | a, __m128i b, int offset);              

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: VINSERTI128
description:
VINSERTI128  -  Insert Packed Integer Values:
| Opcode/Instruction                         | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                           
| VEX.NDS.256.66.0F3A.W0 38 /r ib VINSERTI128| RVMI | V/V            | AVX2              | Insert 128-bits of integer data from  
| ymm1, ymm2, xmm3/m128, imm8                |      |                |                   | xmm3/mem and the remaining values from
|                                            |      |                |                   | ymm2 into ymm1.                       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVMI | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| Imm8     

Description:
Performs an insertion of 128-bits of packed integer data from the second source
operand (third operand) into an the destination operand (first operand) at a
128-bit offset from imm8[0]. The remaining portions of the destination are written
by the corresponding fields of the first source operand (second operand). The
second source operand can be either an XMM register or a 128-bit memory location.
The high 7 bits of the immediate are ignored. VEX.L must be 1; an attempt to
execute this instruction with VEX.L=0 will cause #UD.

Operation:

VINSERTI128
TEMP[255:0] <- SRC1[255:0]
CASE (imm8[0]) OF
  0: TEMP[127:0] <-SRC2[127:0]
  1: TEMP[255:128] <- SRC2[127:0]
ESAC
DEST <-TEMP

Intel C/C++ Compiler Intrinsic Equivalent:
VINSERTI128: __m256i _mm256_inserti128_si256 (__m256i a, __m128i b, int offset);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.L = 0, If VEX.W = 1.


platform: x86
mnem: VMASKMOV
description:
VMASKMOV - Conditional SIMD Packed Loads and Stores:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| VEX.NDS.128.66.0F38.W0 2C /r VMASKMOVPS| RVM  | V/V           | AVX               | Conditionally load packed single-precision 
| xmm1, xmm2, m128                       |      |               |                   | values from m128 using mask in xmm2        
|                                        |      |               |                   | and store in xmm1.                         
| VEX.NDS.256.66.0F38.W0 2C /r VMASKMOVPS| RVM  | V/V           | AVX               | Conditionally load packed single-precision 
| ymm1, ymm2, m256                       |      |               |                   | values from m256 using mask in ymm2        
|                                        |      |               |                   | and store in ymm1.                         
| VEX.NDS.128.66.0F38.W0 2D /r VMASKMOVPD| RVM  | V/V           | AVX               | Conditionally load packed double-precision 
| xmm1, xmm2, m128                       |      |               |                   | values from m128 using mask in xmm2        
|                                        |      |               |                   | and store in xmm1.                         
| VEX.NDS.256.66.0F38.W0 2D /r VMASKMOVPD| RVM  | V/V           | AVX               | Conditionally load packed double-precision 
| ymm1, ymm2, m256                       |      |               |                   | values from m256 using mask in ymm2        
|                                        |      |               |                   | and store in ymm1.                         
| VEX.NDS.128.66.0F38.W0 2E /r VMASKMOVPS| MVR  | V/V           | AVX               | Conditionally store packed single-precision
| m128, xmm1, xmm2                       |      |               |                   | values from xmm2 using mask in xmm1.       
| VEX.NDS.256.66.0F38.W0 2E /r VMASKMOVPS| MVR  | V/V           | AVX               | Conditionally store packed single-precision
| m256, ymm1, ymm2                       |      |               |                   | values from ymm2 using mask in ymm1.       
| VEX.NDS.128.66.0F38.W0 2F /r VMASKMOVPD| MVR  | V/V           | AVX               | Conditionally store packed double-precision
| m128, xmm1, xmm2                       |      |               |                   | values from xmm2 using mask in xmm1.       
| VEX.NDS.256.66.0F38.W0 2F /r VMASKMOVPD| MVR  | V/V           | AVX               | Conditionally store packed double-precision
| m256, ymm1, ymm2                       |      |               |                   | values from ymm2 using mask in ymm1.       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2   | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       
| MVR  | ModRM:r/m (w)| VEX.vvvv (r)| ModRM:reg (r)| NA       

Description:
Conditionally moves packed data elements from the second source operand into
the corresponding data element of the destination operand, depending on the
mask bits associated with each data element. The mask bits are specified in
the first source operand. The mask bit for each data element is the most significant
bit of that element in the first source operand. If a mask is 1, the corresponding
data element is copied from the second source operand to the destination operand.
If the mask is 0, the corresponding data element is set to zero in the load
form of these instructions, and unmodified in the store form. The second source
operand is a memory address for the load form of these instruction. The destination
operand is a memory address for the store form of these instructions. The other
operands are both XMM registers (for VEX.128 version) or YMM registers (for
VEX.256 version). Faults occur only due to mask-bit required memory accesses
that caused the faults. Faults will not occur due to referencing any memory
location if the corresponding mask bit for that memory location is 0. For example,
no faults will be detected if the mask bits are all zero. Unlike previous MASKMOV
instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions. Instruction behavior on alignment check reporting with mask
bits of less than all 1s are the same as with mask bits of all 1s. VMASKMOV
should not be used to access memory mapped I/O and un-cached memory as the access
and the ordering of the individual loads or stores it does is implementation
specific.

In cases where mask bits indicate data should not be loaded or stored paging
A and D bits will be set in an implementation dependent way. However, A and
D bits are always set for pages where data is actually loaded/stored. Note:
for load forms, the first source (the mask) is encoded in VEX.vvvv; the second
source is encoded in rm_field, and the destination register is encoded in reg_field.
Note: for store forms, the first source (the mask) is encoded in VEX.vvvv; the
second source register is encoded in reg_field, and the destination memory location
is encoded in rm_field.

Operation:

VMASKMOVPS -128-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] <- 0
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VMASKMOVPD - 128-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] <- 0
VMASKMOVPD - 256-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VMASKMOVPS - 128-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
VMASKMOVPS - 256-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
IF (SRC1[159]) DEST[159:128] <-SRC2[159:128]
IF (SRC1[191]) DEST[191:160] <- SRC2[191:160]
IF (SRC1[223]) DEST[223:192] <- SRC2[223:192]
IF (SRC1[255]) DEST[255:224] <- SRC2[255:224]
VMASKMOVPD - 128-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]
VMASKMOVPD - 256-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]
VMASKMOVPS - 256-bit load
IF (SRC1[191]) DEST[191:128] <- SRC2[191:128]
IF (SRC1[255]) DEST[255:192] <- SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| __m256                                | _mm256_maskload_ps(float const *a, __m256i
|                                       | mask)                                     
| void __m256d _mm256_maskload_pd(double| _mm256_maskstore_ps(float *a, __m256i     
| *a, __m256i mask);                    | mask, __m256 b)                           
| void __m128 _mm128_maskload_ps(float  | _mm256_maskstore_pd(double *a, __m256i    
| const *a, __m128i mask)               | mask, __m256d b);                         
| void __m128d _mm128_maskload_pd(double| _mm128_maskstore_ps(float *a, __m128i     
| *a, __m128i mask);                    | mask, __m128 b)                           
| void                                  | _mm128_maskstore_pd(double *a, __m128i    
|                                       | mask, __m128d b);                         

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6 (No AC# reported for any mask bit combinations); additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: VPBLENDD
description:
VPBLENDD  -  Blend Packed Dwords:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                          
| VEX.NDS.128.66.0F3A.W0 02 /r ib VPBLENDD| RVMI | V/V            | AVX2              | Select dwords from xmm2 and xmm3/m128
| xmm1, xmm2, xmm3/m128, imm8             |      |                |                   | from mask specified in imm8 and store
|                                         |      |                |                   | the values into xmm1.                
| VEX.NDS.256.66.0F3A.W0 02 /r ib VPBLENDD| RVMI | V/V            | AVX2              | Select dwords from ymm2 and ymm3/m256
| ymm1, ymm2, ymm3/m256, imm8             |      |                |                   | from mask specified in imm8 and store
|                                         |      |                |                   | the values into ymm1.                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVMI | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| Imm8     

Description:
Dword elements from the source operand (second operand) are conditionally written
to the destination operand (first operand) depending on bits in the immediate
operand (third operand). The immediate bits (bits 7:0) form a mask that determines
whether the corresponding word in the destination is copied from the source.
If a bit in the mask, corresponding to a word, is “1", then the word is copied,
else the word is unchanged. VEX.128 encoded version: The second source operand
can be an XMM register or a 128-bit memory location. The first source and destination
operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand is a YMM register or a 256-bit memory location. The
destination operand is a YMM register.

Operation:

VPBLENDD (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]
ELSE DEST[31:0] <- SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]
ELSE DEST[63:32] <- SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]
ELSE DEST[95:64] <- SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]
ELSE DEST[127:96] <- SRC1[127:96]
IF (imm8[4] == 1) THEN DEST[159:128] <- SRC2[159:128]
ELSE DEST[159:128] <- SRC1[159:128]
IF (imm8[5] == 1) THEN DEST[191:160] <- SRC2[191:160]
ELSE DEST[191:160] <- SRC1[191:160]
IF (imm8[6] == 1) THEN DEST[223:192] <- SRC2[223:192]
ELSE DEST[223:192] <- SRC1[223:192]
IF (imm8[7] == 1) THEN DEST[255:224] <- SRC2[255:224]
ELSE DEST[255:224] <- SRC1[255:224]
VPBLENDD (VEX.128 encoded version)
IF (imm8[0] == 1) THEN DEST[31:0] <- SRC2[31:0]
ELSE DEST[31:0] <- SRC1[31:0]
IF (imm8[1] == 1) THEN DEST[63:32] <- SRC2[63:32]
ELSE DEST[63:32] <- SRC1[63:32]
IF (imm8[2] == 1) THEN DEST[95:64] <- SRC2[95:64]
ELSE DEST[95:64] <- SRC1[95:64]
IF (imm8[3] == 1) THEN DEST[127:96] <- SRC2[127:96]
ELSE DEST[127:96] <- SRC1[127:96]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| VPBLENDD:| __m128i _mm_blend_epi32 (__m128i v1,
|          | __m128i v2, const int mask)         
| VPBLENDD:| __m256i _mm256_blend_epi32 (__m256i 
|          | v1, __m256i v2, const int mask)     

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: VPBROADCAST
description:
VPBROADCAST - Broadcast Integer Data:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                            
| VEX.128.66.0F38.W0 78 /r VPBROADCASTB  | RM   | V/V            | AVX2              | Broadcast a byte integer in the source 
| xmm1, xmm2/m8                          |      |                |                   | operand to sixteen locations in xmm1.  
| VEX.256.66.0F38.W0 78 /r VPBROADCASTB  | RM   | V/V            | AVX2              | Broadcast a byte integer in the source 
| ymm1, xmm2/m8                          |      |                |                   | operand to thirtytwo locations in ymm1.
| VEX.128.66.0F38.W0 79 /r VPBROADCASTW  | RM   | V/V            | AVX2              | Broadcast a word integer in the source 
| xmm1, xmm2/m16                         |      |                |                   | operand to eight locations in xmm1.    
| VEX.256.66.0F38.W0 79 /r VPBROADCASTW  | RM   | V/V            | AVX2              | Broadcast a word integer in the source 
| ymm1, xmm2/m16                         |      |                |                   | operand to sixteen locations in ymm1.  
| VEX.128.66.0F38.W0 58 /r VPBROADCASTD  | RM   | V/V            | AVX2              | Broadcast a dword integer in the source
| xmm1, xmm2/m32                         |      |                |                   | operand to four locations in xmm1.     
| VEX.256.66.0F38.W0 58 /r VPBROADCASTD  | RM   | V/V            | AVX2              | Broadcast a dword integer in the source
| ymm1, xmm2/m32                         |      |                |                   | operand to eight locations in ymm1.    
| VEX.128.66.0F38.W0 59 /r VPBROADCASTQ  | RM   | V/V            | AVX2              | Broadcast a qword element in mem to    
| xmm1, xmm2/m64                         |      |                |                   | two locations in xmm1.                 
| VEX.256.66.0F38.W0 59 /r VPBROADCASTQ  | RM   | V/V            | AVX2              | Broadcast a qword element in mem to    
| ymm1, xmm2/m64                         |      |                |                   | four locations in ymm1.                
| VEX.256.66.0F38.W0 5A /r VBROADCASTI128| RM   | V/V            | AVX2              | Broadcast 128 bits of integer data in  
| ymm1, m128                             |      |                |                   | mem to low and high 128-bits in ymm1.  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Load integer data from the source operand (second operand) and broadcast to
all elements of the destination operand (first operand). The destination operand
is a YMM register. The source operand is 8-bit, 16-bit 32-bit, 64-bit memory
location or the low 8-bit, 16-bit 32-bit, 64-bit data in an XMM register. VPBROADCASTB/D/W/Q
also support XMM register as the source operand. VBROADCASTI128: The destination
operand is a YMM register. The source operand is 128-bit memory location. Register
source encodings for VBROADCASTI128 are reserved and will #UD. VPBROADCASTB/W/D/Q
is supported in both 128-bit and 256-bit wide versions.

VBROADCASTI128 is only supported as a 256-bit wide version. Note: In VEX-encoded
versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD. Attempts to execute any VPBROADCAST* instruction with VEX.W = 1 will cause
#UD. If VBROADCASTI128 is encoded with VEX.L= 0, an attempt to execute the instruction
encoded with VEX.L= 0 will cause an #UD exception.

| m32                                     | X0                
| X0                                      | X0                
| VPBROADCASTD Operation (VEX.256 encoded | Figure 4-33.      
| version)                                |                   
| m32                                     | X0                
| X0                                      | X0                
| VPBROADCASTD Operation (128-bit version)| Figure 4-34. X0 X0
| VPBROADCASTQ Operation                  | Figure 4-35. X0 X0
| VBROADCASTI128 Operation                | Figure 4-36.      
Operation:

VPBROADCASTB (VEX.128 encoded version)
temp <- SRC[7:0]
FOR j <- 0 TO 15
DEST[7+j*8: j*8] <- temp
ENDFOR
DEST[VLMAX-1:128] <- 0
VPBROADCASTB (VEX.256 encoded version)
temp <- SRC[7:0]
FOR j <- 0 TO 31
DEST[7+j*8: j*8] <- temp
ENDFOR
VPBROADCASTW (VEX.128 encoded version)
temp <- SRC[15:0]
FOR j <- 0 TO 7
DEST[15+j*16: j*16] <- temp
ENDFOR
DEST[VLMAX-1:128] <- 0
VPBROADCASTW (VEX.256 encoded version)
temp <- SRC[15:0]
FOR j <- 0 TO 15
DEST[15+j*16: j*16] <- temp
ENDFOR
VPBROADCASTD (128 bit version)
temp <- SRC[31:0]
FOR j <- 0 TO 3
DEST[31+j*32: j*32] <- temp
ENDFOR
DEST[VLMAX-1:128] <- 0
VPBROADCASTD (VEX.256 encoded version)
temp <- SRC[31:0]
FOR j <- 0 TO 7
DEST[31+j*32: j*32] <- temp
ENDFOR
VPBROADCASTQ (VEX.128 encoded version)
temp <- SRC[63:0]
DEST[63:0] <- temp
DEST[127:64] <- temp
DEST[VLMAX-1:128] <- 0
VPBROADCASTQ (VEX.256 encoded version)
temp <- SRC[63:0]
DEST[63:0] <- temp
DEST[127:64] <- temp
DEST[191:128] <- temp
DEST[255:192] <- temp
VBROADCASTI128
temp <- SRC[127:0]
DEST[127:0] <- temp
DEST[VLMAX-1:128] <- temp

Intel C/C++ Compiler Intrinsic Equivalent:
| VPBROADCASTB:  | __m256i _mm256_broadcastb_epi8(__m128i     
|                | );                                         
| VPBROADCASTW:  | __m256i _mm256_broadcastw_epi16(__m128i    
|                | );                                         
| VPBROADCASTD:  | __m256i _mm256_broadcastd_epi32(__m128i    
|                | );                                         
| VPBROADCASTQ:  | __m256i _mm256_broadcastq_epi64(__m128i    
|                | );                                         
| VPBROADCASTB:  | __m128i _mm_broadcastb_epi8(__m128i        
|                | );                                         
| VPBROADCASTW:  | __m128i _mm_broadcastw_epi16(__m128i       
|                | );                                         
| VPBROADCASTD:  | __m128i _mm_broadcastd_epi32(__m128i       
|                | );                                         
| VPBROADCASTQ:  | __m128i _mm_broadcastq_epi64(__m128i       
|                | );                                         
| VBROADCASTI128:| __m256i _mm256_broadcastsi128_si256(__m128i
|                | );                                         

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.W = 1, If VEX.L = 0 for VBROADCASTI128.


platform: x86
mnem: VPERMD
description:
VPERMD  -  Full Doublewords Element Permutation:
| Opcode/Instruction                 | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                           
| VEX.NDS.256.66.0F38.W0 36 /r VPERMD| RVM  | V/V            | AVX2              | Permute doublewords in ymm3/m256 using
| ymm1, ymm2, ymm3/m256              |      |                |                   | indexes in ymm2 and store the result  
|                                    |      |                |                   | in ymm1.                              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       

Description:
Use the index values in each dword element of the first source operand (the
second operand) to select a dword element in the second source operand (the
third operand), the resultant dword value from the second source operand is
copied to the destination operand (the first operand) in the corresponding position
of the index element. Note that this instruction permits a doubleword in the
source operand to be copied to more than one doubleword location in the destination
operand. An attempt to execute VPERMD encoded with VEX.L= 0 will cause an #UD
exception.

Operation:

VPERMD (VEX.256 encoded version)
DEST[31:0] <- (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] <- (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] <- (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] <- (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] <- (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] <- (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] <- (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] <- (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];

Intel C/C++ Compiler Intrinsic Equivalent:
VPERMD: __m256i _mm256_permutevar8x32_epi32(__m256i a, __m256i offsets);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 0 for VPERMD, If VEX.W =
|    | 1.                                 


platform: x86
mnem: VPERMPD
description:
VPERMPD  -  Permute Double-Precision Floating-Point Elements:
| Opcode/Instruction                 | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                            
| VEX.256.66.0F3A.W1 01 /r ib VPERMPD| RMI  | V/V            | AVX2              | Permute double-precision floating-point
| ymm1, ymm2/m256, imm8              |      |                |                   | elements in ymm2/m256 using indexes    
|                                    |      |                |                   | in imm8 and store the result in ymm1.  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| Imm8     | NA       

Description:
Use two-bit index values in the immediate byte to select a double-precision
floating-point element in the source operand; the resultant data from the source
operand is copied to the corresponding element of the destination operand in
the order of the index field. Note that this instruction permits a qword in
the source operand to be copied to multiple location in the destination operand.
An attempt to execute VPERMPD encoded with VEX.L= 0 will cause an #UD exception.

Operation:

VPERMPD (VEX.256 encoded version)
DEST[63:0] <- (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] <- (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] <- (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] <- (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];

Intel C/C++ Compiler Intrinsic Equivalent:
VPERMPD: __m256d _mm256_permute4x64_pd(__m256d a, int control) ;


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 0.


platform: x86
mnem: VPERMPS
description:
VPERMPS  -  Permute Single-Precision Floating-Point Elements:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                            
| VEX.NDS.256.66.0F38.W0 16 /r VPERMPS| RVM  | V/V            | AVX2              | Permute single-precision floating-point
| ymm1, ymm2, ymm3/m256               |      |                |                   | elements in ymm3/m256 using indexes    
|                                     |      |                |                   | in ymm2 and store the result in ymm1.  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       

Description:
Use the index values in each dword element of the first source operand (the
second operand) to select a singleprecision floating-point element in the second
source operand (the third operand), the resultant data from the second source
operand is copied to the destination operand (the first operand) in the corresponding
position of the index element. Note that this instruction permits a doubleword
in the source operand to be copied to more than one doubleword location in the
destination operand. An attempt to execute VPERMPS encoded with VEX.L= 0 will
cause an #UD exception.

Operation:

VPERMPS (VEX.256 encoded version)
DEST[31:0] <- (SRC2[255:0] >> (SRC1[2:0] * 32))[31:0];
DEST[63:32] <- (SRC2[255:0] >> (SRC1[34:32] * 32))[31:0];
DEST[95:64] <- (SRC2[255:0] >> (SRC1[66:64] * 32))[31:0];
DEST[127:96] <- (SRC2[255:0] >> (SRC1[98:96] * 32))[31:0];
DEST[159:128] <- (SRC2[255:0] >> (SRC1[130:128] * 32))[31:0];
DEST[191:160] <- (SRC2[255:0] >> (SRC1[162:160] * 32))[31:0];
DEST[223:192] <- (SRC2[255:0] >> (SRC1[194:192] * 32))[31:0];
DEST[255:224] <- (SRC2[255:0] >> (SRC1[226:224] * 32))[31:0];

Intel C/C++ Compiler Intrinsic Equivalent:
VPERMPS: __m256i _mm256_permutevar8x32_ps(__m256 a, __m256i offsets)


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 0, If VEX.W = 1.


platform: x86
mnem: VPERMQ
description:
VPERMQ  -  Qwords Element Permutation:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                              
| VEX.256.66.0F3A.W1 00 /r ib VPERMQ ymm1,| RMI  | V/V            | AVX2              | Permute qwords in ymm2/m256 using indexes
| ymm2/m256, imm8                         |      |                |                   | in imm8 and store the result in ymm1.    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| Imm8     | NA       

Description:
Use two-bit index values in the immediate byte to select a qword element in
the source operand, the resultant qword value from the source operand is copied
to the corresponding element of the destination operand in the order of the
index field. Note that this instruction permits a qword in the source operand
to be copied to multiple locations in the destination operand. An attempt to
execute VPERMQ encoded with VEX.L= 0 will cause an #UD exception.

Operation:

VPERMQ (VEX.256 encoded version)
DEST[63:0] <- (SRC[255:0] >> (IMM8[1:0] * 64))[63:0];
DEST[127:64] <- (SRC[255:0] >> (IMM8[3:2] * 64))[63:0];
DEST[191:128] <- (SRC[255:0] >> (IMM8[5:4] * 64))[63:0];
DEST[255:192] <- (SRC[255:0] >> (IMM8[7:6] * 64))[63:0];

Intel C/C++ Compiler Intrinsic Equivalent:
VPERMQ: __m256i _mm256_permute4x64_epi64(__m256i a, int control)


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 0.


platform: x86
mnem: VPERM2I128
description:
VPERM2I128  -  Permute Integer Values:
| Opcode/Instruction                        | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                          
| VEX.NDS.256.66.0F3A.W0 46 /r ib VPERM2I128| RVMI | V/V            | AVX2              | Permute 128-bit integer data in ymm2 
| ymm1, ymm2, ymm3/m256, imm8               |      |                |                   | and ymm3/mem using controls from imm8
|                                           |      |                |                   | and store result in ymm1.            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVMI | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| Imm8     

Description:
Permute 128 bit integer data from the first source operand (second operand)
and second source operand (third operand) using bits in the 8-bit immediate
and store results in the destination operand (first operand). The first source
operand is a YMM register, the second source operand is a YMM register or a
256-bit memory location, and the destination operand is a YMM register.

| SRC2| Y1                            | Y0                                    
| SRC1| X1                            | X0                                    
| DEST| X0, X1, Y0, or Y1 Figure 4-37.| X0, X1, Y0, or Y1 VPERM2I128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4]
select the source for the second destination field. If imm8[3] is set, the low
128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.

Operation:

VPERM2I128
CASE IMM8[1:0] of
0: DEST[127:0] <- SRC1[127:0]
1: DEST[127:0] <- SRC1[255:128]
2: DEST[127:0] <- SRC2[127:0]
3: DEST[127:0] <- SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] <- SRC1[127:0]
1: DEST[255:128] <- SRC1[255:128]
2: DEST[255:128] <- SRC2[127:0]
3: DEST[255:128] <- SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] <- 0
FI
IF (imm8[7])
DEST[255:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VPERM2I128: __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, int control)


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.L = 0, If VEX.W = 1.


platform: x86
mnem: VPERMILPD
description:
VPERMILPD  -  Permute Double-Precision Floating-Point Values:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| VEX.NDS.128.66.0F38.W0 0D /r VPERMILPD| RVM  | V/V                   | AVX               | Permute double-precision floating-point    
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | values in xmm2 using controls from xmm3/mem
|                                       |      |                       |                   | and store result in xmm1.                  
| VEX.NDS.256.66.0F38.W0 0D /r VPERMILPD| RVM  | V/V                   | AVX               | Permute double-precision floating-point    
| ymm1, ymm2, ymm3/m256                 |      |                       |                   | values in ymm2 using controls from ymm3/mem
|                                       |      |                       |                   | and store result in ymm1.                  
| VEX.128.66.0F3A.W0 05 /r ib VPERMILPD | RMI  | V/V                   | AVX               | Permute double-precision floating-point    
| xmm1, xmm2/m128, imm8                 |      |                       |                   | values in xmm2/mem using controls from     
|                                       |      |                       |                   | imm8.                                      
| VEX.256.66.0F3A.W0 05 /r ib VPERMILPD | RMI  | V/V                   | AVX               | Permute double-precision floating-point    
| ymm1, ymm2/m256, imm8                 |      |                       |                   | values in ymm2/mem using controls from     
|                                       |      |                       |                   | imm8.                                      

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       

Description:
Permute double-precision floating-point values in the first source operand (second
operand) using 8-bit control fields in the low bytes of the second source operand
(third operand) and store results in the destination operand (first operand).
The first source operand is a YMM register, the second source operand is a YMM
register or a 256bit memory location, and the destination operand is a YMM register.

| SRC1| X3                 | X2                        | X1    | X0    
| DEST| X2..X3 Figure 4-38.| X2..X3 VPERMILPD operation| X0..X1| X0..X1
There is one control byte per destination double-precision element. Each control
byte is aligned with the low 8 bits of the corresponding double-precision destination
element. Each control byte contains a 1-bit select field (see Figure 4-39) that
determines which of the source elements are selected. Source elements are restricted
to lie in the same source 128-bit region as the destination.

Bit

| 255| 194 193 sel Control Field 4 Figure 4-39.| 127 VPERMILPD Shuffle Control| 66 ignored Control Field 2| 65 sel| 63| 2 ignored Control Field1| 1 sel
(immediate control version) Permute double-precision floating-point values in
the first source operand (second operand) using two, 1-bit control fields in
the low 2 bits of the 8-bit immediate and store results in the destination operand
(first operand). The source operand is a YMM register or 256-bit memory location
and the destination operand is a YMM register. Note: For the VEX.128.66.0F3A
05 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruction
will #UD. Note: For the VEX.256.66.0F3A 05 instruction version, VEX.vvvv is
reserved and must be 1111b otherwise instruction will #UD.

Operation:

VPERMILPD (256-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]
IF (imm8[2] = 0) THEN DEST[191:128]<-SRC1[191:128]
IF (imm8[2] = 1) THEN DEST[191:128]<-SRC1[255:192]
IF (imm8[3] = 0) THEN DEST[255:192]<-SRC1[191:128]
IF (imm8[3] = 1) THEN DEST[255:192]<-SRC1[255:192]
VPERMILPD (128-bit immediate version)
IF (imm8[0] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (imm8[0] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (imm8[1] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (imm8[1] = 1) THEN DEST[127:64]<-SRC1[127:64]
DEST[VLMAX-1:128] <- 0
VPERMILPD (256-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]
IF (SRC2[129] = 0) THEN DEST[191:128]<-SRC1[191:128]
IF (SRC2[129] = 1) THEN DEST[191:128]<-SRC1[255:192]
IF (SRC2[193] = 0) THEN DEST[255:192]<-SRC1[191:128]
IF (SRC2[193] = 1) THEN DEST[255:192]<-SRC1[255:192]
VPERMILPD (128-bit variable version)
IF (SRC2[1] = 0) THEN DEST[63:0]<-SRC1[63:0]
IF (SRC2[1] = 1) THEN DEST[63:0]<-SRC1[127:64]
IF (SRC2[65] = 0) THEN DEST[127:64]<-SRC1[63:0]
IF (SRC2[65] = 1) THEN DEST[127:64]<-SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| VPERMILPD:| __m128d _mm_permute_pd (__m128d a, int
|           | control)                              
| VPERMILPD:| __m256d _mm256_permute_pd (__m256d a, 
|           | int control)                          
| VPERMILPD:| __m128d _mm_permutevar_pd (__m128d a, 
|           | __m128i control);                     
| VPERMILPD:| __m256d _mm256_permutevar_pd (__m256d 
|           | a, __m256i control);                  

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.W = 1


platform: x86
mnem: VPERMILPS
description:
VPERMILPS  -  Permute Single-Precision Floating-Point Values:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| VEX.NDS.128.66.0F38.W0 0C /r VPERMILPS| RVM  | V/V                   | AVX               | Permute single-precision floating-point    
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | values in xmm2 using controls from xmm3/mem
|                                       |      |                       |                   | and store result in xmm1.                  
| VEX.128.66.0F3A.W0 04 /r ib VPERMILPS | RMI  | V/V                   | AVX               | Permute single-precision floating-point    
| xmm1, xmm2/m128, imm8                 |      |                       |                   | values in xmm2/mem using controls from     
|                                       |      |                       |                   | imm8 and store result in xmm1.             
| VEX.NDS.256.66.0F38.W0 0C /r VPERMILPS| RVM  | V/V                   | AVX               | Permute single-precision floating-point    
| ymm1, ymm2, ymm3/m256                 |      |                       |                   | values in ymm2 using controls from ymm3/mem
|                                       |      |                       |                   | and store result in ymm1.                  
| VEX.256.66.0F3A.W0 04 /r ib VPERMILPS | RMI  | V/V                   | AVX               | Permute single-precision floating-point    
| ymm1, ymm2/m256, imm8                 |      |                       |                   | values in ymm2/mem using controls from     
|                                       |      |                       |                   | imm8 and store result in ymm1.             

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       

Description:
(variable control version) Permute single-precision floating-point values in
the first source operand (second operand) using 8-bit control fields in the
low bytes of corresponding elements the shuffle control (third operand) and
store results in the destination operand (first operand). The first source operand
is a YMM register, the second source operand is a YMM register or a 256-bit
memory location, and the destination operand is a YMM register.

| SRC1| X7      | X6      | X5                   | X4      | X3                         | X2     | X1      | X0      
| DEST| X7 .. X4| X7 .. X4| X7 .. X4 Figure 4-40.| X7 .. X4| X3 ..X0 VPERMILPS Operation| X3 ..X0| X3 .. X0| X3 .. X0
There is one control byte per destination single-precision element. Each control
byte is aligned with the low 8 bits of the corresponding single-precision destination
element. Each control byte contains a 2-bit select field (see Figure 4-41) that
determines which of the source elements are selected. Source elements are restricted
to lie in the same source 128-bit region as the destination.

Bit

| 255 ignored| 226 Control Field 7| 225 224 sel Figure 4-41.| 63 ignored VPERMILPS Shuffle Control| 34 Control Field 2| 33 32 sel| 31 ignored Control Field 1| 1 sel| 0
(immediate control version) Permute single-precision floating-point values in
the first source operand (second operand) using four 2-bit control fields in
the 8-bit immediate and store results in the destination operand (first operand).
The source operand is a YMM register or 256-bit memory location and the destination
operand is a YMM register. This is similar to a wider version of PSHUFD, just
operating on single-precision floating-point values. Note: For the VEX.128.66.0F3A
04 instruction version, VEX.vvvv is reserved and must be 1111b otherwise instruction
will #UD. Note: For the VEX.256.66.0F3A 04 instruction version, VEX.vvvv is
reserved and must be 1111b otherwise instruction will #UD.

Operation:

Select4(SRC, control) {
CASE (control[1:0]) OF
  0:
  1:
  2:
  3:
ESAC;
RETURN TMP
}
VPERMILPS (256-bit immediate version)
DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <- Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] <- Select4(SRC1[127:0], imm8[7:6]);
DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] <- Select4(SRC1[255:128], imm8[5:4]);
DEST[255:224] <- Select4(SRC1[255:128], imm8[7:6]);
VPERMILPS (128-bit immediate version)
DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <- Select4(SRC1[127:0], imm8[5:4]);
DEST[127:96] <- Select4(SRC1[127:0], imm8[7:6]);
DEST[VLMAX-1:128] <- 0
VPERMILPS (256-bit variable version)
DEST[31:0] <- Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] <- Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] <- Select4(SRC1[127:0], SRC2[97:96]);
DEST[159:128] <- Select4(SRC1[255:128], SRC2[129:128]);
DEST[191:160] <- Select4(SRC1[255:128], SRC2[161:160]);
DEST[223:192] <- Select4(SRC1[255:128], SRC2[193:192]);
DEST[255:224] <- Select4(SRC1[255:128], SRC2[225:224]);
VPERMILPS (128-bit variable version)
DEST[31:0] <- Select4(SRC1[127:0], SRC2[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], SRC2[33:32]);
DEST[95:64] <- Select4(SRC1[127:0], SRC2[65:64]);
DEST[127:96] <- Select4(SRC1[127:0], SRC2[97:96]);
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| VPERM1LPS:| __m128 _mm_permute_ps (__m128 a, int
|           | control);                           
| VPERM1LPS:| __m256 _mm256_permute_ps (__m256 a, 
|           | int control);                       
| VPERM1LPS:| __m128 _mm_permutevar_ps (__m128 a, 
|           | __m128i control);                   
| VPERM1LPS:| __m256 _mm256_permutevar_ps (__m256 
|           | a, __m256i control);                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: VPERM2F128
description:
VPERM2F128  -  Permute Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| VEX.NDS.256.66.0F3A.W0 06 /r ib VPERM2F128| RVMI | V/V                   | AVX               | Permute 128-bit floating-point fields
| ymm1, ymm2, ymm3/m256, imm8               |      |                       |                   | in ymm2 and ymm3/mem using controls  
|                                           |      |                       |                   | from imm8 and store result in ymm1.  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2   | Operand 3    | Operand 4
| RVMI | ModRM:reg (w)| VEX.vvvv (r)| ModRM:r/m (r)| imm8     

Description:
Permute 128 bit floating-point-containing fields from the first source operand
(second operand) and second source operand (third operand) using bits in the
8-bit immediate and store results in the destination operand (first operand).
The first source operand is a YMM register, the second source operand is a YMM
register or a 256-bit memory location, and the destination operand is a YMM
register.

| SRC2| Y1                            | Y0                                    
| SRC1| X1                            | X0                                    
| DEST| X0, X1, Y0, or Y1 Figure 4-42.| X0, X1, Y0, or Y1 VPERM2F128 Operation
Imm8[1:0] select the source for the first destination 128-bit field, imm8[5:4]
select the source for the second destination field. If imm8[3] is set, the low
128-bit field is zeroed. If imm8[7] is set, the high 128-bit field is zeroed.
VEX.L must be 1, otherwise the instruction will #UD.

Operation:

VPERM2F128
CASE IMM8[1:0] of
0: DEST[127:0] <- SRC1[127:0]
1: DEST[127:0] <- SRC1[255:128]
2: DEST[127:0] <- SRC2[127:0]
3: DEST[127:0] <- SRC2[255:128]
ESAC
CASE IMM8[5:4] of
0: DEST[255:128] <- SRC1[127:0]
1: DEST[255:128] <- SRC1[255:128]
2: DEST[255:128] <- SRC2[127:0]
3: DEST[255:128] <- SRC2[255:128]
ESAC
IF (imm8[3])
DEST[127:0] <- 0
FI
IF (imm8[7])
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| VPERM2F128:| __m256 _mm256_permute2f128_ps (__m256     
|            | a, __m256 b, int control)                 
| VPERM2F128:| __m256d _mm256_permute2f128_pd (__m256d   
|            | a, __m256d b, int control)                
| VPERM2F128:| __m256i _mm256_permute2f128_si256 (__m256i
|            | a, __m256i b, int control)                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.L = 0 If VEX.W = 1.


platform: x86
mnem: VPMASKMOV
description:
VPMASKMOV  -  Conditional SIMD Integer Packed Loads and Stores:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                          
| VEX.NDS.128.66.0F38.W0 8C /r VPMASKMOVD| RVM  | V/V            | AVX2              | Conditionally load dword values from 
| xmm1, xmm2, m128                       |      |                |                   | m128 using mask in xmm2 and store in 
|                                        |      |                |                   | xmm1.                                
| VEX.NDS.256.66.0F38.W0 8C /r VPMASKMOVD| RVM  | V/V            | AVX2              | Conditionally load dword values from 
| ymm1, ymm2, m256                       |      |                |                   | m256 using mask in ymm2 and store in 
|                                        |      |                |                   | ymm1.                                
| VEX.NDS.128.66.0F38.W1 8C /r VPMASKMOVQ| RVM  | V/V            | AVX2              | Conditionally load qword values from 
| xmm1, xmm2, m128                       |      |                |                   | m128 using mask in xmm2 and store in 
|                                        |      |                |                   | xmm1.                                
| VEX.NDS.256.66.0F38.W1 8C /r VPMASKMOVQ| RVM  | V/V            | AVX2              | Conditionally load qword values from 
| ymm1, ymm2, m256                       |      |                |                   | m256 using mask in ymm2 and store in 
|                                        |      |                |                   | ymm1.                                
| VEX.NDS.128.66.0F38.W0 8E /r VPMASKMOVD| MVR  | V/V            | AVX2              | Conditionally store dword values from
| m128, xmm1, xmm2                       |      |                |                   | xmm2 using mask in xmm1.             
| VEX.NDS.256.66.0F38.W0 8E /r VPMASKMOVD| MVR  | V/V            | AVX2              | Conditionally store dword values from
| m256, ymm1, ymm2                       |      |                |                   | ymm2 using mask in ymm1.             
| VEX.NDS.128.66.0F38.W1 8E /r VPMASKMOVQ| MVR  | V/V            | AVX2              | Conditionally store qword values from
| m128, xmm1, xmm2                       |      |                |                   | xmm2 using mask in xmm1.             
| VEX.NDS.256.66.0F38.W1 8E /r VPMASKMOVQ| MVR  | V/V            | AVX2              | Conditionally store qword values from
| m256, ymm1, ymm2                       |      |                |                   | ymm2 using mask in ymm1.             

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       
| MVR  | ModRM:r/m (w)| VEX.vvvv | ModRM:reg (r)| NA       

Description:
Conditionally moves packed data elements from the second source operand into
the corresponding data element of the destination operand, depending on the
mask bits associated with each data element. The mask bits are specified in
the first source operand. The mask bit for each data element is the most significant
bit of that element in the first source operand. If a mask is 1, the corresponding
data element is copied from the second source operand to the destination operand.
If the mask is 0, the corresponding data element is set to zero in the load
form of these instructions, and unmodified in the store form. The second source
operand is a memory address for the load form of these instructions. The destination
operand is a memory address for the store form of these instructions. The other
operands are either XMM registers (for VEX.128 version) or YMM registers (for
VEX.256 version). Faults occur only due to mask-bit required memory accesses
that caused the faults. Faults will not occur due to referencing any memory
location if the corresponding mask bit for that memory location is 0. For example,
no faults will be detected if the mask bits are all zero. Unlike previous MASKMOV
instructions (MASKMOVQ and MASKMOVDQU), a nontemporal hint is not applied to
these instructions.

Instruction behavior on alignment check reporting with mask bits of less than
all 1s are the same as with mask bits of all 1s. VMASKMOV should not be used
to access memory mapped I/O as the ordering of the individual loads or stores
it does is implementation specific. In cases where mask bits indicate data should
not be loaded or stored paging A and D bits will be set in an implementation
dependent way. However, A and D bits are always set for pages where data is
actually loaded/stored. Note: for load forms, the first source (the mask) is
encoded in VEX.vvvv; the second source is encoded in rm_field, and the destination
register is encoded in reg_field. Note: for store forms, the first source (the
mask) is encoded in VEX.vvvv; the second source register is encoded in reg_field,
and the destination memory location is encoded in rm_field.

Operation:

VPMASKMOVD - 256-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:96] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[159:128] <- IF (SRC1[159]) Load_32(mem + 16) ELSE 0
DEST[191:160] <- IF (SRC1[191]) Load_32(mem + 20) ELSE 0
DEST[223:192] <- IF (SRC1[223]) Load_32(mem + 24) ELSE 0
DEST[255:224] <- IF (SRC1[255]) Load_32(mem + 28) ELSE 0
VPMASKMOVD -128-bit load
DEST[31:0] <- IF (SRC1[31]) Load_32(mem) ELSE 0
DEST[63:32] <- IF (SRC1[63]) Load_32(mem + 4) ELSE 0
DEST[95:64] <- IF (SRC1[95]) Load_32(mem + 8) ELSE 0
DEST[127:97] <- IF (SRC1[127]) Load_32(mem + 12) ELSE 0
DEST[VLMAX-1:128] <- 0
VPMASKMOVQ - 256-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 8) ELSE 0
DEST[195:128] <- IF (SRC1[191]) Load_64(mem + 16) ELSE 0
DEST[255:196] <- IF (SRC1[255]) Load_64(mem + 24) ELSE 0
VPMASKMOVQ - 128-bit load
DEST[63:0] <- IF (SRC1[63]) Load_64(mem) ELSE 0
DEST[127:64] <- IF (SRC1[127]) Load_64(mem + 16) ELSE 0
DEST[VLMAX-1:128] <- 0
VPMASKMOVD - 256-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
IF (SRC1[159]) DEST[159:128] <-SRC2[159:128]
IF (SRC1[191]) DEST[191:160] <- SRC2[191:160]
IF (SRC1[223]) DEST[223:192] <- SRC2[223:192]
IF (SRC1[255]) DEST[255:224] <- SRC2[255:224]
VPMASKMOVD - 128-bit store
IF (SRC1[31]) DEST[31:0] <- SRC2[31:0]
IF (SRC1[63]) DEST[63:32] <- SRC2[63:32]
IF (SRC1[95]) DEST[95:64] <- SRC2[95:64]
IF (SRC1[127]) DEST[127:96] <- SRC2[127:96]
VPMASKMOVQ - 256-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]
IF (SRC1[191]) DEST[191:128] <- SRC2[191:128]
IF (SRC1[255]) DEST[255:192] <- SRC2[255:192]
VPMASKMOVQ - 128-bit store
IF (SRC1[63]) DEST[63:0] <- SRC2[63:0]
IF (SRC1[127]) DEST[127:64] <-SRC2[127:64]

Intel C/C++ Compiler Intrinsic Equivalent:
VPMASKMOVD: __m256i _mm256_maskload_epi32(int const *a, __m256i mask)

| VPMASKMOVD: void VPMASKMOVQ: __m256i     | _mm256_maskstore_epi32(int *a, __m256i    
| _mm256_maskload_epi64(__int64 const      | mask, __m256i b)                          
| *a, __m256i mask);                       |                                           
| VPMASKMOVQ: void VPMASKMOVD: __m128i     | _mm256_maskstore_epi64(__int64 *a, __m256i
| _mm_maskload_epi32(int const *a, __m128i | mask, __m256d b);                         
| mask)                                    |                                           
| VPMASKMOVD: void VPMASKMOVQ: __m128i     | _mm_maskstore_epi32(int *a, __m128i       
| _mm_maskload_epi64(__int cont *a, __m128i| mask, __m128 b)                           
| mask);                                   |                                           
| VPMASKMOVQ: void                         | _mm_maskstore_epi64(__int64 *a, __m128i   
|                                          | mask, __m128i b);                         

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6 (No AC# reported for any mask bit combinations).


platform: x86
mnem: VPSLLVD
description:
VPSLLVD/VPSLLVQ  -  Variable Bit Shift Left Logical:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDS.128.66.0F38.W0 47 /r VPSLLVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in xmm2 left  
| xmm1, xmm2, xmm3/m128               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of xmm3/m128 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.128.66.0F38.W1 47 /r VPSLLVQ| RVM  | V/V            | AVX2              | Shift bits in quadwords in xmm2 left    
| xmm1, xmm2, xmm3/m128               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of xmm3/m128 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.256.66.0F38.W0 47 /r VPSLLVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in ymm2 left  
| ymm1, ymm2, ymm3/m256               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of ymm3/m256 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.256.66.0F38.W1 47 /r VPSLLVQ| RVM  | V/V            | AVX2              | Shift bits in quadwords in ymm2 left    
| ymm1, ymm2, ymm3/m256               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of ymm3/m256 while shifting     
|                                     |      |                |                   | in 0s.                                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       

Description:
Shifts the bits in the individual data elements (doublewords, or quadword) in
the first source operand to the left by the count value of respective data elements
in the second source operand. As the bits in the data elements are shifted left,
the empty low-order bits are cleared (set to 0). The count values are specified
individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source
operand is greater than 31 (for doublewords), or 63 (for a quadword), then the
destination data element are written with 0. VEX.128 encoded version: The destination
and first source operands are XMM registers. The count operand can be either
an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM register are zeroed. VEX.256 encoded version: The destination and first
source operands are YMM registers. The count operand can be either an YMM register
or a 256-bit memory location.

Operation:

VPSLLVD (VEX.128 version)
COUNT_0 <- SRC2[31 : 0]
  (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] <- ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] <- 0;
  (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] <- ZeroExtend(SRC1[127:96] << COUNT_3);
ELSE
DEST[127:96] <- 0;
DEST[VLMAX-1:128] <- 0;
VPSLLVD (VEX.256 version)
COUNT_0 <- SRC2[31 : 0];
  (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 <- SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] <- ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] <- 0;
  (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] <- ZeroExtend(SRC1[255:224] << COUNT_7);
ELSE
DEST[255:224] <- 0;
VPSLLVQ (VEX.128 version)
COUNT_0 <- SRC2[63 : 0];
COUNT_1 <- SRC2[127 : 64];
IF COUNT_0 < 64THEN
DEST[63:0] <- ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] <- 0;
IF COUNT_1 < 64 THEN
DEST[127:64] <- ZeroExtend(SRC1[127:64] << COUNT_1);
ELSE
DEST[127:96] <- 0;
DEST[VLMAX-1:128] <- 0;
VPSLLVQ (VEX.256 version)
COUNT_0 <- SRC2[5 : 0];
  (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[197 : 192];
IF COUNT_0 < 64THEN
DEST[63:0] <- ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] <- 0;
  (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] <- ZeroExtend(SRC1[255:192] << COUNT_3);
ELSE
DEST[255:192] <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
VPSLLVD: __m256i _mm256_sllv_epi32 (__m256i m, __m256i count)

VPSLLVD: __m128i _mm_sllv_epi32 (__m128i m, __m128i count)

VPSLLVQ: __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)

VPSLLVQ: __m128i _mm_sllv_epi64 (__m128i m, __m128i count)


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4


platform: x86
mnem: VPSRAVD
description:
VPSRAVD  -  Variable Bit Shift Right Arithmetic:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDS.128.66.0F38.W0 46 /r VPSRAVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in xmm2 right 
| xmm1, xmm2, xmm3/m128               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of xmm3/m128 while shifting     
|                                     |      |                |                   | in the sign bits.                       
| VEX.NDS.256.66.0F38.W0 46 /r VPSRAVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in ymm2 right 
| ymm1, ymm2, ymm3/m256               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of ymm3/m256 while shifting     
|                                     |      |                |                   | in the sign bits.                       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       

Description:
Shifts the bits in the individual doubleword data elements in the first source
operand to the right by the count value of respective data elements in the second
source operand. As the bits in each data element are shifted right, the empty
high-order bits are filled with the sign bit of the source element. The count
values are specified individually in each data element of the second source
operand. If the unsigned integer value specified in the respective data element
of the second source operand is greater than 31, then the destination data element
are filled with the corresponding sign bit of the source element. VEX.128 encoded
version: The destination and first source operands are XMM registers. The count
operand can be either an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM register are zeroed. VEX.256 encoded version: The destination
and first source operands are YMM registers. The count operand can be either
an YMM register or a 256-bit memory location.

Operation:

VPSRAVD (VEX.128 version)
COUNT_0 <- SRC2[31: 0]
  (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[127 : 112];
IF COUNT_0 < 32 THEN
  DEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);
ELSE
  For (i = 0 to 31) DEST[i + 0] <- (SRC1[31] );
FI;
  (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
  DEST[127:96] <- SignExtend(SRC1[127:96] >> COUNT_3);
ELSE
  For (i = 0 to 31) DEST[i + 96] <- (SRC1[127] );
FI;
DEST[VLMAX-1:128] <- 0;
VPSRAVD (VEX.256 version)
COUNT_0 <- SRC2[31 : 0];
  (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 <- SRC2[255 : 224];
IF COUNT_0 < 32 THEN
  DEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);
ELSE
  For (i = 0 to 31) DEST[i + 0] <- (SRC1[31] );
FI;
  (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
  DEST[255:224] <- SignExtend(SRC1[255:224] >> COUNT_7);
ELSE
  For (i = 0 to 31) DEST[i + 224] <- (SRC1[255] );
FI;

Intel C/C++ Compiler Intrinsic Equivalent:
VPSRAVD: __m256i _mm256_srav_epi32 (__m256i m, __m256i count)

VPSRAVD: __m128i _mm_srav_epi32 (__m128i m, __m128i count)


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: VPSRLVD
description:
VPSRLVD/VPSRLVQ  -  Variable Bit Shift Right Logical:
| Opcode/Instruction                  | Op/EN| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDS.128.66.0F38.W0 45 /r VPSRLVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in xmm2 right 
| xmm1, xmm2, xmm3/m128               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of xmm3/m128 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.128.66.0F38.W1 45 /r VPSRLVQ| RVM  | V/V            | AVX2              | Shift bits in quadwords in xmm2 right   
| xmm1, xmm2, xmm3/m128               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of xmm3/m128 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.256.66.0F38.W0 45 /r VPSRLVD| RVM  | V/V            | AVX2              | Shift bits in doublewords in ymm2 right 
| ymm1, ymm2, ymm3/m256               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of ymm3/m256 while shifting     
|                                     |      |                |                   | in 0s.                                  
| VEX.NDS.256.66.0F38.W1 45 /r VPSRLVQ| RVM  | V/V            | AVX2              | Shift bits in quadwords in ymm2 right   
| ymm1, ymm2, ymm3/m256               |      |                |                   | by amount specified in the corresponding
|                                     |      |                |                   | element of ymm3/m256 while shifting     
|                                     |      |                |                   | in 0s.                                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv | ModRM:r/m (r)| NA       

Description:
Shifts the bits in the individual data elements (doublewords, or quadword) in
the first source operand to the right by the count value of respective data
elements in the second source operand. As the bits in the data elements are
shifted right, the empty high-order bits are cleared (set to 0). The count values
are specified individually in each data element of the second source operand.
If the unsigned integer value specified in the respective data element of the
second source operand is greater than 31 (for doublewords), or 63 (for a quadword),
then the destination data element are written with 0. VEX.128 encoded version:
The destination and first source operands are XMM registers. The count operand
can be either an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM register are zeroed. VEX.256 encoded version: The destination
and first source operands are YMM registers. The count operand can be either
an YMM register or a 256-bit memory location.

Operation:

VPSRLVD (VEX.128 version)
COUNT_0 <- SRC2[31 : 0]
  (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[127 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] <- ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] <- 0;
  (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] <- ZeroExtend(SRC1[127:96] >> COUNT_3);
ELSE
DEST[127:96] <- 0;
DEST[VLMAX-1:128] <- 0;
VPSRLVD (VEX.256 version)
COUNT_0 <- SRC2[31 : 0];
  (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 <- SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] <- ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] <- 0;
  (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] <- ZeroExtend(SRC1[255:224] >> COUNT_7);
ELSE
DEST[255:224] <- 0;
VPSRLVQ (VEX.128 version)
COUNT_0 <- SRC2[63 : 0];
COUNT_1 <- SRC2[127 : 64];
IF COUNT_0 < 64 THEN
DEST[63:0] <- ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] <- 0;
IF COUNT_1 < 64THEN
DEST[127:64] <- ZeroExtend(SRC1[127:64] >> COUNT_1);
ELSE
DEST[127:64] <- 0;
DEST[VLMAX-1:128] <- 0;
VPSRLVQ (VEX.256 version)
COUNT_0 <- SRC2[63 : 0];
  (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[255 : 192];
IF COUNT_0 < 64 THEN
DEST[63:0] <- ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] <- 0;
  (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64THEN
DEST[255:192] <- ZeroExtend(SRC1[255:192] >> COUNT_3);
ELSE
DEST[255:192] <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
VPSRLVD: __m256i _mm256_srlv_epi32 (__m256i m, __m256i count);

VPSRLVD: __m128i _mm_srlv_epi32 (__m128i m, __m128i count);

VPSRLVQ: __m256i _mm256_srlv_epi64 (__m256i m, __m256i count);

VPSRLVQ: __m128i _mm_srlv_epi64 (__m128i m, __m128i count);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 4


platform: x86
mnem: VTESTPD
description:
VTESTPD/VTESTPS - Packed Bit Test:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| VEX.128.66.0F38.W0 0E /r VTESTPS xmm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on sign bit    
| xmm2/m128                             |      |                       |                   | AND and ANDN of packed single-precision
|                                       |      |                       |                   | floating-point sources.                
| VEX.256.66.0F38.W0 0E /r VTESTPS ymm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on sign bit    
| ymm2/m256                             |      |                       |                   | AND and ANDN of packed single-precision
|                                       |      |                       |                   | floating-point sources.                
| VEX.128.66.0F38.W0 0F /r VTESTPD xmm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on sign bit    
| xmm2/m128                             |      |                       |                   | AND and ANDN of packed double-precision
|                                       |      |                       |                   | floating-point sources.                
| VEX.256.66.0F38.W0 0F /r VTESTPD ymm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on sign bit    
| ymm2/m256                             |      |                       |                   | AND and ANDN of packed double-precision
|                                       |      |                       |                   | floating-point sources.                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
VTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision
elements in the first source operation and corresponding sign bits in the second
source operand. If the AND of the source sign bits with the dest sign bits produces
all zeros, the ZF is set else the ZF is clear. If the AND of the source sign
bits with the inverted dest sign bits produces all zeros the CF is set else
the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will cause #UD.
VTESTPD performs a bitwise comparison of all the sign bits of the double-precision
elements in the first source operation and corresponding sign bits in the second
source operand. If the AND of the source sign bits with the dest sign bits produces
all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits
with the inverted dest sign bits produces all zeros the CF is set else the CF
is clear. An attempt to execute VTESTPS with VEX.W=1 will cause #UD. The first
source register is specified by the ModR/M reg field. 128-bit version: The first
source register is an XMM register. The second source register can be an XMM
register or a 128-bit memory location. The destination register is not modified.
VEX.256 encoded version: The first source register is a YMM register. The second
source register can be a YMM register or a 256-bit memory location. The destination
register is not modified. Note: In VEX-encoded versions, VEX.vvvv is reserved
and must be 1111b, otherwise instructions will #UD.

Operation:

VTESTPS (128-bit version)
TEMP[127:0] <- SRC[127:0] AND DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
  THEN ZF <-1;
  ELSE ZF <- 0;
TEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
  THEN CF <-1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;
VTESTPS (VEX.256 encoded version)
TEMP[255:0] <- SRC[255:0] AND DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
  THEN ZF <-1;
  ELSE ZF <- 0;
TEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
  THEN CF <-1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;
VTESTPD (128-bit version)
TEMP[127:0] <- SRC[127:0] AND DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
  THEN ZF <-1;
  ELSE ZF <- 0;
TEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
  THEN CF <-1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;
VTESTPD (VEX.256 encoded version)
TEMP[255:0] <- SRC[255:0] AND DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
  THEN ZF <-1;
  ELSE ZF <- 0;
TEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
  THEN CF <-1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
VTESTPS

int _mm256_testz_ps (__m256 s1, __m256 s2);

int _mm256_testc_ps (__m256 s1, __m256 s2);

int _mm256_testnzc_ps (__m256 s1, __m128 s2);

int _mm_testz_ps (__m128 s1, __m128 s2);

int _mm_testc_ps (__m128 s1, __m128 s2);

int _mm_testnzc_ps (__m128 s1, __m128 s2);

VTESTPD

int _mm256_testz_pd (__m256d s1, __m256d s2);

int _mm256_testc_pd (__m256d s1, __m256d s2);

int _mm256_testnzc_pd (__m256d s1, __m256d s2);

int _mm_testz_pd (__m128d s1, __m128d s2);

int _mm_testc_pd (__m128d s1, __m128d s2);

int _mm_testnzc_pd (__m128d s1, __m128d s2);


Flags Affected:
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according
to the operation.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.vvvv != 1111B. If VEX.W = 1 for
|    | VTESTPS or VTESTPD.                   


platform: x86
mnem: VZEROALL
description:
VZEROALL - Zero All YMM Registers:
| Opcode/Instruction        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description            
| VEX.256.0F.WIG 77 VZEROALL| NP   | V/V                   | AVX               | Zero all YMM registers.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
The instruction zeros contents of all XMM or YMM registers. Note: VEX.vvvv is
reserved and must be 1111b, otherwise instructions will #UD. In Compatibility
and legacy 32-bit mode only the lower 8 registers are modified.

Operation:

VZEROALL (VEX.256 encoded version)
IF (64-bit mode)
  YMM0[VLMAX-1:0] <- 0
  YMM1[VLMAX-1:0] <- 0
  YMM2[VLMAX-1:0] <- 0
  YMM3[VLMAX-1:0] <- 0
  YMM4[VLMAX-1:0] <- 0
  YMM5[VLMAX-1:0] <- 0
  YMM6[VLMAX-1:0] <- 0
  YMM7[VLMAX-1:0] <- 0
  YMM8[VLMAX-1:0] <- 0
  YMM9[VLMAX-1:0] <- 0
  YMM10[VLMAX-1:0] <- 0
  YMM11[VLMAX-1:0] <- 0
  YMM12[VLMAX-1:0] <- 0
  YMM13[VLMAX-1:0] <- 0
  YMM14[VLMAX-1:0] <- 0
  YMM15[VLMAX-1:0] <- 0
ELSE
  YMM0[VLMAX-1:0] <- 0
  YMM1[VLMAX-1:0] <- 0
  YMM2[VLMAX-1:0] <- 0
  YMM3[VLMAX-1:0] <- 0
  YMM4[VLMAX-1:0] <- 0
  YMM5[VLMAX-1:0] <- 0
  YMM6[VLMAX-1:0] <- 0
  YMM7[VLMAX-1:0] <- 0
  YMM8-15: Unmodified
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| VZEROALL:| _mm256_zeroall()

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 8.


platform: x86
mnem: VZEROUPPER
description:
VZEROUPPER - Zero Upper Bits of YMM Registers:
| Opcode/Instruction          | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| VEX.128.0F.WIG 77 VZEROUPPER| NP   | V/V                   | AVX               | Zero upper 128 bits of all YMM registers.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
The instruction zeros the bits in position 128 and higher of all YMM registers.
The lower 128-bits of the registers (the corresponding XMM registers) are unmodified.

This instruction is recommended when transitioning between AVX and legacy SSE
code - it will eliminate performance penalties caused by false dependencies.
Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
In Compatibility and legacy 32-bit mode only the lower 8 registers are modified.

Operation:

VZEROUPPER
IF (64-bit mode)
  YMM0[VLMAX-1:128] <- 0
  YMM1[VLMAX-1:128] <- 0
  YMM2[VLMAX-1:128] <- 0
  YMM3[VLMAX-1:128] <- 0
  YMM4[VLMAX-1:128] <- 0
  YMM5[VLMAX-1:128] <- 0
  YMM6[VLMAX-1:128] <- 0
  YMM7[VLMAX-1:128] <- 0
  YMM8[VLMAX-1:128] <- 0
  YMM9[VLMAX-1:128] <- 0
  YMM10[VLMAX-1:128] <- 0
  YMM11[VLMAX-1:128] <- 0
  YMM12[VLMAX-1:128] <- 0
  YMM13[VLMAX-1:128] <- 0
  YMM14[VLMAX-1:128] <- 0
  YMM15[VLMAX-1:128] <- 0
ELSE
  YMM0[VLMAX-1:128] <- 0
  YMM1[VLMAX-1:128] <- 0
  YMM2[VLMAX-1:128] <- 0
  YMM3[VLMAX-1:128] <- 0
  YMM4[VLMAX-1:128] <- 0
  YMM5[VLMAX-1:128] <- 0
  YMM6[VLMAX-1:128] <- 0
  YMM7[VLMAX-1:128] <- 0
  YMM8-15: unmodified
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| VZEROUPPER:| _mm256_zeroupper()

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 8.


platform: x86
mnem: WAIT
description:
WAIT/FWAIT - Wait:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 9B    | WAIT       | NP   | Valid      | Valid          | Check pending unmasked floating-point
|       |            |      |            |                | exceptions.                          
| 9B    | FWAIT      | NP   | Valid      | Valid          | Check pending unmasked floating-point
|       |            |      |            |                | exceptions.                          

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Causes the processor to check for and handle pending, unmasked, floating-point
exceptions before proceeding. (FWAIT is an alternate mnemonic for WAIT.)

This instruction is useful for synchronizing exceptions in critical sections
of code. Coding a WAIT instruction after a floating-point instruction ensures
that any unmasked floating-point exceptions the instruction may raise are handled
before the processor can modify the instruction's results. See the section titled
“Floating-Point Exception Synchronization” in Chapter 8 of the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for more information
on using the WAIT/FWAIT instruction.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CheckForPendingUnmaskedFloatingPointExceptions;

FPU Flags Affected:
The C0, C1, C2, and C3 flags are undefined.


Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| If CR0.MP[bit 1] = 1 and CR0.TS[bit
|    | 3] = 1.                            
| #UD| If the LOCK prefix is used.        

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: WBINVD
description:
WBINVD - Write Back and Invalidate Cache:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 09 | WBINVD     | NP   | Valid      | Valid          | Write back and flush Internal caches;
|       |            |      |            |                | initiate writing-back and flushing of
|       |            |      |            |                | external caches.                     

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Writes back all modified cache lines in the processor's internal cache to main
memory and invalidates (flushes) the internal caches. The instruction then issues
a special-function bus cycle that directs external caches to also write back
modified data and another bus cycle to indicate that the external caches should
be invalidated.

After executing this instruction, the processor does not wait for the external
caches to complete their write-back and flushing operations before proceeding
with instruction execution. It is the responsibility of hardware to respond
to the cache write-back and flush signals. The amount of time or cycles for
WBINVD to complete will vary due to size and other factors of different cache
hierarchies. As a consequence, the use of the WBINVD instruction can have an
impact on logical processor interrupt/event response time. Additional information
of WBINVD behavior in a cache hierarchy with hierarchical sharing topology can
be found in Chapter 2 of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.

The WBINVD instruction is a privileged instruction. When the processor is running
in protected mode, the CPL of a program or procedure must be 0 to execute this
instruction. This instruction is also a serializing instruction (see “Serializing
Instructions” in Chapter 8 of the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A).

In situations where cache coherency with main memory is not a concern, software
can use the INVD instruction.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
The WBINVD instruction is implementation dependent, and its function may be
implemented differently on future Intel 64 and IA-32 processors. The instruction
is not supported on IA-32 processors earlier than the Intel486 processor.

Operation:

WriteBack(InternalCaches);
Flush(InternalCaches);
SignalWriteBack(ExternalCaches);
SignalFlush(ExternalCaches);
Continue; (* Continue execution *)

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not
|       | 0.                                   
| #UD   | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)| WBINVD cannot be executed at the virtual-8086
|       | mode.                                        

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: WRFSBASE
description:
WRFSBASE/WRGSBASE - Write FS/GS Segment Base:
| Opcode/Instruction              | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                             
| F3 0F AE /2 WRFSBASE r32        | M    | V/I          | FSGSBASE          | Load the FS base address with the 32-bit
|                                 |      |              |                   | value in the source register.           
| REX.W + F3 0F AE /2 WRFSBASE r64| M    | V/I          | FSGSBASE          | Load the FS base address with the 64-bit
|                                 |      |              |                   | value in the source register.           
| F3 0F AE /3 WRGSBASE r32        | M    | V/I          | FSGSBASE          | Load the GS base address with the 32-bit
|                                 |      |              |                   | value in the source register.           
| REX.W + F3 0F AE /3 WRGSBASE r64| M    | V/I          | FSGSBASE          | Load the GS base address with the 64-bit
|                                 |      |              |                   | value in the source register.           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Loads the FS or GS segment base address with the general-purpose register indicated
by the modR/M:r/m field.

The source operand may be either a 32-bit or a 64-bit general-purpose register.
The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is
used, the operand size is 32 bits; the upper 32 bits of the source register
are ignored and upper 32 bits of the base address (for FS or GS) are cleared.
This instruction is supported only in 64-bit mode.

Operation:

FS/GS segment base address <- SRC;

Flags Affected:
None


C/C++ Compiler Intrinsic Equivalent:
| WRFSBASE:| void _writefsbase_u32( unsigned int  
|          | );                                   
| WRFSBASE:| _writefsbase_u64( unsigned __int64 );
| WRGSBASE:| void _writegsbase_u32( unsigned int  
|          | );                                   
| WRGSBASE:| _writegsbase_u64( unsigned __int64 );

Protected Mode Exceptions:
| #UD| The WRFSBASE and WRGSBASE instructions
|    | are not recognized in protected mode. 

Real-Address Mode Exceptions:
| #UD| The WRFSBASE and WRGSBASE instructions  
|    | are not recognized in real-address mode.

Virtual-8086 Mode Exceptions:
| #UD| The WRFSBASE and WRGSBASE instructions  
|    | are not recognized in virtual-8086 mode.

Compatibility Mode Exceptions:
| #UD| The WRFSBASE and WRGSBASE instructions
|    | are not recognized in compatibility   
|    | mode.                                 

64-Bit Mode Exceptions:
| #UD   | If the LOCK prefix is used. If CR4.FSGSBASE[bit
|       | 16] = 0. If CPUID.07H.0H:EBX.FSGSBASE[bit      
|       | 0] = 0                                         
| #GP(0)| If the source register contains a non-canonical
|       | address.                                       


platform: x86
mnem: WRMSR
description:
WRMSR - Write to Model Specific Register:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                
| 0F 30 | WRMSR      | NP   | Valid      | Valid          | Write the value in EDX:EAX to MSR specified
|       |            |      |            |                | by ECX.                                    

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Writes the contents of registers EDX:EAX into the 64-bit model specific register
(MSR) specified in the ECX register. (On processors that support the Intel 64
architecture, the high-order 32 bits of RCX are ignored.) The contents of the
EDX register are copied to high-order 32 bits of the selected MSR and the contents
of the EAX register are copied to low-order 32 bits of the MSR. (On processors
that support the Intel 64 architecture, the high-order 32 bits of each of RAX
and RDX are ignored.) Undefined or reserved bits in an MSR should be set to
values previously read.

This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) is generated. Specifying a
reserved or unimplemented MSR address in ECX will also cause a general protection
exception. The processor will also generate a general protection exception if
software attempts to write to bits in a reserved MSR.

When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated.
This includes global entries (see “Translation Lookaside Buffers (TLBs)” in
Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A).

MSRs control functions for testability, execution tracing, performance-monitoring
and machine check errors. Chapter 35, “Model-Specific Registers (MSRs)”, in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3C,
lists all MSRs that can be written with this instruction and their addresses.
Note that each processor family has its own set of MSRs.

The WRMSR instruction is a serializing instruction (see “Serializing Instructions”
in Chapter 8 of the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE MSR (MSR index 6E0H) and
the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.

The CPUID instruction should be used to determine whether MSRs are supported
(CPUID.01H:EDX[5] = 1) before using this instruction.


IA-32 Architecture Compatibility:
The MSRs and the ability to read them with the WRMSR instruction were introduced
into the IA-32 architecture with the Pentium processor. Execution of this instruction
by an IA-32 processor earlier than the Pentium processor results in an invalid
opcode exception #UD.

Operation:

MSR[ECX] <- EDX:EAX;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not          
|       | 0. If the value in ECX specifies a reserved    
|       | or unimplemented MSR address. If the           
|       | value in EDX:EAX sets bits that are            
|       | reserved in the MSR specified by ECX.          
|       | If the source register contains a non-canonical
|       | address and ECX specifies one of the           
|       | following MSRs: IA32_DS_AREA, IA32_FS_BASE,    
|       | IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, 
|       | IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.          
| #UD   | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If the value in ECX specifies a reserved       
|    | or unimplemented MSR address. If the           
|    | value in EDX:EAX sets bits that are            
|    | reserved in the MSR specified by ECX.          
|    | If the source register contains a non-canonical
|    | address and ECX specifies one of the           
|    | following MSRs: IA32_DS_AREA, IA32_FS_BASE,    
|    | IA32_GS_BASE, IA32_KERNEL_GS_BASE, IA32_LSTAR, 
|    | IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.          
| #UD| If the LOCK prefix is used.                    

Virtual-8086 Mode Exceptions:
| #GP(0)| The WRMSR instruction is not recognized
|       | in virtual-8086 mode.                  

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: XACQUIRE
description:
XACQUIRE/XRELEASE  -  Hardware Lock Elision Prefix Hints:
| Opcode/Instruction| 64/32bit Mode Support| CPUID Feature Flag| Description                            
| F2 XACQUIRE       | V/V                  | HLE1              | A hint used with an “XACQUIRE-enabled“ 
|                   |                      |                   | instruction to start lock elision on   
|                   |                      |                   | the instruction memory operand address.
| F3 XRELEASE       | V/V                  | HLE               | A hint used with an “XRELEASE-enabled“ 
|                   |                      |                   | instruction to end lock elision on the 
|                   |                      |                   | instruction memory operand address.    
Notes: 1. Software is not required to check the HLE feature flag to use XACQUIRE
or XRELEASE, as they are treated as regular prefix if HLE feature flag reports
0.


Description:
The XACQUIRE prefix is a hint to start lock elision on the memory address specified
by the instruction and the XRELEASE prefix is a hint to end lock elision on
the memory address specified by the instruction. The XACQUIRE prefix hint can
only be used with the following instructions (these instructions are also referred
to as XACQUIRE-enabled when used with the XACQUIRE prefix):

 - Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction
where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR,
BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG.
 - The XCHG instruction either with or without the presence of the LOCK prefix.

The XRELEASE prefix hint can only be used with the following instructions (also
referred to as XRELEASE-enabled when used with the XRELEASE prefix):

 - Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction
where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR,
BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG.
 - The XCHG instruction either with or without the presence of the LOCK prefix.
 - The "MOV mem, reg" (Opcode 88H/89H) and "MOV mem, imm" (Opcode C6H/C7H) instructions.
In these cases, the XRELEASE is recognized without the presence of the LOCK
prefix.

The lock variables must satisfy the guidelines described in Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1, Section 15.3.3, for elision
to be successful, otherwise an HLE abort may be signaled. If an encoded byte
sequence that meets XACQUIRE/XRELEASE requirements includes both prefixes, then
the HLE semantic is determined by the prefix byte that is placed closest to
the instruction opcode. For example, an F3F2C6 will not be treated as a XRELEASE-enabled
instruction since the F2H (XACQUIRE) is closest to the instruction opcode C6.
Similarly, an F2F3F0 prefixed instruction will be treated as a XRELEASE-enabled
instruction since F3H (XRELEASE) is closest to the instruction opcode. Intel
64 and IA-32 Compatibility The effect of the XACQUIRE/XRELEASE prefix hint is
the same in non-64-bit modes and in 64-bit mode.

| For instructions that do not support  | prefix behaves the same way as REPNE/REPNZ
| the XACQUIRE hint, the presence of the| semantics for string instructions,        
| F2H prior hardware, according to •    |                                           
| •                                     | Serve as SIMD prefix for legacy SIMD      
|                                       | instructions operating on XMM register    
| •                                     | Cause #UD if prepending the VEX prefix.   
| •                                     | Undefined for non-string instructions     
|                                       | or other situations.                      
For instructions that do not support the XRELEASE hint, the presence of the
F3H prefix behaves the same way as in prior hardware, according to

 - REP/REPE/REPZ semantics for string instructions,
 - Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
 - Cause #UD if prepending the VEX prefix.
 - Undefined for non-string instructions or other situations.

Operation:

XACQUIRE
IF XACQUIRE-enabled instruction
  THEN
     IF (HLE_NEST_COUNT < MAX_HLE_NEST_COUNT) THEN
       HLE_NEST_COUNT++
       IF (HLE_NEST_COUNT = 1) THEN
          HLE_ACTIVE <- 1
          IF 64-bit mode
             THEN
               restartRIP <- instruction pointer of the XACQUIRE-enabled instruction
             ELSE
               restartEIP <- instruction pointer of the XACQUIRE-enabled instruction
          FI;
          Enter HLE Execution (* record register state, start tracking memory state *)
       FI; (* HLE_NEST_COUNT = 1*)
       IF ElisionBufferAvailable
          THEN
             Allocate elision buffer
             Record address and data for forwarding and commit checking
             Perform elision
          ELSE
             Perform lock acquire operation transactionally but without elision
       FI;
     ELSE (* HLE_NEST_COUNT = MAX_HLE_NEST_COUNT *)
          GOTO HLE_ABORT_PROCESSING
     FI;
  ELSE
     Treat instruction as non-XACQUIRE F2H prefixed legacy instruction
FI;
XRELEASE
IF XRELEASE-enabled instruction
  THEN
     IF (HLE_NEST_COUNT > 0)
       THEN
          HLE_NEST_COUNT--
          IF lock address matches in elision buffer THEN
             IF lock satisfies address and value requirements THEN
               Deallocate elision buffer
             ELSE
               GOTO HLE_ABORT_PROCESSING
             FI;
          FI;
          IF (HLE_NEST_COUNT = 0)
             THEN
               IF NoAllocatedElisionBuffer
                  THEN
                     Try to commit transactional execution
                     IF fail to commit transactional execution
                       THEN
                          GOTO HLE_ABORT_PROCESSING;
                       ELSE (* commit success *)
                          HLE_ACTIVE <- 0
                     FI;
                  ELSE
                     GOTO HLE_ABORT_PROCESSING
               FI;
          FI;
     FI; (* HLE_NEST_COUNT > 0 *)
  ELSE
     Treat instruction as non-XRELEASE F3H prefixed legacy instruction
FI;
(* For any HLE abort condition encountered during HLE execution *)
HLE_ABORT_PROCESSING:
  HLE_ACTIVE <- 0
  HLE_NEST_COUNT <- 0
  Restore architectural register state
  Discard memory updates performed in transaction
  Free any allocated lock elision buffers
  IF 64-bit mode
     THEN
       RIP <- restartRIP
     ELSE
       EIP <- restartEIP
  FI;
  Execute and retire instruction at RIP (or EIP) and ignore any HLE hint
END

SIMD Floating-Point Exceptions:
None


Other Exceptions:
| #GP(0)| If the use of prefix causes instruction
|       | length to exceed 15 bytes.             


platform: x86
mnem: XABORT
description:
XABORT  -  Transactional Abort:
| Opcode/Instruction  | Op/En| 64/32bit Mode Support| CPUID Feature Flag| Description                            
| C6 F8 ib XABORT imm8| A    | V/V                  | RTM               | Causes an RTM abort if in RTM execution

Instruction Operand Encoding:
| Op/En| Operand 1| Operand2| Operand3| Operand4
| A    | imm8     | NA      | NA      | NA      

Description:
XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes
execution at the fallback address computed through the outermost XBEGIN instruction.
The EAX register is updated to reflect an XABORT instruction caused the abort,
and the imm8 argument will be provided in bits 31:24 of EAX.

Operation:

XABORT
IF RTM_ACTIVE = 0
  THEN
     Treat as NOP;
  ELSE
     GOTO RTM_ABORT_PROCESSING;
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
  Restore architectural register state;
  Discard memory updates performed in transaction;
  Update EAX with status and XABORT argument;
  RTM_NEST_COUNT <- 0;
  RTM_ACTIVE <- 0;
  IF 64-bit Mode
     THEN
       RIP <- fallbackRIP;
     ELSE
       EIP <- fallbackEIP;
  FI;
END

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| XABORT:| void _xabort( unsigned int);

SIMD Floating-Point Exceptions:
None


Other Exceptions:
| #UD| CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.
|    | If LOCK prefix is used.              


platform: x86
mnem: XADD
description:
XADD - Exchange and Add:
| Opcode          | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F C0 /r        | XADD r/m8, r8  | MR   | Valid      | Valid          | Exchange r8 and r/m8; load sum into  
|                 |                |      |            |                | r/m8.                                
| REX + 0F C0 /r  | XADD r/m8*, r8*| MR   | Valid      | N.E.           | Exchange r8 and r/m8; load sum into  
|                 |                |      |            |                | r/m8.                                
| 0F C1 /r        | XADD r/m16, r16| MR   | Valid      | Valid          | Exchange r16 and r/m16; load sum into
|                 |                |      |            |                | r/m16.                               
| 0F C1 /r        | XADD r/m32, r32| MR   | Valid      | Valid          | Exchange r32 and r/m32; load sum into
|                 |                |      |            |                | r/m32.                               
| REX.W + 0F C1 /r| XADD r/m64, r64| MR   | Valid      | N.E.           | Exchange r64 and r/m64; load sum into
|                 |                |      |            |                | r/m64.                               
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (r, w)| ModRM:reg (W)| NA       | NA       

Description:
Exchanges the first operand (destination operand) with the second operand (source
operand), then loads the sum of the two values into the destination operand.
The destination operand can be a register or a memory location; the source operand
is a register.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.


IA-32 Architecture Compatibility:
IA-32 processors earlier than the Intel486 processor do not recognize this instruction.
If this instruction is used, you should provide an equivalent code sequence
that runs on earlier processors.

Operation:

TEMP <- SRC + DEST;
SRC <- DEST;
DEST <- TEMP;

Flags Affected:
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the
addition, which is stored in the destination operand.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used but the destination 
|                | is not a memory operand.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: XBEGIN
description:
XBEGIN  -  Transactional Begin:
| Opcode/Instruction| Op/En| 64/32bit Mode Support| CPUID Feature Flag| Description                           
| C7 F8 XBEGIN rel16| A    | V/V                  | RTM               | Specifies the start of an RTM region. 
|                   |      |                      |                   | Provides a 16-bit relative offset to  
|                   |      |                      |                   | compute the address of the fallback   
|                   |      |                      |                   | instruction address at which execution
|                   |      |                      |                   | resumes following an RTM abort.       
| C7 F8 XBEGIN rel32| A    | V/V                  | RTM               | Specifies the start of an RTM region. 
|                   |      |                      |                   | Provides a 32-bit relative offset to  
|                   |      |                      |                   | compute the address of the fallback   
|                   |      |                      |                   | instruction address at which execution
|                   |      |                      |                   | resumes following an RTM abort.       

Instruction Operand Encoding:
| Op/En| Operand 1| Operand2| Operand3| Operand4
| A    | Offset   | NA      | NA      | NA      

Description:
The XBEGIN instruction specifies the start of an RTM code region. If the logical
processor was not already in transactional execution, then the XBEGIN instruction
causes the logical processor to transition into transactional execution. The
XBEGIN instruction that transitions the logical processor into transactional
execution is referred to as the outermost XBEGIN instruction. The instruction
also specifies a relative offset to compute the address of the fallback code
path following a transactional abort. On an RTM abort, the logical processor
discards all architectural register and memory updates performed during the
RTM execution and restores architectural state to that corresponding to the
outermost XBEGIN instruction. The fallback address following an abort is computed
from the outermost XBEGIN instruction.

Operation:

XBEGIN
IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT
  THEN
     RTM_NEST_COUNT++
     IF RTM_NEST_COUNT = 1 THEN
       IF 64-bit Mode
          THEN
               fallbackRIP <- RIP + SignExtend64(IMM)
                       (* RIP is instruction following XBEGIN instruction *)
             ELSE
               fallbackEIP <- EIP + SignExtend32(IMM)
                       (* EIP is instruction following XBEGIN instruction *)
       FI;
       IF (64-bit mode)
          THEN IF (fallbackRIP is not canonical)
             THEN #GP(0)
          FI;
          ELSE IF (fallbackEIP outside code segment limit)
             THEN #GP(0)
          FI;
       FI;
       RTM_ACTIVE <- 1
       Enter RTM Execution (* record register state, start tracking memory state*)
     FI; (* RTM_NEST_COUNT = 1 *)
  ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT *)
     GOTO RTM_ABORT_PROCESSING
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
  Restore architectural register state
  Discard memory updates performed in transaction
  Update EAX with status
  RTM_NEST_COUNT <- 0
  RTM_ACTIVE <- 0
  IF 64-bit mode
     THEN
       RIP <- fallbackRIP
     ELSE
       EIP <- fallbackEIP
  FI;
END

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| XBEGIN:| unsigned int _xbegin( void );

SIMD Floating-Point Exceptions:
None


Protected Mode Exceptions:
| #UD   | CPUID.(EAX=7, ECX=0):RTM[bit 11]=0.   
|       | If LOCK prefix is used.               
| #GP(0)| If the fallback address is outside the
|       | CS segment.                           

Real-Address Mode Exceptions:
| #GP(0)| If the fallback address is outside the
|       | address space 0000H and FFFFH.        
| #UD   | CPUID.(EAX=7, ECX=0):RTM[bit 11]=0.   
|       | If LOCK prefix is used.               

Virtual-8086 Mode Exceptions:
| #GP(0)| If the fallback address is outside the
|       | address space 0000H and FFFFH.        
| #UD   | CPUID.(EAX=7, ECX=0):RTM[bit 11]=0.   
|       | If LOCK prefix is used.               

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-bit Mode Exceptions:
| #UD   | CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.    
|       | If LOCK prefix is used.                  
| #GP(0)| If the fallback address is non-canonical.


platform: x86
mnem: XCHG
description:
XCHG - Exchange Register/Memory with Register:
| Opcode       | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 90+rw        | XCHG AX, r16   | O    | Valid      | Valid          | Exchange r16 with AX.                   
| 90+rw        | XCHG r16, AX   | O    | Valid      | Valid          | Exchange AX with r16.                   
| 90+rd        | XCHG EAX, r32  | O    | Valid      | Valid          | Exchange r32 with EAX.                  
| REX.W + 90+rd| XCHG RAX, r64  | O    | Valid      | N.E.           | Exchange r64 with RAX.                  
| 90+rd        | XCHG r32, EAX  | O    | Valid      | Valid          | Exchange EAX with r32.                  
| REX.W + 90+rd| XCHG r64, RAX  | O    | Valid      | N.E.           | Exchange RAX with r64.                  
| 86 /r        | XCHG r/m8, r8  | MR   | Valid      | Valid          | Exchange r8 (byte register) with byte   
|              |                |      |            |                | from r/m8.                              
| REX + 86 /r  | XCHG r/m8*, r8*| MR   | Valid      | N.E.           | Exchange r8 (byte register) with byte   
|              |                |      |            |                | from r/m8.                              
| 86 /r        | XCHG r8, r/m8  | RM   | Valid      | Valid          | Exchange byte from r/m8 with r8 (byte   
|              |                |      |            |                | register).                              
| REX + 86 /r  | XCHG r8*, r/m8*| RM   | Valid      | N.E.           | Exchange byte from r/m8 with r8 (byte   
|              |                |      |            |                | register).                              
| 87 /r        | XCHG r/m16, r16| MR   | Valid      | Valid          | Exchange r16 with word from r/m16.      
| 87 /r        | XCHG r16, r/m16| RM   | Valid      | Valid          | Exchange word from r/m16 with r16.      
| 87 /r        | XCHG r/m32, r32| MR   | Valid      | Valid          | Exchange r32 with doubleword from r/m32.
| REX.W + 87 /r| XCHG r/m64, r64| MR   | Valid      | N.E.           | Exchange r64 with quadword from r/m64.  
| 87 /r        | XCHG r32, r/m32| RM   | Valid      | Valid          | Exchange doubleword from r/m32 with     
|              |                |      |            |                | r32.                                    
| REX.W + 87 /r| XCHG r64, r/m64| RM   | Valid      | N.E.           | Exchange quadword from r/m64 with r64.  
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1         | Operand 2         | Operand 3| Operand 4
| O    | AX/EAX/RAX (r, w) | opcode + rd (r, w)| NA       | NA       
| O    | opcode + rd (r, w)| AX/EAX/RAX (r, w) | NA       | NA       
| MR   | ModRM:r/m (r, w)  | ModRM:reg (r)     | NA       | NA       
| RM   | ModRM:reg (w)     | ModRM:r/m (r)     | NA       | NA       

Description:
Exchanges the contents of the destination (first) and source (second) operands.
The operands can be two generalpurpose registers or a register and a memory
location. If a memory operand is referenced, the processor's locking protocol
is automatically implemented for the duration of the exchange operation, regardless
of the presence or absence of the LOCK prefix or of the value of the IOPL. (See
the LOCK prefix description in this chapter for more information on the locking
protocol.)

This instruction is useful for implementing semaphores or similar data structures
for process synchronization. (See “Bus Locking” in Chapter 8 of the Intel® 64
and IA-32 Architectures Software Developer's Manual, Volume 3A, for more information
on bus locking.)

The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit
operands.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

TEMP <- DEST;
DEST <- SRC;
SRC <- TEMP;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If either operand is in a non-writable        
|                | segment. If a memory operand effective        
|                | address is outside the CS, DS, ES, FS,        
|                | or GS segment limit. If the DS, ES,           
|                | FS, or GS register contains a NULL segment    
|                | selector.                                     
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: XEND
description:
XEND  -  Transactional End:
| Opcode/Instruction| Op/En| 64/32bit Mode Support| CPUID Feature Flag| Description                             
| 0F 01 D5 XEND     | A    | V/V                  | RTM               | Specifies the end of an RTM code region.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand2| Operand3| Operand4
| A    | NA       | NA      | NA      | NA      

Description:
The instruction marks the end of an RTM code region. If this corresponds to
the outermost scope (that is, including this XEND instruction, the number of
XBEGIN instructions is the same as number of XEND instructions), the logical
processor will attempt to commit the logical processor state atomically. If
the commit fails, the logical processor will rollback all architectural register
and memory updates performed during the RTM execution. The logical processor
will resume execution at the fallback address computed from the outermost XBEGIN
instruction. The EAX register is updated to reflect RTM abort information. XEND
executed outside a transactional region will cause a #GP (General Protection
Fault).

Operation:

XEND
IF (RTM_ACTIVE = 0) THEN
  SIGNAL #GP
ELSE
  RTM_NEST_COUNT--
  IF (RTM_NEST_COUNT = 0) THEN
     Try to commit transaction
     IF fail to commit transactional execution
       THEN
          GOTO RTM_ABORT_PROCESSING;
       ELSE (* commit success *)
          RTM_ACTIVE <- 0
     FI;
  FI;
FI;
(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
  Restore architectural register state
  Discard memory updates performed in transaction
  Update EAX with status
  RTM_NEST_COUNT <- 0
  RTM_ACTIVE <- 0
  IF 64-bit Mode
     THEN
       RIP <- fallbackRIP
     ELSE
       EIP <- fallbackEIP
  FI;
END

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| XEND:| void _xend( void );

SIMD Floating-Point Exceptions:
None


Other Exceptions:
| #UD   | CPUID.(EAX=7, ECX=0):RTM[bit 11] = 0.
|       | If LOCK or 66H or F2H or F3H prefix  
|       | is used.                             
| #GP(0)| If RTM_ACTIVE = 0.                   


platform: x86
mnem: XGETBV
description:
XGETBV - Get Value of Extended Control Register:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                
| 0F 01 D0| XGETBV     | NP   | Valid      | Valid          | Reads an XCR specified by ECX into EDX:EAX.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Reads the contents of the extended control register (XCR) specified in the ECX
register into registers EDX:EAX. (On processors that support the Intel 64 architecture,
the high-order 32 bits of RCX are ignored.) The EDX register is loaded with
the high-order 32 bits of the XCR and the EAX register is loaded with the low-order
32 bits. (On processors that support the Intel 64 architecture, the high-order
32 bits of each of RAX and RDX are cleared.) If fewer than 64 bits are implemented
in the XCR being read, the values returned to EDX:EAX in unimplemented bit locations
are undefined.

XCR0 is supported on any processor that supports the XGETBV instruction. If
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns
in EDX:EAX the logicalAND of XCR0 and the current value of the XINUSE state-component
bitmap. This allows software to discover the state of the init optimization
used by XSAVEOPT and XSAVES. See Chapter 13, “Managing State Using the XSAVE
Feature Set‚” in Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1.

Use of any other value for ECX results in a general-protection (#GP) exception.

Operation:

EDX:EAX <- XCR[ECX];

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XGETBV:| unsigned __int64 _xgetbv( unsigned int);

Protected Mode Exceptions:
| #GP(0)| If an invalid XCR is specified in ECX                 
|       | (includes ECX = 1 if CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit
|       | 2] = 0).                                              
| #UD   | If CPUID.01H:ECX.XSAVE[bit 26] = 0.                   
|       | If CR4.OSXSAVE[bit 18] = 0. If the LOCK               
|       | prefix is used. If 66H, F3H or F2H prefix             
|       | is used.                                              

Real-Address Mode Exceptions:
| #GP(0)| If an invalid XCR is specified in ECX                 
|       | (includes ECX = 1 if CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit
|       | 2] = 0).                                              
| #UD   | If CPUID.01H:ECX.XSAVE[bit 26] = 0.                   
|       | If CR4.OSXSAVE[bit 18] = 0. If the LOCK               
|       | prefix is used. If 66H, F3H or F2H prefix             
|       | is used.                                              

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: XLAT
description:
XLAT/XLATB - Table Look-up Translation:
| Opcode    | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| D7        | XLAT m8    | NP   | Valid      | Valid          | Set AL to memory byte DS:[(E)BX + unsigned
|           |            |      |            |                | AL].                                      
| D7        | XLATB      | NP   | Valid      | Valid          | Set AL to memory byte DS:[(E)BX + unsigned
|           |            |      |            |                | AL].                                      
| REX.W + D7| XLATB      | NP   | Valid      | N.E.           | Set AL to memory byte [RBX + unsigned     
|           |            |      |            |                | AL].                                      

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Locates a byte entry in a table in memory, using the contents of the AL register
as a table index, then copies the contents of the table entry back into the
AL register. The index in the AL register is treated as an unsigned integer.
The XLAT and XLATB instructions get the base address of the table in memory
from either the DS:EBX or the DS:BX registers (depending on the address-size
attribute of the instruction, 32 or 16, respectively). (The DS segment may be
overridden with a segment override prefix.)

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operand”
form and the “nooperand” form. The explicit-operand form (specified with the
XLAT mnemonic) allows the base address of the table to be specified explicitly
with a symbol. This explicit-operands form is provided to allow documentation;
however, note that the documentation provided by this form can be misleading.
That is, the symbol does not have to specify the correct base address. The base
address is always specified by the DS:(E)BX registers, which must be loaded
correctly before the XLAT instruction is executed.

The no-operands form (XLATB) provides a “short form” of the XLAT instructions.
Here also the processor assumes that the DS:(E)BX registers contain the base
address of the table.

In 64-bit mode, operation is similar to that in legacy or compatibility mode.
AL is used to specify the table index (the operand size is fixed at 8 bits).
RBX, however, is used to specify the table's base address. See the summary chart
at the beginning of this section for encoding data and limits.

Operation:

IF AddressSize = 16
  THEN
     AL <- (DS:BX + ZeroExtend(AL));
  ELSE IF (AddressSize = 32)
     AL <- (DS:EBX + ZeroExtend(AL)); FI;
  ELSE (AddressSize = 64)
     AL <- (RBX + ZeroExtend(AL));
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit.                       
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #UD            | If the LOCK prefix is used.          

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: XOR
description:
XOR - Logical Exclusive OR:
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                     
| 34 ib           | XOR AL, imm8    | I    | Valid      | Valid          | AL XOR imm8.                    
| 35 iw           | XOR AX, imm16   | I    | Valid      | Valid          | AX XOR imm16.                   
| 35 id           | XOR EAX, imm32  | I    | Valid      | Valid          | EAX XOR imm32.                  
| REX.W + 35 id   | XOR RAX, imm32  | I    | Valid      | N.E.           | RAX XOR imm32 (sign-extended).  
| 80 /6 ib        | XOR r/m8, imm8  | MI   | Valid      | Valid          | r/m8 XOR imm8.                  
| REX + 80 /6 ib  | XOR r/m8*, imm8 | MI   | Valid      | N.E.           | r/m8 XOR imm8.                  
| 81 /6 iw        | XOR r/m16, imm16| MI   | Valid      | Valid          | r/m16 XOR imm16.                
| 81 /6 id        | XOR r/m32, imm32| MI   | Valid      | Valid          | r/m32 XOR imm32.                
| REX.W + 81 /6 id| XOR r/m64, imm32| MI   | Valid      | N.E.           | r/m64 XOR imm32 (sign-extended).
| 83 /6 ib        | XOR r/m16, imm8 | MI   | Valid      | Valid          | r/m16 XOR imm8 (sign-extended). 
| 83 /6 ib        | XOR r/m32, imm8 | MI   | Valid      | Valid          | r/m32 XOR imm8 (sign-extended). 
| REX.W + 83 /6 ib| XOR r/m64, imm8 | MI   | Valid      | N.E.           | r/m64 XOR imm8 (sign-extended). 
| 30 /r           | XOR r/m8, r8    | MR   | Valid      | Valid          | r/m8 XOR r8.                    
| REX + 30 /r     | XOR r/m8*, r8*  | MR   | Valid      | N.E.           | r/m8 XOR r8.                    
| 31 /r           | XOR r/m16, r16  | MR   | Valid      | Valid          | r/m16 XOR r16.                  
| 31 /r           | XOR r/m32, r32  | MR   | Valid      | Valid          | r/m32 XOR r32.                  
| REX.W + 31 /r   | XOR r/m64, r64  | MR   | Valid      | N.E.           | r/m64 XOR r64.                  
| 32 /r           | XOR r8, r/m8    | RM   | Valid      | Valid          | r8 XOR r/m8.                    
| REX + 32 /r     | XOR r8*, r/m8*  | RM   | Valid      | N.E.           | r8 XOR r/m8.                    
| 33 /r           | XOR r16, r/m16  | RM   | Valid      | Valid          | r16 XOR r/m16.                  
| 33 /r           | XOR r32, r/m32  | RM   | Valid      | Valid          | r32 XOR r/m32.                  
| REX.W + 33 /r   | XOR r64, r/m64  | RM   | Valid      | N.E.           | r64 XOR r/m64.                  
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| I    | AL/AX/EAX/RAX   | imm8/16/32   | NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8/16/32   | NA       | NA       
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and
source (second) operands and stores the result in the destination operand location.
The source operand can be an immediate, a register, or a memory location; the
destination operand can be a register or a memory location. (However, two memory
operands cannot be used in one instruction.) Each bit of the result is 1 if
the corresponding bits of the operands are different; each bit is 0 if the corresponding
bits are the same.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation
to 64 bits. See the summary chart at the beginning of this section for encoding
data and limits.

Operation:

DEST <- DEST XOR SRC;

Flags Affected:
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according
to the result. The state of the AF flag is undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: XORPD
description:
XORPD - Bitwise Logical XOR for Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 66 0F 57 /r XORPD xmm1, xmm2/m128            | RM   | V/V                   | SSE2              | Bitwise exclusive-OR of xmm2/m128 and   
|                                              |      |                       |                   | xmm1.                                   
| VEX.NDS.128.66.0F.WIG 57 /r VXORPD xmm1,xmm2,| RVM  | V/V                   | AVX               | Return the bitwise logical XOR of packed
| xmm3/m128                                    |      |                       |                   | double-precision floating-point values  
|                                              |      |                       |                   | in xmm2 and xmm3/mem.                   
| VEX.NDS.256.66.0F.WIG 57 /r VXORPD ymm1,     | RVM  | V/V                   | AVX               | Return the bitwise logical XOR of packed
| ymm2, ymm3/m256                              |      |                       |                   | double-precision floating-point values  
|                                              |      |                       |                   | in ymm2 and ymm3/mem.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical exclusive-OR of the two packed double-precision floating-point
values from the source operand (second operand) and the destination operand
(first operand), and stores the result in the destination operand. The source
operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register.

Operation:

XORPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] BITWISE XOR SRC[63:0]
DEST[127:64] <- DEST[127:64] BITWISE XOR SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VXORPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VXORPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[191:128] <- SRC1[191:128] BITWISE XOR SRC2[191:128]
DEST[255:192] <- SRC1[255:192] BITWISE XOR SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| XORPD: | __m128d _mm_xor_pd(__m128d a, __m128d    
|        | b)                                       
| VXORPD:| __m256d _mm256_xor_pd (__m256d a, __m256d
|        | b);                                      

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: XORPS
description:
XORPS - Bitwise Logical XOR for Single-Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 57 /r XORPS xmm1, xmm2/m128            | RM   | V/V                   | SSE               | Bitwise exclusive-OR of xmm2/m128 and   
|                                           |      |                       |                   | xmm1.                                   
| VEX.NDS.128.0F.WIG 57 /r VXORPS xmm1,xmm2,| RVM  | V/V                   | AVX               | Return the bitwise logical XOR of packed
| xmm3/m128                                 |      |                       |                   | singleprecision floating-point values   
|                                           |      |                       |                   | in xmm2 and xmm3/mem.                   
| VEX.NDS.256.0F.WIG 57 /r VXORPS ymm1,     | RVM  | V/V                   | AVX               | Return the bitwise logical XOR of packed
| ymm2, ymm3/m256                           |      |                       |                   | singleprecision floating-point values   
|                                           |      |                       |                   | in ymm2 and ymm3/mem.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical exclusive-OR of the four packed single-precision
floating-point values from the source operand (second operand) and the destination
operand (first operand), and stores the result in the destination operand. The
source operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register.

Operation:

XORPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VXORPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VXORPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[159:128] <- SRC1[159:128] BITWISE XOR SRC2[159:128]
DEST[191:160]<- SRC1[191:160] BITWISE XOR SRC2[191:160]
DEST[223:192] <- SRC1[223:192] BITWISE XOR SRC2[223:192]
DEST[255:224] <- SRC1[255:224] BITWISE XOR SRC2[255:224].

Intel C/C++ Compiler Intrinsic Equivalent:
| XORPS: | __m128 _mm_xor_ps(__m128 a, __m128 b) 
| VXORPS:| __m256 _mm256_xor_ps (__m256 a, __m256
|        | b);                                   

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: XRSTOR
description:
XRSTOR - Restore Processor Extended States:
| Opcode         | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F AE /5       | XRSTOR mem  | M    | Valid      | Valid          | Restore state components specified by
|                |             |      |            |                | EDX:EAX from mem.                    
| REX.W+ 0F AE /5| XRSTOR64 mem| M    | Valid      | N.E.           | Restore state components specified by
|                |             |      |            |                | EDX:EAX from mem.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Performs a full or partial restore of processor state components from the XSAVE
area located at the memory address specified by the source operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components restored correspond to the bits set in the requested-feature bitmap
(RFBM), which is the logical-AND of EDX:EAX and XCR0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.7, “Operation of XRSTOR,” of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 provides a detailed description of the operation
of the XRSTOR instruction. The following items provide a highlevel outline:

 - Execution of XRSTOR may take one of two forms: standard and compacted. Bit 63
of the XCOMP_BV field in the XSAVE header determines which form is used: value
0 specifies the standard form, while value 1 specifies the compacted form.
 - If RFBM[i] = 0, XRSTOR does not update state component i.1
 - If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header,
XRSTOR initializes state component i.
 - If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTOR loads state component i from the
XSAVE area.
 - The standard form of XRSTOR treats MXCSR (which is part of state component 1
 -  SSE) differently from the XMM registers. If either form attempts to load MXCSR
with an illegal value, a general-protection exception (#GP) occurs.
 - XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a
subsequent execution of XSAVEOPT or XSAVES.
 - Immediately following an execution of XRSTOR, the processor tracks as in-use
(not in initial configuration) any state component i for which RFBM[i] = 1 and
XSTATE_BV[i] = 1; it tracks as modified any state component i for which RFBM[i]
= 0.

Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit
modes) results in a general-protection (#GP) exception. In 64-bit mode, the
upper 32 bits of RDX and RAX are ignored.

Operation:

RFBM <- XCR0 AND EDX:EAX;
COMPMASK <- XCOMP_BV field from XSAVE header;
RSTORMASK <- XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
  THEN VMXNR <- 1;
1.
  even though MXCSR is part of state component 1  -  SSE. The compacted form of XRSTOR does not make this exception.
  ELSE VMXNR <- 0;
FI;
LAXA <- linear address of XSAVE area;
IF COMPMASK[63] = 0
  THEN
     /* Standard form of XRSTOR */
     If RFBM[0] = 1
       THEN
          IF RSTORMASK[0] = 1
             THEN load x87 state from legacy region of XSAVE area;
             ELSE initialize x87 state;
          FI;
     FI;
     If RFBM[1] = 1
       THEN
          IF RSTORMASK[1] = 1
             THEN load XMM registers from legacy region of XSAVE area;
             ELSE set all XMM registers to 0;
          FI;
     FI;
     If RFBM[2] = 1
       THEN
          IF RSTORMASK[2] = 1
             THEN load AVX state from extended region (standard format) of XSAVE area;
             ELSE initialize AVX state;
          FI;
     FI;
     If RFBM[1] = 1 or RFBM[2] = 1
       THEN load MXCSR from legacy region of XSAVE area;
     FI;
FI;
  ELSE
     /* Compacted form of XRSTOR */
     IF CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0
       THEN
          #GP(0);
     FI;
     If RFBM[0] = 1
       THEN
          IF RSTORMASK[0] = 1
             THEN load x87 state from legacy region of XSAVE area;
             ELSE initialize x87 state;
          FI;
     FI;
     If RFBM[1] = 1
       THEN
          IF RSTORMASK[1] = 1
             THEN load SSE state from legacy region of XSAVE area;
             ELSE initialize SSE state;
          FI;
     FI;
     If RFBM[2] = 1
       THEN
          IF RSTORMASK[2] = 1
             THEN load AVX state from extended region (compacted format) of XSAVE area;
             ELSE initialize AVX state;
          FI;
     FI;
FI;
XRSTOR_INFO <- CPL,VMXNR,LAXA,COMPMASK;

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XRSTOR:| void _xrstor( void * , unsigned __int64);  
| XRSTOR:| void _xrstor64( void * , unsigned __int64);

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address                                  
|                | is outside the CS, DS, ES, FS, or GS                                   
|                | segment limit. If a memory operand is                                  
|                | not aligned on a 64-byte boundary, regardless                          
|                | of segment. If bit 63 of the XCOMP_BV                                  
|                | field of the XSAVE header is 1 and CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit
|                | 1] = 0. If the standard form is executed                               
|                | and a bit in XCR0 is 0 and the corresponding                           
|                | bit in the XSTATE_BV field of the XSAVE                                
|                | header is 1. If the standard form is                                   
|                | executed and bytes 23:8 of the XSAVE                                   
|                | header are not all zero. If the compacted                              
|                | form is executed and a bit in XCR0 is                                  
|                | 0 and the corresponding bit in the XCOMP_BV                            
|                | field of the XSAVE header is 1. If the                                 
|                | compacted form is executed and a bit                                   
|                | in the XCOMP_BV field in the XSAVE header                              
|                | is 0 and the corresponding bit in the                                  
|                | XSTATE_BV field is 1. If the compacted                                 
|                | form is executed and bytes 63:16 of                                    
|                | the XSAVE header are not all zero. If                                  
|                | attempting to write any reserved bits                                  
|                | of the MXCSR register with 1.                                          
| #SS(0)         | If a memory operand effective address                                  
|                | is outside the SS segment limit.                                       
| #PF(fault-code)| If a page fault occurs.                                                
| #NM            | If CR0.TS[bit 3] = 1.                                                  
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0.                                    
|                | If CR4.OSXSAVE[bit 18] = 0. If any of                                  
|                | the LOCK, 66H, F3H or F2H prefixes is                                  
|                | used.                                                                  
| #AC            | If this exception is disabled a general                                
|                | protection exception (#GP) is signaled                                 
|                | if the memory operand is not aligned                                   
|                | on a 16-byte boundary, as described                                    
|                | above. If the alignment check exception                                
|                | (#AC) is enabled (and the CPL is 3),                                   
|                | signaling of #AC is not guaranteed and                                 
|                | may vary with implementation, as follows.                              
|                | In all implementations where #AC is                                    
|                | not signaled, a general protection exception                           
|                | is signaled in its place. In addition,                                 
|                | the width of the alignment check may                                   
|                | also vary with implementation. For instance,                           
|                | for a given implementation, an alignment                               
|                | check exception might be signaled for                                  
|                | a 2-byte misalignment, whereas a general                               
|                | protection exception might be signaled                                 
|                | for all other misalignments (4-, 8-,                                   
|                | or 16-byte misalignments).                                             

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on                            
|    | a 64-byte boundary, regardless of segment.                       
|    | If any part of the operand lies outside                          
|    | the effective address space from 0 to                            
|    | FFFFH. If bit 63 of the XCOMP_BV field                           
|    | of the XSAVE header is 1 and CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit
|    | 1] = 0.                                                          
If the standard form is executed and a bit in XCR0 is 0 and the corresponding
bit in the XSTATE_BV field of the XSAVE header is 1. If the standard form is
executed and bytes 23:8 of the XSAVE header are not all zero. If the compacted
form is executed and a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV
field of the XSAVE header is 1. If the compacted form is executed and a bit
in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in
the XSTATE_BV field is 1. If the compacted form is executed and bytes 63:16
of the XSAVE header are not all zero. If attempting to write any reserved bits
of the MXCSR register with 1.

| #NM| If CR0.TS[bit 3] = 1.                
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0.  
|    | If CR4.OSXSAVE[bit 18] = 0. If any of
|    | the LOCK, 66H, F3H or F2H prefixes is
|    | used.                                

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If a memory address is in a non-canonical                        
|                | form. If a memory operand is not aligned                         
|                | on a 64-byte boundary, regardless of                             
|                | segment. If bit 63 of the XCOMP_BV field                         
|                | of the XSAVE header is 1 and CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit
|                | 1] = 0. If the standard form is executed                         
|                | and a bit in XCR0 is 0 and the corresponding                     
|                | bit in the XSTATE_BV field of the XSAVE                          
|                | header is 1. If the standard form is                             
|                | executed and bytes 23:8 of the XSAVE                             
|                | header are not all zero. If the compacted                        
|                | form is executed and a bit in XCR0 is                            
|                | 0 and the corresponding bit in the XCOMP_BV                      
|                | field of the XSAVE header is 1. If the                           
|                | compacted form is executed and a bit                             
|                | in the XCOMP_BV field in the XSAVE header                        
|                | is 0 and the corresponding bit in the                            
|                | XSTATE_BV field is 1. If the compacted                           
|                | form is executed and bytes 63:16 of                              
|                | the XSAVE header are not all zero. If                            
|                | attempting to write any reserved bits                            
|                | of the MXCSR register with 1.                                    
| #SS(0)         | If a memory address referencing the                              
|                | SS segment is in a non-canonical form.                           
| #PF(fault-code)| If a page fault occurs.                                          
| #NM            | If CR0.TS[bit 3] = 1.                                            
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0.                              
|                | If CR4.OSXSAVE[bit 18] = 0. If any of                            
|                | the LOCK, 66H, F3H or F2H prefixes is                            
|                | used.                                                            
| #AC            | If this exception is disabled a general                          
|                | protection exception (#GP) is signaled                           
|                | if the memory operand is not aligned                             
|                | on a 16-byte boundary, as described                              
|                | above. If the alignment check exception                          
|                | (#AC) is enabled (and the CPL is 3),                             
|                | signaling of #AC is not guaranteed and                           
|                | may vary with implementation, as follows.                        
|                | In all implementations where #AC is                              
|                | not signaled, a general protection exception                     
|                | is signaled in its place. In addition,                           
|                | the width of the alignment check may                             
|                | also vary with implementation. For instance,                     
|                | for a given implementation, an alignment                         
|                | check exception might be signaled for                            
|                | a 2-byte misalignment, whereas a general                         
|                | protection exception might be signaled                           
|                | for all other misalignments (4-, 8-,                             
|                | or 16-byte misalignments).                                       


platform: x86
mnem: XRSTORS
description:
XRSTORS - Restore Processor Extended States Supervisor:
| Opcode         | Instruction  | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F C7 /3       | XRSTORS mem  | M    | Valid      | Valid          | Restore state components specified by
|                |              |      |            |                | EDX:EAX from mem.                    
| REX.W+ 0F C7 /3| XRSTORS64 mem| M    | Valid      | N.E.           | Restore state components specified by
|                |              |      |            |                | EDX:EAX from mem.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Performs a full or partial restore of processor state components from the XSAVE
area located at the memory address specified by the source operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components restored correspond to the bits set in the requested-feature bitmap
(RFBM), which is the logical-AND of EDX:EAX and the logical-OR of XCR0 with
the IA32_XSS MSR. XRSTORS may be executed only if CPL = 0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.11, “Operation of XRSTORS,” of Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1 provides a detailed description of the
operation of the XRSTOR instruction. The following items provide a high-level
outline:

 - Execution of XRSTORS is similar to that of the compacted form of XRSTOR; XRSTORS
cannot restore from an XSAVE area in which the extended region is in the standard
format (see Section 13.4.3, “Extended Region of an XSAVE Area”).
 - XRSTORS differs from XRSTOR in that it can restore state components corresponding
to bits set in the IA32_XSS MSR.
 - If RFBM[i] = 0, XRSTORS does not update state component i.
 - If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header,
XRSTORS initializes state component i.
 - If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTORS loads state component i from the
XSAVE area.
 - If XRSTORS attempts to load MXCSR with an illegal value, a general-protection
exception (#GP) occurs.
 - XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize
a subsequent execution of XSAVEOPT or XSAVES.
 - Immediately following an execution of XRSTORS, the processor tracks as in-use
(not in initial configuration) any state component i for which RFBM[i] = 1 and
XSTATE_BV[i] = 1; it tracks as modified any state component i for which RFBM[i]
= 0.

Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit
modes) results in a general-protection (#GP) exception. In 64-bit mode, the
upper 32 bits of RDX and RAX are ignored.

Operation:

RFBM <- (XCR0 OR IA32_XSS) AND EDX:EAX;
COMPMASK <- XCOMP_BV field from XSAVE header;
RSTORMASK <- XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
  THEN VMXNR <- 1;
  ELSE VMXNR <- 0;
FI;
LAXA <- linear address of XSAVE area;
If RFBM[0] = 1
  THEN
     IF RSTORMASK[0] = 1
       THEN load x87 state from legacy region of XSAVE area;
       ELSE initialize x87 state;
     FI;
FI;
If RFBM[1] = 1
  THEN
     IF RSTORMASK[1] = 1
       THEN load SSE state from legacy region of XSAVE area;
       ELSE initialize SSE state;
     FI;
FI;
If RFBM[2] = 1
  THEN
     IF RSTORMASK[2] = 1
       THEN load AVX state from extended region (compacted format) of XSAVE area;
       ELSE initialize AVX state;
     FI;
FI;
XRSTOR_INFO <- CPL,VMXNR,LAXA,COMPMASK;

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XRSTORS: XRSTORS64: void _xrstors64(| void _xrstors( void * , unsigned __int64);
| void * , unsigned __int64);         |                                           

Protected Mode Exceptions:
| #GP(0)         | If CPL > 0. If a memory operand effective
|                | address is outside the CS, DS, ES, FS,   
|                | or GS segment limit. If a memory operand 
|                | is not aligned on a 64-byte boundary,    
|                | regardless of segment. If bit 63 of      
|                | the XCOMP_BV field of the XSAVE header   
|                | is 0. If a bit in XCR0 is 0 and the      
|                | corresponding bit in the XCOMP_BV field  
|                | of the XSAVE header is 1. If a bit in    
|                | the XCOMP_BV field in the XSAVE header   
|                | is 0 and the corresponding bit in the    
|                | XSTATE_BV field is 1. If bytes 63:16     
|                | of the XSAVE header are not all zero.    
|                | If attempting to write any reserved      
|                | bits of the MXCSR register with 1.       
| #SS(0)         | If a memory operand effective address    
|                | is outside the SS segment limit.         
| #PF(fault-code)| If a page fault occurs.                  
| #NM            | If CR0.TS[bit 3] = 1.                    
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or    
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]     
|                | = 0. If CR4.OSXSAVE[bit 18] = 0. If      
|                | any of the LOCK, 66H, F3H or F2H prefixes
|                | is used.                                 
| #AC            | If this exception is disabled a general  
|                | protection exception (#GP) is signaled   
|                | if the memory operand is not aligned     
|                | on a 16-byte boundary, as described      
|                | above. If the alignment check            
exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed
and may vary with implementation, as follows. In all implementations where #AC
is not signaled, a #GP is signaled in its place. In addition, the width of the
alignment check may also vary with implementation. For instance, for a given
implementation, an alignment check exception might be signaled for a 2-byte
misalignment, whereas a #GP might be signaled for all other misalignments (4-,
8-, or 16-byte misalignments).


Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on         
|    | a 64-byte boundary, regardless of segment.    
|    | If any part of the operand lies outside       
|    | the effective address space from 0 to         
|    | FFFFH. If bit 63 of the XCOMP_BV field        
|    | of the XSAVE header is 0. If a bit in         
|    | XCR0 is 0 and the corresponding bit           
|    | in the XCOMP_BV field of the XSAVE header     
|    | is 1. If a bit in the XCOMP_BV field          
|    | in the XSAVE header is 0 and the corresponding
|    | bit in the XSTATE_BV field is 1. If           
|    | bytes 63:16 of the XSAVE header are           
|    | not all zero. If attempting to write          
|    | any reserved bits of the MXCSR register       
|    | with 1.                                       
| #NM| If CR0.TS[bit 3] = 1.                         
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0 or         
|    | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]          
|    | = 0. If CR4.OSXSAVE[bit 18] = 0. If           
|    | any of the LOCK, 66H, F3H or F2H prefixes     
|    | is used.                                      

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If CPL > 0. If a memory address is in       
|                | a non-canonical form. If a memory operand   
|                | is not aligned on a 64-byte boundary,       
|                | regardless of segment. If bit 63 of         
|                | the XCOMP_BV field of the XSAVE header      
|                | is 0. If a bit in XCR0 is 0 and the         
|                | corresponding bit in the XCOMP_BV field     
|                | of the XSAVE header is 1. If a bit in       
|                | the XCOMP_BV field in the XSAVE header      
|                | is 0 and the corresponding bit in the       
|                | XSTATE_BV field is 1. If bytes 63:16        
|                | of the XSAVE header are not all zero.       
|                | If attempting to write any reserved         
|                | bits of the MXCSR register with 1.          
| #SS(0)         | If a memory address referencing the         
|                | SS segment is in a non-canonical form.      
| #PF(fault-code)| If a page fault occurs.                     
| #NM            | If CR0.TS[bit 3] = 1.                       
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or       
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]        
|                | = 0. If CR4.OSXSAVE[bit 18] = 0. If         
|                | any of the LOCK, 66H, F3H or F2H prefixes   
|                | is used.                                    
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protec-                                     
tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
misalignments).


platform: x86
mnem: XSAVE
description:
XSAVE - Save Processor Extended States:
| Opcode         | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| 0F AE /4       | XSAVE mem  | M    | Valid      | Valid          | Save state components specified by EDX:EAX
|                |            |      |            |                | to mem.                                   
| REX.W+ 0F AE /4| XSAVE64 mem| M    | Valid      | N.E.           | Save state components specified by EDX:EAX
|                |            |      |            |                | to mem.                                   

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Performs a full or partial save of processor state components to the XSAVE area
located at the memory address specified by the destination operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components saved correspond to the bits set in the requested-feature bitmap
(RFBM), which is the logical-AND of EDX:EAX and XCR0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.6, “Operation of XSAVE,” of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 provides a detailed description of the operation
of the XSAVE instruction. The following items provide a high-level outline:

 - XSAVE saves state component i if and only if RFBM[i] = 1.1
 - XSAVE does not modify bytes 511:464 of the legacy region of the XSAVE area (see
Section 13.4.1, “Legacy Region of an XSAVE Area”).
 - XSAVE reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, “XSAVE
Header”) and writes a modified value back to memory as follows. If RFBM[i] =
1, XSAVE writes XSTATE_BV[i] with the value of XINUSE[i]. (XINUSE is a bitmap
by which the processor tracks the status of various state components. See Section
13.5.4, “Processor Tracking of XSAVE-Managed State.”) If RFBM[i] = 0, XSAVE
writes XSTATE_BV[i]with the value that it read from memory (it does not modify
the bit). XSAVE does not write to any part of the XSAVE header other than the
XSTATE_BV field.
 - XSAVE always uses the standard format of the extended region of the XSAVE area
(see Section 13.4.3, “Extended Region of an XSAVE Area”).

Use of a destination operand not aligned to 64-byte boundary (in either 64-bit
or 32-bit modes) results in a general-protection (#GP) exception. In 64-bit
mode, the upper 32 bits of RDX and RAX are ignored.

Operation:

RFBM <- XCR0 AND EDX:EAX;
OLD_BV <- XSTATE_BV field from XSAVE header;
IF RFBM[0] = 1
  THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1
  THEN store XMM registers into legacy region of XSAVE area;
FI;
1.
  ory if either RFBM[1] or RFBM[2] is 1.
IF RFBM[2] = 1
  THEN store AVX state into extended region of XSAVE area;
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
  THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header <- (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XSAVE:| void _xsave( void * , unsigned __int64);  
| XSAVE:| void _xsave64( void * , unsigned __int64);

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address        
|                | is outside the CS, DS, ES, FS, or GS         
|                | segment limit. If a memory operand is        
|                | not aligned on a 64-byte boundary, regardless
|                | of segment.                                  
| #SS(0)         | If a memory operand effective address        
|                | is outside the SS segment limit.             
| #PF(fault-code)| If a page fault occurs.                      
| #NM            | If CR0.TS[bit 3] = 1.                        
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0.          
|                | If CR4.OSXSAVE[bit 18] = 0. If any of        
|                | the LOCK, 66H, F3H or F2H prefixes is        
|                | used.                                        
| #AC            | If this exception is disabled a general      
|                | protection exception (#GP) is signaled       
|                | if the memory operand is not aligned         
|                | on a 16-byte boundary, as described          
|                | above. If the alignment check exception      
|                | (#AC) is enabled (and the CPL is 3),         
|                | signaling of #AC is not guaranteed and       
|                | may vary with implementation, as follows.    
|                | In all implementations where #AC is          
|                | not signaled, a general protection exception 
|                | is signaled in its place. In addition,       
|                | the width of the alignment check may         
|                | also vary with implementation. For instance, 
|                | for a given implementation, an alignment     
|                | check exception might be signaled for        
|                | a 2-byte misalignment, whereas a general     
|                | protection exception might be signaled       
|                | for all other misalignments (4-, 8-,         
|                | or 16-byte misalignments).                   

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 64-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #NM| If CR0.TS[bit 3] = 1.                     
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0.       
|    | If CR4.OSXSAVE[bit 18] = 0. If any of     
|    | the LOCK, 66H, F3H or F2H prefixes is     
|    | used.                                     

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical 
|                | form. If a memory operand is not aligned    
|                | on a 64-byte boundary, regardless of        
|                | segment.                                    
| #SS(0)         | If a memory address referencing the         
|                | SS segment is in a non-canonical form.      
| #PF(fault-code)| If a page fault occurs.                     
| #NM            | If CR0.TS[bit 3] = 1.                       
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0.         
|                | If CR4.OSXSAVE[bit 18] = 0. If any of       
|                | the LOCK, 66H, F3H or F2H prefixes is       
|                | used.                                       
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  


platform: x86
mnem: XSAVEC
description:
XSAVEC - Save Processor Extended States with Compaction:
| Opcode         | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| 0F C7 /4       | XSAVEC mem  | M    | Valid      | Valid          | Save state components specified by EDX:EAX
|                |             |      |            |                | to mem with compaction.                   
| REX.W+ 0F C7 /4| XSAVEC64 mem| M    | Valid      | N.E.           | Save state components specified by EDX:EAX
|                |             |      |            |                | to mem with compaction.                   

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Performs a full or partial save of processor state components to the XSAVE area
located at the memory address specified by the destination operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components saved correspond to the bits set in the requested-feature bitmap
(RFBM), which is the logical-AND of EDX:EAX and XCR0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.9, “Operation of XSAVEC,” of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 provides a detailed description of the operation
of the XSAVEC instruction. The following items provide a highlevel outline:

 - Execution of XSAVEC is similar to that of XSAVE. XSAVEC differs from XSAVE in
that it uses compaction and that it may use the init optimization.
 - XSAVEC saves state component i if and only if RFBM[i] = 1 and XINUSE[i] = 1.1
(XINUSE is a bitmap by which the processor tracks the status of various state
components. See Section 13.5.4, “Processor Tracking of XSAVE-Managed State.”)
 - XSAVEC does not modify bytes 511:464 of the legacy region of the XSAVE area
(see Section 13.4.1, “Legacy Region of an XSAVE Area”).
 - XSAVEC writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the
XSAVE header.2,3 (See Section 13.4.2, “XSAVE Header.”) XSAVEC sets bit 63 of
the XCOMP_BV field and sets bits 62:0 of that field to RFBM[62:0]. XSAVEC does
not write to any parts of the XSAVE header other than the XSTATE_BV and XCOMP_BV
fields.
 - XSAVEC always uses the compacted format of the extended region of the XSAVE
area (see Section 13.4.3, “Extended Region of an XSAVE Area”).

Use of a destination operand not aligned to 64-byte boundary (in either 64-bit
or 32-bit modes) results in a general-protection (#GP) exception. In 64-bit
mode, the upper 32 bits of RDX and RAX are ignored.

Operation:

RFBM <- XCR0 AND EDX:EAX;
COMPMASK <- RFBM OR 80000000_00000000H;
IF RFBM[0] = 1 and XINUSE[0] = 1
1.
  have its initial value of 1F80H. In this case, XSAVEC saves SSE state as long as RFBM[1] = 1.
2.
3.
  have its initial value of 1F80H. In this case, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.
  THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR != 1F80H)
  THEN store SSE state into legacy region of XSAVE area;
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
  THEN store AVX state into extended region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header <- XINUSE AND RFBM;
XCOMP_BV field in XSAVE header <- COMPMASK;

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XSAVEC:  | void _xsavec( void * , unsigned __int64);  
| XSAVEC64:| void _xsavec64( void * , unsigned __int64);

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address        
|                | is outside the CS, DS, ES, FS, or GS         
|                | segment limit. If a memory operand is        
|                | not aligned on a 64-byte boundary, regardless
|                | of segment.                                  
| #SS(0)         | If a memory operand effective address        
|                | is outside the SS segment limit.             
| #PF(fault-code)| If a page fault occurs.                      
| #NM            | If CR0.TS[bit 3] = 1.                        
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or        
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit         
|                | 1] = 0. If CR4.OSXSAVE[bit 18] = 0.          
|                | If any of the LOCK, 66H, F3H or F2H          
|                | prefixes is used.                            
| #AC            | If this exception is disabled a general      
|                | protection exception (#GP) is signaled       
|                | if the memory operand is not aligned         
|                | on a 16-byte boundary, as described          
|                | above. If the alignment check exception      
|                | (#AC) is enabled (and the CPL is 3),         
|                | signaling of #AC is not guaranteed and       
|                | may vary with implementation, as follows.    
|                | In all implementations where #AC is          
|                | not signaled, a general protection exception 
|                | is signaled in its place. In addition,       
|                | the width of the alignment check may         
|                | also vary with implementation. For instance, 
|                | for a given implementation, an alignment     
|                | check exception might be signaled for        
|                | a 2-byte misalignment, whereas a general     
|                | protection exception might be signaled       
|                | for all other misalignments (4-, 8-,         
|                | or 16-byte misalignments).                   

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 64-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #NM| If CR0.TS[bit 3] = 1.                     
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0 or     
|    | CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit      
|    | 1] = 0. If CR4.OSXSAVE[bit 18] = 0.       
|    | If any of the LOCK, 66H, F3H or F2H       
|    | prefixes is used.                         

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical 
|                | form. If a memory operand is not aligned    
|                | on a 64-byte boundary, regardless of        
|                | segment.                                    
| #SS(0)         | If a memory address referencing the         
|                | SS segment is in a non-canonical form.      
| #PF(fault-code)| If a page fault occurs.                     
| #NM            | If CR0.TS[bit 3] = 1.                       
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or       
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit        
|                | 1] = 0. If CR4.OSXSAVE[bit 18] = 0.         
|                | If any of the LOCK, 66H, F3H or F2H         
|                | prefixes is used.                           
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  


platform: x86
mnem: XSAVEOPT
description:
XSAVEOPT - Save Processor Extended States Optimized:
| Opcode/Instruction             | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 0F AE /6 XSAVEOPT mem          | M    | V/V                   | XSAVEOPT          | Save state components specified by EDX:EAX
|                                |      |                       |                   | to mem, optimizing if possible.           
| REX.W + 0F AE /6 XSAVEOPT64 mem| M    | V/V                   | XSAVEOPT          | Save state components specified by EDX:EAX
|                                |      |                       |                   | to mem, optimizing if possible.           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Performs a full or partial save of processor state components to the XSAVE area
located at the memory address specified by the destination operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components saved correspond to the bits set in the requested-feature bitmap
(RFBM), which is the logical-AND of EDX:EAX and XCR0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.8, “Operation of XSAVEOPT,” of Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1 provides a detailed description of the
operation of the XSAVEOPT instruction. The following items provide a high-level
outline:

 - Execution of XSAVEOPT is similar to that of XSAVE. XSAVEOPT differs from XSAVE
in that it uses compaction and that it may use the init and modified optimizations.
The performance of XSAVEOPT will be equal to or better than that of XSAVE.
 - XSAVEOPT saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE
is a bitmap by which the processor tracks the status of various state components.
See Section 13.5.4, “Processor Tracking of XSAVEManaged State.”) Even if both
bits are 1, XSAVEOPT may optimize and not save state component i if (1) state
component i has not been modified since the last execution of XRTOR or XRSTORS;
and (2) this execution of XSAVES corresponds to that last execution of XRTOR
or XRSTORS as determined by the internal value XRSTOR_INFO (see the Operation
section below).
 - XSAVEOPT does not modify bytes 511:464 of the legacy region of the XSAVE area
(see Section 13.4.1, “Legacy Region of an XSAVE Area”).
 - XSAVEOPT reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2,
“XSAVE Header”) and writes a modified value back to memory as follows. If RFBM[i]
= 1, XSAVEOPT writes XSTATE_BV[i] with the value of XINUSE[i]. If RFBM[i] =
0, XSAVEOPT writes XSTATE_BV[i] with the value that it read from memory (it
does not modify the bit). XSAVEOPT does not write to any part of the XSAVE header
other than the XSTATE_BV field.
 - XSAVEOPT always uses the standard format of the extended region of the XSAVE
area (see Section 13.4.3, “Extended Region of an XSAVE Area”).

Use of a destination operand not aligned to 64-byte boundary (in either 64-bit
or 32-bit modes) will result in a general-protection (#GP) exception. In 64-bit
mode, the upper 32 bits of RDX and RAX are ignored.

Operation:

RFBM <- XCR0 AND EDX:EAX;
OLD_BV <- XSTATE_BV field from XSAVE header;
1.
  these to memory if RFBM[1] = 1 or RFBM[2] = 1, regardless of the value of XINUSE.
IF in VMX non-root operation
  THEN VMXNR <- 1;
  ELSE VMXNR <- 0;
FI;
LAXA <- linear address of XSAVE area;
COMPMASK <- 00000000_00000000H;
IF XRSTOR_INFO = CPL,VMXNR,LAXA,COMPMASK
  THEN MODOPT <- 1;
  ELSE MODOPT <- 0;
FI;
IF RFBM[0] = 1 and XINUSE[0] = 1
  THEN store x87 state into legacy region of XSAVE area;
  /* might avoid saving if x87 state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 and XINUSE[1]
  THEN store XMM registers into legacy region of XSAVE area;
  /* might avoid saving if XMM registers are not modified and MODOPT = 1 */
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
  THEN store AVX state into extended region of XSAVE area;
  /* might avoid saving if AVX state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
  THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;
FI;
XSTATE_BV field in XSAVE header <- (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XSAVEOPT:| void _xsaveopt( void * , unsigned __int64);
| XSAVEOPT:| void _xsaveopt64( void * , unsigned        
|          | __int64);                                  

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address        
|                | is outside the CS, DS, ES, FS, or GS         
|                | segment limit. If a memory operand is        
|                | not aligned on a 64-byte boundary, regardless
|                | of segment.                                  
| #SS(0)         | If a memory operand effective address        
|                | is outside the SS segment limit.             
| #PF(fault-code)| If a page fault occurs.                      
| #NM            | If CR0.TS[bit 3] = 1.                        
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or        
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSAVEOPT[bit       
|                | 0] =0. If CR4.OSXSAVE[bit 18] = 0. If        
|                | the LOCK prefix is used. If 66H, F3H         
|                | or F2H prefix is used.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 64-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #NM| If CR0.TS[bit 3] = 1.                     
| #UD| 0] =0. If CR4.OSXSAVE[bit 18] = 0. If     
|    | the LOCK prefix is used. If 66H, F3H      
|    | or F2H prefix is used.                    

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form. If a memory operand is not aligned   
|                | on a 64-byte boundary, regardless of       
|                | segment.                                   
| #PF(fault-code)| If a page fault occurs.                    
| #NM            | If CR0.TS[bit 3] = 1.                      
| #UD            | 0] =0. If CR4.OSXSAVE[bit 18] = 0. If      
|                | the LOCK prefix is used. If 66H, F3H       
|                | or F2H prefix is used.                     


platform: x86
mnem: XSAVES
description:
XSAVES - Save Processor Extended States Supervisor:
| Opcode         | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| 0F C7 /5       | XSAVES mem  | M    | Valid      | Valid          | Save state components specified by EDX:EAX
|                |             |      |            |                | to mem with compaction, optimizing if     
|                |             |      |            |                | possible.                                 
| REX.W+ 0F C7 /5| XSAVES64 mem| M    | Valid      | N.E.           | Save state components specified by EDX:EAX
|                |             |      |            |                | to mem with compaction, optimizing if     
|                |             |      |            |                | possible.                                 

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Performs a full or partial save of processor state components to the XSAVE area
located at the memory address specified by the destination operand. The implicit
EDX:EAX register pair specifies a 64-bit instruction mask. The specific state
components saved correspond to the bits set in the requested-feature bitmap
(RFBM), the logicalAND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS
MSR. XSAVES may be executed only if CPL = 0.

The format of the XSAVE area is detailed in Section 13.4, “XSAVE Area,” of Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Section 13.10, “Operation of XSAVES,” of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 provides a detailed description of the operation
of the XSAVES instruction. The following items provide a highlevel outline:

 - Execution of XSAVES is similar to that of XSAVEC. XSAVES differs from XSAVEC
in that it can save state components corresponding to bits set in the IA32_XSS
MSR and that it may use the modified optimization.
 - XSAVES saves state component i only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE
is a bitmap by which the processor tracks the status of various state components.
See Section 13.5.4, “Processor Tracking of XSAVEManaged State.”) Even if both
bits are 1, XSAVES may optimize and not save state component i if (1) state
component i has not been modified since the last execution of XRTOR or XRSTORS;
and (2) this execution of XSAVES correspond to that last execution of XRTOR
or XRSTORS as determined by XRSTOR_INFO (see the Operation section below).
 - XSAVES does not modify bytes 511:464 of the legacy region of the XSAVE area
(see Section 13.4.1, “Legacy Region of an XSAVE Area”).
 - XSAVES writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the
XSAVE header.2 (See Section 13.4.2, “XSAVE Header.”) XSAVES sets bit 63 of the
XCOMP_BV field and sets bits 62:0 of that field to RFBM[62:0]. XSAVES does not
write to any parts of the XSAVE header other than the XSTATE_BV and XCOMP_BV
fields.
 - XSAVES always uses the compacted format of the extended region of the XSAVE
area (see Section 13.4.3, “Extended Region of an XSAVE Area”).

Use of a destination operand not aligned to 64-byte boundary (in either 64-bit
or 32-bit modes) results in a general-protection (#GP) exception. In 64-bit
mode, the upper 32 bits of RDX and RAX are ignored.

| 1.| There is an exception for state component
|   | 1 (SSE). MXCSR is part of SSE state,     
|   | but XINUSE[1] may be 0 even if MXCSR     
|   | does not have its initial value of 1F80H.
|   | In this case, the init optimization      
|   | does not apply and XSAVEC will save      
|   | SSE state as long as RFBM[1] =1 and      
|   | the modified optimization is not being   
|   | applied.                                 
| 2.| There is an exception for state component
|   | 1 (SSE). MXCSR is part of SSE state,     
|   | but XINUSE[1] may be 0 even if MXCSR     
|   | does not have its initial value of 1F80H.
|   | In this case, XSAVES sets XSTATE_BV[1]   
|   | to 1 as long as RFBM[1] = 1.             
Operation:

RFBM <- XCR0 AND EDX:EAX;
IF in VMX non-root operation
  THEN VMXNR <- 1;
  ELSE VMXNR <- 0;
FI;
LAXA <- linear address of XSAVE area;
COMPMASK <- RFBM OR 80000000_00000000H;
IF XRSTOR_INFO = CPL,VMXNR,LAXA,COMPMASK
  THEN MODOPT <- 1;
  ELSE MODOPT <- 0;
FI;
IF RFBM[0] = 1 and XINUSE[0] = 1
  THEN store x87 state into legacy region of XSAVE area;
  /* might avoid saving if x87 state is not modified and MODOPT = 1 */
FI;
IF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR != 1F80H)
  THEN store SSE state into legacy region of XSAVE area;
  /* might avoid saving if SSE state is not modified and MODOPT = 1 */
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
  THEN store AVX state into extended region of XSAVE area;
  /* might avoid saving if AVX state is not modified and MODOPT = 1 */
FI;
XSTATE_BV field in XSAVE header <- XINUSE AND RFBM;
XCOMP_BV field in XSAVE header <- COMPMASK;

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XSAVES:  | void _xsaves( void * , unsigned __int64);  
| XSAVES64:| void _xsaves64( void * , unsigned __int64);

Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address        
|                | is outside the CS, DS, ES, FS, or GS         
|                | segment limit. If a memory operand is        
|                | not aligned on a 64-byte boundary, regardless
|                | of segment.                                  
| #SS(0)         | If a memory operand effective address        
|                | is outside the SS segment limit.             
| #PF(fault-code)| If a page fault occurs.                      
| #NM            | If CR0.TS[bit 3] = 1.                        
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or        
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]         
|                | = 0. If CR4.OSXSAVE[bit 18] = 0. If          
|                | any of the LOCK, 66H, F3H or F2H prefixes    
|                | is used.                                     
| #AC            | If this exception is disabled a general      
|                | protection exception (#GP) is signaled       
|                | if the memory operand is not aligned         
|                | on a 16-byte boundary, as described          
|                | above. If the alignment check exception      
|                | (#AC) is enabled (and the CPL is 3),         
|                | signaling of #AC is not guaranteed and       
|                | may vary with implementation, as follows.    
|                | In all implementations where #AC is          
|                | not signaled, a general protection exception 
|                | is signaled in its place. In addition,       
|                | the width of the alignment check may         
|                | also vary with implementation. For instance, 
|                | for a given implementation, an align-        
ment check exception might be signaled for a 2-byte misalignment, whereas a
general protection exception might be signaled for all other misalignments (4-,
8-, or 16-byte misalignments).


Real-Address Mode Exceptions:
| #GP| If a memory operand is not aligned on     
|    | a 64-byte boundary, regardless of segment.
|    | If any part of the operand lies outside   
|    | the effective address space from 0 to     
|    | FFFFH.                                    
| #NM| If CR0.TS[bit 3] = 1.                     
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0 or     
|    | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]      
|    | = 0. If CR4.OSXSAVE[bit 18] = 0. If       
|    | any of the LOCK, 66H, F3H or F2H prefixes 
|    | is used.                                  

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical 
|                | form. If a memory operand is not aligned    
|                | on a 64-byte boundary, regardless of        
|                | segment.                                    
| #SS(0)         | If a memory address referencing the         
|                | SS segment is in a non-canonical form.      
| #PF(fault-code)| If a page fault occurs.                     
| #NM            | If CR0.TS[bit 3] = 1.                       
| #UD            | If CPUID.01H:ECX.XSAVE[bit 26] = 0 or       
|                | CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3]        
|                | = 0. If CR4.OSXSAVE[bit 18] = 0. If         
|                | any of the LOCK, 66H, F3H or F2H prefixes   
|                | is used.                                    
| #AC            | If this exception is disabled a general     
|                | protection exception (#GP) is signaled      
|                | if the memory operand is not aligned        
|                | on a 16-byte boundary, as described         
|                | above. If the alignment check exception     
|                | (#AC) is enabled (and the CPL is 3),        
|                | signaling of #AC is not guaranteed and      
|                | may vary with implementation, as follows.   
|                | In all implementations where #AC is         
|                | not signaled, a general protection exception
|                | is signaled in its place. In addition,      
|                | the width of the alignment check may        
|                | also vary with implementation. For instance,
|                | for a given implementation, an alignment    
|                | check exception might be signaled for       
|                | a 2-byte misalignment, whereas a general    
|                | protection exception might be signaled      
|                | for all other misalignments (4-, 8-,        
|                | or 16-byte misalignments).                  


platform: x86
mnem: XSETBV
description:
XSETBV - Set Extended Control Register:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 01 D1| XSETBV     | NP   | Valid      | Valid          | Write the value in EDX:EAX to the XCR
|         |            |      |            |                | specified by ECX.                    

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Writes the contents of registers EDX:EAX into the 64-bit extended control register
(XCR) specified in the ECX register. (On processors that support the Intel 64
architecture, the high-order 32 bits of RCX are ignored.) The contents of the
EDX register are copied to high-order 32 bits of the selected XCR and the contents
of the EAX register are copied to low-order 32 bits of the XCR. (On processors
that support the Intel 64 architecture, the highorder 32 bits of each of RAX
and RDX are ignored.) Undefined or reserved bits in an XCR should be set to
values previously read.

This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) is generated. Specifying a
reserved or unimplemented XCR in ECX will also cause a general protection exception.
The processor will also generate a general protection exception if software
attempts to write to reserved bits in an XCR.

Currently, only XCR0 is supported. Thus, all other values of ECX are reserved
and will cause a #GP(0). Note that bit 0 of XCR0 (corresponding to x87 state)
must be set to 1; the instruction will cause a #GP(0) if an attempt is made
to clear this bit. In addition, the instruction causes a #GP(0) if an attempt
is made to set XCR0[2] (AVX state) while clearing XCR0[1] (SSE state); it is
necessary to set both bits to use AVX instructions; Section 13.3, “Enabling
the XSAVE Feature Set and XSAVE-Supported Features,” of Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1.

Operation:

XCR[ECX] <- EDX:EAX;

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| XSETBV:| void _xsetbv( unsigned int, unsigned
|        | __int64);                           

Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not    
|       | 0. If an invalid XCR is specified in     
|       | ECX. If the value in EDX:EAX sets bits   
|       | that are reserved in the XCR specified   
|       | by ECX. If an attempt is made to clear   
|       | bit 0 of XCR0. If an attempt is made     
|       | to set XCR0[2:1] to 10b.                 
| #UD   | If CPUID.01H:ECX.XSAVE[bit 26] = 0.      
|       | If CR4.OSXSAVE[bit 18] = 0. If the LOCK  
|       | prefix is used. If 66H, F3H or F2H prefix
|       | is used.                                 

Real-Address Mode Exceptions:
| #GP| If an invalid XCR is specified in ECX.   
|    | If the value in EDX:EAX sets bits that   
|    | are reserved in the XCR specified by     
|    | ECX. If an attempt is made to clear      
|    | bit 0 of XCR0. If an attempt is made     
|    | to set XCR0[2:1] to 10b.                 
| #UD| If CPUID.01H:ECX.XSAVE[bit 26] = 0.      
|    | If CR4.OSXSAVE[bit 18] = 0. If the LOCK  
|    | prefix is used. If 66H, F3H or F2H prefix
|    | is used.                                 

Virtual-8086 Mode Exceptions:
| #GP(0)| The XSETBV instruction is not recognized
|       | in virtual-8086 mode.                   

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: XTEST
description:
XTEST  -  Test If In Transactional Execution:
| Opcode/Instruction| Op/En| 64/32bit Mode Support| CPUID Feature Flag| Description                         
| 0F 01 D6 XTEST    | A    | V/V                  | HLE or RTM        | Test if executing in a transactional
|                   |      |                      |                   | region                              

Instruction Operand Encoding:
| Op/En| Operand 1| Operand2| Operand3| Operand4
| A    | NA       | NA      | NA      | NA      

Description:
The XTEST instruction queries the transactional execution status. If the instruction
executes inside a transactionally executing RTM region or a transactionally
executing HLE region, then the ZF flag is cleared, else it is set.

Operation:

XTEST
IF (RTM_ACTIVE = 1 OR HLE_ACTIVE = 1)
  THEN
     ZF <- 0
  ELSE
     ZF <- 1
FI;

Flags Affected:
The ZF flag is cleared if the instruction is executed transactionally; otherwise
it is set to 1. The CF, OF, SF, PF, and AF, flags are cleared.


Intel C/C++ Compiler Intrinsic Equivalent:
| XTEST:| int _xtest( void );

SIMD Floating-Point Exceptions:
None


Other Exceptions:
| #UD| CPUID.(EAX=7, ECX=0):HLE[bit 4] = 0     
|    | and CPUID.(EAX=7, ECX=0):RTM[bit 11]    
|    | = 0. If LOCK or 66H or F2H or F3H prefix
|    | is used.                                


