# instructions

platform: x86_64
mnem: SHUFPS
description:
SHUFPS-Packed Interleave Shuffle of Quadruplets of Single-Precision Floating-Point Values
 Opcode/                               Op /   64/32        CPUID           Description
 Instruction                           En     bit Mode     Feature
                                              Support      Flag
 0F C6 /r ib                           RMI    V/V          SSE             Select from quadruplet of single-precision floating-
 SHUFPS xmm1, xmm3/m128, imm8                                              point values in xmm1 and xmm2/m128 using imm8,
                                                                           interleaved result pairs are stored in xmm1.
 VEX.NDS.128.0F.WIG C6 /r ib           RVMI   V/V          AVX             Select from quadruplet of single-precision floating-
 VSHUFPS xmm1, xmm2,                                                       point values in xmm1 and xmm2/m128 using imm8,
 xmm3/m128, imm8                                                           interleaved result pairs are stored in xmm1.
 VEX.NDS.256.0F.WIG C6 /r ib           RVMI   V/V          AVX             Select from quadruplet of single-precision floating-
 VSHUFPS ymm1, ymm2,                                                       point values in ymm2 and ymm3/m256 using imm8,
 ymm3/m256, imm8                                                           interleaved result pairs are stored in ymm1.
 EVEX.NDS.128.0F.W0 C6 /r ib           FV     V/V          AVX512VL        Select from quadruplet of single-precision floating-
 VSHUFPS xmm1{k1}{z}, xmm2,                                AVX512F         point values in xmm1 and xmm2/m128 using imm8,
 xmm3/m128/m32bcst, imm8                                                   interleaved result pairs are stored in xmm1, subject to
                                                                           writemask k1.
 EVEX.NDS.256.0F.W0 C6 /r ib           FV     V/V          AVX512VL        Select from quadruplet of single-precision floating-
 VSHUFPS ymm1{k1}{z}, ymm2,                                AVX512F         point values in ymm2 and ymm3/m256 using imm8,
 ymm3/m256/m32bcst, imm8                                                   interleaved result pairs are stored in ymm1, subject to
                                                                           writemask k1.
 EVEX.NDS.512.0F.W0 C6 /r ib           FV     V/V          AVX512F         Select from quadruplet of single-precision floating-
 VSHUFPS zmm1{k1}{z}, zmm2,                                                point values in zmm2 and zmm3/m512 using imm8,
 zmm3/m512/m32bcst, imm8                                                   interleaved result pairs are stored in zmm1, subject to
                                                                           writemask k1.



                                              Instruction Operand Encoding
        Op/En              Operand 1                  Operand 2                      Operand 3                     Operand 4
         RMI            ModRM:reg (r, w)            ModRM:r/m (r)                       Imm8                           NA
        RVMI             ModRM:reg (w)               VEX.vvvv (r)                  ModRM:r/m (r)                      Imm8
         FV              ModRM:reg (w)               EVEX.vvvv (r)                 ModRM:r/m (r)                      Imm8

Description
Selects a single-precision floating-point value of an input quadruplet using a two-bit control and move to a desig-
nated element of the destination operand. Each 64-bit element-pair of a 128-bit lane of the destination operand is
interleaved between the corresponding lane of the first source operand and the second source operand at the gran-
ularity 128 bits. Each two bits in the imm8 byte, starting from bit 0, is the select control of the corresponding
element of a 128-bit lane of the destination to received the shuffled result of an input quadruplet. The two lower
elements of a 128-bit lane in the destination receives shuffle results from the quadruple of the first source operand.
The next two elements of the destination receives shuffle results from the quadruple of the second source operand.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32-bit memory location. The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
Imm8[7:0] provides 4 select controls for each applicable 128-bit lane of the destination.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. Imm8[7:0] provides 4 select
controls for the high and low 128-bit of the destination.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed. Imm8[7:0] provides 4 select controls for each element
of the destination.





128-bit Legacy SSE version: The source can be an XMM register or an 128-bit memory location. The destination is
not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified. Imm8[7:0] provides 4 select controls for each element of the destination.




                        SRC1     X7         X6        X5         X4        X3         X2        X1         X0



                        SRC2     Y7         Y6        Y5         Y4        Y3         Y2        Y1         Y0



                        DEST Y7 .. Y4    Y7 .. Y4    X7 .. X4   X7 .. X4 Y3 ..Y0    Y3 ..Y0   X3 .. X0   X3 .. X0




  Figure 4-26. 256-bit VSHUFPS Operation of Selection from Input Quadruplet and Pair-wise Interleaved Result


Operation
Select4(SRC, control) {
CASE (control[1:0]) OF
   0: TMP <-SRC[31:0];
   1: TMP <-SRC[63:32];
   2: TMP <-SRC[95:64];
   3: TMP <-SRC[127:96];
ESAC;
RETURN TMP
}

VPSHUFPS (EVEX encoded versions when SRC2 is a vector register)
(KL, VL) = (4, 128), (8, 256), (16, 512)

TMP_DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] <- Select4(SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] <- Select4(SRC2[127:0], imm8[7:6]);
IF VL >= 256
    TMP_DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);
    TMP_DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);
    TMP_DEST[223:192] <- Select4(SRC2[255:128], imm8[5:4]);
    TMP_DEST[255:224] <- Select4(SRC2[255:128], imm8[7:6]);
FI;
IF VL >= 512
    TMP_DEST[287:256] <- Select4(SRC1[383:256], imm8[1:0]);
    TMP_DEST[319:288] <- Select4(SRC1[383:256], imm8[3:2]);
    TMP_DEST[351:320] <- Select4(SRC2[383:256], imm8[5:4]);
    TMP_DEST[383:352] <- Select4(SRC2[383:256], imm8[7:6]);
    TMP_DEST[415:384] <- Select4(SRC1[511:384], imm8[1:0]);
    TMP_DEST[447:416] <- Select4(SRC1[511:384], imm8[3:2]);
    TMP_DEST[479:448] <-Select4(SRC2[511:384], imm8[5:4]);
    TMP_DEST[511:480] <- Select4(SRC2[511:384], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1




   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSHUFPS (EVEX encoded versions when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
TMP_DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
TMP_DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
TMP_DEST[95:64] <- Select4(TMP_SRC2[127:0], imm8[5:4]);
TMP_DEST[127:96] <- Select4(TMP_SRC2[127:0], imm8[7:6]);
IF VL >= 256
    TMP_DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);
    TMP_DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);
    TMP_DEST[223:192] <- Select4(TMP_SRC2[255:128], imm8[5:4]);
    TMP_DEST[255:224] <- Select4(TMP_SRC2[255:128], imm8[7:6]);
FI;
IF VL >= 512
    TMP_DEST[287:256] <- Select4(SRC1[383:256], imm8[1:0]);
    TMP_DEST[319:288] <- Select4(SRC1[383:256], imm8[3:2]);
    TMP_DEST[351:320] <- Select4(TMP_SRC2[383:256], imm8[5:4]);
    TMP_DEST[383:352] <- Select4(TMP_SRC2[383:256], imm8[7:6]);
    TMP_DEST[415:384] <- Select4(SRC1[511:384], imm8[1:0]);
    TMP_DEST[447:416] <- Select4(SRC1[511:384], imm8[3:2]);
    TMP_DEST[479:448] <-Select4(TMP_SRC2[511:384], imm8[5:4]);
    TMP_DEST[511:480] <- Select4(TMP_SRC2[511:384], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR



DEST[MAX_VL-1:VL] <- 0
VSHUFPS (VEX.256 encoded version)
DEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);
DEST[159:128] <-Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] <-Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] <-Select4(SRC2[255:128], imm8[5:4]);
DEST[255:224] <-Select4(SRC2[255:128], imm8[7:6]);
DEST[MAX_VL-1:256] <-0

VSHUFPS (VEX.128 encoded version)
DEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);
DEST[MAX_VL-1:128] <-0

SHUFPS (128-bit Legacy SSE version)
DEST[31:0] <-Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <-Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <-Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <-Select4(SRC2[127:0], imm8[7:6]);
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSHUFPS __m512 _mm512_shuffle_ps(__m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_mask_shuffle_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m512 _mm512_maskz_shuffle_ps(__mmask16 k, __m512 a, __m512 b, int imm);
VSHUFPS __m256 _mm256_shuffle_ps (__m256 a, __m256 b, const int select);
VSHUFPS __m256 _mm256_mask_shuffle_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);
VSHUFPS __m256 _mm256_maskz_shuffle_ps(__mmask8 k, __m256 a, __m256 b, int imm);
SHUFPS __m128 _mm_shuffle_ps (__m128 a, __m128 b, const int select);
VSHUFPS __m128 _mm_mask_shuffle_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VSHUFPS __m128 _mm_maskz_shuffle_ps(__mmask8 k, __m128 a, __m128 b, int imm);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.






platform: x86_64
mnem: SIDT
description:
SIDT-Store Interrupt Descriptor Table Register
 Opcode*                   Instruction                   Op/    64-Bit       Compat/ Description
                                                         En     Mode         Leg Mode
 0F 01 /1                  SIDT m                        M      Valid        Valid         Store IDTR to m.



                                                   Instruction Operand Encoding
   Op/En             Operand 1                      Operand 2                        Operand 3                       Operand 4
     M             ModRM:r/m (w)                        NA                                NA                             NA


Description
Stores the content the interrupt descriptor table register (IDTR) in the destination operand. The destination
operand specifies a 6-byte memory location.
In non-64-bit modes, if the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low
2 bytes of the memory location and the 32-bit base address is stored in the high 4 bytes. If the operand-size attri-
bute is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in the third, fourth, and
fifth byte, with the sixth byte filled with 0s.
In 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores 8-byte base and 2-byte limit values.
SIDT is only useful in operating-system software; however, it can be used in application programs without causing
an exception to be generated if CR4.UMIP = 0. See "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register"
in Chapter 3, Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for information on
loading the GDTR and IDTR.

IA-32 Architecture Compatibility
The 16-bit form of SIDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The Intel
286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits with
0s.

Operation
IF instruction is SIDT
     THEN
         IF OperandSize = 16
              THEN
                    DEST[0:15] <- IDTR(Limit);
                    DEST[16:39] <- IDTR(Base); (* 24 bits of base address stored; *)
                    DEST[40:47] <- 0;
              ELSE IF (32-bit Operand Size)
                    DEST[0:15] <- IDTR(Limit);
                    DEST[16:47] <- IDTR(Base); FI; (* Full 32-bit base address stored *)
              ELSE (* 64-bit Operand Size *)
                    DEST[0:15] <- IDTR(Limit);
                    DEST[16:79] <- IDTR(Base); (* Full 64-bit base address stored *)
         FI;
FI;

Flags Affected
None.





Protected Mode Exceptions
#GP(0)                    If the destination is located in a non-writable segment.
                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                          selector.
                          If CR4.UMIP = 1 and CPL > 0.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD                       If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                       If a memory operand effective address is outside the SS segment limit.
#UD                       If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If CR4.UMIP = 1.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made.
#UD                       If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                    If a memory address referencing the SS segment is in a non-canonical form.
#UD                       If the destination operand is a register.
                          If the LOCK prefix is used.
#GP(0)                    If the memory address is in a non-canonical form.
                          If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.






platform: x86_64
mnem: SLDT
description:
SLDT-Store Local Descriptor Table Register
 Opcode*                  Instruction                 Op/     64-Bit   Compat/ Description
                                                      En      Mode     Leg Mode
 0F 00 /0                 SLDT r/m16                  M       Valid    Valid       Stores segment selector from LDTR in r/m16.
 REX.W + 0F 00 /0         SLDT r64/m16                M       Valid    Valid       Stores segment selector from LDTR in
                                                                                   r64/m16.



                                              Instruction Operand Encoding
  Op/En               Operand 1                   Operand 2                    Operand 3                     Operand 4
    M               ModRM:r/m (w)                     NA                          NA                             NA


Description
Stores the segment selector from the local descriptor table register (LDTR) in the destination operand. The desti-
nation operand can be a general-purpose register or a memory location. The segment selector stored with this
instruction points to the segment descriptor (located in the GDT) for the current LDT. This instruction can only be
executed in protected mode.
Outside IA-32e mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into
the low-order 16 bits of the register. The high-order 16 bits of the register are cleared for the Pentium 4, Intel Xeon,
and P6 family processors. They are undefined for Pentium, Intel486, and Intel386 processors. When the destina-
tion operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of
the operand size.
In compatibility mode, when the destination operand is a 32-bit register, the 16-bit segment selector is copied into
the low-order 16 bits of the register. The high-order 16 bits of the register are cleared. When the destination
operand is a memory location, the segment selector is written to memory as a 16-bit quantity, regardless of the
operand size.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). The
behavior of SLDT with a 64-bit register is to zero-extend the 16-bit selector and store it in the register. If the desti-
nation is memory and operand size is 64, SLDT will write the 16-bit selector to memory as a 16-bit quantity,
regardless of the operand size.

Operation
DEST <- LDTR(SegmentSelector);

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the destination is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                        selector.
                        If CR4.UMIP = 1 and CPL > 0.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD                     If the LOCK prefix is used.





Real-Address Mode Exceptions
#UD                       The SLDT instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                       The SLDT instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                    If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                    If the memory address is in a non-canonical form.
                          If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD                       If the LOCK prefix is used.






platform: x86_64
mnem: SMSW
description:
SMSW-Store Machine Status Word
 Opcode*                    Instruction         Op/     64-Bit   Compat/ Description
                                                En      Mode     Leg Mode
 0F 01 /4                   SMSW r/m16          M       Valid    Valid       Store machine status word to r/m16.
 0F 01 /4                   SMSW r32/m16        M       Valid    Valid       Store machine status word in low-order 16
                                                                             bits of r32/m16; high-order 16 bits of r32 are
                                                                             undefined.
 REX.W + 0F 01 /4           SMSW r64/m16        M       Valid    Valid       Store machine status word in low-order 16
                                                                             bits of r64/m16; high-order 16 bits of r32 are
                                                                             undefined.



                                           Instruction Operand Encoding
    Op/En             Operand 1             Operand 2                    Operand 3                     Operand 4
     M              ModRM:r/m (w)              NA                           NA                             NA


Description
Stores the machine status word (bits 0 through 15 of control register CR0) into the destination operand. The desti-
nation operand can be a general-purpose register or a memory location.
In non-64-bit modes, when the destination operand is a 32-bit register, the low-order 16 bits of register CR0 are
copied into the low-order 16 bits of the register and the high-order 16 bits are undefined. When the destination
operand is a memory location, the low-order 16 bits of register CR0 are written to memory as a 16-bit quantity,
regardless of the operand size.
In 64-bit mode, the behavior of the SMSW instruction is defined by the following examples:
.    SMSW r16 operand size 16, store CR0[15:0] in r16
.    SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
.    SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64
.    SMSW m16 operand size 16, store CR0[15:0] in m16
.    SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)
.    SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)
SMSW is only useful in operating-system software. However, it is not a privileged instruction and can be used in
application programs if CR4.UMIP = 0. It is provided for compatibility with the Intel 286 processor. Programs and
procedures intended to run on IA-32 and Intel 64 processors beginning with the Intel386 processors should use the
MOV CR instruction to load the machine status word.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
DEST <- CR0[15:0];
(* Machine status word *)

Flags Affected
None.





Protected Mode Exceptions
#GP(0)                 If the destination is located in a non-writable segment.
                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                       selector.
                       If CR4.UMIP = 1 and CPL > 0.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD                    If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#UD                    If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If CR4.UMIP = 1.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
                       If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.
#UD                    If the LOCK prefix is used.






platform: x86_64
mnem: SQRTPD
description:
SQRTPD-Square Root of Double-Precision Floating-Point Values
 Opcode/                            Op /   64/32       CPUID          Description
 Instruction                        En     bit Mode    Feature
                                           Support     Flag
 66 0F 51 /r                        RM     V/V         SSE2           Computes Square Roots of the packed double-precision
 SQRTPD xmm1, xmm2/m128                                               floating-point values in xmm2/m128 and stores the result
                                                                      in xmm1.
 VEX.128.66.0F.WIG 51 /r            RM     V/V         AVX            Computes Square Roots of the packed double-precision
 VSQRTPD xmm1, xmm2/m128                                              floating-point values in xmm2/m128 and stores the result
                                                                      in xmm1.
 VEX.256.66.0F.WIG 51 /r            RM     V/V         AVX            Computes Square Roots of the packed double-precision
 VSQRTPD ymm1, ymm2/m256                                              floating-point values in ymm2/m256 and stores the result
                                                                      in ymm1.
 EVEX.128.66.0F.W1 51 /r            FV     V/V         AVX512VL       Computes Square Roots of the packed double-precision
 VSQRTPD xmm1 {k1}{z},                                 AVX512F        floating-point values in xmm2/m128/m64bcst and stores
 xmm2/m128/m32bcst                                                    the result in xmm1 subject to writemask k1.
 EVEX.256.66.0F.W1 51 /r            FV     V/V         AVX512VL       Computes Square Roots of the packed double-precision
 VSQRTPD ymm1 {k1}{z},                                 AVX512F        floating-point values in ymm2/m256/m64bcst and stores
 ymm2/m256/m32bcst                                                    the result in ymm1 subject to writemask k1.
 EVEX.512.66.0F.W1 51 /r            FV     V/V         AVX512F        Computes Square Roots of the packed double-precision
 VSQRTPD zmm1 {k1}{z},                                                floating-point values in zmm2/m512/m64bcst and stores
 zmm2/m512/m64bcst{er}                                                the result in zmm1 subject to writemask k1.



                                             Instruction Operand Encoding
       Op/En                Operand 1                  Operand 2                    Operand 3                  Operand 4
         RM                ModRM:reg (w)              ModRM:r/m (r)                    NA                          NA
         FV                ModRM:reg (w)              ModRM:r/m (r)                    NA                          NA

Description
Performs a SIMD computation of the square roots of the two, four or eight packed double-precision floating-point
values in the source operand (the second operand) stores the packed double-precision floating-point results in the
destination operand (the first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or
a 512/256/128-bit vector broadcasted from a 64-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-
tion operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-
tion is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





Operation
VSQRTPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+63:i] <- SQRT(SRC[63:0])
                    ELSE DEST[i+63:i] <- SQRT(SRC[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSQRTPD (VEX.256 encoded version)
DEST[63:0] <-SQRT(SRC[63:0])
DEST[127:64] <-SQRT(SRC[127:64])
DEST[191:128] <-SQRT(SRC[191:128])
DEST[255:192] <-SQRT(SRC[255:192])
DEST[MAX_VL-1:256] <- 0
.
VSQRTPD (VEX.128 encoded version)
DEST[63:0] <-SQRT(SRC[63:0])
DEST[127:64] <-SQRT(SRC[127:64])
DEST[MAX_VL-1:128] <-0

SQRTPD (128-bit Legacy SSE version)
DEST[63:0] <-SQRT(SRC[63:0])
DEST[127:64] <-SQRT(SRC[127:64])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSQRTPD __m512d _mm512_sqrt_round_pd(__m512d a, int r);
VSQRTPD __m512d _mm512_mask_sqrt_round_pd(__m512d s, __mmask8 k, __m512d a, int r);
VSQRTPD __m512d _mm512_maskz_sqrt_round_pd( __mmask8 k, __m512d a, int r);
VSQRTPD __m256d _mm256_sqrt_pd (__m256d a);
VSQRTPD __m256d _mm256_mask_sqrt_pd(__m256d s, __mmask8 k, __m256d a, int r);
VSQRTPD __m256d _mm256_maskz_sqrt_pd( __mmask8 k, __m256d a, int r);
SQRTPD __m128d _mm_sqrt_pd (__m128d a);
VSQRTPD __m128d _mm_mask_sqrt_pd(__m128d s, __mmask8 k, __m128d a, int r);
VSQRTPD __m128d _mm_maskz_sqrt_pd( __mmask8 k, __m128d a, int r);




SIMD Floating-Point Exceptions
Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2; additionally
#UD                  If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E2.
#UD                  If EVEX.vvvv != 1111B.






platform: x86_64
mnem: SQRTPS
description:
SQRTPS-Square Root of Single-Precision Floating-Point Values
 Opcode/                                 Op /    64/32           CPUID      Description
 Instruction                             En      bit Mode        Feature
                                                 Support         Flag
 0F 51 /r                                RM      V/V             SSE        Computes Square Roots of the packed single-precision
 SQRTPS xmm1, xmm2/m128                                                     floating-point values in xmm2/m128 and stores the result in
                                                                            xmm1.
 VEX.128.0F.WIG 51 /r                    RM      V/V             AVX        Computes Square Roots of the packed single-precision
 VSQRTPS xmm1, xmm2/m128                                                    floating-point values in xmm2/m128 and stores the result in
                                                                            xmm1.
 VEX.256.0F.WIG 51/r                     RM      V/V             AVX        Computes Square Roots of the packed single-precision
 VSQRTPS ymm1, ymm2/m256                                                    floating-point values in ymm2/m256 and stores the result in
                                                                            ymm1.
 EVEX.128.0F.W0 51 /r                    FV      V/V             AVX512VL   Computes Square Roots of the packed single-precision
 VSQRTPS xmm1 {k1}{z},                                           AVX512F    floating-point values in xmm2/m128/m32bcst and stores
 xmm2/m128/m32bcst                                                          the result in xmm1 subject to writemask k1.
 EVEX.256.0F.W0 51 /r                    FV      V/V             AVX512VL   Computes Square Roots of the packed single-precision
 VSQRTPS ymm1 {k1}{z},                                           AVX512F    floating-point values in ymm2/m256/m32bcst and stores
 ymm2/m256/m32bcst                                                          the result in ymm1 subject to writemask k1.
 EVEX.512.0F.W0 51/r                     FV      V/V             AVX512F    Computes Square Roots of the packed single-precision
 VSQRTPS zmm1 {k1}{z},                                                      floating-point values in zmm2/m512/m32bcst and stores
 zmm2/m512/m32bcst{er}                                                      the result in zmm1 subject to writemask k1.



                                                       Instruction Operand Encoding
       Op/En                 Operand 1                         Operand 2               Operand 3                    Operand 4
        RM                 ModRM:reg (w)                  ModRM:r/m (r)                    NA                           NA
        FV                 ModRM:reg (w)                  ModRM:r/m (r)                    NA                           NA

Description
Performs a SIMD computation of the square roots of the four, eight or sixteen packed single-precision floating-point
values in the source operand (second operand) stores the packed single-precision floating-point results in the
destination operand.
EVEX.512 encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location
or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination are
zeroed.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-
tion operand is an XMM register. The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination are
zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-
tion is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding ZMM
register destination are unmodified.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





Operation
VSQRTPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+31:i] <- SQRT(SRC[31:0])
                    ELSE DEST[i+31:i] <- SQRT(SRC[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSQRTPS (VEX.256 encoded version)
DEST[31:0] <-SQRT(SRC[31:0])
DEST[63:32] <-SQRT(SRC[63:32])
DEST[95:64] <-SQRT(SRC[95:64])
DEST[127:96] <-SQRT(SRC[127:96])
DEST[159:128] <-SQRT(SRC[159:128])
DEST[191:160] <-SQRT(SRC[191:160])
DEST[223:192] <-SQRT(SRC[223:192])
DEST[255:224] <-SQRT(SRC[255:224])

VSQRTPS (VEX.128 encoded version)
DEST[31:0] <-SQRT(SRC[31:0])
DEST[63:32] <-SQRT(SRC[63:32])
DEST[95:64] <-SQRT(SRC[95:64])
DEST[127:96] <-SQRT(SRC[127:96])
DEST[MAX_VL-1:128] <-0

SQRTPS (128-bit Legacy SSE version)
DEST[31:0] <-SQRT(SRC[31:0])
DEST[63:32] <-SQRT(SRC[63:32])
DEST[95:64] <-SQRT(SRC[95:64])
DEST[127:96] <-SQRT(SRC[127:96])
DEST[MAX_VL-1:128] (Unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VSQRTPS __m512 _mm512_sqrt_round_ps(__m512 a, int r);
VSQRTPS __m512 _mm512_mask_sqrt_round_ps(__m512 s, __mmask16 k, __m512 a, int r);
VSQRTPS __m512 _mm512_maskz_sqrt_round_ps( __mmask16 k, __m512 a, int r);
VSQRTPS __m256 _mm256_sqrt_ps (__m256 a);
VSQRTPS __m256 _mm256_mask_sqrt_ps(__m256 s, __mmask8 k, __m256 a, int r);
VSQRTPS __m256 _mm256_maskz_sqrt_ps( __mmask8 k, __m256 a, int r);
SQRTPS __m128 _mm_sqrt_ps (__m128 a);
VSQRTPS __m128 _mm_mask_sqrt_ps(__m128 s, __mmask8 k, __m128 a, int r);
VSQRTPS __m128 _mm_maskz_sqrt_ps( __mmask8 k, __m128 a, int r);

SIMD Floating-Point Exceptions
Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2; additionally
#UD                      If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E2.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: SQRTSD
description:
SQRTSD-Compute Square Root of Scalar Double-Precision Floating-Point Value
 Opcode/                         Op /   64/32        CPUID         Description
 Instruction                     En     bit Mode     Feature
                                        Support      Flag
 F2 0F 51/r                      RM     V/V          SSE2          Computes square root of the low double-precision floating-
 SQRTSD xmm1,xmm2/m64                                              point value in xmm2/m64 and stores the results in xmm1.
 VEX.NDS.128.F2.0F.WIG 51/r      RVM    V/V          AVX           Computes square root of the low double-precision floating-
 VSQRTSD xmm1,xmm2,                                                point value in xmm3/m64 and stores the results in xmm1.
 xmm3/m64                                                          Also, upper double-precision floating-point value
                                                                   (bits[127:64]) from xmm2 is copied to xmm1[127:64].
 EVEX.NDS.LIG.F2.0F.W1 51/r      T1S    V/V          AVX512F       Computes square root of the low double-precision floating-
 VSQRTSD xmm1 {k1}{z}, xmm2,                                       point value in xmm3/m64 and stores the results in xmm1
 xmm3/m64{er}                                                      under writemask k1. Also, upper double-precision floating-
                                                                   point value (bits[127:64]) from xmm2 is copied to
                                                                   xmm1[127:64].



                                          Instruction Operand Encoding
       Op/En              Operand 1                Operand 2                     Operand 3                    Operand 4
        RM              ModRM:reg (w)          ModRM:r/m (r)                        NA                            NA
        RVM             ModRM:reg (w)              VEX.vvvv (r)               ModRM:r/m (r)                       NA
        T1S             ModRM:reg (w)          EVEX.vvvv (r)                  ModRM:r/m (r)                       NA

Description
Computes the square root of the low double-precision floating-point value in the second source operand and stores
the double-precision floating-point result in the destination operand. The second source operand can be an XMM
register or a 64-bit memory location. The first source and destination operands are XMM registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. The quadword at
bits 127:64 of the destination operand remains unchanged. Bits (MAX_VL-1:64) of the corresponding destination
register remain unchanged.
VEX.128 and EVEX encoded versions: Bits 127:64 of the destination operand are copied from the corresponding
bits of the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VSQRTSD is encoded with VEX.L=0. Encoding VSQRTSD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VSQRTSD (EVEX encoded version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SQRT(SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VSQRTSD (VEX.128 encoded version)
DEST[63:0] <-SQRT(SRC2[63:0])
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

SQRTSD (128-bit Legacy SSE version)
DEST[63:0] <-SQRT(SRC[63:0])
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSQRTSD __m128d _mm_sqrt_round_sd(__m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_mask_sqrt_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int r);
VSQRTSD __m128d _mm_maskz_sqrt_round_sd(__mmask8 k, __m128d a, __m128d b, int r);
SQRTSD __m128d _mm_sqrt_sd (__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: SQRTSS
description:
SQRTSS-Compute Square Root of Scalar Single-Precision Value
 Opcode/                         Op /   64/32      CPUID          Description
 Instruction                     En     bit Mode   Feature
                                        Support    Flag
 F3 0F 51 /r                     RM     V/V        SSE            Computes square root of the low single-precision floating-point
 SQRTSS xmm1, xmm2/m32                                            value in xmm2/m32 and stores the results in xmm1.
 VEX.NDS.128.F3.0F.WIG 51 /r     RVM    V/V        AVX            Computes square root of the low single-precision floating-point
 VSQRTSS xmm1, xmm2,                                              value in xmm3/m32 and stores the results in xmm1. Also,
 xmm3/m32                                                         upper single-precision floating-point values (bits[127:32]) from
                                                                  xmm2 are copied to xmm1[127:32].
 EVEX.NDS.LIG.F3.0F.W0 51 /r     T1S    V/V        AVX512F        Computes square root of the low single-precision floating-point
 VSQRTSS xmm1 {k1}{z}, xmm2,                                      value in xmm3/m32 and stores the results in xmm1 under
 xmm3/m32{er}                                                     writemask k1. Also, upper single-precision floating-point values
                                                                  (bits[127:32]) from xmm2 are copied to xmm1[127:32].



                                              Instruction Operand Encoding
       Op/En              Operand 1                 Operand 2                      Operand 3                    Operand 4
        RM              ModRM:reg (w)              ModRM:r/m (r)                       NA                           NA
        RVM             ModRM:reg (w)              VEX.vvvv (r)                  ModRM:r/m (r)                      NA
        T1S             ModRM:reg (w)              EVEX.vvvv (r)                 ModRM:r/m (r)                      NA

Description
Computes the square root of the low single-precision floating-point value in the second source operand and stores
the single-precision floating-point result in the destination operand. The second source operand can be an XMM
register or a 32-bit memory location. The first source and destination operands is an XMM register.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (MAX_VL-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits 127:32 of the destination operand are copied from the corresponding
bits of the first source operand. Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VSQRTSS is encoded with VEX.L=0. Encoding VSQRTSS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.





Operation
VSQRTSS (EVEX encoded version)
IF (EVEX.b = 1) AND (SRC2 *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SQRT(SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[31:0] <- 0
         FI;
FI;
DEST[127:31] <- SRC1[127:31]
DEST[MAX_VL-1:128] <- 0

VSQRTSS (VEX.128 encoded version)
DEST[31:0] <-SQRT(SRC2[31:0])
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

SQRTSS (128-bit Legacy SSE version)
DEST[31:0] <-SQRT(SRC2[31:0])
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSQRTSS __m128 _mm_sqrt_round_ss(__m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_mask_sqrt_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int r);
VSQRTSS __m128 _mm_maskz_sqrt_round_ss( __mmask8 k, __m128 a, __m128 b, int r);
SQRTSS __m128 _mm_sqrt_ss(__m128 a)

SIMD Floating-Point Exceptions
Invalid, Precision, Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: STAC
description:
STAC-Set AC Flag in EFLAGS Register
 Opcode/                                  Op /        64/32 bit   CPUID     Description
 Instruction                              En          Mode        Feature
                                                      Support     Flag
 0F 01 CB                                 NP          V/V         SMAP      Set the AC flag in the EFLAGS register.
 STAC



                                          Instruction Operand Encoding
  Op/En           Operand 1                Operand 2                        Operand 3                     Operand 4
    NP               NA                          NA                            NA                             NA

Description
Sets the AC flag bit in EFLAGS register. This may enable alignment checking of user-mode data accesses. This
allows explicit supervisor-mode data accesses to user-mode pages even if the SMAP bit is set in the CR4 register.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Attempts to execute STAC when
CPL > 0 cause #UD.

Operation

EFLAGS.AC <- 1;

Flags Affected
AC set. Other flags are unaffected.

Protected Mode Exceptions
#UD                 If the LOCK prefix is used.
                    If the CPL > 0.
                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

Real-Address Mode Exceptions
#UD                 If the LOCK prefix is used.
                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

Virtual-8086 Mode Exceptions
#UD                 The STAC instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
#UD                 If the LOCK prefix is used.
                    If the CPL > 0.
                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.

64-Bit Mode Exceptions
#UD                 If the LOCK prefix is used.
                    If the CPL > 0.
                    If CPUID.(EAX=07H, ECX=0H):EBX.SMAP[bit 20] = 0.






platform: x86_64
mnem: STC
description:
STC-Set Carry Flag
 Opcode                  Instruction                 Op/   64-Bit   Compat/ Description
                                                     En    Mode     Leg Mode
 F9                      STC                         NP    Valid    Valid       Set CF flag.



                                             Instruction Operand Encoding
   Op/En             Operand 1                Operand 2                     Operand 3                      Operand 4
      NP                NA                       NA                            NA                             NA


Description
Sets the CF flag in the EFLAGS register. Operation is the same in all modes.

Operation
CF <- 1;

Flags Affected
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.

Exceptions (All Operating Modes)
#UD                    If the LOCK prefix is used.






platform: x86_64
mnem: STD
description:
STD-Set Direction Flag
Opcode                 Instruction                 Op/   64-bit   Compat/ Description
                                                   En    Mode     Leg Mode
FD                     STD                         NP    Valid    Valid        Set DF flag.



                                            Instruction Operand Encoding
  Op/En           Operand 1                  Operand 2                     Operand 3             Operand 4
     NP               NA                        NA                            NA                    NA


Description
Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string operations decrement the index regis-
ters (ESI and/or EDI). Operation is the same in all modes.

Operation
DF <- 1;

Flags Affected
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.

Exceptions (All Operating Modes)
#UD                  If the LOCK prefix is used.






platform: x86_64
mnem: STI
description:
STI-Set Interrupt Flag
 Opcode                      Instruction                   Op/   64-Bit       Compat/ Description
                                                           En    Mode         Leg Mode
 FB                          STI                           NP    Valid        Valid         Set interrupt flag; external, maskable
                                                                                            interrupts enabled at the end of the next
                                                                                            instruction.



                                                    Instruction Operand Encoding
   Op/En                 Operand 1                   Operand 2                        Operand 3                      Operand 4
      NP                     NA                           NA                               NA                            NA


Description
If protected-mode virtual interrupts are not enabled, STI sets the interrupt flag (IF) in the EFLAGS register. After
the IF flag is set, the processor begins responding to external, maskable interrupts after the next instruction is
executed. The delayed effect of this instruction is provided to allow interrupts to be enabled just before returning
from a procedure (or subroutine). For instance, if an STI instruction is followed by an RET instruction, the RET
instruction is allowed to execute before external interrupts are recognized1. If the STI instruction is followed by a
CLI instruction (which clears the IF flag), the effect of the STI instruction is negated.
The IF flag and the STI and CLI instructions do not prohibit the generation of exceptions and NMI interrupts. NMI
interrupts (and SMIs) may be blocked for one macroinstruction following an STI.
When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than 3; STI sets the VIF flag in the
EFLAGS register, leaving IF unaffected.
Table 4-19 indicates the action of the STI instruction depending on the processor's mode of operation and the
CPL/IOPL settings of the running program or procedure.
Operation is the same in all modes.

                                              Table 4-19. Decision Table for STI Results
      CR0.PE       EFLAGS.VM       EFLAGS.IOPL      CS.CPL         CR4.PVI      EFLAGS.VIP         CR4.VME             STI Result
         0               X             X              X                  X             X               X                 IF = 1
         1               0            >= CPL           X                  X             X               X                  IF = 1
         1               0            < CPL           3                  1             X               X                 VIF = 1
         1               0            < CPL           <3                 X             X               X                GP Fault
         1               0            < CPL           X                  0             X               X                GP Fault
         1               0            < CPL           X                  X             1               X                GP Fault
         1               1             3              X                  X             X               X                 IF = 1
         1               1             <3             X                  X             0               1                 VIF = 1
         1               1             <3             X                  X             1               X                GP Fault
         1               1             <3             X                  X             X               0                GP Fault
 NOTES:
 X = This setting has no impact.


1. The STI instruction delays recognition of interrupts only if it is executed with EFLAGS.IF = 0. In a sequence of STI instructions, only
   the first instruction in the sequence is guaranteed to delay interrupts.
      In the following instruction sequence, interrupts may be recognized before RET executes:
      STI
      STI
      RET




Operation
IF PE = 0 (* Executing in real-address mode *)
    THEN
        IF <- 1; (* Set Interrupt Flag *)
    ELSE (* Executing in protected mode or virtual-8086 mode *)
        IF VM = 0 (* Executing in protected mode*)
             THEN
                  IF IOPL >= CPL
                       THEN
                             IF <- 1; (* Set Interrupt Flag *)
                  ELSE
                       IF (IOPL < CPL) and (CPL = 3) and (PVI = 1)
                             THEN
                                 VIF <- 1; (* Set Virtual Interrupt Flag *)
                             ELSE
                                 #GP(0);
                       FI;
                  FI;
             ELSE (* Executing in Virtual-8086 mode *)
                  IF IOPL = 3
                       THEN
                             IF <- 1; (* Set Interrupt Flag *)
                  ELSE
                       IF ((IOPL < 3) and (VIP = 0) and (VME = 1))
                             THEN
                                 VIF <- 1; (* Set Virtual Interrupt Flag *)
                       ELSE
                             #GP(0); (* Trap to virtual-8086 monitor *)
                       FI;)
                  FI;
        FI;
FI;

Flags Affected
The IF flag is set to 1; or the VIF flag is set to 1. Other flags are unaffected.

Protected Mode Exceptions
#GP(0)                   If the CPL is greater (has less privilege) than the IOPL of the current program or procedure.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.




platform: x86_64
mnem: STMXCSR
description:
STMXCSR-Store MXCSR Register State
 Opcode*/                                          Op/      64/32 bit   CPUID      Description
 Instruction                                       En       Mode        Feature
                                                            Support     Flag
 0F AE /3                                          M        V/V         SSE        Store contents of MXCSR register to m32.
 STMXCSR m32
 VEX.LZ.0F.WIG AE /3                               M        V/V         AVX        Store contents of MXCSR register to m32.
 VSTMXCSR m32



                                            Instruction Operand Encoding
  Op/En                Operand 1                Operand 2                     Operand 3                    Operand 4
     M             ModRM:r/m (w)                   NA                             NA                           NA


Description
Stores the contents of the MXCSR control and status register to the destination operand. The destination operand
is a 32-bit memory location. The reserved bits in the MXCSR register are stored as 0s.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
VEX.L must be 0, otherwise instructions will #UD.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
m32 <- MXCSR;

Intel C/C++ Compiler Intrinsic Equivalent
_mm_getcsr(void)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 5; additionally
#UD                      If VEX.L= 1,
                         If VEX.vvvv != 1111B.






platform: x86_64
mnem: STOS
description:
STOS/STOSB/STOSW/STOSD/STOSQ-Store String
Opcode                 Instruction              Op/      64-Bit   Compat/ Description
                                                En       Mode     Leg Mode
AA                     STOS m8                  NA       Valid    Valid       For legacy mode, store AL at address ES:(E)DI;
                                                                              For 64-bit mode store AL at address RDI or
                                                                              EDI.
AB                     STOS m16                 NA       Valid    Valid       For legacy mode, store AX at address ES:(E)DI;
                                                                              For 64-bit mode store AX at address RDI or
                                                                              EDI.
AB                     STOS m32                 NA       Valid    Valid       For legacy mode, store EAX at address
                                                                              ES:(E)DI; For 64-bit mode store EAX at address
                                                                              RDI or EDI.
REX.W + AB             STOS m64                 NA       Valid    N.E.        Store RAX at address RDI or EDI.
AA                     STOSB                    NA       Valid    Valid       For legacy mode, store AL at address ES:(E)DI;
                                                                              For 64-bit mode store AL at address RDI or
                                                                              EDI.
AB                     STOSW                    NA       Valid    Valid       For legacy mode, store AX at address ES:(E)DI;
                                                                              For 64-bit mode store AX at address RDI or
                                                                              EDI.
AB                     STOSD                    NA       Valid    Valid       For legacy mode, store EAX at address
                                                                              ES:(E)DI; For 64-bit mode store EAX at address
                                                                              RDI or EDI.
REX.W + AB             STOSQ                    NA       Valid    N.E.        Store RAX at address RDI or EDI.



                                           Instruction Operand Encoding
  Op/En           Operand 1                  Operand 2                    Operand 3                    Operand 4
     NA               NA                        NA                           NA                            NA


Description
In non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from the AL, AX, or EAX register
(respectively) into the destination operand. The destination operand is a memory location, the address of which is
read from either the ES:EDI or ES:DI register (depending on the address-size attribute of the instruction and the
mode of operation). The ES segment cannot be overridden with a segment override prefix.
At the assembly-code level, two forms of the instruction are allowed: the "explicit-operands" form and the "no-
operands" form. The explicit-operands form (specified with the STOS mnemonic) allows the destination operand to
be specified explicitly. Here, the destination operand should be a symbol that indicates the size and location of the
destination value. The source operand is then automatically selected to match the size of the destination operand
(the AL register for byte operands, AX for word operands, EAX for doubleword operands). The explicit-operands
form is provided to allow documentation; however, note that the documentation provided by this form can be
misleading. That is, the destination operand symbol must specify the correct type (size) of the operand (byte,
word, or doubleword), but it does not have to specify the correct location. The location is always specified by the
ES:(E)DI register. These must be loaded correctly before the store string instruction is executed.
The no-operands form provides "short forms" of the byte, word, doubleword, and quadword versions of the STOS
instructions. Here also ES:(E)DI is assumed to be the destination operand and AL, AX, or EAX is assumed to be the
source operand. The size of the destination and source operands is selected by the mnemonic: STOSB (byte read
from register AL), STOSW (word from AX), STOSD (doubleword from EAX).
After the byte, word, or doubleword is transferred from the register to the memory location, the (E)DI register is
incremented or decremented according to the setting of the DF flag in the EFLAGS register. If the DF flag is 0, the
register is incremented; if the DF flag is 1, the register is decremented (the register is incremented or decremented
by 1 for byte operations, by 2 for word operations, by 4 for doubleword operations).




NOTE: To improve performance, more recent processors support modifications to the processor's operation during
the string store operations initiated with STOS and STOSB. See Section 7.3.9.3 in the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 1 for additional information on fast-string operation.
In 64-bit mode, the default address size is 64 bits, 32-bit address size is supported using the prefix 67H. Using a
REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The promoted no-operand
mnemonic is STOSQ. STOSQ (and its explicit operands variant) store a quadword from the RAX register into the
destination addressed by RDI or EDI. See the summary chart at the beginning of this section for encoding data and
limits.
The STOS, STOSB, STOSW, STOSD, STOSQ instructions can be preceded by the REP prefix for block loads of ECX
bytes, words, or doublewords. More often, however, these instructions are used within a LOOP construct because
data needs to be moved into the AL, AX, or EAX register before it can be stored. See "REP/REPE/REPZ
/REPNE/REPNZ-Repeat String Operation Prefix" in this chapter for a description of the REP prefix.

Operation
Non-64-bit Mode:

IF (Byte store)
    THEN
         DEST <- AL;
              THEN IF DF = 0
                  THEN (E)DI <- (E)DI + 1;
                  ELSE (E)DI <- (E)DI - 1;
              FI;
    ELSE IF (Word store)
         THEN
              DEST <- AX;
                  THEN IF DF = 0
                       THEN (E)DI <- (E)DI + 2;
                       ELSE (E)DI <- (E)DI - 2;
                  FI;
         FI;
    ELSE IF (Doubleword store)
         THEN
              DEST <- EAX;
                  THEN IF DF = 0
                       THEN (E)DI <- (E)DI + 4;
                       ELSE (E)DI <- (E)DI - 4;
                  FI;
         FI;
FI;

64-bit Mode:

IF (Byte store)
    THEN
         DEST <- AL;
             THEN IF DF = 0
                  THEN (R|E)DI <- (R|E)DI + 1;
                  ELSE (R|E)DI <- (R|E)DI - 1;
             FI;
    ELSE IF (Word store)
         THEN
             DEST <- AX;



                   THEN IF DF = 0
                       THEN (R|E)DI <- (R|E)DI + 2;
                       ELSE (R|E)DI <- (R|E)DI - 2;
                   FI;
          FI;
      ELSE IF (Doubleword store)
          THEN
                DEST <- EAX;
                    THEN IF DF = 0
                        THEN (R|E)DI <- (R|E)DI + 4;
                        ELSE (R|E)DI <- (R|E)DI - 4;
                    FI;
          FI;
      ELSE IF (Quadword store using REX.W )
          THEN
                DEST <- RAX;
                    THEN IF DF = 0
                        THEN (R|E)DI <- (R|E)DI + 8;
                        ELSE (R|E)DI <- (R|E)DI - 8;
                    FI;
          FI;
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                    If the destination is located in a non-writable segment.
                          If a memory operand effective address is outside the limit of the ES segment.
                          If the ES register contains a NULL segment selector.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the
                          current privilege level is 3.
#UD                       If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                       If a memory operand effective address is outside the ES segment limit.
#UD                       If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                    If a memory operand effective address is outside the ES segment limit.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made.
#UD                       If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                    If the memory address is in a non-canonical form.




#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: STR
description:
STR-Store Task Register
Opcode                 Instruction                 Op/   64-Bit   Compat/ Description
                                                   En    Mode     Leg Mode
0F 00 /1               STR r/m16                   M     Valid    Valid      Stores segment selector from TR in r/m16.



                                           Instruction Operand Encoding
   Op/En             Operand 1                 Operand 2                  Operand 3                   Operand 4
      M           ModRM:r/m (w)                     NA                       NA                           NA


Description
Stores the segment selector from the task register (TR) in the destination operand. The destination operand can be
a general-purpose register or a memory location. The segment selector stored with this instruction points to the
task state segment (TSS) for the currently running task.
When the destination operand is a 32-bit register, the 16-bit segment selector is copied into the lower 16 bits of the
register and the upper 16 bits of the register are cleared. When the destination operand is a memory location, the
segment selector is written to memory as a 16-bit quantity, regardless of operand size.
In 64-bit mode, operation is the same. The size of the memory operand is fixed at 16 bits. In register stores, the 2-
byte TR is zero extended if stored to a 64-bit register.
The STR instruction is useful only in operating-system software. It can only be executed in protected mode.

Operation
DEST <- TR(SegmentSelector);

Flags Affected
None.

Protected Mode Exceptions
#GP(0)               If the destination is a memory operand that is located in a non-writable segment or if the
                     effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                     selector.
                     If CR4.UMIP = 1 and CPL > 0.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                  The STR instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                  The STR instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#GP(0)                    If the memory address is in a non-canonical form.
                          If CR4.UMIP = 1 and CPL > 0.
#SS(0)                    If the stack address is in a non-canonical form.
#PF(fault-code)           If a page fault occurs.
#AC(0)                    If alignment checking is enabled and an unaligned memory reference is made while the
                          current privilege level is 3.
#UD                       If the LOCK prefix is used.






platform: x86_64
mnem: SUB
description:
SUB-Subtract
Opcode                     Instruction                 Op/    64-Bit       Compat/ Description
                                                       En     Mode         Leg Mode
2C ib                      SUB AL, imm8                I      Valid        Valid       Subtract imm8 from AL.
2D iw                      SUB AX, imm16               I      Valid        Valid       Subtract imm16 from AX.
2D id                      SUB EAX, imm32              I      Valid        Valid       Subtract imm32 from EAX.
REX.W + 2D id              SUB RAX, imm32              I      Valid        N.E.        Subtract imm32 sign-extended to 64-bits
                                                                                       from RAX.
80 /5 ib                   SUB r/m8, imm8              MI     Valid        Valid       Subtract imm8 from r/m8.
REX + 80 /5 ib             SUB r/m8*, imm8             MI     Valid        N.E.        Subtract imm8 from r/m8.
81 /5 iw                   SUB r/m16, imm16            MI     Valid        Valid       Subtract imm16 from r/m16.
81 /5 id                   SUB r/m32, imm32            MI     Valid        Valid       Subtract imm32 from r/m32.
REX.W + 81 /5 id           SUB r/m64, imm32            MI     Valid        N.E.        Subtract imm32 sign-extended to 64-bits
                                                                                       from r/m64.
83 /5 ib                   SUB r/m16, imm8             MI     Valid        Valid       Subtract sign-extended imm8 from r/m16.
83 /5 ib                   SUB r/m32, imm8             MI     Valid        Valid       Subtract sign-extended imm8 from r/m32.
REX.W + 83 /5 ib           SUB r/m64, imm8             MI     Valid        N.E.        Subtract sign-extended imm8 from r/m64.
28 /r                      SUB r/m8, r8                MR     Valid        Valid       Subtract r8 from r/m8.
REX + 28 /r                SUB r/m8*, r8*              MR     Valid        N.E.        Subtract r8 from r/m8.
29 /r                      SUB r/m16, r16              MR     Valid        Valid       Subtract r16 from r/m16.
29 /r                      SUB r/m32, r32              MR     Valid        Valid       Subtract r32 from r/m32.
REX.W + 29 /r              SUB r/m64, r64              MR     Valid        N.E.        Subtract r64 from r/m64.
2A /r                      SUB r8, r/m8                RM     Valid        Valid       Subtract r/m8 from r8.
REX + 2A /r                SUB r8*, r/m8*              RM     Valid        N.E.        Subtract r/m8 from r8.
2B /r                      SUB r16, r/m16              RM     Valid        Valid       Subtract r/m16 from r16.
2B /r                      SUB r32, r/m32              RM     Valid        Valid       Subtract r/m32 from r32.
REX.W + 2B /r              SUB r64, r/m64              RM     Valid        N.E.        Subtract r/m64 from r64.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                 Instruction Operand Encoding
  Op/En               Operand 1                     Operand 2                      Operand 3                      Operand 4
     I             AL/AX/EAX/RAX                  imm8/26/32                          NA                             NA
    MI             ModRM:r/m (r, w)               imm8/26/32                          NA                             NA
    MR             ModRM:r/m (r, w)               ModRM:reg (r)                       NA                             NA
    RM             ModRM:reg (r, w)               ModRM:r/m (r)                       NA                             NA


Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result
in the destination operand. The destination operand can be a register or a memory location; the source operand
can be an immediate, register, or memory location. (However, two memory operands cannot be used in one
instruction.) When an immediate value is used as an operand, it is sign-extended to the length of the destination
operand format.





The SUB instruction performs integer subtraction. It evaluates the result for both signed and unsigned integer
operands and sets the OF and CF flags to indicate an overflow in the signed or unsigned result, respectively. The SF
flag indicates the sign of the signed result.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

Operation
DEST <- (DEST - SRC);

Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.

Protected Mode Exceptions
#GP(0)                 If the destination is located in a non-writable segment.
                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                    If a memory operand effective address is outside the SS segment limit.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: SUBPD
description:
SUBPD-Subtract Packed Double-Precision Floating-Point Values
 Opcode/                               Op/   64/32         CPUID      Description
 Instruction                           En    bit Mode      Feature
                                             Support       Flag
 66 0F 5C /r                           RM    V/V           SSE2       Subtract packed double-precision floating-point values
 SUBPD xmm1, xmm2/m128                                                in xmm2/mem from xmm1 and store result in xmm1.
 VEX.NDS.128.66.0F.WIG 5C /r           RVM   V/V           AVX        Subtract packed double-precision floating-point values
 VSUBPD xmm1,xmm2, xmm3/m128                                          in xmm3/mem from xmm2 and store result in xmm1.
 VEX.NDS.256.66.0F.WIG 5C /r           RVM   V/V           AVX        Subtract packed double-precision floating-point values
 VSUBPD ymm1, ymm2, ymm3/m256                                         in ymm3/mem from ymm2 and store result in ymm1.
 EVEX.NDS.128.66.0F.W1 5C /r           FV    V/V           AVX512VL   Subtract packed double-precision floating-point values
 VSUBPD xmm1 {k1}{z}, xmm2,                                AVX512F    from xmm3/m128/m64bcst to xmm2 and store result
 xmm3/m128/m64bcst                                                    in xmm1 with writemask k1.
 EVEX.NDS.256.66.0F.W1 5C /r           FV    V/V           AVX512VL   Subtract packed double-precision floating-point values
 VSUBPD ymm1 {k1}{z}, ymm2,                                AVX512F    from ymm3/m256/m64bcst to ymm2 and store result
 ymm3/m256/m64bcst                                                    in ymm1 with writemask k1.
 EVEX.NDS.512.66.0F.W1 5C /r           FV    V/V           AVX512F    Subtract packed double-precision floating-point values
 VSUBPD zmm1 {k1}{z}, zmm2,                                           from zmm3/m512/m64bcst to zmm2 and store result in
 zmm3/m512/m64bcst{er}                                                zmm1 with writemask k1.



                                             Instruction Operand Encoding
     Op/En             Operand 1                    Operand 2                 Operand 3                     Operand 4
       RM           ModRM:reg (r, w)               ModRM:r/m (r)                  NA                            NA
      RVM            ModRM:reg (w)                 VEX.vvvv (r)             ModRM:r/m (r)                       NA
       FV            ModRM:reg (w)                 EVEX.vvvv (r)            ModRM:r/m (r)                       NA

Description
Performs a SIMD subtract of the two, four or eight packed double-precision floating-point values of the second
Source operand from the first Source operand, and stores the packed double-precision floating-point results in the
destination operand.
VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory
location. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corre-
sponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory
location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corre-
sponding destination register are zeroed.
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 64-bit memory location. The first source operand and destination operands are ZMM
registers. The destination operand is conditionally updated according to the writemask.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.





Operation
VSUBPD (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i]
   ELSE
        IF *merging-masking*                ; merging-masking
             THEN *DEST[63:0] remains unchanged*
             ELSE                           ; zeroing-masking
                  DEST[63:0] <- 0
        FI;
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSUBPD (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask* THEN
             IF (EVEX.b = 1)
                  THEN     DEST[i+63:i] <- SRC1[i+63:i] - SRC2[63:0];
                  ELSE     EST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i];
             FI;
   ELSE
        IF *merging-masking*                ; merging-masking
             THEN *DEST[63:0] remains unchanged*
             ELSE                           ; zeroing-masking
                  DEST[63:0] <- 0
        FI;
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSUBPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
DEST[127:64] <- SRC1[127:64] - SRC2[127:64]
DEST[191:128] <- SRC1[191:128] - SRC2[191:128]
DEST[255:192] <- SRC1[255:192] - SRC2[255:192]
DEST[MAX_VL-1:256] <- 0





VSUBPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
DEST[127:64] <- SRC1[127:64] - SRC2[127:64]
DEST[MAX_VL-1:128] <- 0

SUBPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] - SRC[63:0]
DEST[127:64] <- DEST[127:64] - SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSUBPD __m512d _mm512_sub_pd (__m512d a, __m512d b);
VSUBPD __m512d _mm512_mask_sub_pd (__m512d s, __mmask8 k, __m512d a, __m512d b);
VSUBPD __m512d _mm512_maskz_sub_pd (__mmask8 k, __m512d a, __m512d b);
VSUBPD __m512d _mm512_sub_round_pd (__m512d a, __m512d b, int);
VSUBPD __m512d _mm512_mask_sub_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m512d _mm512_maskz_sub_round_pd (__mmask8 k, __m512d a, __m512d b, int);
VSUBPD __m256d _mm256_sub_pd (__m256d a, __m256d b);
VSUBPD __m256d _mm256_mask_sub_pd (__m256d s, __mmask8 k, __m256d a, __m256d b);
VSUBPD __m256d _mm256_maskz_sub_pd (__mmask8 k, __m256d a, __m256d b);
SUBPD __m128d _mm_sub_pd (__m128d a, __m128d b);
VSUBPD __m128d _mm_mask_sub_pd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VSUBPD __m128d _mm_maskz_sub_pd (__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: SUBPS
description:
SUBPS-Subtract Packed Single-Precision Floating-Point Values
 Opcode/                                      Op/      64/32        CPUID      Description
 Instruction                                  En       bit Mode     Feature
                                                       Support      Flag
 0F 5C /r                                     RM       V/V          SSE        Subtract packed single-precision floating-point values
 SUBPS xmm1, xmm2/m128                                                         in xmm2/mem from xmm1 and store result in xmm1.
 VEX.NDS.128.0F.WIG 5C /r                     RVM      V/V          AVX        Subtract packed single-precision floating-point values
 VSUBPS xmm1,xmm2, xmm3/m128                                                   in xmm3/mem from xmm2 and stores result in xmm1.
 VEX.NDS.256.0F.WIG 5C /r                     RVM      V/V          AVX        Subtract packed single-precision floating-point values
 VSUBPS ymm1, ymm2, ymm3/m256                                                  in ymm3/mem from ymm2 and stores result in ymm1.
 EVEX.NDS.128.0F.W0 5C /r                     FV       V/V          AVX512VL   Subtract packed single-precision floating-point values
 VSUBPS xmm1 {k1}{z}, xmm2,                                         AVX512F    from xmm3/m128/m32bcst to xmm2 and stores
 xmm3/m128/m32bcst                                                             result in xmm1 with writemask k1.
 EVEX.NDS.256.0F.W0 5C /r                     FV       V/V          AVX512VL   Subtract packed single-precision floating-point values
 VSUBPS ymm1 {k1}{z}, ymm2,                                         AVX512F    from ymm3/m256/m32bcst to ymm2 and stores
 ymm3/m256/m32bcst                                                             result in ymm1 with writemask k1.
 EVEX.NDS.512.0F.W0 5C /r                     FV       V/V          AVX512F    Subtract packed single-precision floating-point values
 VSUBPS zmm1 {k1}{z}, zmm2,                                                    in zmm3/m512/m32bcst from zmm2 and stores result
 zmm3/m512/m32bcst{er}                                                         in zmm1 with writemask k1.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                        Operand 2              Operand 3                     Operand 4
        RM               ModRM:reg (r, w)                ModRM:r/m (r)                  NA                            NA
       RVM                ModRM:reg (w)                   VEX.vvvv (r)             ModRM:r/m (r)                      NA
        FV                ModRM:reg (w)                  EVEX.vvvv (r)             ModRM:r/m (r)                      NA

Description
Performs a SIMD subtract of the packed single-precision floating-point values in the second Source operand from
the First Source operand, and stores the packed single-precision floating-point results in the destination operand.
VEX.128 and EVEX.128 encoded versions: The second source operand is an XMM register or an 128-bit memory
location. The first source operand and destination operands are XMM registers. Bits (MAX_VL-1:128) of the corre-
sponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory
location. The first source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corre-
sponding destination register are zeroed.
EVEX.512 encoded version: The second source operand is a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 32-bit memory location. The first source operand and destination operands are ZMM
registers. The destination operand is conditionally updated according to the writemask.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper Bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.





Operation
VSUBPS (EVEX encoded versions) when src2 operand is a vector register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i]
   ELSE
        IF *merging-masking*                ; merging-masking
             THEN *DEST[31:0] remains unchanged*
             ELSE                           ; zeroing-masking
                  DEST[31:0] <- 0
        FI;
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VSUBPS (EVEX encoded versions) when src2 operand is a memory source
(KL, VL) = (4, 128), (8, 256),(16, 512)
FOR j <- 0 TO KL-1
    i <-j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1)
                    THEN     DEST[i+31:i] <- SRC1[i+31:i] - SRC2[31:0];
                    ELSE     DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i];
               FI;

   ELSE
       IF *merging-masking*              ; merging-masking
            THEN *DEST[31:0] remains unchanged*
            ELSE                         ; zeroing-masking
                DEST[31:0] <- 0
       FI;
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VSUBPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[159:128] <- SRC1[159:128] - SRC2[159:128]
DEST[191:160]<- SRC1[191:160] - SRC2[191:160]
DEST[223:192] <- SRC1[223:192] - SRC2[223:192]
DEST[255:224] <- SRC1[255:224] - SRC2[255:224].
DEST[MAX_VL-1:256] <- 0



VSUBPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[MAX_VL-1:128] <- 0

SUBPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSUBPS __m512 _mm512_sub_ps (__m512 a, __m512 b);
VSUBPS __m512 _mm512_mask_sub_ps (__m512 s, __mmask16 k, __m512 a, __m512 b);
VSUBPS __m512 _mm512_maskz_sub_ps (__mmask16 k, __m512 a, __m512 b);
VSUBPS __m512 _mm512_sub_round_ps (__m512 a, __m512 b, int);
VSUBPS __m512 _mm512_mask_sub_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VSUBPS __m512 _mm512_maskz_sub_round_ps (__mmask16 k, __m512 a, __m512 b, int);
VSUBPS __m256 _mm256_sub_ps (__m256 a, __m256 b);
VSUBPS __m256 _mm256_mask_sub_ps (__m256 s, __mmask8 k, __m256 a, __m256 b);
VSUBPS __m256 _mm256_maskz_sub_ps (__mmask16 k, __m256 a, __m256 b);
SUBPS __m128 _mm_sub_ps (__m128 a, __m128 b);
VSUBPS __m128 _mm_mask_sub_ps (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBPS __m128 _mm_maskz_sub_ps (__mmask16 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 2.
EVEX-encoded instructions, see Exceptions Type E2.






platform: x86_64
mnem: SUBSD
description:
SUBSD-Subtract Scalar Double-Precision Floating-Point Value
 Opcode/                             Op /   64/32        CPUID     Description
 Instruction                         En     bit Mode     Feature
                                            Support      Flag
 F2 0F 5C /r                         RM     V/V          SSE2      Subtract the low double-precision floating-point value in
 SUBSD xmm1, xmm2/m64                                              xmm2/m64 from xmm1 and store the result in xmm1.
 VEX.NDS.128.F2.0F.WIG 5C /r         RVM    V/V          AVX       Subtract the low double-precision floating-point value in
 VSUBSD xmm1,xmm2, xmm3/m64                                        xmm3/m64 from xmm2 and store the result in xmm1.
 EVEX.NDS.LIG.F2.0F.W1 5C /r         T1S    V/V          AVX512F   Subtract the low double-precision floating-point value in
 VSUBSD xmm1 {k1}{z}, xmm2,                                        xmm3/m64 from xmm2 and store the result in xmm1
 xmm3/m64{er}                                                      under writemask k1.



                                            Instruction Operand Encoding
    Op/En            Operand 1                    Operand 2                Operand 3                       Operand 4
      RM          ModRM:reg (r, w)           ModRM:r/m (r)                     NA                             NA
     RVM           ModRM:reg (w)              VEX.vvvv (r)               ModRM:r/m (r)                        NA
     T1S           ModRM:reg (w)              EVEX.vvvv (r)              ModRM:r/m (r)                        NA

Description
Subtract the low double-precision floating-point value in the second source operand from the first source operand
and stores the double-precision floating-point result in the low quadword of the destination operand.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VSUBSD is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VSUBSD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                   THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VSUBSD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0] - SRC2[63:0]
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

SUBSD (128-bit Legacy SSE version)
DEST[63:0] <-DEST[63:0] - SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSUBSD __m128d _mm_mask_sub_sd (__m128d s, __mmask8 k, __m128d a, __m128d b);
VSUBSD __m128d _mm_maskz_sub_sd (__mmask8 k, __m128d a, __m128d b);
VSUBSD __m128d _mm_sub_round_sd (__m128d a, __m128d b, int);
VSUBSD __m128d _mm_mask_sub_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSUBSD __m128d _mm_maskz_sub_round_sd (__mmask8 k, __m128d a, __m128d b, int);
SUBSD __m128d _mm_sub_sd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: SUBSS
description:
SUBSS-Subtract Scalar Single-Precision Floating-Point Value
 Opcode/                              Op /   64/32        CPUID     Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 F3 0F 5C /r                          RM     V/V          SSE       Subtract the low single-precision floating-point value in
 SUBSS xmm1, xmm2/m32                                               xmm2/m32 from xmm1 and store the result in xmm1.
 VEX.NDS.128.F3.0F.WIG 5C /r          RVM    V/V          AVX       Subtract the low single-precision floating-point value in
 VSUBSS xmm1,xmm2, xmm3/m32                                         xmm3/m32 from xmm2 and store the result in xmm1.
 EVEX.NDS.LIG.F3.0F.W0 5C /r          T1S    V/V          AVX512F   Subtract the low single-precision floating-point value in
 VSUBSS xmm1 {k1}{z}, xmm2,                                         xmm3/m32 from xmm2 and store the result in xmm1
 xmm3/m32{er}                                                       under writemask k1.



                                             Instruction Operand Encoding
      Op/En             Operand 1                   Operand 2                Operand 3                       Operand 4
        RM           ModRM:reg (r, w)              ModRM:r/m (r)                  NA                             NA
       RVM            ModRM:reg (w)                VEX.vvvv (r)             ModRM:r/m (r)                        NA
       T1S            ModRM:reg (w)                EVEX.vvvv (r)            ModRM:r/m (r)                        NA

Description
Subtract the low single-precision floating-point value from the second source operand and the first source operand
and store the double-precision floating-point result in the low doubleword of the destination operand.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:32) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded versions: Bits (127:32) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VSUBSS is encoded with VEX.L=0. Encoding VSUBSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
VSUBSS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                   THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VSUBSS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0] - SRC2[31:0]
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

SUBSS (128-bit Legacy SSE version)
DEST[31:0] <-DEST[31:0] - SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSUBSS __m128 _mm_mask_sub_ss (__m128 s, __mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_maskz_sub_ss (__mmask8 k, __m128 a, __m128 b);
VSUBSS __m128 _mm_sub_round_ss (__m128 a, __m128 b, int);
VSUBSS __m128 _mm_mask_sub_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSUBSS __m128 _mm_maskz_sub_round_ss (__mmask8 k, __m128 a, __m128 b, int);
SUBSS __m128 _mm_sub_ss (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3.
EVEX-encoded instructions, see Exceptions Type E3.






platform: x86_64
mnem: SWAPGS
description:
SWAPGS-Swap GS Base Register
 Opcode                    Instruction             Op/   64-Bit    Compat/ Description
                                                   En    Mode      Leg Mode
 0F 01 F8                  SWAPGS                  NP    Valid     Invalid      Exchanges the current GS base register value
                                                                                with the value contained in MSR address
                                                                                C0000102H.



                                               Instruction Operand Encoding
   Op/En               Operand 1                 Operand 2                   Operand 3                   Operand 4
    NP                    NA                        NA                          NA                           NA


Description
SWAPGS exchanges the current GS base register value with the value contained in MSR address C0000102H
(IA32_KERNEL_GS_BASE). The SWAPGS instruction is a privileged instruction intended for use by system soft-
ware.
When using SYSCALL to implement system calls, there is no kernel stack at the OS entry point. Neither is there a
straightforward method to obtain a pointer to kernel structures from which the kernel stack pointer could be read.
Thus, the kernel cannot save general purpose registers or reference memory.
By design, SWAPGS does not require any general purpose registers or memory operands. No registers need to be
saved before using the instruction. SWAPGS exchanges the CPL 0 data pointer from the IA32_KERNEL_GS_BASE
MSR with the GS base register. The kernel can then use the GS prefix on normal memory references to access
kernel data structures. Similarly, when the OS kernel is entered using an interrupt or exception (where the kernel
stack is already set up), SWAPGS can be used to quickly get a pointer to the kernel data structures.
The IA32_KERNEL_GS_BASE MSR itself is only accessible using RDMSR/WRMSR instructions. Those instructions
are only accessible at privilege level 0. The WRMSR instruction ensures that the IA32_KERNEL_GS_BASE MSR
contains a canonical address.

Operation
IF CS.L != 1 (* Not in 64-Bit Mode *)
    THEN
         #UD; FI;

IF CPL != 0
    THEN #GP(0); FI;

tmp <- GS.base;
GS.base <- IA32_KERNEL_GS_BASE;
IA32_KERNEL_GS_BASE <- tmp;

Flags Affected
None

Protected Mode Exceptions
#UD                     If Mode    != 64-Bit.

Real-Address Mode Exceptions
#UD                     If Mode    != 64-Bit.

Virtual-8086 Mode Exceptions
#UD                     If Mode    != 64-Bit.


Compatibility Mode Exceptions
#UD                   If Mode   != 64-Bit.

64-Bit Mode Exceptions
#GP(0)                If CPL   != 0.
                      If the LOCK prefix is used.






platform: x86_64
mnem: SYSCALL
description:
SYSCALL-Fast System Call
 Opcode                   Instruction                 Op/   64-Bit      Compat/ Description
                                                      En    Mode        Leg Mode
 0F 05                    SYSCALL                     NP    Valid       Invalid      Fast call to privilege level 0 system
                                                                                     procedures.



                                                Instruction Operand Encoding
  Op/En              Operand 1                    Operand 2                       Operand 3                     Operand 4
    NP                  NA                            NA                             NA                             NA


Description
SYSCALL invokes an OS system-call handler at privilege level 0. It does so by loading RIP from the IA32_LSTAR
MSR (after saving the address of the instruction following SYSCALL into RCX). (The WRMSR instruction ensures
that the IA32_LSTAR MSR always contain a canonical address.)
SYSCALL also saves RFLAGS into R11 and then masks RFLAGS using the IA32_FMASK MSR (MSR address
C0000084H); specifically, the processor clears in RFLAGS every bit corresponding to a bit that is set in the
IA32_FMASK MSR.
SYSCALL loads the CS and SS selectors with values derived from bits 47:32 of the IA32_STAR MSR. However, the
CS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.
Instead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the respon-
sibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-
spond to the fixed values loaded into the descriptor caches; the SYSCALL instruction does not ensure this
correspondence.
The SYSCALL instruction does not save the stack pointer (RSP). If the OS system-call handler will change the stack
pointer, it is the responsibility of software to save the previous value of the stack pointer. This might be done prior
to executing SYSCALL, with software restoring the stack pointer with the instruction following SYSCALL (which will
be executed after SYSRET). Alternatively, the OS system-call handler may save the stack pointer and restore it
before executing SYSRET.

Operation
IF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
    THEN #UD;
FI;

RCX <- RIP;                       (* Will contain address of next instruction *)
RIP <- IA32_LSTAR;
R11 <- RFLAGS;
RFLAGS <- RFLAGS AND NOT(IA32_FMASK);

CS.Selector <- IA32_STAR[47:32] AND FFFCH (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;                             (* Flat segment *)
CS.Limit <- FFFFFH;                       (* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type <- 11;                            (* Execute/read code, accessed *)
CS.S <- 1;
CS.DPL <- 0;
CS.P <- 1;
CS.L <- 1;                                (* Entry is to 64-bit mode *)
CS.D <- 0;                                (* Required if CS.L = 1 *)
CS.G <- 1;                                (* 4-KByte granularity *)
CPL <- 0;



SS.Selector <- IA32_STAR[47:32] + 8;           (* SS just above CS *)
(* Set rest of SS to a fixed value *)
SS.Base <- 0;                                  (* Flat segment *)
SS.Limit <- FFFFFH;                            (* With 4-KByte granularity, implies a 4-GByte limit *)
SS.Type <- 3;                                  (* Read/write data, accessed *)
SS.S <- 1;
SS.DPL <- 0;
SS.P <- 1;
SS.B <- 1;                                     (* 32-bit stack segment *)
SS.G <- 1;                                     (* 4-KByte granularity *)

Flags Affected
All.

Protected Mode Exceptions
#UD                        The SYSCALL instruction is not recognized in protected mode.

Real-Address Mode Exceptions
#UD                        The SYSCALL instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                        The SYSCALL instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
#UD                        The SYSCALL instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions
#UD                        If IA32_EFER.SCE = 0.
                           If the LOCK prefix is used.






platform: x86_64
mnem: SYSENTER
description:
SYSENTER-Fast System Call
Opcode                  Instruction               Op/     64-Bit   Compat/ Description
                                                  En      Mode     Leg Mode
0F 34                   SYSENTER                  NP      Valid    Valid       Fast call to privilege level 0 system
                                                                               procedures.



                                             Instruction Operand Encoding
    Op/En          Operand 1                  Operand 2                    Operand 3                      Operand 4
     NP                NA                        NA                           NA                              NA


Description
Executes a fast call to a level 0 system procedure or routine. SYSENTER is a companion instruction to SYSEXIT. The
instruction is optimized to provide the maximum performance for system calls from user code running at privilege
level 3 to operating system or executive procedures running at privilege level 0.
When executed in IA-32e mode, the SYSENTER instruction transitions the logical processor to 64-bit mode; other-
wise, the logical processor remains in protected mode.
Prior to executing the SYSENTER instruction, software must specify the privilege level 0 code segment and code
entry point, and the privilege level 0 stack segment and stack pointer by writing values to the following MSRs:
.    IA32_SYSENTER_CS (MSR address 174H) - The lower 16 bits of this MSR are the segment selector for the
     privilege level 0 code segment. This value is also used to determine the segment selector of the privilege level
     0 stack segment (see the Operation section). This value cannot indicate a null selector.
.    IA32_SYSENTER_EIP (MSR address 176H) - The value of this MSR is loaded into RIP (thus, this value
     references the first instruction of the selected operating procedure or routine). In protected mode, only
     bits 31:0 are loaded.
.    IA32_SYSENTER_ESP (MSR address 175H) - The value of this MSR is loaded into RSP (thus, this value
     contains the stack pointer for the privilege level 0 stack). This value cannot represent a non-canonical address.
     In protected mode, only bits 31:0 are loaded.
These MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction ensures that the
IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs always contain canonical addresses.
While SYSENTER loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and
SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of
OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the
fixed values loaded into the descriptor caches; the SYSENTER instruction does not ensure this correspondence.
The SYSENTER instruction can be invoked from all operating modes except real-address mode.
The SYSENTER and SYSEXIT instructions are companion instructions, but they do not constitute a call/return pair.
When executing a SYSENTER instruction, the processor does not save state information for the user code (e.g., the
instruction pointer), and neither the SYSENTER nor the SYSEXIT instruction supports passing parameters on the
stack.
To use the SYSENTER and SYSEXIT instructions as companion instructions for transitions between privilege level 3
code and privilege level 0 operating system procedures, the following conventions must be followed:
.    The segment descriptors for the privilege level 0 code and stack segments and for the privilege level 3 code and
     stack segments must be contiguous in a descriptor table. This convention allows the processor to compute the
     segment selectors from the value entered in the SYSENTER_CS_MSR MSR.
.    The fast system call "stub" routines executed by user code (typically in shared libraries or DLLs) must save the
     required return IP and processor state information if a return to the calling procedure is required. Likewise, the
     operating system or executive procedures called with SYSENTER instructions must have access to and use this
     saved return and state information when returning to the user code.





The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.
The availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature
flag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must
also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually
present. For example:

IF CPUID SEP bit is set
    THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)
        THEN
             SYSENTER/SYSEXIT_Not_Supported; FI;
        ELSE
             SYSENTER/SYSEXIT_Supported; FI;
FI;
When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP
flag as set, but does not support the SYSENTER/SYSEXIT instructions.

Operation
IF CR0.PE = 0 OR IA32_SYSENTER_CS[15:2] = 0 THEN #GP(0); FI;

RFLAGS.VM <- 0;                           (* Ensures protected mode execution *)
RFLAGS.IF <- 0;                           (* Mask interrupts *)
IF in IA-32e mode
     THEN
          RSP <- IA32_SYSENTER_ESP;
          RIP <- IA32_SYSENTER_EIP;
ELSE
          ESP <- IA32_SYSENTER_ESP[31:0];
          EIP <- IA32_SYSENTER_EIP[31:0];
FI;

CS.Selector <- IA32_SYSENTER_CS[15:0] AND FFFCH;
                                        (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;                            (* Flat segment *)
CS.Limit <- FFFFFH;                      (* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type <- 11;                           (* Execute/read code, accessed *)
CS.S <- 1;
CS.DPL <- 0;
CS.P <- 1;
IF in IA-32e mode
     THEN
          CS.L <- 1;                     (* Entry is to 64-bit mode *)
          CS.D <- 0;                     (* Required if CS.L = 1 *)
     ELSE
          CS.L <- 0;
          CS.D <- 1;                     (* 32-bit code segment*)
FI;
CS.G <- 1;                               (* 4-KByte granularity *)
CPL <- 0;

SS.Selector <- CS.Selector + 8;                (* SS just above CS *)
(* Set rest of SS to a fixed value *)
SS.Base <- 0;                                  (* Flat segment *)
SS.Limit <- FFFFFH;                            (* With 4-KByte granularity, implies a 4-GByte limit *)
SS.Type <- 3;                                  (* Read/write data, accessed *)



SS.S <- 1;
SS.DPL <- 0;
SS.P <- 1;
SS.B <- 1;                              (* 32-bit stack segment*)
SS.G <- 1;                              (* 4-KByte granularity *)

Flags Affected
VM, IF (see Operation above)

Protected Mode Exceptions
#GP(0)              If IA32_SYSENTER_CS[15:2] = 0.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 The SYSENTER instruction is not recognized in real-address mode.
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: SYSEXIT
description:
SYSEXIT-Fast Return from Fast System Call
Opcode                     Instruction                  Op/   64-Bit   Compat/ Description
                                                        En    Mode     Leg Mode
0F 35                      SYSEXIT                      NP    Valid    Valid      Fast return to privilege level 3 user code.
REX.W + 0F 35              SYSEXIT                      NP    Valid    Valid      Fast return to 64-bit mode privilege level 3
                                                                                  user code.



                                                 Instruction Operand Encoding
    Op/En             Operand 1                     Operand 2                  Operand 3                      Operand 4
     NP                   NA                            NA                        NA                             NA


Description
Executes a fast return to privilege level 3 user code. SYSEXIT is a companion instruction to the SYSENTER instruc-
tion. The instruction is optimized to provide the maximum performance for returns from system procedures
executing at protections levels 0 to user procedures executing at protection level 3. It must be executed from code
executing at privilege level 0.
With a 64-bit operand size, SYSEXIT remains in 64-bit mode; otherwise, it either enters compatibility mode (if the
logical processor is in IA-32e mode) or remains in protected mode (if it is not).
Prior to executing SYSEXIT, software must specify the privilege level 3 code segment and code entry point, and the
privilege level 3 stack segment and stack pointer by writing values into the following MSR and general-purpose
registers:
.    IA32_SYSENTER_CS (MSR address 174H) - Contains a 32-bit value that is used to determine the segment
     selectors for the privilege level 3 code and stack segments (see the Operation section)
.    RDX - The canonical address in this register is loaded into RIP (thus, this value references the first instruction
     to be executed in the user code). If the return is not to 64-bit mode, only bits 31:0 are loaded.
.    ECX - The canonical address in this register is loaded into RSP (thus, this value contains the stack pointer for
     the privilege level 3 stack). If the return is not to 64-bit mode, only bits 31:0 are loaded.
The IA32_SYSENTER_CS MSR can be read from and written to using RDMSR and WRMSR.
While SYSEXIT loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS MSR, the CS and
SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors. Instead,
the descriptor caches are loaded with fixed values. See the Operation section for details. It is the responsibility of
OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values correspond to the
fixed values loaded into the descriptor caches; the SYSEXIT instruction does not ensure this correspondence.
The SYSEXIT instruction can be invoked from all operating modes except real-address mode and virtual-8086
mode.
The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture in the Pentium II processor.
The availability of these instructions on a processor is indicated with the SYSENTER/SYSEXIT present (SEP) feature
flag returned to the EDX register by the CPUID instruction. An operating system that qualifies the SEP flag must
also qualify the processor family and model to ensure that the SYSENTER/SYSEXIT instructions are actually
present. For example:

IF CPUID SEP bit is set
    THEN IF (Family = 6) and (Model < 3) and (Stepping < 3)
        THEN
             SYSENTER/SYSEXIT_Not_Supported; FI;
        ELSE
             SYSENTER/SYSEXIT_Supported; FI;
FI;
When the CPUID instruction is executed on the Pentium Pro processor (model 1), the processor returns a the SEP
flag as set, but does not support the SYSENTER/SYSEXIT instructions.



Operation
IF IA32_SYSENTER_CS[15:2] = 0 OR CR0.PE = 0 OR CPL != 0 THEN #GP(0); FI;

IF operand size is 64-bit
    THEN     (* Return to 64-bit mode *)
        RSP <- RCX;
        RIP <- RDX;
    ELSE     (* Return to protected mode or compatibility mode *)
        RSP <- ECX;
        RIP <- EDX;
FI;

IF operand size is 64-bit                      (* Operating system provides CS; RPL forced to 3 *)
    THEN CS.Selector <- IA32_SYSENTER_CS[15:0] + 32;
    ELSE CS.Selector <- IA32_SYSENTER_CS[15:0] + 16;
FI;
CS.Selector <- CS.Selector OR 3;                (* RPL forced to 3 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;                                   (* Flat segment *)
CS.Limit <- FFFFFH;                             (* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type <- 11;                                  (* Execute/read code, accessed *)
CS.S <- 1;
CS.DPL <- 3;
CS.P <- 1;
IF operand size is 64-bit
    THEN      (* return to 64-bit mode *)
         CS.L <- 1;                             (* 64-bit code segment *)
         CS.D <- 0;                             (* Required if CS.L = 1 *)
    ELSE      (* return to protected mode or compatibility mode *)
         CS.L <- 0;
         CS.D <- 1;                             (* 32-bit code segment*)
FI;
CS.G <- 1;                                      (* 4-KByte granularity *)
CPL <- 3;

SS.Selector <- CS.Selector + 8;                 (* SS just above CS *)
(* Set rest of SS to a fixed value *)
SS.Base <- 0;                                   (* Flat segment *)
SS.Limit <- FFFFFH;                             (* With 4-KByte granularity, implies a 4-GByte limit *)
SS.Type <- 3;                                   (* Read/write data, accessed *)
SS.S <- 1;
SS.DPL <- 3;
SS.P <- 1;
SS.B <- 1;                                      (* 32-bit stack segment*)
SS.G <- 1;                                      (* 4-KByte granularity *)

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                   If IA32_SYSENTER_CS[15:2] = 0.
                         If CPL   != 0.
#UD                      If the LOCK prefix is used.




Real-Address Mode Exceptions
#GP                      The SYSEXIT instruction is not recognized in real-address mode.
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   The SYSEXIT instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                   If IA32_SYSENTER_CS = 0.
                         If CPL   != 0.
                         If RCX or RDX contains a non-canonical address.
#UD                      If the LOCK prefix is used.






platform: x86_64
mnem: SYSRET
description:
SYSRET-Return From Fast System Call
Opcode                     Instruction                  Op/    64-Bit       Compat/ Description
                                                        En     Mode         Leg Mode
0F 07                      SYSRET                       NP     Valid        Invalid       Return to compatibility mode from fast
                                                                                          system call
REX.W + 0F 07              SYSRET                       NP     Valid        Invalid       Return to 64-bit mode from fast system call



                                                  Instruction Operand Encoding
    Op/En           Operand 1                      Operand 2                          Operand 3                    Operand 4
     NP                 NA                             NA                                NA                           NA


Description
SYSRET is a companion instruction to the SYSCALL instruction. It returns from an OS system-call handler to user
code at privilege level 3. It does so by loading RIP from RCX and loading RFLAGS from R11.1 With a 64-bit operand
size, SYSRET remains in 64-bit mode; otherwise, it enters compatibility mode and only the low 32 bits of the regis-
ters are loaded.
SYSRET loads the CS and SS selectors with values derived from bits 63:48 of the IA32_STAR MSR. However, the
CS and SS descriptor caches are not loaded from the descriptors (in GDT or LDT) referenced by those selectors.
Instead, the descriptor caches are loaded with fixed values. See the Operation section for details. It is the respon-
sibility of OS software to ensure that the descriptors (in GDT or LDT) referenced by those selector values corre-
spond to the fixed values loaded into the descriptor caches; the SYSRET instruction does not ensure this
correspondence.
The SYSRET instruction does not modify the stack pointer (ESP or RSP). For that reason, it is necessary for software
to switch to the user stack. The OS may load the user stack pointer (if it was saved after SYSCALL) before executing
SYSRET; alternatively, user code may load the stack pointer (if it was saved before SYSCALL) after receiving control
from SYSRET.
If the OS loads the stack pointer before executing SYSRET, it must ensure that the handler of any interrupt or
exception delivered between restoring the stack pointer and successful execution of SYSRET is not invoked with the
user stack. It can do so using approaches such as the following:
.    External interrupts. The OS can prevent an external interrupt from being delivered by clearing EFLAGS.IF
     before loading the user stack pointer.
.    Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked with the correct stack by
     using the interrupt stack table (IST) mechanism for gate 2 (NMI) in the IDT (see Section 6.14.5, "Interrupt
     Stack Table," in Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A).
.    General-protection exceptions (#GP). The SYSRET instruction generates #GP(0) if the value of RCX is not
     canonical. The OS can address this possibility using one or more of the following approaches:
     - Confirming that the value of RCX is canonical before executing SYSRET.
     - Using paging to ensure that the SYSCALL instruction will never save a non-canonical value into RCX.
     - Using the IST mechanism for gate 13 (#GP) in the IDT.

Operation
IF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
    THEN #UD; FI;
IF (CPL != 0) OR (RCX is not canonical) THEN #GP(0); FI;



1. Regardless of the value of R11, the RF and VM flags are always 0 in RFLAGS after execution of SYSRET. In addition, all reserved bits
   in RFLAGS retain the fixed values.



IF (operand size is 64-bit)
    THEN (* Return to 64-Bit Mode *)
         RIP <- RCX;
    ELSE (* Return to Compatibility Mode *)
         RIP <- ECX;
FI;
RFLAGS <- (R11 & 3C7FD7H) | 2;                 (* Clear RF, VM, reserved bits; set bit 2 *)

IF (operand size is 64-bit)
    THEN CS.Selector <- IA32_STAR[63:48]+16;
    ELSE CS.Selector <- IA32_STAR[63:48];
FI;
CS.Selector <- CS.Selector OR 3;             (* RPL forced to 3 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;                                (* Flat segment *)
CS.Limit <- FFFFFH;                          (* With 4-KByte granularity, implies a 4-GByte limit *)
CS.Type <- 11;                               (* Execute/read code, accessed *)
CS.S <- 1;
CS.DPL <- 3;
CS.P <- 1;
IF (operand size is 64-bit)
    THEN (* Return to 64-Bit Mode *)
         CS.L <- 1;                          (* 64-bit code segment *)
         CS.D <- 0;                          (* Required if CS.L = 1 *)
    ELSE (* Return to Compatibility Mode *)
         CS.L <- 0;                          (* Compatibility mode *)
         CS.D <- 1;                          (* 32-bit code segment *)
FI;
CS.G <- 1;                                   (* 4-KByte granularity *)
CPL <- 3;

SS.Selector <- (IA32_STAR[63:48]+8) OR 3;      (* RPL forced to 3 *)
(* Set rest of SS to a fixed value *)
SS.Base <- 0;                                  (* Flat segment *)
SS.Limit <- FFFFFH;                            (* With 4-KByte granularity, implies a 4-GByte limit *)
SS.Type <- 3;                                  (* Read/write data, accessed *)
SS.S <- 1;
SS.DPL <- 3;
SS.P <- 1;
SS.B <- 1;                                     (* 32-bit stack segment*)
SS.G <- 1;                                     (* 4-KByte granularity *)

Flags Affected
All.

Protected Mode Exceptions
#UD                     The SYSRET instruction is not recognized in protected mode.

Real-Address Mode Exceptions
#UD                     The SYSRET instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                     The SYSRET instruction is not recognized in virtual-8086 mode.



Compatibility Mode Exceptions
#UD                 The SYSRET instruction is not recognized in compatibility mode.

64-Bit Mode Exceptions
#UD                 If IA32_EFER.SCE = 0.
                    If the LOCK prefix is used.
#GP(0)              If CPL   != 0.
                    If RCX contains a non-canonical address.






platform: x86_64
mnem: TEST
description:
TEST-Logical Compare
 Opcode                   Instruction                  Op/    64-Bit       Compat/ Description
                                                       En     Mode         Leg Mode
 A8 ib                    TEST AL, imm8                 I     Valid        Valid       AND imm8 with AL; set SF, ZF, PF according to
                                                                                       result.
 A9 iw                    TEST AX, imm16                I     Valid        Valid       AND imm16 with AX; set SF, ZF, PF according
                                                                                       to result.
 A9 id                    TEST EAX, imm32               I     Valid        Valid       AND imm32 with EAX; set SF, ZF, PF according
                                                                                       to result.
 REX.W + A9 id            TEST RAX, imm32               I     Valid        N.E.        AND imm32 sign-extended to 64-bits with
                                                                                       RAX; set SF, ZF, PF according to result.
 F6 /0 ib                 TEST r/m8, imm8               MI    Valid        Valid       AND imm8 with r/m8; set SF, ZF, PF according
                                                                                       to result.
 REX + F6 /0 ib           TEST r/m8*, imm8              MI    Valid        N.E.        AND imm8 with r/m8; set SF, ZF, PF according
                                                                                       to result.
 F7 /0 iw                 TEST r/m16, imm16             MI    Valid        Valid       AND imm16 with r/m16; set SF, ZF, PF
                                                                                       according to result.
 F7 /0 id                 TEST r/m32, imm32             MI    Valid        Valid       AND imm32 with r/m32; set SF, ZF, PF
                                                                                       according to result.
 REX.W + F7 /0 id         TEST r/m64, imm32             MI    Valid        N.E.        AND imm32 sign-extended to 64-bits with
                                                                                       r/m64; set SF, ZF, PF according to result.
 84 /r                    TEST r/m8, r8                 MR    Valid        Valid       AND r8 with r/m8; set SF, ZF, PF according to
                                                                                       result.
 REX + 84 /r              TEST r/m8*, r8*               MR    Valid        N.E.        AND r8 with r/m8; set SF, ZF, PF according to
                                                                                       result.
 85 /r                    TEST r/m16, r16               MR    Valid        Valid       AND r16 with r/m16; set SF, ZF, PF according
                                                                                       to result.
 85 /r                    TEST r/m32, r32               MR    Valid        Valid       AND r32 with r/m32; set SF, ZF, PF according
                                                                                       to result.
 REX.W + 85 /r            TEST r/m64, r64               MR    Valid        N.E.        AND r64 with r/m64; set SF, ZF, PF according
                                                                                       to result.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                    Operand 2                      Operand 3                      Operand 4
         I          AL/AX/EAX/RAX                  imm8/16/32                          NA                             NA
     MI             ModRM:r/m (r)                  imm8/16/32                          NA                             NA
    MR              ModRM:r/m (r)                 ModRM:reg (r)                        NA                             NA


Description
Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand)
and sets the SF, ZF, and PF status flags according to the result. The result is then discarded.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a
REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.





Operation
TEMP <- SRC1 AND SRC2;
SF <- MSB(TEMP);

IF TEMP = 0
    THEN ZF <- 1;
    ELSE ZF <- 0;
FI:

PF <- BitwiseXNOR(TEMP[0:7]);
CF <- 0;
OF <- 0;
(* AF is undefined *)

Flags Affected
The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according to the result (see the "Operation" section
above). The state of the AF flag is undefined.

Protected Mode Exceptions
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                  If a memory operand effective address is outside the SS segment limit.
#UD                  If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.
#UD                  If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the memory address is in a non-canonical form.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.





platform: x86_64
mnem: TZCNT
description:
TZCNT - Count the Number of Trailing Zero Bits
 Opcode/                           Op/    64/32    CPUID     Description
 Instruction                       En     -bit     Feature
                                          Mode     Flag
 F3 0F BC /r                       RM     V/V      BMI1      Count the number of trailing zero bits in r/m16, return result in r16.
 TZCNT r16, r/m16
 F3 0F BC /r                       RM     V/V      BMI1      Count the number of trailing zero bits in r/m32, return result in r32.
 TZCNT r32, r/m32
 F3 REX.W 0F BC /r                 RM     V/N.E.   BMI1      Count the number of trailing zero bits in r/m64, return result in r64.
 TZCNT r64, r/m64



                                                   Instruction Operand Encoding
     Op/En             Operand 1                    Operand 2                     Operand 3                       Operand 4
      A              ModRM:reg (w)                 ModRM:r/m (r)                     NA                               NA


Description
TZCNT counts the number of trailing least significant zero bits in source operand (second operand) and returns the
result in destination operand (first operand). TZCNT is an extension of the BSF instruction. The key difference
between TZCNT and BSF instruction is that TZCNT provides operand size as output when source operand is zero
while in the case of BSF instruction, if source operand is zero, the content of destination operand are undefined. On
processors that do not support TZCNT, the instruction byte encoding is executed as BSF.

Operation
temp <- 0
DEST <- 0
DO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )

     temp <- temp +1
     DEST <- DEST+ 1
OD

IF DEST = OperandSize
    CF <- 1
ELSE
    CF <- 0
FI

IF DEST = 0
    ZF <- 1
ELSE
    ZF <- 0
FI

Flags Affected
ZF is set to 1 in case of zero output (least significant bit of the source is set), and to 0 otherwise, CF is set to 1 if
the input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.

Intel C/C++ Compiler Intrinsic Equivalent
TZCNT:        unsigned __int32 _tzcnt_u32(unsigned __int32 src);
TZCNT:        unsigned __int64 _tzcnt_u64(unsigned __int64 src);



Protected Mode Exceptions
#GP(0)              For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
                    If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
                    selector.
#SS(0)              For an illegal address in the SS segment.
#PF (fault-code)    For a page fault.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.

Real-Address Mode Exceptions
#GP(0)              If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)              For an illegal address in the SS segment.

Virtual 8086 Mode Exceptions
#GP(0)              If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)              For an illegal address in the SS segment.
#PF (fault-code)    For a page fault.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.

Compatibility Mode Exceptions
Same exceptions as in Protected Mode.

64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)    For a page fault.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.






platform: x86_64
mnem: UCOMISD
description:
UCOMISD-Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS
 Opcode/                                   Op /   64/32        CPUID         Description
 Instruction                               En     bit Mode     Feature
                                                  Support      Flag
 66 0F 2E /r                               RM     V/V          SSE2          Compare low double-precision floating-point values in
 UCOMISD xmm1, xmm2/m64                                                      xmm1 and xmm2/mem64 and set the EFLAGS flags
                                                                             accordingly.
 VEX.128.66.0F.WIG 2E /r                   RM     V/V          AVX           Compare low double-precision floating-point values in
 VUCOMISD xmm1, xmm2/m64                                                     xmm1 and xmm2/mem64 and set the EFLAGS flags
                                                                             accordingly.
 EVEX.LIG.66.0F.W1 2E /r                   T1S    V/V          AVX512F       Compare low double-precision floating-point values in
 VUCOMISD xmm1, xmm2/m64{sae}                                                xmm1 and xmm2/m64 and set the EFLAGS flags
                                                                             accordingly.



                                                   Instruction Operand Encoding
      Op/En                 Operand 1                     Operand 2                      Operand 3                  Operand 4
        RM                 ModRM:reg (r)                ModRM:r/m (r)                       NA                          NA
       T1S                ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA

Description
Performs an unordered compare of the double-precision floating-point values in the low quadwords of operand 1
(first operand) and operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according
to the result (unordered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set
to 0. The unordered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 64 bit memory
location.
The UCOMISD instruction differs from the COMISD instruction in that it signals a SIMD floating-point invalid oper-
ation exception (#I) only when a source operand is an SNaN. The COMISD instruction signals an invalid numeric
exception only if a source operand is either an SNaN or a QNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISD is encoded with VEX.L=0. Encoding VCOMISD with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
(V)UCOMISD (all versions)
RESULT <- UnorderedCompare(DEST[63:0] <> SRC[63:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
    UNORDERED: ZF,PF,CF <- 111;
    GREATER_THAN: ZF,PF,CF <- 000;
    LESS_THAN: ZF,PF,CF <- 001;
    EQUAL: ZF,PF,CF <- 100;
ESAC;
OF, AF, SF <- 0; }





Intel C/C++ Compiler Intrinsic Equivalent
VUCOMISD int _mm_comi_round_sd(__m128d a, __m128d b, int imm, int sae);
UCOMISD int _mm_ucomieq_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomilt_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomile_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomigt_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomige_sd(__m128d a, __m128d b)
UCOMISD int _mm_ucomineq_sd(__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Invalid (if SNaN operands), Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD                    If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: UCOMISS
description:
UCOMISS-Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS
 Opcode/                                    Op /   64/32         CPUID        Description
 Instruction                                En     bit Mode      Feature
                                                   Support       Flag
 0F 2E /r                                   RM     V/V           SSE          Compare low single-precision floating-point values in
 UCOMISS xmm1, xmm2/m32                                                       xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                              accordingly.
 VEX.128.0F.WIG 2E /r                       RM     V/V           AVX          Compare low single-precision floating-point values in
 VUCOMISS xmm1, xmm2/m32                                                      xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                              accordingly.
 EVEX.LIG.0F.W0 2E /r                       T1S    V/V           AVX512F      Compare low single-precision floating-point values in
 VUCOMISS xmm1, xmm2/m32{sae}                                                 xmm1 and xmm2/mem32 and set the EFLAGS flags
                                                                              accordingly.



                                                    Instruction Operand Encoding
       Op/En                  Operand 1                     Operand 2                    Operand 3                    Operand 4
        RM                  ModRM:reg (r)                 ModRM:r/m (r)                     NA                           NA
        T1S                ModRM:reg (w)                  ModRM:r/m (r)                     NA                           NA

Description
Compares the single-precision floating-point values in the low doublewords of operand 1 (first operand) and
operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register according to the result (unor-
dered, greater than, less than, or equal). The OF, SF and AF flags in the EFLAGS register are set to 0. The unor-
dered result is returned if either source operand is a NaN (QNaN or SNaN).
Operand 1 is an XMM register; operand 2 can be an XMM register or a 32 bit memory location.
The UCOMISS instruction differs from the COMISS instruction in that it signals a SIMD floating-point invalid opera-
tion exception (#I) only if a source operand is an SNaN. The COMISS instruction signals an invalid numeric excep-
tion when a source operand is either a QNaN or SNaN.
The EFLAGS register is not updated if an unmasked SIMD floating-point exception is generated.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCOMISS is encoded with VEX.L=0. Encoding VCOMISS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
(V)UCOMISS (all versions)
RESULT <- UnorderedCompare(DEST[31:0] <> SRC[31:0]) {
(* Set EFLAGS *) CASE (RESULT) OF
    UNORDERED: ZF,PF,CF <- 111;
    GREATER_THAN: ZF,PF,CF <- 000;
    LESS_THAN: ZF,PF,CF <- 001;
    EQUAL: ZF,PF,CF <- 100;
ESAC;
OF, AF, SF <- 0; }





Intel C/C++ Compiler Intrinsic Equivalent
VUCOMISS    int _mm_comi_round_ss(__m128 a, __m128 b, int imm, int sae);
UCOMISS     int _mm_ucomieq_ss(__m128 a, __m128 b);
UCOMISS     int _mm_ucomilt_ss(__m128 a, __m128 b);
UCOMISS     int _mm_ucomile_ss(__m128 a, __m128 b);
UCOMISS     int _mm_ucomigt_ss(__m128 a, __m128 b);
UCOMISS     int _mm_ucomige_ss(__m128 a, __m128 b);
UCOMISS     int _mm_ucomineq_ss(__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Invalid (if SNaN Operands), Denormal

Other Exceptions
VEX-encoded instructions, see Exceptions Type 3; additionally
#UD                    If VEX.vvvv != 1111B.
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: UD2
description:
UD2-Undefined Instruction
 Opcode                     Instruction             Op/   64-Bit    Compat/ Description
                                                    En    Mode      Leg Mode
 0F 0B                      UD2                     NP    Valid     Valid       Raise invalid opcode exception.



                                                Instruction Operand Encoding
   Op/En              Operand 1                  Operand 2                  Operand 3                     Operand 4
    NP                      NA                      NA                         NA                            NA


Description
Generates an invalid opcode exception. This instruction is provided for software testing to explicitly generate an
invalid opcode exception. The opcode for this instruction is reserved for this purpose.
Other than raising the invalid opcode exception, this instruction has no effect on processor state or memory.
Even though it is the execution of the UD2 instruction that causes the invalid opcode exception, the instruction
pointer saved by delivery of the exception references the UD2 instruction (and not the following instruction).
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
#UD (* Generates invalid opcode exception *);

Flags Affected
None.

Exceptions (All Operating Modes)
#UD                     Raises an invalid opcode exception in all operating modes.






platform: x86_64
mnem: UNPCKHPD
description:
UNPCKHPD-Unpack and Interleave High Packed Double-Precision Floating-Point Values
 Opcode/                               Op /   64/32         CPUID          Description
 Instruction                           En     bit Mode      Feature
                                              Support       Flag
 66 0F 15 /r                                  V/V           SSE2           Unpacks and Interleaves double-precision floating-point
 UNPCKHPD xmm1, xmm2/m128              RM                                  values from high quadwords of xmm1 and
                                                                           xmm2/m128.
 VEX.NDS.128.66.0F.WIG 15 /r                  V/V           AVX            Unpacks and Interleaves double-precision floating-point
 VUNPCKHPD xmm1,xmm2,                  RVM                                 values from high quadwords of xmm2 and
 xmm3/m128                                                                 xmm3/m128.
 VEX.NDS.256.66.0F.WIG 15 /r           RVM    V/V           AVX            Unpacks and Interleaves double-precision floating-point
 VUNPCKHPD ymm1,ymm2,                                                      values from high quadwords of ymm2 and
 ymm3/m256                                                                 ymm3/m256.
 EVEX.NDS.128.66.0F.W1 15 /r           FV     V/V           AVX512VL       Unpacks and Interleaves double precision floating-point
 VUNPCKHPD xmm1 {k1}{z}, xmm2,                              AVX512F        values from high quadwords of xmm2 and
 xmm3/m128/m64bcst                                                         xmm3/m128/m64bcst subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 15 /r           FV     V/V           AVX512VL       Unpacks and Interleaves double precision floating-point
 VUNPCKHPD ymm1 {k1}{z}, ymm2,                              AVX512F        values from high quadwords of ymm2 and
 ymm3/m256/m64bcst                                                         ymm3/m256/m64bcst subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 15 /r           FV     V/V           AVX512F        Unpacks and Interleaves double-precision floating-point
 VUNPCKHPD zmm1 {k1}{z}, zmm2,                                             values from high quadwords of zmm2 and
 zmm3/m512/m64bcst                                                         zmm3/m512/m64bcst subject to writemask k1.



                                              Instruction Operand Encoding
      Op/En            Operand 1                     Operand 2                    Operand 3                      Operand 4
       RM           ModRM:reg (r, w)                ModRM:r/m (r)                     NA                             NA
      RVM            ModRM:reg (w)                  VEX.vvvv (r)                ModRM:r/m (r)                        NA
       FV            ModRM:reg (w)                  EVEX.vvvv (r)               ModRM:r/m (r)                        NA

Description
Performs an interleaved unpack of the high double-precision floating-point values from the first source operand and
the second source operand. See Figure 4-15 in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 2B.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1.



Operation
VUNPCKHPD (EVEX encoded versions when SRC2 is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL >= 128
    TMP_DEST[63:0] <- SRC1[127:64]
    TMP_DEST[127:64] <- SRC2[127:64]
FI;
IF VL >= 256
    TMP_DEST[191:128] <- SRC1[255:192]
    TMP_DEST[255:192] <- SRC2[255:192]
FI;
IF VL >= 512
    TMP_DEST[319:256] <- SRC1[383:320]
    TMP_DEST[383:320] <- SRC2[383:320]
    TMP_DEST[447:384] <- SRC1[511:448]
    TMP_DEST[511:448] <- SRC2[511:448]
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VUNPCKHPD (EVEX encoded version when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL >= 128
    TMP_DEST[63:0] <- SRC1[127:64]
    TMP_DEST[127:64] <- TMP_SRC2[127:64]
FI;
IF VL >= 256
    TMP_DEST[191:128] <- SRC1[255:192]
    TMP_DEST[255:192] <- TMP_SRC2[255:192]
FI;
IF VL >= 512
    TMP_DEST[319:256] <- SRC1[383:320]
    TMP_DEST[383:320] <- TMP_SRC2[383:320]
    TMP_DEST[447:384] <- SRC1[511:448]
    TMP_DEST[511:448] <- TMP_SRC2[511:448]
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VUNPCKHPD (VEX.256 encoded version)
DEST[63:0] <-SRC1[127:64]
DEST[127:64] <-SRC2[127:64]
DEST[191:128]<-SRC1[255:192]
DEST[255:192]<-SRC2[255:192]
DEST[MAX_VL-1:256] <-0

VUNPCKHPD (VEX.128 encoded version)
DEST[63:0] <-SRC1[127:64]
DEST[127:64] <-SRC2[127:64]
DEST[MAX_VL-1:128] <-0

UNPCKHPD (128-bit Legacy SSE version)
DEST[63:0] <-SRC1[127:64]
DEST[127:64] <-SRC2[127:64]
DEST[MAX_VL-1:128] (Unmodified)



Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKHPD __m512d _mm512_unpackhi_pd( __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_mask_unpackhi_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m512d _mm512_maskz_unpackhi_pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKHPD __m256d _mm256_unpackhi_pd(__m256d a, __m256d b)
VUNPCKHPD __m256d _mm256_mask_unpackhi_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKHPD __m256d _mm256_maskz_unpackhi_pd(__mmask8 k, __m256d a, __m256d b);
UNPCKHPD __m128d _mm_unpackhi_pd(__m128d a, __m128d b)
VUNPCKHPD __m128d _mm_mask_unpackhi_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKHPD __m128d _mm_maskz_unpackhi_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.






platform: x86_64
mnem: UNPCKHPS
description:
UNPCKHPS-Unpack and Interleave High Packed Single-Precision Floating-Point Values
 Opcode/                            Op /   64/32         CPUID          Description
 Instruction                        En     bit Mode      Feature
                                           Support       Flag
 0F 15 /r                                  V/V           SSE            Unpacks and Interleaves single-precision floating-point
                                    RM
 UNPCKHPS xmm1, xmm2/m128                                               values from high quadwords of xmm1 and xmm2/m128.
 VEX.NDS.128.0F.WIG 15 /r                  V/V           AVX            Unpacks and Interleaves single-precision floating-point
 VUNPCKHPS xmm1, xmm2,              RVM                                 values from high quadwords of xmm2 and xmm3/m128.
 xmm3/m128
 VEX.NDS.256.0F.WIG 15 /r           RVM    V/V           AVX            Unpacks and Interleaves single-precision floating-point
 VUNPCKHPS ymm1, ymm2,                                                  values from high quadwords of ymm2 and ymm3/m256.
 ymm3/m256
 EVEX.NDS.128.0F.W0 15 /r           FV     V/V           AVX512VL       Unpacks and Interleaves single-precision floating-point
 VUNPCKHPS xmm1 {k1}{z}, xmm2,                           AVX512F        values from high quadwords of xmm2 and
 xmm3/m128/m32bcst                                                      xmm3/m128/m32bcst and write result to xmm1 subject to
                                                                        writemask k1.
 EVEX.NDS.256.0F.W0 15 /r           FV     V/V           AVX512VL       Unpacks and Interleaves single-precision floating-point
 VUNPCKHPS ymm1 {k1}{z}, ymm2,                           AVX512F        values from high quadwords of ymm2 and
 ymm3/m256/m32bcst                                                      ymm3/m256/m32bcst and write result to ymm1 subject to
                                                                        writemask k1.
 EVEX.NDS.512.0F.W0 15 /r           FV     V/V           AVX512F        Unpacks and Interleaves single-precision floating-point
 VUNPCKHPS zmm1 {k1}{z}, zmm2,                                          values from high quadwords of zmm2 and
 zmm3/m512/m32bcst                                                      zmm3/m512/m32bcst and write result to zmm1 subject to
                                                                        writemask k1.



                                             Instruction Operand Encoding
      Op/En             Operand 1                     Operand 2                     Operand 3                     Operand 4
       RM            ModRM:reg (r, w)            ModRM:r/m (r)                          NA                            NA
       RVM           ModRM:reg (w)                VEX.vvvv (r)                    ModRM:r/m (r)                       NA
        FV           ModRM:reg (w)               EVEX.vvvv (r)                    ModRM:r/m (r)                       NA

Description
Performs an interleaved unpack of the high single-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers.





                          SRC1     X7         X6        X5        X4         X3     X2   X1     X0


                          SRC2     Y7         Y6        Y5        Y4         Y3     Y2   Y1     Y0




                          DEST     Y7         X7        Y6        X6         Y3     X3   Y2     X2




                                                Figure 4-27. VUNPCKHPS Operation


EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is a XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1.

Operation
VUNPCKHPS (EVEX encoded version when SRC2 is a register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL >= 128
    TMP_DEST[31:0] <- SRC1[95:64]
    TMP_DEST[63:32] <- SRC2[95:64]
    TMP_DEST[95:64] <- SRC1[127:96]
    TMP_DEST[127:96] <- SRC2[127:96]
FI;
IF VL >= 256
    TMP_DEST[159:128] <- SRC1[223:192]
    TMP_DEST[191:160] <- SRC2[223:192]
    TMP_DEST[223:192] <- SRC1[255:224]
    TMP_DEST[255:224] <- SRC2[255:224]
FI;
IF VL >= 512
    TMP_DEST[287:256] <- SRC1[351:320]
    TMP_DEST[319:288] <- SRC2[351:320]
    TMP_DEST[351:320] <- SRC1[383:352]
    TMP_DEST[383:352] <- SRC2[383:352]
    TMP_DEST[415:384] <- SRC1[479:448]
    TMP_DEST[447:416] <- SRC2[479:448]
    TMP_DEST[479:448] <- SRC1[511:480]
    TMP_DEST[511:480] <- SRC2[511:480]
FI;





FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VUNPCKHPS (EVEX encoded version when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL >= 128
    TMP_DEST[31:0] <- SRC1[95:64]
    TMP_DEST[63:32] <- TMP_SRC2[95:64]
    TMP_DEST[95:64] <- SRC1[127:96]
    TMP_DEST[127:96] <- TMP_SRC2[127:96]
FI;
IF VL >= 256
    TMP_DEST[159:128] <- SRC1[223:192]
    TMP_DEST[191:160] <- TMP_SRC2[223:192]
    TMP_DEST[223:192] <- SRC1[255:224]
    TMP_DEST[255:224] <- TMP_SRC2[255:224]
FI;
IF VL >= 512
    TMP_DEST[287:256] <- SRC1[351:320]
    TMP_DEST[319:288] <- TMP_SRC2[351:320]
    TMP_DEST[351:320] <- SRC1[383:352]
    TMP_DEST[383:352] <- TMP_SRC2[383:352]
    TMP_DEST[415:384] <- SRC1[479:448]
    TMP_DEST[447:416] <- TMP_SRC2[479:448]
    TMP_DEST[479:448] <- SRC1[511:480]
    TMP_DEST[511:480] <- TMP_SRC2[511:480]
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0



          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VUNPCKHPS (VEX.256 encoded version)
DEST[31:0] <-SRC1[95:64]
DEST[63:32] <-SRC2[95:64]
DEST[95:64] <-SRC1[127:96]
DEST[127:96] <-SRC2[127:96]
DEST[159:128] <-SRC1[223:192]
DEST[191:160] <-SRC2[223:192]
DEST[223:192] <-SRC1[255:224]
DEST[255:224] <-SRC2[255:224]
DEST[MAX_VL-1:256] <- 0

VUNPCKHPS (VEX.128 encoded version)
DEST[31:0] <-SRC1[95:64]
DEST[63:32] <-SRC2[95:64]
DEST[95:64] <-SRC1[127:96]
DEST[127:96] <-SRC2[127:96]
DEST[MAX_VL-1:128] <-0

UNPCKHPS (128-bit Legacy SSE version)
DEST[31:0] <-SRC1[95:64]
DEST[63:32] <-SRC2[95:64]
DEST[95:64] <-SRC1[127:96]
DEST[127:96] <-SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKHPS __m512 _mm512_unpackhi_ps( __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_mask_unpackhi_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m512 _mm512_maskz_unpackhi_ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKHPS __m256 _mm256_unpackhi_ps (__m256 a, __m256 b);
VUNPCKHPS __m256 _mm256_mask_unpackhi_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VUNPCKHPS __m256 _mm256_maskz_unpackhi_ps(__mmask8 k, __m256 a, __m256 b);
UNPCKHPS __m128 _mm_unpackhi_ps (__m128 a, __m128 b);
VUNPCKHPS __m128 _mm_mask_unpackhi_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKHPS __m128 _mm_maskz_unpackhi_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.






platform: x86_64
mnem: UNPCKLPD
description:
UNPCKLPD-Unpack and Interleave Low Packed Double-Precision Floating-Point Values
 Opcode/                           Op /   64/32        CPUID           Description
 Instruction                       En     bit Mode     Feature
                                          Support      Flag
 66 0F 14 /r                              V/V          SSE2            Unpacks and Interleaves double-precision floating-point
                                   RM
 UNPCKLPD xmm1, xmm2/m128                                              values from low quadwords of xmm1 and xmm2/m128.
 VEX.NDS.128.66.0F.WIG 14 /r              V/V          AVX             Unpacks and Interleaves double-precision floating-point
 VUNPCKLPD xmm1,xmm2,              RVM                                 values from low quadwords of xmm2 and xmm3/m128.
 xmm3/m128
 VEX.NDS.256.66.0F.WIG 14 /r       RVM    V/V          AVX             Unpacks and Interleaves double-precision floating-point
 VUNPCKLPD ymm1,ymm2,                                                  values from low quadwords of ymm2 and ymm3/m256.
 ymm3/m256
 EVEX.NDS.128.66.0F.W1 14 /r       FV     V/V          AVX512VL        Unpacks and Interleaves double precision floating-point
 VUNPCKLPD xmm1 {k1}{z}, xmm2,                         AVX512F         values from low quadwords of xmm2 and
 xmm3/m128/m64bcst                                                     xmm3/m128/m64bcst subject to write mask k1.
 EVEX.NDS.256.66.0F.W1 14 /r       FV     V/V          AVX512VL        Unpacks and Interleaves double precision floating-point
 VUNPCKLPD ymm1 {k1}{z}, ymm2,                         AVX512F         values from low quadwords of ymm2 and
 ymm3/m256/m64bcst                                                     ymm3/m256/m64bcst subject to write mask k1.
 EVEX.NDS.512.66.0F.W1 14 /r       FV     V/V          AVX512F         Unpacks and Interleaves double-precision floating-point
 VUNPCKLPD zmm1 {k1}{z}, zmm2,                                         values from low quadwords of zmm2 and
 zmm3/m512/m64bcst                                                     zmm3/m512/m64bcst subject to write mask k1.



                                            Instruction Operand Encoding
      Op/En            Operand 1                 Operand 2                       Operand 3                     Operand 4
       RM           ModRM:reg (r, w)            ModRM:r/m (r)                        NA                            NA
       RVM           ModRM:reg (w)               VEX.vvvv (r)                  ModRM:r/m (r)                       NA
        FV           ModRM:reg (w)              EVEX.vvvv (r)                  ModRM:r/m (r)                       NA

Description
Performs an interleaved unpack of the low double-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 64-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1.





Operation
VUNPCKLPD (EVEX encoded versions when SRC2 is a register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL >= 128
    TMP_DEST[63:0] <- SRC1[63:0]
    TMP_DEST[127:64] <- SRC2[63:0]
FI;
IF VL >= 256
    TMP_DEST[191:128] <- SRC1[191:128]
    TMP_DEST[255:192] <- SRC2[191:128]
FI;
IF VL >= 512
    TMP_DEST[319:256] <- SRC1[319:256]
    TMP_DEST[383:320] <- SRC2[319:256]
    TMP_DEST[447:384] <- SRC1[447:384]
    TMP_DEST[511:448] <- SRC2[447:384]
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VUNPCKLPD (EVEX encoded version when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL >= 128
    TMP_DEST[63:0] <- SRC1[63:0]
    TMP_DEST[127:64] <- TMP_SRC2[63:0]
FI;
IF VL >= 256
    TMP_DEST[191:128] <- SRC1[191:128]
    TMP_DEST[255:192] <- TMP_SRC2[191:128]
FI;
IF VL >= 512
    TMP_DEST[319:256] <- SRC1[319:256]
    TMP_DEST[383:320] <- TMP_SRC2[319:256]
    TMP_DEST[447:384] <- SRC1[447:384]
    TMP_DEST[511:448] <- TMP_SRC2[447:384]
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VUNPCKLPD (VEX.256 encoded version)
DEST[63:0] <-SRC1[63:0]
DEST[127:64] <-SRC2[63:0]
DEST[191:128] <-SRC1[191:128]
DEST[255:192] <-SRC2[191:128]
DEST[MAX_VL-1:256] <- 0

VUNPCKLPD (VEX.128 encoded version)
DEST[63:0] <-SRC1[63:0]
DEST[127:64] <-SRC2[63:0]
DEST[MAX_VL-1:128] <-0

UNPCKLPD (128-bit Legacy SSE version)
DEST[63:0] <-SRC1[63:0]
DEST[127:64] <-SRC2[63:0]
DEST[MAX_VL-1:128] (Unmodified)




Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKLPD __m512d _mm512_unpacklo_pd( __m512d a, __m512d b);
VUNPCKLPD __m512d _mm512_mask_unpacklo_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m512d _mm512_maskz_unpacklo_pd(__mmask8 k, __m512d a, __m512d b);
VUNPCKLPD __m256d _mm256_unpacklo_pd(__m256d a, __m256d b)
VUNPCKLPD __m256d _mm256_mask_unpacklo_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VUNPCKLPD __m256d _mm256_maskz_unpacklo_pd(__mmask8 k, __m256d a, __m256d b);
UNPCKLPD __m128d _mm_unpacklo_pd(__m128d a, __m128d b)
VUNPCKLPD __m128d _mm_mask_unpacklo_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VUNPCKLPD __m128d _mm_maskz_unpacklo_pd(__mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.






platform: x86_64
mnem: UNPCKLPS
description:
UNPCKLPS-Unpack and Interleave Low Packed Single-Precision Floating-Point Values
 Opcode/                            Op /   64/32        CPUID           Description
 Instruction                        En     bit Mode     Feature
                                           Support      Flag
 0F 14 /r                                  V/V          SSE             Unpacks and Interleaves single-precision floating-point
                                    RM
 UNPCKLPS xmm1, xmm2/m128                                               values from low quadwords of xmm1 and xmm2/m128.
 VEX.NDS.128.0F.WIG 14 /r                  V/V          AVX             Unpacks and Interleaves single-precision floating-point
 VUNPCKLPS xmm1,xmm2,               RVM                                 values from low quadwords of xmm2 and xmm3/m128.
 xmm3/m128
 VEX.NDS.256.0F.WIG 14 /r           RVM    V/V          AVX             Unpacks and Interleaves single-precision floating-point
 VUNPCKLPS                                                              values from low quadwords of ymm2 and ymm3/m256.
 ymm1,ymm2,ymm3/m256
 EVEX.NDS.128.0F.W0 14 /r           FV     V/V          AVX512VL        Unpacks and Interleaves single-precision floating-point
 VUNPCKLPS xmm1 {k1}{z}, xmm2,                          AVX512F         values from low quadwords of xmm2 and xmm3/mem and
 xmm3/m128/m32bcst                                                      write result to xmm1 subject to write mask k1.
 EVEX.NDS.256.0F.W0 14 /r           FV     V/V          AVX512VL        Unpacks and Interleaves single-precision floating-point
 VUNPCKLPS ymm1 {k1}{z}, ymm2,                          AVX512F         values from low quadwords of ymm2 and ymm3/mem and
 ymm3/m256/m32bcst                                                      write result to ymm1 subject to write mask k1.
 EVEX.NDS.512.0F.W0 14 /r           FV     V/V          AVX512F         Unpacks and Interleaves single-precision floating-point
 VUNPCKLPS zmm1 {k1}{z}, zmm2,                                          values from low quadwords of zmm2 and
 zmm3/m512/m32bcst                                                      zmm3/m512/m32bcst and write result to zmm1 subject
                                                                        to write mask k1.



                                             Instruction Operand Encoding
      Op/En             Operand 1                     Operand 2                    Operand 3                     Operand 4
        RM           ModRM:reg (r, w)            ModRM:r/m (r)                         NA                            NA
       RVM            ModRM:reg (w)               VEX.vvvv (r)                   ModRM:r/m (r)                       NA
        FV            ModRM:reg (w)              EVEX.vvvv (r)                   ModRM:r/m (r)                       NA

Description
Performs an interleaved unpack of the low single-precision floating-point values from the first source operand and
the second source operand.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified. When unpacking from a memory operand, an implementation may fetch
only the appropriate 64 bits; however, alignment to 16-byte boundary and normal segment checking will still be
enforced.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.





                         SRC1      X7        X6        X5        X4         X3     X2   X1     X0


                         SRC2      Y7        Y6        Y5        Y4         Y3     Y2   Y1     Y0




                         DEST      Y5        X5        Y4        X4         Y1     X1   Y0     X0




                                                  Figure 4-28. VUNPCKLPS Operation


EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a ZMM register, conditionally updated using writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1.

Operation
VUNPCKLPS (EVEX encoded version when SRC2 is a ZMM register)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL >= 128
    TMP_DEST[31:0] <- SRC1[31:0]
    TMP_DEST[63:32] <- SRC2[31:0]
    TMP_DEST[95:64] <- SRC1[63:32]
    TMP_DEST[127:96] <- SRC2[63:32]
FI;
IF VL >= 256
    TMP_DEST[159:128] <- SRC1[159:128]
    TMP_DEST[191:160] <- SRC2[159:128]
    TMP_DEST[223:192] <- SRC1[191:160]
    TMP_DEST[255:224] <- SRC2[191:160]
FI;
IF VL >= 512
    TMP_DEST[287:256] <- SRC1[287:256]
    TMP_DEST[319:288] <- SRC2[287:256]
    TMP_DEST[351:320] <- SRC1[319:288]
    TMP_DEST[383:352] <- SRC2[319:288]
    TMP_DEST[415:384] <- SRC1[415:384]
    TMP_DEST[447:416] <- SRC2[415:384]
    TMP_DEST[479:448] <- SRC1[447:416]
    TMP_DEST[511:480] <- SRC2[447:416]
FI;
FOR j <- 0 TO KL-1
    i <- j * 32



   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VUNPCKLPS (EVEX encoded version when SRC2 is memory)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 31
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL >= 128
TMP_DEST[31:0] <- SRC1[31:0]
TMP_DEST[63:32] <- TMP_SRC2[31:0]
TMP_DEST[95:64] <- SRC1[63:32]
TMP_DEST[127:96] <- TMP_SRC2[63:32]
FI;
IF VL >= 256
    TMP_DEST[159:128] <- SRC1[159:128]
    TMP_DEST[191:160] <- TMP_SRC2[159:128]
    TMP_DEST[223:192] <- SRC1[191:160]
    TMP_DEST[255:224] <- TMP_SRC2[191:160]
FI;
IF VL >= 512
    TMP_DEST[287:256] <- SRC1[287:256]
    TMP_DEST[319:288] <- TMP_SRC2[287:256]
    TMP_DEST[351:320] <- SRC1[319:288]
    TMP_DEST[383:352] <- TMP_SRC2[319:288]
    TMP_DEST[415:384] <- SRC1[415:384]
    TMP_DEST[447:416] <- TMP_SRC2[415:384]
    TMP_DEST[479:448] <- SRC1[447:416]
    TMP_DEST[511:480] <- TMP_SRC2[447:416]
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;



ENDFOR
DEST[MAX_VL-1:VL] <- 0

UNPCKLPS (VEX.256 encoded version)
DEST[31:0] <-SRC1[31:0]
DEST[63:32] <-SRC2[31:0]
DEST[95:64] <-SRC1[63:32]
DEST[127:96] <-SRC2[63:32]
DEST[159:128] <-SRC1[159:128]
DEST[191:160] <-SRC2[159:128]
DEST[223:192] <-SRC1[191:160]
DEST[255:224] <-SRC2[191:160]
DEST[MAX_VL-1:256] <- 0

VUNPCKLPS (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0]
DEST[63:32] <-SRC2[31:0]
DEST[95:64] <-SRC1[63:32]
DEST[127:96] <-SRC2[63:32]
DEST[MAX_VL-1:128] <-0

UNPCKLPS (128-bit Legacy SSE version)
DEST[31:0] <-SRC1[31:0]
DEST[63:32] <-SRC2[31:0]
DEST[95:64] <-SRC1[63:32]
DEST[127:96] <-SRC2[63:32]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VUNPCKLPS __m512 _mm512_unpacklo_ps(__m512 a, __m512 b);
VUNPCKLPS __m512 _mm512_mask_unpacklo_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VUNPCKLPS __m512 _mm512_maskz_unpacklo_ps(__mmask16 k, __m512 a, __m512 b);
VUNPCKLPS __m256 _mm256_unpacklo_ps (__m256 a, __m256 b);
VUNPCKLPS __m256 _mm256_mask_unpacklo_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VUNPCKLPS __m256 _mm256_maskz_unpacklo_ps(__mmask8 k, __m256 a, __m256 b);
UNPCKLPS __m128 _mm_unpacklo_ps (__m128 a, __m128 b);
VUNPCKLPS __m128 _mm_mask_unpacklo_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VUNPCKLPS __m128 _mm_maskz_unpacklo_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4NF.






platform: x86_64
mnem: VALIGND
description:
VALIGND/VALIGNQ-Align Doubleword/Quadword Vectors
 Opcode/                                 Op /   64/32      CPUID      Description
 Instruction                             En     bit Mode   Feature
                                                Support    Flag
 EVEX.NDS.128.66.0F3A.W0 03 /r ib        FV     V/V        AVX512VL   Shift right and merge vectors xmm2 and
 VALIGND xmm1 {k1}{z}, xmm2,                               AVX512F    xmm3/m128/m32bcst with double-word granularity
 xmm3/m128/m32bcst, imm8                                              using imm8 as number of elements to shift, and store the
                                                                      final result in xmm1, under writemask.
 EVEX.NDS.128.66.0F3A.W1 03 /r ib        FV     V/V        AVX512VL   Shift right and merge vectors xmm2 and
 VALIGNQ xmm1 {k1}{z}, xmm2,                               AVX512F    xmm3/m128/m64bcst with quad-word granularity using
 xmm3/m128/m64bcst, imm8                                              imm8 as number of elements to shift, and store the final
                                                                      result in xmm1, under writemask.
 EVEX.NDS.256.66.0F3A.W0 03 /r ib        FV     V/V        AVX512VL   Shift right and merge vectors ymm2 and
 VALIGND ymm1 {k1}{z}, ymm2,                               AVX512F    ymm3/m256/m32bcst with double-word granularity
 ymm3/m256/m32bcst, imm8                                              using imm8 as number of elements to shift, and store the
                                                                      final result in ymm1, under writemask.
 EVEX.NDS.256.66.0F3A.W1 03 /r ib        FV     V/V        AVX512VL   Shift right and merge vectors ymm2 and
 VALIGNQ ymm1 {k1}{z}, ymm2,                               AVX512F    ymm3/m256/m64bcst with quad-word granularity using
 ymm3/m256/m64bcst, imm8                                              imm8 as number of elements to shift, and store the final
                                                                      result in ymm1, under writemask.
 EVEX.NDS.512.66.0F3A.W0 03 /r ib        FV     V/V        AVX512F    Shift right and merge vectors zmm2 and
 VALIGND zmm1 {k1}{z}, zmm2,                                          zmm3/m512/m32bcst with double-word granularity
 zmm3/m512/m32bcst, imm8                                              using imm8 as number of elements to shift, and store the
                                                                      final result in zmm1, under writemask.
 EVEX.NDS.512.66.0F3A.W1 03 /r ib        FV     V/V        AVX512F    Shift right and merge vectors zmm2 and
 VALIGNQ zmm1 {k1}{z}, zmm2,                                          zmm3/m512/m64bcst with quad-word granularity using
 zmm3/m512/m64bcst, imm8                                              imm8 as number of elements to shift, and store the final
                                                                      result in zmm1, under writemask.



                                                Instruction Operand Encoding
      Op/En                Operand 1                  Operand 2                Operand 3                   Operand 4
        FV               ModRM:reg (w)                EVEX.vvvv              ModRM:r/m (r)                     NA

Description
Concatenates and shifts right doubleword/quadword elements of the first source operand (the second operand)
and the second source operand (the third operand) into a 1024/512/256-bit intermediate vector. The low
512/256/128-bit of the intermediate vector is written to the destination operand (the first operand) using the
writemask k1. The destination and first source operands are ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted
from a 32/64-bit memory location.
This instruction is writemasked, so only those elements with the corresponding bit set in vector mask register k1
are computed and stored into zmm1. Elements in zmm1 with the corresponding bit clear in k1 retain their previous
values (merging-masking) or are set to 0 (zeroing-masking).





Operation
VALIGND (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)

IF (SRC2 *is memory*) (AND EVEX.b = 1)
    THEN
          FOR j <- 0 TO KL-1
               i <-j * 32
               src[i+31:i] <- SRC2[31:0]
          ENDFOR;
    ELSE src <- SRC2
FI
; Concatenate sources
tmp[VL-1:0] <- src[VL-1:0]
tmp[2VL-1:VL] <- SRC1[VL-1:0]
; Shift right doubleword elements
IF VL = 128
    THEN SHIFT = imm8[1:0]
    ELSE
          IF VL = 256
               THEN SHIFT = imm8[2:0]
               ELSE SHIFT = imm8[3:0]
          FI
FI;
tmp[2VL-1:0] <- tmp[2VL-1:0] >> (32*SHIFT)
; Apply writemask
FOR j <- 0 TO KL-1
    i <-j * 32
    IF k1[j] OR *no writemask*
          THEN DEST[i+31:i] <- tmp[i+31:i]
          ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





VALIGNQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256),(8, 512)
IF (SRC2 *is memory*) (AND EVEX.b = 1)
    THEN
          FOR j <- 0 TO KL-1
               i <-j * 64
               src[i+63:i] <- SRC2[63:0]
          ENDFOR;
    ELSE src <- SRC2
FI
; Concatenate sources
tmp[VL-1:0] <- src[VL-1:0]
tmp[2VL-1:VL] <- SRC1[VL-1:0]
; Shift right quadword elements
IF VL = 128
    THEN SHIFT = imm8[0]
    ELSE
          IF VL = 256
               THEN SHIFT = imm8[1:0]
               ELSE SHIFT = imm8[2:0]
          FI
FI;
tmp[2VL-1:0] <- tmp[2VL-1:0] >> (64*SHIFT)
; Apply writemask
FOR j <- 0 TO KL-1
    i <-j * 64
    IF k1[j] OR *no writemask*
          THEN DEST[i+63:i] <- tmp[i+63:i]
          ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VALIGND __m512i _mm512_alignr_epi32( __m512i a, __m512i b, int cnt);
VALIGND __m512i _mm512_mask_alignr_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b, int cnt);
VALIGND __m512i _mm512_maskz_alignr_epi32( __mmask16 k, __m512i a, __m512i b, int cnt);
VALIGND __m256i _mm256_mask_alignr_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m256i _mm256_maskz_alignr_epi32( __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGND __m128i _mm_mask_alignr_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGND __m128i _mm_maskz_alignr_epi32( __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m512i _mm512_alignr_epi64( __m512i a, __m512i b, int cnt);
VALIGNQ __m512i _mm512_mask_alignr_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b, int cnt);
VALIGNQ __m512i _mm512_maskz_alignr_epi64( __mmask8 k, __m512i a, __m512i b, int cnt);
VALIGNQ __m256i _mm256_mask_alignr_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGNQ __m256i _mm256_maskz_alignr_epi64( __mmask8 k, __m256i a, __m256i b, int cnt);
VALIGNQ __m128i _mm_mask_alignr_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b, int cnt);
VALIGNQ __m128i _mm_maskz_alignr_epi64( __mmask8 k, __m128i a, __m128i b, int cnt);

Exceptions
See Exceptions Type E4NF.






platform: x86_64
mnem: VBLENDMPD
description:
VBLENDMPD/VBLENDMPS-Blend Float64/Float32 Vectors Using an OpMask Control
 Opcode/                              Op /   64/32        CPUID       Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 EVEX.NDS.128.66.0F38.W1 65 /r        FV     V/V          AVX512VL    Blend double-precision vector xmm2 and double-precision
 VBLENDMPD xmm1 {k1}{z},                                  AVX512F     vector xmm3/m128/m64bcst and store the result in xmm1,
 xmm2, xmm3/m128/m64bcst                                              under control mask.
 EVEX.NDS.256.66.0F38.W1 65 /r        FV     V/V          AVX512VL    Blend double-precision vector ymm2 and double-precision
 VBLENDMPD ymm1 {k1}{z},                                  AVX512F     vector ymm3/m256/m64bcst and store the result in ymm1,
 ymm2, ymm3/m256/m64bcst                                              under control mask.
 EVEX.NDS.512.66.0F38.W1 65 /r        FV     V/V          AVX512F     Blend double-precision vector zmm2 and double-precision
 VBLENDMPD zmm1 {k1}{z},                                              vector zmm3/m512/m64bcst and store the result in zmm1,
 zmm2, zmm3/m512/m64bcst                                              under control mask.
 EVEX.NDS.128.66.0F38.W0 65 /r        FV     V/V          AVX512VL    Blend single-precision vector xmm2 and single-precision
 VBLENDMPS xmm1 {k1}{z},                                  AVX512F     vector xmm3/m128/m32bcst and store the result in xmm1,
 xmm2, xmm3/m128/m32bcst                                              under control mask.
 EVEX.NDS.256.66.0F38.W0 65 /r        FV     V/V          AVX512VL    Blend single-precision vector ymm2 and single-precision
 VBLENDMPS ymm1 {k1}{z},                                  AVX512F     vector ymm3/m256/m32bcst and store the result in ymm1,
 ymm2, ymm3/m256/m32bcst                                              under control mask.
 EVEX.NDS.512.66.0F38.W0 65 /r        FV     V/V          AVX512F     Blend single-precision vector zmm2 and single-precision
 VBLENDMPS zmm1 {k1}{z},                                              vector zmm3/m512/m32bcst using k1 as select control and
 zmm2, zmm3/m512/m32bcst                                              store the result in zmm1.



                                                   Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                   Operand 3                Operand 4
       FV               ModRM:reg (w)                   EVEX.vvvv              ModRM:r/m (r)                    NA

Description
Performs an element-by-element blending between float64/float32 elements in the first source operand (the
second operand) with the elements in the second source operand (the third operand) using an opmask register as
select control. The blended result is written to the destination register.
The destination and first source operands are ZMM/YMM/XMM registers. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location.
The opmask register is not used as a writemask for this instruction. Instead, the mask is used as an element
selector: every element of the destination is conditionally selected between first source or second source using the
value of the related mask bit (0 for first source operand, 1 for second source operand).
If EVEX.z is set, the elements with corresponding mask bit value of 0 in the destination operand are zeroed.





Operation
VBLENDMPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no controlmask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- SRC2[63:0]
                    ELSE
                         DEST[i+63:i] <- SRC2[i+63:i]
               FI;
         ELSE
               IF *merging-masking*                  ; merging-masking
                    THEN DEST[i+63:i] <- SRC1[i+63:i]
                    ELSE                             ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0
VBLENDMPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no controlmask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- SRC2[31:0]
                    ELSE
                         DEST[i+31:i] <- SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                  ; merging-masking
                    THEN DEST[i+31:i] <- SRC1[i+31:i]
                    ELSE                             ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VBLENDMPD __m512d _mm512_mask_blend_pd(__mmask8 k, __m512d a, __m512d b);
VBLENDMPD __m256d _mm256_mask_blend_pd(__mmask8 k, __m256d a, __m256d b);
VBLENDMPD __m128d _mm_mask_blend_pd(__mmask8 k, __m128d a, __m128d b);
VBLENDMPS __m512 _mm512_mask_blend_ps(__mmask16 k, __m512 a, __m512 b);
VBLENDMPS __m256 _mm256_mask_blend_ps(__mmask8 k, __m256 a, __m256 b);
VBLENDMPS __m128 _mm_mask_blend_ps(__mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VBROADCAST
description:
VBROADCAST-Load with Broadcast Floating-Point Data
 Opcode/                         Op /   64/32     CPUID      Description
 Instruction                     En     bit       Feature
                                        Mode      Flag
                                        Support
 VEX.128.66.0F38.W0 18 /r        RM     V/V       AVX        Broadcast single-precision floating-point element in
 VBROADCASTSS xmm1, m32                                      mem to four locations in xmm1.
 VEX.256.66.0F38.W0 18 /r        RM     V/V       AVX        Broadcast single-precision floating-point element in
 VBROADCASTSS ymm1, m32                                      mem to eight locations in ymm1.
 VEX.256.66.0F38.W0 19 /r        RM     V/V       AVX        Broadcast double-precision floating-point element in
 VBROADCASTSD ymm1, m64                                      mem to four locations in ymm1.
 VEX.256.66.0F38.W0 1A /r        RM     V/V       AVX        Broadcast 128 bits of floating-point data in mem to
 VBROADCASTF128 ymm1, m128                                   low and high 128-bits in ymm1.
 EVEX.256.66.0F38.W1 19 /r       T1S    V/V       AVX512VL   Broadcast low double-precision floating-point element
 VBROADCASTSD ymm1 {k1}{z},                       AVX512F    in xmm2/m64 to four locations in ymm1 using
 xmm2/m64                                                    writemask k1.
 EVEX.512.66.0F38.W1 19 /r       T1S    V/V       AVX512F    Broadcast low double-precision floating-point element
 VBROADCASTSD zmm1 {k1}{z},                                  in xmm2/m64 to eight locations in zmm1 using
 xmm2/m64                                                    writemask k1.
 EVEX.256.66.0F38.W0 19 /r       T2     V/V       AVX512VL   Broadcast two single-precision floating-point elements
 VBROADCASTF32X2 ymm1 {k1}{z},                    AVX512DQ   in xmm2/m64 to locations in ymm1 using writemask
 xmm2/m64                                                    k1.
 EVEX.512.66.0F38.W0 19 /r       T2     V/V       AVX512DQ   Broadcast two single-precision floating-point elements
 VBROADCASTF32X2 zmm1 {k1}{z},                               in xmm2/m64 to locations in zmm1 using writemask
 xmm2/m64                                                    k1.
 EVEX.128.66.0F38.W0 18 /r       T1S    V/V       AVX512VL   Broadcast low single-precision floating-point element
 VBROADCASTSS xmm1 {k1}{z},                       AVX512F    in xmm2/m32 to all locations in xmm1 using
 xmm2/m32                                                    writemask k1.
 EVEX.256.66.0F38.W0 18 /r       T1S    V/V       AVX512VL   Broadcast low single-precision floating-point element
 VBROADCASTSS ymm1 {k1}{z},                       AVX512F    in xmm2/m32 to all locations in ymm1 using
 xmm2/m32                                                    writemask k1.
 EVEX.512.66.0F38.W0 18 /r       T1S    V/V       AVX512F    Broadcast low single-precision floating-point element
 VBROADCASTSS zmm1 {k1}{z},                                  in xmm2/m32 to all locations in zmm1 using
 xmm2/m32                                                    writemask k1.
 EVEX.256.66.0F38.W0 1A /r       T4     V/V       AVX512VL   Broadcast 128 bits of 4 single-precision floating-point
 VBROADCASTF32X4 ymm1 {k1}{z},                    AVX512F    data in mem to locations in ymm1 using writemask k1.
 m128
 EVEX.512.66.0F38.W0 1A /r       T4     V/V       AVX512F    Broadcast 128 bits of 4 single-precision floating-point
 VBROADCASTF32X4 zmm1 {k1}{z},                               data in mem to locations in zmm1 using writemask k1.
 m128
 EVEX.256.66.0F38.W1 1A /r       T2     V/V       AVX512VL   Broadcast 128 bits of 2 double-precision floating-point
 VBROADCASTF64X2 ymm1 {k1}{z},                    AVX512DQ   data in mem to locations in ymm1 using writemask k1.
 m128
 EVEX.512.66.0F38.W1 1A /r       T2     V/V       AVX512DQ   Broadcast 128 bits of 2 double-precision floating-point
 VBROADCASTF64X2 zmm1 {k1}{z},                               data in mem to locations in zmm1 using writemask k1.
 m128
 EVEX.512.66.0F38.W0 1B /r       T8     V/V       AVX512DQ   Broadcast 256 bits of 8 single-precision floating-point
 VBROADCASTF32X8 zmm1 {k1}{z},                               data in mem to locations in zmm1 using writemask k1.
 m256
 EVEX.512.66.0F38.W1 1B /r       T4     V/V       AVX512F    Broadcast 256 bits of 4 double-precision floating-point
 VBROADCASTF64X4 zmm1 {k1}{z},                               data in mem to locations in zmm1 using writemask k1.
 m256





                                                 Instruction Operand Encoding
       Op/En                Operand 1                  Operand 2                Operand 3                 Operand 4
        RM                ModRM:reg (w)               ModRM:r/m (r)                   NA                     NA
  T1S, T2, T4, T8         ModRM:reg (w)               ModRM:r/m (r)                   NA                     NA

Description
VBROADCASTSD/VBROADCASTSS/VBROADCASTF128 load floating-point values as one tuple from the source
operand (second operand) in memory and broadcast to all elements of the destination operand (first operand).
    VEX256-encoded versions: The destination operand is a YMM register. The source operand is either a 32-bit,
    64-bit, or 128-bit memory location. Register source encodings are reserved and will #UD. Bits (MAX_VL-
    1:256) of the destination register are zeroed.
    EVEX-encoded versions: The destination operand is a ZMM/YMM/XMM register and updated according to the
    writemask k1. The source operand is either a 32-bit, 64-bit memory location or the low
    doubleword/quadword element of an XMM register.
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2/VBROADCASTF32X8/VBROADCASTF64X4 load
floating-point values as tuples from the source operand (the second operand) in memory or register and broadcast
to all elements of the destination operand (the first operand). The destination operand is a YMM/ZMM register
updated according to the writemask k1. The source operand is either a register or 64-bit/128-bit/256-bit memory
location.
VBROADCASTSD and VBROADCASTF128,F32x4 and F64x2 are only supported as 256-bit and 512-bit wide
versions and up. VBROADCASTSS is supported in 128-bit, 256-bit and 512-bit wide versions. F32x8 and F64x4 are
only supported as 512-bit wide versions.
VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF32X8 have 32-bit granularity. VBROADCASTF64X2 and
VBROADCASTF64X4 have 64-bit granularity.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VBROADCASTSD or VBROADCASTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded
with VEX.L= 0 will cause an #UD exception.




                                                                                m32         X0




                     DEST     X0        X0       X0      X0        X0   X0            X0    X0


                            Figure 5-1. VBROADCASTSS Operation (VEX.256 encoded version)




                                                                                m32         X0




                     DEST     0         0        0       0         X0   X0            X0    X0


                                  Figure 5-2. VBROADCASTSS Operation (VEX.128-bit version)



                                                             m64               X0




                 DEST       X0                  X0          X0                 X0


                          Figure 5-3. VBROADCASTSD Operation (VEX.256-bit version)




                                                     m128          X0




                  DEST              X0                             X0


                         Figure 5-4. VBROADCASTF128 Operation (VEX.256-bit version)




                                                     m256          X0




                  DEST              X0                             X0


                Figure 5-5. VBROADCASTF64X4 Operation (512-bit version with writemask all 1s)


Operation
VBROADCASTSS (128 bit version VEX and legacy)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[MAX_VL-1:128] <- 0





VBROADCASTSS (VEX.256 encoded version)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[159:128] <- temp
DEST[191:160] <- temp
DEST[223:192] <- temp
DEST[255:224] <- temp
DEST[MAX_VL-1:256] <- 0

VBROADCASTSS (EVEX encoded versions)
(KL, VL) (4, 128), (8, 256),= (16, 512)
FOR j <- 0 TO KL-1
    i <-j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[31:0]
         ELSE
              IF *merging-masking*                 ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTSD (VEX.256 encoded version)
temp <- SRC[63:0]
DEST[63:0] <- temp
DEST[127:64] <- temp
DEST[191:128] <- temp
DEST[255:192] <- temp
DEST[MAX_VL-1:256] <- 0

VBROADCASTSD (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <-j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[63:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VBROADCASTF32x2 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    n <- (j mod 2) * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[n+31:n]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTF128 (VEX.256 encoded version)
temp <- SRC[127:0]
DEST[127:0] <- temp
DEST[255:128] <- temp
DEST[MAX_VL-1:256] <- 0

VBROADCASTF32X4 (EVEX encoded versions)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j* 32
    n <- (j modulo 4) * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[n+31:n]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VBROADCASTF64X2 (EVEX encoded versions)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    n <-(j modulo 2) * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[n+63:n]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] = 0
               FI
    FI;
ENDFOR;

VBROADCASTF32X8 (EVEX.U1.512 encoded version)
FOR j <- 0 TO 15
   i <- j * 32
   n <-(j modulo 8) * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- SRC[n+31:n]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VBROADCASTF64X4 (EVEX.512 encoded version)
FOR j <- 0 TO 7
   i <- j * 64
   n <- (j modulo 4) * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- SRC[n+63:n]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VBROADCASTF32x2 __m512 _mm512_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m512 _mm512_mask_broadcast_f32x2(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x2 __m512 _mm512_maskz_broadcast_f32x2( __mmask16 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_broadcast_f32x2( __m128 a);
VBROADCASTF32x2 __m256 _mm256_mask_broadcast_f32x2(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x2 __m256 _mm256_maskz_broadcast_f32x2( __mmask8 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m512 _mm512_mask_broadcast_f32x4(__m512 s, __mmask16 k, __m128 a);
VBROADCASTF32x4 __m512 _mm512_maskz_broadcast_f32x4( __mmask16 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_broadcast_f32x4( __m128 a);
VBROADCASTF32x4 __m256 _mm256_mask_broadcast_f32x4(__m256 s, __mmask8 k, __m128 a);
VBROADCASTF32x4 __m256 _mm256_maskz_broadcast_f32x4( __mmask8 k, __m128 a);
VBROADCASTF32x8 __m512 _mm512_broadcast_f32x8( __m256 a);
VBROADCASTF32x8 __m512 _mm512_mask_broadcast_f32x8(__m512 s, __mmask16 k, __m256 a);
VBROADCASTF32x8 __m512 _mm512_maskz_broadcast_f32x8( __mmask16 k, __m256 a);
VBROADCASTF64x2 __m512d _mm512_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m512d _mm512_mask_broadcast_f64x2(__m512d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m512d _mm512_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_broadcast_f64x2( __m128d a);
VBROADCASTF64x2 __m256d _mm256_mask_broadcast_f64x2(__m256d s, __mmask8 k, __m128d a);
VBROADCASTF64x2 __m256d _mm256_maskz_broadcast_f64x2( __mmask8 k, __m128d a);
VBROADCASTF64x4 __m512d _mm512_broadcast_f64x4( __m256d a);
VBROADCASTF64x4 __m512d _mm512_mask_broadcast_f64x4(__m512d s, __mmask8 k, __m256d a);
VBROADCASTF64x4 __m512d _mm512_maskz_broadcast_f64x4( __mmask8 k, __m256d a);
VBROADCASTSD __m512d _mm512_broadcastsd_pd( __m128d a);
VBROADCASTSD __m512d _mm512_mask_broadcastsd_pd(__m512d s, __mmask8 k, __m128d a);
VBROADCASTSD __m512d _mm512_maskz_broadcastsd_pd(__mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcastsd_pd(__m128d a);
VBROADCASTSD __m256d _mm256_mask_broadcastsd_pd(__m256d s, __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_maskz_broadcastsd_pd( __mmask8 k, __m128d a);
VBROADCASTSD __m256d _mm256_broadcast_sd(double *a);
VBROADCASTSS __m512 _mm512_broadcastss_ps( __m128 a);
VBROADCASTSS __m512 _mm512_mask_broadcastss_ps(__m512 s, __mmask16 k, __m128 a);
VBROADCASTSS __m512 _mm512_maskz_broadcastss_ps( __mmask16 k, __m128 a);
VBROADCASTSS __m256 _mm256_broadcastss_ps(__m128 a);
VBROADCASTSS __m256 _mm256_mask_broadcast_ss(__m256 s, __mmask8 k, __m128 a);
VBROADCASTSS __m256 _mm256_maskz_broadcast_ss( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcastss_ps(__m128 a);
VBROADCASTSS __m128 _mm_mask_broadcast_ss(__m128 s, __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_maskz_broadcast_ss( __mmask8 k, __m128 a);
VBROADCASTSS __m128 _mm_broadcast_ss(float *a);
VBROADCASTSS __m256 _mm256_broadcast_ss(float *a);
VBROADCASTF128 __m256 _mm256_broadcast_ps(__m128 * a);
VBROADCASTF128 __m256d _mm256_broadcast_pd(__m128d * a);

Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6.
#UD                    If VEX.L = 0 for VBROADCASTSD or VBROADCASTF128.
                       If EVEX.L'L = 0 for VBROADCASTSD/VBROADCASTF32X2/VBROADCASTF32X4/VBROADCASTF64X2.
                       If EVEX.L'L < 10b for VBROADCASTF32X8/VBROADCASTF64X4.





platform: x86_64
mnem: VPBROADCASTM
description:
VPBROADCASTM-Broadcast Mask to Vector Register
 Opcode/                              Op/    64/32       CPUID      Description
 Instruction                          En     bit Mode    Feature
                                             Support     Flag
 EVEX.128.F3.0F38.W1 2A /r            RM     V/V         AVX512VL   Broadcast low byte value in k1 to two locations in xmm1.
 VPBROADCASTMB2Q xmm1, k1                                AVX512CD
 EVEX.256.F3.0F38.W1 2A /r            RM     V/V         AVX512VL   Broadcast low byte value in k1 to four locations in ymm1.
 VPBROADCASTMB2Q ymm1, k1                                AVX512CD
 EVEX.512.F3.0F38.W1 2A /r            RM     V/V         AVX512CD   Broadcast low byte value in k1 to eight locations in zmm1.
 VPBROADCASTMB2Q zmm1, k1
 EVEX.128.F3.0F38.W0 3A /r            RM     V/V         AVX512VL   Broadcast low word value in k1 to four locations in xmm1.
 VPBROADCASTMW2D xmm1, k1                                AVX512CD
 EVEX.256.F3.0F38.W0 3A /r            RM     V/V         AVX512VL   Broadcast low word value in k1 to eight locations in ymm1.
 VPBROADCASTMW2D ymm1, k1                                AVX512CD
 EVEX.512.F3.0F38.W0 3A /r            RM     V/V         AVX512CD   Broadcast low word value in k1 to sixteen locations in
 VPBROADCASTMW2D zmm1, k1                                           zmm1.



                                                 Instruction Operand Encoding
     Op/En              Operand 1                   Operand 2                Operand 3                     Operand 4
      RM              ModRM:reg (w)                ModRM:r/m (r)                  NA                           NA

Description
Broadcasts the zero-extended 64/32 bit value of the low byte/word of the source operand (the second operand) to
each 64/32 bit element of the destination operand (the first operand). The source operand is an opmask register.
The destination operand is a ZMM register (EVEX.512), YMM register (EVEX.256), or XMM register (EVEX.128).
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VPBROADCASTMB2Q
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j*64
    DEST[i+63:i] <- ZeroExtend(SRC[7:0])
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPBROADCASTMW2D
(KL, VL) = (4, 128), (8, 256),(16, 512)
FOR j <- 0 TO KL-1
    i <- j*32
    DEST[i+31:i] <- ZeroExtend(SRC[15:0])
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent

VPBROADCASTMB2Q __m512i _mm512_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m512i _mm512_broadcastmw_epi32( __mmask16);
VPBROADCASTMB2Q __m256i _mm256_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m256i _mm256_broadcastmw_epi32( __mmask8);
VPBROADCASTMB2Q __m128i _mm_broadcastmb_epi64( __mmask8);
VPBROADCASTMW2D __m128i _mm_broadcastmw_epi32( __mmask8);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instruction, see Exceptions Type E6NF.






platform: x86_64
mnem: VCOMPRESSPD
description:
VCOMPRESSPD-Store Sparse Packed Double-Precision Floating-Point Values into Dense
Memory
 Opcode/                                      Op /     64/32       CPUID          Description
 Instruction                                  En       bit Mode    Feature
                                                       Support     Flag
 EVEX.128.66.0F38.W1 8A /r                    T1S      V/V         AVX512VL       Compress packed double-precision floating-point
 VCOMPRESSPD xmm1/m128 {k1}{z},                                    AVX512F        values from xmm2 to xmm1/m128 using writemask
 xmm2                                                                             k1.
 EVEX.256.66.0F38.W1 8A /r                    T1S      V/V         AVX512VL       Compress packed double-precision floating-point
 VCOMPRESSPD ymm1/m256 {k1}{z},                                    AVX512F        values from ymm2 to ymm1/m256 using writemask
 ymm2                                                                             k1.
 EVEX.512.66.0F38.W1 8A /r                    T1S      V/V         AVX512F        Compress packed double-precision floating-point
 VCOMPRESSPD zmm1/m512 {k1}{z},                                                   values from zmm2 using control mask k1 to
 zmm2                                                                             zmm1/m512.



                                                     Instruction Operand Encoding
       Op/En                Operand 1                     Operand 2                    Operand 3                 Operand 4
        T1S               ModRM:r/m (w)                 ModRM:reg (r)                      NA                       NA

Description
Compress (store) up to 8 double-precision floating-point values from the source operand (the second operand) as
a contiguous vector to the destination operand (the first operand) The source operand is a ZMM/YMM/XMM register,
the destination operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (partial vector or possibly non-contiguous if less than 8 active
elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to the
destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VCOMPRESSPD (EVEX encoded versions) store form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <- 64
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+63:i]
               k <- k + SIZE
    FI;
ENDFOR





VCOMPRESSPD (EVEX encoded versions) reg-reg form
(KL, VL) = (2, 128), (4, 256), (8, 512)
SIZE <- 64
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+63:i]
               k <- k + SIZE
    FI;
ENDFOR
IF *merging-masking*
           THEN *DEST[VL-1:k] remains unchanged*
           ELSE DEST[VL-1:k] <- 0
FI
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPD __m512d _mm512_mask_compress_pd( __m512d s, __mmask8 k, __m512d a);
VCOMPRESSPD __m512d _mm512_maskz_compress_pd( __mmask8 k, __m512d a);
VCOMPRESSPD void _mm512_mask_compressstoreu_pd( void * d, __mmask8 k, __m512d a);
VCOMPRESSPD __m256d _mm256_mask_compress_pd( __m256d s, __mmask8 k, __m256d a);
VCOMPRESSPD __m256d _mm256_maskz_compress_pd( __mmask8 k, __m256d a);
VCOMPRESSPD void _mm256_mask_compressstoreu_pd( void * d, __mmask8 k, __m256d a);
VCOMPRESSPD __m128d _mm_mask_compress_pd( __m128d s, __mmask8 k, __m128d a);
VCOMPRESSPD __m128d _mm_maskz_compress_pd( __mmask8 k, __m128d a);
VCOMPRESSPD void _mm_mask_compressstoreu_pd( void * d, __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCOMPRESSPS
description:
VCOMPRESSPS-Store Sparse Packed Single-Precision Floating-Point Values into Dense Memory
 Opcode/                                      Op /     64/32         CPUID         Description
 Instruction                                  En       bit Mode      Feature
                                                       Support       Flag
 EVEX.128.66.0F38.W0 8A /r                    T1S      V/V           AVX512VL      Compress packed single-precision floating-point
 VCOMPRESSPS xmm1/m128 {k1}{z},                                      AVX512F       values from xmm2 to xmm1/m128 using writemask
 xmm2                                                                              k1.
 EVEX.256.66.0F38.W0 8A /r                    T1S      V/V           AVX512VL      Compress packed single-precision floating-point
 VCOMPRESSPS ymm1/m256 {k1}{z},                                      AVX512F       values from ymm2 to ymm1/m256 using writemask
 ymm2                                                                              k1.
 EVEX.512.66.0F38.W0 8A /r                    T1S      V/V           AVX512F       Compress packed single-precision floating-point
 VCOMPRESSPS zmm1/m512 {k1}{z},                                                    values from zmm2 using control mask k1 to
 zmm2                                                                              zmm1/m512.



                                                     Instruction Operand Encoding
      Op/En                Operand 1                     Operand 2                     Operand 3                 Operand 4
       T1S               ModRM:r/m (w)                 ModRM:reg (r)                       NA                       NA

Description
Compress (stores) up to 16 single-precision floating-point values from the source operand (the second operand) to
the destination operand (the first operand). The source operand is a ZMM/YMM/XMM register, the destination
operand can be a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The opmask register k1 selects the active elements (a partial vector or possibly non-contiguous if less than 16
active elements) from the source operand to compress into a contiguous vector. The contiguous vector is written to
the destination starting from the low element of the destination operand.
Memory destination version: Only the contiguous vector is written to the destination memory location. EVEX.z
must be zero.
Register destination version: If the vector length of the contiguous vector is less than that of the input vector in the
source operand, the upper bits of the destination register are unmodified if EVEX.z is not set, otherwise the upper
bits are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VCOMPRESSPS (EVEX encoded versions) store form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE <- 32
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+31:i]
               k <- k + SIZE
    FI;
ENDFOR;





VCOMPRESSPS (EVEX encoded versions) reg-reg form
(KL, VL) = (4, 128), (8, 256), (16, 512)
SIZE <- 32
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               DEST[k+SIZE-1:k]<- SRC[i+31:i]
               k <- k + SIZE
    FI;
ENDFOR
IF *merging-masking*
    THEN *DEST[VL-1:k] remains unchanged*
    ELSE DEST[VL-1:k] <- 0
FI
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCOMPRESSPS __m512 _mm512_mask_compress_ps( __m512 s, __mmask16 k, __m512 a);
VCOMPRESSPS __m512 _mm512_maskz_compress_ps( __mmask16 k, __m512 a);
VCOMPRESSPS void _mm512_mask_compressstoreu_ps( void * d, __mmask16 k, __m512 a);
VCOMPRESSPS __m256 _mm256_mask_compress_ps( __m256 s, __mmask8 k, __m256 a);
VCOMPRESSPS __m256 _mm256_maskz_compress_ps( __mmask8 k, __m256 a);
VCOMPRESSPS void _mm256_mask_compressstoreu_ps( void * d, __mmask8 k, __m256 a);
VCOMPRESSPS __m128 _mm_mask_compress_ps( __m128 s, __mmask8 k, __m128 a);
VCOMPRESSPS __m128 _mm_maskz_compress_ps( __mmask8 k, __m128 a);
VCOMPRESSPS void _mm_mask_compressstoreu_ps( void * d, __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E4.nb.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPD2QQ
description:
VCVTPD2QQ-Convert Packed Double-Precision Floating-Point Values to Packed Quadword
Integers
 Opcode/                           Op /    64/32        CPUID           Description
 Instruction                       En      bit Mode     Feature
                                           Support      Flag
 EVEX.128.66.0F.W1 7B /r           FV      V/V          AVX512VL        Convert two packed double-precision floating-point values from
 VCVTPD2QQ xmm1 {k1}{z},                                AVX512DQ        xmm2/m128/m64bcst to two packed quadword integers in
 xmm2/m128/m64bcst                                                      xmm1 with writemask k1.
 EVEX.256.66.0F.W1 7B /r           FV      V/V          AVX512VL        Convert four packed double-precision floating-point values from
 VCVTPD2QQ ymm1 {k1}{z},                                AVX512DQ        ymm2/m256/m64bcst to four packed quadword integers in
 ymm2/m256/m64bcst                                                      ymm1 with writemask k1.
 EVEX.512.66.0F.W1 7B /r           FV      V/V          AVX512DQ        Convert eight packed double-precision floating-point values
 VCVTPD2QQ zmm1 {k1}{z},                                                from zmm2/m512/m64bcst to eight packed quadword integers
 zmm2/m512/m64bcst{er}                                                  in zmm1 with writemask k1.



                                                   Instruction Operand Encoding
         Op/En                   Operand 1                    Operand 2                       Operand 3               Operand 4
           FV                 ModRM:reg (w)                 ModRM:r/m (r)                        NA                      NA

Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed quad-
word integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-        Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[63:0])
                  ELSE
                       DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2QQ __m512i _mm512_cvtpd_epi64( __m512d a);
VCVTPD2QQ __m512i _mm512_mask_cvtpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_maskz_cvtpd_epi64( __mmask8 k, __m512d a);
VCVTPD2QQ __m512i _mm512_cvt_roundpd_epi64( __m512d a, int r);
VCVTPD2QQ __m512i _mm512_mask_cvt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m512i _mm512_maskz_cvt_roundpd_epi64( __mmask8 k, __m512d a, int r);
VCVTPD2QQ __m256i _mm256_mask_cvtpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2QQ __m256i _mm256_maskz_cvtpd_epi64( __mmask8 k, __m256d a);
VCVTPD2QQ __m128i _mm_mask_cvtpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2QQ __m128i _mm_maskz_cvtpd_epi64( __mmask8 k, __m128d a);
VCVTPD2QQ __m256i _mm256_cvtpd_epi64 (__m256d src)
VCVTPD2QQ __m128i _mm_cvtpd_epi64 (__m128d src)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPD2UDQ
description:
VCVTPD2UDQ-Convert Packed Double-Precision Floating-Point Values to Packed Unsigned
Doubleword Integers
 Opcode                              Op /   64/32         CPUID          Description
 Instruction                         En     bit Mode      Feature
                                            Support       Flag
 EVEX.128.0F.W1 79 /r                FV     V/V           AVX512VL       Convert two packed double-precision floating-point
 VCVTPD2UDQ xmm1 {k1}{z},                                 AVX512F        values in xmm2/m128/m64bcst to two unsigned
 xmm2/m128/m64bcst                                                       doubleword integers in xmm1 subject to writemask k1.
 EVEX.256.0F.W1 79 /r                FV     V/V           AVX512VL       Convert four packed double-precision floating-point
 VCVTPD2UDQ xmm1 {k1}{z},                                 AVX512F        values in ymm2/m256/m64bcst to four unsigned
 ymm2/m256/m64bcst                                                       doubleword integers in xmm1 subject to writemask k1.
 EVEX.512.0F.W1 79 /r                FV     V/V           AVX512F        Convert eight packed double-precision floating-point
 VCVTPD2UDQ ymm1 {k1}{z},                                                values in zmm2/m512/m64bcst to eight unsigned
 zmm2/m512/m64bcst{er}                                                   doubleword integers in ymm1 subject to writemask k1.



                                             Instruction Operand Encoding
     Op/En            Operand 1                    Operand 2                    Operand 3                      Operand 4
       FV           ModRM:reg (w)                 ModRM:r/m (r)                     NA                             NA

Description
Converts packed double-precision floating-point values in the source operand (the second operand) to packed
unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are zeroed.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

VCVTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_UInteger(SRC[k+63:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UDQ __m256i _mm512_cvtpd_epu32( __m512d a);
VCVTPD2UDQ __m256i _mm512_mask_cvtpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_maskz_cvtpd_epu32( __mmask8 k, __m512d a);
VCVTPD2UDQ __m256i _mm512_cvt_roundpd_epu32( __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_mask_cvt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m256i _mm512_maskz_cvt_roundpd_epu32( __mmask8 k, __m512d a, int r);
VCVTPD2UDQ __m128i _mm256_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm256_maskz_cvtpd_epu32( __mmask8 k, __m256d a);
VCVTPD2UDQ __m128i _mm_mask_cvtpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UDQ __m128i _mm_maskz_cvtpd_epu32( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPD2UQQ
description:
VCVTPD2UQQ-Convert Packed Double-Precision Floating-Point Values to Packed Unsigned
Quadword Integers
 Opcode/                           Op /    64/32        CPUID           Description
 Instruction                       En      bit Mode     Feature
                                           Support      Flag
 EVEX.128.66.0F.W1 79 /r           FV      V/V          AVX512VL        Convert two packed double-precision floating-point values from
 VCVTPD2UQQ xmm1 {k1}{z},                               AVX512DQ        xmm2/mem to two packed unsigned quadword integers in
 xmm2/m128/m64bcst                                                      xmm1 with writemask k1.
 EVEX.256.66.0F.W1 79 /r           FV      V/V          AVX512VL        Convert fourth packed double-precision floating-point values
 VCVTPD2UQQ ymm1 {k1}{z},                               AVX512DQ        from ymm2/mem to four packed unsigned quadword integers
 ymm2/m256/m64bcst                                                      in ymm1 with writemask k1.
 EVEX.512.66.0F.W1 79 /r           FV      V/V          AVX512DQ        Convert eight packed double-precision floating-point values
 VCVTPD2UQQ zmm1 {k1}{z},                                               from zmm2/mem to eight packed unsigned quadword integers
 zmm2/m512/m64bcst{er}                                                  in zmm1 with writemask k1.



                                                   Instruction Operand Encoding
        Op/En                  Operand 1                       Operand 2                       Operand 3               Operand 4
          FV                 ModRM:reg (w)                   ModRM:r/m (r)                         NA                     NA

Description
Converts packed double-precision floating-point values in the source operand (second operand) to packed
unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[63:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_UQuadInteger(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPD2UQQ __m512i _mm512_cvtpd_epu64( __m512d a);
VCVTPD2UQQ __m512i _mm512_mask_cvtpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_maskz_cvtpd_epu64( __mmask8 k, __m512d a);
VCVTPD2UQQ __m512i _mm512_cvt_roundpd_epu64( __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_mask_cvt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m512i _mm512_maskz_cvt_roundpd_epu64( __mmask8 k, __m512d a, int r);
VCVTPD2UQQ __m256i _mm256_mask_cvtpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTPD2UQQ __m256i _mm256_maskz_cvtpd_epu64( __mmask8 k, __m256d a);
VCVTPD2UQQ __m128i _mm_mask_cvtpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTPD2UQQ __m128i _mm_maskz_cvtpd_epu64( __mmask8 k, __m128d a);
VCVTPD2UQQ __m256i _mm256_cvtpd_epu64 (__m256d src)
VCVTPD2UQQ __m128i _mm_cvtpd_epu64 (__m128d src)

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPH2PS
description:
VCVTPH2PS-Convert 16-bit FP values to Single-Precision FP values
 Opcode/                              Op /     64/32      CPUID           Description
 Instruction                          En       bit Mode   Feature
                                               Support    Flag
 VEX.128.66.0F38.W0 13 /r             RM       V/V        F16C            Convert four packed half precision (16-bit) floating-
 VCVTPH2PS xmm1, xmm2/m64                                                 point values in xmm2/m64 to packed single-precision
                                                                          floating-point value in xmm1.
 VEX.256.66.0F38.W0 13 /r             RM       V/V        F16C            Convert eight packed half precision (16-bit) floating-
 VCVTPH2PS ymm1, xmm2/m128                                                point values in xmm2/m128 to packed single-
                                                                          precision floating-point value in ymm1.
 EVEX.128.66.0F38.W0 13 /r            HVM      V/V        AVX512VL        Convert four packed half precision (16-bit) floating-
 VCVTPH2PS xmm1 {k1}{z}, xmm2/m64                         AVX512F         point values in xmm2/m64 to packed single-precision
                                                                          floating-point values in xmm1.
 EVEX.256.66.0F38.W0 13 /r            HVM      V/V        AVX512VL        Convert eight packed half precision (16-bit) floating-
 VCVTPH2PS ymm1 {k1}{z},                                  AVX512F         point values in xmm2/m128 to packed single-
 xmm2/m128                                                                precision floating-point values in ymm1.
 EVEX.512.66.0F38.W0 13 /r            HVM      V/V        AVX512F         Convert sixteen packed half precision (16-bit)
 VCVTPH2PS zmm1 {k1}{z},                                                  floating-point values in ymm2/m256 to packed
 ymm2/m256 {sae}                                                          single-precision floating-point values in zmm1.



                                             Instruction Operand Encoding
     Op/En             Operand 1                 Operand 2                     Operand 3                      Operand 4
       RM            ModRM:reg (w)              ModRM:r/m (r)                      NA                             NA
      HVM            ModRM:reg (w)              ModRM:r/m (r)                      NA                             NA

Description
Converts packed half precision (16-bits) floating-point values in the low-order bits of the source operand (the
second operand) to packed single-precision floating-point values and writes the converted values into the destina-
tion operand (the first operand).
If case of a denormal operand, the correct normal result is returned. MXCSR.DAZ is ignored and is treated as if it
0. No denormal exception is reported on MXCSR.
VEX.128 version: The source operand is a XMM register or 64-bit memory location. The destination operand is a
XMM register. The upper bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 version: The source operand is a XMM register or 128-bit memory location. The destination operand is a
YMM register. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit
memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
The diagram below illustrates how data is converted from four packed half precision (in 64 bits) to four single preci-
sion (in 128 bits) FP values.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).





                                         VCVTPH2PS xmm1, xmm2/mem64, imm8
                   127              96   95               64   63         48   47         32   31         16   15             0
                                                                    VH3             VH2             VH1             VH0           xmm2/mem64




                                                                                                convert          convert
                          convert               convert


                   127              96   95               64   63                     32       31                         0
                           VS3                   VS2                       VS1                             VS0                    xmm1


                                              Figure 5-6. VCVTPH2PS (128-bit Version)


Operation
vCvt_h2s(SRC1[15:0])
{
RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);
}

VCVTPH2PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               vCvt_h2s(SRC[k+15:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPH2PS (VEX.256 encoded version)
DEST[31:0] <-vCvt_h2s(SRC1[15:0]);
DEST[63:32] <-vCvt_h2s(SRC1[31:16]);
DEST[95:64] <-vCvt_h2s(SRC1[47:32]);
DEST[127:96] <-vCvt_h2s(SRC1[63:48]);
DEST[159:128] <-vCvt_h2s(SRC1[79:64]);
DEST[191:160] <-vCvt_h2s(SRC1[95:80]);
DEST[223:192] <-vCvt_h2s(SRC1[111:96]);
DEST[255:224] <-vCvt_h2s(SRC1[127:112]);
DEST[MAX_VL-1:256] <- 0





VCVTPH2PS (VEX.128 encoded version)
DEST[31:0] <-vCvt_h2s(SRC1[15:0]);
DEST[63:32] <-vCvt_h2s(SRC1[31:16]);
DEST[95:64] <-vCvt_h2s(SRC1[47:32]);
DEST[127:96] <-vCvt_h2s(SRC1[63:48]);
DEST[MAX_VL-1:128] <- 0

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
VCVTPH2PS __m512 _mm512_cvtph_ps( __m256i a);
VCVTPH2PS __m512 _mm512_mask_cvtph_ps(__m512 s, __mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_maskz_cvtph_ps(__mmask16 k, __m256i a);
VCVTPH2PS __m512 _mm512_cvt_roundph_ps( __m256i a, int sae);
VCVTPH2PS __m512 _mm512_mask_cvt_roundph_ps(__m512 s, __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m512 _mm512_maskz_cvt_roundph_ps( __mmask16 k, __m256i a, int sae);
VCVTPH2PS __m256 _mm256_mask_cvtph_ps(__m256 s, __mmask8 k, __m128i a);
VCVTPH2PS __m256 _mm256_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_mask_cvtph_ps(__m128 s, __mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_maskz_cvtph_ps(__mmask8 k, __m128i a);
VCVTPH2PS __m128 _mm_cvtph_ps ( __m128i m1);
VCVTPH2PS __m256 _mm256_cvtph_ps ( __m128i m1)

SIMD Floating-Point Exceptions
Invalid

Other Exceptions
VEX-encoded instructions, see Exceptions Type 11 (do not report #AC);
EVEX-encoded instructions, see Exceptions Type E11.
#UD                    If VEX.W=1.
#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPS2PH
description:
VCVTPS2PH-Convert Single-Precision FP value to 16-bit FP value
 Opcode/                                   Op /      64/32         CPUID                Description
 Instruction                               En        bit Mode      Feature
                                                     Support       Flag
 VEX.128.66.0F3A.W0 1D /r ib               MRI       V/V           F16C                 Convert four packed single-precision floating-point values
 VCVTPS2PH xmm1/m64, xmm2,                                                              in xmm2 to packed half-precision (16-bit) floating-point
 imm8                                                                                   values in xmm1/m64. Imm8 provides rounding controls.
 VEX.256.66.0F3A.W0 1D /r ib               MRI       V/V           F16C                 Convert eight packed single-precision floating-point values
 VCVTPS2PH xmm1/m128, ymm2,                                                             in ymm2 to packed half-precision (16-bit) floating-point
 imm8                                                                                   values in xmm1/m128. Imm8 provides rounding controls.
 EVEX.128.66.0F3A.W0 1D /r ib              HVM       V/V           AVX512VL             Convert four packed single-precision floating-point values
 VCVTPS2PH xmm1/m64 {k1}{z},                                       AVX512F              in xmm2 to packed half-precision (16-bit) floating-point
 xmm2, imm8                                                                             values in xmm1/m64. Imm8 provides rounding controls.
 EVEX.256.66.0F3A.W0 1D /r ib              HVM       V/V           AVX512VL             Convert eight packed single-precision floating-point values
 VCVTPS2PH xmm1/m128 {k1}{z},                                      AVX512F              in ymm2 to packed half-precision (16-bit) floating-point
 ymm2, imm8                                                                             values in xmm1/m128. Imm8 provides rounding controls.
 EVEX.512.66.0F3A.W0 1D /r ib              HVM       V/V           AVX512F              Convert sixteen packed single-precision floating-point
 VCVTPS2PH ymm1/m256 {k1}{z},                                                           values in zmm2 to packed half-precision (16-bit) floating-
 zmm2{sae}, imm8                                                                        point values in ymm1/m256. Imm8 provides rounding
                                                                                        controls.



                                                      Instruction Operand Encoding
       Op/En                   Operand 1                         Operand 2                             Operand 3                          Operand 4
         MRI                ModRM:r/m (w)                    ModRM:reg (r)                                  Imm8                              NA
        HVM                 ModRM:r/m (w)                    ModRM:reg (r)                                  Imm8                              NA

Description
Convert packed single-precision floating values in the source operand to half-precision (16-bit) floating-point
values and store to the destination operand. The rounding mode is specified using the immediate field (imm8).
Underflow results (i.e., tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source element is
denormal relative to the input format with DM masked and at least one of PM or UM unmasked; a SIMD exception
will be raised with DE, UE and PE set.



                                         VCVTPS2PH xmm1/mem64, xmm2, imm8
                   127              96   95             64  63                           32     31                       0
                           VS3                     VS2                        VS1                           VS0                  xmm2

                          convert                 convert                    convert
                                                                                                                  convert




                   127              96   95                 64    63         48 47           32 31         16 15             0
                                                                       VH3             VH2           VH1           VH0           xmm1/mem64


                                              Figure 5-7. VCVTPS2PH (128-bit Version)


The immediate byte defines several bit fields that control rounding operation. The effect and encoding of the RC
field are listed in Table 5-3.





                Table 5-3. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions
                      Bits           Field Name/value                   Description                  Comment
                 Imm[1:0]         RC=00B                     Round to nearest even             If Imm[2] = 0
                                  RC=01B                     Round down
                                  RC=10B                     Round up
                                  RC=11B                     Truncate
                 Imm[2]           MS1=0                      Use imm[1:0] for rounding         Ignore MXCSR.RC
                                  MS1=1                      Use MXCSR.RC for rounding
                 Imm[7:3]         Ignored                    Ignored by processor

VEX.128 version: The source operand is a XMM register. The destination operand is a XMM register or 64-bit
memory location. If the destination operand is a register then the upper bits (MAX_VL-1:64) of corresponding
register are zeroed.
VEX.256 version: The source operand is a YMM register. The destination operand is a XMM register or 128-bit
memory location. If the destination operand is a register, the upper bits (MAX_VL-1:128) of the corresponding
destination register are zeroed.
Note: VEX.vvvv and EVEX.vvvv are reserved (must be 1111b).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register. The destination operand is a
YMM/XMM/XMM (low 64-bits) register or a 256/128/64-bit memory location, conditionally updated with writemask
k1. Bits (MAX_VL-1:256/128/64) of the corresponding destination register are zeroed.

Operation
vCvt_s2h(SRC1[31:0])
{
IF Imm[2] = 0
THEN ; using Imm[1:0] for rounding control, see Table 5-3
    RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE ; using MXCSR.RC for rounding control
    RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;
}

VCVTPS2PH (EVEX encoded versions) when dest is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <-
               vCvt_s2h(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





VCVTPS2PH (EVEX encoded versions) when dest is memory
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <-
               vCvt_s2h(SRC[k+31:k])
         ELSE
               *DEST[i+15:i] remains unchanged* ; merging-masking
    FI;
ENDFOR

VCVTPS2PH (VEX.256 encoded version)
DEST[15:0] <-vCvt_s2h(SRC1[31:0]);
DEST[31:16] <-vCvt_s2h(SRC1[63:32]);
DEST[47:32] <-vCvt_s2h(SRC1[95:64]);
DEST[63:48] <-vCvt_s2h(SRC1[127:96]);
DEST[79:64] <-vCvt_s2h(SRC1[159:128]);
DEST[95:80] <-vCvt_s2h(SRC1[191:160]);
DEST[111:96] <-vCvt_s2h(SRC1[223:192]);
DEST[127:112] <-vCvt_s2h(SRC1[255:224]);
DEST[MAX_VL-1:128] <- 0

VCVTPS2PH (VEX.128 encoded version)
DEST[15:0] <-vCvt_s2h(SRC1[31:0]);
DEST[31:16] <-vCvt_s2h(SRC1[63:32]);
DEST[47:32] <-vCvt_s2h(SRC1[95:64]);
DEST[63:48] <-vCvt_s2h(SRC1[127:96]);
DEST[MAX_VL-1:64] <- 0

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2PH __m256i _mm512_cvtps_ph(__m512 a);
VCVTPS2PH __m256i _mm512_mask_cvtps_ph(__m256i s, __mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_maskz_cvtps_ph(__mmask16 k,__m512 a);
VCVTPS2PH __m256i _mm512_cvt_roundps_ph(__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_mask_cvt_roundps_ph(__m256i s, __mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m256i _mm512_maskz_cvt_roundps_ph(__mmask16 k,__m512 a, const int imm);
VCVTPS2PH __m128i _mm256_mask_cvtps_ph(__m128i s, __mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm256_maskz_cvtps_ph(__mmask8 k,__m256 a);
VCVTPS2PH __m128i _mm_mask_cvtps_ph(__m128i s, __mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_maskz_cvtps_ph(__mmask8 k,__m128 a);
VCVTPS2PH __m128i _mm_cvtps_ph ( __m128 m1, const int imm);
VCVTPS2PH __m128i _mm256_cvtps_ph(__m256 m1, const int imm);

SIMD Floating-Point Exceptions
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);





Other Exceptions
VEX-encoded instructions, see Exceptions Type 11 (do not report #AC);
EVEX-encoded instructions, see Exceptions Type E11.
#UD                 If VEX.W=1.
#UD                 If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPS2UDQ
description:
VCVTPS2UDQ-Convert Packed Single-Precision Floating-Point Values to Packed Unsigned Doubleword Integer Values
 Opcode/                                    Op /    64/32        CPUID          Description
 Instruction                                En      bit Mode     Feature
                                                    Support      Flag
 EVEX.128.0F.W0 79 /r                       FV      V/V          AVX512VL       Convert four packed single precision floating-point
 VCVTPS2UDQ xmm1 {k1}{z},                                        AVX512F        values from xmm2/m128/m32bcst to four packed
 xmm2/m128/m32bcst                                                              unsigned doubleword values in xmm1 subject to
                                                                                writemask k1.
 EVEX.256.0F.W0 79 /r                       FV      V/V          AVX512VL       Convert eight packed single precision floating-point
 VCVTPS2UDQ ymm1 {k1}{z},                                        AVX512F        values from ymm2/m256/m32bcst to eight packed
 ymm2/m256/m32bcst                                                              unsigned doubleword values in ymm1 subject to
                                                                                writemask k1.
 EVEX.512.0F.W0 79 /r                       FV      V/V          AVX512F        Convert sixteen packed single-precision floating-point
 VCVTPS2UDQ zmm1 {k1}{z},                                                       values from zmm2/m512/m32bcst to sixteen packed
 zmm2/m512/m32bcst{er}                                                          unsigned doubleword values in zmm1 subject to
                                                                                writemask k1.



                                                    Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                     Operand 3                   Operand 4
        FV                ModRM:reg (w)                   ModRM:r/m (r)                       NA                         NA

Description
Converts sixteen packed single-precision floating-point values in the source operand to sixteen unsigned double-
word integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_UInteger(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UDQ __m512i _mm512_cvtps_epu32( __m512 a);
VCVTPS2UDQ __m512i _mm512_mask_cvtps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_maskz_cvtps_epu32( __mmask16 k, __m512 a);
VCVTPS2UDQ __m512i _mm512_cvt_roundps_epu32( __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_mask_cvt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m512i _mm512_maskz_cvt_roundps_epu32( __mmask16 k, __m512 a, int r);
VCVTPS2UDQ __m256i _mm256_cvtps_epu32( __m256d a);
VCVTPS2UDQ __m256i _mm256_mask_cvtps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UDQ __m256i _mm256_maskz_cvtps_epu32( __mmask8 k, __m256 a);
VCVTPS2UDQ __m128i _mm_cvtps_epu32( __m128 a);
VCVTPS2UDQ __m128i _mm_mask_cvtps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UDQ __m128i _mm_maskz_cvtps_epu32( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPS2QQ
description:
VCVTPS2QQ-Convert Packed Single Precision Floating-Point Values to Packed Singed
Quadword Integer Values
 Opcode/                      Op /      64/32        CPUID           Description
 Instruction                  En        bit Mode     Feature
                                        Support      Flag
 EVEX.128.66.0F.W0 7B /r      HV        V/V          AVX512VL        Convert two packed single precision floating-point values from
 VCVTPS2QQ xmm1 {k1}{z},                             AVX512DQ        xmm2/m64/m32bcst to two packed signed quadword values in
 xmm2/m64/m32bcst                                                    xmm1 subject to writemask k1.
 EVEX.256.66.0F.W0 7B /r      HV        V/V          AVX512VL        Convert four packed single precision floating-point values from
 VCVTPS2QQ ymm1 {k1}{z},                             AVX512DQ        xmm2/m128/m32bcst to four packed signed quadword values
 xmm2/m128/m32bcst                                                   in ymm1 subject to writemask k1.
 EVEX.512.66.0F.W0 7B /r      HV        V/V          AVX512DQ        Convert eight packed single precision floating-point values from
 VCVTPS2QQ zmm1 {k1}{z},                                             ymm2/m256/m32bcst to eight packed signed quadword values
 ymm2/m256/m32bcst{er}                                               in zmm1 subject to writemask k1.



                                                Instruction Operand Encoding
         Op/En                   Operand 1                        Operand 2                     Operand 3               Operand 4
           HV                ModRM:reg (w)                      ModRM:r/m (r)                       NA                     NA

Description
Converts eight packed single-precision floating-point values in the source operand to eight signed quadword inte-
gers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the indefinite integer value
(2w-1, where w represents the number of bits in the destination format) is returned.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_QuadInteger(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_QuadInteger(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2QQ __m512i _mm512_cvtps_epi64( __m512 a);
VCVTPS2QQ __m512i _mm512_mask_cvtps_epi64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_maskz_cvtps_epi64( __mmask16 k, __m512 a);
VCVTPS2QQ __m512i _mm512_cvt_roundps_epi64( __m512 a, int r);
VCVTPS2QQ __m512i _mm512_mask_cvt_roundps_epi64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m512i _mm512_maskz_cvt_roundps_epi64( __mmask16 k, __m512 a, int r);
VCVTPS2QQ __m256i _mm256_cvtps_epi64( __m256 a);
VCVTPS2QQ __m256i _mm256_mask_cvtps_epi64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2QQ __m256i _mm256_maskz_cvtps_epi64( __mmask8 k, __m256 a);
VCVTPS2QQ __m128i _mm_cvtps_epi64( __m128 a);
VCVTPS2QQ __m128i _mm_mask_cvtps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2QQ __m128i _mm_maskz_cvtps_epi64( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTPS2UQQ
description:
VCVTPS2UQQ-Convert Packed Single Precision Floating-Point Values to Packed Unsigned
Quadword Integer Values
 Opcode/                           Op /    64/32        CPUID           Description
 Instruction                       En      bit Mode     Feature
                                           Support      Flag
 EVEX.128.66.0F.W0 79 /r           HV      V/V          AVX512VL        Convert two packed single precision floating-point values from
 VCVTPS2UQQ xmm1 {k1}{z},                               AVX512DQ        zmm2/m64/m32bcst to two packed unsigned quadword values
 xmm2/m64/m32bcst                                                       in zmm1 subject to writemask k1.
 EVEX.256.66.0F.W0 79 /r           HV      V/V          AVX512VL        Convert four packed single precision floating-point values from
 VCVTPS2UQQ ymm1 {k1}{z},                               AVX512DQ        xmm2/m128/m32bcst to four packed unsigned quadword
 xmm2/m128/m32bcst                                                      values in ymm1 subject to writemask k1.
 EVEX.512.66.0F.W0 79 /r           HV      V/V          AVX512DQ        Convert eight packed single precision floating-point values from
 VCVTPS2UQQ zmm1 {k1}{z},                                               ymm2/m256/m32bcst to eight packed unsigned quadword
 ymm2/m256/m32bcst{er}                                                  values in zmm1 subject to writemask k1.



                                                   Instruction Operand Encoding
        Op/En                 Operand 1                     Operand 2                    Operand 3                    Operand 4
         HV                 ModRM:reg (w)                 ModRM:r/m (r)                      NA                          NA

Description
Converts up to eight packed single-precision floating-point values in the source operand to unsigned quadword
integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
The source operand is a YMM/XMM/XMM (low 64- bits) register or a 256/128/64-bit memory location. The destina-
tion operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
VCVTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VCVTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_UQuadInteger(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_UQuadInteger(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTPS2UQQ __m512i _mm512_cvtps_epu64( __m512 a);
VCVTPS2UQQ __m512i _mm512_mask_cvtps_epu64( __m512i s, __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_maskz_cvtps_epu64( __mmask16 k, __m512 a);
VCVTPS2UQQ __m512i _mm512_cvt_roundps_epu64( __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_mask_cvt_roundps_epu64( __m512i s, __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m512i _mm512_maskz_cvt_roundps_epu64( __mmask16 k, __m512 a, int r);
VCVTPS2UQQ __m256i _mm256_cvtps_epu64( __m256 a);
VCVTPS2UQQ __m256i _mm256_mask_cvtps_epu64( __m256i s, __mmask8 k, __m256 a);
VCVTPS2UQQ __m256i _mm256_maskz_cvtps_epu64( __mmask8 k, __m256 a);
VCVTPS2UQQ __m128i _mm_cvtps_epu64( __m128 a);
VCVTPS2UQQ __m128i _mm_mask_cvtps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTPS2UQQ __m128i _mm_maskz_cvtps_epu64( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTQQ2PD
description:
VCVTQQ2PD-Convert Packed Quadword Integers to Packed Double-Precision Floating-Point
Values
 Opcode/                        Op /    64/32       CPUID          Description
 Instruction                    En      bit Mode    Feature
                                        Support     Flag
 EVEX.128.F3.0F.W1 E6 /r        FV      V/V         AVX512VL       Convert two packed quadword integers from
 VCVTQQ2PD xmm1 {k1}{z},                            AVX512DQ       xmm2/m128/m64bcst to packed double-precision floating-
 xmm2/m128/m64bcst                                                 point values in xmm1 with writemask k1.
 EVEX.256.F3.0F.W1 E6 /r        FV      V/V         AVX512VL       Convert four packed quadword integers from
 VCVTQQ2PD ymm1 {k1}{z},                            AVX512DQ       ymm2/m256/m64bcst to packed double-precision floating-
 ymm2/m256/m64bcst                                                 point values in ymm1 with writemask k1.
 EVEX.512.F3.0F.W1 E6 /r        FV      V/V         AVX512DQ       Convert eight packed quadword integers from
 VCVTQQ2PD zmm1 {k1}{z},                                           zmm2/m512/m64bcst to eight packed double-precision
 zmm2/m512/m64bcst{er}                                             floating-point values in zmm1 with writemask k1.



                                               Instruction Operand Encoding
            Op/En                 Operand 1                   Operand 2                      Operand 3              Operand 4
               FV              ModRM:reg (w)                ModRM:r/m (r)                       NA                      NA

Description
Converts packed quadword integers in the source operand (second operand) to packed double-precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a ZMM/YMM/XMM register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VCVTQQ2PD (EVEX2 encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <-
             Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTQQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b == 1)
                    THEN
                         DEST[i+63:i] <-
               Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
                    ELSE
                         DEST[i+63:i] <-
               Convert_QuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PD __m512d _mm512_cvtepi64_pd( __m512i a);
VCVTQQ2PD __m512d _mm512_mask_cvtepi64_pd( __m512d s, __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_maskz_cvtepi64_pd( __mmask16 k, __m512i a);
VCVTQQ2PD __m512d _mm512_cvt_roundepi64_pd( __m512i a, int r);
VCVTQQ2PD __m512d _mm512_mask_cvt_roundepi_ps( __m512d s, __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m512d _mm512_maskz_cvt_roundepi64_pd( __mmask8 k, __m512i a, int r);
VCVTQQ2PD __m256d _mm256_mask_cvtepi64_pd( __m256d s, __mmask8 k, __m256i a);
VCVTQQ2PD __m256d _mm256_maskz_cvtepi64_pd( __mmask8 k, __m256i a);
VCVTQQ2PD __m128d _mm_mask_cvtepi64_pd( __m128d s, __mmask8 k, __m128i a);
VCVTQQ2PD __m128d _mm_maskz_cvtepi64_pd( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTQQ2PS
description:
VCVTQQ2PS-Convert Packed Quadword Integers to Packed Single-Precision Floating-Point
Values
 Opcode/                         Op /   64/32         CPUID          Description
 Instruction                     En     bit Mode      Feature
                                        Support       Flag
 EVEX.128.0F.W1 5B /r            FV     V/V           AVX512VL       Convert two packed quadword integers from xmm2/mem to
 VCVTQQ2PS xmm1 {k1}{z},                              AVX512DQ       packed single-precision floating-point values in xmm1 with
 xmm2/m128/m64bcst                                                   writemask k1.
 EVEX.256.0F.W1 5B /r            FV     V/V           AVX512VL       Convert four packed quadword integers from ymm2/mem to
 VCVTQQ2PS xmm1 {k1}{z},                              AVX512DQ       packed single-precision floating-point values in xmm1 with
 ymm2/m256/m64bcst                                                   writemask k1.
 EVEX.512.0F.W1 5B /r            FV     V/V           AVX512DQ       Convert eight packed quadword integers from zmm2/mem to
 VCVTQQ2PS ymm1 {k1}{z},                                             eight packed single-precision floating-point values in ymm1 with
 zmm2/m512/m64bcst{er}                                               writemask k1.



                                                 Instruction Operand Encoding
          Op/En                 Operand 1                      Operand 2                      Operand 3                Operand 4
            FV                ModRM:reg (w)                  ModRM:r/m (r)                        NA                       NA

Description
Converts packed quadword integers in the source operand (second operand) to packed single-precision floating-
point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operation
is a YMM/XMM/XMM (lower 64 bits) register conditionally updated with writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VCVTQQ2PS (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[k+31:k] <-
             Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
        ELSE
             IF *merging-masking*               ; merging-masking
                  THEN *DEST[k+31:k] remains unchanged*
                  ELSE                          ; zeroing-masking
                       DEST[k+31:k] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





VCVTQQ2PS (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[k+31:k] <-
             Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
                  ELSE
                       DEST[k+31:k] <-
             Convert_QuadInteger_To_Single_Precision_Floating_Point(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*               ; merging-masking
                  THEN *DEST[k+31:k] remains unchanged*
                  ELSE                          ; zeroing-masking
                       DEST[k+31:k] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTQQ2PS __m256 _mm512_cvtepi64_ps( __m512i a);
VCVTQQ2PS __m256 _mm512_mask_cvtepi64_ps( __m256 s, __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_maskz_cvtepi64_ps( __mmask16 k, __m512i a);
VCVTQQ2PS __m256 _mm512_cvt_roundepi64_ps( __m512i a, int r);
VCVTQQ2PS __m256 _mm512_mask_cvt_roundepi_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m256 _mm512_maskz_cvt_roundepi64_ps( __mmask8 k, __m512i a, int r);
VCVTQQ2PS __m128 _mm256_cvtepi64_ps( __m256i a);
VCVTQQ2PS __m128 _mm256_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm256_maskz_cvtepi64_ps( __mmask8 k, __m256i a);
VCVTQQ2PS __m128 _mm_cvtepi64_ps( __m128i a);
VCVTQQ2PS __m128 _mm_mask_cvtepi64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTQQ2PS __m128 _mm_maskz_cvtepi64_ps( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTSD2USI
description:
VCVTSD2USI-Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword
Integer
 Opcode/                                Op /    64/32        CPUID          Description
 Instruction                            En      bit Mode     Feature
                                                Support      Flag
 EVEX.LIG.F2.0F.W0 79 /r                T1F     V/V          AVX512F        Convert one double-precision floating-point value from
 VCVTSD2USI r32, xmm1/m64{er}                                               xmm1/m64 to one unsigned doubleword integer r32.
 EVEX.LIG.F2.0F.W1 79 /r                T1F     V/N.E.1      AVX512F        Convert one double-precision floating-point value from
 VCVTSD2USI r64, xmm1/m64{er}                                               xmm1/m64 to one unsigned quadword integer zero-
                                                                            extended into r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                Instruction Operand Encoding
     Op/En               Operand 1                    Operand 2                      Operand 3                      Operand 4
      T1F              ModRM:reg (w)                ModRM:r/m (r)                         NA                            NA

Description
Converts a double-precision floating-point value in the source operand (the second operand) to an unsigned
doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or
a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an
XMM register, the double-precision floating-point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.

Operation
VCVTSD2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode and OperandSize = 64
    THEN      DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
    ELSE      DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);
FI

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);
VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);
VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);
VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.




platform: x86_64
mnem: VCVTSS2USI
description:
VCVTSS2USI-Convert Scalar Single-Precision Floating-Point Value to Unsigned Doubleword
Integer
 Opcode/                                      Op /    64/32        CPUID          Description
 Instruction                                  En      bit Mode     Feature
                                                      Support      Flag
 EVEX.LIG.F3.0F.W0 79 /r                      T1F     V/V          AVX512F        Convert one single-precision floating-point value from
 VCVTSS2USI r32, xmm1/m32{er}                                                     xmm1/m32 to one unsigned doubleword integer in r32.
 EVEX.LIG.F3.0F.W1 79 /r                      T1F     V/N.E.1      AVX512F        Convert one single-precision floating-point value from
 VCVTSS2USI r64, xmm1/m32{er}                                                     xmm1/m32 to one unsigned quadword integer in r64.
NOTES:
1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                       Operand 2                       Operand 3                 Operand 4
       T1F                ModRM:reg (w)                   ModRM:r/m (r)                          NA                       NA

Description
Converts a single-precision floating-point value in the source operand (the second operand) to an unsigned double-
word integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand (the first
operand). The source operand can be an XMM register or a memory location. The destination operand is a general-
purpose register. When the source operand is an XMM register, the single-precision floating-point value is
contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register or the embedded rounding control bits. If a converted result cannot be represented in the destination
format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2w - 1 is
returned, where w represents the number of bits in the destination format.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTSS2USI (EVEX encoded version)
IF (SRC *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-bit Mode and OperandSize = 64
THEN
    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
ELSE
    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_UInteger(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTSS2USI unsigned _mm_cvtss_u32( __m128 a);
VCVTSS2USI unsigned _mm_cvt_roundss_u32( __m128 a, int r);
VCVTSS2USI unsigned __int64 _mm_cvtss_u64( __m128 a);
VCVTSS2USI unsigned __int64 _mm_cvt_roundss_u64( __m128 a, int r);





SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: VCVTTPD2QQ
description:
VCVTTPD2QQ-Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Quadword Integers
 Opcode/                            Op /    64/32        CPUID          Description
 Instruction                        En      bit Mode     Feature
                                            Support      Flag
 EVEX.128.66.0F.W1 7A /r            FV      V/V          AVX512VL       Convert two packed double-precision floating-point values from
 VCVTTPD2QQ xmm1 {k1}{z},                                AVX512DQ       zmm2/m128/m64bcst to two packed quadword integers in
 xmm2/m128/m64bcst                                                      zmm1 using truncation with writemask k1.
 EVEX.256.66.0F.W1 7A /r            FV      V/V          AVX512VL       Convert four packed double-precision floating-point values
 VCVTTPD2QQ ymm1 {k1}{z},                                AVX512DQ       from ymm2/m256/m64bcst to four packed quadword integers
 ymm2/m256/m64bcst                                                      in ymm1 using truncation with writemask k1.
 EVEX.512.66.0F.W1 7A /r            FV      V/V          AVX512DQ       Convert eight packed double-precision floating-point values
 VCVTTPD2QQ zmm1 {k1}{z},                                               from zmm2/m512 to eight packed quadword integers in zmm1
 zmm2/m512/m64bcst{sae}                                                 using truncation with writemask k1.



                                                   Instruction Operand Encoding
      Op/En                Operand 1                      Operand 2                      Operand 3                  Operand 4
        FV               ModRM:reg (w)                  ModRM:r/m (r)                       NA                          NA

Description
Converts with truncation packed double-precision floating-point values in the source operand (second operand) to
packed quadword integers in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits
in the destination format) is returned.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTTPD2QQ (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTTPD2QQ (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-        Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[63:0])
                  ELSE
                       DEST[i+63:i] <- Convert_Double_Precision_Floating_Point_To_QuadInteger_Truncate(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2QQ __m512i _mm512_cvttpd_epi64( __m512d a);
VCVTTPD2QQ __m512i _mm512_mask_cvttpd_epi64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_maskz_cvttpd_epi64( __mmask8 k, __m512d a);
VCVTTPD2QQ __m512i _mm512_cvtt_roundpd_epi64( __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_mask_cvtt_roundpd_epi64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m512i _mm512_maskz_cvtt_roundpd_epi64( __mmask8 k, __m512d a, int sae);
VCVTTPD2QQ __m256i _mm256_mask_cvttpd_epi64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2QQ __m256i _mm256_maskz_cvttpd_epi64( __mmask8 k, __m256d a);
VCVTTPD2QQ __m128i _mm_mask_cvttpd_epi64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2QQ __m128i _mm_maskz_cvttpd_epi64( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTPD2UDQ
description:
VCVTTPD2UDQ-Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Unsigned Doubleword Integers
 Opcode                                   Op /   64/32         CPUID          Description
 Instruction                              En     bit Mode      Feature
                                                 Support       Flag
 EVEX.128.0F.W1 78 /r                     FV     V/V           AVX512VL       Convert two packed double-precision floating-point values
 VCVTTPD2UDQ xmm1 {k1}{z},                                     AVX512F        in xmm2/m128/m64bcst to two unsigned doubleword
 xmm2/m128/m64bcst                                                            integers in xmm1 using truncation subject to writemask
                                                                              k1.
 EVEX.256.0F.W1 78 02 /r                  FV     V/V           AVX512VL       Convert four packed double-precision floating-point
 VCVTTPD2UDQ xmm1 {k1}{z},                                     AVX512F        values in ymm2/m256/m64bcst to four unsigned
 ymm2/m256/m64bcst                                                            doubleword integers in xmm1 using truncation subject to
                                                                              writemask k1.
 EVEX.512.0F.W1 78 /r                     FV     V/V           AVX512F        Convert eight packed double-precision floating-point
 VCVTTPD2UDQ ymm1 {k1}{z},                                                    values in zmm2/m512/m64bcst to eight unsigned
 zmm2/m512/m64bcst{sae}                                                       doubleword integers in ymm1 using truncation subject to
                                                                              writemask k1.



                                                   Instruction Operand Encoding
      Op/En                Operand 1                    Operand 2                     Operand 3                       Operand 4
        FV               ModRM:reg (w)                 ModRM:r/m (r)                      NA                               NA

Description
Converts with truncation packed double-precision floating-point values in the source operand (the second operand)
to packed unsigned doubleword integers in the destination operand (the first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of
bits in the destination format.
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM/XMM/XMM (low 64 bits) register
conditionally updated with writemask k1. The upper bits (MAX_VL-1:256) of the corresponding destination are
zeroed.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





Operation
VCVTTPD2UDQ (EVEX encoded versions) when src2 operand is a register
(KL, VL) = (2, 128), (4, 256),(8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+31:i] <-
               Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

VCVTTPD2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256),(8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[k+63:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPD2UDQ __m256i _mm512_cvttpd_epu32( __m512d a);
VCVTTPD2UDQ __m256i _mm512_mask_cvttpd_epu32( __m256i s, __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_maskz_cvttpd_epu32( __mmask8 k, __m512d a);
VCVTTPD2UDQ __m256i _mm512_cvtt_roundpd_epu32( __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_mask_cvtt_roundpd_epu32( __m256i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m256i _mm512_maskz_cvtt_roundpd_epu32( __mmask8 k, __m512d a, int sae);
VCVTTPD2UDQ __m128i _mm256_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm256_maskz_cvttpd_epu32( __mmask8 k, __m256d a);
VCVTTPD2UDQ __m128i _mm_mask_cvttpd_epu32( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UDQ __m128i _mm_maskz_cvttpd_epu32( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTPD2UQQ
description:
VCVTTPD2UQQ-Convert with Truncation Packed Double-Precision Floating-Point Values to
Packed Unsigned Quadword Integers
 Opcode/                            Op /    64/32         CPUID          Description
 Instruction                        En      bit Mode      Feature
                                            Support       Flag
 EVEX.128.66.0F.W1 78 /r            FV      V/V           AVX512VL       Convert two packed double-precision floating-point values
 VCVTTPD2UQQ xmm1 {k1}{z},                                AVX512DQ       from xmm2/m128/m64bcst to two packed unsigned
 xmm2/m128/m64bcst                                                       quadword integers in xmm1 using truncation with
                                                                         writemask k1.
 EVEX.256.66.0F.W1 78 /r            FV      V/V           AVX512VL       Convert four packed double-precision floating-point values
 VCVTTPD2UQQ ymm1 {k1}{z},                                AVX512DQ       from ymm2/m256/m64bcst to four packed unsigned
 ymm2/m256/m64bcst                                                       quadword integers in ymm1 using truncation with
                                                                         writemask k1.
 EVEX.512.66.0F.W1 78 /r            FV      V/V           AVX512DQ       Convert eight packed double-precision floating-point values
 VCVTTPD2UQQ zmm1 {k1}{z},                                               from zmm2/mem to eight packed unsigned quadword
 zmm2/m512/m64bcst{sae}                                                  integers in zmm1 using truncation with writemask k1.



                                                  Instruction Operand Encoding
     Op/En               Operand 1                      Operand 2                      Operand 3                    Operand 4
       FV              ModRM:reg (w)                   ModRM:r/m (r)                      NA                           NA

Description
Converts with truncation packed double-precision floating-point values in the source operand (second operand) to
packed unsigned quadword integers in the destination operand (first operand).
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of
bits in the destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operation is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTTPD2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTTPD2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[63:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Double_Precision_Floating_Point_To_UQuadInteger_Truncate(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent

VCVTTPD2UQQ _mm<size>[_mask[z]]_cvtt[_round]pd_epu64
VCVTTPD2UQQ __m512i _mm512_cvttpd_epu64( __m512d a);
VCVTTPD2UQQ __m512i _mm512_mask_cvttpd_epu64( __m512i s, __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_maskz_cvttpd_epu64( __mmask8 k, __m512d a);
VCVTTPD2UQQ __m512i _mm512_cvtt_roundpd_epu64( __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_mask_cvtt_roundpd_epu64( __m512i s, __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m512i _mm512_maskz_cvtt_roundpd_epu64( __mmask8 k, __m512d a, int sae);
VCVTTPD2UQQ __m256i _mm256_mask_cvttpd_epu64( __m256i s, __mmask8 k, __m256d a);
VCVTTPD2UQQ __m256i _mm256_maskz_cvttpd_epu64( __mmask8 k, __m256d a);
VCVTTPD2UQQ __m128i _mm_mask_cvttpd_epu64( __m128i s, __mmask8 k, __m128d a);
VCVTTPD2UQQ __m128i _mm_maskz_cvttpd_epu64( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTPS2UDQ
description:
VCVTTPS2UDQ-Convert with Truncation Packed Single-Precision Floating-Point Values to
Packed Unsigned Doubleword Integer Values
 Opcode/                                      Op /     64/32        CPUID          Description
 Instruction                                  En       bit Mode     Feature
                                                       Support      Flag
 EVEX.128.0F.W0 78 /r                         FV       V/V          AVX512VL       Convert four packed single precision floating-point
 VCVTTPS2UDQ xmm1 {k1}{z},                                          AVX512F        values from xmm2/m128/m32bcst to four packed
 xmm2/m128/m32bcst                                                                 unsigned doubleword values in xmm1 using
                                                                                   truncation subject to writemask k1.
 EVEX.256.0F.W0 78 /r                         FV       V/V          AVX512VL       Convert eight packed single precision floating-point
 VCVTTPS2UDQ ymm1 {k1}{z},                                          AVX512F        values from ymm2/m256/m32bcst to eight packed
 ymm2/m256/m32bcst                                                                 unsigned doubleword values in ymm1 using
                                                                                   truncation subject to writemask k1.
 EVEX.512.0F.W0 78 /r                         FV       V/V          AVX512F        Convert sixteen packed single-precision floating-
 VCVTTPS2UDQ zmm1 {k1}{z},                                                         point values from zmm2/m512/m32bcst to sixteen
 zmm2/m512/m32bcst{sae}                                                            packed unsigned doubleword values in zmm1 using
                                                                                   truncation subject to writemask k1.



                                                     Instruction Operand Encoding
     Op/En               Operand 1                      Operand 2                     Operand 3                      Operand 4
       FV              ModRM:reg (w)                   ModRM:r/m (r)                      NA                             NA

Description
Converts with truncation packed single-precision floating-point values in the source operand to sixteen unsigned
doubleword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR.
If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised,
and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of bits in the
destination format.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or
a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VCVTTPS2UDQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <-
               Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VCVTTPS2UDQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UDQ __m512i _mm512_cvttps_epu32( __m512 a);
VCVTTPS2UDQ __m512i _mm512_mask_cvttps_epu32( __m512i s, __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_maskz_cvttps_epu32( __mmask16 k, __m512 a);
VCVTTPS2UDQ __m512i _mm512_cvtt_roundps_epu32( __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_mask_cvtt_roundps_epu32( __m512i s, __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m512i _mm512_maskz_cvtt_roundps_epu32( __mmask16 k, __m512 a, int sae);
VCVTTPS2UDQ __m256i _mm256_mask_cvttps_epu32( __m256i s, __mmask8 k, __m256 a);
VCVTTPS2UDQ __m256i _mm256_maskz_cvttps_epu32( __mmask8 k, __m256 a);
VCVTTPS2UDQ __m128i _mm_mask_cvttps_epu32( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UDQ __m128i _mm_maskz_cvttps_epu32( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTPS2QQ
description:
VCVTTPS2QQ-Convert with Truncation Packed Single Precision Floating-Point Values to
Packed Singed Quadword Integer Values
 Opcode/                         Op /    64/32        CPUID           Description
 Instruction                     En      bit Mode     Feature
                                         Support      Flag
 EVEX.128.66.0F.W0 7A /r         HV      V/V          AVX512VL        Convert two packed single precision floating-point values from
 VCVTTPS2QQ xmm1 {k1}{z},                             AVX512DQ        xmm2/m64/m32bcst to two packed signed quadword values in
 xmm2/m64/m32bcst                                                     xmm1 using truncation subject to writemask k1.
 EVEX.256.66.0F.W0 7A /r         HV      V/V          AVX512VL        Convert four packed single precision floating-point values from
 VCVTTPS2QQ ymm1 {k1}{z},                             AVX512DQ        xmm2/m128/m32bcst to four packed signed quadword values
 xmm2/m128/m32bcst                                                    in ymm1 using truncation subject to writemask k1.
 EVEX.512.66.0F.W0 7A /r         HV      V/V          AVX512DQ        Convert eight packed single precision floating-point values from
 VCVTTPS2QQ zmm1 {k1}{z},                                             ymm2/m256/m32bcst to eight packed signed quadword values
 ymm2/m256/m32bcst{sae}                                               in zmm1 using truncation subject to writemask k1.



                                                  Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                      Operand 3                     Operand 4
       HV              ModRM:reg (w)                  ModRM:r/m (r)                        NA                            NA

Description
Converts with truncation packed single-precision floating-point values in the source operand to eight signed quad-
word integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the indefinite integer value (2w-1, where w represents the number of bits
in the destination format) is returned.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VCVTTPS2QQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTTPS2QQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_QuadInteger_Truncate(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_QuadInteger_Truncate(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2QQ __m512i _mm512_cvttps_epi64( __m256 a);
VCVTTPS2QQ __m512i _mm512_mask_cvttps_epi64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_maskz_cvttps_epi64( __mmask16 k, __m256 a);
VCVTTPS2QQ __m512i _mm512_cvtt_roundps_epi64( __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_mask_cvtt_roundps_epi64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m512i _mm512_maskz_cvtt_roundps_epi64( __mmask16 k, __m256 a, int sae);
VCVTTPS2QQ __m256i _mm256_mask_cvttps_epi64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m256i _mm256_maskz_cvttps_epi64( __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_mask_cvttps_epi64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2QQ __m128i _mm_maskz_cvttps_epi64( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTPS2UQQ
description:
VCVTTPS2UQQ-Convert with Truncation Packed Single Precision Floating-Point Values to
Packed Unsigned Quadword Integer Values
 Opcode/                          Op /    64/32        CPUID            Description
 Instruction                      En      bit Mode     Feature
                                          Support      Flag
 EVEX.128.66.0F.W0 78 /r          HV      V/V          AVX512VL         Convert two packed single precision floating-point values
 VCVTTPS2UQQ xmm1 {k1}{z},                             AVX512DQ         from xmm2/m64/m32bcst to two packed unsigned quadword
 xmm2/m64/m32bcst                                                       values in xmm1 using truncation subject to writemask k1.
 EVEX.256.66.0F.W0 78 /r          HV      V/V          AVX512VL         Convert four packed single precision floating-point values
 VCVTTPS2UQQ ymm1 {k1}{z},                             AVX512DQ         from xmm2/m128/m32bcst to four packed unsigned
 xmm2/m128/m32bcst                                                      quadword values in ymm1 using truncation subject to
                                                                        writemask k1.
 EVEX.512.66.0F.W0 78 /r          HV      V/V          AVX512DQ         Convert eight packed single precision floating-point values
 VCVTTPS2UQQ zmm1 {k1}{z},                                              from ymm2/m256/m32bcst to eight packed unsigned
 ymm2/m256/m32bcst{sae}                                                 quadword values in zmm1 using truncation subject to
                                                                        writemask k1.



                                                  Instruction Operand Encoding
       Op/En                Operand 1                     Operand 2                     Operand 3                     Operand 4
        HV                ModRM:reg (w)                 ModRM:r/m (r)                       NA                            NA

Description
Converts with truncation up to eight packed single-precision floating-point values in the source operand to
unsigned quadword integers in the destination operand.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of
bits in the destination format.
EVEX encoded versions: The source operand is a YMM/XMM/XMM (low 64 bits) register or a 256/128/64-bit
memory location. The destination operation is a vector register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
VCVTTPS2UQQ (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTTPS2UQQ (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_Single_Precision_To_UQuadInteger_Truncate(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTPS2UQQ _mm<size>[_mask[z]]_cvtt[_round]ps_epu64
VCVTTPS2UQQ __m512i _mm512_cvttps_epu64( __m256 a);
VCVTTPS2UQQ __m512i _mm512_mask_cvttps_epu64( __m512i s, __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_maskz_cvttps_epu64( __mmask16 k, __m256 a);
VCVTTPS2UQQ __m512i _mm512_cvtt_roundps_epu64( __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_mask_cvtt_roundps_epu64( __m512i s, __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m512i _mm512_maskz_cvtt_roundps_epu64( __mmask16 k, __m256 a, int sae);
VCVTTPS2UQQ __m256i _mm256_mask_cvttps_epu64( __m256i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m256i _mm256_maskz_cvttps_epu64( __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_mask_cvttps_epu64( __m128i s, __mmask8 k, __m128 a);
VCVTTPS2UQQ __m128i _mm_maskz_cvttps_epu64( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3.
#UD                      If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTTSD2USI
description:
VCVTTSD2USI-Convert with Truncation Scalar Double-Precision Floating-Point Value to
Unsigned Integer
 Opcode/                                    Op /    64/32       CPUID          Description
 Instruction                                En      bit Mode    Feature
                                                    Support     Flag
 EVEX.LIG.F2.0F.W0 78 /r                    T1F     V/V         AVX512F        Convert one double-precision floating-point value from
 VCVTTSD2USI r32, xmm1/m64{sae}                                                xmm1/m64 to one unsigned doubleword integer r32
                                                                               using truncation.
 EVEX.LIG.F2.0F.W1 78 /r                    T1F     V/N.E.1     AVX512F        Convert one double-precision floating-point value from
 VCVTTSD2USI r64, xmm1/m64{sae}                                                xmm1/m64 to one unsigned quadword integer zero-
                                                                               extended into r64 using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
  used.



                                                   Instruction Operand Encoding
     Op/En               Operand 1                     Operand 2                     Operand 3                       Operand 4
      T1F              ModRM:reg (w)                 ModRM:r/m (r)                       NA                              NA

Description
Converts with truncation a double-precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination
operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-
point value is contained in the low quadword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of
bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.

Operation
VCVTTSD2USI (EVEX encoded version)
IF 64-Bit Mode and OperandSize = 64
    THEN     DEST[63:0] <- Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
    ELSE     DEST[31:0] <- Convert_Double_Precision_Floating_Point_To_UInteger_Truncate(SRC[63:0]);
FI

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSD2USI unsigned int _mm_cvttsd_u32(__m128d);
VCVTTSD2USI unsigned int _mm_cvtt_roundsd_u32(__m128d, int sae);
VCVTTSD2USI unsigned __int64 _mm_cvttsd_u64(__m128d);
VCVTTSD2USI unsigned __int64 _mm_cvtt_roundsd_u64(__m128d, int sae);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: VCVTTSS2USI
description:
VCVTTSS2USI-Convert with Truncation Scalar Single-Precision Floating-Point Value to
Unsigned Integer
 Opcode/                                       Op /    64/32         CPUID           Description
 Instruction                                   En      bit Mode      Feature
                                                       Support       Flag
 EVEX.LIG.F3.0F.W0 78 /r                       T1F     V/V           AVX512F         Convert one single-precision floating-point value from
 VCVTTSS2USI r32, xmm1/m32{sae}                                                      xmm1/m32 to one unsigned doubleword integer in
                                                                                     r32 using truncation.
 EVEX.LIG.F3.0F.W1 78 /r                       T1F     V/N.E.1       AVX512F         Convert one single-precision floating-point value from
 VCVTTSS2USI r64, xmm1/m32{sae}                                                      xmm1/m32 to one unsigned quadword integer in r64
                                                                                     using truncation.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
  used.



                                                      Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                       Operand 3                    Operand 4
        T1F               ModRM:reg (w)                  ModRM:r/m (r)                         NA                           NA

Description
Converts with truncation a single-precision floating-point value in the source operand (the second operand) to an
unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the destination operand
(the first operand). The source operand can be an XMM register or a memory location. The destination operand is
a general-purpose register. When the source operand is an XMM register, the single-precision floating-point value
is contained in the low doubleword of the register.
When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR
register. If a converted result cannot be represented in the destination format, the floating-point invalid exception
is raised, and if this exception is masked, the integer value 2w - 1 is returned, where w represents the number of
bits in the destination format.
EVEX.W1 version: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





Operation
VCVTTSS2USI (EVEX encoded version)
IF 64-bit Mode and OperandSize = 64
THEN
    DEST[63:0] <- Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
ELSE
    DEST[31:0] <- Convert_Single_Precision_Floating_Point_To_UInteger_Truncate(SRC[31:0]);
FI;

Intel C/C++ Compiler Intrinsic Equivalent
VCVTTSS2USI unsigned int _mm_cvttss_u32( __m128 a);
VCVTTSS2USI unsigned int _mm_cvtt_roundss_u32( __m128 a, int sae);
VCVTTSS2USI unsigned __int64 _mm_cvttss_u64( __m128 a);
VCVTTSS2USI unsigned __int64 _mm_cvtt_roundss_u64( __m128 a, int sae);

SIMD Floating-Point Exceptions
Invalid, Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E3NF.






platform: x86_64
mnem: VCVTUDQ2PD
description:
VCVTUDQ2PD-Convert Packed Unsigned Doubleword Integers to Packed Double-Precision
Floating-Point Values
 Opcode/                                   Op /    64/32        CPUID            Description
 Instruction                               En      bit Mode     Feature
                                                   Support      Flag
 EVEX.128.F3.0F.W0 7A /r                   HV      V/V          AVX512VL         Convert two packed unsigned doubleword integers
 VCVTUDQ2PD xmm1 {k1}{z},                                       AVX512F          from ymm2/m64/m32bcst to packed double-precision
 xmm2/m64/m32bcst                                                                floating-point values in zmm1 with writemask k1.
 EVEX.256.F3.0F.W0 7A /r                   HV      V/V          AVX512VL         Convert four packed unsigned doubleword integers
 VCVTUDQ2PD ymm1 {k1}{z},                                       AVX512F          from xmm2/m128/m32bcst to packed double-
 xmm2/m128/m32bcst                                                               precision floating-point values in zmm1 with
                                                                                 writemask k1.
 EVEX.512.F3.0F.W0 7A /r                   HV      V/V          AVX512F          Convert eight packed unsigned doubleword integers
 VCVTUDQ2PD zmm1 {k1}{z},                                                        from ymm2/m256/m32bcst to eight packed double-
 ymm2/m256/m32bcst                                                               precision floating-point values in zmm1 with
                                                                                 writemask k1.



                                                   Instruction Operand Encoding
     Op/En                 Operand 1                      Operand 2                     Operand 3                  Operand 4
       HV               ModRM:reg (w)                    ModRM:r/m (r)                      NA                        NA

Description
Converts packed unsigned doubleword integers in the source operand (second operand) to packed double-preci-
sion floating-point values in the destination operand (first operand).
The source operand is a YMM/XMM/XMM (low 64 bits) register, a 256/128/64-bit memory location or a
256/128/64-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.
Attempt to encode this instruction with EVEX embedded rounding is ignored.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTUDQ2PD (EVEX encoded versions) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <-
               Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VCVTUDQ2PD (EVEX encoded versions) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   k <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_UInteger_To_Double_Precision_Floating_Point(SRC[31:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_UInteger_To_Double_Precision_Floating_Point(SRC[k+31:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PD __m512d _mm512_cvtepu32_pd( __m256i a);
VCVTUDQ2PD __m512d _mm512_mask_cvtepu32_pd( __m512d s, __mmask8 k, __m256i a);
VCVTUDQ2PD __m512d _mm512_maskz_cvtepu32_pd( __mmask8 k, __m256i a);
VCVTUDQ2PD __m256d _mm256_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m256d _mm256_mask_cvtepu32_pd( __m256d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m256d _mm256_maskz_cvtepu32_pd( __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_cvtepu32_pd( __m128i a);
VCVTUDQ2PD __m128d _mm_mask_cvtepu32_pd( __m128d s, __mmask8 k, __m128i a);
VCVTUDQ2PD __m128d _mm_maskz_cvtepu32_pd( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E5.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTUDQ2PS
description:
VCVTUDQ2PS-Convert Packed Unsigned Doubleword Integers to Packed Single-Precision
Floating-Point Values
 Opcode/                                    Op /    64/32        CPUID           Description
 Instruction                                En      bit Mode     Feature
                                                    Support      Flag
 EVEX.128.F2.0F.W0 7A /r                    FV      V/V          AVX512VL        Convert four packed unsigned doubleword integers from
 VCVTUDQ2PS xmm1 {k1}{z},                                        AVX512F         xmm2/m128/m32bcst to packed single-precision
 xmm2/m128/m32bcst                                                               floating-point values in xmm1 with writemask k1.
 EVEX.256.F2.0F.W0 7A /r                    FV      V/V          AVX512VL        Convert eight packed unsigned doubleword integers
 VCVTUDQ2PS ymm1 {k1}{z},                                        AVX512F         from ymm2/m256/m32bcst to packed single-precision
 ymm2/m256/m32bcst                                                               floating-point values in zmm1 with writemask k1.
 EVEX.512.F2.0F.W0 7A /r                    FV      V/V          AVX512F         Convert sixteen packed unsigned doubleword integers
 VCVTUDQ2PS zmm1 {k1}{z},                                                        from zmm2/m512/m32bcst to sixteen packed single-
 zmm2/m512/m32bcst{er}                                                           precision floating-point values in zmm1 with writemask
                                                                                 k1.



                                                   Instruction Operand Encoding
     Op/En                 Operand 1                      Operand 2                     Operand 3                      Operand 4
       FV                ModRM:reg (w)                  ModRM:r/m (r)                       NA                            NA

Description
Converts packed unsigned doubleword integers in the source operand (second operand) to single-precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTUDQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



VCVTUDQ2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_UInteger_To_Single_Precision_Floating_Point(SRC[i+31:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTUDQ2PS __m512 _mm512_cvtepu32_ps( __m512i a);
VCVTUDQ2PS __m512 _mm512_mask_cvtepu32_ps( __m512 s, __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_maskz_cvtepu32_ps( __mmask16 k, __m512i a);
VCVTUDQ2PS __m512 _mm512_cvt_roundepu32_ps( __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_mask_cvt_roundepu32_ps( __m512 s, __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m512 _mm512_maskz_cvt_roundepu32_ps( __mmask16 k, __m512i a, int r);
VCVTUDQ2PS __m256 _mm256_cvtepu32_ps( __m256i a);
VCVTUDQ2PS __m256 _mm256_mask_cvtepu32_ps( __m256 s, __mmask8 k, __m256i a);
VCVTUDQ2PS __m256 _mm256_maskz_cvtepu32_ps( __mmask8 k, __m256i a);
VCVTUDQ2PS __m128 _mm_cvtepu32_ps( __m128i a);
VCVTUDQ2PS __m128 _mm_mask_cvtepu32_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUDQ2PS __m128 _mm_maskz_cvtepu32_ps( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTUQQ2PD
description:
VCVTUQQ2PD-Convert Packed Unsigned Quadword Integers to Packed Double-Precision
Floating-Point Values
 Opcode/                             Op /    64/32        CPUID            Description
 Instruction                         En      bit Mode     Feature
                                             Support      Flag
 EVEX.128.F3.0F.W1 7A /r             FV      V/V          AVX512VL         Convert two packed unsigned quadword integers from
 VCVTUQQ2PD xmm1 {k1}{z},                                 AVX512DQ         xmm2/m128/m64bcst to two packed double-precision
 xmm2/m128/m64bcst                                                         floating-point values in xmm1 with writemask k1.
 EVEX.256.F3.0F.W1 7A /r             FV      V/V          AVX512VL         Convert four packed unsigned quadword integers from
 VCVTUQQ2PD ymm1 {k1}{z},                                 AVX512DQ         ymm2/m256/m64bcst to packed double-precision floating-
 ymm2/m256/m64bcst                                                         point values in ymm1 with writemask k1.
 EVEX.512.F3.0F.W1 7A /r             FV      V/V           AVX512DQ        Convert eight packed unsigned quadword integers from
 VCVTUQQ2PD zmm1 {k1}{z},                                                  zmm2/m512/m64bcst to eight packed double-precision
 zmm2/m512/m64bcst{er}                                                     floating-point values in zmm1 with writemask k1.



                                                   Instruction Operand Encoding
       Op/En                 Operand 1                    Operand 2                      Operand 3                   Operand 4
         FV               ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA

Description
Converts packed unsigned quadword integers in the source operand (second operand) to packed double-precision
floating-point values in the destination operand (first operand).
The source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTUQQ2PD (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL == 512) AND (EVEX.b == 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <-
             Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VCVTUQQ2PD (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b == 1)
                  THEN
                       DEST[i+63:i] <-
             Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[63:0])
                  ELSE
                       DEST[i+63:i] <-
             Convert_UQuadInteger_To_Double_Precision_Floating_Point(SRC[i+63:i])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PD __m512d _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PD __m512d _mm512_mask_cvtepu64_ps( __m512d s, __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PD __m512d _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_mask_cvt_roundepu64_ps( __m512d s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m512d _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PD __m256d _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PD __m256d _mm256_mask_cvtepu64_ps( __m256d s, __mmask8 k, __m256i a);
VCVTUQQ2PD __m256d _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PD __m128d _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PD __m128d _mm_mask_cvtepu64_ps( __m128d s, __mmask8 k, __m128i a);
VCVTUQQ2PD __m128d _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions

Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTUQQ2PS
description:
VCVTUQQ2PS-Convert Packed Unsigned Quadword Integers to Packed Single-Precision
Floating-Point Values
 Opcode/                             Op /    64/32        CPUID            Description
 Instruction                         En      bit Mode     Feature
                                             Support      Flag
 EVEX.128.F2.0F.W1 7A /r             FV      V/V          AVX512VL         Convert two packed unsigned quadword integers from
 VCVTUQQ2PS xmm1 {k1}{z},                                 AVX512DQ         xmm2/m128/m64bcst to packed single-precision floating-
 xmm2/m128/m64bcst                                                         point values in zmm1 with writemask k1.
 EVEX.256.F2.0F.W1 7A /r             FV      V/V          AVX512VL         Convert four packed unsigned quadword integers from
 VCVTUQQ2PS xmm1 {k1}{z},                                 AVX512DQ         ymm2/m256/m64bcst to packed single-precision floating-
 ymm2/m256/m64bcst                                                         point values in xmm1 with writemask k1.
 EVEX.512.F2.0F.W1 7A /r             FV      V/V          AVX512DQ         Convert eight packed unsigned quadword integers from
 VCVTUQQ2PS ymm1 {k1}{z},                                                  zmm2/m512/m64bcst to eight packed single-precision
 zmm2/m512/m64bcst{er}                                                     floating-point values in zmm1 with writemask k1.



                                                   Instruction Operand Encoding
      Op/En                 Operand 1                    Operand 2                       Operand 3                  Operand 4
        FV                ModRM:reg (w)                 ModRM:r/m (r)                       NA                          NA

Description
Converts packed unsigned quadword integers in the source operand (second operand) to single-precision floating-
point values in the destination operand (first operand).
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a YMM/XMM/XMM (low 64 bits) register conditionally updated with writemask k1.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
VCVTUQQ2PS (EVEX encoded version) when src operand is a register
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <-
             Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0




VCVTUQQ2PS (EVEX encoded version) when src operand is a memory source
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   k <- j * 64
   IF k1[j] OR *no writemask*
        THEN
             IF (EVEX.b = 1)
                  THEN
                       DEST[i+31:i] <-
             Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[63:0])
                  ELSE
                       DEST[i+31:i] <-
             Convert_UQuadInteger_To_Single_Precision_Floating_Point(SRC[k+63:k])
             FI;
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL/2] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTUQQ2PS __m256 _mm512_cvtepu64_ps( __m512i a);
VCVTUQQ2PS __m256 _mm512_mask_cvtepu64_ps( __m256 s, __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_maskz_cvtepu64_ps( __mmask8 k, __m512i a);
VCVTUQQ2PS __m256 _mm512_cvt_roundepu64_ps( __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_mask_cvt_roundepu64_ps( __m256 s, __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m256 _mm512_maskz_cvt_roundepu64_ps( __mmask8 k, __m512i a, int r);
VCVTUQQ2PS __m128 _mm256_cvtepu64_ps( __m256i a);
VCVTUQQ2PS __m128 _mm256_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm256_maskz_cvtepu64_ps( __mmask8 k, __m256i a);
VCVTUQQ2PS __m128 _mm_cvtepu64_ps( __m128i a);
VCVTUQQ2PS __m128 _mm_mask_cvtepu64_ps( __m128 s, __mmask8 k, __m128i a);
VCVTUQQ2PS __m128 _mm_maskz_cvtepu64_ps( __mmask8 k, __m128i a);

SIMD Floating-Point Exceptions

Precision

Other Exceptions
EVEX-encoded instructions, see Exceptions Type E2.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VCVTUSI2SD
description:
VCVTUSI2SD-Convert Unsigned Integer to Scalar Double-Precision Floating-Point Value
 Opcode/                                        Op /    64/32         CPUID           Description
 Instruction                                    En      bit Mode      Feature
                                                        Support       Flag
 EVEX.NDS.LIG.F2.0F.W0 7B /r                    T1S     V/V           AVX512F         Convert one unsigned doubleword integer from
 VCVTUSI2SD xmm1, xmm2, r/m32                                                         r/m32 to one double-precision floating-point value in
                                                                                      xmm1.
 EVEX.NDS.LIG.F2.0F.W1 7B /r                    T1S     V/N.E.1       AVX512F         Convert one unsigned quadword integer from r/m64
 VCVTUSI2SD xmm1, xmm2, r/m64{er}                                                     to one double-precision floating-point value in xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
  used.



                                                     Instruction Operand Encoding
       Op/En                  Operand 1                      Operand 2                     Operand 3                    Operand 4
        T1S                ModRM:reg (w)                    EVEX.vvvv                     ModRM:r/m (r)                     NA

Description
Converts an unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the second
source operand to a double-precision floating-point value in the destination operand. The result is stored in the low
quadword of the destination operand. When conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:64) of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.
EVEX.W0 version: attempt to encode this instruction with EVEX embedded rounding is ignored.

Operation
VCVTUSI2SD (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[63:0] <- Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[63:0]);
ELSE
    DEST[63:0] <- Convert_UInteger_To_Double_Precision_Floating_Point(SRC2[31:0]);
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SD __m128d _mm_cvtu32_sd( __m128d s, unsigned a);
VCVTUSI2SD __m128d _mm_cvtu64_sd( __m128d s, unsigned __int64 a);
VCVTUSI2SD __m128d _mm_cvt_roundu64_sd( __m128d s, unsigned __int64 a, int r);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
See Exceptions Type E3NF if W1, else type E10NF.






platform: x86_64
mnem: VCVTUSI2SS
description:
VCVTUSI2SS-Convert Unsigned Integer to Scalar Single-Precision Floating-Point Value
 Opcode/                                        Op /    64/32        CPUID            Description
 Instruction                                    En      bit Mode     Feature
                                                        Support      Flag
 EVEX.NDS.LIG.F3.0F.W0 7B /r                    T1S     V/V          AVX512F          Convert one signed doubleword integer from r/m32 to
 VCVTUSI2SS xmm1, xmm2, r/m32{er}                                                     one single-precision floating-point value in xmm1.
 EVEX.NDS.LIG.F3.0F.W1 7B /r                    T1S     V/N.E.1      AVX512F          Convert one signed quadword integer from r/m64 to
 VCVTUSI2SS xmm1, xmm2, r/m64{er}                                                     one single-precision floating-point value in xmm1.
NOTES:
1. For this specific instruction, EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is
  used.



                                                       Instruction Operand Encoding
       Op/En                   Operand 1                       Operand 2                      Operand 3                  Operand 4
        T1S                  ModRM:reg (w)                     VEX.vvvv                     ModRM:r/m (r)                   NA

Description
Converts a unsigned doubleword integer (or unsigned quadword integer if operand size is 64 bits) in the source
operand (second operand) to a single-precision floating-point value in the destination operand (first operand). The
source operand can be a general-purpose register or a memory location. The destination operand is an XMM
register. The result is stored in the low doubleword of the destination operand. When a conversion is inexact, the
value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding
control bits.
The second source operand can be a general-purpose register or a 32/64-bit memory location. The first source and
destination operands are XMM registers. Bits (127:32) of the XMM register destination are copied from corre-
sponding bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX.W1 version: promotes the instruction to use 64-bit input value in 64-bit mode.





Operation
VCVTUSI2SS (EVEX encoded version)
IF (SRC2 *is register*) AND (EVEX.b = 1)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF 64-Bit Mode And OperandSize = 64
THEN
    DEST[31:0] <- Convert_UInteger_To_Single_Precision_Floating_Point(SRC[63:0]);
ELSE
    DEST[31:0] <- Convert_UInteger_To_Single_Precision_Floating_Point(SRC[31:0]);
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VCVTUSI2SS __m128 _mm_cvtu32_ss( __m128 s, unsigned a);
VCVTUSI2SS __m128 _mm_cvt_roundu32_ss( __m128 s, unsigned a, int r);
VCVTUSI2SS __m128 _mm_cvtu64_ss( __m128 s, unsigned __int64 a);
VCVTUSI2SS __m128 _mm_cvt_roundu64_ss( __m128 s, unsigned __int64 a, int r);

SIMD Floating-Point Exceptions
Precision

Other Exceptions
See Exceptions Type E3NF.






platform: x86_64
mnem: VDBPSADBW
description:
VDBPSADBW-Double Block Packed Sum-Absolute-Differences (SAD) on Unsigned Bytes
    Opcode/                              Op /   64/32        CPUID          Description
    Instruction                          En     bit Mode     Feature
                                                Support      Flag
    EVEX.NDS.128.66.0F3A.W0 42 /r ib     FVM    V/V          AVX512VL       Compute packed SAD word results of unsigned bytes in
    VDBPSADBW xmm1 {k1}{z}, xmm2,                            AVX512BW       dword block from xmm2 with unsigned bytes of dword
    xmm3/m128, imm8                                                         blocks transformed from xmm3/m128 using the shuffle
                                                                            controls in imm8. Results are written to xmm1 under the
                                                                            writemask k1.
    EVEX.NDS.256.66.0F3A.W0 42 /r ib     FVM    V/V          AVX512VL       Compute packed SAD word results of unsigned bytes in
    VDBPSADBW ymm1 {k1}{z}, ymm2,                            AVX512BW       dword block from ymm2 with unsigned bytes of dword
    ymm3/m256, imm8                                                         blocks transformed from ymm3/m256 using the shuffle
                                                                            controls in imm8. Results are written to ymm1 under the
                                                                            writemask k1.
    EVEX.NDS.512.66.0F3A.W0 42 /r ib     FVM    V/V          AVX512BW       Compute packed SAD word results of unsigned bytes in
    VDBPSADBW zmm1 {k1}{z}, zmm2,                                           dword block from zmm2 with unsigned bytes of dword
    zmm3/m512, imm8                                                         blocks transformed from zmm3/m512 using the shuffle
                                                                            controls in imm8. Results are written to zmm1 under the
                                                                            writemask k1.


                                                  Instruction Operand Encoding
         Op/En               Operand 1                     Operand 2                  Operand 3                  Operand 4
          FVM              ModRM:reg (w)                   EVEX.vvvv                ModRM:r/m (r)                   Imm8

Description
Compute packed SAD (sum of absolute differences) word results of unsigned bytes from two 32-bit dword
elements. Packed SAD word results are calculated in multiples of qword superblocks, producing 4 SAD word results
in each 64-bit superblock of the destination register.
Within each super block of packed word results, the SAD results from two 32-bit dword elements are calculated as
follows:
.     The lower two word results are calculated each from the SAD operation between a sliding dword element within
      a qword superblock from an intermediate vector with a stationary dword element in the corresponding qword
      superblock of the first source operand. The intermediate vector, see "Tmp1" in Figure 5-8, is constructed from
      the second source operand the imm8 byte as shuffle control to select dword elements within a 128-bit lane of
      the second source operand. The two sliding dword elements in a qword superblock of Tmp1 are located at byte
      offset 0 and 1 within the superblock, respectively. The stationary dword element in the qword superblock from
      the first source operand is located at byte offset 0.
.     The next two word results are calculated each from the SAD operation between a sliding dword element within
      a qword superblock from the intermediate vector Tmp1 with a second stationary dword element in the corre-
      sponding qword superblock of the first source operand. The two sliding dword elements in a qword superblock
      of Tmp1 are located at byte offset 2and 3 within the superblock, respectively. The stationary dword element in
      the qword superblock from the first source operand is located at byte offset 4.
.     The intermediate vector is constructed in 128-bits lanes. Within each 128-bit lane, each dword element of the
      intermediate vector is selected by a two-bit field within the imm8 byte on the corresponding 128-bits of the
      second source operand. The imm8 byte serves as dword shuffle control within each 128-bit lanes of the inter-
      mediate vector and the second source operand, similarly to PSHUFD.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, or
a 512/256/128-bit memory location. The destination operand is conditionally updated based on writemask k1 at
16-bit word granularity.





                                               127+128*n                         95+128*n                     63+128*n                                31+128*n                          128*n
               128-bit Lane of Src2                          DW3                            DW2                           DW1                                      DW0


                                                                                                                                                                        00B: DW0
                                                                                                                                                                        01B: DW1
                                                                       imm8 shuffle control                                                                             10B: DW2
                                                                                                                                                                        11B: DW3
                                                                                                     7        5      3          1     0



                                              127+128*n                          95+128*n                     63+128*n                                31+128*n                         128*n
                128-bit Lane of Tmp1

                                                                                                                              Tmp1 qword superblock




                          55     47           39     31 24                                                               39      31         23         15 8
                                                             Tmp1 sliding dword                                                                                       Tmp1 sliding dword

                          63     55           47     39 32                                                           31          23         15        7        0
                                                                                                                                                                      Src1 stationary dword 0
                                                             Src1 stationary dword 1
                            _         _        _      _                                                                   _         _        _             _
                           abs    abs          abs    abs                                                                abs        abs      abs           abs




                                          +                      47    39        31     23 16                                           +
                                                                                                                                                      31         23        15     7       0
                                                                                                Tmp1 sliding dword
                                                                                                                                                                                              Tmp1 sliding dword
                                                                63     55        47     39 32
                                                                                                                                                   31            23        15     7       0
                                                                                                Src1 stationary dword 1
                                                                                                                                                                                              Src1 stationary dword 0
                                                                   _     _        _      _
                                                                                                                                                       _           _        _         _
                                                                 abs    abs       abs   abs
                                                                                                                                                      abs          abs      abs       abs




                                                                             +
                                                                                                                                                                       +
                                               63                           47                           31                                      15                               0
        Destination qword superblock




                                          Figure 5-8. 64-bit Super Block of SAD Operation in VDBPSADBW





Operation
VDBPSADBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Selection of quadruplets:
FOR I = 0 to VL step 128
    TMP1[I+31:I] <- select (SRC2[I+127: I], imm8[1:0])
    TMP1[I+63: I+32] <- select (SRC2[I+127: I], imm8[3:2])
    TMP1[I+95: I+64] <- select (SRC2[I+127: I], imm8[5:4])
    TMP1[I+127: I+96]<- select (SRC2[I+127: I], imm8[7:6])
END FOR

SAD of quadruplets:

FOR I =0 to VL step 64
   TMP_DEST[I+15:I] <- ABS(SRC1[I+7: I] - TMP1[I+7: I]) +
        ABS(SRC1[I+15: I+8]- TMP1[I+15: I+8]) +
        ABS(SRC1[I+23: I+16]- TMP1[I+23: I+16]) +
        ABS(SRC1[I+31: I+24]- TMP1[I+31: I+24])

   TMP_DEST[I+31: I+16] <-ABS(SRC1[I+7: I] - TMP1[I+15: I+8]) +
      ABS(SRC1[I+15: I+8]- TMP1[I+23: I+16]) +
      ABS(SRC1[I+23: I+16]- TMP1[I+31: I+24]) +
      ABS(SRC1[I+31: I+24]- TMP1[I+39: I+32])
   TMP_DEST[I+47: I+32] <-ABS(SRC1[I+39: I+32] - TMP1[I+23: I+16]) +
      ABS(SRC1[I+47: I+40]- TMP1[I+31: I+24]) +
      ABS(SRC1[I+55: I+48]- TMP1[I+39: I+32]) +
      ABS(SRC1[I+63: I+56]- TMP1[I+47: I+40])

   TMP_DEST[I+63: I+48] <-ABS(SRC1[I+39: I+32] - TMP1[I+31: I+24]) +
      ABS(SRC1[I+47: I+40] - TMP1[I+39: I+32]) +
      ABS(SRC1[I+55: I+48] - TMP1[I+47: I+40]) +
      ABS(SRC1[I+63: I+56] - TMP1[I+55: I+48])
ENDFOR

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VDBPSADBW __m512i _mm512_dbsad_epu8(__m512i a, __m512i b);
VDBPSADBW __m512i _mm512_mask_dbsad_epu8(__m512i s, __mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m512i _mm512_maskz_dbsad_epu8(__mmask32 m, __m512i a, __m512i b);
VDBPSADBW __m256i _mm256_dbsad_epu8(__m256i a, __m256i b);
VDBPSADBW __m256i _mm256_mask_dbsad_epu8(__m256i s, __mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m256i _mm256_maskz_dbsad_epu8(__mmask16 m, __m256i a, __m256i b);
VDBPSADBW __m128i _mm_dbsad_epu8(__m128i a, __m128i b);
VDBPSADBW __m128i _mm_mask_dbsad_epu8(__m128i s, __mmask8 m, __m128i a, __m128i b);
VDBPSADBW __m128i _mm_maskz_dbsad_epu8(__mmask8 m, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4NF.nb.






platform: x86_64
mnem: VEXPANDPD
description:
VEXPANDPD-Load Sparse Packed Double-Precision Floating-Point Values from Dense Memory
 Opcode/                                      Op /     64/32      CPUID          Description
 Instruction                                  En       bit Mode   Feature
                                                       Support    Flag
 EVEX.128.66.0F38.W1 88 /r                    T1S      V/V        AVX512VL       Expand packed double-precision floating-point values
 VEXPANDPD xmm1 {k1}{z},                                          AVX512F        from xmm2/m128 to xmm1 using writemask k1.
 xmm2/m128
 EVEX.256.66.0F38.W1 88 /r                    T1S      V/V        AVX512VL       Expand packed double-precision floating-point values
 VEXPANDPD ymm1 {k1}{z}, ymm2/m256                                AVX512F        from ymm2/m256 to ymm1 using writemask k1.
 EVEX.512.66.0F38.W1 88 /r                    T1S      V/V        AVX512F        Expand packed double-precision floating-point values
 VEXPANDPD zmm1 {k1}{z}, zmm2/m512                                               from zmm2/m512 to zmm1 using writemask k1.



                                                     Instruction Operand Encoding
       Op/En                Operand 1                     Operand 2                     Operand 3                  Operand 4
        T1S               ModRM:reg (w)                 ModRM:r/m (r)                      NA                         NA

Description
Expand (load) up to 8/4/2, contiguous, double-precision floating-point values of the input vector in the source
operand (the second operand) to sparse elements in the destination operand (the first operand) selected by the
writemask k1.
The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a
512/256/128-bit memory location.
The input vector starts from the lowest element in the source operand. The writemask register k1 selects the desti-
nation elements (a partial vector or sparse elements if less than 8 elements) to be replaced by the ascending
elements in the input vector. Destination elements not selected by the writemask k1 are either unmodified or
zeroed, depending on EVEX.z.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VEXPANDPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
k<-0
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+63:i] <- SRC[k+63:k];
               k <- k + 64
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPD __m512d _mm512_mask_expand_pd( __m512d s, __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_maskz_expand_pd( __mmask8 k, __m512d a);
VEXPANDPD __m512d _mm512_mask_expandloadu_pd( __m512d s, __mmask8 k, void * a);
VEXPANDPD __m512d _mm512_maskz_expandloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m256d _mm256_mask_expand_pd( __m256d s, __mmask8 k, __m256d a);
VEXPANDPD __m256d _mm256_maskz_expand_pd( __mmask8 k, __m256d a);
VEXPANDPD __m256d _mm256_mask_expandloadu_pd( __m256d s, __mmask8 k, void * a);
VEXPANDPD __m256d _mm256_maskz_expandloadu_pd( __mmask8 k, void * a);
VEXPANDPD __m128d _mm_mask_expand_pd( __m128d s, __mmask8 k, __m128d a);
VEXPANDPD __m128d _mm_maskz_expand_pd( __mmask8 k, __m128d a);
VEXPANDPD __m128d _mm_mask_expandloadu_pd( __m128d s, __mmask8 k, void * a);
VEXPANDPD __m128d _mm_maskz_expandloadu_pd( __mmask8 k, void * a);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.nb.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VEXPANDPS
description:
VEXPANDPS-Load Sparse Packed Single-Precision Floating-Point Values from Dense Memory
 Opcode/                                       Op /    64/32       CPUID          Description
 Instruction                                   En      bit Mode    Feature
                                                       Support     Flag
 EVEX.128.66.0F38.W0 88 /r                     T1S     V/V         AVX512VL       Expand packed single-precision floating-point values
 VEXPANDPS xmm1 {k1}{z}, xmm2/m128                                 AVX512F        from xmm2/m128 to xmm1 using writemask k1.
 EVEX.256.66.0F38.W0 88 /r                     T1S     V/V         AVX512VL       Expand packed single-precision floating-point values
 VEXPANDPS ymm1 {k1}{z}, ymm2/m256                                 AVX512F        from ymm2/m256 to ymm1 using writemask k1.
 EVEX.512.66.0F38.W0 88 /r                     T1S     V/V         AVX512F        Expand packed single-precision floating-point values
 VEXPANDPS zmm1 {k1}{z}, zmm2/m512                                                from zmm2/m512 to zmm1 using writemask k1.



                                                     Instruction Operand Encoding
       Op/En                 Operand 1                       Operand 2                  Operand 3                   Operand 4
        T1S                ModRM:reg (w)                 ModRM:r/m (r)                      NA                          NA

Description
Expand (load) up to 16/8/4, contiguous, single-precision floating-point values of the input vector in the source
operand (the second operand) to sparse elements of the destination operand (the first operand) selected by the
writemask k1.
The destination operand is a ZMM/YMM/XMM register, the source operand can be a ZMM/YMM/XMM register or a
512/256/128-bit memory location.
The input vector starts from the lowest element in the source operand. The writemask k1 selects the destination
elements (a partial vector or sparse elements if less than 16 elements) to be replaced by the ascending elements
in the input vector. Destination elements not selected by the writemask k1 are either unmodified or zeroed,
depending on EVEX.z.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Note that the compressed displacement assumes a pre-scaling (N) corresponding to the size of one single element
instead of the size of the full vector.

Operation
VEXPANDPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
k<-0
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               DEST[i+31:i] <- SRC[k+31:k];
               k <- k + 32
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VEXPANDPS __m512 _mm512_mask_expand_ps( __m512 s, __mmask16 k, __m512 a);
VEXPANDPS __m512 _mm512_maskz_expand_ps( __mmask16 k, __m512 a);
VEXPANDPS __m512 _mm512_mask_expandloadu_ps( __m512 s, __mmask16 k, void * a);
VEXPANDPS __m512 _mm512_maskz_expandloadu_ps( __mmask16 k, void * a);
VEXPANDPD __m256 _mm256_mask_expand_ps( __m256 s, __mmask8 k, __m256 a);
VEXPANDPD __m256 _mm256_maskz_expand_ps( __mmask8 k, __m256 a);
VEXPANDPD __m256 _mm256_mask_expandloadu_ps( __m256 s, __mmask8 k, void * a);
VEXPANDPD __m256 _mm256_maskz_expandloadu_ps( __mmask8 k, void * a);
VEXPANDPD __m128 _mm_mask_expand_ps( __m128 s, __mmask8 k, __m128 a);
VEXPANDPD __m128 _mm_maskz_expand_ps( __mmask8 k, __m128 a);
VEXPANDPD __m128 _mm_mask_expandloadu_ps( __m128 s, __mmask8 k, void * a);
VEXPANDPD __m128 _mm_maskz_expandloadu_ps( __mmask8 k, void * a);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.nb.
#UD                    If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VERR
description:
VERR/VERW-Verify a Segment for Reading or Writing
 Opcode                    Instruction                  Op/   64-Bit   Compat/ Description
                                                        En    Mode     Leg Mode
 0F 00 /4                  VERR r/m16                   M     Valid    Valid       Set ZF=1 if segment specified with r/m16 can
                                                                                   be read.
 0F 00 /5                  VERW r/m16                   M     Valid    Valid       Set ZF=1 if segment specified with r/m16 can
                                                                                   be written.



                                                    Instruction Operand Encoding
    Op/En             Operand 1                       Operand 2                Operand 3                    Operand 4
     M              ModRM:r/m (r)                        NA                        NA                           NA


Description
Verifies whether the code or data segment specified with the source operand is readable (VERR) or writable
(VERW) from the current privilege level (CPL). The source operand is a 16-bit register or a memory location that
contains the segment selector for the segment to be verified. If the segment is accessible and readable (VERR) or
writable (VERW), the ZF flag is set; otherwise, the ZF flag is cleared. Code segments are never verified as writable.
This check cannot be performed on system segments.
To set the ZF flag, the following conditions must be met:
.    The segment selector is not NULL.
.    The selector must denote a descriptor within the bounds of the descriptor table (GDT or LDT).
.    The selector must denote the descriptor of a code or data segment (not that of a system segment or gate).
.    For the VERR instruction, the segment must be readable.
.    For the VERW instruction, the segment must be a writable data segment.
.    If the segment is not a conforming code segment, the segment's DPL must be greater than or equal to (have
     less or the same privilege as) both the CPL and the segment selector's RPL.
The validation performed is the same as is performed when a segment selector is loaded into the DS, ES, FS, or GS
register, and the indicated access (read or write) is performed. The segment selector's value cannot result in a
protection exception, enabling the software to anticipate possible segment access problems.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. The operand size is fixed at 16 bits.

Operation
IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
    THEN ZF <- 0; FI;

Read segment descriptor;

IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
or (SegmentDescriptor(Type) != conforming code segment)
and (CPL > DPL) or (RPL > DPL)
    THEN
        ZF <- 0;
    ELSE
        IF ((Instruction = VERR) and (Segment readable))
        or ((Instruction = VERW) and (Segment writable))
              THEN
                   ZF <- 1;
        FI;
FI;




Flags Affected
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or writable (VERW); otherwise, it is set to 0.

Protected Mode Exceptions
The only exceptions generated for these instructions are those related to illegal addressing of the source operand.
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                     selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                  The VERR and VERW instructions are not recognized in real-address mode.
                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#UD                  The VERR and VERW instructions are not recognized in virtual-8086 mode.
                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the memory address is in a non-canonical form.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.






platform: x86_64
mnem: VEXP2PD
description:
VEXP2PD-Approximation to the Exponential 2^x of Packed Double-Precision Floating-Point
Values with Less Than 2^-23 Relative Error
 Opcode/                            Op /    64/32         CPUID          Description
 Instruction                        En      bit Mode      Feature
                                            Support       Flag
 EVEX.512.66.0F38.W1 C8 /r          FV      V/V           AVX512ER       Computes approximations to the exponential 2^x (with less
 VEXP2PD zmm1 {k1}{z},                                                   than 2^-23 of maximum relative error) of the packed double-
 zmm2/m512/m64bcst {sae}                                                 precision floating-point values from zmm2/m512/m64bcst and
                                                                         stores the floating-point result in zmm1with writemask k1.



                                                    Instruction Operand Encoding
       Op/En                  Operand 1                      Operand 2                     Operand 3                     Operand 4
         FV                ModRM:reg (r, w)                ModRM:r/m (r)                       NA                             NA

Description
Computes the approximate base-2 exponential evaluation of the double-precision floating-point values in the
source operand (the second operand) and stores the results to the destination operand (the first operand) using
the writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VEXP2PD
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+63:i] <- EXP2_23_DP(SRC[63:0])
                    ELSE DEST[i+63:i] <- EXP2_23_DP(SRC[i+63:i])
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+63:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+63:i] <- 0
         FI;
    FI;
ENDFOR;





                                                      Table 5-4. Special Values Behavior
               Source Input                   Result                                            Comments
               NaN                            QNaN(src)                                         If (SRC = SNaN) then #I
               +inf                             +inf
               +/-0                           1.0f                                              Exact result
               -inf                             +0.0f
               Integral value N               2^ (N)                                            Exact result

Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PD __m512d _mm512_exp2a23_round_pd (__m512d a, int sae);
VEXP2PD __m512d _mm512_mask_exp2a23_round_pd (__m512d a, __mmask8 m, __m512d b, int sae);
VEXP2PD __m512d _mm512_maskz_exp2a23_round_pd ( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions
Invalid (if SNaN input), Overflow

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VEXP2PS
description:
VEXP2PS-Approximation to the Exponential 2^x of Packed Single-Precision Floating-Point
Values with Less Than 2^-23 Relative Error
 Opcode/                             Op /    64/32         CPUID           Description
 Instruction                         En      bit Mode      Feature
                                             Support       Flag
 EVEX.512.66.0F38.W0 C8 /r           FV      V/V           AVX512ER        Computes approximations to the exponential 2^x (with less
 VEXP2PS zmm1 {k1}{z},                                                     than 2^-23 of maximum relative error) of the packed single-
 zmm2/m512/m32bcst {sae}                                                   precision floating-point values from zmm2/m512/m32bcst and
                                                                           stores the floating-point result in zmm1with writemask k1.



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                        Operand 2                      Operand 3                      Operand 4
       FV                ModRM:reg (r, w)                  ModRM:r/m (r)                        NA                                NA

Description
Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the
source operand (the second operand) and store the results in the destination operand (the first operand) using the
writemask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VEXP2xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VEXP2PS
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
              IF (EVEX.b = 1) AND (SRC *is memory*)
                   THEN DEST[i+31:i] <- EXP2_23_SP(SRC[31:0])
                   ELSE DEST[i+31:i] <- EXP2_23_SP(SRC[i+31:i])
              FI;
    ELSE
         IF *merging-masking*                 ; merging-masking
              THEN *DEST[i+31:i] remains unchanged*
              ELSE                            ; zeroing-masking
                   DEST[i+31:i] <- 0
         FI;
    FI;
ENDFOR;





                                                      Table 5-5. Special Values Behavior
               Source Input                   Result                                            Comments
               NaN                            QNaN(src)                                         If (SRC = SNaN) then #I
               +inf                             +inf
               +/-0                           1.0f                                              Exact result
               -inf                             +0.0f
               Integral value N               2^ (N)                                            Exact result

Intel C/C++ Compiler Intrinsic Equivalent
VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);
VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);
VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);

SIMD Floating-Point Exceptions
Invalid (if SNaN input), Overflow

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VEXTRACTF128
description:
VEXTRACTF128/VEXTRACTF32x4/VEXTRACTF64x2/VEXTRACTF32x8/VEXTRACTF64x4-Extr
act Packed Floating-Point Values
 Opcode/                                  Op /    64/32        CPUID      Description
 Instruction                              En      bit Mode     Feature
                                                  Support      Flag
 VEX.256.66.0F3A.W0 19 /r ib              RMI     V/V          AVX        Extract 128 bits of packed floating-point values
 VEXTRACTF128 xmm1/m128, ymm2,                                            from ymm2 and store results in xmm1/m128.
 imm8
 EVEX.256.66.0F3A.W0 19 /r ib             T4      V/V          AVX512VL   Extract 128 bits of packed single-precision floating-
 VEXTRACTF32X4 xmm1/m128 {k1}{z},                              AVX512F    point values from ymm2 and store results in
 ymm2, imm8                                                               xmm1/m128 subject to writemask k1.
 EVEX.512.66.0F3A.W0 19 /r ib             T4      V/V          AVX512F    Extract 128 bits of packed single-precision floating-
 VEXTRACTF32x4 xmm1/m128 {k1}{z},                                         point values from zmm2 and store results in
 zmm2, imm8                                                               xmm1/m128 subject to writemask k1.
 EVEX.256.66.0F3A.W1 19 /r ib             T2      V/V          AVX512VL   Extract 128 bits of packed double-precision
 VEXTRACTF64X2 xmm1/m128 {k1}{z},                              AVX512DQ   floating-point values from ymm2 and store results
 ymm2, imm8                                                               in xmm1/m128 subject to writemask k1.
 EVEX.512.66.0F3A.W1 19 /r ib             T2      V/V          AVX512DQ   Extract 128 bits of packed double-precision
 VEXTRACTF64X2 xmm1/m128 {k1}{z},                                         floating-point values from zmm2 and store results
 zmm2, imm8                                                               in xmm1/m128 subject to writemask k1.
 EVEX.512.66.0F3A.W0 1B /r ib             T8      V/V          AVX512DQ   Extract 256 bits of packed single-precision floating-
 VEXTRACTF32X8 ymm1/m256 {k1}{z},                                         point values from zmm2 and store results in
 zmm2, imm8                                                               ymm1/m256 subject to writemask k1.
 EVEX.512.66.0F3A.W1 1B /r ib             T4      V/V          AVX512F    Extract 256 bits of packed double-precision
 VEXTRACTF64x4 ymm1/m256 {k1}{z},                                         floating-point values from zmm2 and store results
 zmm2, imm8                                                               in ymm1/m256 subject to writemask k1.



                                               Instruction Operand Encoding
       Op/En                Operand 1                   Operand 2             Operand 3                     Operand 4
        RMI               ModRM:r/m (w)             ModRM:reg (r)               Imm8                           NA
     T2, T4, T8           ModRM:r/m (w)             ModRM:reg (r)               Imm8                           NA

Description
VEXTRACTF128/VEXTRACTF32x4 and VEXTRACTF64x2 extract 128-bits of single-precision floating-point values
from the source operand (the second operand) and store to the low 128-bit of the destination operand (the first
operand). The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or
imm8[1:0] as the multiply factor. The destination may be either a vector register or an 128-bit memory location.
VEXTRACTF32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the
writemask.
VEXTRACTF32x8 and VEXTRACTF64x4 extract 256-bits of double-precision floating-point values from the source
operand (second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit
data extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply
factor The destination may be either a vector register or a 256-bit memory location.
VEXTRACTF64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The high 6 bits of the immediate are ignored.
If VEXTRACTF128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.





Operation
VEXTRACTF32x4 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;
FOR j <- 0 TO 3
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+31:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:128] <- 0





VEXTRACTF32x4 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;

FOR j <- 0 TO 3
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE *DEST[i+31:i] remains unchanged*     ; merging-masking
   FI;
ENDFOR





VEXTRACTF64x2 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;

FOR j <- 0 TO 1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:128] <- 0





VEXTRACTF64x2 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;

FOR j <- 0 TO 1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE *DEST[i+63:i] remains unchanged*         ; merging-masking
   FI;
ENDFOR

VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 7
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:256] <- 0





VEXTRACTF32x8 (EVEX.U1.512 encoded version) when destination is memory
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 7
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE *DEST[i+31:i] remains unchanged*         ; merging-masking
   FI;
ENDFOR

VEXTRACTF64x4 (EVEX.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 3
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:256] <- 0

VEXTRACTF64x4 (EVEX.512 encoded version) when destination is memory
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 3
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE      ; merging-masking
             *DEST[i+63:i] remains unchanged*
   FI;
ENDFOR





VEXTRACTF128 (memory destination form)
CASE (imm8[0]) OF
   0: DEST[127:0] <-SRC1[127:0]
   1: DEST[127:0] <-SRC1[255:128]
ESAC.

VEXTRACTF128 (register destination form)
CASE (imm8[0]) OF
   0: DEST[127:0] <-SRC1[127:0]
   1: DEST[127:0] <-SRC1[255:128]
ESAC.
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VEXTRACTF32x4 __m128 _mm512_extractf32x4_ps(__m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm512_maskz_extractf32x4_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_extractf32x4_ps(__m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_mask_extractf32x4_ps(__m128 s, __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x4 __m128 _mm256_maskz_extractf32x4_ps( __mmask8 k, __m256 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_extractf32x8_ps(__m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_mask_extractf32x8_ps(__m256 s, __mmask8 k, __m512 a, const int nidx);
VEXTRACTF32x8 __m256 _mm512_maskz_extractf32x8_ps( __mmask8 k, __m512 a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_extractf64x2_pd(__m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm512_maskz_extractf64x2_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_extractf64x2_pd(__m256d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_mask_extractf64x2_pd(__m128d s, __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x2 __m128d _mm256_maskz_extractf64x2_pd( __mmask8 k, __m256d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_extractf64x4_pd( __m512d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_mask_extractf64x4_pd(__m256d s, __mmask8 k, __m512d a, const int nidx);
VEXTRACTF64x4 __m256d _mm512_maskz_extractf64x4_pd( __mmask8 k, __m512d a, const int nidx);
VEXTRACTF128 __m128 _mm256_extractf128_ps (__m256 a, int offset);
VEXTRACTF128 __m128d _mm256_extractf128_pd (__m256d a, int offset);
VEXTRACTF128 __m128i_mm256_extractf128_si256(__m256i a, int offset);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6NF.
#UD                    IF VEX.L = 0.
#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: VEXTRACTI128
description:
VEXTRACTI128/VEXTRACTI32x4/VEXTRACTI64x2/VEXTRACTI32x8/VEXTRACTI64x4-Extract
packed Integer Values
 Opcode/                                 Op /    64/32       CPUID       Description
 Instruction                             En      bit Mode    Feature
                                                 Support     Flag
 VEX.256.66.0F3A.W0 39 /r ib             RMI     V/V         AVX2        Extract 128 bits of integer data from ymm2 and
 VEXTRACTI128 xmm1/m128, ymm2,                                           store results in xmm1/m128.
 imm8
 EVEX.256.66.0F3A.W0 39 /r ib            T4      V/V         AVX512VL    Extract 128 bits of double-word integer values
 VEXTRACTI32X4 xmm1/m128 {k1}{z},                            AVX512F     from ymm2 and store results in xmm1/m128
 ymm2, imm8                                                              subject to writemask k1.
 EVEX.512.66.0F3A.W0 39 /r ib            T4      V/V         AVX512F     Extract 128 bits of double-word integer values
 VEXTRACTI32x4 xmm1/m128 {k1}{z},                                        from zmm2 and store results in xmm1/m128
 zmm2, imm8                                                              subject to writemask k1.
 EVEX.256.66.0F3A.W1 39 /r ib            T2      V/V         AVX512VL    Extract 128 bits of quad-word integer values from
 VEXTRACTI64X2 xmm1/m128 {k1}{z},                            AVX512DQ    ymm2 and store results in xmm1/m128 subject to
 ymm2, imm8                                                              writemask k1.
 EVEX.512.66.0F3A.W1 39 /r ib            T2      V/V         AVX512DQ    Extract 128 bits of quad-word integer values from
 VEXTRACTI64X2 xmm1/m128 {k1}{z},                                        zmm2 and store results in xmm1/m128 subject to
 zmm2, imm8                                                              writemask k1.
 EVEX.512.66.0F3A.W0 3B /r ib            T8      V/V         AVX512DQ    Extract 256 bits of double-word integer values
 VEXTRACTI32X8 ymm1/m256 {k1}{z},                                        from zmm2 and store results in ymm1/m256
 zmm2, imm8                                                              subject to writemask k1.
 EVEX.512.66.0F3A.W1 3B /r ib            T4      V/V         AVX512F     Extract 256 bits of quad-word integer values from
 VEXTRACTI64x4 ymm1/m256 {k1}{z},                                        zmm2 and store results in ymm1/m256 subject to
 zmm2, imm8                                                              writemask k1.



                                              Instruction Operand Encoding
        Op/En              Operand 1                   Operand 2              Operand 3                  Operand 4
         RMI             ModRM:r/m (w)              ModRM:reg (r)               Imm8                         NA
      T2, T4, T8         ModRM:r/m (w)              ModRM:reg (r)               Imm8                         NA

Description
VEXTRACTI128/VEXTRACTI32x4 and VEXTRACTI64x2 extract 128-bits of doubleword integer values from the
source operand (the second operand) and store to the low 128-bit of the destination operand (the first operand).
The 128-bit data extraction occurs at an 128-bit granular offset specified by imm8[0] (256-bit) or imm8[1:0] as
the multiply factor. The destination may be either a vector register or an 128-bit memory location.
VEXTRACTI32x4: The low 128-bit of the destination operand is updated at 32-bit granularity according to the
writemask.
VEXTRACTI64x2: The low 128-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEXTRACTI32x8 and VEXTRACTI64x4 extract 256-bits of quadword integer values from the source operand (the
second operand) and store to the low 256-bit of the destination operand (the first operand). The 256-bit data
extraction occurs at an 256-bit granular offset specified by imm8[0] (256-bit) or imm8[0] as the multiply factor
The destination may be either a vector register or a 256-bit memory location.
VEXTRACTI32x8: The low 256-bit of the destination operand is updated at 32-bit granularity according to the
writemask.





VEXTRACTI64x4: The low 256-bit of the destination operand is updated at 64-bit granularity according to the
writemask.
VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
The high 7 bits (6 bits in EVEX.512) of the immediate are ignored.
If VEXTRACTI128 is encoded with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.

Operation
VEXTRACTI32x4 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;
FOR j <- 0 TO 3
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+31:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+31:i] <- 0
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:128] <- 0

VEXTRACTI32x4 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.



FI;

FOR j <- 0 TO 3
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE *DEST[i+31:i] remains unchanged*         ; merging-masking
   FI;
ENDFOR

VEXTRACTI64x2 (EVEX encoded versions) when destination is a register
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;

FOR j <- 0 TO 1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:128] <- 0





VEXTRACTI64x2 (EVEX encoded versions) when destination is memory
VL = 256, 512
IF VL = 256
    CASE (imm8[0]) OF
         0: TMP_DEST[127:0] <- SRC1[127:0]
         1: TMP_DEST[127:0] <- SRC1[255:128]
    ESAC.
FI;
IF VL = 512
    CASE (imm8[1:0]) OF
         00: TMP_DEST[127:0] <- SRC1[127:0]
         01: TMP_DEST[127:0] <- SRC1[255:128]
         10: TMP_DEST[127:0] <- SRC1[383:256]
         11: TMP_DEST[127:0] <- SRC1[511:384]
    ESAC.
FI;

FOR j <- 0 TO 1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE *DEST[i+63:i] remains unchanged*         ; merging-masking
   FI;
ENDFOR

VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 7
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:256] <- 0





VEXTRACTI32x8 (EVEX.U1.512 encoded version) when destination is memory
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 7
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE *DEST[i+31:i] remains unchanged*         ; merging-masking
   FI;
ENDFOR

VEXTRACTI64x4 (EVEX.512 encoded version) when destination is a register
VL = 512
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.

FOR j <- 0 TO 3
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:256] <- 0

VEXTRACTI64x4 (EVEX.512 encoded version) when destination is memory
CASE (imm8[0]) OF
   0: TMP_DEST[255:0] <- SRC1[255:0]
   1: TMP_DEST[255:0] <- SRC1[511:256]
ESAC.
FOR j <- 0 TO 3
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE *DEST[i+63:i] remains unchanged* ; merging-masking
   FI;
ENDFOR





VEXTRACTI128 (memory destination form)
CASE (imm8[0]) OF
   0: DEST[127:0] <-SRC1[127:0]
   1: DEST[127:0] <-SRC1[255:128]
ESAC.

VEXTRACTI128 (register destination form)
CASE (imm8[0]) OF
   0: DEST[127:0] <-SRC1[127:0]
   1: DEST[127:0] <-SRC1[255:128]
ESAC.
DEST[MAX_VL-1:128] <-0

Intel C/C++ Compiler Intrinsic Equivalent
VEXTRACTI32x4 __m128i _mm512_extracti32x4_epi32(__m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm512_maskz_extracti32x4_epi32( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_extracti32x4_epi32(__m256i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_mask_extracti32x4_epi32(__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI32x4 __m128i _mm256_maskz_extracti32x4_epi32( __mmask8 k, __m256i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_extracti32x8_epi32(__m512i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_mask_extracti32x8_epi32(__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI32x8 __m256i _mm512_maskz_extracti32x8_epi32( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_extracti64x2_epi64(__m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm512_maskz_extracti64x2_epi64( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_extracti64x2_epi64(__m256i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_mask_extracti64x2_epi64(__m128i s, __mmask8 k, __m256i a, const int nidx);
VEXTRACTI64x2 __m128i _mm256_maskz_extracti64x2_epi64( __mmask8 k, __m256i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_extracti64x4_epi64(__m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_mask_extracti64x4_epi64(__m256i s, __mmask8 k, __m512i a, const int nidx);
VEXTRACTI64x4 __m256i _mm512_maskz_extracti64x4_epi64( __mmask8 k, __m512i a, const int nidx);
VEXTRACTI128 __m128i _mm256_extracti128_si256(__m256i a, int offset);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instructions, see Exceptions Type 6;
EVEX-encoded instructions, see Exceptions Type E6NF.
#UD                    IF VEX.L = 0.
#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






