# instructions

platform: x86_64
mnem: PMADDUBSW
description:
PMADDUBSW - Multiply and Add Packed Signed and Unsigned Bytes
Opcode/                                             Op/    64/32 bit   CPUID         Description
Instruction                                         En     Mode        Feature
                                                           Support     Flag
0F 38 04 /r1                                        RM     V/V         SSSE3         Multiply signed and unsigned bytes, add
PMADDUBSW mm1, mm2/m64                                                               horizontal pair of signed words, pack
                                                                                     saturated signed-words to mm1.
66 0F 38 04 /r                                      RM     V/V         SSSE3         Multiply signed and unsigned bytes, add
PMADDUBSW xmm1, xmm2/m128                                                            horizontal pair of signed words, pack
                                                                                     saturated signed-words to xmm1.
VEX.NDS.128.66.0F38.WIG 04 /r                       RVM V/V            AVX           Multiply signed and unsigned bytes, add
VPMADDUBSW xmm1, xmm2, xmm3/m128                                                     horizontal pair of signed words, pack
                                                                                     saturated signed-words to xmm1.
VEX.NDS.256.66.0F38.WIG 04 /r                       RVM V/V            AVX2          Multiply signed and unsigned bytes, add
VPMADDUBSW ymm1, ymm2, ymm3/m256                                                     horizontal pair of signed words, pack
                                                                                     saturated signed-words to ymm1.
EVEX.NDS.128.66.0F38.WIG 04 /r                      FVM V/V            AVX512VL Multiply signed and unsigned bytes, add
VPMADDUBSW xmm1 {k1}{z}, xmm2, xmm3/m128                               AVX512BW horizontal pair of signed words, pack
                                                                                saturated signed-words to xmm1 under
                                                                                writemask k1.
EVEX.NDS.256.66.0F38.WIG 04 /r                      FVM V/V            AVX512VL Multiply signed and unsigned bytes, add
VPMADDUBSW ymm1 {k1}{z}, ymm2, ymm3/m256                               AVX512BW horizontal pair of signed words, pack
                                                                                saturated signed-words to ymm1 under
                                                                                writemask k1.
EVEX.NDS.512.66.0F38.WIG 04 /r                      FVM V/V            AVX512BW Multiply signed and unsigned bytes, add
VPMADDUBSW zmm1 {k1}{z}, zmm2, zmm3/m512                                        horizontal pair of signed words, pack
                                                                                saturated signed-words to zmm1 under
                                                                                writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En             Operand 1                    Operand 2                      Operand 3                    Operand 4
    RM           ModRM:reg (r, w)               ModRM:r/m (r)                       NA                            NA
    RVM           ModRM:reg (w)                  VEX.vvvv (r)                  ModRM:r/m (r)                      NA
    FVM           ModRM:reg (w)                 EVEX.vvvv (r)                  ModRM:r/m (r)                      NA


Description
(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand (first operand) with the corre-
sponding signed byte of the source operand (second operand), producing intermediate signed 16-bit integers. Each
adjacent pair of signed words is added and the saturated result is packed to the destination operand. For example,
the lowest-order bytes (bits 7-0) in the source and destination operands are multiplied and the intermediate signed
word result is added with the corresponding intermediate result from the 2nd lowest-order bytes (bits 15-8) of the
operands; the sign-saturated result is stored in the lowest word of the destination register (15-0). The same oper-
ation is performed on the other pairs of adjacent bytes. Both operands can be MMX register or XMM registers. When
the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15.




128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 and EVEX.128 encoded versions: The first source and destination operands are XMM registers. The
second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corre-
sponding destination register are zeroed.
VEX.256 and EVEX.256 encoded versions: The second source operand can be an YMM register or a 256-bit memory
location. The first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding
ZMM register are zeroed.
EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The
first source and destination operands are ZMM registers.

Operation
PMADDUBSW (with 64 bit operands)
  DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
  DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
  DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
  DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);
PMADDUBSW (with 128 bit operands)
  DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
  // Repeat operation for 2nd through 7th word
  SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);

VPMADDUBSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 7th word
DEST[127:112] <- SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
DEST[VLMAX-1:128] <- 0

VPMADDUBSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 15th word
DEST[255:240] <- SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])
DEST[VLMAX-1:256] <- 0

VPMADDUBSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- SaturateToSignedWord(SRC2[i+15:i+8]* SRC1[i+15:i+8] + SRC2[i+7:i]*SRC1[i+7:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalents
VPMADDUBSW __m512i _mm512_mddubs_epi16( __m512i a, __m512i b);
VPMADDUBSW __m512i _mm512_mask_mddubs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMADDUBSW __m512i _mm512_maskz_mddubs_epi16( __mmask32 k, __m512i a, __m512i b);
VPMADDUBSW __m256i _mm256_mask_mddubs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMADDUBSW __m256i _mm256_maskz_mddubs_epi16( __mmask16 k, __m256i a, __m256i b);
VPMADDUBSW __m128i _mm_mask_mddubs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMADDUBSW __m128i _mm_maskz_maddubs_epi16( __mmask8 k, __m128i a, __m128i b);
PMADDUBSW: __m64 _mm_maddubs_pi16 (__m64 a, __m64 b)
(V)PMADDUBSW: __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
VPMADDUBSW:       __m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PMADDWD
description:
PMADDWD-Multiply and Add Packed Integers
Opcode/                                            Op/   64/32 bit   CPUID         Description
Instruction                                        En    Mode        Feature
                                                         Support     Flag
0F F5 /r1                                          RM    V/V         MMX           Multiply the packed words in mm by the packed
PMADDWD mm, mm/m64                                                                 words in mm/m64, add adjacent doubleword
                                                                                   results, and store in mm.
66 0F F5 /r                                        RM    V/V         SSE2          Multiply the packed word integers in xmm1 by
PMADDWD xmm1, xmm2/m128                                                            the packed word integers in xmm2/m128, add
                                                                                   adjacent doubleword results, and store in
                                                                                   xmm1.
VEX.NDS.128.66.0F.WIG F5 /r                        RVM V/V           AVX           Multiply the packed word integers in xmm2 by
VPMADDWD xmm1, xmm2, xmm3/m128                                                     the packed word integers in xmm3/m128, add
                                                                                   adjacent doubleword results, and store in
                                                                                   xmm1.
VEX.NDS.256.66.0F.WIG F5 /r                        RVM V/V           AVX2          Multiply the packed word integers in ymm2 by
VPMADDWD ymm1, ymm2, ymm3/m256                                                     the packed word integers in ymm3/m256, add
                                                                                   adjacent doubleword results, and store in
                                                                                   ymm1.
EVEX.NDS.128.66.0F.WIG F5 /r                       FVM V/V           AVX512VL Multiply the packed word integers in xmm2 by
VPMADDWD xmm1 {k1}{z}, xmm2, xmm3/m128                               AVX512BW the packed word integers in xmm3/m128, add
                                                                              adjacent doubleword results, and store in
                                                                              xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG F5 /r                       FVM V/V           AVX512VL Multiply the packed word integers in ymm2 by
VPMADDWD ymm1 {k1}{z}, ymm2, ymm3/m256                               AVX512BW the packed word integers in ymm3/m256, add
                                                                              adjacent doubleword results, and store in
                                                                              ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG F5 /r                       FVM V/V           AVX512BW Multiply the packed word integers in zmm2 by
VPMADDWD zmm1 {k1}{z}, zmm2, zmm3/m512                                        the packed word integers in zmm3/m512, add
                                                                              adjacent doubleword results, and store in
                                                                              zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En              Operand 1                   Operand 2                    Operand 3                     Operand 4
    RM            ModRM:reg (r, w)              ModRM:r/m (r)                     NA                            NA
    RVM            ModRM:reg (w)                 VEX.vvvv (r)                ModRM:r/m (r)                      NA
    FVM            ModRM:reg (w)                EVEX.vvvv (r)                ModRM:r/m (r)                      NA


Description
Multiplies the individual signed words of the destination operand (first operand) by the corresponding signed words
of the source operand (second operand), producing temporary signed, doubleword results. The adjacent double-
word results are then summed and stored in the destination operand. For example, the corresponding low-order
words (15-0) and (31-16) in the source and destination operands are multiplied by one another and the double-
word results are added together and stored in the low doubleword of the destination register (31-0). The same
operation is performed on the other pairs of adjacent words. (Figure 4-11 shows this operation when using 64-bit
operands).





The (V)PMADDWD instruction wraps around only in one situation: when the 2 pairs of words being operated on in
a group are all 8000H. In this case, the result wraps around to 80000000H.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version: The first source and destination operands are MMX registers. The second source operand is an
MMX register or a 64-bit memory location.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX.512 encoded version: The second source operand can be an ZMM register or a 512-bit memory location. The
first source and destination operands are ZMM registers.



                                     SRC         X3         X2     X1         X0


                                     DEST         Y3         Y2     Y1         Y0


                       TEMP        X3 * Y3             X2 * Y2           X1 * Y1       X0 * Y0


                                     DEST       (X3*Y3) + (X2*Y2) (X1*Y1) + (X0*Y0)


                           Figure 4-11. PMADDWD Execution Model Using 64-bit Operands


Operation
PMADDWD (with 64-bit operands)
  DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);
  DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);

PMADDWD (with 128-bit operands)
  DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);
  DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);
  DEST[95:64] <- (DEST[79:64] * SRC[79:64]) + (DEST[95:80] * SRC[95:80]);
  DEST[127:96] <- (DEST[111:96] * SRC[111:96]) + (DEST[127:112] * SRC[127:112]);

VPMADDWD (VEX.128 encoded version)
DEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])
DEST[VLMAX-1:128] <- 0

VPMADDWD (VEX.256 encoded version)
DEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])




DEST[159:128] <- (SRC1[143:128] * SRC2[143:128]) + (SRC1[159:144] * SRC2[159:144])
DEST[191:160] <- (SRC1[175:160] * SRC2[175:160]) + (SRC1[191:176] * SRC2[191:176])
DEST[223:192] <- (SRC1[207:192] * SRC2[207:192]) + (SRC1[223:208] * SRC2[223:208])
DEST[255:224] <- (SRC1[239:224] * SRC2[239:224]) + (SRC1[255:240] * SRC2[255:240])
DEST[VLMAX-1:256] <- 0

VPMADDWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- (SRC2[i+31:i+16]* SRC1[i+31:i+16]) + (SRC2[i+15:i]*SRC1[i+15:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] = 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMADDWD __m512i _mm512_mdd_epi16( __m512i a, __m512i b);
VPMADDWD __m512i _mm512_mask_mdd_epi16(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMADDWD __m512i _mm512_maskz_mdd_epi16( __mmask16 k, __m512i a, __m512i b);
VPMADDWD __m256i _mm256_mask_mdd_epi16(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMADDWD __m256i _mm256_maskz_mdd_epi16( __mmask8 k, __m256i a, __m256i b);
VPMADDWD __m128i _mm_mask_mdd_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMADDWD __m128i _mm_maskz_madd_epi16( __mmask8 k, __m128i a, __m128i b);
PMADDWD:__m64 _mm_madd_pi16(__m64 m1, __m64 m2)
(V)PMADDWD:__m128i _mm_madd_epi16 ( __m128i a, __m128i b)
VPMADDWD:__m256i _mm256_madd_epi16 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PMAXSB
description:
PMAXSB/PMAXSW/PMAXSD/PMAXSQ-Maximum of Packed Signed Integers
 Opcode/                          Op /   64/32      CPUID        Description
 Instruction                      En     bit Mode   Feature
                                         Support    Flag
 0F EE /r1                        RM     V/V        SSE          Compare signed word integers in mm2/m64 and
 PMAXSW mm1, mm2/m64                                             mm1 and return maximum values.
 66 0F 38 3C /r                   RM     V/V        SSE4_1       Compare packed signed byte integers in xmm1 and
 PMAXSB xmm1, xmm2/m128                                          xmm2/m128 and store packed maximum values in
                                                                 xmm1.
 66 0F EE /r                      RM     V/V        SSE2         Compare packed signed word integers in
 PMAXSW xmm1, xmm2/m128                                          xmm2/m128 and xmm1 and stores maximum
                                                                 packed values in xmm1.
 66 0F 38 3D /r                   RM     V/V        SSE4_1       Compare packed signed dword integers in xmm1
 PMAXSD xmm1, xmm2/m128                                          and xmm2/m128 and store packed maximum values
                                                                 in xmm1.
 VEX.NDS.128.66.0F38.WIG 3C /r    RVM    V/V        AVX          Compare packed signed byte integers in xmm2 and
 VPMAXSB xmm1, xmm2, xmm3/m128                                   xmm3/m128 and store packed maximum values in
                                                                 xmm1.
 VEX.NDS.128.66.0F.WIG EE /r      RVM    V/V        AVX          Compare packed signed word integers in
 VPMAXSW xmm1, xmm2, xmm3/m128                                   xmm3/m128 and xmm2 and store packed maximum
                                                                 values in xmm1.
 VEX.NDS.128.66.0F38.WIG 3D /r    RVM    V/V        AVX          Compare packed signed dword integers in xmm2
 VPMAXSD xmm1, xmm2, xmm3/m128                                   and xmm3/m128 and store packed maximum values
                                                                 in xmm1.
 VEX.NDS.256.66.0F38.WIG 3C /r    RVM    V/V        AVX2         Compare packed signed byte integers in ymm2 and
 VPMAXSB ymm1, ymm2, ymm3/m256                                   ymm3/m256 and store packed maximum values in
                                                                 ymm1.
 VEX.NDS.256.66.0F.WIG EE /r      RVM    V/V        AVX2         Compare packed signed word integers in
 VPMAXSW ymm1, ymm2, ymm3/m256                                   ymm3/m256 and ymm2 and store packed maximum
                                                                 values in ymm1.
 VEX.NDS.256.66.0F38.WIG 3D /r    RVM    V/V        AVX2         Compare packed signed dword integers in ymm2
 VPMAXSD ymm1, ymm2, ymm3/m256                                   and ymm3/m256 and store packed maximum values
                                                                 in ymm1.
 EVEX.NDS.128.66.0F38.WIG 3C /r   FVM    V/V        AVX512VL     Compare packed signed byte integers in xmm2 and
 VPMAXSB xmm1{k1}{z}, xmm2,                         AVX512BW     xmm3/m128 and store packed maximum values in
 xmm3/m128                                                       xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.WIG 3C /r   FVM    V/V        AVX512VL     Compare packed signed byte integers in ymm2 and
 VPMAXSB ymm1{k1}{z}, ymm2,                         AVX512BW     ymm3/m256 and store packed maximum values in
 ymm3/m256                                                       ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.WIG 3C /r   FVM    V/V        AVX512BW     Compare packed signed byte integers in zmm2 and
 VPMAXSB zmm1{k1}{z}, zmm2,                                      zmm3/m512 and store packed maximum values in
 zmm3/m512                                                       zmm1 under writemask k1.
 EVEX.NDS.128.66.0F.WIG EE /r     FVM    V/V        AVX512VL     Compare packed signed word integers in xmm2 and
 VPMAXSW xmm1{k1}{z}, xmm2,                         AVX512BW     xmm3/m128 and store packed maximum values in
 xmm3/m128                                                       xmm1 under writemask k1.
 EVEX.NDS.256.66.0F.WIG EE /r     FVM    V/V        AVX512VL     Compare packed signed word integers in ymm2 and
 VPMAXSW ymm1{k1}{z}, ymm2,                         AVX512BW     ymm3/m256 and store packed maximum values in
 ymm3/m256                                                       ymm1 under writemask k1.
 EVEX.NDS.512.66.0F.WIG EE /r     FVM    V/V        AVX512BW     Compare packed signed word integers in zmm2 and
 VPMAXSW zmm1{k1}{z}, zmm2,                                      zmm3/m512 and store packed maximum values in
 zmm3/m512                                                       zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.W0 3D /r    FV     V/V        AVX512VL     Compare packed signed dword integers in xmm2
 VPMAXSD xmm1 {k1}{z}, xmm2,                        AVX512F      and xmm3/m128/m32bcst and store packed
 xmm3/m128/m32bcst                                               maximum values in xmm1 using writemask k1.




 Opcode/                                 Op /     64/32       CPUID      Description
 Instruction                             En       bit Mode    Feature
                                                  Support     Flag
 EVEX.NDS.256.66.0F38.W0 3D /r           FV       V/V         AVX512VL   Compare packed signed dword integers in ymm2
 VPMAXSD ymm1 {k1}{z}, ymm2,                                  AVX512F    and ymm3/m256/m32bcst and store packed
 ymm3/m256/m32bcst                                                       maximum values in ymm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W0 3D /r           FV       V/V         AVX512F    Compare packed signed dword integers in zmm2 and
 VPMAXSD zmm1 {k1}{z}, zmm2,                                             zmm3/m512/m32bcst and store packed maximum
 zmm3/m512/m32bcst                                                       values in zmm1 using writemask k1.
 EVEX.NDS.128.66.0F38.W1 3D /r           FV       V/V         AVX512VL   Compare packed signed qword integers in xmm2
 VPMAXSQ xmm1 {k1}{z}, xmm2,                                  AVX512F    and xmm3/m128/m64bcst and store packed
 xmm3/m128/m64bcst                                                       maximum values in xmm1 using writemask k1.
 EVEX.NDS.256.66.0F38.W1 3D /r           FV       V/V         AVX512VL   Compare packed signed qword integers in ymm2
 VPMAXSQ ymm1 {k1}{z}, ymm2,                                  AVX512F    and ymm3/m256/m64bcst and store packed
 ymm3/m256/m64bcst                                                       maximum values in ymm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W1 3D /r           FV       V/V         AVX512F    Compare packed signed qword integers in zmm2 and
 VPMAXSQ zmm1 {k1}{z}, zmm2,                                             zmm3/m512/m64bcst and store packed maximum
 zmm3/m512/m64bcst                                                       values in zmm1 using writemask k1.


                                                Instruction Operand Encoding
      Op/En              Operand 1                   Operand 2                 Operand 3                Operand 4
       RM             ModRM:reg (r, w)             ModRM:r/m (r)                  NA                       NA
      RVM              ModRM:reg (w)                VEX.vvvv (r)           ModRM:r/m (r)                   NA
      FVM              ModRM:reg (w)                EVEX.vvvv (r)          ModRM:r/m (r)                   NA
       FV              ModRM:reg (w)                EVEX.vvvv (r)          ModRM:r/m (r)                   NA

Description
Performs a SIMD compare of the packed signed byte, word, dword or qword integers in the second source operand
and the first source operand and returns the maximum value for each pair of integers to the destination operand.
Legacy SSE version PMAXSW: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.
EVEX encoded VPMAXSD/Q: The first source operand is a ZMM/YMM/XMM register; The second source operand is
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.
EVEX encoded VPMAXSB/W: The first source operand is a ZMM/YMM/XMM register; The second source operand is
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.

Operation
PMAXSW (64-bit operands)
  IF DEST[15:0] > SRC[15:0]) THEN
       DEST[15:0] <- DEST[15:0];



   ELSE
        DEST[15:0] <- SRC[15:0]; FI;
   (* Repeat operation for 2nd and 3rd words in source and destination operands *)
   IF DEST[63:48] > SRC[63:48]) THEN
        DEST[63:48] <- DEST[63:48];
   ELSE
        DEST[63:48] <- SRC[63:48]; FI;

PMAXSB (128-bit Legacy SSE version)
   IF DEST[7:0] >SRC[7:0] THEN
        DEST[7:0] <-DEST[7:0];
   ELSE
        DEST[7:0] <-SRC[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF DEST[127:120] >SRC[127:120] THEN
        DEST[127:120] <-DEST[127:120];
   ELSE
        DEST[127:120] <-SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXSB (VEX.128 encoded version)
   IF SRC1[7:0] >SRC2[7:0] THEN
        DEST[7:0] <-SRC1[7:0];
   ELSE
        DEST[7:0] <-SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF SRC1[127:120] >SRC2[127:120] THEN
        DEST[127:120] <-SRC1[127:120];
   ELSE
        DEST[127:120] <-SRC2[127:120]; FI;
DEST[MAX_VL-1:128] <-0

VPMAXSB (VEX.256 encoded version)
   IF SRC1[7:0] >SRC2[7:0] THEN
        DEST[7:0] <-SRC1[7:0];
   ELSE
        DEST[7:0] <-SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
   IF SRC1[255:248] >SRC2[255:248] THEN
        DEST[255:248] <-SRC1[255:248];
   ELSE
        DEST[255:248] <-SRC2[255:248]; FI;
DEST[MAX_VL-1:256] <-0

VPMAXSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+7:i] > SRC2[i+7:i]
              THEN DEST[i+7:i] <- SRC1[i+7:i];
              ELSE DEST[i+7:i] <- SRC2[i+7:i];
         FI;
         ELSE



            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+7:i] remains unchanged*
                 ELSE                           ; zeroing-masking
                     DEST[i+7:i] <- 0
            FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PMAXSW (128-bit Legacy SSE version)
   IF DEST[15:0] >SRC[15:0] THEN
        DEST[15:0] <-DEST[15:0];
   ELSE
        DEST[15:0] <-SRC[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:112] >SRC[127:112] THEN
        DEST[127:112] <-DEST[127:112];
   ELSE
        DEST[127:112] <-SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXSW (VEX.128 encoded version)
   IF SRC1[15:0] > SRC2[15:0] THEN
        DEST[15:0] <-SRC1[15:0];
   ELSE
        DEST[15:0] <-SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF SRC1[127:112] >SRC2[127:112] THEN
        DEST[127:112] <-SRC1[127:112];
   ELSE
        DEST[127:112] <-SRC2[127:112]; FI;
DEST[MAX_VL-1:128] <-0

VPMAXSW (VEX.256 encoded version)
    IF SRC1[15:0] > SRC2[15:0] THEN
         DEST[15:0] <-SRC1[15:0];
    ELSE
         DEST[15:0] <-SRC2[15:0]; FI;
    (* Repeat operation for 2nd through 15th words in source and destination operands *)
    IF SRC1[255:240] >SRC2[255:240] THEN
         DEST[255:240] <-SRC1[255:240];
    ELSE
         DEST[255:240] <-SRC2[255:240]; FI;
DEST[MAX_VL-1:256] <-0
VPMAXSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+15:i] > SRC2[i+15:i]
               THEN DEST[i+15:i] <- SRC1[i+15:i];
               ELSE DEST[i+15:i] <- SRC2[i+15:i];
         FI;
         ELSE



             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                      DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PMAXSD (128-bit Legacy SSE version)
   IF DEST[31:0] >SRC[31:0] THEN
        DEST[31:0] <-DEST[31:0];
   ELSE
        DEST[31:0] <-SRC[31:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:96] >SRC[127:96] THEN
        DEST[127:96] <-DEST[127:96];
   ELSE
        DEST[127:96] <-SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXSD (VEX.128 encoded version)
   IF SRC1[31:0] > SRC2[31:0] THEN
        DEST[31:0] <-SRC1[31:0];
   ELSE
        DEST[31:0] <-SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
   IF SRC1[127:96] > SRC2[127:96] THEN
        DEST[127:96] <-SRC1[127:96];
   ELSE
        DEST[127:96] <-SRC2[127:96]; FI;
DEST[MAX_VL-1:128] <-0

VPMAXSD (VEX.256 encoded version)
   IF SRC1[31:0] > SRC2[31:0] THEN
        DEST[31:0] <-SRC1[31:0];
   ELSE
        DEST[31:0] <-SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
   IF SRC1[255:224] > SRC2[255:224] THEN
        DEST[255:224] <-SRC1[255:224];
   ELSE
        DEST[255:224] <-SRC2[255:224]; FI;
DEST[MAX_VL-1:256] <-0

VPMAXSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                   IF SRC1[i+31:i] > SRC2[31:0]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];



                     ELSE DEST[i+31:i] <- SRC2[31:0];
                FI;
            ELSE
                IF SRC1[i+31:i] > SRC2[i+31:i]
                     THEN DEST[i+31:i] <- SRC1[i+31:i];
                     ELSE DEST[i+31:i] <- SRC2[i+31:i];
            FI;
        FI;
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+31:i] remains unchanged*
                 ELSE DEST[i+31:i] <- 0          ; zeroing-masking
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMAXSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+63:i] > SRC2[63:0]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[63:0];
                    FI;
               ELSE
                    IF SRC1[i+63:i] > SRC2[i+63:i]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[i+63:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMAXSB __m512i _mm512_max_epi8( __m512i a, __m512i b);
VPMAXSB __m512i _mm512_mask_max_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMAXSB __m512i _mm512_maskz_max_epi8( __mmask64 k, __m512i a, __m512i b);
VPMAXSW __m512i _mm512_max_epi16( __m512i a, __m512i b);
VPMAXSW __m512i _mm512_mask_max_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMAXSW __m512i _mm512_maskz_max_epi16( __mmask32 k, __m512i a, __m512i b);
VPMAXSB __m256i _mm256_mask_max_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMAXSB __m256i _mm256_maskz_max_epi8( __mmask32 k, __m256i a, __m256i b);
VPMAXSW __m256i _mm256_mask_max_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);



VPMAXSW __m256i _mm256_maskz_max_epi16( __mmask16 k, __m256i a, __m256i b);
VPMAXSB __m128i _mm_mask_max_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMAXSB __m128i _mm_maskz_max_epi8( __mmask16 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_mask_max_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSW __m128i _mm_maskz_max_epi16( __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m256i _mm256_mask_max_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXSD __m256i _mm256_maskz_max_epi32( __mmask16 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_mask_max_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMAXSQ __m256i _mm256_maskz_max_epi64( __mmask8 k, __m256i a, __m256i b);
VPMAXSD __m128i _mm_mask_max_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m128i _mm_maskz_max_epi32( __mmask8 k, __m128i a, __m128i b);
VPMAXSQ __m128i _mm_mask_max_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXSQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);
VPMAXSD __m512i _mm512_max_epi32( __m512i a, __m512i b);
VPMAXSD __m512i _mm512_mask_max_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMAXSD __m512i _mm512_maskz_max_epi32( __mmask16 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_max_epi64( __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_mask_max_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMAXSQ __m512i _mm512_maskz_max_epi64( __mmask8 k, __m512i a, __m512i b);
(V)PMAXSB __m128i _mm_max_epi8 ( __m128i a, __m128i b);
(V)PMAXSW __m128i _mm_max_epi16 ( __m128i a, __m128i b)
(V)PMAXSD __m128i _mm_max_epi32 ( __m128i a, __m128i b);
VPMAXSB __m256i _mm256_max_epi8 ( __m256i a, __m256i b);
VPMAXSW __m256i _mm256_max_epi16 ( __m256i a, __m256i b)
VPMAXSD __m256i _mm256_max_epi32 ( __m256i a, __m256i b);
PMAXSW:__m64 _mm_max_pi16(__m64 a, __m64 b)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPMAXSD/Q, see Exceptions Type E4.
EVEX-encoded VPMAXSB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMAXUB
description:
PMAXUB/PMAXUW-Maximum of Packed Unsigned Integers
 Opcode/                                     Op /    64/32        CPUID          Description
 Instruction                                 En      bit Mode     Feature
                                                     Support      Flag
 0F DE /r1                                   RM      V/V          SSE            Compare unsigned byte integers in mm2/m64 and
 PMAXUB mm1, mm2/m64                                                             mm1 and returns maximum values.
 66 0F DE /r                                 RM      V/V          SSE2           Compare packed unsigned byte integers in xmm1
 PMAXUB xmm1, xmm2/m128                                                          and xmm2/m128 and store packed maximum
                                                                                 values in xmm1.
 66 0F 38 3E/r                               RM      V/V          SSE4_1         Compare packed unsigned word integers in
 PMAXUW xmm1, xmm2/m128                                                          xmm2/m128 and xmm1 and stores maximum
                                                                                 packed values in xmm1.
 VEX.NDS.128.66.0F DE /r                     RVM     V/V          AVX            Compare packed unsigned byte integers in xmm2
 VPMAXUB xmm1, xmm2, xmm3/m128                                                   and xmm3/m128 and store packed maximum
                                                                                 values in xmm1.
 VEX.NDS.128.66.0F38 3E/r                    RVM     V/V          AVX            Compare packed unsigned word integers in
 VPMAXUW xmm1, xmm2, xmm3/m128                                                   xmm3/m128 and xmm2 and store maximum
                                                                                 packed values in xmm1.
 VEX.NDS.256.66.0F DE /r                     RVM     V/V          AVX2           Compare packed unsigned byte integers in ymm2
 VPMAXUB ymm1, ymm2, ymm3/m256                                                   and ymm3/m256 and store packed maximum
                                                                                 values in ymm1.
 VEX.NDS.256.66.0F38 3E/r                    RVM     V/V          AVX2           Compare packed unsigned word integers in
 VPMAXUW ymm1, ymm2, ymm3/m256                                                   ymm3/m256 and ymm2 and store maximum
                                                                                 packed values in ymm1.
 EVEX.NDS.128.66.0F.WIG DE /r                FVM     V/V          AVX512VL       Compare packed unsigned byte integers in xmm2
 VPMAXUB xmm1{k1}{z}, xmm2,                                       AVX512BW       and xmm3/m128 and store packed maximum
 xmm3/m128                                                                       values in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F.WIG DE /r                FVM     V/V          AVX512VL       Compare packed unsigned byte integers in ymm2
 VPMAXUB ymm1{k1}{z}, ymm2,                                       AVX512BW       and ymm3/m256 and store packed maximum
 ymm3/m256                                                                       values in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F.WIG DE /r                FVM     V/V          AVX512BW       Compare packed unsigned byte integers in zmm2
 VPMAXUB zmm1{k1}{z}, zmm2,                                                      and zmm3/m512 and store packed maximum
 zmm3/m512                                                                       values in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.WIG 3E /r              FVM     V/V          AVX512VL       Compare packed unsigned word integers in xmm2
 VPMAXUW xmm1{k1}{z}, xmm2,                                       AVX512BW       and xmm3/m128 and store packed maximum
 xmm3/m128                                                                       values in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.WIG 3E /r              FVM     V/V          AVX512VL       Compare packed unsigned word integers in ymm2
 VPMAXUW ymm1{k1}{z}, ymm2,                                       AVX512BW       and ymm3/m256 and store packed maximum
 ymm3/m256                                                                       values in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.WIG 3E /r              FVM     V/V          AVX512BW       Compare packed unsigned word integers in zmm2
 VPMAXUW zmm1{k1}{z}, zmm2,                                                      and zmm3/m512 and store packed maximum
 zmm3/m512                                                                       values in zmm1 under writemask k1.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX
 Registers" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                  Instruction Operand Encoding
       Op/En                Operand 1                       Operand 2                       Operand 3                Operand 4
        RM               ModRM:reg (r, w)                  ModRM:r/m (r)                        NA                       NA
        RVM               ModRM:reg (w)                    VEX.vvvv (r)                   ModRM:r/m (r)                  NA
        FVM               ModRM:reg (w)                    EVEX.vvvv (r)                  ModRM:r/m (r)                  NA




Description
Performs a SIMD compare of the packed unsigned byte, word integers in the second source operand and the first
source operand and returns the maximum value for each pair of integers to the destination operand.
Legacy SSE version PMAXUB: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.

Operation
PMAXUB (64-bit operands)
  IF DEST[7:0] > SRC[17:0]) THEN
       DEST[7:0] <- DEST[7:0];
  ELSE
       DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 7th bytes in source and destination operands *)
  IF DEST[63:56] > SRC[63:56]) THEN
       DEST[63:56] <- DEST[63:56];
  ELSE
       DEST[63:56] <- SRC[63:56]; FI;

PMAXUB (128-bit Legacy SSE version)
   IF DEST[7:0] >SRC[7:0] THEN
        DEST[7:0] <- DEST[7:0];
   ELSE
        DEST[15:0] <- SRC[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF DEST[127:120] >SRC[127:120] THEN
        DEST[127:120] <- DEST[127:120];
   ELSE
        DEST[127:120] <- SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXUB (VEX.128 encoded version)
   IF SRC1[7:0] >SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[7:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF SRC1[127:120] >SRC2[127:120] THEN
        DEST[127:120] <- SRC1[127:120];
   ELSE
        DEST[127:120] <- SRC2[127:120]; FI;
DEST[MAX_VL-1:128] <- 0




VPMAXUB (VEX.256 encoded version)
   IF SRC1[7:0] >SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[15:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
   IF SRC1[255:248] >SRC2[255:248] THEN
        DEST[255:248] <- SRC1[255:248];
   ELSE
        DEST[255:248] <- SRC2[255:248]; FI;
DEST[MAX_VL-1:128] <- 0

VPMAXUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+7:i] > SRC2[i+7:i]
              THEN DEST[i+7:i] <- SRC1[i+7:i];
              ELSE DEST[i+7:i] <- SRC2[i+7:i];
         FI;
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PMAXUW (128-bit Legacy SSE version)
   IF DEST[15:0] >SRC[15:0] THEN
        DEST[15:0] <- DEST[15:0];
   ELSE
        DEST[15:0] <- SRC[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:112] >SRC[127:112] THEN
        DEST[127:112] <- DEST[127:112];
   ELSE
        DEST[127:112] <- SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXUW (VEX.128 encoded version)
   IF SRC1[15:0] > SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF SRC1[127:112] >SRC2[127:112] THEN
        DEST[127:112] <- SRC1[127:112];
   ELSE
        DEST[127:112] <- SRC2[127:112]; FI;
DEST[MAX_VL-1:128] <- 0



VPMAXUW (VEX.256 encoded version)
   IF SRC1[15:0] > SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 15th words in source and destination operands *)
   IF SRC1[255:240] >SRC2[255:240] THEN
        DEST[255:240] <- SRC1[255:240];
   ELSE
        DEST[255:240] <- SRC2[255:240]; FI;
DEST[MAX_VL-1:128] <- 0

VPMAXUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+15:i] > SRC2[i+15:i]
               THEN DEST[i+15:i] <- SRC1[i+15:i];
               ELSE DEST[i+15:i] <- SRC2[i+15:i];
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMAXUB __m512i _mm512_max_epu8( __m512i a, __m512i b);
VPMAXUB __m512i _mm512_mask_max_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMAXUB __m512i _mm512_maskz_max_epu8( __mmask64 k, __m512i a, __m512i b);
VPMAXUW __m512i _mm512_max_epu16( __m512i a, __m512i b);
VPMAXUW __m512i _mm512_mask_max_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMAXUW __m512i _mm512_maskz_max_epu16( __mmask32 k, __m512i a, __m512i b);
VPMAXUB __m256i _mm256_mask_max_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMAXUB __m256i _mm256_maskz_max_epu8( __mmask32 k, __m256i a, __m256i b);
VPMAXUW __m256i _mm256_mask_max_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXUW __m256i _mm256_maskz_max_epu16( __mmask16 k, __m256i a, __m256i b);
VPMAXUB __m128i _mm_mask_max_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMAXUB __m128i _mm_maskz_max_epu8( __mmask16 k, __m128i a, __m128i b);
VPMAXUW __m128i _mm_mask_max_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUW __m128i _mm_maskz_max_epu16( __mmask8 k, __m128i a, __m128i b);
(V)PMAXUB __m128i _mm_max_epu8 ( __m128i a, __m128i b);
(V)PMAXUW __m128i _mm_max_epu16 ( __m128i a, __m128i b)
VPMAXUB __m256i _mm256_max_epu8 ( __m256i a, __m256i b);
VPMAXUW __m256i _mm256_max_epu16 ( __m256i a, __m256i b);
PMAXUB: __m64 _mm_max_pu8(__m64 a, __m64 b);





SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMAXUD
description:
PMAXUD/PMAXUQ-Maximum of Packed Unsigned Integers
 Opcode/                                Op/    64/32       CPUID      Description
 Instruction                            En     bit Mode    Feature
                                               Support     Flag
 66 0F 38 3F /r                         RM     V/V         SSE4_1     Compare packed unsigned dword integers in xmm1
 PMAXUD xmm1, xmm2/m128                                               and xmm2/m128 and store packed maximum values in
                                                                      xmm1.
 VEX.NDS.128.66.0F38.WIG 3F /r          RVM    V/V         AVX        Compare packed unsigned dword integers in xmm2
 VPMAXUD xmm1, xmm2, xmm3/m128                                        and xmm3/m128 and store packed maximum values in
                                                                      xmm1.
 VEX.NDS.256.66.0F38.WIG 3F /r          RVM    V/V         AVX2       Compare packed unsigned dword integers in ymm2
 VPMAXUD ymm1, ymm2, ymm3/m256                                        and ymm3/m256 and store packed maximum values in
                                                                      ymm1.
 EVEX.NDS.128.66.0F38.W0 3F /r          FV     V/V         AVX512VL   Compare packed unsigned dword integers in xmm2
 VPMAXUD xmm1 {k1}{z}, xmm2,                               AVX512F    and xmm3/m128/m32bcst and store packed
 xmm3/m128/m32bcst                                                    maximum values in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W0 3F /r          FV     V/V         AVX512VL   Compare packed unsigned dword integers in ymm2
 VPMAXUD ymm1 {k1}{z}, ymm2,                               AVX512F    and ymm3/m256/m32bcst and store packed
 ymm3/m256/m32bcst                                                    maximum values in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W0 3F /r          FV     V/V         AVX512F    Compare packed unsigned dword integers in zmm2
 VPMAXUD zmm1 {k1}{z}, zmm2,                                          and zmm3/m512/m32bcst and store packed maximum
 zmm3/m512/m32bcst                                                    values in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.W1 3F /r          FV     V/V         AVX512VL   Compare packed unsigned qword integers in xmm2
 VPMAXUQ xmm1 {k1}{z}, xmm2,                               AVX512F    and xmm3/m128/m64bcst and store packed
 xmm3/m128/m64bcst                                                    maximum values in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W1 3F /r          FV     V/V         AVX512VL   Compare packed unsigned qword integers in ymm2
 VPMAXUQ ymm1 {k1}{z}, ymm2,                               AVX512F    and ymm3/m256/m64bcst and store packed
 ymm3/m256/m64bcst                                                    maximum values in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W1 3F /r          FV     V/V         AVX512F    Compare packed unsigned qword integers in zmm2
 VPMAXUQ zmm1 {k1}{z}, zmm2,                                          and zmm3/m512/m64bcst and store packed maximum
 zmm3/m512/m64bcst                                                    values in zmm1 under writemask k1.



                                              Instruction Operand Encoding
      Op/En             Operand 1                    Operand 2               Operand 3                Operand 4
       RM            ModRM:reg (r, w)            ModRM:r/m (r)                  NA                        NA
       RVM            ModRM:reg (w)                  VEX.vvvv              ModRM:r/m (r)                  NA
        FV            ModRM:reg (w)                  EVEX.vvvv             ModRM:r/m (r)                  NA

Description
Performs a SIMD compare of the packed unsigned dword or qword integers in the second source operand and the
first source operand and returns the maximum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register
or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.



Operation
PMAXUD (128-bit Legacy SSE version)
   IF DEST[31:0] >SRC[31:0] THEN
        DEST[31:0] <- DEST[31:0];
   ELSE
        DEST[31:0] <- SRC[31:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:96] >SRC[127:96] THEN
        DEST[127:96] <- DEST[127:96];
   ELSE
        DEST[127:96] <- SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMAXUD (VEX.128 encoded version)
   IF SRC1[31:0] > SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
   IF SRC1[127:96] > SRC2[127:96] THEN
        DEST[127:96] <- SRC1[127:96];
   ELSE
        DEST[127:96] <- SRC2[127:96]; FI;
DEST[MAX_VL-1:128] <- 0

VPMAXUD (VEX.256 encoded version)
   IF SRC1[31:0] > SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
   IF SRC1[255:224] > SRC2[255:224] THEN
        DEST[255:224] <- SRC1[255:224];
   ELSE
        DEST[255:224] <- SRC2[255:224]; FI;
DEST[MAX_VL-1:256] <- 0





VPMAXUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+31:i] > SRC2[31:0]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[31:0];
                    FI;
               ELSE
                    IF SRC1[i+31:i] > SRC2[i+31:i]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[i+31:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         THEN DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPMAXUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+63:i] > SRC2[63:0]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[63:0];
                    FI;
               ELSE
                    IF SRC1[i+31:i] > SRC2[i+31:i]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[i+63:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0




Intel C/C++ Compiler Intrinsic Equivalent
VPMAXUD __m512i _mm512_max_epu32( __m512i a, __m512i b);
VPMAXUD __m512i _mm512_mask_max_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMAXUD __m512i _mm512_maskz_max_epu32( __mmask16 k, __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_max_epu64( __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_mask_max_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMAXUQ __m512i _mm512_maskz_max_epu64( __mmask8 k, __m512i a, __m512i b);
VPMAXUD __m256i _mm256_mask_max_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMAXUD __m256i _mm256_maskz_max_epu32( __mmask16 k, __m256i a, __m256i b);
VPMAXUQ __m256i _mm256_mask_max_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMAXUQ __m256i _mm256_maskz_max_epu64( __mmask8 k, __m256i a, __m256i b);
VPMAXUD __m128i _mm_mask_max_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUD __m128i _mm_maskz_max_epu32( __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_mask_max_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMAXUQ __m128i _mm_maskz_max_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMAXUD __m128i _mm_max_epu32 ( __m128i a, __m128i b);
VPMAXUD __m256i _mm256_max_epu32 ( __m256i a, __m256i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PMINSB
description:
PMINSB/PMINSW-Minimum of Packed Signed Integers
 Opcode/                                  Op /    64/32         CPUID          Description
 Instruction                              En      bit Mode      Feature
                                                  Support       Flag
 0F EA /r1                                RM      V/V           SSE           Compare signed word integers in mm2/m64 and mm1
 PMINSW mm1, mm2/m64                                                          and return minimum values.
 66 0F 38 38 /r                           RM      V/V           SSE4_1         Compare packed signed byte integers in xmm1 and
 PMINSB xmm1, xmm2/m128                                                        xmm2/m128 and store packed minimum values in
                                                                               xmm1.
 66 0F EA /r                              RM      V/V           SSE2           Compare packed signed word integers in xmm2/m128
 PMINSW xmm1, xmm2/m128                                                        and xmm1 and store packed minimum values in xmm1.
 VEX.NDS.128.66.0F38 38 /r                RVM     V/V           AVX            Compare packed signed byte integers in xmm2 and
 VPMINSB xmm1, xmm2, xmm3/m128                                                 xmm3/m128 and store packed minimum values in
                                                                               xmm1.
 VEX.NDS.128.66.0F EA /r                  RVM     V/V           AVX            Compare packed signed word integers in xmm3/m128
 VPMINSW xmm1, xmm2, xmm3/m128                                                 and xmm2 and return packed minimum values in
                                                                               xmm1.
 VEX.NDS.256.66.0F38 38 /r                RVM     V/V           AVX2           Compare packed signed byte integers in ymm2 and
 VPMINSB ymm1, ymm2, ymm3/m256                                                 ymm3/m256 and store packed minimum values in
                                                                               ymm1.
 VEX.NDS.256.66.0F EA /r                  RVM     V/V           AVX2           Compare packed signed word integers in ymm3/m256
 VPMINSW ymm1, ymm2, ymm3/m256                                                 and ymm2 and return packed minimum values in
                                                                               ymm1.
 EVEX.NDS.128.66.0F38.WIG 38 /r           FVM     V/V           AVX512VL       Compare packed signed byte integers in xmm2 and
 VPMINSB xmm1{k1}{z}, xmm2,                                     AVX512BW       xmm3/m128 and store packed minimum values in
 xmm3/m128                                                                     xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.WIG 38 /r           FVM     V/V           AVX512VL       Compare packed signed byte integers in ymm2 and
 VPMINSB ymm1{k1}{z}, ymm2,                                     AVX512BW       ymm3/m256 and store packed minimum values in
 ymm3/m256                                                                     ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.WIG 38 /r           FVM     V/V           AVX512BW       Compare packed signed byte integers in zmm2 and
 VPMINSB zmm1{k1}{z}, zmm2,                                                    zmm3/m512 and store packed minimum values in
 zmm3/m512                                                                     zmm1 under writemask k1.
 EVEX.NDS.128.66.0F.WIG EA /r             FVM     V/V           AVX512VL       Compare packed signed word integers in xmm2 and
 VPMINSW xmm1{k1}{z}, xmm2,                                     AVX512BW       xmm3/m128 and store packed minimum values in
 xmm3/m128                                                                     xmm1 under writemask k1.
 EVEX.NDS.256.66.0F.WIG EA /r             FVM     V/V           AVX512VL       Compare packed signed word integers in ymm2 and
 VPMINSW ymm1{k1}{z}, ymm2,                                     AVX512BW       ymm3/m256 and store packed minimum values in
 ymm3/m256                                                                     ymm1 under writemask k1.
 EVEX.NDS.512.66.0F.WIG EA /r             FVM     V/V           AVX512BW       Compare packed signed word integers in zmm2 and
 VPMINSW zmm1{k1}{z}, zmm2,                                                    zmm3/m512 and store packed minimum values in
 zmm3/m512                                                                     zmm1 under writemask k1.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX
 Registers" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                 Instruction Operand Encoding
        Op/En                 Operand 1                       Operand 2                       Operand 3               Operand 4
         RM                ModRM:reg (r, w)                 ModRM:r/m (r)                         NA                      NA
         RVM                ModRM:reg (w)                    VEX.vvvv (r)                    ModRM:r/m (r)                NA
         FVM                ModRM:reg (w)                    EVEX.vvvv (r)                   ModRM:r/m (r)                NA





Description
Performs a SIMD compare of the packed signed byte, word, or dword integers in the second source operand and
the first source operand and returns the minimum value for each pair of integers to the destination operand.
Legacy SSE version PMINSW: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.

Operation
PMINSW (64-bit operands)
  IF DEST[15:0] < SRC[15:0] THEN
       DEST[15:0] <- DEST[15:0];
  ELSE
       DEST[15:0] <- SRC[15:0]; FI;
  (* Repeat operation for 2nd and 3rd words in source and destination operands *)
  IF DEST[63:48] < SRC[63:48] THEN
       DEST[63:48] <- DEST[63:48];
  ELSE
       DEST[63:48] <- SRC[63:48]; FI;

PMINSB (128-bit Legacy SSE version)
   IF DEST[7:0] < SRC[7:0] THEN
        DEST[7:0] <- DEST[7:0];
   ELSE
        DEST[15:0] <- SRC[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF DEST[127:120] < SRC[127:120] THEN
        DEST[127:120] <- DEST[127:120];
   ELSE
        DEST[127:120] <- SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINSB (VEX.128 encoded version)
   IF SRC1[7:0] < SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[7:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF SRC1[127:120] < SRC2[127:120] THEN
        DEST[127:120] <- SRC1[127:120];
   ELSE
        DEST[127:120] <- SRC2[127:120]; FI;
DEST[MAX_VL-1:128] <- 0




VPMINSB (VEX.256 encoded version)
   IF SRC1[7:0] < SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[15:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
   IF SRC1[255:248] < SRC2[255:248] THEN
        DEST[255:248] <- SRC1[255:248];
   ELSE
        DEST[255:248] <- SRC2[255:248]; FI;
DEST[MAX_VL-1:256] <- 0

VPMINSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+7:i] < SRC2[i+7:i]
              THEN DEST[i+7:i] <- SRC1[i+7:i];
              ELSE DEST[i+7:i] <- SRC2[i+7:i];
         FI;
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PMINSW (128-bit Legacy SSE version)
   IF DEST[15:0] < SRC[15:0] THEN
        DEST[15:0] <- DEST[15:0];
   ELSE
        DEST[15:0] <- SRC[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:112] < SRC[127:112] THEN
        DEST[127:112] <- DEST[127:112];
   ELSE
        DEST[127:112] <- SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINSW (VEX.128 encoded version)
   IF SRC1[15:0] < SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF SRC1[127:112] < SRC2[127:112] THEN
        DEST[127:112] <- SRC1[127:112];
   ELSE
        DEST[127:112] <- SRC2[127:112]; FI;
DEST[MAX_VL-1:128] <- 0



VPMINSW (VEX.256 encoded version)
   IF SRC1[15:0] < SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 15th words in source and destination operands *)
   IF SRC1[255:240] < SRC2[255:240] THEN
        DEST[255:240] <- SRC1[255:240];
   ELSE
        DEST[255:240] <- SRC2[255:240]; FI;
DEST[MAX_VL-1:256] <- 0

VPMINSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+15:i] < SRC2[i+15:i]
               THEN DEST[i+15:i] <- SRC1[i+15:i];
               ELSE DEST[i+15:i] <- SRC2[i+15:i];
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMINSB __m512i _mm512_min_epi8( __m512i a, __m512i b);
VPMINSB __m512i _mm512_mask_min_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMINSB __m512i _mm512_maskz_min_epi8( __mmask64 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_min_epi16( __m512i a, __m512i b);
VPMINSW __m512i _mm512_mask_min_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMINSW __m512i _mm512_maskz_min_epi16( __mmask32 k, __m512i a, __m512i b);
VPMINSB __m256i _mm256_mask_min_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMINSB __m256i _mm256_maskz_min_epi8( __mmask32 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_mask_min_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINSW __m256i _mm256_maskz_min_epi16( __mmask16 k, __m256i a, __m256i b);
VPMINSB __m128i _mm_mask_min_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINSB __m128i _mm_maskz_min_epi8( __mmask16 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_mask_min_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSW __m128i _mm_maskz_min_epi16( __mmask8 k, __m128i a, __m128i b);
(V)PMINSB __m128i _mm_min_epi8 ( __m128i a, __m128i b);
(V)PMINSW __m128i _mm_min_epi16 ( __m128i a, __m128i b)
VPMINSB __m256i _mm256_min_epi8 ( __m256i a, __m256i b);
VPMINSW __m256i _mm256_min_epi16 ( __m256i a, __m256i b)
PMINSW:__m64 _mm_min_pi16 (__m64 a, __m64 b)





SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.
#MF                  (64-bit operations only) If there is a pending x87 FPU exception.






platform: x86_64
mnem: PMINSD
description:
PMINSD/PMINSQ-Minimum of Packed Signed Integers
 Opcode/                                  Op/     64/32         CPUID      Description
 Instruction                              En      bit Mode      Feature
                                                  Support       Flag
 66 0F 38 39 /r                           RM      V/V           SSE4_1     Compare packed signed dword integers in xmm1 and
 PMINSD xmm1, xmm2/m128                                                    xmm2/m128 and store packed minimum values in
                                                                           xmm1.
 VEX.NDS.128.66.0F38.WIG 39 /r            RVM     V/V           AVX        Compare packed signed dword integers in xmm2 and
 VPMINSD xmm1, xmm2, xmm3/m128                                             xmm3/m128 and store packed minimum values in
                                                                           xmm1.
 VEX.NDS.256.66.0F38.WIG 39 /r            RVM     V/V           AVX2       Compare packed signed dword integers in ymm2 and
 VPMINSD ymm1, ymm2, ymm3/m256                                             ymm3/m128 and store packed minimum values in
                                                                           ymm1.
 EVEX.NDS.128.66.0F38.W0 39 /r            FV      V/V           AVX512VL   Compare packed signed dword integers in xmm2 and
 VPMINSD xmm1 {k1}{z}, xmm2,                                    AVX512F    xmm3/m128 and store packed minimum values in
 xmm3/m128/m32bcst                                                         xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W0 39 /r            FV      V/V           AVX512VL   Compare packed signed dword integers in ymm2 and
 VPMINSD ymm1 {k1}{z}, ymm2,                                    AVX512F    ymm3/m256 and store packed minimum values in
 ymm3/m256/m32bcst                                                         ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W0 39 /r            FV      V/V           AVX512F    Compare packed signed dword integers in zmm2 and
 VPMINSD zmm1 {k1}{z}, zmm2,                                               zmm3/m512/m32bcst and store packed minimum
 zmm3/m512/m32bcst                                                         values in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.W1 39 /r            FV      V/V           AVX512VL   Compare packed signed qword integers in xmm2 and
 VPMINSQ xmm1 {k1}{z}, xmm2,                                    AVX512F    xmm3/m128 and store packed minimum values in
 xmm3/m128/m64bcst                                                         xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W1 39 /r            FV      V/V           AVX512VL   Compare packed signed qword integers in ymm2 and
 VPMINSQ ymm1 {k1}{z}, ymm2,                                    AVX512F    ymm3/m256 and store packed minimum values in
 ymm3/m256/m64bcst                                                         ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W1 39 /r            FV      V/V           AVX512F    Compare packed signed qword integers in zmm2 and
 VPMINSQ zmm1 {k1}{z}, zmm2,                                               zmm3/m512/m64bcst and store packed minimum
 zmm3/m512/m64bcst                                                         values in zmm1 under writemask k1.



                                                  Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                 Operand 3                  Operand 4
       RM              ModRM:reg (r, w)              ModRM:r/m (r)                   NA                         NA
       RVM              ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                   NA
        FV              ModRM:reg (w)                EVEX.vvvv (r)              ModRM:r/m (r)                   NA

Description
Performs a SIMD compare of the packed signed dword or qword integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.





EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.

Operation
PMINSD (128-bit Legacy SSE version)
   IF DEST[31:0] < SRC[31:0] THEN
        DEST[31:0] <- DEST[31:0];
   ELSE
        DEST[31:0] <- SRC[31:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:96] < SRC[127:96] THEN
        DEST[127:96] <- DEST[127:96];
   ELSE
        DEST[127:96] <- SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINSD (VEX.128 encoded version)
   IF SRC1[31:0] < SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
   IF SRC1[127:96] < SRC2[127:96] THEN
        DEST[127:96] <- SRC1[127:96];
   ELSE
        DEST[127:96] <- SRC2[127:96]; FI;
DEST[MAX_VL-1:128] <- 0

VPMINSD (VEX.256 encoded version)
   IF SRC1[31:0] < SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
   IF SRC1[255:224] < SRC2[255:224] THEN
        DEST[255:224] <- SRC1[255:224];
   ELSE
        DEST[255:224] <- SRC2[255:224]; FI;
DEST[MAX_VL-1:256] <- 0





VPMINSD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+31:i] < SRC2[31:0]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[31:0];
                    FI;
               ELSE
                    IF SRC1[i+31:i] < SRC2[i+31:i]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[i+31:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPMINSQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+63:i] < SRC2[63:0]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[63:0];
                    FI;
               ELSE
                    IF SRC1[i+63:i] < SRC2[i+63:i]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[i+63:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0




Intel C/C++ Compiler Intrinsic Equivalent
VPMINSD __m512i _mm512_min_epi32( __m512i a, __m512i b);
VPMINSD __m512i _mm512_mask_min_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMINSD __m512i _mm512_maskz_min_epi32( __mmask16 k, __m512i a, __m512i b);
VPMINSQ __m512i _mm512_min_epi64( __m512i a, __m512i b);
VPMINSQ __m512i _mm512_mask_min_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMINSQ __m512i _mm512_maskz_min_epi64( __mmask8 k, __m512i a, __m512i b);
VPMINSD __m256i _mm256_mask_min_epi32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINSD __m256i _mm256_maskz_min_epi32( __mmask16 k, __m256i a, __m256i b);
VPMINSQ __m256i _mm256_mask_min_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMINSQ __m256i _mm256_maskz_min_epi64( __mmask8 k, __m256i a, __m256i b);
VPMINSD __m128i _mm_mask_min_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSD __m128i _mm_maskz_min_epi32( __mmask8 k, __m128i a, __m128i b);
VPMINSQ __m128i _mm_mask_min_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINSQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMINSD __m128i _mm_min_epi32 ( __m128i a, __m128i b);
VPMINSD __m256i _mm256_min_epi32 (__m256i a, __m256i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PMINUB
description:
PMINUB/PMINUW-Minimum of Packed Unsigned Integers
 Opcode/                                     Op /     64/32       CPUID          Description
 Instruction                                 En       bit Mode    Feature
                                                      Support     Flag
 0F DA /r1                                   RM       V/V         SSE            Compare unsigned byte integers in mm2/m64 and
 PMINUB mm1, mm2/m64                                                             mm1 and returns minimum values.
 66 0F DA /r                                 RM       V/V         SSE2           Compare packed unsigned byte integers in xmm1
 PMINUB xmm1, xmm2/m128                                                          and xmm2/m128 and store packed minimum values
                                                                                 in xmm1.
 66 0F 38 3A/r                               RM       V/V         SSE4_1         Compare packed unsigned word integers in
 PMINUW xmm1, xmm2/m128                                                          xmm2/m128 and xmm1 and store packed minimum
                                                                                 values in xmm1.
 VEX.NDS.128.66.0F DA /r                     RVM      V/V         AVX            Compare packed unsigned byte integers in xmm2
 VPMINUB xmm1, xmm2, xmm3/m128                                                   and xmm3/m128 and store packed minimum values
                                                                                 in xmm1.
 VEX.NDS.128.66.0F38 3A/r                    RVM      V/V         AVX            Compare packed unsigned word integers in
 VPMINUW xmm1, xmm2, xmm3/m128                                                   xmm3/m128 and xmm2 and return packed
                                                                                 minimum values in xmm1.
 VEX.NDS.256.66.0F DA /r                     RVM      V/V         AVX2           Compare packed unsigned byte integers in ymm2
 VPMINUB ymm1, ymm2, ymm3/m256                                                   and ymm3/m256 and store packed minimum values
                                                                                 in ymm1.
 VEX.NDS.256.66.0F38 3A/r                    RVM      V/V         AVX2           Compare packed unsigned word integers in
 VPMINUW ymm1, ymm2, ymm3/m256                                                   ymm3/m256 and ymm2 and return packed
                                                                                 minimum values in ymm1.
 EVEX.NDS.128.66.0F DA /r                    FVM      V/V         AVX512VL       Compare packed unsigned byte integers in xmm2
 VPMINUB xmm1 {k1}{z}, xmm2,                                      AVX512BW       and xmm3/m128 and store packed minimum values
 xmm3/m128                                                                       in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F DA /r                    FVM      V/V         AVX512VL       Compare packed unsigned byte integers in ymm2
 VPMINUB ymm1 {k1}{z}, ymm2,                                      AVX512BW       and ymm3/m256 and store packed minimum values
 ymm3/m256                                                                       in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F DA /r                    FVM      V/V         AVX512BW       Compare packed unsigned byte integers in zmm2
 VPMINUB zmm1 {k1}{z}, zmm2,                                                     and zmm3/m512 and store packed minimum values
 zmm3/m512                                                                       in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38 3A/r                   FVM      V/V         AVX512VL       Compare packed unsigned word integers in
 VPMINUW xmm1{k1}{z}, xmm2,                                       AVX512BW       xmm3/m128 and xmm2 and return packed
 xmm3/m128                                                                       minimum values in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38 3A/r                   FVM      V/V         AVX512VL       Compare packed unsigned word integers in
 VPMINUW ymm1{k1}{z}, ymm2,                                       AVX512BW       ymm3/m256 and ymm2 and return packed
 ymm3/m256                                                                       minimum values in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38 3A/r                   FVM      V/V         AVX512BW       Compare packed unsigned word integers in
 VPMINUW zmm1{k1}{z}, zmm2,                                                      zmm3/m512 and zmm2 and return packed
 zmm3/m512                                                                       minimum values in zmm1 under writemask k1.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX
 Registers" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                    Instruction Operand Encoding
        Op/En                Operand 1                       Operand 2                      Operand 3                Operand 4
         RM               ModRM:reg (r, w)                  ModRM:r/m (r)                       NA                       NA
         RVM               ModRM:reg (w)                    VEX.vvvv (r)                   ModRM:r/m (r)                 NA
         FVM               ModRM:reg (w)                    EVEX.vvvv (r)                  ModRM:r/m (r)                 NA




Description
Performs a SIMD compare of the packed unsigned byte or word integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
Legacy SSE version PMINUB: The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand can be an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.

Operation
PMINUB (for 64-bit operands)
  IF DEST[7:0] < SRC[17:0] THEN
       DEST[7:0] <- DEST[7:0];
  ELSE
       DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 7th bytes in source and destination operands *)
  IF DEST[63:56] < SRC[63:56] THEN
       DEST[63:56] <- DEST[63:56];
  ELSE
       DEST[63:56] <- SRC[63:56]; FI;

PMINUB instruction for 128-bit operands:
   IF DEST[7:0] < SRC[7:0] THEN
        DEST[7:0] <- DEST[7:0];
   ELSE
        DEST[15:0] <- SRC[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF DEST[127:120] < SRC[127:120] THEN
        DEST[127:120] <- DEST[127:120];
   ELSE
        DEST[127:120] <- SRC[127:120]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINUB (VEX.128 encoded version)
   IF SRC1[7:0] < SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[7:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
   IF SRC1[127:120] < SRC2[127:120] THEN
        DEST[127:120] <- SRC1[127:120];
   ELSE
        DEST[127:120] <- SRC2[127:120]; FI;
DEST[MAX_VL-1:128] <- 0




VPMINUB (VEX.256 encoded version)
   IF SRC1[7:0] < SRC2[7:0] THEN
        DEST[7:0] <- SRC1[7:0];
   ELSE
        DEST[15:0] <- SRC2[7:0]; FI;
   (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
   IF SRC1[255:248] < SRC2[255:248] THEN
        DEST[255:248] <- SRC1[255:248];
   ELSE
        DEST[255:248] <- SRC2[255:248]; FI;
DEST[MAX_VL-1:256] <- 0

VPMINUB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+7:i] < SRC2[i+7:i]
              THEN DEST[i+7:i] <- SRC1[i+7:i];
              ELSE DEST[i+7:i] <- SRC2[i+7:i];
         FI;
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE                           ; zeroing-masking
                        DEST[i+7:i] <- 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

PMINUW instruction for 128-bit operands:
   IF DEST[15:0] < SRC[15:0] THEN
        DEST[15:0] <- DEST[15:0];
   ELSE
        DEST[15:0] <- SRC[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:112] < SRC[127:112] THEN
        DEST[127:112] <- DEST[127:112];
   ELSE
        DEST[127:112] <- SRC[127:112]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINUW (VEX.128 encoded version)
   IF SRC1[15:0] < SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF SRC1[127:112] < SRC2[127:112] THEN
        DEST[127:112] <- SRC1[127:112];
   ELSE
        DEST[127:112] <- SRC2[127:112]; FI;
DEST[MAX_VL-1:128] <- 0



VPMINUW (VEX.256 encoded version)
   IF SRC1[15:0] < SRC2[15:0] THEN
        DEST[15:0] <- SRC1[15:0];
   ELSE
        DEST[15:0] <- SRC2[15:0]; FI;
   (* Repeat operation for 2nd through 15th words in source and destination operands *)
   IF SRC1[255:240] < SRC2[255:240] THEN
        DEST[255:240] <- SRC1[255:240];
   ELSE
        DEST[255:240] <- SRC2[255:240]; FI;
DEST[MAX_VL-1:256] <- 0

VPMINUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask* THEN
         IF SRC1[i+15:i] < SRC2[i+15:i]
               THEN DEST[i+15:i] <- SRC1[i+15:i];
               ELSE DEST[i+15:i] <- SRC2[i+15:i];
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMINUB __m512i _mm512_min_epu8( __m512i a, __m512i b);
VPMINUB __m512i _mm512_mask_min_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPMINUB __m512i _mm512_maskz_min_epu8( __mmask64 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_min_epu16( __m512i a, __m512i b);
VPMINUW __m512i _mm512_mask_min_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMINUW __m512i _mm512_maskz_min_epu16( __mmask32 k, __m512i a, __m512i b);
VPMINUB __m256i _mm256_mask_min_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPMINUB __m256i _mm256_maskz_min_epu8( __mmask32 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_mask_min_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINUW __m256i _mm256_maskz_min_epu16( __mmask16 k, __m256i a, __m256i b);
VPMINUB __m128i _mm_mask_min_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPMINUB __m128i _mm_maskz_min_epu8( __mmask16 k, __m128i a, __m128i b);
VPMINUW __m128i _mm_mask_min_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUW __m128i _mm_maskz_min_epu16( __mmask8 k, __m128i a, __m128i b);
(V)PMINUB __m128i _mm_min_epu8 ( __m128i a, __m128i b)
(V)PMINUW __m128i _mm_min_epu16 ( __m128i a, __m128i b);
VPMINUB __m256i _mm256_min_epu8 ( __m256i a, __m256i b)
VPMINUW __m256i _mm256_min_epu16 ( __m256i a, __m256i b);
PMINUB: __m64 _m_min_pu8 (__m64 a, __m64 b)





SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMINUD
description:
PMINUD/PMINUQ-Minimum of Packed Unsigned Integers
 Opcode/                             Op/   64/32      CPUID      Description
 Instruction                         En    bit Mode   Feature
                                           Support    Flag
 66 0F 38 3B /r                      RM    V/V        SSE4_1     Compare packed unsigned dword integers in xmm1 and
 PMINUD xmm1, xmm2/m128                                          xmm2/m128 and store packed minimum values in xmm1.
 VEX.NDS.128.66.0F38.WIG 3B /r       RVM   V/V        AVX        Compare packed unsigned dword integers in xmm2 and
 VPMINUD xmm1, xmm2,                                             xmm3/m128 and store packed minimum values in xmm1.
 xmm3/m128
 VEX.NDS.256.66.0F38.WIG 3B /r       RVM   V/V        AVX2       Compare packed unsigned dword integers in ymm2 and
 VPMINUD ymm1, ymm2,                                             ymm3/m256 and store packed minimum values in ymm1.
 ymm3/m256
 EVEX.NDS.128.66.0F38.W0 3B /r       FV    V/V        AVX512VL   Compare packed unsigned dword integers in xmm2 and
 VPMINUD xmm1 {k1}{z}, xmm2,                          AVX512F    xmm3/m128/m32bcst and store packed minimum values
 xmm3/m128/m32bcst                                               in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W0 3B /r       FV    V/V        AVX512VL   Compare packed unsigned dword integers in ymm2 and
 VPMINUD ymm1 {k1}{z}, ymm2,                          AVX512F    ymm3/m256/m32bcst and store packed minimum values
 ymm3/m256/m32bcst                                               in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W0 3B /r       FV    V/V        AVX512F    Compare packed unsigned dword integers in zmm2 and
 VPMINUD zmm1 {k1}{z}, zmm2,                                     zmm3/m512/m32bcst and store packed minimum values
 zmm3/m512/m32bcst                                               in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.W1 3B /r       FV    V/V        AVX512VL   Compare packed unsigned qword integers in xmm2 and
 VPMINUQ xmm1 {k1}{z}, xmm2,                          AVX512F    xmm3/m128/m64bcst and store packed minimum values
 xmm3/m128/m64bcst                                               in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W1 3B /r       FV    V/V        AVX512VL   Compare packed unsigned qword integers in ymm2 and
 VPMINUQ ymm1 {k1}{z}, ymm2,                          AVX512F    ymm3/m256/m64bcst and store packed minimum values
 ymm3/m256/m64bcst                                               in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W1 3B /r       FV    V/V        AVX512F    Compare packed unsigned qword integers in zmm2 and
 VPMINUQ zmm1 {k1}{z}, zmm2,                                     zmm3/m512/m64bcst and store packed minimum values
 zmm3/m512/m64bcst                                               in zmm1 under writemask k1.



                                            Instruction Operand Encoding
       Op/En             Operand 1                Operand 2                Operand 3                 Operand 4
        RM            ModRM:reg (r, w)           ModRM:r/m (r)                 NA                        NA
        RVM            ModRM:reg (w)              VEX.vvvv (r)           ModRM:r/m (r)                   NA
        FV             ModRM:reg (w)             EVEX.vvvv (r)           ModRM:r/m (r)                   NA

Description
Performs a SIMD compare of the packed unsigned dword/qword integers in the second source operand and the first
source operand and returns the minimum value for each pair of integers to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding destination
register are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register; The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.



Operation
PMINUD (128-bit Legacy SSE version)
PMINUD instruction for 128-bit operands:
   IF DEST[31:0] < SRC[31:0] THEN
        DEST[31:0] <- DEST[31:0];
   ELSE
        DEST[31:0] <- SRC[31:0]; FI;
   (* Repeat operation for 2nd through 7th words in source and destination operands *)
   IF DEST[127:96] < SRC[127:96] THEN
        DEST[127:96] <- DEST[127:96];
   ELSE
        DEST[127:96] <- SRC[127:96]; FI;
DEST[MAX_VL-1:128] (Unmodified)

VPMINUD (VEX.128 encoded version)
VPMINUD instruction for 128-bit operands:
   IF SRC1[31:0] < SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
   IF SRC1[127:96] < SRC2[127:96] THEN
        DEST[127:96] <- SRC1[127:96];
   ELSE
        DEST[127:96] <- SRC2[127:96]; FI;
DEST[MAX_VL-1:128] <- 0

VPMINUD (VEX.256 encoded version)
VPMINUD instruction for 128-bit operands:
   IF SRC1[31:0] < SRC2[31:0] THEN
        DEST[31:0] <- SRC1[31:0];
   ELSE
        DEST[31:0] <- SRC2[31:0]; FI;
   (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
   IF SRC1[255:224] < SRC2[255:224] THEN
        DEST[255:224] <- SRC1[255:224];
   ELSE
        DEST[255:224] <- SRC2[255:224]; FI;
DEST[MAX_VL-1:256] <- 0





VPMINUD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+31:i] < SRC2[31:0]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[31:0];
                    FI;
               ELSE
                    IF SRC1[i+31:i] < SRC2[i+31:i]
                         THEN DEST[i+31:i] <- SRC1[i+31:i];
                         ELSE DEST[i+31:i] <- SRC2[i+31:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPMINUQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
         IF (EVEX.b = 1) AND (SRC2 *is memory*)
               THEN
                    IF SRC1[i+63:i] < SRC2[63:0]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[63:0];
                    FI;
               ELSE
                    IF SRC1[i+63:i] < SRC2[i+63:i]
                         THEN DEST[i+63:i] <- SRC1[i+63:i];
                         ELSE DEST[i+63:i] <- SRC2[i+63:i];
               FI;
         FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0




Intel C/C++ Compiler Intrinsic Equivalent
VPMINUD __m512i _mm512_min_epu32( __m512i a, __m512i b);
VPMINUD __m512i _mm512_mask_min_epu32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMINUD __m512i _mm512_maskz_min_epu32( __mmask16 k, __m512i a, __m512i b);
VPMINUQ __m512i _mm512_min_epu64( __m512i a, __m512i b);
VPMINUQ __m512i _mm512_mask_min_epu64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMINUQ __m512i _mm512_maskz_min_epu64( __mmask8 k, __m512i a, __m512i b);
VPMINUD __m256i _mm256_mask_min_epu32(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMINUD __m256i _mm256_maskz_min_epu32( __mmask16 k, __m256i a, __m256i b);
VPMINUQ __m256i _mm256_mask_min_epu64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMINUQ __m256i _mm256_maskz_min_epu64( __mmask8 k, __m256i a, __m256i b);
VPMINUD __m128i _mm_mask_min_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUD __m128i _mm_maskz_min_epu32( __mmask8 k, __m128i a, __m128i b);
VPMINUQ __m128i _mm_mask_min_epu64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMINUQ __m128i _mm_maskz_min_epu64( __mmask8 k, __m128i a, __m128i b);
(V)PMINUD __m128i _mm_min_epu32 ( __m128i a, __m128i b);
VPMINUD __m256i _mm256_min_epu32 ( __m256i a, __m256i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PMOVMSKB
description:
PMOVMSKB-Move Byte Mask
 Opcode/                                              Op/   64/32 bit   CPUID       Description
 Instruction                                          En    Mode        Feature
                                                            Support     Flag
 0F D7 /r1                                            RM    V/V         SSE         Move a byte mask of mm to reg. The upper
 PMOVMSKB reg, mm                                                                   bits of r32 or r64 are zeroed

 66 0F D7 /r                                          RM    V/V         SSE2        Move a byte mask of xmm to reg. The upper
 PMOVMSKB reg, xmm                                                                  bits of r32 or r64 are zeroed

 VEX.128.66.0F.WIG D7 /r                              RM    V/V         AVX         Move a byte mask of xmm1 to reg. The upper
 VPMOVMSKB reg, xmm1                                                                bits of r32 or r64 are filled with zeros.

 VEX.256.66.0F.WIG D7 /r                              RM    V/V         AVX2        Move a 32-bit mask of ymm1 to reg. The
 VPMOVMSKB reg, ymm1                                                                upper bits of r64 are filled with zeros.

 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                Instruction Operand Encoding
   Op/En             Operand 1                     Operand 2                    Operand 3                     Operand 4
    RM             ModRM:reg (w)                 ModRM:r/m (r)                      NA                           NA


Description
Creates a mask made up of the most significant bit of each byte of the source operand (second operand) and stores
the result in the low byte or word of the destination operand (first operand).
The byte mask is 8 bits for 64-bit source operand, 16 bits for 128-bit source operand and 32 bits for 256-bit source
operand. The destination operand is a general-purpose register.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
Legacy SSE version: The source operand is an MMX technology register.
128-bit Legacy SSE version: The source operand is an XMM register.
VEX.128 encoded version: The source operand is an XMM register.
VEX.256 encoded version: The source operand is a YMM register.
Note: VEX.vvvv is reserved and must be 1111b.

Operation
PMOVMSKB (with 64-bit source operand and r32)
  r32[0] <- SRC[7];
  r32[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 6 *)
  r32[7] <- SRC[63];
  r32[31:8] <- ZERO_FILL;

(V)PMOVMSKB (with 128-bit source operand and r32)
   r32[0] <- SRC[7];
   r32[1] <- SRC[15];
   (* Repeat operation for bytes 2 through 14 *)
   r32[15] <- SRC[127];
   r32[31:16] <- ZERO_FILL;



VPMOVMSKB (with 256-bit source operand and r32)
r32[0] <- SRC[7];
r32[1] <- SRC[15];
(* Repeat operation for bytes 3rd through 31*)
r32[31] <- SRC[255];

PMOVMSKB (with 64-bit source operand and r64)
  r64[0] <- SRC[7];
  r64[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 6 *)
  r64[7] <- SRC[63];
  r64[63:8] <- ZERO_FILL;

(V)PMOVMSKB (with 128-bit source operand and r64)
   r64[0] <- SRC[7];
   r64[1] <- SRC[15];
   (* Repeat operation for bytes 2 through 14 *)
   r64[15] <- SRC[127];
   r64[63:16] <- ZERO_FILL;

VPMOVMSKB (with 256-bit source operand and r64)
r64[0] <- SRC[7];
r64[1] <- SRC[15];
(* Repeat operation for bytes 2 through 31*)
r64[31] <- SRC[255];
r64[63:32] <- ZERO_FILL;

Intel C/C++ Compiler Intrinsic Equivalent
PMOVMSKB:          int _mm_movemask_pi8(__m64 a)
(V)PMOVMSKB:       int _mm_movemask_epi8 ( __m128i a)
VPMOVMSKB:         int _mm256_movemask_epi8 ( __m256i a)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
See Exceptions Type 7; additionally
#UD                  If VEX.vvvv != 1111B.






platform: x86_64
mnem: PMOVSX
description:
PMOVSX-Packed Move with Sign Extend
 Opcode/                         Op /   64/32      CPUID      Description
 Instruction                     En     bit Mode   Feature
                                        Support    Flag
 66 0f 38 20 /r                  RM     V/V        SSE4_1     Sign extend 8 packed 8-bit integers in the low 8 bytes
 PMOVSXBW xmm1, xmm2/m64                                      of xmm2/m64 to 8 packed 16-bit integers in xmm1.
 66 0f 38 21 /r                  RM     V/V        SSE4_1     Sign extend 4 packed 8-bit integers in the low 4 bytes
 PMOVSXBD xmm1, xmm2/m32                                      of xmm2/m32 to 4 packed 32-bit integers in xmm1.
 66 0f 38 22 /r                  RM     V/V        SSE4_1     Sign extend 2 packed 8-bit integers in the low 2 bytes
 PMOVSXBQ xmm1, xmm2/m16                                      of xmm2/m16 to 2 packed 64-bit integers in xmm1.
 66 0f 38 23/r                   RM     V/V        SSE4_1     Sign extend 4 packed 16-bit integers in the low 8 bytes
 PMOVSXWD xmm1, xmm2/m64                                      of xmm2/m64 to 4 packed 32-bit integers in xmm1.
 66 0f 38 24 /r                  RM     V/V        SSE4_1     Sign extend 2 packed 16-bit integers in the low 4 bytes
 PMOVSXWQ xmm1, xmm2/m32                                      of xmm2/m32 to 2 packed 64-bit integers in xmm1.
 66 0f 38 25 /r                  RM     V/V        SSE4_1     Sign extend 2 packed 32-bit integers in the low 8 bytes
 PMOVSXDQ xmm1, xmm2/m64                                      of xmm2/m64 to 2 packed 64-bit integers in xmm1.
 VEX.128.66.0F38.WIG 20 /r       RM     V/V        AVX        Sign extend 8 packed 8-bit integers in the low 8 bytes
 VPMOVSXBW xmm1, xmm2/m64                                     of xmm2/m64 to 8 packed 16-bit integers in xmm1.
 VEX.128.66.0F38.WIG 21 /r       RM     V/V        AVX        Sign extend 4 packed 8-bit integers in the low 4 bytes
 VPMOVSXBD xmm1, xmm2/m32                                     of xmm2/m32 to 4 packed 32-bit integers in xmm1.
 VEX.128.66.0F38.WIG 22 /r       RM     V/V        AVX        Sign extend 2 packed 8-bit integers in the low 2 bytes
 VPMOVSXBQ xmm1, xmm2/m16                                     of xmm2/m16 to 2 packed 64-bit integers in xmm1.
 VEX.128.66.0F38.WIG 23 /r       RM     V/V        AVX        Sign extend 4 packed 16-bit integers in the low 8 bytes
 VPMOVSXWD xmm1, xmm2/m64                                     of xmm2/m64 to 4 packed 32-bit integers in xmm1.
 VEX.128.66.0F38.WIG 24 /r       RM     V/V        AVX        Sign extend 2 packed 16-bit integers in the low 4 bytes
 VPMOVSXWQ xmm1, xmm2/m32                                     of xmm2/m32 to 2 packed 64-bit integers in xmm1.
 VEX.128.66.0F38.WIG 25 /r       RM     V/V        AVX        Sign extend 2 packed 32-bit integers in the low 8 bytes
 VPMOVSXDQ xmm1, xmm2/m64                                     of xmm2/m64 to 2 packed 64-bit integers in xmm1.
 VEX.256.66.0F38.WIG 20 /r       RM     V/V        AVX2       Sign extend 16 packed 8-bit integers in xmm2/m128 to
 VPMOVSXBW ymm1, xmm2/m128                                    16 packed 16-bit integers in ymm1.
 VEX.256.66.0F38.WIG 21 /r       RM     V/V        AVX2       Sign extend 8 packed 8-bit integers in the low 8 bytes
 VPMOVSXBD ymm1, xmm2/m64                                     of xmm2/m64 to 8 packed 32-bit integers in ymm1.
 VEX.256.66.0F38.WIG 22 /r       RM     V/V        AVX2       Sign extend 4 packed 8-bit integers in the low 4 bytes
 VPMOVSXBQ ymm1, xmm2/m32                                     of xmm2/m32 to 4 packed 64-bit integers in ymm1.
 VEX.256.66.0F38.WIG 23 /r       RM     V/V        AVX2       Sign extend 8 packed 16-bit integers in the low 16
 VPMOVSXWD ymm1, xmm2/m128                                    bytes of xmm2/m128 to 8 packed 32-bit integers in
                                                              ymm1.
 VEX.256.66.0F38.WIG 24 /r       RM     V/V        AVX2       Sign extend 4 packed 16-bit integers in the low 8 bytes
 VPMOVSXWQ ymm1, xmm2/m64                                     of xmm2/m64 to 4 packed 64-bit integers in ymm1.
 VEX.256.66.0F38.WIG 25 /r       RM     V/V        AVX2       Sign extend 4 packed 32-bit integers in the low 16
 VPMOVSXDQ ymm1, xmm2/m128                                    bytes of xmm2/m128 to 4 packed 64-bit integers in
                                                              ymm1.
 EVEX.128.66.0F38.WIG 20 /r      HVM    V/V        AVX512VL   Sign extend 8 packed 8-bit integers in xmm2/m64 to 8
 VPMOVSXBW xmm1 {k1}{z},                           AVX512BW   packed 16-bit integers in zmm1.
 xmm2/m64
 EVEX.256.66.0F38.WIG 20 /r      HVM    V/V        AVX512VL   Sign extend 16 packed 8-bit integers in xmm2/m128 to
 VPMOVSXBW ymm1 {k1}{z},                           AVX512BW   16 packed 16-bit integers in ymm1.
 xmm2/m128
 EVEX.512.66.0F38.WIG 20 /r      HVM    V/V        AVX512BW   Sign extend 32 packed 8-bit integers in ymm2/m256 to
 VPMOVSXBW zmm1 {k1}{z},                                      32 packed 16-bit integers in zmm1.
 ymm2/m256
 EVEX.128.66.0F38.WIG 21 /r      QVM    V/V        AVX512VL   Sign extend 4 packed 8-bit integers in the low 4 bytes
 VPMOVSXBD xmm1 {k1}{z},                           AVX512F    of xmm2/m32 to 4 packed 32-bit integers in xmm1
 xmm2/m32                                                     subject to writemask k1.



 Opcode/                              Op /   64/32      CPUID      Description
 Instruction                          En     bit Mode   Feature
                                             Support    Flag
 EVEX.256.66.0F38.WIG 21 /r           QVM    V/V        AVX512VL   Sign extend 8 packed 8-bit integers in the low 8 bytes
 VPMOVSXBD ymm1 {k1}{z},                                AVX512F    of xmm2/m64 to 8 packed 32-bit integers in ymm1
 xmm2/m64                                                          subject to writemask k1.
 EVEX.512.66.0F38.WIG 21 /r           QVM    V/V        AVX512F    Sign extend 16 packed 8-bit integers in the low 16
 VPMOVSXBD zmm1 {k1}{z},                                           bytes of xmm2/m128 to 16 packed 32-bit integers in
 xmm2/m128                                                         zmm1 subject to writemask k1.
 EVEX.128.66.0F38.WIG 22 /r           OVM    V/V        AVX512VL   Sign extend 2 packed 8-bit integers in the low 2 bytes
 VPMOVSXBQ xmm1 {k1}{z},                                AVX512F    of xmm2/m16 to 2 packed 64-bit integers in xmm1
 xmm2/m16                                                          subject to writemask k1.
 EVEX.256.66.0F38.WIG 22 /r           OVM    V/V        AVX512VL   Sign extend 4 packed 8-bit integers in the low 4 bytes
 VPMOVSXBQ ymm1 {k1}{z},                                AVX512F    of xmm2/m32 to 4 packed 64-bit integers in ymm1
 xmm2/m32                                                          subject to writemask k1.
 EVEX.512.66.0F38.WIG 22 /r           OVM    V/V        AVX512F    Sign extend 8 packed 8-bit integers in the low 8 bytes
 VPMOVSXBQ zmm1 {k1}{z},                                           of xmm2/m64 to 8 packed 64-bit integers in zmm1
 xmm2/m64                                                          subject to writemask k1.
 EVEX.128.66.0F38.WIG 23 /r           HVM    V/V        AVX512VL   Sign extend 4 packed 16-bit integers in the low 8 bytes
 VPMOVSXWD xmm1 {k1}{z},                                AVX512F    of ymm2/mem to 4 packed 32-bit integers in xmm1
 xmm2/m64                                                          subject to writemask k1.
 EVEX.256.66.0F38.WIG 23 /r           HVM    V/V        AVX512VL   Sign extend 8 packed 16-bit integers in the low 16
 VPMOVSXWD ymm1 {k1}{z},                                AVX512F    bytes of ymm2/m128 to 8 packed 32-bit integers in
 xmm2/m128                                                         ymm1 subject to writemask k1.
 EVEX.512.66.0F38.WIG 23 /r           HVM    V/V        AVX512F    Sign extend 16 packed 16-bit integers in the low 32
 VPMOVSXWD zmm1 {k1}{z},                                           bytes of ymm2/m256 to 16 packed 32-bit integers in
 ymm2/m256                                                         zmm1 subject to writemask k1.
 EVEX.128.66.0F38.WIG 24 /r           QVM    V/V        AVX512VL   Sign extend 2 packed 16-bit integers in the low 4 bytes
 VPMOVSXWQ xmm1 {k1}{z},                                AVX512F    of xmm2/m32 to 2 packed 64-bit integers in xmm1
 xmm2/m32                                                          subject to writemask k1.
 EVEX.256.66.0F38.WIG 24 /r           QVM    V/V        AVX512VL   Sign extend 4 packed 16-bit integers in the low 8 bytes
 VPMOVSXWQ ymm1 {k1}{z},                                AVX512F    of xmm2/m64 to 4 packed 64-bit integers in ymm1
 xmm2/m64                                                          subject to writemask k1.
 EVEX.512.66.0F38.WIG 24 /r           QVM    V/V        AVX512F    Sign extend 8 packed 16-bit integers in the low 16
 VPMOVSXWQ zmm1 {k1}{z},                                           bytes of xmm2/m128 to 8 packed 64-bit integers in
 xmm2/m128                                                         zmm1 subject to writemask k1.
 EVEX.128.66.0F38.W0 25 /r            HVM    V/V        AVX512VL   Sign extend 2 packed 32-bit integers in the low 8 bytes
 VPMOVSXDQ xmm1 {k1}{z},                                AVX512F    of xmm2/m64 to 2 packed 64-bit integers in zmm1
 xmm2/m64                                                          using writemask k1.
 EVEX.256.66.0F38.W0 25 /r            HVM    V/V        AVX512VL   Sign extend 4 packed 32-bit integers in the low 16
 VPMOVSXDQ ymm1 {k1}{z},                                AVX512F    bytes of xmm2/m128 to 4 packed 64-bit integers in
 xmm2/m128                                                         zmm1 using writemask k1.
 EVEX.512.66.0F38.W0 25 /r            HVM    V/V        AVX512F    Sign extend 8 packed 32-bit integers in the low 32
 VPMOVSXDQ zmm1 {k1}{z},                                           bytes of ymm2/m256 to 8 packed 64-bit integers in
 ymm2/m256                                                         zmm1 using writemask k1.





                                          Instruction Operand Encoding
         Op/En              Operand 1              Operand 2             Operand 3                Operand 4
          RM              ModRM:reg (w)          ModRM:r/m (r)              NA                       NA
    HVM, QVM, OVM         ModRM:reg (w)          ModRM:r/m (r)              NA                       NA

Description
Legacy and VEX encoded versions: Packed byte, word, or dword integers in the low bytes of the source operand
(second operand) are sign extended to word, dword, or quadword integers and stored in packed signed bytes the
destination operand.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the corresponding destination register are
zeroed.
VEX.256 and EVEX.256 encoded versions: Bits (MAX_VL-1:256) of the corresponding destination register are
zeroed.
EVEX encoded versions: Packed byte, word or dword integers starting from the low bytes of the source operand
(second operand) are sign extended to word, dword or quadword integers and stored to the destination operand
under the writemask. The destination register is XMM, YMM or ZMM Register.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





Operation
Packed_Sign_Extend_BYTE_to_WORD(DEST, SRC)
DEST[15:0] <-SignExtend(SRC[7:0]);
DEST[31:16] <-SignExtend(SRC[15:8]);
DEST[47:32] <-SignExtend(SRC[23:16]);
DEST[63:48] <-SignExtend(SRC[31:24]);
DEST[79:64] <-SignExtend(SRC[39:32]);
DEST[95:80] <-SignExtend(SRC[47:40]);
DEST[111:96] <-SignExtend(SRC[55:48]);
DEST[127:112] <-SignExtend(SRC[63:56]);

Packed_Sign_Extend_BYTE_to_DWORD(DEST, SRC)
DEST[31:0] <-SignExtend(SRC[7:0]);
DEST[63:32] <-SignExtend(SRC[15:8]);
DEST[95:64] <-SignExtend(SRC[23:16]);
DEST[127:96] <-SignExtend(SRC[31:24]);

Packed_Sign_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] <-SignExtend(SRC[7:0]);
DEST[127:64] <-SignExtend(SRC[15:8]);

Packed_Sign_Extend_WORD_to_DWORD(DEST, SRC)
DEST[31:0] <-SignExtend(SRC[15:0]);
DEST[63:32] <-SignExtend(SRC[31:16]);
DEST[95:64] <-SignExtend(SRC[47:32]);
DEST[127:96] <-SignExtend(SRC[63:48]);

Packed_Sign_Extend_WORD_to_QWORD(DEST, SRC)
DEST[63:0] <-SignExtend(SRC[15:0]);
DEST[127:64] <-SignExtend(SRC[31:16]);

Packed_Sign_Extend_DWORD_to_QWORD(DEST, SRC)
DEST[63:0] <-SignExtend(SRC[31:0]);
DEST[127:64] <-SignExtend(SRC[63:32]);

VPMOVSXBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])
    Packed_Sign_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- TEMP_DEST[i+15:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0



          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVSXBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
    Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
    Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])
    Packed_Sign_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVSXBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
    Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])
FI;
IF VL >= 512
    Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])
    Packed_Sign_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPMOVSXWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])
    Packed_Sign_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVSXWQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
    Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
    Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])
    Packed_Sign_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPMOVSXDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])
    Packed_Sign_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVSXBW (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0

VPMOVSXBD (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] <- 0

VPMOVSXBQ (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
DEST[MAX_VL-1:256] <- 0

VPMOVSXWD (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0

VPMOVSXWQ (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] <- 0

VPMOVSXDQ (VEX.256 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0




VPMOVSXBW (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_WORDDEST[127:0], SRC[127:0]()
DEST[MAX_VL-1:128] <-0

VPMOVSXBD (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] <-0

VPMOVSXBQ (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] <-0

VPMOVSXWD (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] <-0

VPMOVSXWQ (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] <-0

VPMOVSXDQ (VEX.128 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] <-0

PMOVSXBW
Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

PMOVSXBD
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

PMOVSXBQ
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

PMOVSXWD
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

PMOVSXWQ
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

PMOVSXDQ
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[127:0])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VPMOVSXBW __m512i _mm512_cvtepi8_epi16(__m512i a);
VPMOVSXBW __m512i _mm512_mask_cvtepi8_epi16(__m512i a, __mmask32 k, __m512i b);
VPMOVSXBW __m512i _mm512_maskz_cvtepi8_epi16( __mmask32 k, __m512i b);
VPMOVSXBD __m512i _mm512_cvtepi8_epi32(__m512i a);
VPMOVSXBD __m512i _mm512_mask_cvtepi8_epi32(__m512i a, __mmask16 k, __m512i b);



VPMOVSXBD __m512i _mm512_maskz_cvtepi8_epi32( __mmask16 k, __m512i b);
VPMOVSXBQ __m512i _mm512_cvtepi8_epi64(__m512i a);
VPMOVSXBQ __m512i _mm512_mask_cvtepi8_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXBQ __m512i _mm512_maskz_cvtepi8_epi64( __mmask8 k, __m512i a);
VPMOVSXDQ __m512i _mm512_cvtepi32_epi64(__m512i a);
VPMOVSXDQ __m512i _mm512_mask_cvtepi32_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXDQ __m512i _mm512_maskz_cvtepi32_epi64( __mmask8 k, __m512i a);
VPMOVSXWD __m512i _mm512_cvtepi16_epi32(__m512i a);
VPMOVSXWD __m512i _mm512_mask_cvtepi16_epi32(__m512i a, __mmask16 k, __m512i b);
VPMOVSXWD __m512i _mm512_maskz_cvtepi16_epi32(__mmask16 k, __m512i a);
VPMOVSXWQ __m512i _mm512_cvtepi16_epi64(__m512i a);
VPMOVSXWQ __m512i _mm512_mask_cvtepi16_epi64(__m512i a, __mmask8 k, __m512i b);
VPMOVSXWQ __m512i _mm512_maskz_cvtepi16_epi64( __mmask8 k, __m512i a);
VPMOVSXBW __m256i _mm256_cvtepi8_epi16(__m256i a);
VPMOVSXBW __m256i _mm256_mask_cvtepi8_epi16(__m256i a, __mmask16 k, __m256i b);
VPMOVSXBW __m256i _mm256_maskz_cvtepi8_epi16( __mmask16 k, __m256i b);
VPMOVSXBD __m256i _mm256_cvtepi8_epi32(__m256i a);
VPMOVSXBD __m256i _mm256_mask_cvtepi8_epi32(__m256i a, __mmask8 k, __m256i b);
VPMOVSXBD __m256i _mm256_maskz_cvtepi8_epi32( __mmask8 k, __m256i b);
VPMOVSXBQ __m256i _mm256_cvtepi8_epi64(__m256i a);
VPMOVSXBQ __m256i _mm256_mask_cvtepi8_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXBQ __m256i _mm256_maskz_cvtepi8_epi64( __mmask8 k, __m256i a);
VPMOVSXDQ __m256i _mm256_cvtepi32_epi64(__m256i a);
VPMOVSXDQ __m256i _mm256_mask_cvtepi32_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXDQ __m256i _mm256_maskz_cvtepi32_epi64( __mmask8 k, __m256i a);
VPMOVSXWD __m256i _mm256_cvtepi16_epi32(__m256i a);
VPMOVSXWD __m256i _mm256_mask_cvtepi16_epi32(__m256i a, __mmask16 k, __m256i b);
VPMOVSXWD __m256i _mm256_maskz_cvtepi16_epi32(__mmask16 k, __m256i a);
VPMOVSXWQ __m256i _mm256_cvtepi16_epi64(__m256i a);
VPMOVSXWQ __m256i _mm256_mask_cvtepi16_epi64(__m256i a, __mmask8 k, __m256i b);
VPMOVSXWQ __m256i _mm256_maskz_cvtepi16_epi64( __mmask8 k, __m256i a);
VPMOVSXBW __m128i _mm_mask_cvtepi8_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBW __m128i _mm_maskz_cvtepi8_epi16( __mmask8 k, __m128i b);
VPMOVSXBD __m128i _mm_mask_cvtepi8_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBD __m128i _mm_maskz_cvtepi8_epi32( __mmask8 k, __m128i b);
VPMOVSXBQ __m128i _mm_mask_cvtepi8_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXBQ __m128i _mm_maskz_cvtepi8_epi64( __mmask8 k, __m128i a);
VPMOVSXDQ __m128i _mm_mask_cvtepi32_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXDQ __m128i _mm_maskz_cvtepi32_epi64( __mmask8 k, __m128i a);
VPMOVSXWD __m128i _mm_mask_cvtepi16_epi32(__m128i a, __mmask16 k, __m128i b);
VPMOVSXWD __m128i _mm_maskz_cvtepi16_epi32(__mmask16 k, __m128i a);
VPMOVSXWQ __m128i _mm_mask_cvtepi16_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVSXWQ __m128i _mm_maskz_cvtepi16_epi64( __mmask8 k, __m128i a);
PMOVSXBW __m128i _mm_ cvtepi8_epi16 ( __m128i a);
PMOVSXBD __m128i _mm_ cvtepi8_epi32 ( __m128i a);
PMOVSXBQ __m128i _mm_ cvtepi8_epi64 ( __m128i a);
PMOVSXWD __m128i _mm_ cvtepi16_epi32 ( __m128i a);
PMOVSXWQ __m128i _mm_ cvtepi16_epi64 ( __m128i a);
PMOVSXDQ __m128i _mm_ cvtepi32_epi64 ( __m128i a);

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E5.
#UD                    If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PMOVZX
description:
PMOVZX-Packed Move with Zero Extend
 Opcode/                         Op /   64/32      CPUID     Description
 Instruction                     En     bit Mode   Feature
                                        Support    Flag
 66 0f 38 30 /r                  RM     V/V        SSE4_1    Zero extend 8 packed 8-bit integers in the low 8
 PMOVZXBW xmm1, xmm2/m64                                     bytes of xmm2/m64 to 8 packed 16-bit integers in
                                                             xmm1.
 66 0f 38 31 /r                  RM     V/V        SSE4_1    Zero extend 4 packed 8-bit integers in the low 4
 PMOVZXBD xmm1, xmm2/m32                                     bytes of xmm2/m32 to 4 packed 32-bit integers in
                                                             xmm1.
 66 0f 38 32 /r                  RM     V/V        SSE4_1    Zero extend 2 packed 8-bit integers in the low 2
 PMOVZXBQ xmm1, xmm2/m16                                     bytes of xmm2/m16 to 2 packed 64-bit integers in
                                                             xmm1.
 66 0f 38 33 /r                  RM     V/V        SSE4_1    Zero extend 4 packed 16-bit integers in the low 8
 PMOVZXWD xmm1, xmm2/m64                                     bytes of xmm2/m64 to 4 packed 32-bit integers in
                                                             xmm1.
 66 0f 38 34 /r                  RM     V/V        SSE4_1    Zero extend 2 packed 16-bit integers in the low 4
 PMOVZXWQ xmm1, xmm2/m32                                     bytes of xmm2/m32 to 2 packed 64-bit integers in
                                                             xmm1.
 66 0f 38 35 /r                  RM     V/V        SSE4_1    Zero extend 2 packed 32-bit integers in the low 8
 PMOVZXDQ xmm1, xmm2/m64                                     bytes of xmm2/m64 to 2 packed 64-bit integers in
                                                             xmm1.
 VEX.128.66.0F38.WIG 30 /r       RM     V/V        AVX       Zero extend 8 packed 8-bit integers in the low 8
 VPMOVZXBW xmm1, xmm2/m64                                    bytes of xmm2/m64 to 8 packed 16-bit integers in
                                                             xmm1.
 VEX.128.66.0F38.WIG 31 /r       RM     V/V        AVX       Zero extend 4 packed 8-bit integers in the low 4
 VPMOVZXBD xmm1, xmm2/m32                                    bytes of xmm2/m32 to 4 packed 32-bit integers in
                                                             xmm1.
 VEX.128.66.0F38.WIG 32 /r       RM     V/V        AVX       Zero extend 2 packed 8-bit integers in the low 2
 VPMOVZXBQ xmm1, xmm2/m16                                    bytes of xmm2/m16 to 2 packed 64-bit integers in
                                                             xmm1.
 VEX.128.66.0F38.WIG 33 /r       RM     V/V        AVX       Zero extend 4 packed 16-bit integers in the low 8
 VPMOVZXWD xmm1, xmm2/m64                                    bytes of xmm2/m64 to 4 packed 32-bit integers in
                                                             xmm1.
 VEX.128.66.0F38.WIG 34 /r       RM     V/V        AVX       Zero extend 2 packed 16-bit integers in the low 4
 VPMOVZXWQ xmm1, xmm2/m32                                    bytes of xmm2/m32 to 2 packed 64-bit integers in
                                                             xmm1.
 VEX.128.66.0F 38.WIG 35 /r      RM     V/V        AVX       Zero extend 2 packed 32-bit integers in the low 8
 VPMOVZXDQ xmm1, xmm2/m64                                    bytes of xmm2/m64 to 2 packed 64-bit integers in
                                                             xmm1.
 VEX.256.66.0F38.WIG 30 /r       RM     V/V        AVX2      Zero extend 16 packed 8-bit integers in
 VPMOVZXBW ymm1, xmm2/m128                                   xmm2/m128 to 16 packed 16-bit integers in ymm1.
 VEX.256.66.0F38.WIG 31 /r       RM     V/V        AVX2      Zero extend 8 packed 8-bit integers in the low 8
 VPMOVZXBD ymm1, xmm2/m64                                    bytes of xmm2/m64 to 8 packed 32-bit integers in
                                                             ymm1.
 VEX.256.66.0F38.WIG 32 /r       RM     V/V        AVX2      Zero extend 4 packed 8-bit integers in the low 4
 VPMOVZXBQ ymm1, xmm2/m32                                    bytes of xmm2/m32 to 4 packed 64-bit integers in
                                                             ymm1.
 VEX.256.66.0F38.WIG 33 /r       RM     V/V        AVX2      Zero extend 8 packed 16-bit integers xmm2/m128
 VPMOVZXWD ymm1, xmm2/m128                                   to 8 packed 32-bit integers in ymm1.
 VEX.256.66.0F38.WIG 34 /r       RM     V/V        AVX2      Zero extend 4 packed 16-bit integers in the low 8
 VPMOVZXWQ ymm1, xmm2/m64                                    bytes of xmm2/m64 to 4 packed 64-bit integers in
                                                             xmm1.
 VEX.256.66.0F38.WIG 35 /r       RM     V/V        AVX2      Zero extend 4 packed 32-bit integers in
 VPMOVZXDQ ymm1, xmm2/m128                                   xmm2/m128 to 4 packed 64-bit integers in ymm1.


 Opcode/                              Op /   64/32      CPUID      Description
 Instruction                          En     bit Mode   Feature
                                             Support    Flag
 EVEX.128.66.0F38 30.WIG /r           HVM    V/V        AVX512VL   Zero extend 8 packed 8-bit integers in the low 8
 VPMOVZXBW xmm1 {k1}{z}, xmm2/m64                       AVX512BW   bytes of xmm2/m64 to 8 packed 16-bit integers in
                                                                   xmm1.
 EVEX.256.66.0F38.WIG 30 /r           HVM    V/V        AVX512VL   Zero extend 16 packed 8-bit integers in
 VPMOVZXBW ymm1 {k1}{z},                                AVX512BW   xmm2/m128 to 16 packed 16-bit integers in ymm1.
 xmm2/m128
 EVEX.512.66.0F38.WIG 30 /r           HVM    V/V        AVX512BW   Zero extend 32 packed 8-bit integers in
 VPMOVZXBW zmm1 {k1}{z},                                           ymm2/m256 to 32 packed 16-bit integers in zmm1.
 ymm2/m256
 EVEX.128.66.0F38.WIG 31 /r           QVM    V/V        AVX512VL   Zero extend 4 packed 8-bit integers in the low 4
 VPMOVZXBD xmm1 {k1}{z}, xmm2/m32                       AVX512F    bytes of xmm2/m32 to 4 packed 32-bit integers in
                                                                   xmm1 subject to writemask k1.
 EVEX.256.66.0F38.WIG 31 /r           QVM    V/V        AVX512VL   Zero extend 8 packed 8-bit integers in the low 8
 VPMOVZXBD ymm1 {k1}{z}, xmm2/m64                       AVX512F    bytes of xmm2/m64 to 8 packed 32-bit integers in
                                                                   ymm1 subject to writemask k1.
 EVEX.512.66.0F38.WIG 31 /r           QVM    V/V        AVX512F    Zero extend 16 packed 8-bit integers in
 VPMOVZXBD zmm1 {k1}{z},                                           xmm2/m128 to 16 packed 32-bit integers in zmm1
 xmm2/m128                                                         subject to writemask k1.
 EVEX.128.66.0F38.WIG 32 /r           OVM    V/V        AVX512VL   Zero extend 2 packed 8-bit integers in the low 2
 VPMOVZXBQ xmm1 {k1}{z}, xmm2/m16                       AVX512F    bytes of xmm2/m16 to 2 packed 64-bit integers in
                                                                   xmm1 subject to writemask k1.
 EVEX.256.66.0F38.WIG 32 /r           OVM    V/V        AVX512VL   Zero extend 4 packed 8-bit integers in the low 4
 VPMOVZXBQ ymm1 {k1}{z}, xmm2/m32                       AVX512F    bytes of xmm2/m32 to 4 packed 64-bit integers in
                                                                   ymm1 subject to writemask k1.
 EVEX.512.66.0F38.WIG 32 /r           OVM    V/V        AVX512F    Zero extend 8 packed 8-bit integers in the low 8
 VPMOVZXBQ zmm1 {k1}{z}, xmm2/m64                                  bytes of xmm2/m64 to 8 packed 64-bit integers in
                                                                   zmm1 subject to writemask k1.
 EVEX.128.66.0F38.WIG 33 /r           HVM    V/V        AVX512VL   Zero extend 4 packed 16-bit integers in the low 8
 VPMOVZXWD xmm1 {k1}{z}, xmm2/m64                       AVX512F    bytes of xmm2/m64 to 4 packed 32-bit integers in
                                                                   xmm1 subject to writemask k1.
 EVEX.256.66.0F38.WIG 33 /r           HVM    V/V        AVX512VL   Zero extend 8 packed 16-bit integers in
 VPMOVZXWD ymm1 {k1}{z},                                AVX512F    xmm2/m128 to 8 packed 32-bit integers in zmm1
 xmm2/m128                                                         subject to writemask k1.
 EVEX.512.66.0F38.WIG 33 /r           HVM    V/V        AVX512F    Zero extend 16 packed 16-bit integers in
 VPMOVZXWD zmm1 {k1}{z},                                           ymm2/m256 to 16 packed 32-bit integers in zmm1
 ymm2/m256                                                         subject to writemask k1.
 EVEX.128.66.0F38.WIG 34 /r           QVM    V/V        AVX512VL   Zero extend 2 packed 16-bit integers in the low 4
 VPMOVZXWQ xmm1 {k1}{z}, xmm2/m32                       AVX512F    bytes of xmm2/m32 to 2 packed 64-bit integers in
                                                                   xmm1 subject to writemask k1.
 EVEX.256.66.0F38.WIG 34 /r           QVM    V/V        AVX512VL   Zero extend 4 packed 16-bit integers in the low 8
 VPMOVZXWQ ymm1 {k1}{z}, xmm2/m64                       AVX512F    bytes of xmm2/m64 to 4 packed 64-bit integers in
                                                                   ymm1 subject to writemask k1.
 EVEX.512.66.0F38.WIG 34 /r           QVM    V/V        AVX512F    Zero extend 8 packed 16-bit integers in
 VPMOVZXWQ zmm1 {k1}{z},                                           xmm2/m128 to 8 packed 64-bit integers in zmm1
 xmm2/m128                                                         subject to writemask k1.




 Opcode/                                 Op /      64/32        CPUID      Description
 Instruction                             En        bit Mode     Feature
                                                   Support      Flag
 EVEX.128.66.0F38.W0 35 /r               HVM       V/V          AVX512VL   Zero extend 2 packed 32-bit integers in the low 8
 VPMOVZXDQ xmm1 {k1}{z}, xmm2/m64                               AVX512F    bytes of xmm2/m64 to 2 packed 64-bit integers in
                                                                           zmm1 using writemask k1.
 EVEX.256.66.0F38.W0 35 /r               HVM       V/V          AVX512VL   Zero extend 4 packed 32-bit integers in
 VPMOVZXDQ ymm1 {k1}{z},                                        AVX512F    xmm2/m128 to 4 packed 64-bit integers in zmm1
 xmm2/m128                                                                 using writemask k1.
 EVEX.512.66.0F38.W0 35 /r               HVM       V/V          AVX512F    Zero extend 8 packed 32-bit integers in
 VPMOVZXDQ zmm1 {k1}{z},                                                   ymm2/m256 to 8 packed 64-bit integers in zmm1
 ymm2/m256                                                                 using writemask k1.


                                                Instruction Operand Encoding
        Op/En                Operand 1                    Operand 2             Operand 3                   Operand 4
          RM             ModRM:reg (w)                   ModRM:r/m (r)             NA                          NA
   HVM, QVM, OVM         ModRM:reg (w)                   ModRM:r/m (r)             NA                          NA

Description
Legacy, VEX and EVEX encoded versions: Packed byte, word, or dword integers starting from the low bytes of the
source operand (second operand) are zero extended to word, dword, or quadword integers and stored in packed
signed bytes the destination operand.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the corresponding destination register are zeroed.
EVEX encoded versions: Packed dword integers starting from the low bytes of the source operand (second
operand) are zero extended to quadword integers and stored to the destination operand under the writemask.The
destination register is XMM, YMM or ZMM Register.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation
Packed_Zero_Extend_BYTE_to_WORD(DEST, SRC)
DEST[15:0] <-ZeroExtend(SRC[7:0]);
DEST[31:16] <-ZeroExtend(SRC[15:8]);
DEST[47:32] <-ZeroExtend(SRC[23:16]);
DEST[63:48] <-ZeroExtend(SRC[31:24]);
DEST[79:64] <-ZeroExtend(SRC[39:32]);
DEST[95:80] <-ZeroExtend(SRC[47:40]);
DEST[111:96] <-ZeroExtend(SRC[55:48]);
DEST[127:112] <-ZeroExtend(SRC[63:56]);

Packed_Zero_Extend_BYTE_to_DWORD(DEST, SRC)
DEST[31:0] <-ZeroExtend(SRC[7:0]);
DEST[63:32] <-ZeroExtend(SRC[15:8]);
DEST[95:64] <-ZeroExtend(SRC[23:16]);
DEST[127:96] <-ZeroExtend(SRC[31:24]);

Packed_Zero_Extend_BYTE_to_QWORD(DEST, SRC)
DEST[63:0] <-ZeroExtend(SRC[7:0]);
DEST[127:64] <-ZeroExtend(SRC[15:8]);





Packed_Zero_Extend_WORD_to_DWORD(DEST, SRC)
DEST[31:0] <-ZeroExtend(SRC[15:0]);
DEST[63:32] <-ZeroExtend(SRC[31:16]);
DEST[95:64] <-ZeroExtend(SRC[47:32]);
DEST[127:96] <-ZeroExtend(SRC[63:48]);

Packed_Zero_Extend_WORD_to_QWORD(DEST, SRC)
DEST[63:0] <-ZeroExtend(SRC[15:0]);
DEST[127:64] <-ZeroExtend(SRC[31:16]);

Packed_Zero_Extend_DWORD_to_QWORD(DEST, SRC)
DEST[63:0] <-ZeroExtend(SRC[31:0]);
DEST[127:64] <-ZeroExtend(SRC[63:32]);

VPMOVZXBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[383:256], SRC[191:128])
    Packed_Zero_Extend_BYTE_to_WORD(TMP_DEST[511:384], SRC[255:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- TEMP_DEST[i+15:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVZXBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
    Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
    Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[383:256], SRC[95:64])
    Packed_Zero_Extend_BYTE_to_DWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*            ; merging-masking



                THEN *DEST[i+31:i] remains unchanged*
                ELSE *zeroing-masking*             ; zeroing-masking
                    DEST[i+31:i] <- 0
          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVZXBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[127:0], SRC[15:0])
IF VL >= 256
    Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[255:128], SRC[31:16])
FI;
IF VL >= 512
    Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[383:256], SRC[47:32])
    Packed_Zero_Extend_BYTE_to_QWORD(TMP_DEST[511:384], SRC[63:48])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVZXWD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[383:256], SRC[191:128])
    Packed_Zero_Extend_WORD_to_DWORD(TMP_DEST[511:384], SRC[256:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TEMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR



DEST[MAX_VL-1:VL] <- 0

VPMOVZXWQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[127:0], SRC[31:0])
IF VL >= 256
    Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[255:128], SRC[63:32])
FI;
IF VL >= 512
    Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[383:256], SRC[95:64])
    Packed_Zero_Extend_WORD_to_QWORD(TMP_DEST[511:384], SRC[127:96])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVZXDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[127:0], SRC[63:0])
IF VL >= 256
    Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[255:128], SRC[127:64])
FI;
IF VL >= 512
    Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[383:256], SRC[191:128])
    Packed_Zero_Extend_DWORD_to_QWORD(TEMP_DEST[511:384], SRC[255:192])
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TEMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMOVZXBW (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0



VPMOVZXBD (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] <- 0

VPMOVZXBQ (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Zero_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
DEST[MAX_VL-1:256] <- 0

VPMOVZXWD (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0

VPMOVZXWQ (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
DEST[MAX_VL-1:256] <- 0

VPMOVZXDQ (VEX.256 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])
DEST[MAX_VL-1:256] <- 0

VPMOVZXBW (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_WORD()
DEST[MAX_VL-1:128] <-0

VPMOVZXBD (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD()
DEST[MAX_VL-1:128] <-0

VPMOVZXBQ (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD()
DEST[MAX_VL-1:128] <-0

VPMOVZXWD (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_DWORD()
DEST[MAX_VL-1:128] <-0

VPMOVZXWQ (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_QWORD()
DEST[MAX_VL-1:128] <-0

VPMOVZXDQ (VEX.128 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD()
DEST[MAX_VL-1:128] <-0

PMOVZXBW
Packed_Zero_Extend_BYTE_to_WORD()
DEST[MAX_VL-1:128] (Unmodified)




PMOVZXBD
Packed_Zero_Extend_BYTE_to_DWORD()
DEST[MAX_VL-1:128] (Unmodified)

PMOVZXBQ
Packed_Zero_Extend_BYTE_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)

PMOVZXWD
Packed_Zero_Extend_WORD_to_DWORD()
DEST[MAX_VL-1:128] (Unmodified)

PMOVZXWQ
Packed_Zero_Extend_WORD_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)

PMOVZXDQ
Packed_Zero_Extend_DWORD_to_QWORD()
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VPMOVZXBW __m512i _mm512_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m512i _mm512_mask_cvtepu8_epi16(__m512i a, __mmask32 k, __m256i b);
VPMOVZXBW __m512i _mm512_maskz_cvtepu8_epi16( __mmask32 k, __m256i b);
VPMOVZXBD __m512i _mm512_cvtepu8_epi32(__m128i a);
VPMOVZXBD __m512i _mm512_mask_cvtepu8_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXBD __m512i _mm512_maskz_cvtepu8_epi32( __mmask16 k, __m128i b);
VPMOVZXBQ __m512i _mm512_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m512i _mm512_mask_cvtepu8_epi64(__m512i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m512i _mm512_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m512i _mm512_cvtepu32_epi64(__m256i a);
VPMOVZXDQ __m512i _mm512_mask_cvtepu32_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXDQ __m512i _mm512_maskz_cvtepu32_epi64( __mmask8 k, __m256i a);
VPMOVZXWD __m512i _mm512_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m512i _mm512_mask_cvtepu16_epi32(__m512i a, __mmask16 k, __m128i b);
VPMOVZXWD __m512i _mm512_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);
VPMOVZXWQ __m512i _mm512_cvtepu16_epi64(__m256i a);
VPMOVZXWQ __m512i _mm512_mask_cvtepu16_epi64(__m512i a, __mmask8 k, __m256i b);
VPMOVZXWQ __m512i _mm512_maskz_cvtepu16_epi64( __mmask8 k, __m256i a);
VPMOVZXBW __m256i _mm256_cvtepu8_epi16(__m256i a);
VPMOVZXBW __m256i _mm256_mask_cvtepu8_epi16(__m256i a, __mmask16 k, __m128i b);
VPMOVZXBW __m256i _mm256_maskz_cvtepu8_epi16( __mmask16 k, __m128i b);
VPMOVZXBD __m256i _mm256_cvtepu8_epi32(__m128i a);
VPMOVZXBD __m256i _mm256_mask_cvtepu8_epi32(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBD __m256i _mm256_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_cvtepu8_epi64(__m128i a);
VPMOVZXBQ __m256i _mm256_mask_cvtepu8_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m256i _mm256_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m256i _mm256_cvtepu32_epi64(__m128i a);
VPMOVZXDQ __m256i _mm256_mask_cvtepu32_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m256i _mm256_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m256i _mm256_cvtepu16_epi32(__m128i a);
VPMOVZXWD __m256i _mm256_mask_cvtepu16_epi32(__m256i a, __mmask16 k, __m128i b);
VPMOVZXWD __m256i _mm256_maskz_cvtepu16_epi32(__mmask16 k, __m128i a);



VPMOVZXWQ __m256i _mm256_cvtepu16_epi64(__m128i a);
VPMOVZXWQ __m256i _mm256_mask_cvtepu16_epi64(__m256i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m256i _mm256_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
VPMOVZXBW __m128i _mm_mask_cvtepu8_epi16(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBW __m128i _mm_maskz_cvtepu8_epi16( __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_mask_cvtepu8_epi32(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBD __m128i _mm_maskz_cvtepu8_epi32( __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_mask_cvtepu8_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXBQ __m128i _mm_maskz_cvtepu8_epi64( __mmask8 k, __m128i a);
VPMOVZXDQ __m128i _mm_mask_cvtepu32_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXDQ __m128i _mm_maskz_cvtepu32_epi64( __mmask8 k, __m128i a);
VPMOVZXWD __m128i _mm_mask_cvtepu16_epi32(__m128i a, __mmask16 k, __m128i b);
VPMOVZXWD __m128i _mm_maskz_cvtepu16_epi32(__mmask8 k, __m128i a);
VPMOVZXWQ __m128i _mm_mask_cvtepu16_epi64(__m128i a, __mmask8 k, __m128i b);
VPMOVZXWQ __m128i _mm_maskz_cvtepu16_epi64( __mmask8 k, __m128i a);
PMOVZXBW __m128i _mm_ cvtepu8_epi16 ( __m128i a);
PMOVZXBD __m128i _mm_ cvtepu8_epi32 ( __m128i a);
PMOVZXBQ __m128i _mm_ cvtepu8_epi64 ( __m128i a);
PMOVZXWD __m128i _mm_ cvtepu16_epi32 ( __m128i a);
PMOVZXWQ __m128i _mm_ cvtepu16_epi64 ( __m128i a);
PMOVZXDQ __m128i _mm_ cvtepu32_epi64 ( __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E5.
#UD                  If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PMULDQ
description:
PMULDQ-Multiply Packed Doubleword Integers
 Opcode/                              Op /   64/32        CPUID      Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 66 0F 38 28 /r                       RM     V/V          SSE4_1     Multiply packed signed doubleword integers in xmm1 by
 PMULDQ xmm1, xmm2/m128                                              packed signed doubleword integers in xmm2/m128, and
                                                                     store the quadword results in xmm1.
 VEX.NDS.128.66.0F38.WIG 28 /r        RVM    V/V          AVX        Multiply packed signed doubleword integers in xmm2 by
 VPMULDQ xmm1, xmm2,                                                 packed signed doubleword integers in xmm3/m128, and
 xmm3/m128                                                           store the quadword results in xmm1.
 VEX.NDS.256.66.0F38.WIG 28 /r        RVM    V/V          AVX2       Multiply packed signed doubleword integers in ymm2 by
 VPMULDQ ymm1, ymm2,                                                 packed signed doubleword integers in ymm3/m256, and
 ymm3/m256                                                           store the quadword results in ymm1.
 EVEX.NDS.128.66.0F38.W1 28 /r        FV     V/V          AVX512VL   Multiply packed signed doubleword integers in xmm2 by
 VPMULDQ xmm1 {k1}{z}, xmm2,                              AVX512F    packed signed doubleword integers in
 xmm3/m128/m64bcst                                                   xmm3/m128/m64bcst, and store the quadword results in
                                                                     xmm1 using writemask k1.
 EVEX.NDS.256.66.0F38.W1 28 /r        FV     V/V          AVX512VL   Multiply packed signed doubleword integers in ymm2 by
 VPMULDQ ymm1 {k1}{z}, ymm2,                              AVX512F    packed signed doubleword integers in
 ymm3/m256/m64bcst                                                   ymm3/m256/m64bcst, and store the quadword results in
                                                                     ymm1 using writemask k1.
 EVEX.NDS.512.66.0F38.W1 28 /r        FV     V/V          AVX512F    Multiply packed signed doubleword integers in zmm2 by
 VPMULDQ zmm1 {k1}{z}, zmm2,                                         packed signed doubleword integers in
 zmm3/m512/m64bcst                                                   zmm3/m512/m64bcst, and store the quadword results in
                                                                     zmm1 using writemask k1.



                                               Instruction Operand Encoding
       Op/En                Operand 1                   Operand 2                  Operand 3                Operand 4
        RM               ModRM:reg (r, w)           ModRM:r/m (r)                     NA                       NA
        RVM               ModRM:reg (w)             VEX.vvvv (r)              ModRM:r/m (r)                    NA
         FV               ModRM:reg (w)             EVEX.vvvv (r)             ModRM:r/m (r)                    NA

Description
Multiplies packed signed doubleword integers in the even-numbered (zero-based reference) elements of the first
source operand with the packed signed doubleword integers in the corresponding elements of the second source
operand and stores packed signed quadword results in the destination operand.
128-bit Legacy SSE version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e. the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation. The first source
operand and the destination XMM operand is the same. The second source operand can be an XMM register or 128-
bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e., the first (low) and third doubleword element. For 128-bit memory operands, 128 bits are
fetched from memory, but only the first and third doublewords are used in the computation.The first source
operand and the destination operand are XMM registers. The second source operand can be an XMM register or
128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX.256 encoded version: The input signed doubleword integers are taken from the even-numbered elements of
the source operands, i.e. the first, 3rd, 5th, 7th doubleword element. For 256-bit memory operands, 256 bits are
fetched from memory, but only the four even-numbered doublewords are used in the computation. The first source
operand and the destination operand are YMM registers. The second source operand can be a YMM register or 256-
bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.





EVEX encoded version: The input signed doubleword integers are taken from the even-numbered elements of the
source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-
bit granularity.

Operation
VPMULDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[31:0])
                    ELSE DEST[i+63:i] <- SignExtend64( SRC1[i+31:i]) * SignExtend64( SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMULDQ (VEX.256 encoded version)
DEST[63:0] <-SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] <-SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[191:128] <-SignExtend64( SRC1[159:128]) * SignExtend64( SRC2[159:128])
DEST[255:192] <-SignExtend64( SRC1[223:192]) * SignExtend64( SRC2[223:192])
DEST[MAX_VL-1:256] <-0

VPMULDQ (VEX.128 encoded version)
DEST[63:0] <-SignExtend64( SRC1[31:0]) * SignExtend64( SRC2[31:0])
DEST[127:64] <-SignExtend64( SRC1[95:64]) * SignExtend64( SRC2[95:64])
DEST[MAX_VL-1:128] <-0

PMULDQ (128-bit Legacy SSE version)
DEST[63:0] <-SignExtend64( DEST[31:0]) * SignExtend64( SRC[31:0])
DEST[127:64] <-SignExtend64( DEST[95:64]) * SignExtend64( SRC[95:64])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VPMULDQ __m512i _mm512_mul_epi32(__m512i a, __m512i b);
VPMULDQ __m512i _mm512_mask_mul_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m512i _mm512_maskz_mul_epi32( __mmask8 k, __m512i a, __m512i b);
VPMULDQ __m256i _mm256_mask_mul_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m256i _mm256_mask_mul_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULDQ __m128i _mm_mask_mul_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULDQ __m128i _mm_mask_mul_epi32( __mmask8 k, __m128i a, __m128i b);
(V)PMULDQ __m128i _mm_mul_epi32( __m128i a, __m128i b);
VPMULDQ __m256i _mm256_mul_epi32( __m256i a, __m256i b);



SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PMULHRSW
description:
PMULHRSW - Packed Multiply High with Round and Scale
Opcode/                                             Op/   64/32 bit   CPUID         Description
Instruction                                         En    Mode        Feature
                                                          Support     Flag
0F 38 0B /r1                                        RM    V/V         SSSE3         Multiply 16-bit signed words, scale and round
PMULHRSW mm1, mm2/m64                                                               signed doublewords, pack high 16 bits to
                                                                                    mm1.
66 0F 38 0B /r                                      RM    V/V         SSSE3         Multiply 16-bit signed words, scale and round
PMULHRSW xmm1, xmm2/m128                                                            signed doublewords, pack high 16 bits to
                                                                                    xmm1.
VEX.NDS.128.66.0F38.WIG 0B /r                       RVM V/V           AVX           Multiply 16-bit signed words, scale and round
VPMULHRSW xmm1, xmm2, xmm3/m128                                                     signed doublewords, pack high 16 bits to
                                                                                    xmm1.
VEX.NDS.256.66.0F38.WIG 0B /r                       RVM V/V           AVX2          Multiply 16-bit signed words, scale and round
VPMULHRSW ymm1, ymm2, ymm3/m256                                                     signed doublewords, pack high 16 bits to
                                                                                    ymm1.
EVEX.NDS.128.66.0F38.WIG 0B /r                      FVM V/V           AVX512VL Multiply 16-bit signed words, scale and round
VPMULHRSW xmm1 {k1}{z}, xmm2, xmm3/m128                               AVX512BW signed doublewords, pack high 16 bits to
                                                                               xmm1 under writemask k1.
EVEX.NDS.256.66.0F38.WIG 0B /r                      FVM V/V           AVX512VL Multiply 16-bit signed words, scale and round
VPMULHRSW ymm1 {k1}{z}, ymm2, ymm3/m256                               AVX512BW signed doublewords, pack high 16 bits to
                                                                               ymm1 under writemask k1.
EVEX.NDS.512.66.0F38.WIG 0B /r                      FVM V/V           AVX512BW Multiply 16-bit signed words, scale and round
VPMULHRSW zmm1 {k1}{z}, zmm2, zmm3/m512                                        signed doublewords, pack high 16 bits to
                                                                               zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                   Operand 2                     Operand 3                       Operand 4
    RM           ModRM:reg (r, w)             ModRM:r/m (r)                       NA                              NA
   RVM           ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                        NA
   FVM           ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                        NA


Description
PMULHRSW multiplies vertically each signed 16-bit integer from the destination operand (first operand) with the
corresponding signed 16-bit integer of the source operand (second operand), producing intermediate, signed 32-
bit integers. Each intermediate 32-bit integer is truncated to the 18 most significant bits. Rounding is always
performed by adding 1 to the least significant bit of the 18-bit intermediate result. The final result is obtained by
selecting the 16 bits immediately to the right of the most significant bit of each 18-bit intermediate result and
packed to the destination operand.
When the source operand is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary or a
general-protection exception (#GP) will be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.
Legacy SSE version 64-bit operand: Both operands can be MMX registers. The second source operand is an MMX
register or a 64-bit memory location.





128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.

Operation
PMULHRSW (with 64-bit operands)
  temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
  temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
  temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;
  temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;
  DEST[15:0] = temp0[16:1];
  DEST[31:16] = temp1[16:1];
  DEST[47:32] = temp2[16:1];
  DEST[63:48] = temp3[16:1];

PMULHRSW (with 128-bit operand)
  temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
  temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
  temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;
  temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;
  temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;
  temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;
  temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;
  temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;
  DEST[15:0] = temp0[16:1];
  DEST[31:16] = temp1[16:1];
  DEST[47:32] = temp2[16:1];
  DEST[63:48] = temp3[16:1];
  DEST[79:64] = temp4[16:1];
  DEST[95:80] = temp5[16:1];
  DEST[111:96] = temp6[16:1];
  DEST[127:112] = temp7[16:1];

VPMULHRSW (VEX.128 encoded version)
temp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
DEST[15:0] <- temp0[16:1]
DEST[31:16] <- temp1[16:1]
DEST[47:32] <- temp2[16:1]



DEST[63:48] <- temp3[16:1]
DEST[79:64] <- temp4[16:1]
DEST[95:80] <- temp5[16:1]
DEST[111:96] <- temp6[16:1]
DEST[127:112] <- temp7[16:1]
DEST[VLMAX-1:128] <- 0

VPMULHRSW (VEX.256 encoded version)
temp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
temp8[31:0] <- INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1
temp9[31:0] <- INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1
temp10[31:0] <- INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1
temp11[31:0] <- INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1
temp12[31:0] <- INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1
temp13[31:0] <- INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1
temp14[31:0] <- INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1
temp15[31:0] <- INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1

DEST[15:0] <- temp0[16:1]
DEST[31:16] <- temp1[16:1]
DEST[47:32] <- temp2[16:1]
DEST[63:48] <- temp3[16:1]
DEST[79:64] <- temp4[16:1]
DEST[95:80] <- temp5[16:1]
DEST[111:96] <- temp6[16:1]
DEST[127:112] <- temp7[16:1]
DEST[143:128] <- temp8[16:1]
DEST[159:144] <- temp9[16:1]
DEST[175:160] <- temp10[16:1]
DEST[191:176] <- temp11[16:1]
DEST[207:192] <- temp12[16:1]
DEST[223:208] <- temp13[16:1]
DEST[239:224] <- temp14[16:1]
DEST[255:240] <- temp15[16:1]
DEST[MAX_VL-1:256] <- 0

VPMULHRSW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN
               temp[31:0] <- ((SRC1[i+15:i] * SRC2[i+15:i]) >>14) + 1
               DEST[i+15:i] <- tmp[16:1]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*



                  ELSE *zeroing-masking*               ; zeroing-masking
                      DEST[i+15:i] <- 0
          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPMULHRSW __m512i _mm512_mulhrs_epi16(__m512i a, __m512i b);
VPMULHRSW __m512i _mm512_mask_mulhrs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m512i _mm512_maskz_mulhrs_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHRSW __m256i _mm256_mask_mulhrs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m256i _mm256_maskz_mulhrs_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHRSW __m128i _mm_mask_mulhrs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHRSW __m128i _mm_maskz_mulhrs_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHRSW: __m64 _mm_mulhrs_pi16 (__m64 a, __m64 b)
(V)PMULHRSW: __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
VPMULHRSW:__m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMULHUW
description:
PMULHUW-Multiply Packed Unsigned Integers and Store High Result
Opcode/                                             Op/   64/32 bit    CPUID         Description
Instruction                                         En    Mode         Feature
                                                          Support      Flag
0F E4 /r1                                           RM     V/V         SSE           Multiply the packed unsigned word integers in
PMULHUW mm1, mm2/m64                                                                 mm1 register and mm2/m64, and store the
                                                                                     high 16 bits of the results in mm1.
66 0F E4 /r                                         RM    V/V          SSE2          Multiply the packed unsigned word integers in
PMULHUW xmm1, xmm2/m128                                                              xmm1 and xmm2/m128, and store the high
                                                                                     16 bits of the results in xmm1.
VEX.NDS.128.66.0F.WIG E4 /r                         RVM V/V            AVX           Multiply the packed unsigned word integers in
VPMULHUW xmm1, xmm2, xmm3/m128                                                       xmm2 and xmm3/m128, and store the high
                                                                                     16 bits of the results in xmm1.
VEX.NDS.256.66.0F.WIG E4 /r                         RVM V/V            AVX2          Multiply the packed unsigned word integers in
VPMULHUW ymm1, ymm2, ymm3/m256                                                       ymm2 and ymm3/m256, and store the high
                                                                                     16 bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG E4 /r                        FVM V/V            AVX512VL Multiply the packed unsigned word integers in
VPMULHUW xmm1 {k1}{z}, xmm2, xmm3/m128                                 AVX512BW xmm2 and xmm3/m128, and store the high
                                                                                16 bits of the results in xmm1 under
                                                                                writemask k1.
EVEX.NDS.256.66.0F.WIG E4 /r                        FVM V/V            AVX512VL Multiply the packed unsigned word integers in
VPMULHUW ymm1 {k1}{z}, ymm2, ymm3/m256                                 AVX512BW ymm2 and ymm3/m256, and store the high
                                                                                16 bits of the results in ymm1 under
                                                                                writemask k1.
EVEX.NDS.512.66.0F.WIG E4 /r                        FVM V/V            AVX512BW Multiply the packed unsigned word integers in
VPMULHUW zmm1 {k1}{z}, zmm2, zmm3/m512                                          zmm2 and zmm3/m512, and store the high 16
                                                                                bits of the results in zmm1 under writemask
                                                                                k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                     Operand 2                      Operand 3                     Operand 4
    RM           ModRM:reg (r, w)               ModRM:r/m (r)                       NA                             NA
   RVM            ModRM:reg (w)                  VEX.vvvv (r)                 ModRM:r/m (r)                        NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                        NA


Description
Performs a SIMD unsigned multiply of the packed unsigned word integers in the destination operand (first operand)
and the source operand (second operand), and stores the high 16 bits of each 32-bit intermediate results in the
destination operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.



VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.




                                          SRC          X3         X2       X1        X0


                                          DEST          Y3        Y2        Y1        Y0


                          TEMP      Z3 = X3 * Y3        Z2 = X2 * Y2        Z1 = X1 * Y1       Z0 = X0 * Y0


                                          DEST       Z3[31:16] Z2[31:16] Z1[31:16] Z0[31:16]


                   Figure 4-12. PMULHUW and PMULHW Instruction Operation Using 64-bit Operands


Operation
PMULHUW (with 64-bit operands)
  TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Unsigned multiplication *)
  TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
  TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
  TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
  DEST[15:0] <-    TEMP0[31:16];
  DEST[31:16] <- TEMP1[31:16];
  DEST[47:32] <- TEMP2[31:16];
  DEST[63:48] <- TEMP3[31:16];

PMULHUW (with 128-bit operands)
  TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Unsigned multiplication *)
  TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
  TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
  TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
  TEMP4[31:0] <- DEST[79:64] * SRC[79:64];
  TEMP5[31:0] <- DEST[95:80] * SRC[95:80];
  TEMP6[31:0] <- DEST[111:96] * SRC[111:96];
  TEMP7[31:0] <- DEST[127:112] * SRC[127:112];
  DEST[15:0] <-    TEMP0[31:16];
  DEST[31:16] <- TEMP1[31:16];
  DEST[47:32] <- TEMP2[31:16];
  DEST[63:48] <- TEMP3[31:16];
  DEST[79:64] <- TEMP4[31:16];
  DEST[95:80] <- TEMP5[31:16];
  DEST[111:96] <- TEMP6[31:16];
  DEST[127:112] <- TEMP7[31:16];

VPMULHUW (VEX.128 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]



TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[VLMAX-1:128] <- 0

PMULHUW (VEX.256 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[143:128] <- TEMP8[31:16]
DEST[159:144] <- TEMP9[31:16]
DEST[175:160] <- TEMP10[31:16]
DEST[191:176] <- TEMP11[31:16]
DEST[207:192] <- TEMP12[31:16]
DEST[223:208] <- TEMP13[31:16]
DEST[239:224] <- TEMP14[31:16]
DEST[255:240] <- TEMP15[31:16]
DEST[MAX_VL-1:256] <- 0

PMULHUW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)



FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN
             temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]
             DEST[i+15:i] <- tmp[31:16]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMULHUW __m512i _mm512_mulhi_epu16(__m512i a, __m512i b);
VPMULHUW __m512i _mm512_mask_mulhi_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m512i _mm512_maskz_mulhi_epu16( __mmask32 k, __m512i a, __m512i b);
VPMULHUW __m256i _mm256_mask_mulhi_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m256i _mm256_maskz_mulhi_epu16( __mmask16 k, __m256i a, __m256i b);
VPMULHUW __m128i _mm_mask_mulhi_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHUW __m128i _mm_maskz_mulhi_epu16( __mmask8 k, __m128i a, __m128i b);
PMULHUW:__m64 _mm_mulhi_pu16(__m64 a, __m64 b)
(V)PMULHUW:__m128i _mm_mulhi_epu16 ( __m128i a, __m128i b)
VPMULHUW:__m256i _mm256_mulhi_epu16 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMULHW
description:
PMULHW-Multiply Packed Signed Integers and Store High Result
Opcode/                                          Op/   64/32 bit   CPUID          Description
Instruction                                      En    Mode        Feature
                                                       Support     Flag
0F E5 /r1                                        RM    V/V         MMX            Multiply the packed signed word integers in mm1
PMULHW mm, mm/m64                                                                 register and mm2/m64, and store the high 16
                                                                                  bits of the results in mm1.
66 0F E5 /r                                      RM    V/V         SSE2           Multiply the packed signed word integers in
PMULHW xmm1, xmm2/m128                                                            xmm1 and xmm2/m128, and store the high 16
                                                                                  bits of the results in xmm1.
VEX.NDS.128.66.0F.WIG E5 /r                      RVM V/V           AVX            Multiply the packed signed word integers in
VPMULHW xmm1, xmm2, xmm3/m128                                                     xmm2 and xmm3/m128, and store the high 16
                                                                                  bits of the results in xmm1.
VEX.NDS.256.66.0F.WIG E5 /r                      RVM V/V           AVX2           Multiply the packed signed word integers in
VPMULHW ymm1, ymm2, ymm3/m256                                                     ymm2 and ymm3/m256, and store the high 16
                                                                                  bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG E5 /r                     FVM V/V           AVX512VL       Multiply the packed signed word integers in
VPMULHW xmm1 {k1}{z}, xmm2, xmm3/m128                              AVX512BW       xmm2 and xmm3/m128, and store the high 16
                                                                                  bits of the results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG E5 /r                     FVM V/V           AVX512VL       Multiply the packed signed word integers in
VPMULHW ymm1 {k1}{z}, ymm2, ymm3/m256                              AVX512BW       ymm2 and ymm3/m256, and store the high 16
                                                                                  bits of the results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG E5 /r                     FVM V/V           AVX512BW       Multiply the packed signed word integers in
VPMULHW zmm1 {k1}{z}, zmm2, zmm3/m512                                             zmm2 and zmm3/m512, and store the high 16
                                                                                  bits of the results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                     Operand 3                       Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                       NA                              NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                         NA
   FVM            ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                         NA


Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the high 16 bits of each intermediate 32-bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)
n 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.



VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is a ZMM/YMM/XMM
register conditionally updated with writemask k1.

Operation
PMULHW (with 64-bit operands)
  TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
  TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
  TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
  TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
  DEST[15:0] <-     TEMP0[31:16];
  DEST[31:16] <- TEMP1[31:16];
  DEST[47:32] <- TEMP2[31:16];
  DEST[63:48] <- TEMP3[31:16];

PMULHW (with 128-bit operands)
  TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
  TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
  TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
  TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
  TEMP4[31:0] <- DEST[79:64] * SRC[79:64];
  TEMP5[31:0] <- DEST[95:80] * SRC[95:80];
  TEMP6[31:0] <- DEST[111:96] * SRC[111:96];
  TEMP7[31:0] <- DEST[127:112] * SRC[127:112];
  DEST[15:0] <-    TEMP0[31:16];
  DEST[31:16] <- TEMP1[31:16];
  DEST[47:32] <- TEMP2[31:16];
  DEST[63:48] <- TEMP3[31:16];
  DEST[79:64] <- TEMP4[31:16];
  DEST[95:80] <- TEMP5[31:16];
  DEST[111:96] <- TEMP6[31:16];
  DEST[127:112] <- TEMP7[31:16];

VPMULHW (VEX.128 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[VLMAX-1:128] <- 0




PMULHW (VEX.256 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[143:128] <- TEMP8[31:16]
DEST[159:144] <- TEMP9[31:16]
DEST[175:160] <- TEMP10[31:16]
DEST[191:176] <- TEMP11[31:16]
DEST[207:192] <- TEMP12[31:16]
DEST[223:208] <- TEMP13[31:16]
DEST[239:224] <- TEMP14[31:16]
DEST[255:240] <- TEMP15[31:16]
DEST[VLMAX-1:256] <- 0

PMULHW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN
               temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]
               DEST[i+15:i] <- tmp[31:16]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPMULHW __m512i _mm512_mulhi_epi16(__m512i a, __m512i b);
VPMULHW __m512i _mm512_mask_mulhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULHW __m512i _mm512_maskz_mulhi_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULHW __m256i _mm256_mask_mulhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULHW __m256i _mm256_maskz_mulhi_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULHW __m128i _mm_mask_mulhi_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULHW __m128i _mm_maskz_mulhi_epi16( __mmask8 k, __m128i a, __m128i b);
PMULHW:__m64 _mm_mulhi_pi16 (__m64 m1, __m64 m2)
(V)PMULHW:__m128i _mm_mulhi_epi16 ( __m128i a, __m128i b)
VPMULHW:__m256i _mm256_mulhi_epi16 ( __m256i a, __m256i b)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMULLD
description:
PMULLD/PMULLQ-Multiply Packed Integers and Store Low Result
 Opcode/                          Op/    64/32        CPUID        Description
 Instruction                      En     bit Mode     Feature
                                         Support      Flag
 66 0F 38 40 /r                   RM     V/V          SSE4_1       Multiply the packed dword signed integers in xmm1 and
 PMULLD xmm1, xmm2/m128                                            xmm2/m128 and store the low 32 bits of each product in
                                                                   xmm1.
 VEX.NDS.128.66.0F38.WIG 40 /r    RVM    V/V          AVX          Multiply the packed dword signed integers in xmm2 and
 VPMULLD xmm1, xmm2,                                               xmm3/m128 and store the low 32 bits of each product in
 xmm3/m128                                                         xmm1.
 VEX.NDS.256.66.0F38.WIG 40 /r    RVM    V/V          AVX2         Multiply the packed dword signed integers in ymm2 and
 VPMULLD ymm1, ymm2,                                               ymm3/m256 and store the low 32 bits of each product in
 ymm3/m256                                                         ymm1.
 EVEX.NDS.128.66.0F38.W0 40 /r    FV     V/V          AVX512VL     Multiply the packed dword signed integers in xmm2 and
 VPMULLD xmm1 {k1}{z}, xmm2,                          AVX512F      xmm3/m128/m32bcst and store the low 32 bits of each
 xmm3/m128/m32bcst                                                 product in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W0 40 /r    FV     V/V          AVX512VL     Multiply the packed dword signed integers in ymm2 and
 VPMULLD ymm1 {k1}{z}, ymm2,                          AVX512F      ymm3/m256/m32bcst and store the low 32 bits of each
 ymm3/m256/m32bcst                                                 product in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W0 40 /r    FV     V/V          AVX512F      Multiply the packed dword signed integers in zmm2 and
 VPMULLD zmm1 {k1}{z}, zmm2,                                       zmm3/m512/m32bcst and store the low 32 bits of each
 zmm3/m512/m32bcst                                                 product in zmm1 under writemask k1.
 EVEX.NDS.128.66.0F38.W1 40 /r    FV     V/V          AVX512VL     Multiply the packed qword signed integers in xmm2 and
 VPMULLQ xmm1 {k1}{z}, xmm2,                          AVX512DQ     xmm3/m128/m64bcst and store the low 64 bits of each
 xmm3/m128/m64bcst                                                 product in xmm1 under writemask k1.
 EVEX.NDS.256.66.0F38.W1 40 /r    FV     V/V          AVX512VL     Multiply the packed qword signed integers in ymm2 and
 VPMULLQ ymm1 {k1}{z}, ymm2,                          AVX512DQ     ymm3/m256/m64bcst and store the low 64 bits of each
 ymm3/m256/m64bcst                                                 product in ymm1 under writemask k1.
 EVEX.NDS.512.66.0F38.W1 40 /r    FV     V/V          AVX512DQ     Multiply the packed qword signed integers in zmm2 and
 VPMULLQ zmm1 {k1}{z}, zmm2,                                       zmm3/m512/m64bcst and store the low 64 bits of each
 zmm3/m512/m64bcst                                                 product in zmm1 under writemask k1.



                                           Instruction Operand Encoding
       Op/En             Operand 1                  Operand 2                    Operand 3                 Operand 4
         RM           ModRM:reg (r, w)          ModRM:r/m (r)                       NA                        NA
        RVM            ModRM:reg (w)                VEX.vvvv (r)            ModRM:r/m (r)                     NA
         FV            ModRM:reg (w)            EVEX.vvvv (r)               ModRM:r/m (r)                     NA

Description
Performs a SIMD signed multiply of the packed signed dword/qword integers from each element of the first source
operand with the corresponding element in the second source operand. The low 32/64 bits of each 64/128-bit
intermediate results are stored to the destination operand.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register; The second source operand is a YMM register
or 256-bit memory location. Bits (MAX_VL-1:256) of the corresponding destination ZMM register are zeroed.





EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is conditionally updated based on writemask k1.

Operation
VPMULLQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN Temp[127:0] <- SRC1[i+63:i] * SRC2[63:0]
                    ELSE Temp[127:0] <- SRC1[i+63:i] * SRC2[i+63:i]
               FI;
               DEST[i+63:i] <- Temp[63:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPMULLD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN Temp[63:0] <- SRC1[i+31:i] * SRC2[31:0]
                    ELSE Temp[63:0] <- SRC1[i+31:i] * SRC2[i+31:i]
               FI;
               DEST[i+31:i] <- Temp[31:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPMULLD (VEX.256 encoded version)
Temp0[63:0] <- SRC1[31:0] * SRC2[31:0]
Temp1[63:0] <- SRC1[63:32] * SRC2[63:32]
Temp2[63:0] <- SRC1[95:64] * SRC2[95:64]
Temp3[63:0] <- SRC1[127:96] * SRC2[127:96]
Temp4[63:0] <- SRC1[159:128] * SRC2[159:128]
Temp5[63:0] <- SRC1[191:160] * SRC2[191:160]
Temp6[63:0] <- SRC1[223:192] * SRC2[223:192]
Temp7[63:0] <- SRC1[255:224] * SRC2[255:224]

DEST[31:0] <- Temp0[31:0]
DEST[63:32] <- Temp1[31:0]
DEST[95:64] <- Temp2[31:0]
DEST[127:96] <- Temp3[31:0]
DEST[159:128] <- Temp4[31:0]
DEST[191:160] <- Temp5[31:0]
DEST[223:192] <- Temp6[31:0]
DEST[255:224] <- Temp7[31:0]
DEST[MAX_VL-1:256] <- 0

VPMULLD (VEX.128 encoded version)
Temp0[63:0] <- SRC1[31:0] * SRC2[31:0]
Temp1[63:0] <- SRC1[63:32] * SRC2[63:32]
Temp2[63:0] <- SRC1[95:64] * SRC2[95:64]
Temp3[63:0] <- SRC1[127:96] * SRC2[127:96]
DEST[31:0] <- Temp0[31:0]
DEST[63:32] <- Temp1[31:0]
DEST[95:64] <- Temp2[31:0]
DEST[127:96] <- Temp3[31:0]
DEST[MAX_VL-1:128] <- 0

PMULLD (128-bit Legacy SSE version)
Temp0[63:0] <- DEST[31:0] * SRC[31:0]
Temp1[63:0] <- DEST[63:32] * SRC[63:32]
Temp2[63:0] <- DEST[95:64] * SRC[95:64]
Temp3[63:0] <- DEST[127:96] * SRC[127:96]
DEST[31:0] <- Temp0[31:0]
DEST[63:32] <- Temp1[31:0]
DEST[95:64] <- Temp2[31:0]
DEST[127:96] <- Temp3[31:0]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VPMULLD __m512i _mm512_mullo_epi32(__m512i a, __m512i b);
VPMULLD __m512i _mm512_mask_mullo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPMULLD __m512i _mm512_maskz_mullo_epi32( __mmask16 k, __m512i a, __m512i b);
VPMULLD __m256i _mm256_mask_mullo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLD __m256i _mm256_maskz_mullo_epi32( __mmask8 k, __m256i a, __m256i b);
VPMULLD __m128i _mm_mask_mullo_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLD __m128i _mm_maskz_mullo_epi32( __mmask8 k, __m128i a, __m128i b);
VPMULLD __m256i _mm256_mullo_epi32(__m256i a, __m256i b);
PMULLD __m128i _mm_mullo_epi32(__m128i a, __m128i b);
VPMULLQ __m512i _mm512_mullo_epi64(__m512i a, __m512i b);
VPMULLQ __m512i _mm512_mask_mullo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);



VPMULLQ __m512i _mm512_maskz_mullo_epi64( __mmask8 k, __m512i a, __m512i b);
VPMULLQ __m256i _mm256_mullo_epi64(__m256i a, __m256i b);
VPMULLQ __m256i _mm256_mask_mullo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m256i _mm256_maskz_mullo_epi64( __mmask8 k, __m256i a, __m256i b);
VPMULLQ __m128i _mm_mullo_epi64(__m128i a, __m128i b);
VPMULLQ __m128i _mm_mask_mullo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLQ __m128i _mm_maskz_mullo_epi64( __mmask8 k, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PMULLW
description:
PMULLW-Multiply Packed Signed Integers and Store Low Result
Opcode/                                            Op/   64/32 bit   CPUID          Description
Instruction                                        En    Mode        Feature
                                                         Support     Flag
0F D5 /r1                                          RM    V/V         MMX            Multiply the packed signed word integers in
PMULLW mm, mm/m64                                                                   mm1 register and mm2/m64, and store the low
                                                                                    16 bits of the results in mm1.
66 0F D5 /r                                        RM    V/V         SSE2           Multiply the packed signed word integers in
PMULLW xmm1, xmm2/m128                                                              xmm1 and xmm2/m128, and store the low 16
                                                                                    bits of the results in xmm1.
VEX.NDS.128.66.0F.WIG D5 /r                        RVM V/V           AVX            Multiply the packed dword signed integers in
VPMULLW xmm1, xmm2, xmm3/m128                                                       xmm2 and xmm3/m128 and store the low 32
                                                                                    bits of each product in xmm1.
VEX.NDS.256.66.0F.WIG D5 /r                        RVM V/V           AVX2           Multiply the packed signed word integers in
VPMULLW ymm1, ymm2, ymm3/m256                                                       ymm2 and ymm3/m256, and store the low 16
                                                                                    bits of the results in ymm1.
EVEX.NDS.128.66.0F.WIG D5 /r                       FVM V/V           AVX512VL Multiply the packed signed word integers in
VPMULLW xmm1 {k1}{z}, xmm2, xmm3/m128                                AVX512BW xmm2 and xmm3/m128, and store the low 16
                                                                              bits of the results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.WIG D5 /r                       FVM V/V           AVX512VL Multiply the packed signed word integers in
VPMULLW ymm1 {k1}{z}, ymm2, ymm3/m256                                AVX512BW ymm2 and ymm3/m256, and store the low 16
                                                                              bits of the results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.WIG D5 /r                       FVM V/V           AVX512BW Multiply the packed signed word integers in
VPMULLW zmm1 {k1}{z}, zmm2, zmm3/m512                                         zmm2 and zmm3/m512, and store the low 16
                                                                              bits of the results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                    Operand 2                      Operand 3                        Operand 4
   RM           ModRM:reg (r, w)              ModRM:r/m (r)                        NA                              NA
   RVM           ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                         NA
   FVM           ModRM:reg (w)                EVEX.vvvv (r)                  ModRM:r/m (r)                         NA


Description
Performs a SIMD signed multiply of the packed signed word integers in the destination operand (first operand) and
the source operand (second operand), and stores the low 16 bits of each intermediate 32-bit result in the destina-
tion operand. (Figure 4-12 shows this operation when using 64-bit operands.)
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise the instruction will #UD.



VEX.256 encoded version: The second source operand can be an YMM register or a 256-bit memory location. The
first source and destination operands are YMM registers.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand is a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination operand is conditionally updated
based on writemask k1.



                                          SRC           X3        X2         X1         X0


                                          DEST           Y3        Y2         Y1         Y0


                          TEMP       Z3 = X3 * Y3       Z2 = X2 * Y2          Z1 = X1 * Y1        Z0 = X0 * Y0


                                          DEST        Z3[15:0]   Z2[15:0]   Z1[15:0]   Z0[15:0]


                             Figure 4-13. PMULLU Instruction Operation Using 64-bit Operands


Operation
PMULLW (with 64-bit operands)
  TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
  TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
  TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
  TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
  DEST[15:0] <-     TEMP0[15:0];
  DEST[31:16] <- TEMP1[15:0];
  DEST[47:32] <- TEMP2[15:0];
  DEST[63:48] <- TEMP3[15:0];

PMULLW (with 128-bit operands)
   TEMP0[31:0] <- DEST[15:0] * SRC[15:0]; (* Signed multiplication *)
   TEMP1[31:0] <- DEST[31:16] * SRC[31:16];
   TEMP2[31:0] <- DEST[47:32] * SRC[47:32];
   TEMP3[31:0] <- DEST[63:48] * SRC[63:48];
   TEMP4[31:0] <- DEST[79:64] * SRC[79:64];
   TEMP5[31:0] <- DEST[95:80] * SRC[95:80];
   TEMP6[31:0] <- DEST[111:96] * SRC[111:96];
   TEMP7[31:0] <- DEST[127:112] * SRC[127:112];
   DEST[15:0] <-    TEMP0[15:0];
   DEST[31:16] <- TEMP1[15:0];
   DEST[47:32] <- TEMP2[15:0];
   DEST[63:48] <- TEMP3[15:0];
   DEST[79:64] <- TEMP4[15:0];
   DEST[95:80] <- TEMP5[15:0];
   DEST[111:96] <- TEMP6[15:0];
   DEST[127:112] <- TEMP7[15:0];
DEST[VLMAX-1:256] <- 0





VPMULLW (VEX.128 encoded version)
Temp0[31:0] <- SRC1[15:0] * SRC2[15:0]
Temp1[31:0] <- SRC1[31:16] * SRC2[31:16]
Temp2[31:0] <- SRC1[47:32] * SRC2[47:32]
Temp3[31:0] <- SRC1[63:48] * SRC2[63:48]
Temp4[31:0] <- SRC1[79:64] * SRC2[79:64]
Temp5[31:0] <- SRC1[95:80] * SRC2[95:80]
Temp6[31:0] <- SRC1[111:96] * SRC2[111:96]
Temp7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- Temp0[15:0]
DEST[31:16] <- Temp1[15:0]
DEST[47:32] <- Temp2[15:0]
DEST[63:48] <- Temp3[15:0]
DEST[79:64] <- Temp4[15:0]
DEST[95:80] <- Temp5[15:0]
DEST[111:96] <- Temp6[15:0]
DEST[127:112] <- Temp7[15:0]
DEST[VLMAX-1:128] <- 0

PMULLW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN
               temp[31:0] <- SRC1[i+15:i] * SRC2[i+15:i]
               DEST[i+15:i] <- temp[15:0]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMULLW __m512i _mm512_mullo_epi16(__m512i a, __m512i b);
VPMULLW __m512i _mm512_mask_mullo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPMULLW __m512i _mm512_maskz_mullo_epi16( __mmask32 k, __m512i a, __m512i b);
VPMULLW __m256i _mm256_mask_mullo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPMULLW __m256i _mm256_maskz_mullo_epi16( __mmask16 k, __m256i a, __m256i b);
VPMULLW __m128i _mm_mask_mullo_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULLW __m128i _mm_maskz_mullo_epi16( __mmask8 k, __m128i a, __m128i b);
PMULLW: __m64 _mm_mullo_pi16(__m64 m1, __m64 m2)
(V)PMULLW: __m128i _mm_mullo_epi16 ( __m128i a, __m128i b)
VPMULLW:__m256i _mm256_mullo_epi16 ( __m256i a, __m256i b);

Flags Affected
None.





SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PMULUDQ
description:
PMULUDQ-Multiply Packed Unsigned Doubleword Integers
Opcode/                                          Op/   64/32 bit   CPUID          Description
Instruction                                      En    Mode        Feature
                                                       Support     Flag
0F F4 /r1                                        RM    V/V         SSE2           Multiply unsigned doubleword integer in mm1 by
PMULUDQ mm1, mm2/m64                                                              unsigned doubleword integer in mm2/m64, and
                                                                                  store the quadword result in mm1.
66 0F F4 /r                                      RM    V/V         SSE2           Multiply packed unsigned doubleword integers in
PMULUDQ xmm1, xmm2/m128                                                           xmm1 by packed unsigned doubleword integers
                                                                                  in xmm2/m128, and store the quadword results
                                                                                  in xmm1.
VEX.NDS.128.66.0F.WIG F4 /r                      RVM V/V           AVX            Multiply packed unsigned doubleword integers in
VPMULUDQ xmm1, xmm2, xmm3/m128                                                    xmm2 by packed unsigned doubleword integers
                                                                                  in xmm3/m128, and store the quadword results
                                                                                  in xmm1.
VEX.NDS.256.66.0F.WIG F4 /r                      RVM V/V           AVX2           Multiply packed unsigned doubleword integers in
VPMULUDQ ymm1, ymm2, ymm3/m256                                                    ymm2 by packed unsigned doubleword integers
                                                                                  in ymm3/m256, and store the quadword results
                                                                                  in ymm1.
EVEX.NDS.128.66.0F.W1 F4 /r                      FV    V/V         AVX512VL       Multiply packed unsigned doubleword integers in
VPMULUDQ xmm1 {k1}{z}, xmm2,                                       AVX512F        xmm2 by packed unsigned doubleword integers
xmm3/m128/m64bcst                                                                 in xmm3/m128/m64bcst, and store the
                                                                                  quadword results in xmm1 under writemask k1.
EVEX.NDS.256.66.0F.W1 F4 /r                      FV    V/V         AVX512VL       Multiply packed unsigned doubleword integers in
VPMULUDQ ymm1 {k1}{z}, ymm2,                                       AVX512F        ymm2 by packed unsigned doubleword integers
ymm3/m256/m64bcst                                                                 in ymm3/m256/m64bcst, and store the
                                                                                  quadword results in ymm1 under writemask k1.
EVEX.NDS.512.66.0F.W1 F4 /r                      FV    V/V         AVX512F        Multiply packed unsigned doubleword integers in
VPMULUDQ zmm1 {k1}{z}, zmm2,                                                      zmm2 by packed unsigned doubleword integers
zmm3/m512/m64bcst                                                                 in zmm3/m512/m64bcst, and store the
                                                                                  quadword results in zmm1 under writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                    Operand 2                     Operand 3                      Operand 4
    RM          ModRM:reg (r, w)              ModRM:r/m (r)                       NA                             NA
   RVM           ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                       NA
    FV           ModRM:reg (w)                EVEX.vvvv (r)                  ModRM:r/m (r)                       NA


Description
Multiplies the first operand (destination operand) by the second operand (source operand) and stores the result in
the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be an unsigned doubleword integer stored in the low
doubleword of an MMX technology register or a 64-bit memory location. The destination operand can be an
unsigned doubleword integer stored in the low doubleword an MMX technology register. The result is an unsigned



quadword integer stored in the destination an MMX technology register. When a quadword result is too large to be
represented in 64 bits (overflow), the result is wrapped around and the low 64 bits are written to the destination
element (that is, the carry is ignored).
For 64-bit memory operands, 64 bits are fetched from memory, but only the low doubleword is used in the compu-
tation.
128-bit Legacy SSE version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX-
1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is two packed unsigned doubleword integers stored in the
first (low) and third doublewords of an XMM register or a 128-bit memory location. For 128-bit memory operands,
128 bits are fetched from memory, but only the first and third doublewords are used in the computation. The first
source operand is two packed unsigned doubleword integers stored in the first and third doublewords of an XMM
register. The destination contains two packed unsigned quadword integers stored in an XMM register. Bits (VLMAX-
1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand is four packed unsigned doubleword integers stored in the
first (low), third, fifth and seventh doublewords of a YMM register or a 256-bit memory location. For 256-bit
memory operands, 256 bits are fetched from memory, but only the first, third, fifth and seventh doublewords are
used in the computation. The first source operand is four packed unsigned doubleword integers stored in the first,
third, fifth and seventh doublewords of an YMM register. The destination contains four packed unaligned quadword
integers stored in an YMM register.
EVEX encoded version: The input unsigned doubleword integers are taken from the even-numbered elements of
the source operands. The first source operand is a ZMM/YMM/XMM registers. The second source operand can be an
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-
bit memory location. The destination is a ZMM/YMM/XMM register, and updated according to the writemask at 64-
bit granularity.

Operation
PMULUDQ (with 64-Bit operands)
  DEST[63:0] <- DEST[31:0] * SRC[31:0];

PMULUDQ (with 128-Bit operands)
  DEST[63:0] <- DEST[31:0] * SRC[31:0];
  DEST[127:64] <- DEST[95:64] * SRC[95:64];

VPMULUDQ (VEX.128 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64]
DEST[VLMAX-1:128] <- 0

VPMULUDQ (VEX.256 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64
DEST[191:128] <- SRC1[159:128] * SRC2[159:128]
DEST[255:192] <- SRC1[223:192] * SRC2[223:192]
DEST[VLMAX-1:256] <- 0

VPMULUDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)


                 THEN DEST[i+63:i] <- ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[31:0] )
                 ELSE DEST[i+63:i] <- ZeroExtend64( SRC1[i+31:i]) * ZeroExtend64( SRC2[i+31:i] )
            FI;
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+63:i] remains unchanged*
                 ELSE *zeroing-masking*              ; zeroing-masking
                     DEST[i+63:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPMULUDQ __m512i _mm512_mul_epu32(__m512i a, __m512i b);
VPMULUDQ __m512i _mm512_mask_mul_epu32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m512i _mm512_maskz_mul_epu32( __mmask8 k, __m512i a, __m512i b);
VPMULUDQ __m256i _mm256_mask_mul_epu32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m256i _mm256_maskz_mul_epu32( __mmask8 k, __m256i a, __m256i b);
VPMULUDQ __m128i _mm_mask_mul_epu32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPMULUDQ __m128i _mm_maskz_mul_epu32( __mmask8 k, __m128i a, __m128i b);
PMULUDQ:__m64 _mm_mul_su32 (__m64 a, __m64 b)
(V)PMULUDQ:__m128i _mm_mul_epu32 ( __m128i a, __m128i b)
VPMULUDQ:__m256i _mm256_mul_epu32( __m256i a, __m256i b);

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: POP
description:
POP-Pop a Value from the Stack
 Opcode                    Instruction           Op/   64-Bit    Compat/ Description
                                                 En    Mode      Leg Mode
 8F /0                     POP r/m16             M     Valid     Valid       Pop top of stack into m16; increment stack
                                                                             pointer.
 8F /0                     POP r/m32             M     N.E.      Valid       Pop top of stack into m32; increment stack
                                                                             pointer.
 8F /0                     POP r/m64             M     Valid     N.E.        Pop top of stack into m64; increment stack
                                                                             pointer. Cannot encode 32-bit operand size.
 58+ rw                    POP r16               O     Valid     Valid       Pop top of stack into r16; increment stack
                                                                             pointer.
 58+ rd                    POP r32               O     N.E.      Valid       Pop top of stack into r32; increment stack
                                                                             pointer.
 58+ rd                    POP r64               O     Valid     N.E.        Pop top of stack into r64; increment stack
                                                                             pointer. Cannot encode 32-bit operand size.
 1F                        POP DS                NP    Invalid   Valid       Pop top of stack into DS; increment stack
                                                                             pointer.
 07                        POP ES                NP    Invalid   Valid       Pop top of stack into ES; increment stack
                                                                             pointer.
 17                        POP SS                NP    Invalid   Valid       Pop top of stack into SS; increment stack
                                                                             pointer.
 0F A1                     POP FS                NP    Valid     Valid       Pop top of stack into FS; increment stack
                                                                             pointer by 16 bits.
 0F A1                     POP FS                NP    N.E.      Valid       Pop top of stack into FS; increment stack
                                                                             pointer by 32 bits.
 0F A1                     POP FS                NP    Valid     N.E.        Pop top of stack into FS; increment stack
                                                                             pointer by 64 bits.

 0F A9                     POP GS                NP    Valid     Valid       Pop top of stack into GS; increment stack
                                                                             pointer by 16 bits.
 0F A9                     POP GS                NP    N.E.      Valid       Pop top of stack into GS; increment stack
                                                                             pointer by 32 bits.
 0F A9                     POP GS                NP    Valid     N.E.        Pop top of stack into GS; increment stack
                                                                             pointer by 64 bits.



                                            Instruction Operand Encoding
    Op/En             Operand 1               Operand 2                  Operand 3                     Operand 4
      M             ModRM:r/m (w)                NA                         NA                             NA
      O            opcode + rd (w)               NA                         NA                             NA
      NP                  NA                     NA                         NA                             NA


Description
Loads the value from the top of the stack to the location specified with the destination operand (or explicit opcode)
and then increments the stack pointer. The destination operand can be a general-purpose register, memory loca-
tion, or segment register.
Address and operand sizes are determined and used as follows:
.     Address size. The D flag in the current code-segment descriptor determines the default address size; it may be
      overridden by an instruction prefix (67H).



    The address size is used only when writing to a destination operand in memory.
.   Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may
    be overridden by instruction prefixes (66H or REX.W).
    The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is incremented (2, 4
    or 8).
.   Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the
    size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.
    The stack-address size determines the width of the stack pointer when reading from the stack in memory and
    when incrementing the stack pointer. (As stated above, the amount by which the stack pointer is incremented
    is determined by the operand size.)
If the destination operand is one of the segment registers DS, ES, FS, GS, or SS, the value loaded into the register
must be a valid segment selector. In protected mode, popping a segment selector into a segment register automat-
ically causes the descriptor information associated with that segment selector to be loaded into the hidden
(shadow) part of the segment register and causes the selector and the descriptor information to be validated (see
the "Operation" section below).
A NULL value (0000-0003) may be popped into the DS, ES, FS, or GS register without causing a general protection
fault. However, any subsequent attempt to reference a segment whose corresponding segment register is loaded
with a NULL value causes a general protection exception (#GP). In this situation, no memory reference occurs and
the saved value of the segment register is NULL.
The POP instruction cannot pop a value into the CS register. To load the CS register from the stack, use the RET
instruction.
If the ESP register is used as a base register for addressing a destination operand in memory, the POP instruction
computes the effective address of the operand after it increments the ESP register. For the case of a 16-bit stack
where ESP wraps to 0H as a result of the POP instruction, the resulting location of the memory write is processor-
family-specific.
The POP ESP instruction increments the stack pointer (ESP) before data at the old top of stack is written into the
destination.
A POP SS instruction inhibits all interrupts, including the NMI interrupt, until after execution of the next instruction.
This action allows sequential execution of POP SS and MOV ESP, EBP instructions without the danger of having an
invalid stack during an interrupt1. However, use of the LSS instruction is the preferred method of loading the SS
and ESP registers.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). When in
64-bit mode, POPs using 32-bit operands are not encodable and POPs to DS, ES, SS are not valid. See the summary
chart at the beginning of this section for encoding data and limits.

Operation
IF StackAddrSize = 32
    THEN
        IF OperandSize = 32
             THEN
                 DEST <- SS:ESP; (* Copy a doubleword *)
                 ESP <- ESP + 4;
             ELSE (* OperandSize = 16*)
                 DEST <- SS:ESP; (* Copy a word *)

1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a POP SS instruction, the breakpoint
   may not be triggered. However, in a sequence of instructions that POP the SS register, only the first instruction in the sequence is
   guaranteed to delay an interrupt.
    In the following sequence, interrupts may be recognized before POP ESP executes:
    POP SS
    POP SS
    POP ESP



                    ESP <- ESP + 2;
          FI;
      ELSE IF StackAddrSize = 64
          THEN
               IF OperandSize = 64
                    THEN
                        DEST <- SS:RSP; (* Copy quadword *)
                        RSP <- RSP + 8;
                    ELSE (* OperandSize = 16*)
                        DEST <- SS:RSP; (* Copy a word *)
                        RSP <- RSP + 2;
               FI;
          FI;
      ELSE StackAddrSize = 16
          THEN
               IF OperandSize = 16
                    THEN
                        DEST <- SS:SP; (* Copy a word *)
                        SP <- SP + 2;
                    ELSE (* OperandSize = 32 *)
                        DEST <- SS:SP; (* Copy a doubleword *)
                        SP <- SP + 4;
               FI;

FI;


Loading a segment register while in protected mode results in special actions, as described in the following listing.
These checks are performed on the segment selector and the segment descriptor it points to.

64-BIT_MODE
IF FS, or GS is loaded with non-NULL selector;
    THEN
         IF segment selector index is outside descriptor table limits
               OR segment is not a data or readable code segment
               OR ((segment is a data or nonconforming code segment)
                    AND (both RPL and CPL > DPL))
                        THEN #GP(selector);
               IF segment not marked present
                    THEN #NP(selector);
         ELSE
               SegmentRegister <- segment selector;
               SegmentRegister <- segment descriptor;
         FI;
FI;
IF FS, or GS is loaded with a NULL selector;
         THEN
               SegmentRegister <- segment selector;
               SegmentRegister <- segment descriptor;
FI;



PREOTECTED MODE OR COMPATIBILITY MODE;

IF SS is loaded;



      THEN
         IF segment selector is NULL
              THEN #GP(0);
         FI;
         IF segment selector index is outside descriptor table limits
              or segment selector's RPL != CPL
              or segment is not a writable data segment
              or DPL != CPL
                   THEN #GP(selector);
         FI;
         IF segment not marked present
              THEN #SS(selector);
              ELSE
                   SS <- segment selector;
                   SS <- segment descriptor;
         FI;
FI;

IF DS, ES, FS, or GS is loaded with non-NULL selector;
    THEN
         IF segment selector index is outside descriptor table limits
               or segment is not a data or readable code segment
               or ((segment is a data or nonconforming code segment)
               and (both RPL and CPL > DPL))
                     THEN #GP(selector);
         FI;
         IF segment not marked present
               THEN #NP(selector);
               ELSE
                     SegmentRegister <- segment selector;
                     SegmentRegister <- segment descriptor;
          FI;
FI;

IF DS, ES, FS, or GS is loaded with a NULL selector
    THEN
         SegmentRegister <- segment selector;
         SegmentRegister <- segment descriptor;
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                    If attempt is made to load SS register with NULL segment selector.
                          If the destination operand is in a non-writable segment.
                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                          selector.
#GP(selector)             If segment selector index is outside descriptor table limits.
                          If the SS register is being loaded and the segment selector's RPL and the segment descriptor's
                          DPL are not equal to the CPL.




                        If the SS register is being loaded and the segment pointed to is a
                        non-writable data segment.
                        If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
                        readable code segment.
                        If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
                        nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)                  If the current top of stack is not within the stack segment.
                        If a memory operand effective address is outside the SS segment limit.
#SS(selector)           If the SS register is being loaded and the segment pointed to is marked not present.
#NP                     If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not
                        present.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while the current privilege level is 3 and alignment
                        checking is enabled.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while alignment checking is enabled.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#GP(0)                  If the memory address is in a non-canonical form.
#SS(0)                  If the stack address is in a non-canonical form.
#GP(selector)           If the descriptor is outside the descriptor table limit.
                        If the FS or GS register is being loaded and the segment pointed to is not a data or readable
                        code segment.
                        If the FS or GS register is being loaded and the segment pointed to is a data or nonconforming
                        code segment, but both the RPL and the CPL are greater than the DPL.
#AC(0)                  If an unaligned memory reference is made while alignment checking is enabled.
#PF(fault-code)         If a page fault occurs.
#NP                     If the FS or GS register is being loaded and the segment pointed to is marked not present.
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: POPA
description:
POPA/POPAD-Pop All General-Purpose Registers
Opcode                     Instruction                   Op/    64-Bit    Compat/ Description
                                                         En     Mode      Leg Mode
61                         POPA                          NP     Invalid   Valid      Pop DI, SI, BP, BX, DX, CX, and AX.
61                         POPAD                         NP     Invalid   Valid      Pop EDI, ESI, EBP, EBX, EDX, ECX, and EAX.



                                                   Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                    Operand 3                      Operand 4
     NP                  NA                              NA                          NA                             NA


Description
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose registers. The registers are
loaded in the following order: EDI, ESI, EBP, EBX, EDX, ECX, and EAX (if the operand-size attribute is 32) and DI,
SI, BP, BX, DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse the operation of the
PUSHA/PUSHAD instructions.) The value on the stack for the ESP or SP register is ignored. Instead, the ESP or SP
register is incremented after each register is loaded.
The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode. The POPA instruction is
intended for use when the operand-size attribute is 16 and the POPAD instruction for when the operand-size attri-
bute is 32. Some assemblers may force the operand size to 16 when POPA is used and to 32 when POPAD is used
(using the operand-size override prefix [66H] if necessary). Others may treat these mnemonics as synonyms
(POPA/POPAD) and use the current setting of the operand-size attribute to determine the size of values to be
popped from the stack, regardless of the mnemonic used. (The D flag in the current code segment's segment
descriptor determines the operand-size attribute.)
This instruction executes as described in non-64-bit modes. It is not valid in 64-bit mode.

Operation
IF 64-Bit Mode
    THEN
         #UD;
ELSE
    IF OperandSize = 32 (* Instruction = POPAD *)
    THEN
         EDI <- Pop();
         ESI <- Pop();
         EBP <- Pop();
         Increment ESP by 4; (* Skip next 4 bytes of stack *)
         EBX <- Pop();
         EDX <- Pop();
         ECX <- Pop();
         EAX <- Pop();
    ELSE (* OperandSize = 16, instruction = POPA *)
         DI <- Pop();
         SI <- Pop();
         BP <- Pop();
         Increment ESP by 2; (* Skip next 2 bytes of stack *)
         BX <- Pop();
         DX <- Pop();
         CX <- Pop();
         AX <- Pop();
    FI;
FI;



Flags Affected
None.

Protected Mode Exceptions
#SS(0)                  If the starting or ending stack address is not within the stack segment.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while the current privilege level is 3 and alignment
                        checking is enabled.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#SS                     If the starting or ending stack address is not within the stack segment.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#SS(0)                  If the starting or ending stack address is not within the stack segment.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while alignment checking is enabled.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same as for protected mode exceptions.

64-Bit Mode Exceptions
#UD                     If in 64-bit mode.






platform: x86_64
mnem: POPCNT
description:
POPCNT - Return the Count of Number of Bits Set to 1
 Opcode                        Instruction               Op/   64-Bit   Compat/ Description
                                                         En    Mode     Leg Mode
 F3 0F B8 /r                   POPCNT r16, r/m16         RM    Valid    Valid      POPCNT on r/m16
 F3 0F B8 /r                   POPCNT r32, r/m32         RM    Valid    Valid      POPCNT on r/m32
 F3 REX.W 0F B8 /r             POPCNT r64, r/m64         RM    Valid    N.E.       POPCNT on r/m64



                                                   Instruction Operand Encoding
   Op/En                 Operand 1                    Operand 2                 Operand 3                      Operand 4
     RM               ModRM:reg (w)                ModRM:r/m (r)                   NA                              NA


Description
This instruction calculates the number of bits set to 1 in the second operand (source) and returns the count in the
first operand (a destination register).

Operation
Count = 0;
For (i=0; i < OperandSize; i++)
{        IF (SRC[ i] = 1) // i'th bit
         THEN Count++; FI;
}
DEST <- Count;

Flags Affected
OF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is cleared.

Intel C/C++ Compiler Intrinsic Equivalent
POPCNT:            int _mm_popcnt_u32(unsigned int a);
POPCNT:             int64_t _mm_popcnt_u64(unsigned __int64 a);

Protected Mode Exceptions
#GP(0)                      If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)                      If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)            For a page fault.
#AC(0)                      If an unaligned memory reference is made while the current privilege level is 3 and alignment
                            checking is enabled.
#UD                         If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
                            If LOCK prefix is used.

Real-Address Mode Exceptions
#GP(0)                      If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                      If a memory operand effective address is outside the SS segment limit.
#UD                         If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
                            If LOCK prefix is used.





Virtual 8086 Mode Exceptions
#GP(0)                   If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)         For a page fault.
#AC(0)                   If an unaligned memory reference is made while alignment checking is enabled.
#UD                      If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
                         If LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in Protected Mode.

64-Bit Mode Exceptions
#GP(0)                   If the memory address is in a non-canonical form.
#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)         For a page fault.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.
#UD                      If CPUID.01H:ECX.POPCNT [Bit 23] = 0.
                         If LOCK prefix is used.






platform: x86_64
mnem: POPF
description:
POPF/POPFD/POPFQ-Pop Stack into EFLAGS Register
Opcode                     Instruction                    Op/   64-Bit       Compat/ Description
                                                          En    Mode         Leg Mode
9D                         POPF                           NP    Valid        Valid        Pop top of stack into lower 16 bits of EFLAGS.
9D                         POPFD                          NP    N.E.         Valid        Pop top of stack into EFLAGS.
9D                         POPFQ                          NP    Valid        N.E.         Pop top of stack and zero-extend into RFLAGS.



                                                   Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                       Operand 3                       Operand 4
     NP                   NA                              NA                              NA                              NA


Description
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size attribute is 32) and stores the
value in the EFLAGS register, or pops a word from the top of the stack (if the operand-size attribute is 16) and
stores it in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These instructions reverse the
operation of the PUSHF/PUSHFD instructions.
The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same opcode. The POPF instruction
is intended for use when the operand-size attribute is 16; the POPFD instruction is intended for use when the
operand-size attribute is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for POPFD.
Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting of the operand-size attribute to
determine the size of values to pop from the stack.
The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode of operation. See the Table
4-15 and key below for details.
When operating in protected, compatibility, or 64-bit mode at privilege level 0 (or in real-address mode, the equiv-
alent to privilege level 0), all non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be modi-
fied. VIP, VIF and VM remain unaffected.
When operating in protected, compatibility, or 64-bit mode with a privilege level greater than 0, but less than or
equal to IOPL, all flags can be modified except the IOPL field and RF1, IF, VIP, VIF, and VM; these remain unaffected.
The AC and ID flags can only be modified if the operand-size attribute is 32. The interrupt flag (IF) is altered only
when executing at a level at least as privileged as the IOPL. If a POPF/POPFD instruction is executed with insuffi-
cient privilege, an exception does not occur but privileged bits do not change.
When operating in virtual-8086 mode (EFLAGS.VM = 1) without the virtual-8086 mode extensions (CR4.VME = 0),
the POPF/POPFD instructions can be used only if IOPL = 3; otherwise, a general-protection exception (#GP) occurs.
If the virtual-8086 mode extensions are enabled (CR4.VME = 1), POPF (but not POPFD) can be executed in virtual-
8086 mode with IOPL < 3.
In 64-bit mode, the mnemonic assigned is POPFQ (note that the 32-bit operand is not encodable). POPFQ pops 64
bits from the stack. Reserved bits of RFLAGS (including the upper 32 bits of RFLAGS) are not affected.
See Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for more informa-
tion about the EFLAGS registers.




1. RF is always zero after the execution of POPF. This is because POPF, like all instructions, clears RF as it begins to execute.



                                     Table 4-15. Effect of POPF/POPFD on the EFLAGS Register
                                                                                       Flags
     Mode         Operand   CPL      IOPL                                                                                                 Notes
                                            21   20    19    18   17   16   14   13:12    11    10   9    8    7    6    4    2      0
                    Size
                                            ID   VIP   VIF   AC   VM   RF   NT   IOPL     OF    DF   IF   TF   SF   ZF   AF   PF    CF
 Real-Address        16       0      0-3    N    N     N     N    N    0    S      S       S    S    S    S    S    S    S    S      S
 Mode (CR0.PE
                     32       0      0-3    S    N     N     S    N    0    S      S       S    S    S    S    S    S    S    S      S
     = 0)
  Protected,         16       0      0-3    N    N     N     N    N    0    S      S       S    S    S    S    S    S    S    S      S
 Compatibility,
                     16      1-3     <CPL   N    N     N     N    N    0    S     N        S    S    N    S    S    S    S    S      S
  and 64-Bit
    Modes            16      1-3     >=CPL   N    N     N     N    N    0    S     N        S    S    S    S    S    S    S    S      S
                   32, 64     0      0-3    S    N     N     S    N    0    S      S       S    S    S    S    S    S    S    S      S
 (CR0.PE = 1,
 EFLAGS.VM =       32, 64    1-3     <CPL   S    N     N     S    N    0    S     N        S    S    N    S    S    S    S    S      S
      0)
                   32, 64    1-3     >=CPL   S    N     N     S    N    0    S     N        S    S    S    S    S    S    S    S      S
                                                                                                                                            1
 Virtual-8086        16       3      0-2    X    X     X     X    X    X    X     X        X    X    X    X    X    X    X    X      X
  (CR0.PE = 1,
                     16       3       3     N    N     N     N    N    0    S     N        S    S    S    S    S    S    S    S      S
 EFLAGS.VM =
                                                                                                                                            1
       1,            32       3      0-2    X    X     X     X    X    X    X     X        X    X    X    X    X    X    X    X      X
 CR4.VME = 0)
                     32       3       3     S    N     N     S    N    0    S     N        S    S    S    S    S    S    S    S      S
                                                                                                                                            2
     VME             16       3      0-2    N/   N/    SV/   N/   N/   0/   S/   N/X       S/   S/   N/   S/   S/   S/   S/   S/     S/
  (CR0.PE = 1,                              X    X      X    X    X    X    X              X    X    X    X    X    X    X    X      X
 EFLAGS.VM =
                     16       3       3     N    N     N     N    N    0    S     N        S    S    S    S    S    S    S    S      S
       1,
 CR4.VME = 1)                                                                                                                               1
                     32       3      0-2    X    X     X     X    X    X    X     X        X    X    X    X    X    X    X    X      X
                     32       3       3     S    N     N     S    N    0    S     N        S    S    S    S    S    S    S    S      S

NOTES:
1. #GP fault - no flag update
2. #GP fault with no flag update if VIP=1 in EFLAGS register and IF=1 in FLAGS value on stack


                                      Key
       S          Updated from stack
      SV          Updated from IF (bit 9) in FLAGS value on stack
       N          No change in value
       X          No EFLAGS update
       0          Value is cleared

Operation
IF VM = 0 (* Not in Virtual-8086 Mode *)
    THEN IF CPL = 0
        THEN
             IF OperandSize = 32;
                   THEN
                        EFLAGS <- Pop(); (* 32-bit pop *)
                        (* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
                        VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
                   ELSE IF (Operandsize = 64)
                        RFLAGS = Pop(); (* 64-bit pop *)
                        (* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
                        VIP, VIF, VM, and all reserved bits are unaffected. RF is cleared. *)
                   ELSE (* OperandSize = 16 *)



                      EFLAGS[15:0] <- Pop(); (* 16-bit pop *)
                      (* All non-reserved flags can be modified. *)
            FI;
       ELSE (* CPL > 0 *)
            IF OperandSize = 32
                 THEN
                     IF CPL > IOPL
                           THEN
                               EFLAGS <- Pop(); (* 32-bit pop *)
                               (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;
                               IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
                           ELSE
                               EFLAGS <- Pop(); (* 32-bit pop *)
                               (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;
                               IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
                     FI;
                 ELSE IF (Operandsize = 64)
                     IF CPL > IOPL
                           THEN
                               RFLAGS <- Pop(); (* 64-bit pop *)
                               (* All non-reserved bits except IF, IOPL, VIP, VIF, VM and RF can be modified;
                               IF, IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
                           ELSE
                               RFLAGS <- Pop(); (* 64-bit pop *)
                               (* All non-reserved bits except IOPL, VIP, VIF, VM and RF can be modified;
                               IOPL, VIP, VIF, VM and all reserved bits are unaffected; RF is cleared. *)
                     FI;
                 ELSE (* OperandSize = 16 *)
                     EFLAGS[15:0] <- Pop(); (* 16-bit pop *)
                     (* All non-reserved bits except IOPL can be modified; IOPL and all
                     reserved bits are unaffected. *)
            FI;
       FI;
   ELSE IF CR4.VME = 1 (* In Virtual-8086 Mode with VME Enabled *)
       IF IOPL = 3
            THEN IF OperandSize = 32
                 THEN
                     EFLAGS <- Pop();
                     (* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
                     VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)
                 ELSE
                     EFLAGS[15:0] <- Pop(); FI;
                     (* All non-reserved bits except IOPL can be modified;
                     IOPL and all reserved bits are unaffected. *)
            FI;
       ELSE (* IOPL < 3 *)
            IF (Operandsize = 32)
                 THEN
                     #GP(0); (* Trap to virtual-8086 monitor. *)
                 ELSE (* Operandsize = 16 *)
                     tempFLAGS <- Pop();
                     IF EFLAGS.VIP = 1 AND tempFLAGS[9] = 1
                           THEN #GP(0);
                           ELSE



                                    EFLAGS.VIF <- tempFLAGS[9];
                                    EFLAGS[15:0] <- tempFLAGS;
                              (* All non-reserved bits except IOPL and IF can be modified;
                              IOPL, IF, and all reserved bits are unaffected. *)
                     FI;
               FI;
          FI;
      ELSE (* In Virtual-8086 Mode *)
          IF IOPL = 3
               THEN IF OperandSize = 32
                     THEN
                          EFLAGS <- Pop();
                          (* All non-reserved bits except IOPL, VIP, VIF, VM, and RF can be modified;
                          VIP, VIF, VM, IOPL and all reserved bits are unaffected. RF is cleared. *)
                     ELSE
                          EFLAGS[15:0] <- Pop(); FI;
                          (* All non-reserved bits except IOPL can be modified;
                          IOPL and all reserved bits are unaffected. *)
          ELSE (* IOPL < 3 *)
               #GP(0); (* Trap to virtual-8086 monitor. *)
          FI;
      FI;
FI;

Flags Affected
All flags may be affected; see the Operation section for details.

Protected Mode Exceptions
#SS(0)                     If the top of stack is not within the stack segment.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If an unaligned memory reference is made while the current privilege level is 3 and alignment
                           checking is enabled.
#UD                        If the LOCK prefix is used.

Real-Address Mode Exceptions
#SS                        If the top of stack is not within the stack segment.
#UD                        If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                     If the I/O privilege level is less than 3.
                           If an attempt is made to execute the POPF/POPFD instruction with an operand-size override
                           prefix.
#SS(0)                     If the top of stack is not within the stack segment.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If an unaligned memory reference is made while alignment checking is enabled.
#UD                        If the LOCK prefix is used.

Compatibility Mode Exceptions
Same as for protected mode exceptions.





64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
#SS(0)              If the stack address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: POR
description:
POR-Bitwise Logical OR
Opcode/                                              Op/   64/32 bit   CPUID         Description
Instruction                                          En    Mode        Feature
                                                           Support     Flag
0F EB /r1                                            RM    V/V         MMX           Bitwise OR of mm/m64 and mm.
POR mm, mm/m64
66 0F EB /r                                          RM    V/V         SSE2          Bitwise OR of xmm2/m128 and xmm1.
POR xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EB /r                          RVM V/V           AVX           Bitwise OR of xmm2/m128 and xmm3.
VPOR xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG EB /r                          RVM V/V           AVX2          Bitwise OR of ymm2/m256 and ymm3.
VPOR ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W0 EB /r                          FV    V/V         AVX512VL      Bitwise OR of packed doubleword integers in
VPORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst                            AVX512F       xmm2 and xmm3/m128/m32bcst using
                                                                                     writemask k1.
EVEX.NDS.256.66.0F.W0 EB /r                          FV    V/V         AVX512VL      Bitwise OR of packed doubleword integers in
VPORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst                            AVX512F       ymm2 and ymm3/m256/m32bcst using
                                                                                     writemask k1.
EVEX.NDS.512.66.0F.W0 EB /r                          FV    V/V         AVX512F       Bitwise OR of packed doubleword integers in
VPORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst                                          zmm2 and zmm3/m512/m32bcst using
                                                                                     writemask k1.
EVEX.NDS.128.66.0F.W1 EB /r                          FV    V/V         AVX512VL      Bitwise OR of packed quadword integers in
VPORQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst                            AVX512F       xmm2 and xmm3/m128/m64bcst using
                                                                                     writemask k1.
EVEX.NDS.256.66.0F.W1 EB /r                          FV    V/V         AVX512VL      Bitwise OR of packed quadword integers in
VPORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst                            AVX512F       ymm2 and ymm3/m256/m64bcst using
                                                                                     writemask k1.
EVEX.NDS.512.66.0F.W1 EB /r                          FV    V/V         AVX512F       Bitwise OR of packed quadword integers in
VPORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst                                          zmm2 and zmm3/m512/m64bcst using
                                                                                     writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En                 Operand 1                Operand 2                      Operand 3                   Operand 4
     RM            ModRM:reg (r, w)             ModRM:r/m (r)                       NA                          NA
    RVM             ModRM:reg (w)                VEX.vvvv (r)                 ModRM:r/m (r)                     NA
     FV             ModRM:reg (w)               EVEX.vvvv (r)                 ModRM:r/m (r)                     NA


Description
Performs a bitwise logical OR operation on the source operand (second operand) and the destination operand (first
operand) and stores the result in the destination operand. Each bit of the result is set to 1 if either or both of the
corresponding bits of the first and second operands are 1; otherwise, it is set to 0.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).





Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source and destination operands can be XMM registers. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit memory location. The first
source and destination operands can be YMM registers.
EVEX encoded version: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1 at 32/64-bit granularity.

Operation
POR (64-bit operand)
DEST <- DEST OR SRC


POR (128-bit Legacy SSE version)
DEST <- DEST OR SRC
DEST[VLMAX-1:128] (Unmodified)

VPOR (VEX.128 encoded version)
DEST <- SRC1 OR SRC2
DEST[VLMAX-1:128] <- 0

VPOR (VEX.256 encoded version)
DEST <- SRC1 OR SRC2
DEST[VLMAX-1:256] <- 0

VPORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[31:0]
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE OR SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPORD __m512i _mm512_or_epi32(__m512i a, __m512i b);
VPORD __m512i _mm512_mask_or_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPORD __m512i _mm512_maskz_or_epi32( __mmask16 k, __m512i a, __m512i b);
VPORD __m256i _mm256_or_epi32(__m256i a, __m256i b);
VPORD __m256i _mm256_mask_or_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b,);
VPORD __m256i _mm256_maskz_or_epi32( __mmask8 k, __m256i a, __m256i b);
VPORD __m128i _mm_or_epi32(__m128i a, __m128i b);
VPORD __m128i _mm_mask_or_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORD __m128i _mm_maskz_or_epi32( __mmask8 k, __m128i a, __m128i b);
VPORQ __m512i _mm512_or_epi64(__m512i a, __m512i b);
VPORQ __m512i _mm512_mask_or_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPORQ __m512i _mm512_maskz_or_epi64(__mmask8 k, __m512i a, __m512i b);
VPORQ __m256i _mm256_or_epi64(__m256i a, int imm);
VPORQ __m256i _mm256_mask_or_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPORQ __m256i _mm256_maskz_or_epi64( __mmask8 k, __m256i a, __m256i b);
VPORQ __m128i _mm_or_epi64(__m128i a, __m128i b);
VPORQ __m128i _mm_mask_or_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPORQ __m128i _mm_maskz_or_epi64( __mmask8 k, __m128i a, __m128i b);
POR __m64 _mm_or_si64(__m64 m1, __m64 m2)
(V)POR: __m128i _mm_or_si128(__m128i m1, __m128i m2)
VPOR: __m256i _mm256_or_si256 ( __m256i a, __m256i b)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PREFETCHh
description:
PREFETCHh-Prefetch Data Into Caches
 Opcode                Instruction              Op/      64-Bit   Compat/ Description
                                                En       Mode     Leg Mode
 0F 18 /1              PREFETCHT0 m8            M        Valid    Valid       Move data from m8 closer to the processor
                                                                              using T0 hint.
 0F 18 /2              PREFETCHT1 m8            M        Valid    Valid       Move data from m8 closer to the processor
                                                                              using T1 hint.
 0F 18 /3              PREFETCHT2 m8            M        Valid    Valid       Move data from m8 closer to the processor
                                                                              using T2 hint.
 0F 18 /0              PREFETCHNTA m8           M        Valid    Valid       Move data from m8 closer to the processor
                                                                              using NTA hint.



                                           Instruction Operand Encoding
    Op/En          Operand 1                 Operand 2                    Operand 3                   Operand 4
     M           ModRM:r/m (r)                  NA                           NA                           NA


Description
Fetches the line of data from memory that contains the byte specified with the source operand to a location in the
cache hierarchy specified by a locality hint:
.   T0 (temporal data)-prefetch data into all levels of the cache hierarchy.
.   T1 (temporal data with respect to first level cache misses)-prefetch data into level 2 cache and higher.
.   T2 (temporal data with respect to second level cache misses)-prefetch data into level 3 cache and higher, or
    an implementation-specific choice.
.   NTA (non-temporal data with respect to all cache levels)-prefetch data into non-temporal cache structure and
    into a location close to the processor, minimizing cache pollution.
The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction
using bits 3 through 5 of the ModR/M byte.)
If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are
described in Section 7.4 of Intel 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A
PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur
at any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other
general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
FETCH (m8);





Intel C/C++ Compiler Intrinsic Equivalent
void _mm_prefetch(char *p, int i)
The argument "*p" gives the address of the byte (and corresponding cache line) to be prefetched. The value "i"
gives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2, or _MM_HINT_NTA) that specifies the type of
prefetch operation to be performed.

Numeric Exceptions
None.

Exceptions (All Operating Modes)
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: PREFETCHW
description:
PREFETCHW-Prefetch Data into Caches in Anticipation of a Write
 Opcode/                           Op/   64/32 bit     CPUID     Description
 Instruction                       En    Mode          Feature
                                         Support       Flag
 0F 0D /1                          A     V/V           PRFCHW    Move data from m8 closer to the processor in anticipation of a
 PREFETCHW m8                                                    write.


                                                 Instruction Operand Encoding
  Op/En             Operand 1                        Operand 2              Operand 3                        Operand 4
    M              ModRM:r/m (r)                        NA                      NA                               NA

Description
Fetches the cache line of data from memory that contains the byte specified with the source operand to a location
in the 1st or 2nd level cache and invalidates other cached instances of the line.
The source operand is a byte memory location. If the line selected is already present in the lowest level cache and
is already in an exclusively owned state, no data movement occurs. Prefetches from non-writeback memory are
ignored.
The PREFETCHW instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor and invalidates other cached copies in anticipation of the line being written to
in the future.
The characteristic of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes. Additional details of the implementation-dependent locality hints are
described in Section 7.4 of Intel 64 and IA-32 Architectures Optimization Reference Manual.
It should be noted that processors are free to speculatively fetch and cache data with exclusive ownership from
system memory regions that permit such accesses (that is, the WB memory type). A PREFETCHW instruction is
considered a hint to this speculative behavior. Because this speculative fetching can occur at any time and is not
tied to instruction execution, a PREFETCHW instruction is not ordered with respect to the fence instructions
(MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW instruction is also unordered with
respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHW instructions, or any other general instruction
It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);

Flags Affected
All flags are affected

C/C++ Compiler Intrinsic Equivalent
void _m_prefetchw( void * );

Protected Mode Exceptions
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                      If the LOCK prefix is used.





Virtual-8086 Mode Exceptions
#UD                      If the LOCK prefix is used.

Compatibility Mode Exceptions
#UD                      If the LOCK prefix is used.

64-Bit Mode Exceptions
#UD                      If the LOCK prefix is used.






platform: x86_64
mnem: PREFETCHWT1
description:
PREFETCHWT1-Prefetch Vector Data Into Caches with Intent to Write and T1 Hint
 Opcode/                         Op/     64/32 bit     CPUID Feature      Description
 Instruction                     En      Mode          Flag
                                         Support
 0F 0D /2                        M       V/V           PREFETCHWT1        Move data from m8 closer to the processor using T1 hint
 PREFETCHWT1 m8                                                           with intent to write.


                                                  Instruction Operand Encoding
     Op/En               Operand 1                    Operand 2                      Operand 3                      Operand 4
       M               ModRM:r/m (r)                      NA                            NA                              NA

Description
Fetches the line of data from memory that contains the byte specified with the source operand to a location in the
cache hierarchy specified by an intent to write hint (so that data is brought into 'Exclusive' state via a request for
ownership) and a locality hint:
. T1 (temporal data with respect to first level cache)-prefetch data into the second level cache.
The source operand is a byte memory location. (The locality hints are encoded into the machine level instruction
using bits 3 through 5 of the ModR/M byte. Use of any ModR/M value other than the specified ones will lead to
unpredictable behavior.)
If the line selected is already present in the cache hierarchy at a level closer to the processor, no data movement
occurs. Prefetches from uncacheable or WC memory are ignored.
The PREFETCHh instruction is merely a hint and does not affect program behavior. If executed, this instruction
moves data closer to the processor in anticipation of future use.
The implementation of prefetch locality hints is implementation-dependent, and can be overloaded or ignored by a
processor implementation. The amount of data prefetched is also processor implementation-dependent. It will,
however, be a minimum of 32 bytes.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions that
are assigned a memory-type that permits speculative reads (that is, the WB, WC, and WT memory types). A
PREFETCHh instruction is considered a hint to this speculative behavior. Because this speculative fetching can occur
at any time and is not tied to instruction execution, a PREFETCHh instruction is not ordered with respect to the
fence instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHh instruction is also
unordered with respect to CLFLUSH and CLFLUSHOPT instructions, other PREFETCHh instructions, or any other
general instruction. It is ordered with respect to serializing instructions such as CPUID, WRMSR, OUT, and MOV CR.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request
for exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.

Prefetch (m8, Level = 1, EXCLUSIVE=1);

Flags Affected
All flags are affected

C/C++ Compiler Intrinsic Equivalent
void _mm_prefetch( char const *, int hint= _MM_HINT_ET1);

Protected Mode Exceptions
#UD                      If the LOCK prefix is used.



Real-Address Mode Exceptions
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#UD                      If the LOCK prefix is used.

Compatibility Mode Exceptions
#UD                      If the LOCK prefix is used.

64-Bit Mode Exceptions
#UD                      If the LOCK prefix is used.






platform: x86_64
mnem: PSADBW
description:
PSADBW-Compute Sum of Absolute Differences
Opcode/                                         Op/   64/32 bit   CPUID Feature Description
Instruction                                     En    Mode        Flag
                                                      Support
0F F6 /r1                                       RM    V/V         SSE              Computes the absolute differences of the
PSADBW mm1, mm2/m64                                                                packed unsigned byte integers from mm2
                                                                                   /m64 and mm1; differences are then summed
                                                                                   to produce an unsigned word integer result.
66 0F F6 /r                                     RM    V/V         SSE2             Computes the absolute differences of the
PSADBW xmm1, xmm2/m128                                                             packed unsigned byte integers from xmm2
                                                                                   /m128 and xmm1; the 8 low differences and 8
                                                                                   high differences are then summed separately
                                                                                   to produce two unsigned word integer results.
VEX.NDS.128.66.0F.WIG F6 /r                     RVM V/V           AVX              Computes the absolute differences of the
VPSADBW xmm1, xmm2, xmm3/m128                                                      packed unsigned byte integers from xmm3
                                                                                   /m128 and xmm2; the 8 low differences and 8
                                                                                   high differences are then summed separately
                                                                                   to produce two unsigned word integer results.
VEX.NDS.256.66.0F.WIG F6 /r                     RVM V/V           AVX2             Computes the absolute differences of the
VPSADBW ymm1, ymm2, ymm3/m256                                                      packed unsigned byte integers from ymm3
                                                                                   /m256 and ymm2; then each consecutive 8
                                                                                   differences are summed separately to produce
                                                                                   four unsigned word integer results.
EVEX.NDS.128.66.0F.WIG F6 /r                    FVM V/V           AVX512VL         Computes the absolute differences of the
VPSADBW xmm1, xmm2, xmm3/m128                                     AVX512BW         packed unsigned byte integers from xmm3
                                                                                   /m128 and xmm2; then each consecutive 8
                                                                                   differences are summed separately to produce
                                                                                   four unsigned word integer results.
EVEX.NDS.256.66.0F.WIG F6 /r                    FVM V/V           AVX512VL         Computes the absolute differences of the
VPSADBW ymm1, ymm2, ymm3/m256                                     AVX512BW         packed unsigned byte integers from ymm3
                                                                                   /m256 and ymm2; then each consecutive 8
                                                                                   differences are summed separately to produce
                                                                                   four unsigned word integer results.
EVEX.NDS.512.66.0F.WIG F6 /r                    FVM V/V           AVX512BW         Computes the absolute differences of the
VPSADBW zmm1, zmm2, zmm3/m512                                                      packed unsigned byte integers from zmm3
                                                                                   /m512 and zmm2; then each consecutive 8
                                                                                   differences are summed separately to produce
                                                                                   four unsigned word integer results.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                     Operand 2                    Operand 3                     Operand 4
    RM          ModRM:reg (r, w)               ModRM:r/m (r)                      NA                            NA
   RVM           ModRM:reg (w)                  VEX.vvvv (r)                ModRM:r/m (r)                       NA
   FVM           ModRM:reg (w)                  EVEX.vvvv                   ModRM:r/m (r)                       NA


Description
Computes the absolute value of the difference of 8 unsigned byte integers from the source operand (second



operand) and from the destination operand (first operand). These 8 differences are then summed to produce an
unsigned word integer result that is stored in the destination operand. Figure 4-14 shows the operation of the
PSADBW instruction when using 64-bit operands.
When operating on 64-bit operands, the word integer result is stored in the low word of the destination operand,
and the remaining bytes in the destination operand are cleared to all 0s.
When operating on 128-bit operands, two packed results are computed. Here, the 8 low-order bytes of the source
and destination operands are operated on to produce a word result that is stored in the low word of the destination
operand, and the 8 high-order bytes are operated on to produce a word result that is stored in bits 64 through 79
of the destination operand. The remaining bytes of the destination operand are cleared.
For 256-bit version, the third group of 8 differences are summed to produce an unsigned word in bits[143:128] of
the destination register and the fourth group of 8 differences are summed to produce an unsigned word in
bits[207:192] of the destination register. The remaining words of the destination are set to 0.
For 512-bit version, the fifth group result is stored in bits [271:256] of the destination. The result from the sixth
group is stored in bits [335:320]. The results for the seventh and eighth group are stored respectively in bits
[399:384] and bits [463:447], respectively. The remaining bits in the destination are set to 0.
In 64-bit mode and not encoded by VEX/EVEX prefix, using a REX prefix in the form of REX.R permits this instruc-
tion to access additional registers (XMM8-XMM15).
Legacy SSE version: The source operand can be an MMX technology register or a 64-bit memory location. The
destination operand is an MMX technology register.
128-bit Legacy SSE version: The first source operand and destination register are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding ZMM
destination register remain unchanged.
VEX.128 and EVEX.128 encoded versions: The first source operand and destination register are XMM registers. The
second source operand is an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corre-
sponding ZMM register are zeroed.
VEX.256 and EVEX.256 encoded versions: The first source operand and destination register are YMM registers. The
second source operand is an YMM register or a 256-bit memory location. Bits (MAX_VL-1:256) of the corre-
sponding ZMM register are zeroed.
EVEX.512 encoded version: The first source operand and destination register are ZMM registers. The second
source operand is a ZMM register or a 512-bit memory location.



                          SRC      X7         X6         X5         X4         X3         X2         X1         X0


                         DEST      Y7        Y6          Y5         Y4         Y3         Y2         Y1         Y0


                        TEMP    ABS(X7:Y7) ABS(X6:Y6) ABS(X5:Y5) ABS(X4:Y4) ABS(X3:Y3) ABS(X2:Y2) ABS(X1:Y1) ABS(X0:Y0)




                         DEST      00H       00H        00H         00H       00H         00H     SUM(TEMP7...TEMP0)



                           Figure 4-14. PSADBW Instruction Operation Using 64-bit Operands


Operation
VPSADBW (EVEX encoded versions)
VL = 128, 256, 512
TEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 1 through 15 *)
TEMP15 <- ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H



DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000H

IF VL >= 256
    (* Repeat operation for bytes 16 through 31*)
    TEMP31 <- ABS(SRC1[255:248] - SRC2[255:248])
    DEST[143:128] <-SUM(TEMP16:TEMP23)
    DEST[191:144] <- 000000000000H
    DEST[207:192] <- SUM(TEMP24:TEMP31)
    DEST[223:208] <- 00000000000H
FI;
IF VL >= 512
(* Repeat operation for bytes 32 through 63*)
    TEMP63 <- ABS(SRC1[511:504] - SRC2[511:504])
    DEST[271:256] <-SUM(TEMP0:TEMP7)
    DEST[319:272] <- 000000000000H
    DEST[335:320] <- SUM(TEMP8:TEMP15)
    DEST[383:336] <- 00000000000H
    DEST[399:384] <-SUM(TEMP16:TEMP23)
    DEST[447:400] <- 000000000000H
    DEST[463:448] <- SUM(TEMP24:TEMP31)
    DEST[511:464] <- 00000000000H
FI;
DEST[MAX_VL-1:VL] <- 0

VPSADBW (VEX.256 encoded version)
TEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)
TEMP31 <- ABS(SRC1[255:248] - SRC2[255:248])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H
DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000H
DEST[143:128] <-SUM(TEMP16:TEMP23)
DEST[191:144] <- 000000000000H
DEST[207:192] <- SUM(TEMP24:TEMP31)
DEST[223:208] <- 00000000000H
DEST[MAX_VL-1:256] <- 0





VPSADBW (VEX.128 encoded version)
TEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 <- ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H
DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000H
DEST[MAX_VL-1:128] <- 0

PSADBW (128-bit Legacy SSE version)
TEMP0 <- ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 <- ABS(DEST[127:120] - SRC[127:120])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H
DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000
DEST[MAX_VL-1:128] (Unmodified)

PSADBW (64-bit operand)
TEMP0 <- ABS(DEST[7:0] - SRC[7:0])
(* Repeat operation for bytes 2 through 6 *)
TEMP7 <- ABS(DEST[63:56] - SRC[63:56])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H

Intel C/C++ Compiler Intrinsic Equivalent
VPSADBW __m512i _mm512_sad_epu8( __m512i a, __m512i b)
PSADBW:__m64 _mm_sad_pu8(__m64 a,__m64 b)
(V)PSADBW:__m128i _mm_sad_epu8(__m128i a, __m128i b)
VPSADBW:__m256i _mm256_sad_epu8( __m256i a, __m256i b)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PSHUFB
description:
PSHUFB - Packed Shuffle Bytes
Opcode/                                            Op/   64/32 bit    CPUID        Description
Instruction                                        En    Mode         Feature
                                                         Support      Flag
0F 38 00 /r1                                       RM    V/V          SSSE3        Shuffle bytes in mm1 according to contents of
PSHUFB mm1, mm2/m64                                                                mm2/m64.

66 0F 38 00 /r                                     RM    V/V          SSSE3        Shuffle bytes in xmm1 according to contents of
PSHUFB xmm1, xmm2/m128                                                             xmm2/m128.

VEX.NDS.128.66.0F38.WIG 00 /r                      RVM V/V            AVX          Shuffle bytes in xmm2 according to contents of
VPSHUFB xmm1, xmm2, xmm3/m128                                                      xmm3/m128.

VEX.NDS.256.66.0F38.WIG 00 /r                      RVM V/V            AVX2         Shuffle bytes in ymm2 according to contents of
VPSHUFB ymm1, ymm2, ymm3/m256                                                      ymm3/m256.

EVEX.NDS.128.66.0F38.WIG 00 /r                     FVM V/V            AVX512VL Shuffle bytes in xmm2 according to contents of
VPSHUFB xmm1 {k1}{z}, xmm2, xmm3/m128                                 AVX512BW xmm3/m128 under write mask k1.
EVEX.NDS.256.66.0F38.WIG 00 /r                     FVM V/V            AVX512VL Shuffle bytes in ymm2 according to contents of
VPSHUFB ymm1 {k1}{z}, ymm2, ymm3/m256                                 AVX512BW ymm3/m256 under write mask k1.
EVEX.NDS.512.66.0F38.WIG 00 /r                     FVM V/V            AVX512BW Shuffle bytes in zmm2 according to contents of
VPSHUFB zmm1 {k1}{z}, zmm2, zmm3/m512                                          zmm3/m512 under write mask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                     Operand 2                     Operand 3                    Operand 4
    RM           ModRM:reg (r, w)               ModRM:r/m (r)                      NA                            NA
   RVM            ModRM:reg (w)                  VEX.vvvv (r)                 ModRM:r/m (r)                      NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                      NA


Description
PSHUFB performs in-place shuffles of bytes in the destination operand (the first operand) according to the shuffle
control mask in the source operand (the second operand). The instruction permutes the data in the destination
operand, leaving the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte of the shuffle control
mask is set, then constant zero is written in the result byte. Each byte in the shuffle control mask forms an index
to permute the corresponding byte in the destination operand. The value of each index is the least significant 4 bits
(128-bit operation) or 3 bits (64-bit operation) of the shuffle control byte. When the source operand is a 128-bit
memory operand, the operand must be aligned on a 16-byte boundary or a general-protection exception (#GP) will
be generated.
In 64-bit mode and not encoded with VEX/EVEX, use the REX prefix to access XMM8-XMM15 registers.
Legacy SSE version 64-bit operand: Both operands can be MMX registers.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-
1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The destination operand is the first operand, the first source operand is the second
operand, the second source operand is the third operand. Bits (VLMAX-1:128) of the destination YMM register are
zeroed.
VEX.256 encoded version: Bits (255:128) of the destination YMM register stores the 16-byte shuffle result of the
upper 16 bytes of the first source operand, using the upper 16-bytes of the second source operand as control mask.




The value of each index is for the high 128-bit lane is the least significant 4 bits of the respective shuffle control
byte. The index value selects a source data element within each 128-bit lane.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-
tionally updated with writemask k1.
EVEX and VEX encoded version: Four/two in-lane 128-bit shuffles.

Operation
PSHUFB (with 64 bit operands)
TEMP <- DEST
for i = 0 to 7 {
    if (SRC[(i * 8)+7] = 1 ) then
          DEST[(i*8)+7...(i*8)+0] <- 0;
    else
          index[2..0] <- SRC[(i*8)+2 .. (i*8)+0];
          DEST[(i*8)+7...(i*8)+0] <- TEMP[(index*8+7)..(index*8+0)];
    endif;
}

PSHUFB (with 128 bit operands)
TEMP <- DEST
for i = 0 to 15 {
    if (SRC[(i * 8)+7] = 1 ) then
          DEST[(i*8)+7..(i*8)+0] <- 0;
     else
          index[3..0] <- SRC[(i*8)+3 .. (i*8)+0];
          DEST[(i*8)+7..(i*8)+0] <- TEMP[(index*8+7)..(index*8+0)];
    endif
}

VPSHUFB (VEX.128 encoded version)
for i = 0 to 15 {
    if (SRC2[(i * 8)+7] = 1) then
          DEST[(i*8)+7..(i*8)+0] <- 0;
          else
          index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];
          DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];
    endif
}
DEST[VLMAX-1:128] <- 0

VPSHUFB (VEX.256 encoded version)
for i = 0 to 15 {
    if (SRC2[(i * 8)+7] == 1 ) then
          DEST[(i*8)+7..(i*8)+0] <- 0;
          else
          index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];
          DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];
    endif
    if (SRC2[128 + (i * 8)+7] == 1 ) then
          DEST[128 + (i*8)+7..(i*8)+0] <- 0;
          else
          index[3..0] <- SRC2[128 + (i*8)+3 .. (i*8)+0];
          DEST[128 + (i*8)+7..(i*8)+0] <- SRC1[128 + (index*8+7)..(index*8+0)];



    endif
}
VPSHUFB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
jmask <- (KL-1) & ~0xF                                      // 0x00, 0x10, 0x30 depending on the VL
FOR j = 0 TO KL-1                                          // dest
    IF kl[ i ] or no_masking
          index <- src.byte[ j ];
          IF index & 0x80
                 Dest.byte[ j ] <- 0;
          ELSE
                 index <- (index & 0xF) + (j & jmask);      // 16-element in-lane lookup
                 Dest.byte[ j ] <- src.byte[ index ];
    ELSE if zeroing
          Dest.byte[ j ] <- 0;
DEST[MAX_VL-1:VL] <- 0;




                                                          MM2

                           07H      07H           FFH     80H         01H       00H       00H        00H

                                                          MM1

                           04H      01H           07H     03H        02H        02H       FFH        01H



                                                          MM1
                           04H       04H          00H     00H         FFH       01H        01H       01H




                                             Figure 4-15. PSHUFB with 64-Bit Operands


Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFB __m512i _mm512_shuffle_epi8(__m512i a, __m512i b);
VPSHUFB __m512i _mm512_mask_shuffle_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m512i _mm512_maskz_shuffle_epi8( __mmask64 k, __m512i a, __m512i b);
VPSHUFB __m256i _mm256_mask_shuffle_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m256i _mm256_maskz_shuffle_epi8( __mmask32 k, __m256i a, __m256i b);
VPSHUFB __m128i _mm_mask_shuffle_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSHUFB __m128i _mm_maskz_shuffle_epi8( __mmask16 k, __m128i a, __m128i b);
PSHUFB: __m64 _mm_shuffle_pi8 (__m64 a, __m64 b)
(V)PSHUFB: __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
VPSHUFB:__m256i _mm256_shuffle_epi8(__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PSHUFD
description:
PSHUFD-Shuffle Packed Doublewords
Opcode/                                     Op/   64/32 bit   CPUID      Description
Instruction                                 En    Mode        Feature
                                                  Support     Flag
66 0F 70 /r ib                              RMI   V/V         SSE2       Shuffle the doublewords in xmm2/m128 based on
PSHUFD xmm1, xmm2/m128, imm8                                             the encoding in imm8 and store the result in xmm1.

VEX.128.66.0F.WIG 70 /r ib                  RMI   V/V         AVX        Shuffle the doublewords in xmm2/m128 based on
VPSHUFD xmm1, xmm2/m128, imm8                                            the encoding in imm8 and store the result in xmm1.

VEX.256.66.0F.WIG 70 /r ib                  RMI   V/V         AVX2       Shuffle the doublewords in ymm2/m256 based on
VPSHUFD ymm1, ymm2/m256, imm8                                            the encoding in imm8 and store the result in ymm1.

EVEX.128.66.0F.W0 70 /r ib                  FV    V/V         AVX512VL Shuffle the doublewords in xmm2/m128/m32bcst
VPSHUFD xmm1 {k1}{z}, xmm2/m128/m32bcst,                      AVX512F based on the encoding in imm8 and store the result
imm8                                                                   in xmm1 using writemask k1.
EVEX.256.66.0F.W0 70 /r ib                  FV    V/V         AVX512VL Shuffle the doublewords in ymm2/m256/m32bcst
VPSHUFD ymm1 {k1}{z}, ymm2/m256/m32bcst,                      AVX512F based on the encoding in imm8 and store the result
imm8                                                                   in ymm1 using writemask k1.
EVEX.512.66.0F.W0 70 /r ib                  FV    V/V         AVX512F    Shuffle the doublewords in zmm2/m512/m32bcst
VPSHUFD zmm1 {k1}{z}, zmm2/m512/m32bcst,                                 based on the encoding in imm8 and store the result
imm8                                                                     in zmm1 using writemask k1.



                                           Instruction Operand Encoding
   Op/En            Operand 1               Operand 2                   Operand 3                    Operand 4
    RMI           ModRM:reg (w)            ModRM:r/m (r)                  imm8                           NA
    FV            ModRM:reg (w)            ModRM:r/m (r)                  Imm8                           NA


Description
Copies doublewords from source operand (second operand) and inserts them in the destination operand (first
operand) at the locations selected with the order operand (third operand). Figure 4-16 shows the operation of the
256-bit VPSHUFD instruction and the encoding of the order operand. Each 2-bit field in the order operand selects
the contents of one doubleword location within a 128-bit lane and copy to the target element in the destination
operand. For example, bits 0 and 1 of the order operand targets the first doubleword element in the low and high
128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded value of bits 1:0 of the order operand
(see the field encoding in Figure 4-16) determines which doubleword element (from the respective 128-bit lane) of
the source operand will be copied to doubleword 0 of the destination operand.
For 128-bit operation, only the low 128-bit lane are operative. The source operand can be an XMM register or a
128-bit memory location. The destination operand is an XMM register. The order operand is an 8-bit immediate.
Note that this instruction permits a doubleword in the source operand to be copied to more than one doubleword
location in the destination operand.





                             SRC      X7         X6       X5      X4       X3          X2           X1         X0




                            DEST       Y7         Y6      Y5       Y4      Y3          Y2           Y1         Y0


                                Encoding      00B - X4
                               of Fields in   01B - X5                                Encoding      00B - X0
                                                         ORDER                       of Fields in   01B - X1
                                  ORDER       10B - X6
                                 Operand      11B - X7           7 6 5 4 3 2 1   0
                                                                                        ORDER       10B - X2
                                                                                       Operand      11B - X3


                                    Figure 4-16. 256-bit VPSHUFD Instruction Operation

The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM
register. The order operand is an 8-bit immediate. Note that this instruction permits a doubleword in the source
operand to be copied to more than one doubleword location in the destination operand.
In 64-bit mode and not encoded in VEX/EVEX, using REX.R permits this instruction to access XMM8-XMM15.
128-bit Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The source operand can be an XMM register or a 128-bit memory location. The destina-
tion operand is an XMM register. Bits (MAX_VL-1:128) of the corresponding ZMM register are zeroed.
VEX.256 encoded version: The source operand can be an YMM register or a 256-bit memory location. The destina-
tion operand is an YMM register. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed. Bits (255-
1:128) of the destination stores the shuffled results of the upper 16 bytes of the source operand using the imme-
diate byte as the order operand.
EVEX encoded version: The source operand can be an ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion, or a 512/256/128-bit vector broadcasted from a 32-bit memory location. The destination operand is a
ZMM/YMM/XMM register updated according to the writemask.
Each 128-bit lane of the destination stores the shuffled results of the respective lane of the source operand using
the immediate byte as the order operand.
Note: EVEX.vvvv and VEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation
PSHUFD (128-bit Legacy SSE version)
DEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] (Unmodified)

VPSHUFD (VEX.128 encoded version)
DEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] <- 0





VPSHUFD (VEX.256 encoded version)
DEST[31:0] <- (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[159:128] <- (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[191:160] <- (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[223:192] <- (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[255:224] <- (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:256] <- 0

VPSHUFD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC *is memory*)
         THEN TMP_SRC[i+31:i] <- SRC[31:0]
         ELSE TMP_SRC[i+31:i] <- SRC[i+31:i]
    FI;
ENDFOR;
IF VL >= 128
    TMP_DEST[31:0] <- (TMP_SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
    TMP_DEST[63:32] <- (TMP_SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
    TMP_DEST[95:64] <- (TMP_SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
    TMP_DEST[127:96] <- (TMP_SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 256
    TMP_DEST[159:128] <- (TMP_SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
    TMP_DEST[191:160] <- (TMP_SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
    TMP_DEST[223:192] <- (TMP_SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
    TMP_DEST[255:224] <- (TMP_SRC[255:128] >> (ORDER[7:6] * 32))[31:0];
FI;
IF VL >= 512
    TMP_DEST[287:256] <- (TMP_SRC[383:256] >> (ORDER[1:0] * 32))[31:0];
    TMP_DEST[319:288] <- (TMP_SRC[383:256] >> (ORDER[3:2] * 32))[31:0];
    TMP_DEST[351:320] <- (TMP_SRC[383:256] >> (ORDER[5:4] * 32))[31:0];
    TMP_DEST[383:352] <- (TMP_SRC[383:256] >> (ORDER[7:6] * 32))[31:0];
    TMP_DEST[415:384] <- (TMP_SRC[511:384] >> (ORDER[1:0] * 32))[31:0];
    TMP_DEST[447:416] <- (TMP_SRC[511:384] >> (ORDER[3:2] * 32))[31:0];
    TMP_DEST[479:448] <-(TMP_SRC[511:384] >> (ORDER[5:4] * 32))[31:0];
    TMP_DEST[511:480] <- (TMP_SRC[511:384] >> (ORDER[7:6] * 32))[31:0];
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR



DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFD __m512i _mm512_shuffle_epi32(__m512i a, int n );
VPSHUFD __m512i _mm512_mask_shuffle_epi32(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFD __m512i _mm512_maskz_shuffle_epi32( __mmask16 k, __m512i a, int n );
VPSHUFD __m256i _mm256_mask_shuffle_epi32(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFD __m256i _mm256_maskz_shuffle_epi32( __mmask8 k, __m256i a, int n );
VPSHUFD __m128i _mm_mask_shuffle_epi32(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFD __m128i _mm_maskz_shuffle_epi32( __mmask8 k, __m128i a, int n );
(V)PSHUFD:__m128i _mm_shuffle_epi32(__m128i a, int n)
VPSHUFD:__m256i _mm256_shuffle_epi32(__m256i a, const int n)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.
#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PSHUFHW
description:
PSHUFHW-Shuffle Packed High Words
Opcode/                                        Op/   64/32 bit   CPUID       Description
Instruction                                    En    Mode        Feature
                                                     Support     Flag
F3 0F 70 /r ib                                 RMI   V/V         SSE2        Shuffle the high words in xmm2/m128 based
PSHUFHW xmm1, xmm2/m128, imm8                                                on the encoding in imm8 and store the result in
                                                                             xmm1.
VEX.128.F3.0F.WIG 70 /r ib                     RMI   V/V         AVX         Shuffle the high words in xmm2/m128 based
VPSHUFHW xmm1, xmm2/m128, imm8                                               on the encoding in imm8 and store the result in
                                                                             xmm1.
VEX.256.F3.0F.WIG 70 /r ib                     RMI   V/V         AVX2        Shuffle the high words in ymm2/m256 based
VPSHUFHW ymm1, ymm2/m256, imm8                                               on the encoding in imm8 and store the result in
                                                                             ymm1.
EVEX.128.F3.0F.WIG 70 /r ib                    FVM V/V           AVX512VL Shuffle the high words in xmm2/m128 based
VPSHUFHW xmm1 {k1}{z}, xmm2/m128, imm8                           AVX512BW on the encoding in imm8 and store the result in
                                                                          xmm1 under write mask k1.
EVEX.256.F3.0F.WIG 70 /r ib                    FVM V/V           AVX512VL Shuffle the high words in ymm2/m256 based
VPSHUFHW ymm1 {k1}{z}, ymm2/m256, imm8                           AVX512BW on the encoding in imm8 and store the result in
                                                                          ymm1 under write mask k1.
EVEX.512.F3.0F.WIG 70 /r ib                    FVM V/V           AVX512BW Shuffle the high words in zmm2/m512 based
VPSHUFHW zmm1 {k1}{z}, zmm2/m512, imm8                                    on the encoding in imm8 and store the result in
                                                                          zmm1 under write mask k1.



                                            Instruction Operand Encoding
  Op/En             Operand 1                  Operand 2                   Operand 3                    Operand 4
    RMI           ModRM:reg (w)              ModRM:r/m (r)                   imm8                          NA
   FVM            ModRM:reg (w)              ModRM:r/m (r)                   Imm8                          NA


Description
Copies words from the high quadword of a 128-bit lane of the source operand and inserts them in the high quad-
word of the destination operand at word locations (of the respective lane) selected with the immediate operand.
This 256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illus-
trated in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the high quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from the high quadword of the source
operand to be copied to the destination operand. The low quadword of the source operand is copied to the low
quadword of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the high quadword of the source operand to be copied to more than one
word location in the high quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv is
reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.





EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.
Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
PSHUFHW (128-bit Legacy SSE version)
DEST[63:0] <- SRC[63:0]
DEST[79:64] <- (SRC >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] (Unmodified)

VPSHUFHW (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] <- 0

VPSHUFHW (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[191:128] <- SRC1[191:128]
DEST[207192] <- (SRC1 >> (imm[1:0] *16))[207:192]
DEST[223:208] <- (SRC1 >> (imm[3:2] * 16))[207:192]
DEST[239:224] <- (SRC1 >> (imm[5:4] * 16))[207:192]
DEST[255:240] <- (SRC1 >> (imm[7:6] * 16))[207:192]
DEST[VLMAX-1:256] <- 0

VPSHUFHW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
    TMP_DEST[63:0] <- SRC1[63:0]
    TMP_DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]
    TMP_DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]
    TMP_DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]
    TMP_DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]
FI;
IF VL >= 256
    TMP_DEST[191:128] <- SRC1[191:128]
    TMP_DEST[207:192] <- (SRC1 >> (imm[1:0] *16))[207:192]
    TMP_DEST[223:208] <- (SRC1 >> (imm[3:2] * 16))[207:192]
    TMP_DEST[239:224] <- (SRC1 >> (imm[5:4] * 16))[207:192]
    TMP_DEST[255:240] <- (SRC1 >> (imm[7:6] * 16))[207:192]
FI;
IF VL >= 512
    TMP_DEST[319:256] <- SRC1[319:256]
    TMP_DEST[335:320] <- (SRC1 >> (imm[1:0] *16))[335:320]



      TMP_DEST[351:336] <- (SRC1 >> (imm[3:2] * 16))[335:320]
      TMP_DEST[367:352] <- (SRC1 >> (imm[5:4] * 16))[335:320]
      TMP_DEST[383:368] <- (SRC1 >> (imm[7:6] * 16))[335:320]
      TMP_DEST[447:384] <- SRC1[447:384]
      TMP_DEST[463:448] <- (SRC1 >> (imm[1:0] *16))[463:448]
      TMP_DEST[479:464] <- (SRC1 >> (imm[3:2] * 16))[463:448]
      TMP_DEST[495:480] <- (SRC1 >> (imm[5:4] * 16))[463:448]
      TMP_DEST[511:496] <- (SRC1 >> (imm[7:6] * 16))[463:448]
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i];
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFHW __m512i _mm512_shufflehi_epi16(__m512i a, int n);
VPSHUFHW __m512i _mm512_mask_shufflehi_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFHW __m512i _mm512_maskz_shufflehi_epi16( __mmask16 k, __m512i a, int n );
VPSHUFHW __m256i _mm256_mask_shufflehi_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFHW __m256i _mm256_maskz_shufflehi_epi16( __mmask8 k, __m256i a, int n );
VPSHUFHW __m128i _mm_mask_shufflehi_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFHW __m128i _mm_maskz_shufflehi_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFHW:__m128i _mm_shufflehi_epi16(__m128i a, int n)
VPSHUFHW:__m256i _mm256_shufflehi_epi16(__m256i a, const int n)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb
#UD                     If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PSHUFLW
description:
PSHUFLW-Shuffle Packed Low Words
Opcode/                                      Op/   64/32 bit   CPUID        Description
Instruction                                  En    Mode        Feature
                                                   Support     Flag
F2 0F 70 /r ib                               RMI   V/V         SSE2         Shuffle the low words in xmm2/m128 based on
PSHUFLW xmm1, xmm2/m128, imm8                                               the encoding in imm8 and store the result in
                                                                            xmm1.
VEX.128.F2.0F.WIG 70 /r ib                   RMI   V/V         AVX          Shuffle the low words in xmm2/m128 based on
VPSHUFLW xmm1, xmm2/m128, imm8                                              the encoding in imm8 and store the result in
                                                                            xmm1.
VEX.256.F2.0F.WIG 70 /r ib                   RMI   V/V         AVX2         Shuffle the low words in ymm2/m256 based on
VPSHUFLW ymm1, ymm2/m256, imm8                                              the encoding in imm8 and store the result in
                                                                            ymm1.
EVEX.128.F2.0F.WIG 70 /r ib                  FVM V/V           AVX512VL Shuffle the low words in xmm2/m128 based on
VPSHUFLW xmm1 {k1}{z}, xmm2/m128, imm8                         AVX512BW the encoding in imm8 and store the result in
                                                                        xmm1 under write mask k1.
EVEX.256.F2.0F.WIG 70 /r ib                  FVM V/V           AVX512VL Shuffle the low words in ymm2/m256 based on
VPSHUFLW ymm1 {k1}{z}, ymm2/m256, imm8                         AVX512BW the encoding in imm8 and store the result in
                                                                        ymm1 under write mask k1.
EVEX.512.F2.0F.WIG 70 /r ib                  FVM V/V           AVX512BW Shuffle the low words in zmm2/m512 based on
VPSHUFLW zmm1 {k1}{z}, zmm2/m512, imm8                                  the encoding in imm8 and store the result in
                                                                        zmm1 under write mask k1.



                                          Instruction Operand Encoding
  Op/En             Operand 1               Operand 2                    Operand 3                    Operand 4
   RMI            ModRM:reg (w)           ModRM:r/m (r)                    imm8                          NA
   FVM            ModRM:reg (w)           ModRM:r/m (r)                    Imm8                          NA


Description
Copies words from the low quadword of a 128-bit lane of the source operand and inserts them in the low quadword
of the destination operand at word locations (of the respective lane) selected with the immediate operand. The
256-bit operation is similar to the in-lane operation used by the 256-bit VPSHUFD instruction, which is illustrated
in Figure 4-16. For 128-bit operation, only the low 128-bit lane is operative. Each 2-bit field in the immediate
operand selects the contents of one word location in the low quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3) from the low quadword of the source operand
to be copied to the destination operand. The high quadword of the source operand is copied to the high quadword
of the destination operand, for each 128-bit lane.
Note that this instruction permits a word in the low quadword of the source operand to be copied to more than one
word location in the low quadword of the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The destination operand is an XMM register. The source operand can be an XMM
register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.
VEX.128 encoded version: The destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The destination operand is an YMM register. The source operand can be an YMM register
or a 256-bit memory location.
EVEX encoded version: The destination operand is a ZMM/YMM/XMM registers. The source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.


Note: In VEX encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
PSHUFLW (128-bit Legacy SSE version)
DEST[15:0] <- (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)

VPSHUFLW (VEX.128 encoded version)
DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC[127:64]
DEST[VLMAX-1:128] <- 0

VPSHUFLW (VEX.256 encoded version)
DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC1[127:64]
DEST[143:128] <- (SRC1 >> (imm[1:0] *16))[143:128]
DEST[159:144] <- (SRC1 >> (imm[3:2] * 16))[143:128]
DEST[175:160] <- (SRC1 >> (imm[5:4] * 16))[143:128]
DEST[191:176] <- (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] <- SRC1[255:192]
DEST[VLMAX-1:256] <- 0

VPSHUFLW (EVEX.U1.512 encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL >= 128
    TMP_DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]
    TMP_DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]
    TMP_DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]
    TMP_DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]
    TMP_DEST[127:64] <- SRC1[127:64]
FI;
IF VL >= 256
    TMP_DEST[143:128] <- (SRC1 >> (imm[1:0] *16))[143:128]
    TMP_DEST[159:144] <- (SRC1 >> (imm[3:2] * 16))[143:128]
    TMP_DEST[175:160] <- (SRC1 >> (imm[5:4] * 16))[143:128]
    TMP_DEST[191:176] <- (SRC1 >> (imm[7:6] * 16))[143:128]
    TMP_DEST[255:192] <- SRC1[255:192]
FI;
IF VL >= 512
    TMP_DEST[271:256] <- (SRC1 >> (imm[1:0] *16))[271:256]
    TMP_DEST[287:272] <- (SRC1 >> (imm[3:2] * 16))[271:256]
    TMP_DEST[303:288] <- (SRC1 >> (imm[5:4] * 16))[271:256]
    TMP_DEST[319:304] <- (SRC1 >> (imm[7:6] * 16))[271:256]
    TMP_DEST[383:320] <- SRC1[383:320]



      TMP_DEST[399:384] <- (SRC1 >> (imm[1:0] *16))[399:384]
      TMP_DEST[415:400] <- (SRC1 >> (imm[3:2] * 16))[399:384]
      TMP_DEST[431:416] <- (SRC1 >> (imm[5:4] * 16))[399:384]
      TMP_DEST[447:432] <- (SRC1 >> (imm[7:6] * 16))[399:384]
      TMP_DEST[511:448] <- SRC1[511:448]
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i];
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPSHUFLW __m512i _mm512_shufflelo_epi16(__m512i a, int n);
VPSHUFLW __m512i _mm512_mask_shufflelo_epi16(__m512i s, __mmask16 k, __m512i a, int n );
VPSHUFLW __m512i _mm512_maskz_shufflelo_epi16( __mmask16 k, __m512i a, int n );
VPSHUFLW __m256i _mm256_mask_shufflelo_epi16(__m256i s, __mmask8 k, __m256i a, int n );
VPSHUFLW __m256i _mm256_maskz_shufflelo_epi16( __mmask8 k, __m256i a, int n );
VPSHUFLW __m128i _mm_mask_shufflelo_epi16(__m128i s, __mmask8 k, __m128i a, int n );
VPSHUFLW __m128i _mm_maskz_shufflelo_epi16( __mmask8 k, __m128i a, int n );
(V)PSHUFLW:__m128i _mm_shufflelo_epi16(__m128i a, int n)
VPSHUFLW:__m256i _mm256_shufflelo_epi16(__m256i a, const int n)

Flags Affected
None.

SIMD Floating-Point Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb
#UD                     If VEX.vvvv != 1111B, or EVEX.vvvv != 1111B.






platform: x86_64
mnem: PSHUFW
description:
PSHUFW-Shuffle Packed Words
Opcode/                                               Op/   64-Bit    Compat/ Description
Instruction                                           En    Mode      Leg Mode
0F 70 /r ib                                           RMI   Valid     Valid       Shuffle the words in mm2/m64 based on the
PSHUFW mm1, mm2/m64, imm8                                                         encoding in imm8 and store the result in mm1.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                     Operand 2                 Operand 3                    Operand 4
    RMI             ModRM:reg (w)                 ModRM:r/m (r)                  imm8                          NA


Description
Copies words from the source operand (second operand) and inserts them in the destination operand (first
operand) at word locations selected with the order operand (third operand). This operation is similar to the opera-
tion used by the PSHUFD instruction, which is illustrated in Figure 4-16. For the PSHUFW instruction, each 2-bit
field in the order operand selects the contents of one word location in the destination operand. The encodings of the
order operand fields select words from the source operand to be copied to the destination operand.
The source operand can be an MMX technology register or a 64-bit memory location. The destination operand is an
MMX technology register. The order operand is an 8-bit immediate. Note that this instruction permits a word in the
source operand to be copied to more than one word location in the destination operand.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).

Operation
DEST[15:0] <- (SRC >> (ORDER[1:0] * 16))[15:0];
DEST[31:16] <- (SRC >> (ORDER[3:2] * 16))[15:0];
DEST[47:32] <- (SRC >> (ORDER[5:4] * 16))[15:0];
DEST[63:48] <- (SRC >> (ORDER[7:6] * 16))[15:0];

Intel C/C++ Compiler Intrinsic Equivalent
PSHUFW:         __m64 _mm_shuffle_pi16(__m64 a, int n)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
See Table 22-7, "Exception Conditions for SIMD/MMX Instructions with Memory Reference," in the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.






platform: x86_64
mnem: PSIGNB
description:
PSIGNB/PSIGNW/PSIGND - Packed SIGN
 Opcode/                                              Op/    64/32 bit   CPUID       Description
 Instruction                                          En     Mode        Feature
                                                             Support     Flag
 0F 38 08 /r1                                         RM     V/V         SSSE3       Negate/zero/preserve packed byte integers in
 PSIGNB mm1, mm2/m64                                                                 mm1 depending on the corresponding sign in
                                                                                     mm2/m64.
 66 0F 38 08 /r                                       RM     V/V         SSSE3       Negate/zero/preserve packed byte integers in
 PSIGNB xmm1, xmm2/m128                                                              xmm1 depending on the corresponding sign in
                                                                                     xmm2/m128.
 0F 38 09 /r1                                         RM     V/V         SSSE3       Negate/zero/preserve packed word integers
 PSIGNW mm1, mm2/m64                                                                 in mm1 depending on the corresponding sign
                                                                                     in mm2/m128.
 66 0F 38 09 /r                                       RM     V/V         SSSE3       Negate/zero/preserve packed word integers
 PSIGNW xmm1, xmm2/m128                                                              in xmm1 depending on the corresponding sign
                                                                                     in xmm2/m128.
 0F 38 0A /r1                                         RM     V/V         SSSE3       Negate/zero/preserve packed doubleword
 PSIGND mm1, mm2/m64                                                                 integers in mm1 depending on the
                                                                                     corresponding sign in mm2/m128.
 66 0F 38 0A /r                                       RM     V/V         SSSE3       Negate/zero/preserve packed doubleword
 PSIGND xmm1, xmm2/m128                                                              integers in xmm1 depending on the
                                                                                     corresponding sign in xmm2/m128.
 VEX.NDS.128.66.0F38.WIG 08 /r                        RVM V/V            AVX         Negate/zero/preserve packed byte integers in
 VPSIGNB xmm1, xmm2, xmm3/m128                                                       xmm2 depending on the corresponding sign in
                                                                                     xmm3/m128.
 VEX.NDS.128.66.0F38.WIG 09 /r                        RVM V/V            AVX         Negate/zero/preserve packed word integers
 VPSIGNW xmm1, xmm2, xmm3/m128                                                       in xmm2 depending on the corresponding sign
                                                                                     in xmm3/m128.
 VEX.NDS.128.66.0F38.WIG 0A /r                        RVM V/V            AVX         Negate/zero/preserve packed doubleword
 VPSIGND xmm1, xmm2, xmm3/m128                                                       integers in xmm2 depending on the
                                                                                     corresponding sign in xmm3/m128.
 VEX.NDS.256.66.0F38.WIG 08 /r                        RVM V/V            AVX2        Negate packed byte integers in ymm2 if the
 VPSIGNB ymm1, ymm2, ymm3/m256                                                       corresponding sign in ymm3/m256 is less
                                                                                     than zero.
 VEX.NDS.256.66.0F38.WIG 09 /r                        RVM V/V            AVX2        Negate packed 16-bit integers in ymm2 if the
 VPSIGNW ymm1, ymm2, ymm3/m256                                                       corresponding sign in ymm3/m256 is less
                                                                                     than zero.
 VEX.NDS.256.66.0F38.WIG 0A /r                        RVM V/V            AVX2        Negate packed doubleword integers in ymm2
 VPSIGND ymm1, ymm2, ymm3/m256                                                       if the corresponding sign in ymm3/m256 is
                                                                                     less than zero.
 NOTES:
 1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
 Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                Instruction Operand Encoding
  Op/En              Operand 1                   Operand 2                       Operand 3                   Operand 4
    RM            ModRM:reg (r, w)              ModRM:r/m (r)                       NA                           NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                   ModRM:r/m (r)                     NA





Description
(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand (the first operand) if the
signed integer value of the corresponding data element in the source operand (the second operand) is less than
zero. If the signed integer value of a data element in the source operand is positive, the corresponding data
element in the destination operand is unchanged. If a data element in the source operand is zero, the corre-
sponding data element in the destination operand is set to zero.
(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words. (V)PSIGND operates on signed
32-bit integers. When the source operand is a 128bit memory operand, the operand must be aligned on a 16-byte
boundary or a general-protection exception (#GP) will be generated.
Legacy SSE instructions: Both operands can be MMX registers. In 64-bit mode, use the REX prefix to access addi-
tional registers.
128-bit Legacy SSE version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destina-
tion register remain unchanged.
VEX.128 encoded version: The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.L must be 0, otherwise instructions will #UD.
VEX.256 encoded version: The first source and destination operands are YMM registers. The second source
operand is an YMM register or a 256-bit memory location.

Operation
PSIGNB (with 64 bit operands)
   IF (SRC[7:0] < 0 )
        DEST[7:0] <- Neg(DEST[7:0])
   ELSEIF (SRC[7:0] = 0 )
        DEST[7:0] <- 0
   ELSEIF (SRC[7:0] > 0 )
        DEST[7:0] <- DEST[7:0]
   Repeat operation for 2nd through 7th bytes

   IF (SRC[63:56] < 0 )
        DEST[63:56] <- Neg(DEST[63:56])
   ELSEIF (SRC[63:56] = 0 )
        DEST[63:56] <- 0
   ELSEIF (SRC[63:56] > 0 )
        DEST[63:56] <- DEST[63:56]

PSIGNB (with 128 bit operands)
   IF (SRC[7:0] < 0 )
        DEST[7:0] <- Neg(DEST[7:0])
   ELSEIF (SRC[7:0] = 0 )
        DEST[7:0] <- 0
   ELSEIF (SRC[7:0] > 0 )
        DEST[7:0] <- DEST[7:0]
   Repeat operation for 2nd through 15th bytes
   IF (SRC[127:120] < 0 )
        DEST[127:120] <- Neg(DEST[127:120])
   ELSEIF (SRC[127:120] = 0 )
        DEST[127:120] <- 0
   ELSEIF (SRC[127:120] > 0 )
        DEST[127:120] <- DEST[127:120]





VPSIGNB (VEX.128 encoded version)
DEST[127:0] <-BYTE_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0

VPSIGNB (VEX.256 encoded version)
DEST[255:0] <-BYTE_SIGN_256b(SRC1, SRC2)

PSIGNW (with 64 bit operands)
   IF (SRC[15:0] < 0 )
        DEST[15:0] <- Neg(DEST[15:0])
   ELSEIF (SRC[15:0] = 0 )
        DEST[15:0] <- 0
   ELSEIF (SRC[15:0] > 0 )
        DEST[15:0] <- DEST[15:0]
Repeat operation for 2nd through 3rd words
   IF (SRC[63:48] < 0 )
        DEST[63:48] <- Neg(DEST[63:48])
   ELSEIF (SRC[63:48] = 0 )
        DEST[63:48] <- 0
   ELSEIF (SRC[63:48] > 0 )
        DEST[63:48] <- DEST[63:48]

PSIGNW (with 128 bit operands)
   IF (SRC[15:0] < 0 )
        DEST[15:0] <- Neg(DEST[15:0])
   ELSEIF (SRC[15:0] = 0 )
        DEST[15:0] <- 0
   ELSEIF (SRC[15:0] > 0 )
        DEST[15:0] <- DEST[15:0]
   Repeat operation for 2nd through 7th words
   IF (SRC[127:112] < 0 )
        DEST[127:112] <- Neg(DEST[127:112])
   ELSEIF (SRC[127:112] = 0 )
        DEST[127:112] <- 0
   ELSEIF (SRC[127:112] > 0 )
        DEST[127:112] <- DEST[127:112]

VPSIGNW (VEX.128 encoded version)
DEST[127:0] <-WORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0

VPSIGNW (VEX.256 encoded version)
DEST[255:0] <-WORD_SIGN(SRC1, SRC2)

PSIGND (with 64 bit operands)
   IF (SRC[31:0] < 0 )
        DEST[31:0] <- Neg(DEST[31:0])
   ELSEIF (SRC[31:0] = 0 )
        DEST[31:0] <- 0
   ELSEIF (SRC[31:0] > 0 )
        DEST[31:0] <- DEST[31:0]
   IF (SRC[63:32] < 0 )
        DEST[63:32] <- Neg(DEST[63:32])
   ELSEIF (SRC[63:32] = 0 )
        DEST[63:32] <- 0



   ELSEIF (SRC[63:32] > 0 )
       DEST[63:32] <- DEST[63:32]

PSIGND (with 128 bit operands)
   IF (SRC[31:0] < 0 )
        DEST[31:0] <- Neg(DEST[31:0])
   ELSEIF (SRC[31:0] = 0 )
        DEST[31:0] <- 0
   ELSEIF (SRC[31:0] > 0 )
        DEST[31:0] <- DEST[31:0]
   Repeat operation for 2nd through 3rd double words
   IF (SRC[127:96] < 0 )
        DEST[127:96] <- Neg(DEST[127:96])
   ELSEIF (SRC[127:96] = 0 )
        DEST[127:96] <- 0
   ELSEIF (SRC[127:96] > 0 )
        DEST[127:96] <- DEST[127:96]

VPSIGND (VEX.128 encoded version)
DEST[127:0] <-DWORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0

VPSIGND (VEX.256 encoded version)
DEST[255:0] <-DWORD_SIGN(SRC1, SRC2)

Intel C/C++ Compiler Intrinsic Equivalent
PSIGNB:         __m64 _mm_sign_pi8 (__m64 a, __m64 b)
(V)PSIGNB:      __m128i _mm_sign_epi8 (__m128i a, __m128i b)
VPSIGNB:        __m256i _mm256_sign_epi8 (__m256i a, __m256i b)
PSIGNW:         __m64 _mm_sign_pi16 (__m64 a, __m64 b)
(V)PSIGNW:      __m128i _mm_sign_epi16 (__m128i a, __m128i b)
VPSIGNW:        __m256i _mm256_sign_epi16 (__m256i a, __m256i b)
PSIGND:         __m64 _mm_sign_pi32 (__m64 a, __m64 b)
(V)PSIGND:      __m128i _mm_sign_epi32 (__m128i a, __m128i b)
VPSIGND:        __m256i _mm256_sign_epi32 (__m256i a, __m256i b)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                    If VEX.L = 1.






platform: x86_64
mnem: PSLLDQ
description:
PSLLDQ-Shift Double Quadword Left Logical
Opcode/                                         Op/     64/32 bit   CPUID         Description
Instruction                                     En      Mode        Feature
                                                        Support     Flag
66 0F 73 /7 ib                                  MI      V/V         SSE2          Shift xmm1 left by imm8 bytes while shifting
PSLLDQ xmm1, imm8                                                                 in 0s.

VEX.NDD.128.66.0F.WIG 73 /7 ib                  VMI     V/V         AVX           Shift xmm2 left by imm8 bytes while shifting
VPSLLDQ xmm1, xmm2, imm8                                                          in 0s and store result in xmm1.

VEX.NDD.256.66.0F.WIG 73 /7 ib                  VMI     V/V         AVX2          Shift ymm2 left by imm8 bytes while shifting
VPSLLDQ ymm1, ymm2, imm8                                                          in 0s and store result in ymm1.

EVEX.NDD.128.66.0F.WIG 73 /7 ib                 FVMI V/V            AVX512VL Shift xmm2/m128 left by imm8 bytes while
VPSLLDQ xmm1,xmm2/ m128, imm8                                       AVX512BW shifting in 0s and store result in xmm1.
EVEX.NDD.256.66.0F.WIG 73 /7 ib                 FVMI V/V            AVX512VL Shift ymm2/m256 left by imm8 bytes while
VPSLLDQ ymm1, ymm2/m256, imm8                                       AVX512BW shifting in 0s and store result in ymm1.
EVEX.NDD.512.66.0F.WIG 73 /7 ib                 FVMI V/V            AVX512BW Shift zmm2/m512 left by imm8 bytes while
VPSLLDQ zmm1, zmm2/m512, imm8                                                shifting in 0s and store result in zmm1.



                                             Instruction Operand Encoding
   Op/En              Operand 1                Operand 2                      Operand 3                   Operand 4
     MI            ModRM:r/m (r, w)              imm8                            NA                           NA
    VMI              VEX.vvvv (w)            ModRM:r/m (r)                      imm8                          NA
   FVMI             EVEX.vvvv (w)            ModRM:r/m (R)                      Imm8                          NA


Description
Shifts the destination operand (first operand) to the left by the number of bytes specified in the count operand
(second operand). The empty low-order bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corre-
sponding YMM destination register remain unchanged.
VEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed.
VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits
(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and
high 128-bit lanes.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.

Operation
VPSLLDQ (EVEX.U1.512 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST[127:0] <- SRC[127:0] << (TEMP * 8)
DEST[255:128] <- SRC[255:128] << (TEMP * 8)
DEST[383:256] <- SRC[383:256] << (TEMP * 8)
DEST[511:384] <- SRC[511:384] << (TEMP * 8)
DEST[MAX_VL-1:512] <- 0





VPSLLDQ (VEX.256 and EVEX.256 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST[127:0] <- SRC[127:0] << (TEMP * 8)
DEST[255:128] <- SRC[255:128] << (TEMP * 8)
DEST[MAX_VL-1:256] <- 0

VPSLLDQ (VEX.128 and EVEX.128 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- SRC << (TEMP * 8)
DEST[MAX_VL-1:128] <- 0


PSLLDQ(128-bit Legacy SSE version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- DEST << (TEMP * 8)
DEST[VLMAX-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
(V)PSLLDQ:__m128i _mm_slli_si128 ( __m128i a, int imm)
VPSLLDQ:__m256i _mm256_slli_si256 ( __m256i a, const int imm)
VPSLLDQ __m512i _mm512_bslli_epi128 ( __m512i a, const int imm)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PSLLW
description:
PSLLW/PSLLD/PSLLQ-Shift Packed Data Left Logical
Opcode/                                            Op/   64/32 bit   CPUID     Description
Instruction                                        En    Mode        Feature
                                                         Support     Flag
0F F1 /r1                                          RM    V/V         MMX       Shift words in mm left mm/m64 while shifting in
PSLLW mm, mm/m64                                                               0s.

66 0F F1 /r                                        RM    V/V         SSE2      Shift words in xmm1 left by xmm2/m128 while
PSLLW xmm1, xmm2/m128                                                          shifting in 0s.

0F 71 /6 ib                                        MI    V/V         MMX       Shift words in mm left by imm8 while shifting in
PSLLW mm1, imm8                                                                0s.

66 0F 71 /6 ib                                     MI    V/V         SSE2      Shift words in xmm1 left by imm8 while shifting
PSLLW xmm1, imm8                                                               in 0s.

0F F2 /r1                                          RM    V/V         MMX       Shift doublewords in mm left by mm/m64 while
PSLLD mm, mm/m64                                                               shifting in 0s.
66 0F F2 /r                                        RM    V/V         SSE2      Shift doublewords in xmm1 left by xmm2/m128
PSLLD xmm1, xmm2/m128                                                          while shifting in 0s.

0F 72 /6 ib1                                       MI    V/V         MMX       Shift doublewords in mm left by imm8 while
PSLLD mm, imm8                                                                 shifting in 0s.

66 0F 72 /6 ib                                     MI    V/V         SSE2      Shift doublewords in xmm1 left by imm8 while
PSLLD xmm1, imm8                                                               shifting in 0s.

0F F3 /r1                                          RM    V/V         MMX       Shift quadword in mm left by mm/m64 while
PSLLQ mm, mm/m64                                                               shifting in 0s.

66 0F F3 /r                                        RM    V/V         SSE2      Shift quadwords in xmm1 left by xmm2/m128
PSLLQ xmm1, xmm2/m128                                                          while shifting in 0s.

0F 73 /6 ib1                                       MI    V/V         MMX       Shift quadword in mm left by imm8 while
PSLLQ mm, imm8                                                                 shifting in 0s.

66 0F 73 /6 ib                                     MI    V/V         SSE2      Shift quadwords in xmm1 left by imm8 while
PSLLQ xmm1, imm8                                                               shifting in 0s.

VEX.NDS.128.66.0F.WIG F1 /r                        RVM   V/V         AVX       Shift words in xmm2 left by amount specified in
VPSLLW xmm1, xmm2, xmm3/m128                                                   xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 71 /6 ib                     VMI   V/V         AVX       Shift words in xmm2 left by imm8 while shifting
VPSLLW xmm1, xmm2, imm8                                                        in 0s.

VEX.NDS.128.66.0F.WIG F2 /r                        RVM   V/V         AVX       Shift doublewords in xmm2 left by amount
VPSLLD xmm1, xmm2, xmm3/m128                                                   specified in xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 72 /6 ib                     VMI   V/V         AVX       Shift doublewords in xmm2 left by imm8 while
VPSLLD xmm1, xmm2, imm8                                                        shifting in 0s.

VEX.NDS.128.66.0F.WIG F3 /r                        RVM   V/V         AVX       Shift quadwords in xmm2 left by amount
VPSLLQ xmm1, xmm2, xmm3/m128                                                   specified in xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 73 /6 ib                     VMI   V/V         AVX       Shift quadwords in xmm2 left by imm8 while
VPSLLQ xmm1, xmm2, imm8                                                        shifting in 0s.

VEX.NDS.256.66.0F.WIG F1 /r                        RVM   V/V         AVX2      Shift words in ymm2 left by amount specified in
VPSLLW ymm1, ymm2, xmm3/m128                                                   xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 71 /6 ib                     VMI   V/V         AVX2      Shift words in ymm2 left by imm8 while shifting
VPSLLW ymm1, ymm2, imm8                                                        in 0s.





VEX.NDS.256.66.0F.WIG F2 /r               RVM    V/V   AVX2        Shift doublewords in ymm2 left by amount
VPSLLD ymm1, ymm2, xmm3/m128                                       specified in xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 72 /6 ib            VMI    V/V   AVX2        Shift doublewords in ymm2 left by imm8 while
VPSLLD ymm1, ymm2, imm8                                            shifting in 0s.

VEX.NDS.256.66.0F.WIG F3 /r               RVM    V/V   AVX2        Shift quadwords in ymm2 left by amount
VPSLLQ ymm1, ymm2, xmm3/m128                                       specified in xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 73 /6 ib            VMI    V/V   AVX2        Shift quadwords in ymm2 left by imm8 while
VPSLLQ ymm1, ymm2, imm8                                            shifting in 0s.

EVEX.NDS.128.66.0F.WIG F1 /r              M128 V/V     AVX512VL Shift words in xmm2 left by amount specified in
VPSLLW xmm1 {k1}{z}, xmm2, xmm3/m128                   AVX512BW xmm3/m128 while shifting in 0s using
                                                                writemask k1.
EVEX.NDS.256.66.0F.WIG F1 /r              M128 V/V     AVX512VL Shift words in ymm2 left by amount specified in
VPSLLW ymm1 {k1}{z}, ymm2, xmm3/m128                   AVX512BW xmm3/m128 while shifting in 0s using
                                                                writemask k1.
EVEX.NDS.512.66.0F.WIG F1 /r              M128 V/V     AVX512BW Shift words in zmm2 left by amount specified in
VPSLLW zmm1 {k1}{z}, zmm2, xmm3/m128                            xmm3/m128 while shifting in 0s using
                                                                writemask k1.
EVEX.NDD.128.66.0F.WIG 71 /6 ib           FVMI   V/V   AVX512VL Shift words in xmm2/m128 left by imm8 while
VPSLLW xmm1 {k1}{z}, xmm2/m128, imm8                   AVX512BW shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /6 ib           FVMI   V/V   AVX512VL Shift words in ymm2/m256 left by imm8 while
VPSLLW ymm1 {k1}{z}, ymm2/m256, imm8                   AVX512BW shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /6 ib           FVMI   V/V   AVX512BW Shift words in zmm2/m512 left by imm8 while
VPSLLW zmm1 {k1}{z}, zmm2/m512, imm8                            shifting in 0 using writemask k1.
EVEX.NDS.128.66.0F.W0 F2 /r               M128 V/V     AVX512VL    Shift doublewords in xmm2 left by amount
VPSLLD xmm1 {k1}{z}, xmm2, xmm3/m128                   AVX512F     specified in xmm3/m128 while shifting in 0s
                                                                   under writemask k1.
EVEX.NDS.256.66.0F.W0 F2 /r               M128 V/V     AVX512VL    Shift doublewords in ymm2 left by amount
VPSLLD ymm1 {k1}{z}, ymm2, xmm3/m128                   AVX512F     specified in xmm3/m128 while shifting in 0s
                                                                   under writemask k1.
EVEX.NDS.512.66.0F.W0 F2 /r               M128 V/V     AVX512F     Shift doublewords in zmm2 left by amount
VPSLLD zmm1 {k1}{z}, zmm2, xmm3/m128                               specified in xmm3/m128 while shifting in 0s
                                                                   under writemask k1.
EVEX.NDD.128.66.0F.W0 72 /6 ib            FVI    V/V   AVX512VL    Shift doublewords in xmm2/m128/m32bcst left
VPSLLD xmm1 {k1}{z}, xmm2/m128/m32bcst,                AVX512F     by imm8 while shifting in 0s using writemask k1.
imm8
EVEX.NDD.256.66.0F.W0 72 /6 ib            FVI    V/V   AVX512VL    Shift doublewords in ymm2/m256/m32bcst left
VPSLLD ymm1 {k1}{z}, ymm2/m256/m32bcst,                AVX512F     by imm8 while shifting in 0s using writemask k1.
imm8
EVEX.NDD.512.66.0F.W0 72 /6 ib            FVI    V/V   AVX512F     Shift doublewords in zmm2/m512/m32bcst left
VPSLLD zmm1 {k1}{z}, zmm2/m512/m32bcst,                            by imm8 while shifting in 0s using writemask k1.
imm8
EVEX.NDS.128.66.0F.W1 F3 /r               M128 V/V     AVX512VL    Shift quadwords in xmm2 left by amount
VPSLLQ xmm1 {k1}{z}, xmm2, xmm3/m128                   AVX512F     specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.256.66.0F.W1 F3 /r               M128 V/V     AVX512VL    Shift quadwords in ymm2 left by amount
VPSLLQ ymm1 {k1}{z}, ymm2, xmm3/m128                   AVX512F     specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.512.66.0F.W1 F3 /r               M128 V/V     AVX512F     Shift quadwords in zmm2 left by amount
VPSLLQ zmm1 {k1}{z}, zmm2, xmm3/m128                               specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.




EVEX.NDD.128.66.0F.W1 73 /6 ib                       FVI      V/V         AVX512VL    Shift quadwords in xmm2/m128/m64bcst left
VPSLLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,                                   AVX512F     by imm8 while shifting in 0s using writemask k1.
imm8
EVEX.NDD.256.66.0F.W1 73 /6 ib                       FVI      V/V         AVX512VL    Shift quadwords in ymm2/m256/m64bcst left
VPSLLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,                                   AVX512F     by imm8 while shifting in 0s using writemask k1.
imm8
EVEX.NDD.512.66.0F.W1 73 /6 ib                       FVI      V/V         AVX512F     Shift quadwords in zmm2/m512/m64bcst left
VPSLLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,                                               by imm8 while shifting in 0s using writemask k1.
imm8
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                    Instruction Operand Encoding
    Op/En               Operand 1                          Operand 2                  Operand 3                    Operand 4
     RM              ModRM:reg (r, w)                 ModRM:r/m (r)                       NA                           NA
      MI             ModRM:r/m (r, w)                        imm8                         NA                          NA
    RVM               ModRM:reg (w)                      VEX.vvvv (r)                ModRM:r/m (r)                    NA
     VMI               VEX.vvvv (w)                   ModRM:r/m (r)                     imm8                          NA
    FVMI              EVEX.vvvv (w)                   ModRM:r/m (R)                     Imm8                          NA
     FVI              EVEX.vvvv (w)                   ModRM:r/m (R)                     Imm8                          NA
    M128              ModRM:reg (w)                      VEX.vvvv (r)                ModRM:r/m (r)                    NA


Description
Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first
operand) to the left by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted left, the empty low-order bits are cleared (set to 0). If the value specified by the count
operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand
is set to all 0s. Figure 4-17 gives an example of shifting words in a 64-bit operand.


                              Pre-Shift
                                               X3                X2           X1               X0
                                 DEST
                              Shift Left
                              with Zero
                              Extension

                            Post-Shift
                               DEST        X3 << COUNT      X2 << COUNT   X1 << COUNT X0 << COUNT

                   Figure 4-17. PSLLW, PSLLD, and PSLLQ Instruction Operation Using 64-bit Operand

The (V)PSLLW instruction shifts each of the words in the destination operand to the left by the number of bits spec-
ified in the count operand; the (V)PSLLD instruction shifts each of the doublewords in the destination operand; and
the (V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count
operand can be either an MMX technology register or an 64-bit memory location.





128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register
or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded
but the upper 64 bits are ignored.
VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-
tion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are
ignored.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-
diate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /6, or EVEX.128.66.0F 71-73 /6),
VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation
PSLLW (with 64-bit operand)
   IF (COUNT > 15)
   THEN
        DEST[64:0] <- 0000000000000000H;
   ELSE
        DEST[15:0] <- ZeroExtend(DEST[15:0] << COUNT);
        (* Repeat shift operation for 2nd and 3rd words *)
        DEST[63:48] <- ZeroExtend(DEST[63:48] << COUNT);
   FI;

PSLLD (with 64-bit operand)
   IF (COUNT > 31)
   THEN
        DEST[64:0] <- 0000000000000000H;
   ELSE
        DEST[31:0] <- ZeroExtend(DEST[31:0] << COUNT);
        DEST[63:32] <- ZeroExtend(DEST[63:32] << COUNT);
   FI;

PSLLQ (with 64-bit operand)
   IF (COUNT > 63)
   THEN
        DEST[64:0] <- 0000000000000000H;
   ELSE
        DEST <- ZeroExtend(DEST << COUNT);
   FI;

LOGICAL_LEFT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 15)
THEN



    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[15:0] <-ZeroExtend(SRC[15:0] << COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
    DEST[127:112] <-ZeroExtend(SRC[127:112] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[31:0] <- 0
ELSE
    DEST[31:0] <- ZeroExtend(SRC[31:0] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[31:0] <-ZeroExtend(SRC[31:0] << COUNT);
    (* Repeat shift operation for 2nd through 3rd words *)
    DEST[127:96] <-ZeroExtend(SRC[127:96] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[63:0] <- 0
ELSE
    DEST[63:0] <- ZeroExtend(SRC[63:0] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_QWORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[63:0] <-ZeroExtend(SRC[63:0] << COUNT);
    DEST[127:64] <-ZeroExtend(SRC[127:64] << COUNT);
FI;
LOGICAL_LEFT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
    DEST[255:128] <-00000000000000000000000000000000H
ELSE
    DEST[15:0] <-ZeroExtend(SRC[15:0] << COUNT);
    (* Repeat shift operation for 2nd through 15th words *)



      DEST[255:240] <-ZeroExtend(SRC[255:240] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
    DEST[255:128] <-00000000000000000000000000000000H
ELSE
    DEST[31:0] <-ZeroExtend(SRC[31:0] << COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
    DEST[255:224] <-ZeroExtend(SRC[255:224] << COUNT);
FI;

LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
    DEST[255:128] <-00000000000000000000000000000000H
ELSE
    DEST[63:0] <-ZeroExtend(SRC[63:0] << COUNT);
    DEST[127:64] <-ZeroExtend(SRC[127:64] << COUNT)
    DEST[191:128] <-ZeroExtend(SRC[191:128] << COUNT);
    DEST[255:192] <-ZeroExtend(SRC[255:192] << COUNT);
FI;

VPSLLW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



VPSLLW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
    TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSLLW (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSLLW (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_WORD_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;

VPSLLW (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSLLW (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0





PSLLW (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSLLW (xmm, imm8)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

VPSLLD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+31:i] <- LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[31:0], imm8)
                    ELSE DEST[i+31:i] <- LOGICAL_LEFT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSLLD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VPSLLD (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSLLD (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;

VPSLLD (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSLLD (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSLLD (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSLLD (xmm, imm8)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

VPSLLQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+63:i] <- LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[63:0], imm8)
                    ELSE DEST[i+63:i] <- LOGICAL_LEFT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR

VPSLLQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
FI;



FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <-0

VPSLLQ (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSLLQ (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;

VPSLLQ (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSLLQ (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSLLQ (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSLLQ (xmm, imm8)
DEST[127:0] <-LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents
VPSLLD __m512i _mm512_slli_epi32(__m512i a, unsigned int imm);
VPSLLD __m512i _mm512_mask_slli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m512i _mm512_maskz_slli_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSLLD __m256i _mm256_mask_slli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m256i _mm256_maskz_slli_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSLLD __m128i _mm_mask_slli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLD __m128i _mm_maskz_slli_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSLLD __m512i _mm512_sll_epi32(__m512i a, __m128i cnt);
VPSLLD __m512i _mm512_mask_sll_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSLLD __m512i _mm512_maskz_sll_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSLLD __m256i _mm256_mask_sll_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSLLD __m256i _mm256_maskz_sll_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSLLD __m128i _mm_mask_sll_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLD __m128i _mm_maskz_sll_epi32( __mmask8 k, __m128i a, __m128i cnt);



VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_slli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);
VPSLLQ __m512i _mm512_maskz_slli_epi64( __mmask8 k, __m512i a, unsigned int imm);
VPSLLQ __m256i _mm256_mask_slli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSLLQ __m256i _mm256_maskz_slli_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSLLQ __m128i _mm_mask_slli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLQ __m128i _mm_maskz_slli_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i a, __m128i cnt);
VPSLLQ __m512i _mm512_mask_sll_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m512i _mm512_maskz_sll_epi64( __mmask8 k, __m512i a, __m128i cnt);
VPSLLQ __m256i _mm256_mask_sll_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m256i _mm256_maskz_sll_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSLLQ __m128i _mm_mask_sll_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLQ __m128i _mm_maskz_sll_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m512i _mm512_slli_epi16(__m512i a, unsigned int imm);
VPSLLW __m512i _mm512_mask_slli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
VPSLLW __m512i _mm512_maskz_slli_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSLLW __m256i _mm256_mask_sllii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSLLW __m256i _mm256_maskz_slli_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSLLW __m128i _mm_mask_slli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSLLW __m128i _mm_maskz_slli_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSLLW __m512i _mm512_sll_epi16(__m512i a, __m128i cnt);
VPSLLW __m512i _mm512_mask_sll_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m512i _mm512_maskz_sll_epi16( __mmask32 k, __m512i a, __m128i cnt);
VPSLLW __m256i _mm256_mask_sll_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m256i _mm256_maskz_sll_epi16( __mmask16 k, __m256i a, __m128i cnt);
VPSLLW __m128i _mm_mask_sll_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLW __m128i _mm_maskz_sll_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSLLW:__m64 _mm_slli_pi16 (__m64 m, int count)
PSLLW:__m64 _mm_sll_pi16(__m64 m, __m64 count)
(V)PSLLW:__m128i _mm_slli_pi16(__m64 m, int count)
(V)PSLLW:__m128i _mm_slli_pi16(__m128i m, __m128i count)
VPSLLW:__m256i _mm256_slli_epi16 (__m256i m, int count)
VPSLLW:__m256i _mm256_sll_epi16 (__m256i m, __m128i count)
PSLLD:__m64 _mm_slli_pi32(__m64 m, int count)
PSLLD:__m64 _mm_sll_pi32(__m64 m, __m64 count)
(V)PSLLD:__m128i _mm_slli_epi32(__m128i m, int count)
(V)PSLLD:__m128i _mm_sll_epi32(__m128i m, __m128i count)
VPSLLD:__m256i _mm256_slli_epi32 (__m256i m, int count)
VPSLLD:__m256i _mm256_sll_epi32 (__m256i m, __m128i count)
PSLLQ:__m64 _mm_slli_si64(__m64 m, int count)
PSLLQ:__m64 _mm_sll_si64(__m64 m, __m64 count)
(V)PSLLQ:__m128i _mm_slli_epi64(__m128i m, int count)
(V)PSLLQ:__m128i _mm_sll_epi64(__m128i m, __m128i count)
VPSLLQ:__m256i _mm256_slli_epi64 (__m256i m, int count)
VPSLLQ:__m256i _mm256_sll_epi64 (__m256i m, __m128i count)

Flags Affected
None.

Numeric Exceptions
None.




Other Exceptions
VEX-encoded instructions:
    Syntax with RM/RVM operand encoding, see Exceptions Type 4.
    Syntax with MI/VMI operand encoding, see Exceptions Type 7.


EVEX-encoded VPSLLW, see Exceptions Type E4NF.nb.


EVEX-encoded VPSLLD/Q:
    Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
    Syntax with FVI operand encoding, see Exceptions Type E4.






platform: x86_64
mnem: PSRAW
description:
PSRAW/PSRAD/PSRAQ-Shift Packed Data Right Arithmetic
Opcode/                                          Op/   64/32 bit   CPUID       Description
Instruction                                      En    Mode        Feature
                                                       Support     Flag
0F E1 /r1                                        RM    V/V         MMX         Shift words in mm right by mm/m64 while shifting
PSRAW mm, mm/m64                                                               in sign bits.

66 0F E1 /r                                      RM    V/V         SSE2        Shift words in xmm1 right by xmm2/m128 while
PSRAW xmm1, xmm2/m128                                                          shifting in sign bits.

0F 71 /4 ib1                                     MI    V/V         MMX         Shift words in mm right by imm8 while shifting in
PSRAW mm, imm8                                                                 sign bits

66 0F 71 /4 ib                                   MI    V/V         SSE2        Shift words in xmm1 right by imm8 while shifting
PSRAW xmm1, imm8                                                               in sign bits

0F E2 /r1                                        RM    V/V         MMX         Shift doublewords in mm right by mm/m64 while
PSRAD mm, mm/m64                                                               shifting in sign bits.

66 0F E2 /r                                      RM    V/V         SSE2        Shift doubleword in xmm1 right by xmm2 /m128
PSRAD xmm1, xmm2/m128                                                          while shifting in sign bits.

0F 72 /4 ib1                                     MI    V/V         MMX         Shift doublewords in mm right by imm8 while
PSRAD mm, imm8                                                                 shifting in sign bits.

66 0F 72 /4 ib                                   MI    V/V         SSE2        Shift doublewords in xmm1 right by imm8 while
PSRAD xmm1, imm8                                                               shifting in sign bits.

VEX.NDS.128.66.0F.WIG E1 /r                      RVM   V/V         AVX         Shift words in xmm2 right by amount specified in
VPSRAW xmm1, xmm2, xmm3/m128                                                   xmm3/m128 while shifting in sign bits.

VEX.NDD.128.66.0F.WIG 71 /4 ib                   VMI   V/V         AVX         Shift words in xmm2 right by imm8 while shifting
VPSRAW xmm1, xmm2, imm8                                                        in sign bits.

VEX.NDS.128.66.0F.WIG E2 /r                      RVM   V/V         AVX         Shift doublewords in xmm2 right by amount
VPSRAD xmm1, xmm2, xmm3/m128                                                   specified in xmm3/m128 while shifting in sign
                                                                               bits.
VEX.NDD.128.66.0F.WIG 72 /4 ib                   VMI   V/V         AVX         Shift doublewords in xmm2 right by imm8 while
VPSRAD xmm1, xmm2, imm8                                                        shifting in sign bits.

VEX.NDS.256.66.0F.WIG E1 /r                      RVM   V/V         AVX2        Shift words in ymm2 right by amount specified in
VPSRAW ymm1, ymm2, xmm3/m128                                                   xmm3/m128 while shifting in sign bits.

VEX.NDD.256.66.0F.WIG 71 /4 ib                   VMI   V/V         AVX2        Shift words in ymm2 right by imm8 while shifting
VPSRAW ymm1, ymm2, imm8                                                        in sign bits.
VEX.NDS.256.66.0F.WIG E2 /r                      RVM   V/V         AVX2        Shift doublewords in ymm2 right by amount
VPSRAD ymm1, ymm2, xmm3/m128                                                   specified in xmm3/m128 while shifting in sign
                                                                               bits.
VEX.NDD.256.66.0F.WIG 72 /4 ib                   VMI   V/V         AVX2        Shift doublewords in ymm2 right by imm8 while
VPSRAD ymm1, ymm2, imm8                                                        shifting in sign bits.

EVEX.NDS.128.66.0F.WIG E1 /r                     M128 V/V          AVX512VL Shift words in xmm2 right by amount specified in
VPSRAW xmm1 {k1}{z}, xmm2, xmm3/m128                               AVX512BW xmm3/m128 while shifting in sign bits using
                                                                            writemask k1.
EVEX.NDS.256.66.0F.WIG E1 /r                     M128 V/V          AVX512VL Shift words in ymm2 right by amount specified in
VPSRAW ymm1 {k1}{z}, ymm2, xmm3/m128                               AVX512BW xmm3/m128 while shifting in sign bits using
                                                                            writemask k1.
EVEX.NDS.512.66.0F.WIG E1 /r                     M128 V/V          AVX512BW Shift words in zmm2 right by amount specified in
VPSRAW zmm1 {k1}{z}, zmm2, xmm3/m128                                        xmm3/m128 while shifting in sign bits using
                                                                            writemask k1.




EVEX.NDD.128.66.0F.WIG 71 /4 ib                  FVMI   V/V          AVX512VL Shift words in xmm2/m128 right by imm8 while
VPSRAW xmm1 {k1}{z}, xmm2/m128, imm8                                 AVX512BW shifting in sign bits using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /4 ib                  FVMI   V/V          AVX512VL Shift words in ymm2/m256 right by imm8 while
VPSRAW ymm1 {k1}{z}, ymm2/m256, imm8                                 AVX512BW shifting in sign bits using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /4 ib                  FVMI   V/V          AVX512BW Shift words in zmm2/m512 right by imm8 while
VPSRAW zmm1 {k1}{z}, zmm2/m512, imm8                                          shifting in sign bits using writemask k1.
EVEX.NDS.128.66.0F.W0 E2 /r                      M128 V/V            AVX512VL     Shift doublewords in xmm2 right by amount
VPSRAD xmm1 {k1}{z}, xmm2, xmm3/m128                                 AVX512F      specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDS.256.66.0F.W0 E2 /r                      M128 V/V            AVX512VL     Shift doublewords in ymm2 right by amount
VPSRAD ymm1 {k1}{z}, ymm2, xmm3/m128                                 AVX512F      specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDS.512.66.0F.W0 E2 /r                      M128 V/V            AVX512F      Shift doublewords in zmm2 right by amount
VPSRAD zmm1 {k1}{z}, zmm2, xmm3/m128                                              specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDD.128.66.0F.W0 72 /4 ib                   FVI    V/V          AVX512VL     Shift doublewords in xmm2/m128/m32bcst right
VPSRAD xmm1 {k1}{z}, xmm2/m128/m32bcst,                              AVX512F      by imm8 while shifting in sign bits using
imm8                                                                              writemask k1.
EVEX.NDD.256.66.0F.W0 72 /4 ib                   FVI    V/V          AVX512VL     Shift doublewords in ymm2/m256/m32bcst right
VPSRAD ymm1 {k1}{z}, ymm2/m256/m32bcst,                              AVX512F      by imm8 while shifting in sign bits using
imm8                                                                              writemask k1.
EVEX.NDD.512.66.0F.W0 72 /4 ib                   FVI    V/V          AVX512F      Shift doublewords in zmm2/m512/m32bcst right
VPSRAD zmm1 {k1}{z}, zmm2/m512/m32bcst,                                           by imm8 while shifting in sign bits using
imm8                                                                              writemask k1.
EVEX.NDS.128.66.0F.W1 E2 /r                      M128 V/V            AVX512VL     Shift quadwords in xmm2 right by amount
VPSRAQ xmm1 {k1}{z}, xmm2, xmm3/m128                                 AVX512F      specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDS.256.66.0F.W1 E2 /r                      M128 V/V            AVX512VL     Shift quadwords in ymm2 right by amount
VPSRAQ ymm1 {k1}{z}, ymm2, xmm3/m128                                 AVX512F      specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDS.512.66.0F.W1 E2 /r                      M128 V/V            AVX512F      Shift quadwords in zmm2 right by amount
VPSRAQ zmm1 {k1}{z}, zmm2, xmm3/m128                                              specified in xmm3/m128 while shifting in sign bits
                                                                                  using writemask k1.
EVEX.NDD.128.66.0F.W1 72 /4 ib                   FVI    V/V          AVX512VL     Shift quadwords in xmm2/m128/m64bcst right by
VPSRAQ xmm1 {k1}{z}, xmm2/m128/m64bcst,                              AVX512F      imm8 while shifting in sign bits using writemask
imm8                                                                              k1.
EVEX.NDD.256.66.0F.W1 72 /4 ib                   FVI    V/V          AVX512VL     Shift quadwords in ymm2/m256/m64bcst right by
VPSRAQ ymm1 {k1}{z}, ymm2/m256/m64bcst,                              AVX512F      imm8 while shifting in sign bits using writemask
imm8                                                                              k1.
EVEX.NDD.512.66.0F.W1 72 /4 ib                   FVI    V/V          AVX512F      Shift quadwords in zmm2/m512/m64bcst right by
VPSRAQ zmm1 {k1}{z}, zmm2/m512/m64bcst,                                           imm8 while shifting in sign bits using writemask
imm8                                                                              k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers" in
the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.





                                                    Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                 Operand 3                    Operand 4
    RM             ModRM:reg (r, w)                 ModRM:r/m (r)                  NA                           NA
     MI            ModRM:r/m (r, w)                      imm8                      NA                           NA
    RVM             ModRM:reg (w)                    VEX.vvvv (r)            ModRM:r/m (r)                      NA
    VMI             VEX.vvvv (w)                    ModRM:r/m (r)                  imm8                         NA
   FVMI             EVEX.vvvv (w)                   ModRM:r/m (R)                  Imm8                         NA
    FVI             EVEX.vvvv (w)                   ModRM:r/m (R)                  Imm8                         NA
   M128             ModRM:reg (w)                    EVEX.vvvv (r)           ModRM:r/m (r)                      NA


Description
Shifts the bits in the individual data elements (words, doublewords or quadwords) in the destination operand (first
operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted right, the empty high-order bits are filled with the initial value of the sign bit of the data
element. If the value specified by the count operand is greater than 15 (for words), 31 (for doublewords), or 63 (for
quadwords), each destination data element is filled with the initial value of the sign bit of the element. (Figure 4-18
gives an example of shifting words in a 64-bit operand.)



                             Pre-Shift
                                               X3               X2         X1               X0
                                DEST
                             Shift Right
                               with Sign
                              Extension

                            Post-Shift
                               DEST        X3 >> COUNT    X2 >> COUNT   X1 >> COUNT X0 >> COUNT




                     Figure 4-18. PSRAW and PSRAD Instruction Operation Using a 64-bit Operand


Note that only the first 64-bits of a 128-bit count operand are checked to compute the count. If the second source
operand is a memory address, 128 bits are loaded.
The (V)PSRAW instruction shifts each of the words in the destination operand to the right by the number of bits
specified in the count operand, and the (V)PSRAD instruction shifts each of the doublewords in the destination
operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The destination operand is an MMX technology register; the count
operand can be either an MMX technology register or an 64-bit memory location.
128-bit Legacy SSE version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of
the corresponding YMM destination register remain unchanged. The count operand can be either an XMM register
or a 128-bit memory location or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded
but the upper 64 bits are ignored.
VEX.128 encoded version: The destination and first source operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed. The count operand can be either an XMM register or a 128-bit memory loca-
tion or an 8-bit immediate. If the count operand is a memory address, 128 bits are loaded but the upper 64 bits are
ignored.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit
immediate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.



EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /4, EVEX.128.66.0F 71-73 /4),
VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation
PSRAW (with 64-bit operand)
   IF (COUNT > 15)
        THEN COUNT <- 16;
   FI;
   DEST[15:0] <- SignExtend(DEST[15:0] >> COUNT);
   (* Repeat shift operation for 2nd and 3rd words *)
   DEST[63:48] <- SignExtend(DEST[63:48] >> COUNT);


PSRAD (with 64-bit operand)
   IF (COUNT > 31)
        THEN COUNT <- 32;
   FI;
   DEST[31:0] <- SignExtend(DEST[31:0] >> COUNT);
   DEST[63:32] <- SignExtend(DEST[63:32] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[31:0] <- SignBit
ELSE
    DEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);
FI;

ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[63:0] <- SignBit
ELSE
    DEST[63:0] <- SignExtend(SRC[63:0] >> COUNT);
FI;

ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 15)
    THEN     COUNT <- 16;
FI;
DEST[15:0] <- SignExtend(SRC[15:0] >> COUNT);
    (* Repeat shift operation for 2nd through 15th words *)
DEST[255:240] <- SignExtend(SRC[255:240] >> COUNT);



ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 31)
    THEN     COUNT <- 32;
FI;
DEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
DEST[255:224] <- SignExtend(SRC[255:224] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC, VL)            ; VL: 128b, 256b or 512b
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 63)
    THEN     COUNT <- 64;
FI;
DEST[63:0] <- SignExtend(SRC[63:0] >> COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
DEST[VL-1:VL-64] <- SignExtend(SRC[VL-1:VL-64] >> COUNT);



ARITHMETIC_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 15)
    THEN     COUNT <- 16;
FI;
DEST[15:0] <- SignExtend(SRC[15:0] >> COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
DEST[127:112] <- SignExtend(SRC[127:112] >> COUNT);

ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 31)
    THEN     COUNT <- 32;
FI;
DEST[31:0] <- SignExtend(SRC[31:0] >> COUNT);
    (* Repeat shift operation for 2nd through 3rd words *)
DEST[127:96] <- SignExtend(SRC[127:96] >> COUNT);





VPSRAW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRAW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
    TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VPSRAW (ymm, ymm, xmm/m128) - VEX
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <- 0

VPSRAW (ymm, imm8) - VEX
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <- 0

VPSRAW (xmm, xmm, xmm/m128) - VEX
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <- 0

VPSRAW (xmm, imm8) - VEX
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <- 0

PSRAW (xmm, xmm, xmm/m128)
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSRAW (xmm, imm8)
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

VPSRAD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+31:i] <- ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
                    ELSE DEST[i+31:i] <- ARITHMETIC_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRAD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
    TMP_DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)



FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRAD (ymm, ymm, xmm/m128) - VEX
DEST[255:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <- 0

VPSRAD (ymm, imm8) - VEX
DEST[255:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <- 0

VPSRAD (xmm, xmm, xmm/m128) - VEX
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSRAD (xmm, imm8) - VEX
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSRAD (xmm, xmm, xmm/m128)
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSRAD (xmm, imm8)
DEST[127:0] <-ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

VPSRAQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+63:i] <- ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
                    ELSE DEST[i+63:i] <- ARITHMETIC_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0



          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRAQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_DEST[VL-1:0] <- ARITHMETIC_RIGHT_SHIFT_QWORDS(SRC1[VL-1:0], SRC2, VL)

FOR j <- 0 TO 7
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPSRAD __m512i _mm512_srai_epi32(__m512i a, unsigned int imm);
VPSRAD __m512i _mm512_mask_srai_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSRAD __m512i _mm512_maskz_srai_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSRAD __m256i _mm256_mask_srai_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRAD __m256i _mm256_maskz_srai_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSRAD __m128i _mm_mask_srai_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAD __m128i _mm_maskz_srai_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSRAD __m512i _mm512_sra_epi32(__m512i a, __m128i cnt);
VPSRAD __m512i _mm512_mask_sra_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRAD __m512i _mm512_maskz_sra_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSRAD __m256i _mm256_mask_sra_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAD __m256i _mm256_maskz_sra_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRAD __m128i _mm_mask_sra_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAD __m128i _mm_maskz_sra_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRAQ __m512i _mm512_srai_epi64(__m512i a, unsigned int imm);
VPSRAQ __m512i _mm512_mask_srai_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m512i _mm512_maskz_srai_epi64( __mmask8 k, __m512i a, unsigned int imm)
VPSRAQ __m256i _mm256_mask_srai_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m256i _mm256_maskz_srai_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSRAQ __m128i _mm_mask_srai_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAQ __m128i _mm_maskz_srai_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSRAQ __m512i _mm512_sra_epi64(__m512i a, __m128i cnt);
VPSRAQ __m512i _mm512_mask_sra_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt)
VPSRAQ __m512i _mm512_maskz_sra_epi64( __mmask8 k, __m512i a, __m128i cnt)
VPSRAQ __m256i _mm256_mask_sra_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAQ __m256i _mm256_maskz_sra_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSRAQ __m128i _mm_mask_sra_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAQ __m128i _mm_maskz_sra_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRAW __m512i _mm512_srai_epi16(__m512i a, unsigned int imm);
VPSRAW __m512i _mm512_mask_srai_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);



VPSRAW __m512i _mm512_maskz_srai_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSRAW __m256i _mm256_mask_srai_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSRAW __m256i _mm256_maskz_srai_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSRAW __m128i _mm_mask_srai_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRAW __m128i _mm_maskz_srai_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSRAW __m512i _mm512_sra_epi16(__m512i a, __m128i cnt);
VPSRAW __m512i _mm512_mask_sra_epi16(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRAW __m512i _mm512_maskz_sra_epi16( __mmask16 k, __m512i a, __m128i cnt);
VPSRAW __m256i _mm256_mask_sra_epi16(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m256i _mm256_maskz_sra_epi16( __mmask8 k, __m256i a, __m128i cnt);
VPSRAW __m128i _mm_mask_sra_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRAW __m128i _mm_maskz_sra_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRAW:__m64 _mm_srai_pi16 (__m64 m, int count)
PSRAW:__m64 _mm_sra_pi16 (__m64 m, __m64 count)
(V)PSRAW:__m128i _mm_srai_epi16(__m128i m, int count)
(V)PSRAW:__m128i _mm_sra_epi16(__m128i m, __m128i count)
VPSRAW:__m256i _mm256_srai_epi16 (__m256i m, int count)
VPSRAW:__m256i _mm256_sra_epi16 (__m256i m, __m128i count)
PSRAD:__m64 _mm_srai_pi32 (__m64 m, int count)
PSRAD:__m64 _mm_sra_pi32 (__m64 m, __m64 count)
(V)PSRAD:__m128i _mm_srai_epi32 (__m128i m, int count)
(V)PSRAD:__m128i _mm_sra_epi32 (__m128i m, __m128i count)
VPSRAD:__m256i _mm256_srai_epi32 (__m256i m, int count)
VPSRAD:__m256i _mm256_sra_epi32 (__m256i m, __m128i count)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
VEX-encoded instructions:
    Syntax with RM/RVM operand encoding, see Exceptions Type 4.
    Syntax with MI/VMI operand encoding, see Exceptions Type 7.


EVEX-encoded VPSRAW, see Exceptions Type E4NF.nb.


EVEX-encoded VPSRAD/Q:
    Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
    Syntax with FVI operand encoding, see Exceptions Type E4.






