# instructions

platform: x86
mnem: MOVNTQ
description:
MOVNTQ - Store of Quadword Using Non-Temporal Hint:
| Opcode  | Instruction   | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                   
| 0F E7 /r| MOVNTQ m64, mm| MR   | Valid      | Valid          | Move quadword from mm to m64 using nontemporal
|         |               |      |            |                | hint.                                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
Moves the quadword in the source operand (second operand) to the destination
operand (first operand) using a non-temporal hint to minimize cache pollution
during the write to memory. The source operand is an MMX technology register,
which is assumed to contain packed integer data (packed bytes, words, or doublewords).
The destination operand is a 64-bit memory location.

The non-temporal hint is implemented by using a write combining (WC) memory
type protocol when writing the data to memory. Using this protocol, the processor
does not write the data into the cache hierarchy, nor does it fetch the corresponding
cache line from memory into the cache hierarchy. The memory type of the region
being written to can override the non-temporal hint, if the memory address specified
for the non-temporal store is in an uncacheable (UC) or write protected (WP)
memory region. For more information on non-temporal stores, see “Caching of
Temporal vs. Non-Temporal Data” in Chapter 10 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.

Because the WC protocol uses a weakly-ordered memory consistency model, a fencing
operation implemented with the SFENCE or MFENCE instruction should be used in
conjunction with MOVNTQ instructions if multiple processors might use different
memory types to read/write the destination memory locations.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DEST <- SRC;

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVNTQ:| void _mm_stream_pi(__m64 * p, __m64
|        | a)                                 

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without
FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


platform: x86
mnem: MOVQ
description:
MOVQ - Move Quadword:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                           
| 0F 6F /r MOVQ mm, mm/m64               | RM   | V/V           | MMX               | Move quadword from mm/m64 to mm.      
| 0F 7F /r MOVQ mm/m64, mm               | MR   | V/V           | MMX               | Move quadword from mm to mm/m64.      
| F3 0F 7E /r MOVQ xmm1, xmm2/m64        | RM   | V/V           | SSE2              | Move quadword from xmm2/mem64 to xmm1.
| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1,    | RM   | V/V           | AVX               | Move quadword from xmm2 to xmm1.      
| xmm2                                   |      |               |                   |                                       
| VEX.128.F3.0F.WIG 7E /r VMOVQ xmm1,    | RM   | V/V           | AVX               | Load quadword from m64 to xmm1.       
| m64                                    |      |               |                   |                                       
| 66 0F D6 /r MOVQ xmm2/m64, xmm1        | MR   | V/V           | SSE2              | Move quadword from xmm1 to xmm2/mem64.
| VEX.128.66.0F.WIG D6 /r VMOVQ xmm1/m64,| MR   | V/V           | AVX               | Move quadword from xmm2 register to   
| xmm2                                   |      |               |                   | xmm1/m64.                             

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
Copies a quadword from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be MMX technology
registers, XMM registers, or 64-bit memory locations. This instruction can be
used to move a quadword between two MMX technology registers or between an MMX
technology register and a 64-bit memory location, or to move data between two
XMM registers or between an XMM register and a 64-bit memory location. The instruction
cannot be used to transfer data between memory locations.

When the source operand is an XMM register, the low quadword is moved; when
the destination operand is an XMM register, the quadword is stored to the low
quadword of the register, and the high quadword is cleared to all 0s.

In 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Note: In VEX.128.66.0F D6 instruction
version, VEX.vvvv and VEX.L=1 are reserved and the former must be 1111b otherwise
instructions will #UD. Note: In VEX.128.F3.0F 7E version, VEX.vvvv and VEX.L=1
are reserved and the former must be 1111b, otherwise instructions will #UD.

Operation:

MOVQ instruction when operating on MMX technology registers and memory locations:
  DEST <- SRC;
MOVQ instruction when source and destination operands are XMM registers:
  DEST[63:0] <- SRC[63:0];
  DEST[127:64] <- 0000000000000000H;
MOVQ instruction when source operand is XMM register and destination
operand is memory location:
  DEST <- SRC[63:0];
MOVQ instruction when source operand is memory location and destination
operand is XMM register:
  DEST[63:0] <- SRC;
  DEST[127:64] <- 0000000000000000H;
VMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0
VMOVQ (VEX.128.66.0F D6) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0
VMOVQ (7E) with memory source:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0
VMOVQ (D6) with memory dest:
DEST[63:0] <- SRC2[63:0]

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| MOVQ:| m128i _mm_mov_epi64(__m128i a)

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without
FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B.


platform: x86
mnem: MOVQ2DQ
description:
MOVQ2DQ - Move Quadword from MMX Technology to XMM Register:
| Opcode     | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| F3 0F D6 /r| MOVQ2DQ xmm, mm| RM   | Valid      | Valid          | Move quadword from mmx to low quadword
|            |                |      |            |                | of xmm.                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Moves the quadword from the source operand (second operand) to the low quadword
of the destination operand (first operand). The source operand is an MMX technology
register and the destination operand is an XMM register.

This instruction causes a transition from x87 FPU to MMX technology operation
(that is, the x87 FPU top-of-stack pointer is set to 0 and the x87 FPU tag word
is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the MOVQ2DQ
instruction is executed.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation:

DEST[63:0] <- SRC[63:0];
DEST[127:64] <- 00000000000000000H;

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVQ2DQ:| __128i _mm_movpi64_pi64 ( __m64 a)

SIMD Floating-Point Exceptions:
None.


Protected Mode Exceptions:
| #NM| If CR0.TS[bit 3] = 1.                   
| #UD| If CR0.EM[bit 2] = 1. If CR4.OSFXSR[bit 
|    | 9] = 0. If CPUID.01H:EDX.SSE2[bit 26]   
|    | = 0. If the LOCK prefix is used.        
| #MF| If there is a pending x87 FPU exception.

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: MOVS
description:
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String:
\

| Opcode    | Instruction  | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                
| A4        | MOVS m8, m8  | NP   | Valid      | Valid          | For legacy mode, Move byte from address    
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move byte from address (R|E)SI to (R|E)DI. 
| A5        | MOVS m16, m16| NP   | Valid      | Valid          | For legacy mode, move word from address    
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move word at address (R|E)SI to (R|E)DI.   
| A5        | MOVS m32, m32| NP   | Valid      | Valid          | For legacy mode, move dword from address   
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move dword from address (R|E)SI to (R|E)DI.
| REX.W + A5| MOVS m64, m64| NP   | Valid      | N.E.           | Move qword from address (R|E)SI to (R|E)DI.
| A4        | MOVSB        | NP   | Valid      | Valid          | For legacy mode, Move byte from address    
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move byte from address (R|E)SI to (R|E)DI. 
| A5        | MOVSW        | NP   | Valid      | Valid          | For legacy mode, move word from address    
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move word at address (R|E)SI to (R|E)DI.   
| A5        | MOVSD        | NP   | Valid      | Valid          | For legacy mode, move dword from address   
|           |              |      |            |                | DS:(E)SI to ES:(E)DI. For 64-bit mode      
|           |              |      |            |                | move dword from address (R|E)SI to (R|E)DI.
| REX.W + A5| MOVSQ        | NP   | Valid      | N.E.           | Move qword from address (R|E)SI to (R|E)DI.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Moves the byte, word, or doubleword specified with the second operand (source
operand) to the location specified with the first operand (destination operand).
Both the source and destination operands are located in memory. The address
of the source operand is read from the DS:ESI or the DS:SI registers (depending
on the address-size attribute of the instruction, 32 or 16, respectively). The
address of the destination operand is read from the ES:EDI or the ES:DI registers
(again depending on the address-size attribute of the instruction). The DS segment
may be overridden with a segment override prefix, but the ES segment cannot
be overridden.

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands”
form and the “nooperands” form. The explicit-operands form (specified with the
MOVS mnemonic) allows the source and destination operands to be specified explicitly.
Here, the source and destination operands should be symbols that indicate the
size and location of the source value and the destination, respectively. This
explicit-operands form is provided to allow documentation; however, note that
the documentation provided by this form can be misleading. That is, the source
and destination operand symbols must specify the correct type (size) of the
operands (bytes, words, or doublewords), but they do not have to specify the
correct location. The locations of the source and destination operands are always
specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly
before the move string instruction is executed.

The no-operands form provides “short forms” of the byte, word, and doubleword
versions of the MOVS instructions. Here also DS:(E)SI and ES:(E)DI are assumed
to be the source and destination operands, respectively. The size of the source
and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW
(word move), or MOVSD (doubleword move).

After the move operation, the (E)SI and (E)DI registers are incremented or decremented
automatically according to the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E)SI and (E)DI register are incre-

mented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.)
The registers are incremented or decremented by 1 for byte operations, by 2
for word operations, or by 4 for doubleword operations.


NOTE:
To improve performance, more recent processors support modifications to the
processor's operation during the string store operations initiated with MOVS
and MOVSB. See Section 7.3.9.3 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 for additional information on fast-string operation.

The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix
(see “REP/REPE/REPZ /REPNE/REPNZ - Repeat String Operation Prefix” in Chapter
4 of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
2B, for a description of the REP prefix) for block moves of ECX bytes, words,
or doublewords.

In 64-bit mode, the instruction's default address size is 64 bits, 32-bit address
size is supported using the prefix 67H. The 64-bit addresses are specified by
RSI and RDI; 32-bit address are specified by ESI and EDI. Use of the REX.W prefix
promotes doubleword operation to 64 bits. See the summary chart at the beginning
of this section for encoding data and limits.

Operation:

DEST <- SRC;
Non-64-bit Mode:
IF (Byte move)
  THEN IF DF = 0
     THEN
       (E)SI <- (E)SI + 1;
       (E)DI <- (E)DI + 1;
     ELSE
       (E)SI <- (E)SI - 1;
       (E)DI <- (E)DI - 1;
     FI;
  ELSE IF (Word move)
     THEN IF DF = 0
       (E)SI <- (E)SI + 2;
       (E)DI <- (E)DI + 2;
       FI;
     ELSE
       (E)SI <- (E)SI - 2;
       (E)DI <- (E)DI - 2;
     FI;
  ELSE IF (Doubleword move)
     THEN IF DF = 0
       (E)SI <- (E)SI + 4;
       (E)DI <- (E)DI + 4;
       FI;
     ELSE
       (E)SI <- (E)SI - 4;
       (E)DI <- (E)DI - 4;
     FI;
FI;
64-bit Mode:
IF (Byte move)
  THEN IF DF = 0
     THEN
       (R|E)SI <- (R|E)SI + 1;
       (R|E)DI <- (R|E)DI + 1;
     ELSE
       (R|E)SI <- (R|E)SI - 1;
       (R|E)DI <- (R|E)DI - 1;
     FI;
  ELSE IF (Word move)
     THEN IF DF = 0
       (R|E)SI <- (R|E)SI + 2;
       (R|E)DI <- (R|E)DI + 2;
       FI;
     ELSE
       (R|E)SI <- (R|E)SI - 2;
       (R|E)DI <- (R|E)DI - 2;
     FI;
  ELSE IF (Doubleword move)
     THEN IF DF = 0
       (R|E)SI <- (R|E)SI + 4;
       (R|E)DI <- (R|E)DI + 4;
       FI;
     ELSE
       (R|E)SI <- (R|E)SI - 4;
       (R|E)DI <- (R|E)DI - 4;
     FI;
  ELSE IF (Quadword move)
     THEN IF DF = 0
       (R|E)SI <- (R|E)SI + 8;
       (R|E)DI <- (R|E)DI + 8;
       FI;
     ELSE
       (R|E)SI <- (R|E)SI - 8;
       (R|E)DI <- (R|E)DI - 8;
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: MOVSD
description:
MOVSD - Move Scalar Double-Precision Floating-Point Value:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F2 0F 10 /r MOVSD xmm1, xmm2/m64        | RM   | V/V           | SSE2              | Move scalar double-precision floating-point 
|                                         |      |               |                   | value from xmm2/m64 to xmm1 register.       
| VEX.NDS.LIG.F2.0F.WIG 10 /r VMOVSD xmm1,| RVM  | V/V           | AVX               | Merge scalar double-precision floating-point
| xmm2, xmm3                              |      |               |                   | value from xmm2 and xmm3 to xmm1 register.  
| VEX.LIG.F2.0F.WIG 10 /r VMOVSD xmm1,    | XM   | V/V           | AVX               | Load scalar double-precision floating-point 
| m64                                     |      |               |                   | value from m64 to xmm1 register.            
| F2 0F 11 /r MOVSD xmm2/m64, xmm1        | MR   | V/V           | SSE2              | Move scalar double-precision floating-point 
|                                         |      |               |                   | value from xmm1 register to xmm2/m64.       
| VEX.NDS.LIG.F2.0F.WIG 11 /r VMOVSD xmm1,| MVR  | V/V           | AVX               | Merge scalar double-precision floating-point
| xmm2, xmm3                              |      |               |                   | value from xmm2 and xmm3 registers to       
|                                         |      |               |                   | xmm1.                                       
| VEX.LIG.F2.0F.WIG 11 /r VMOVSD m64,     | MR   | V/V           | AVX               | Move scalar double-precision floating-point 
| xmm1                                    |      |               |                   | value from xmm1 register to m64.            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA           | NA       
| XM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| MVR  | ModRM:r/m (w)| VEX.vvvv (r) | ModRM:reg (r)| NA       

Description:
MOVSD moves a scalar double-precision floating-point value from the source operand
(second operand) to the destination operand (first operand). The source and
destination operands can be XMM registers or 64-bit memory locations. This instruction
can be used to move a double-precision floating-point value to and from the
low quadword of an XMM register and a 64-bit memory location, or to move a double-precision
floating-point value between the low quadwords of two XMM registers. The instruction
cannot be used to transfer data between memory locations. For non-VEX encoded
instruction syntax and when the source and destination operands are XMM registers,
the high quadword of the destination operand remains unchanged. When the source
operand is a memory location and destination operand is an XMM registers, the
high quadword of the destination operand is cleared to all 0s.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). Note: For the “VMOVSD m64, xmm1” (memory store form)
instruction version, VEX.vvvv is reserved and must be 1111b, otherwise instruction
will #UD. Note: For the “VMOVSD xmm1, m64” (memory load form) instruction version,
VEX.vvvv is reserved and must be 1111b otherwise instruction will #UD. VEX encoded
instruction syntax supports two source operands and a destination operand if
ModR/M.mod field is 11B. VEX.vvvv is used to encode the first source operand
(the second operand). The low 128 bits of the destination operand stores the
result of merging the low quadword of the second source operand with the quad
word in bits 127:64 of the first source operand. The upper bits of the destination
operand are cleared.

Operation:

MOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] (Unmodified)
MOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)
DEST[63:0] <- SRC[63:0]
MOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)
DEST[63:0] <- SRC[63:0]
DEST[127:64] <- 0
DEST[VLMAX-1:128] (Unmodified)
VMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] <- SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0
VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] <- SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0
VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVSD:| __m128d _mm_load_sd (double *p)         
| MOVSD:| void _mm_store_sd (double *p, __m128d   
|       | a)                                      
| MOVSD:| __m128d _mm_store_sd (__m128d a, __m128d
|       | b)                                      

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: MOVSHDUP
description:
MOVSHDUP - Move Packed Single-FP High and Duplicate:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                   
| F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128   | RM   | V/V           | SSE3              | Move two single-precision floating-point      
|                                        |      |               |                   | values from the higher 32-bit operand         
|                                        |      |               |                   | of each qword in xmm2/m128 to xmm1 and        
|                                        |      |               |                   | duplicate each 32-bit operand to the          
|                                        |      |               |                   | lower 32-bits of each qword.                  
| VEX.128.F3.0F.WIG 16 /r VMOVSHDUP xmm1,| RM   | V/V           | AVX               | Move odd index single-precision floating-point
| xmm2/m128                              |      |               |                   | values from xmm2/mem and duplicate each       
|                                        |      |               |                   | element into xmm1.                            
| VEX.256.F3.0F.WIG 16 /r VMOVSHDUP ymm1,| RM   | V/V           | AVX               | Move odd index single-precision floating-point
| ymm2/m256                              |      |               |                   | values from ymm2/mem and duplicate each       
|                                        |      |               |                   | element into ymm1.                            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
The linear address corresponds to the address of the least-significant byte
of the referenced memory data. When a memory address is indicated, the 16 bytes
of data at memory location m128 are loaded and the single-precision elements
in positions 1 and 3 are duplicated. When the register-register form of this
operation is used, the same operation is performed but with data coming from
the 128-bit source register. See Figure 3-25.

MOVSHDUP xmm1, xmm2/m128

xmm2/

| [127:96]xmm2/| [95:64]xmm1[95:64]xmm2/m128[127:96]| [63:32]xmm1[63:32]xmm2/m128[63:32]| [31:0]m128 xmm1[31:0]RESULT: xmm2/xmm1
|              |                                    |                                   | m128[63:32]                           
| [127:96]     | [95:64]                            | [63:32]                           | [31:0]                                
OM15998

| Figure 3-25.| MOVSHDUP - Move Packed Single-FP High
|             | and Duplicate                      
In 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: Bits
(VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register
are zeroed. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be
1111b otherwise instructions will #UD.

Operation:

MOVSHDUP (128-bit Legacy SSE version)
DEST[31:0] <- SRC[63:32]
DEST[63:32] <- SRC[63:32]
DEST[95:64] <- SRC[127:96]
DEST[127:96] <- SRC[127:96]
DEST[VLMAX-1:128] (Unmodified)
VMOVSHDUP (VEX.128 encoded version)
DEST[31:0] <- SRC[63:32]
DEST[63:32] <- SRC[63:32]
DEST[95:64] <- SRC[127:96]
DEST[127:96] <- SRC[127:96]
DEST[VLMAX-1:128] <- 0
VMOVSHDUP (VEX.256 encoded version)
DEST[31:0] <- SRC[63:32]
DEST[63:32] <- SRC[63:32]
DEST[95:64] <- SRC[127:96]
DEST[127:96] <- SRC[127:96]
DEST[159:128] <- SRC[191:160]
DEST[191:160] <- SRC[191:160]
DEST[223:192] <- SRC[255:224]
DEST[255:224] <- SRC[255:224]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)MOVSHDUP:| __m128 _mm_movehdup_ps(__m128 a)     
| VMOVSHDUP:  | __m256 _mm256_movehdup_ps (__m256 a);

Exceptions:
General protection exception if not aligned on 16-byte boundary, regardless
of segment.


Numeric Exceptions:
None


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: MOVSLDUP
description:
MOVSLDUP - Move Packed Single-FP Low and Duplicate:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                   
| F3 0F 12 /r MOVSLDUP xmm1, xmm2/m128   | RM   | V/V           | SSE3              | Move two single-precision floating-point      
|                                        |      |               |                   | values from the lower 32-bit operand          
|                                        |      |               |                   | of each qword in xmm2/m128 to xmm1 and        
|                                        |      |               |                   | duplicate each 32-bit operand to the          
|                                        |      |               |                   | higher 32-bits of each qword.                 
| VEX.128.F3.0F.WIG 12 /r VMOVSLDUP xmm1,| RM   | V/V           | AVX               | Move even index single-precision floatingpoint
| xmm2/m128                              |      |               |                   | values from xmm2/mem and duplicate each       
|                                        |      |               |                   | element into xmm1.                            
| VEX.256.F3.0F.WIG 12 /r VMOVSLDUP ymm1,| RM   | V/V           | AVX               | Move even index single-precision floatingpoint
| ymm2/m256                              |      |               |                   | values from ymm2/mem and duplicate each       
|                                        |      |               |                   | element into ymm1.                            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
The linear address corresponds to the address of the least-significant byte
of the referenced memory data. When a memory address is indicated, the 16 bytes
of data at memory location m128 are loaded and the single-precision elements
in positions 0 and 2 are duplicated. When the register-register form of this
operation is used, the same operation is performed but with data coming from
the 128-bit source register.

See Figure 3-26.

MOVSLDUP xmm1, xmm2/m128

xmm2/

| [127:96]xmm2/| [95:64]xmm1[95:64]xmm2/m128[95:64]| [63:32]xmm1[63:32]xmm2/m128[31:0]| [31:0]m128 xmm1[31:0]RESULT: xmm2/xmm1
|              |                                   |                                  | m128[31:0]                            
| [127:96]     | [95:64]                           | [63:32]                          | [31:0]                                
OM15999

| Figure 3-26.| MOVSLDUP - Move Packed Single-FP Low and
|             | Duplicate                             
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: Bits (VLMAX-1:128) of the
corresponding YMM destination register remain unchanged. VEX.128 encoded version:
Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise
instructions will #UD.

Operation:

MOVSLDUP (128-bit Legacy SSE version)
DEST[31:0] <- SRC[31:0]
DEST[63:32] <- SRC[31:0]
DEST[95:64] <- SRC[95:64]
DEST[127:96] <- SRC[95:64]
DEST[VLMAX-1:128] (Unmodified)
VMOVSLDUP (VEX.128 encoded version)
DEST[31:0] <- SRC[31:0]
DEST[63:32] <- SRC[31:0]
DEST[95:64] <- SRC[95:64]
DEST[127:96] <- SRC[95:64]
DEST[VLMAX-1:128] <- 0
VMOVSLDUP (VEX.256 encoded version)
DEST[31:0] <- SRC[31:0]
DEST[63:32] <- SRC[31:0]
DEST[95:64] <- SRC[95:64]
DEST[127:96] <- SRC[95:64]
DEST[159:128] <- SRC[159:128]
DEST[191:160] <- SRC[159:128]
DEST[223:192] <- SRC[223:192]
DEST[255:224] <- SRC[223:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)MOVSLDUP:| __m128 _mm_moveldup_ps(__m128 a)     
| VMOVSLDUP:  | __m256 _mm256_moveldup_ps (__m256 a);

Exceptions:
General protection exception if not aligned on 16-byte boundary, regardless
of segment.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: MOVSS
description:
MOVSS - Move Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                 
| F3 0F 10 /r MOVSS xmm1, xmm2/m32        | RM   | V/V           | SSE               | Move scalar single-precision floating-point 
|                                         |      |               |                   | value from xmm2/m32 to xmm1 register.       
| VEX.NDS.LIG.F3.0F.WIG 10 /r VMOVSS xmm1,| RVM  | V/V           | AVX               | Merge scalar single-precision floating-point
| xmm2, xmm3                              |      |               |                   | value from xmm2 and xmm3 to xmm1 register.  
| VEX.LIG.F3.0F.WIG 10 /r VMOVSS xmm1,    | XM   | V/V           | AVX               | Load scalar single-precision floating-point 
| m32                                     |      |               |                   | value from m32 to xmm1 register.            
| F3 0F 11 /r MOVSS xmm2/m32, xmm         | MR   | V/V           | SSE               | Move scalar single-precision floating-point 
|                                         |      |               |                   | value from xmm1 register to xmm2/m32.       
| VEX.NDS.LIG.F3.0F.WIG 11 /r VMOVSS xmm1,| MVR  | V/V           | AVX               | Move scalar single-precision floating-point 
| xmm2, xmm3                              |      |               |                   | value from xmm2 and xmm3 to xmm1 register.  
| VEX.LIG.F3.0F.WIG 11 /r VMOVSS m32,     | MR   | V/V           | AVX               | Move scalar single-precision floating-point 
| xmm1                                    |      |               |                   | value from xmm1 register to m32.            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA           | NA       
| XM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| MVR  | ModRM:r/m (w)| VEX.vvvv (r) | ModRM:reg (r)| NA       

Description:
Moves a scalar single-precision floating-point value from the source operand
(second operand) to the destination operand (first operand). The source and
destination operands can be XMM registers or 32-bit memory locations. This instruction
can be used to move a single-precision floating-point value to and from the
low doubleword of an XMM register and a 32-bit memory location, or to move a
single-precision floating-point value between the low doublewords of two XMM
registers. The instruction cannot be used to transfer data between memory locations.
For non-VEX encoded syntax and when the source and destination operands are
XMM registers, the high doublewords of the destination operand remains unchanged.
When the source operand is a memory location and destination operand is an XMM
registers, the high doublewords of the destination operand is cleared to all
0s.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). VEX encoded instruction syntax supports two source operands
and a destination operand if ModR/M.mod field is 11B. VEX.vvvv is used to encode
the first source operand (the second operand). The low 128 bits of the destination
operand stores the result of merging the low dword of the second source operand
with three dwords in bits 127:32 of the first source operand. The upper bits
of the destination operand are cleared. Note: For the “VMOVSS m32, xmm1” (memory
store form) instruction version, VEX.vvvv is reserved and must be 1111b otherwise
instruction will #UD. Note: For the “VMOVSS xmm1, m32” (memory load form) instruction
version, VEX.vvvv is reserved and must be 1111b otherwise instruction will #UD.

Operation:

MOVSS (Legacy SSE version when the source and destination operands are both XMM registers)
DEST[31:0] <- SRC[31:0]
DEST[VLMAX-1:32] (Unmodified)
MOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)
DEST[31:0] <- SRC[31:0]
MOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)
DEST[31:0] <- SRC[31:0]
DEST[127:32] <- 0
DEST[VLMAX-1:128] (Unmodified)
VMOVSS (VEX.NDS.128.F3.0F 11 /r where the destination is an XMM register)
DEST[31:0] <- SRC2[31:0]
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0
VMOVSS (VEX.NDS.128.F3.0F 10 /r where the source and destination are XMM registers)
DEST[31:0] <- SRC2[31:0]
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0
VMOVSS (VEX.NDS.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)
DEST[31:0] <- SRC[31:0]
DEST[VLMAX-1:32] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVSS:| __m128 _mm_load_ss(float * p)      
| MOVSS:| void _mm_store_ss(float * p, __m128
|       | a)                                 
| MOVSS:| __m128 _mm_move_ss(__m128 a, __m128
|       | b)                                 

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: MOVSX
description:
MOVSX/MOVSXD - Move with Sign-Extension:
| Opcode          | Instruction      | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                    
| 0F BE /r        | MOVSX r16, r/m8  | RM   | Valid      | Valid          | Move byte to word with sign-extension.         
| 0F BE /r        | MOVSX r32, r/m8  | RM   | Valid      | Valid          | Move byte to doubleword with signextension.    
| REX + 0F BE /r  | MOVSX r64, r/m8* | RM   | Valid      | N.E.           | Move byte to quadword with sign-extension.     
| 0F BF /r        | MOVSX r32, r/m16 | RM   | Valid      | Valid          | Move word to doubleword, with signextension.   
| REX.W + 0F BF /r| MOVSX r64, r/m16 | RM   | Valid      | N.E.           | Move word to quadword with sign-extension.     
| REX.W** + 63 /r | MOVSXD r64, r/m32| RM   | Valid      | N.E.           | Move doubleword to quadword with signextension.
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH. ** The use of MOVSXD without
REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using
MOVSXD without REX.W.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Copies the contents of the source operand (register or memory location) to the
destination operand (register) and sign extends the value to 16 or 32 bits (see
Figure 7-6 in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1). The size of the converted value depends on the operand-size attribute.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits. See the summary chart at the beginning
of this section for encoding data and limits.

Operation:

DEST <- SignExtend(SRC);

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit.                       
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #UD            | If the LOCK prefix is used.          

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: MOVUPD
description:
MOVUPD - Move Unaligned Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 66 0F 10 /r MOVUPD xmm1, xmm2/m128        | RM   | V/V           | SSE2              | Move packed double-precision floating-point
|                                           |      |               |                   | values from xmm2/m128 to xmm1.             
| VEX.128.66.0F.WIG 10 /r VMOVUPD xmm1,     | RM   | V/V           | AVX               | Move unaligned packed double-precision     
| xmm2/m128                                 |      |               |                   | floating-point from xmm2/mem to xmm1.      
| VEX.256.66.0F.WIG 10 /r VMOVUPD ymm1,     | RM   | V/V           | AVX               | Move unaligned packed double-precision     
| ymm2/m256                                 |      |               |                   | floating-point from ymm2/mem to ymm1.      
| 66 0F 11 /r MOVUPD xmm2/m128, xmm         | MR   | V/V           | SSE2              | Move packed double-precision floating-point
|                                           |      |               |                   | values from xmm1 to xmm2/m128.             
| VEX.128.66.0F.WIG 11 /r VMOVUPD xmm2/m128,| MR   | V/V           | AVX               | Move unaligned packed double-precision     
| xmm1                                      |      |               |                   | floating-point from xmm1 to xmm2/mem.      
| VEX.256.66.0F.WIG 11 /r VMOVUPD ymm2/m256,| MR   | V/V           | AVX               | Move unaligned packed double-precision     
| ymm1                                      |      |               |                   | floating-point from ymm1 to ymm2/mem.      

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
128-bit versions:

Moves a double quadword containing two packed double-precision floating-point
values from the source operand (second operand) to the destination operand (first
operand). This instruction can be used to load an XMM register from a 128-bit
memory location, store the contents of an XMM register into a 128-bit memory
location, or move data between two XMM registers.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: Bits (VLMAX-1:128) of the
corresponding YMM destination register remain unchanged.

When the source or destination operand is a memory operand, the operand may
be unaligned on a 16-byte boundary without causing a general-protection exception
(#GP) to be generated.1

To move double-precision floating-point values to and from memory locations
that are known to be aligned on 16byte boundaries, use the MOVAPD instruction.

While executing in 16-bit addressing mode, a linear address for a 128-bit data
access that overlaps the end of a 16bit segment is not allowed and is defined
as reserved behavior. A specific processor implementation may or may not generate
a general-protection exception (#GP) in this situation, and the address that
spans the end of the segment may or may not wrap around to the beginning of
the segment. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: Moves 256 bits of packed double-precision
floating-point values from the source operand (second operand) to the destination
operand (first operand). This instruction can be used to load a YMM register
from a 256-bit memory location, to store the contents of a YMM register into
a 256-bit memory location, or to move data between two YMM registers.

| 1.| If alignment checking is enabled (CR0.AM  
|   | = 1, RFLAGS.AC = 1, and CPL = 3), an      
|   | alignment-check exception (#AC) may       
|   | or may not be generated (depending on     
|   | processor implementation) when the operand
|   | is not aligned on an 8-byte boundary.     
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise
instructions will #UD.

Operation:

MOVUPD (128-bit load and register-copy form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] (Unmodified)
(V)MOVUPD (128-bit store form)
DEST[127:0] <- SRC[127:0]
VMOVUPD (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] <- 0
VMOVUPD (VEX.256 encoded version)
DEST[255:0] <- SRC[255:0]

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVUPD: | __m128 _mm_loadu_pd(double * p)       
| MOVUPD: | void _mm_storeu_pd(double *p, __m128  
|         | a)                                    
| VMOVUPD:| __m256d _mm256_loadu_pd (__m256d * p);
| VMOVUPD:| _mm256_storeu_pd(_m256d *p, __m256d   
|         | a);                                   

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4 Note treatment of #AC varies; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: MOVUPS
description:
MOVUPS - Move Unaligned Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                
| 0F 10 /r MOVUPS xmm1, xmm2/m128             | RM   | V/V           | SSE               | Move packed single-precision floating-point
|                                             |      |               |                   | values from xmm2/m128 to xmm1.             
| VEX.128.0F.WIG 10 /r VMOVUPS xmm1, xmm2/m128| RM   | V/V           | AVX               | Move unaligned packed single-precision     
|                                             |      |               |                   | floating-point from xmm2/mem to xmm1.      
| VEX.256.0F.WIG 10 /r VMOVUPS ymm1, ymm2/m256| RM   | V/V           | AVX               | Move unaligned packed single-precision     
|                                             |      |               |                   | floating-point from ymm2/mem to ymm1.      
| 0F 11 /r MOVUPS xmm2/m128, xmm1             | MR   | V/V           | SSE               | Move packed single-precision floating-point
|                                             |      |               |                   | values from xmm1 to xmm2/m128.             
| VEX.128.0F.WIG 11 /r VMOVUPS xmm2/m128,     | MR   | V/V           | AVX               | Move unaligned packed single-precision     
| xmm1                                        |      |               |                   | floating-point from xmm1 to xmm2/mem.      
| VEX.256.0F.WIG 11 /r VMOVUPS ymm2/m256,     | MR   | V/V           | AVX               | Move unaligned packed single-precision     
| ymm1                                        |      |               |                   | floating-point from ymm1 to ymm2/mem.      

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
128-bit versions: Moves a double quadword containing four packed single-precision
floating-point values from the source operand (second operand) to the destination
operand (first operand). This instruction can be used to load an XMM register
from a 128-bit memory location, store the contents of an XMM register into a
128-bit memory location, or move data between two XMM registers.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: Bits (VLMAX-1:128) of the
corresponding YMM destination register remain unchanged.

When the source or destination operand is a memory operand, the operand may
be unaligned on a 16-byte boundary without causing a general-protection exception
(#GP) to be generated.1

To move packed single-precision floating-point values to and from memory locations
that are known to be aligned on 16-byte boundaries, use the MOVAPS instruction.

While executing in 16-bit addressing mode, a linear address for a 128-bit data
access that overlaps the end of a 16bit segment is not allowed and is defined
as reserved behavior. A specific processor implementation may or may not generate
a general-protection exception (#GP) in this situation, and the address that
spans the end of the segment may or may not wrap around to the beginning of
the segment. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed.

VEX.256 encoded version: Moves 256 bits of packed single-precision floating-point
values from the source operand (second operand) to the destination operand (first
operand). This instruction can be used to load a YMM register from a 256-bit
memory location, to store the contents of a YMM register into a 256-bit memory
location, or to move data between two YMM registers. Note: In VEX-encoded versions,
VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

| 1.| If alignment checking is enabled (CR0.AM  
|   | = 1, RFLAGS.AC = 1, and CPL = 3), an      
|   | alignment-check exception (#AC) may       
|   | or may not be generated (depending on     
|   | processor implementation) when the operand
|   | is not aligned on an 8-byte boundary.     
Operation:

MOVUPS (128-bit load and register-copy form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] (Unmodified)
(V)MOVUPS (128-bit store form)
DEST[127:0] <- SRC[127:0]
VMOVUPS (VEX.128 encoded load-form)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] <- 0
VMOVUPS (VEX.256 encoded version)
DEST[255:0] <- SRC[255:0]

Intel C/C++ Compiler Intrinsic Equivalent:
| MOVUPS: | __m128 _mm_loadu_ps(double * p)      
| MOVUPS: | void _mm_storeu_ps(double *p, __m128 
|         | a)                                   
| VMOVUPS:| __m256 _mm256_loadu_ps (__m256 * p); 
| VMOVUPS:| _mm256_storeu_ps(_m256 *p, __m256 a);

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4 Note treatment of #AC varies; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: MOVZX
description:
MOVZX - Move with Zero-Extend:
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F B6 /r        | MOVZX r16, r/m8 | RM   | Valid      | Valid          | Move byte to word with zero-extension.  
| 0F B6 /r        | MOVZX r32, r/m8 | RM   | Valid      | Valid          | Move byte to doubleword, zero-extension.
| REX.W + 0F B6 /r| MOVZX r64, r/m8*| RM   | Valid      | N.E.           | Move byte to quadword, zero-extension.  
| 0F B7 /r        | MOVZX r32, r/m16| RM   | Valid      | Valid          | Move word to doubleword, zero-extension.
| REX.W + 0F B7 /r| MOVZX r64, r/m16| RM   | Valid      | N.E.           | Move word to quadword, zero-extension.  
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if the REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Copies the contents of the source operand (register or memory location) to the
destination operand (register) and zero extends the value. The size of the converted
value depends on the operand-size attribute.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bit operands. See the summary chart at
the beginning of this section for encoding data and limits.

Operation:

DEST <- ZeroExtend(SRC);

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: MPSADBW
description:
MPSADBW  -  Compute Multiple Packed Sums of Absolute Difference:
| Opcode/Instruction                        | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                             
| 66 0F 3A 42 /r ib MPSADBW xmm1, xmm2/m128,| RMI  | V/V           | SSE4_1            | Sums absolute 8-bit integer difference  
| imm8                                      |      |               |                   | of adjacent groups of 4 byte integers   
|                                           |      |               |                   | in xmm1 and xmm2/m128 and writes the    
|                                           |      |               |                   | results in xmm1. Starting offsets within
|                                           |      |               |                   | xmm1 and xmm2/m128 are determined by    
|                                           |      |               |                   | imm8.                                   
| VEX.NDS.128.66.0F3A.WIG 42 /r ib VMPSADBW | RVMI | V/V           | AVX               | Sums absolute 8-bit integer difference  
| xmm1, xmm2, xmm3/m128, imm8               |      |               |                   | of adjacent groups of 4 byte integers   
|                                           |      |               |                   | in xmm2 and xmm3/m128 and writes the    
|                                           |      |               |                   | results in xmm1. Starting offsets within
|                                           |      |               |                   | xmm2 and xmm3/m128 are determined by    
|                                           |      |               |                   | imm8.                                   
| VEX.NDS.256.66.0F3A.WIG 42 /r ib VMPSADBW | RVMI | V/V           | AVX2              | Sums absolute 8-bit integer difference  
| ymm1, ymm2, ymm3/m256, imm8               |      |               |                   | of adjacent groups of 4 byte integers   
|                                           |      |               |                   | in xmm2 and ymm3/m128 and writes the    
|                                           |      |               |                   | results in ymm1. Starting offsets within
|                                           |      |               |                   | ymm2 and xmm3/m128 are determined by    
|                                           |      |               |                   | imm8.                                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
(V)MPSADBW sums the absolute difference of 4 unsigned bytes (block_2) in the
second source operand with sequential groups of 4 unsigned bytes (block_1) in
the first source operand. The immediate byte provides bit fields that specify
the initial offset of block_1 within the first source operand, and the offset
of block_2 within the second source operand. The offset granularity in both
source operands are 32 bits. The sum-absolute-difference (SAD) operation is
repeated 8 times for (V)MPSADW between the same block_2 (fixed offset within
the second source operand) and a variable block_1 (offset is shifted by 8 bits
for each SAD operation) in the first source operand. Each 16-bit result of eight
SAD operations is written to the respective word in the destination operand.
128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2
within the second source operand. Imm[2]*32 specifies the initial bit offset
of the block_1 within the first source operand. The first source operand and
destination operand are the same. The first source and destination operands
are XMM registers. The second source operand is either an XMM register or a
128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. Bits 7:3 of the immediate byte are ignored. VEX.128
encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the
second source operand. Imm[2]*32 specifies the initial bit offset of the block_1
within the first source operand. The first source and destination operands are
XMM registers. The second source operand is either an XMM register or a 128-bit
memory location. Bits (127:128) of the corresponding YMM register are zeroed.
Bits 7:3 of the immediate byte are ignored. VEX.256 encoded version: The sum-absolute-difference
(SAD) operation is repeated 8 times for MPSADW between the same block_2 (fixed
offset within the second source operand) and a variable block_1 (offset is shifted
by 8 bits for each SAD operation) in the first source operand. Each 16-bit result
of eight SAD operations between block_2 and block_1 is written to the respective
word in the lower 128 bits of the destination operand. Additionally, VMPSADBW
performs another eight SAD operations on block_4 of the second source operand
and block_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the
bit offset of block_4 within the second source operand. (Imm[5]*32+128) specifies
the initial bit offset of the block_3 within the first source operand. Each
16-bit result of eight SAD operations between block_4 and block_3 is written
to the respective word in the upper 128 bits of the destination operand.

The first source operand is a YMM register. The second source register can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register. Bits 7:6 of the immediate byte are ignored. Note: If VMPSADBW is encoded
with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.

Imm[4:3]*32+128

| 255| 224| 192| 128
Src2 Abs. Diff. Imm[5]*32+128

Src1 Sum

| 255| 144| 128
Destination

Imm[1:0]*32

| 127| 96| 64| 0
Src2 Abs. Diff. Imm[2]*32

Src1 Sum

| 127| 16| 0
Destination

| Figure 3-27.| VMPSADBW Operation
Operation:

VMPSADBW (VEX.256 encoded version)
SRC2_OFFSET <- imm8[1:0]*32
SRC1_OFFSET <- imm8[2]*32
SRC1_BYTE0 <- SRC1[SRC1_OFFSET+7:SRC1_OFFSET]
SRC1_BYTE1 <- SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8]
SRC1_BYTE2 <- SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16]
SRC1_BYTE3 <- SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24]
SRC1_BYTE4 <-SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32]
SRC1_BYTE5 <- SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40]
SRC1_BYTE6 <- SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48]
SRC1_BYTE7 <- SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56]
SRC1_BYTE8 <- SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64]
SRC1_BYTE9 <- SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72]
SRC1_BYTE10 <- SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80]
SRC2_BYTE0 <-SRC2[SRC2_OFFSET+7:SRC2_OFFSET]
SRC2_BYTE1 <- SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8]
SRC2_BYTE2 <- SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16]
SRC2_BYTE3 <- SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24]
TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
SRC2_OFFSET <- imm8[4:3]*32 + 128
SRC1_OFFSET <- imm8[5]*32 + 128
SRC1_BYTE0 <- SRC1[SRC1_OFFSET+7:SRC1_OFFSET]
SRC1_BYTE1 <- SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8]
SRC1_BYTE2 <- SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16]
SRC1_BYTE3 <- SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24]
SRC1_BYTE4 <- SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32]
SRC1_BYTE5 <- SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40]
SRC1_BYTE6 <- SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48]
SRC1_BYTE7 <- SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56]
SRC1_BYTE8 <- SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64]
SRC1_BYTE9 <- SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72]
SRC1_BYTE10 <- SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80]
SRC2_BYTE0 <-SRC2[SRC2_OFFSET+7:SRC2_OFFSET]
SRC2_BYTE1 <- SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8]
SRC2_BYTE2 <- SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16]
SRC2_BYTE3 <- SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24]
TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[143:128] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <-ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[159:144] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[175:160] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <-ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[191:176] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[207:192] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[223:208] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[239:224] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[255:240] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
VMPSADBW (VEX.128 encoded version)
SRC2_OFFSET <- imm8[1:0]*32
SRC1_OFFSET <- imm8[2]*32
SRC1_BYTE0 <- SRC1[SRC1_OFFSET+7:SRC1_OFFSET]
SRC1_BYTE1 <- SRC1[SRC1_OFFSET+15:SRC1_OFFSET+8]
SRC1_BYTE2 <- SRC1[SRC1_OFFSET+23:SRC1_OFFSET+16]
SRC1_BYTE3 <- SRC1[SRC1_OFFSET+31:SRC1_OFFSET+24]
SRC1_BYTE4 <- SRC1[SRC1_OFFSET+39:SRC1_OFFSET+32]
SRC1_BYTE5 <- SRC1[SRC1_OFFSET+47:SRC1_OFFSET+40]
SRC1_BYTE6 <- SRC1[SRC1_OFFSET+55:SRC1_OFFSET+48]
SRC1_BYTE7 <- SRC1[SRC1_OFFSET+63:SRC1_OFFSET+56]
SRC1_BYTE8 <- SRC1[SRC1_OFFSET+71:SRC1_OFFSET+64]
SRC1_BYTE9 <- SRC1[SRC1_OFFSET+79:SRC1_OFFSET+72]
SRC1_BYTE10 <- SRC1[SRC1_OFFSET+87:SRC1_OFFSET+80]
SRC2_BYTE0 <-SRC2[SRC2_OFFSET+7:SRC2_OFFSET]
SRC2_BYTE1 <- SRC2[SRC2_OFFSET+15:SRC2_OFFSET+8]
SRC2_BYTE2 <- SRC2[SRC2_OFFSET+23:SRC2_OFFSET+16]
SRC2_BYTE3 <- SRC2[SRC2_OFFSET+31:SRC2_OFFSET+24]
TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] <- 0
MPSADBW (128-bit Legacy SSE version)
SRC_OFFSET <- imm8[1:0]*32
DEST_OFFSET <- imm8[2]*32
DEST_BYTE0 <- DEST[DEST_OFFSET+7:DEST_OFFSET]
DEST_BYTE1 <- DEST[DEST_OFFSET+15:DEST_OFFSET+8]
DEST_BYTE2 <- DEST[DEST_OFFSET+23:DEST_OFFSET+16]
DEST_BYTE3 <- DEST[DEST_OFFSET+31:DEST_OFFSET+24]
DEST_BYTE4 <- DEST[DEST_OFFSET+39:DEST_OFFSET+32]
DEST_BYTE5 <- DEST[DEST_OFFSET+47:DEST_OFFSET+40]
DEST_BYTE6 <- DEST[DEST_OFFSET+55:DEST_OFFSET+48]
DEST_BYTE7 <- DEST[DEST_OFFSET+63:DEST_OFFSET+56]
DEST_BYTE8 <- DEST[DEST_OFFSET+71:DEST_OFFSET+64]
DEST_BYTE9 <- DEST[DEST_OFFSET+79:DEST_OFFSET+72]
DEST_BYTE10 <- DEST[DEST_OFFSET+87:DEST_OFFSET+80]
SRC_BYTE0 <- SRC[SRC_OFFSET+7:SRC_OFFSET]
SRC_BYTE1 <- SRC[SRC_OFFSET+15:SRC_OFFSET+8]
SRC_BYTE2 <- SRC[SRC_OFFSET+23:SRC_OFFSET+16]
SRC_BYTE3 <- SRC[SRC_OFFSET+31:SRC_OFFSET+24]
TEMP0 <- ABS( DEST_BYTE0 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE1 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE2 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE3 - SRC_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE1 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE2 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE3 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE4 - SRC_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE2 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE3 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE4 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE5 - SRC_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE3 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE4 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE5 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE6 - SRC_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE4 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE5 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE6 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE7 - SRC_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE5 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE6 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE7 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE8 - SRC_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE6 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE7 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE8 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE9 - SRC_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
TEMP0 <- ABS( DEST_BYTE7 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE8 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE9 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE10 - SRC_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)MPSADBW:| __m128i _mm_mpsadbw_epu8 (__m128i s1,
|            | __m128i s2, const int mask);         
| VMPSADBW:  | __m256i _mm256_mpsadbw_epu8 (__m256i 
|            | s1, __m256i s2, const int mask);     

Flags Affected:
None


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: MUL
description:
MUL - Unsigned Multiply:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| F6 /4        | MUL r/m8   | M    | Valid      | Valid          | Unsigned multiply (AX ← AL * r/m8).       
| REX + F6 /4  | MUL r/m8*  | M    | Valid      | N.E.           | Unsigned multiply (AX ← AL * r/m8).       
| F7 /4        | MUL r/m16  | M    | Valid      | Valid          | Unsigned multiply (DX:AX ← AX * r/m16).   
| F7 /4        | MUL r/m32  | M    | Valid      | Valid          | Unsigned multiply (EDX:EAX ← EAX * r/m32).
| REX.W + F7 /4| MUL r/m64  | M    | Valid      | N.E.           | Unsigned multiply (RDX:RAX ← RAX * r/m64).
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Performs an unsigned multiplication of the first operand (destination operand)
and the second operand (source operand) and stores the result in the destination
operand. The destination operand is an implied operand located in register AL,
AX or EAX (depending on the size of the operand); the source operand is located
in a generalpurpose register or a memory location. The action of this instruction
and the location of the result depends on the opcode and the operand size as
shown in Table 3-66.

The result is stored in register AX, register pair DX:AX, or register pair EDX:EAX
(depending on the operand size), with the high-order bits of the product contained
in register AH, DX, or EDX, respectively. If the high-order bits of the product
are 0, the CF and OF flags are cleared; otherwise, the flags are set.

In 64-bit mode, the instruction's default operation size is 32 bits. Use of
the REX.R prefix permits access to additional registers (R8-R15). Use of the
REX.W prefix promotes operation to 64 bits.

See the summary chart at the beginning of this section for encoding data and
limits.


Table 3-66. MUL Results:
| Operand Size| Source 1 AL AX EAX RAX| Source 2 r/m8 r/m16 r/m32 r/m64| Destination AX DX:AX EDX:EAX RDX:RAX
Operation:

IF (Byte operation)
  THEN
     AX <- AL * SRC;
  ELSE (* Word or doubleword operation *)
     IF OperandSize = 16
       THEN
          DX:AX <- AX * SRC;
       ELSE IF OperandSize = 32
          THEN EDX:EAX <- EAX * SRC; FI;
       ELSE (* OperandSize = 64 *)
          RDX:RAX <- RAX * SRC;
     FI;
FI;

Flags Affected:
The OF and CF flags are set to 0 if the upper half of the result is 0; otherwise,
they are set to 1. The SF, ZF, AF, and PF flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: MULPD
description:
MULPD - Multiply Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                    
| 66 0F 59 /r MULPD xmm1, xmm2/m128            | RM   | V/V           | SSE2              | Multiply packed double-precision floating-point
|                                              |      |               |                   | values in xmm2/m128 by xmm1.                   
| VEX.NDS.128.66.0F.WIG 59 /r VMULPD xmm1,xmm2,| RVM  | V/V           | AVX               | Multiply packed double-precision floating-point
| xmm3/m128                                    |      |               |                   | values from xmm3/mem to xmm2 and stores        
|                                              |      |               |                   | result in xmm1.                                
| VEX.NDS.256.66.0F.WIG 59 /r VMULPD ymm1,     | RVM  | V/V           | AVX               | Multiply packed double-precision floating-point
| ymm2, ymm3/m256                              |      |               |                   | values from ymm3/mem to ymm2 and stores        
|                                              |      |               |                   | result in ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply of the two or four packed double-precision floating-point
values from the source operand (second operand) and the destination operand
(first operand), and stores the packed double-precision floatingpoint results
in the destination operand. The source operand can be an XMM register or a 128-bit
memory location. The destination operand is an XMM register. See Figure 11-3
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, for an illustration of a SIMD double-precision floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The second source can be
an XMM register or an 128-bit memory location. The destination is not distinct
from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. VEX.128 encoded version: the first
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the destination
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand can be a YMM register or
a 256-bit memory location. The destination operand is a YMM register.

Operation:

MULPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] * SRC[63:0]
DEST[127:64] <- DEST[127:64] * SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VMULPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] * SRC2[63:0]
DEST[127:64] <- SRC1[127:64] * SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VMULPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] * SRC2[63:0]
DEST[127:64] <- SRC1[127:64] * SRC2[127:64]
DEST[191:128] <- SRC1[191:128] * SRC2[191:128]
DEST[255:192] <- SRC1[255:192] * SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| MULPD: | __m128d _mm_mul_pd (m128d a, m128d b)    
| VMULPD:| __m256d _mm256_mul_pd (__m256d a, __m256d
|        | b);                                      

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: MULPS
description:
MULPS - Multiply Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                    
| 0F 59 /r MULPS xmm1, xmm2/m128            | RM   | V/V           | SSE               | Multiply packed single-precision floating-point
|                                           |      |               |                   | values in xmm2/mem by xmm1.                    
| VEX.NDS.128.0F.WIG 59 /r VMULPS xmm1,xmm2,| RVM  | V/V           | AVX               | Multiply packed single-precision floating-point
| xmm3/m128                                 |      |               |                   | values from xmm3/mem to xmm2 and stores        
|                                           |      |               |                   | result in xmm1.                                
| VEX.NDS.256.0F.WIG 59 /r VMULPS ymm1,     | RVM  | V/V           | AVX               | Multiply packed single-precision floating-point
| ymm2, ymm3/m256                           |      |               |                   | values from ymm3/mem to ymm2 and stores        
|                                           |      |               |                   | result in ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply of the four packed single-precision floating-point
values from the source operand (second operand) and the destination operand
(first operand), and stores the packed single-precision floatingpoint results
in the destination operand. See Figure 10-5 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1, for an illustration of a SIMD single-precision
floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The second source can be
an XMM register or an 128-bit memory location. The destination is not distinct
from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified. VEX.128 encoded version: the first
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the destination
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand can be a YMM register or
a 256-bit memory location. The destination operand is a YMM register.

Operation:

MULPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] * SRC2[31:0]
DEST[63:32] <- SRC1[63:32] * SRC2[63:32]
DEST[95:64] <- SRC1[95:64] * SRC2[95:64]
DEST[127:96] <- SRC1[127:96] * SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VMULPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] * SRC2[31:0]
DEST[63:32] <- SRC1[63:32] * SRC2[63:32]
DEST[95:64] <- SRC1[95:64] * SRC2[95:64]
DEST[127:96] <- SRC1[127:96] * SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VMULPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] * SRC2[31:0]
DEST[63:32] <- SRC1[63:32] * SRC2[63:32]
DEST[95:64] <- SRC1[95:64] * SRC2[95:64]
DEST[127:96] <- SRC1[127:96] * SRC2[127:96]
DEST[159:128] <- SRC1[159:128] * SRC2[159:128]
DEST[191:160]<- SRC1[191:160] * SRC2[191:160]
DEST[223:192] <- SRC1[223:192] * SRC2[223:192]
DEST[255:224] <- SRC1[255:224] * SRC2[255:224].

Intel C/C++ Compiler Intrinsic Equivalent:
| MULPS: | __m128 _mm_mul_ps(__m128 a, __m128 b) 
| VMULPS:| __m256 _mm256_mul_ps (__m256 a, __m256
|        | b);                                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: MULSD
description:
MULSD - Multiply Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                    
| F2 0F 59 /r MULSD xmm1, xmm2/m64            | RM   | V/V           | SSE2              | Multiply the low double-precision floatingpoint
|                                             |      |               |                   | value in xmm2/mem64 by low doubleprecision     
|                                             |      |               |                   | floating-point value in xmm1.                  
| VEX.NDS.LIG.F2.0F.WIG 59/r VMULSD xmm1,xmm2,| RVM  | V/V           | AVX               | Multiply the low double-precision floatingpoint
| xmm3/m64                                    |      |               |                   | value in xmm3/mem64 by low double precision    
|                                             |      |               |                   | floating-point value in xmm2.                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Multiplies the low double-precision floating-point value in the source operand
(second operand) by the low doubleprecision floating-point value in the destination
operand (first operand), and stores the double-precision floatingpoint result
in the destination operand. The source operand can be an XMM register or a 64-bit
memory location. The destination operand is an XMM register. The high quadword
of the destination operand remains unchanged. See Figure 11-4 in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a scalar double-precision floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The first source operand
and the destination operand are the same. Bits (VLMAX1:64) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

Operation:

MULSD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] * SRC[63:0]
DEST[VLMAX-1:64] (Unmodified)
VMULSD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] * SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| MULSD:| __m128d _mm_mul_sd (m128d a, m128d b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: MULSS
description:
MULSS - Multiply Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                     
| F3 0F 59 /r MULSS xmm1, xmm2/m32             | RM   | V/V           | SSE               | Multiply the low single-precision floating-point
|                                              |      |               |                   | value in xmm2/mem by the low singleprecision    
|                                              |      |               |                   | floating-point value in xmm1.                   
| VEX.NDS.LIG.F3.0F.WIG 59 /r VMULSS xmm1,xmm2,| RVM  | V/V           | AVX               | Multiply the low single-precision floating-point
| xmm3/m32                                     |      |               |                   | value in xmm3/mem by the low singleprecision    
|                                              |      |               |                   | floating-point value in xmm2.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Multiplies the low single-precision floating-point value from the source operand
(second operand) by the low single-precision floating-point value in the destination
operand (first operand), and stores the single-precision floating-point result
in the destination operand. The source operand can be an XMM register or a 32-bit
memory location. The destination operand is an XMM register. The three high-order
doublewords of the destination operand remain unchanged. See Figure 10-6 in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1,
for an illustration of a scalar single-precision floating-point operation.

In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The first source operand
and the destination operand are the same. Bits (VLMAX1:32) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

Operation:

MULSS (128-bit Legacy SSE version)
DEST[31:0] <- DEST[31:0] * SRC[31:0]
DEST[VLMAX-1:32] (Unmodified)
VMULSS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| MULSS:| __m128 _mm_mul_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: MULX
description:
MULX  -  Unsigned Multiply Without Affecting Flags:
| Opcode/Instruction                    | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                        
| VEX.NDD.LZ.F2.0F38.W0 F6 /r MULX r32a,| RVM  | V/V            | BMI2              | Unsigned multiply of r/m32 with EDX
| r32b, r/m32                           |      |                |                   | without affecting arithmetic flags.
| VEX.NDD.LZ.F2.0F38.W1 F6 /r MULX r64a,| RVM  | V/N.E.         | BMI2              | Unsigned multiply of r/m64 with RDX
| r64b, r/m64                           |      |                |                   | without affecting arithmetic flags.

Instruction Operand Encoding:
| Op/En RVM| Operand 1 ModRM:reg (w)| Operand 2 VEX.vvvv (w)| Operand 3 ModRM:r/m (r)| Operand 4 RDX/EDX is implied 64/32 bits
|          |                        |                       |                        | source                                 

Description:
Performs an unsigned multiplication of the implicit source operand (EDX/RDX)
and the specified source operand (the third operand) and stores the low half
of the result in the second destination (second operand), the high half of the
result in the first destination operand (first operand), without reading or
writing the arithmetic flags. This enables efficient programming where the software
can interleave add with carry operations and multiplications. If the first and
second operand are identical, it will contain the high half of the multiplication
result. This instruction is not supported in real mode and virtual-8086 mode.
The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode operand
size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to
execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

// DEST1: ModRM:reg
// DEST2: VEX.vvvv
IF (OperandSize = 32)
  SRC1 <- EDX;
  DEST2 <- (SRC1*SRC2)[31:0];
  DEST1 <- (SRC1*SRC2)[63:32];
ELSE IF (OperandSize = 64)
  SRC1 <- RDX;
     DEST2 <- (SRC1*SRC2)[63:0];
     DEST1 <- (SRC1*SRC2)[127:64];
FI

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
Auto-generated from high-level language when possible.

unsigned int mulx_u32(unsigned int a, unsigned int b, unsigned int * hi);

unsigned __int64 mulx_u64(unsigned __int64 a, unsigned __int64 b, unsigned __int64
* hi);


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: MWAIT
description:
MWAIT - Monitor Wait:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                                
| 0F 01 C9| MWAIT      | NP   | Valid      | Valid          | A hint that allow the processor to stop                    
|         |            |      |            |                | instruction execution and enter an implementation-dependent
|         |            |      |            |                | optimized state until occurrence of                        
|         |            |      |            |                | a class of events.                                         

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
MWAIT instruction provides hints to allow the processor to enter an implementation-dependent
optimized state. There are two principal targeted usages: address-range monitor
and advanced power management. Both usages of MWAIT require the use of the MONITOR
instruction.

CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT
in the processor. When set, MWAIT may be executed only at privilege level 0
(use at any other privilege level results in an invalid-opcode exception). The
operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE
MSR; disabling MWAIT clears the CPUID feature flag and causes execution to generate
an invalid-opcode exception.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

ECX specifies optional extensions for the MWAIT instruction. EAX may contain
hints such as the preferred optimized state the processor should enter. The
first processors to implement MWAIT supported only the zero value for EAX and
ECX. Later processors allowed setting ECX[0] to enable masked interrupts as
break events for MWAIT (see below). Software can use the CPUID instruction to
determine the extensions and hints supported by the processor.


MWAIT for Address Range Monitoring:
For address-range monitoring, the MWAIT instruction operates with the MONITOR
instruction. The two instructions allow the definition of an address at which
to wait (MONITOR) and a implementation-dependent-optimized operation to commence
at the wait address (MWAIT). The execution of MWAIT is a hint to the processor
that it can enter an implementation-dependent-optimized state while waiting
for an event or a store operation to the address range armed by MONITOR.

The following cause the processor to exit the implementation-dependent-optimized
state: a store to the address range armed by the MONITOR instruction, an NMI
or SMI, a debug exception, a machine check exception, the BINIT# signal, the
INIT# signal, and the RESET# signal. Other implementation-dependent events may
also cause the processor to exit the implementation-dependent-optimized state.

In addition, an external interrupt causes the processor to exit the implementation-dependent-optimized
state either (1) if the interrupt would be delivered to software (e.g., as it
would be if HLT had been executed instead of MWAIT); or (2) if ECX[0] = 1. Software
can execute MWAIT with ECX[0] = 1 only if CPUID.05H:ECX[bit 1] = 1. (Implementation-specific
conditions may result in an interrupt causing the processor to exit the implementationdependent-optimized
state even if interrupts are masked and ECX[0] = 0.)

Following exit from the implementation-dependent-optimized state, control passes
to the instruction following the MWAIT instruction. A pending interrupt that
is not masked (including an NMI or an SMI) may be delivered before execution
of that instruction. Unlike the HLT instruction, the MWAIT instruction does
not support a restart at the MWAIT instruction following the handling of an
SMI.

If the preceding MONITOR instruction did not successfully arm an address range
or if the MONITOR instruction has not been executed prior to executing MWAIT,
then the processor will not enter the implementation-dependent-optimized state.
Execution will resume at the instruction following the MWAIT.


MWAIT for Power Management:
MWAIT accepts a hint and optional extension to the processor that it can enter
a specified target C state while waiting for an event or a store operation to
the address range armed by MONITOR. Support for MWAIT extensions for power management
is indicated by CPUID.05H:ECX[bit 0] reporting 1.

EAX and ECX are used to communicate the additional information to the MWAIT
instruction, such as the kind of optimized state the processor should enter.
ECX specifies optional extensions for the MWAIT instruction. EAX may contain
hints such as the preferred optimized state the processor should enter. Implementation-specific
conditions may cause a processor to ignore the hint and enter a different optimized
state. Future processor implementations may implement several optimized “waiting”
states and will select among those states based on the hint argument.

Table 3-67 describes the meaning of ECX and EAX registers for MWAIT extensions.


Table 3-67. MWAIT Extension Register (ECX):
| Bits                                   | Description                     
| Treat interrupts as break events even  | 0                               
| if masked (e.g., even if EFLAGS.IF=0). |                                 
| May be set only if CPUID.05H:ECX[bit   |                                 
| 1] = 1.                                |                                 
| Reserved                               | 31: 1 MWAIT Hints Register (EAX)
| Bits                                   | Description                     
| Sub C-state within a C-state, indicated| 3 : 0                           
| by bits [7:4]                          |                                 
| Target C-state*Value of 0 means C1;    | 7 : 4                           
| 1 means C2 and so on Value of 01111B   |                                 
| means C0                               |                                 
Note: Target C states for MWAIT extensions are processor-specific C-states,
not ACPI C-states

| 31: 8| Reserved
Note that if MWAIT is used to enter any of the C-states that are numerically
higher than C1, a store to the address range armed by the MONITOR instruction
will cause the processor to exit MWAIT only if the store was originated by other
processor agents. A store from non-processor agent might not cause the processor
to exit MWAIT in such cases.

For additional details of MWAIT extensions, see Chapter 14, “Power and Thermal
Management,” of Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A.

Operation:

(* MWAIT takes the argument in EAX as a hint extension and is architected to take the argument in ECX as an instruction extension
MWAIT EAX, ECX *)
{
WHILE ( (“Monitor Hardware is in armed state”)) {
  implementation_dependent_optimized_state(EAX, ECX); }
Set the state of Monitor Hardware as triggered;
}

Intel C/C++ Compiler Intrinsic Equivalent:
| MWAIT:| void _mm_mwait(unsigned extensions,
|       | unsigned hints)                    

Example:
MONITOR/MWAIT instruction pair must be coded in the same loop because execution
of the MWAIT instruction will trigger the monitor hardware. It is not a proper
usage to execute MONITOR once and then execute MWAIT in a loop. Setting up MONITOR
without executing MWAIT has no adverse effects.

Typically the MONITOR/MWAIT pair is used in a sequence, such as:

EAX = Logical Address(Trigger) ECX = 0 (*Hints *) EDX = 0 (* Hints *)

IF ( !trigger_store_happened) {MONITOR EAX, ECX, EDX IF ( !trigger_store_happened
) {MWAIT EAX, ECX }}

The above code sequence makes sure that a triggering store does not happen between
the first check of the trigger and the execution of the monitor instruction.
Without the second check that triggering store would go un-noticed. Typical
usage of MONITOR and MWAIT would have the above code sequence within a loop.


Numeric Exceptions:
None


Protected Mode Exceptions:
| #GP(0)| If ECX[31:1] != 0. If ECX[0] = 1 and 
|       | CPUID.05H:ECX[bit 1] = 0.           
| #UD   | If CPUID.01H:ECX.MONITOR[bit 3] = 0.
|       | If current privilege level is not 0.

Real Address Mode Exceptions:
| #GP| If ECX[31:1] != 0. If ECX[0] = 1 and 
|    | CPUID.05H:ECX[bit 1] = 0.           
| #UD| If CPUID.01H:ECX.MONITOR[bit 3] = 0.

Virtual 8086 Mode Exceptions:
| #UD| The MWAIT instruction is not recognized                
|    | in virtual-8086 mode (even if CPUID.01H:ECX.MONITOR[bit
|    | 3] = 1).                                               

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)| If RCX[63:1] != 0. If RCX[0] = 1 and  
|       | CPUID.05H:ECX[bit 1] = 0.            
| #UD   | If the current privilege level is not
|       | 0. If CPUID.01H:ECX.MONITOR[bit 3] = 
|       | 0.                                   


platform: x86
mnem: NEG
description:
NEG - Two's Complement Negation:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                   
| F6 /3        | NEG r/m8   | M    | Valid      | Valid          | Two's complement negate r/m8. 
| REX + F6 /3  | NEG r/m8*  | M    | Valid      | N.E.           | Two's complement negate r/m8. 
| F7 /3        | NEG r/m16  | M    | Valid      | Valid          | Two's complement negate r/m16.
| F7 /3        | NEG r/m32  | M    | Valid      | Valid          | Two's complement negate r/m32.
| REX.W + F7 /3| NEG r/m64  | M    | Valid      | N.E.           | Two's complement negate r/m64.
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r, w)| NA       | NA       | NA       

Description:
Replaces the value of operand (the destination operand) with its two's complement.
(This operation is equivalent to subtracting the operand from 0.) The destination
operand is located in a general-purpose register or a memory location.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

IF DEST = 0
  THEN CF <- 0;
  ELSE CF <- 1;
FI;
DEST <- [- (DEST)]

Flags Affected:
The CF flag set to 0 if the source operand is 0; otherwise it is set to 1. The
OF, SF, ZF, AF, and PF flags are set according to the result.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used but the destination 
|                | is not a memory operand.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| For a page fault.                             
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: NOP
description:
NOP - No Operation:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| 90      | NOP        | NP   | Valid      | Valid          | One byte no-operation instruction.  
| 0F 1F /0| NOP r/m16  | M    | Valid      | Valid          | Multi-byte no-operation instruction.
| 0F 1F /0| NOP r/m32  | M    | Valid      | Valid          | Multi-byte no-operation instruction.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| NP   | NA           | NA       | NA       | NA       
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
This instruction performs no operation. It is a one-byte or multi-byte NOP that
takes up space in the instruction stream but does not impact machine context,
except for the EIP register.

The multi-byte form of NOP is available on processors with model encoding:

 - CPUID.01H.EAX[Bytes 11:8] = 0110B or 1111B

The multi-byte NOP instruction does not alter the content of a register and
will not issue a memory operation. The instruction's operation is the same in
non-64-bit modes and 64-bit mode.

Operation:

The one-byte NOP instruction is an alias mnemonic for the XCHG (E)AX, (E)AX instruction.
The multi-byte NOP instruction performs no operation on supported processors and generates undefined opcode
exception on processors that do not support the multi-byte NOP instruction.
The memory operand form of the instruction allows software to create a byte sequence of “no operation” as one
instruction. For situations where multiple-byte NOPs are needed, the recommended operations (32-bit mode and
64-bit mode) are:

Table 4-9. Recommended Multi-Byte Sequence of NOP Instruction:
| Length | Assembly                                  | Byte Sequence              
| 2 bytes| 66 NOP                                    | 66 90H                     
| 3 bytes| NOP DWORD ptr [EAX]                       | 0F 1F 00H                  
| 4 bytes| NOP DWORD ptr [EAX + 00H]                 | 0F 1F 40 00H               
| 5 bytes| NOP DWORD ptr [EAX + EAX*1 + 00H]         | 0F 1F 44 00 00H            
| 6 bytes| 66 NOP DWORD ptr [EAX + EAX*1 + 00H]      | 66 0F 1F 44 00 00H         
| 7 bytes| NOP DWORD ptr [EAX + 00000000H]           | 0F 1F 80 00 00 00 00H      
| 8 bytes| NOP DWORD ptr [EAX + EAX*1 + 00000000H]   | 0F 1F 84 00 00 00 00 00H   
| 9 bytes| 66 NOP DWORD ptr [EAX + EAX*1 + 00000000H]| 66 0F 1F 84 00 00 00 00 00H

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: NOT
description:
NOT - One's Complement Negation:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description               
| F6 /2        | NOT r/m8   | M    | Valid      | Valid          | Reverse each bit of r/m8. 
| REX + F6 /2  | NOT r/m8*  | M    | Valid      | N.E.           | Reverse each bit of r/m8. 
| F7 /2        | NOT r/m16  | M    | Valid      | Valid          | Reverse each bit of r/m16.
| F7 /2        | NOT r/m32  | M    | Valid      | Valid          | Reverse each bit of r/m32.
| REX.W + F7 /2| NOT r/m64  | M    | Valid      | N.E.           | Reverse each bit of r/m64.
Notes: 

| *| In 64-bit mode, r/m8 can not be encoded
|  | to access the following byte registers 
|  | if a REX prefix is used: AH, BH, CH,   
|  | DH.                                    

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r, w)| NA       | NA       | NA       

Description:
Performs a bitwise NOT operation (each 1 is set to 0, and each 0 is set to 1)
on the destination operand and stores the result in the destination operand
location. The destination operand can be a register or a memory location.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

DEST <- NOT DEST;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: OR
description:
OR - Logical Inclusive OR:
| Opcode          | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                    
| 0C ib           | OR AL, imm8    | I    | Valid      | Valid          | AL OR imm8.                    
| 0D iw           | OR AX, imm16   | I    | Valid      | Valid          | AX OR imm16.                   
| 0D id           | OR EAX, imm32  | I    | Valid      | Valid          | EAX OR imm32.                  
| REX.W + 0D id   | OR RAX, imm32  | I    | Valid      | N.E.           | RAX OR imm32 (sign-extended).  
| 80 /1 ib        | OR r/m8, imm8  | MI   | Valid      | Valid          | r/m8 OR imm8.                  
| REX + 80 /1 ib  | OR r/m8*, imm8 | MI   | Valid      | N.E.           | r/m8 OR imm8.                  
| 81 /1 iw        | OR r/m16, imm16| MI   | Valid      | Valid          | r/m16 OR imm16.                
| 81 /1 id        | OR r/m32, imm32| MI   | Valid      | Valid          | r/m32 OR imm32.                
| REX.W + 81 /1 id| OR r/m64, imm32| MI   | Valid      | N.E.           | r/m64 OR imm32 (sign-extended).
| 83 /1 ib        | OR r/m16, imm8 | MI   | Valid      | Valid          | r/m16 OR imm8 (sign-extended). 
| 83 /1 ib        | OR r/m32, imm8 | MI   | Valid      | Valid          | r/m32 OR imm8 (sign-extended). 
| REX.W + 83 /1 ib| OR r/m64, imm8 | MI   | Valid      | N.E.           | r/m64 OR imm8 (sign-extended). 
| 08 /r           | OR r/m8, r8    | MR   | Valid      | Valid          | r/m8 OR r8.                    
| REX + 08 /r     | OR r/m8*, r8*  | MR   | Valid      | N.E.           | r/m8 OR r8.                    
| 09 /r           | OR r/m16, r16  | MR   | Valid      | Valid          | r/m16 OR r16.                  
| 09 /r           | OR r/m32, r32  | MR   | Valid      | Valid          | r/m32 OR r32.                  
| REX.W + 09 /r   | OR r/m64, r64  | MR   | Valid      | N.E.           | r/m64 OR r64.                  
| 0A /r           | OR r8, r/m8    | RM   | Valid      | Valid          | r8 OR r/m8.                    
| REX + 0A /r     | OR r8*, r/m8*  | RM   | Valid      | N.E.           | r8 OR r/m8.                    
| 0B /r           | OR r16, r/m16  | RM   | Valid      | Valid          | r16 OR r/m16.                  
| 0B /r           | OR r32, r/m32  | RM   | Valid      | Valid          | r32 OR r/m32.                  
| REX.W + 0B /r   | OR r64, r/m64  | RM   | Valid      | N.E.           | r64 OR r/m64.                  
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| I    | AL/AX/EAX/RAX   | imm8/16/32   | NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8/16/32   | NA       | NA       
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a bitwise inclusive OR operation between the destination (first) and
source (second) operands and stores the result in the destination operand location.
The source operand can be an immediate, a register, or a memory location; the
destination operand can be a register or a memory location. (However, two memory
operands cannot be used in one instruction.) Each bit of the result of the OR
instruction is set to 0 if both corresponding bits of the first and second operands
are 0; otherwise, each bit is set to 1.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

DEST <- DEST OR SRC;

Flags Affected:
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according
to the result. The state of the AF flag is undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination operand points to          
|                | a non-writable segment. If a memory           
|                | operand effective address is outside          
|                | the CS, DS, ES, FS, or GS segment limit.      
|                | If the DS, ES, FS, or GS register contains    
|                | a NULL segment selector.                      
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: ORPD
description:
ORPD - Bitwise Logical OR of Double-Precision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 56 /r ORPD xmm1, xmm2/m128            | RM   | V/V                   | SSE2              | Bitwise OR of xmm2/m128 and xmm1.      
| VEX.NDS.128.66.0F.WIG 56 /r VORPD xmm1,xmm2,| RVM  | V/V                   | AVX               | Return the bitwise logical OR of packed
| xmm3/m128                                   |      |                       |                   | double-precision floating-point values 
|                                             |      |                       |                   | in xmm2 and xmm3/mem.                  
| VEX.NDS.256.66.0F.WIG 56 /r VORPD ymm1,     | RVM  | V/V                   | AVX               | Return the bitwise logical OR of packed
| ymm2, ymm3/m256                             |      |                       |                   | double-precision floating-point values 
|                                             |      |                       |                   | in ymm2 and ymm3/mem.                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical OR of the two or four packed double-precision floating-point
values from the first source operand and the second source operand, and stores
the result in the destination operand

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the destination YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register. Note: If VORPD is encoded with VEX.L= 1, an attempt to execute the
instruction encoded with VEX.L= 1 will cause an #UD exception.

Operation:

ORPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] BITWISE OR SRC[63:0]
DEST[127:64] <- DEST[127:64] BITWISE OR SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VORPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VORPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE OR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE OR SRC2[127:64]
DEST[191:128] <- SRC1[191:128] BITWISE OR SRC2[191:128]
DEST[255:192] <- SRC1[255:192] BITWISE OR SRC2[255:192]

Intel® C/C++ Compiler Intrinsic Equivalent:
| ORPD: | __m128d _mm_or_pd(__m128d a, __m128d    
|       | b);                                     
| VORPD:| __m256d _mm256_or_pd (__m256d a, __m256d
|       | b);                                     

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: ORPS
description:
ORPS - Bitwise Logical OR of Single-Precision Floating-Point Values:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F 56 /r ORPS xmm1, xmm2/m128       | RM   | V/V                   | SSE               | Bitwise OR of xmm1 and xmm2/m128.      
| VEX.NDS.128.0F.WIG 56 /r VORPS xmm1,| RVM  | V/V                   | AVX               | Return the bitwise logical OR of packed
| xmm2, xmm3/m128                     |      |                       |                   | singleprecision floating-point values  
|                                     |      |                       |                   | in xmm2 and xmm3/mem.                  
| VEX.NDS.256.0F.WIG 56 /r VORPS ymm1,| RVM  | V/V                   | AVX               | Return the bitwise logical OR of packed
| ymm2, ymm3/m256                     |      |                       |                   | singleprecision floating-point values  
|                                     |      |                       |                   | in ymm2 and ymm3/mem.                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical OR of the four or eight packed single-precision floating-point
values from the first source operand and the second source operand, and stores
the result in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the destination YMM register destination are zeroed. VEX.256 Encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register. Note: If VORPS is encoded with VEX.L= 1, an attempt to execute the
instruction encoded with VEX.L= 1 will cause an #UD exception.

Operation:

ORPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VORPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VORPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE OR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE OR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE OR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE OR SRC2[127:96]
DEST[159:128] <- SRC1[159:128] BITWISE OR SRC2[159:128]
DEST[191:160]<- SRC1[191:160] BITWISE OR SRC2[191:160]
DEST[223:192] <- SRC1[223:192] BITWISE OR SRC2[223:192]
DEST[255:224] <- SRC1[255:224] BITWISE OR SRC2[255:224].

Intel C/C++ Compiler Intrinsic Equivalent:
| ORPS: | __m128 _mm_or_ps (__m128 a, __m128 b);
| VORPS:| __m256 _mm256_or_ps (__m256 a, __m256 
|       | b);                                   

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: OUT
description:
OUT - Output to Port:
| Opcode*| Instruction  | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| E6 ib  | OUT imm8, AL | I    | Valid      | Valid          | Output byte in AL to I/O port address
|        |              |      |            |                | imm8.                                
| E7 ib  | OUT imm8, AX | I    | Valid      | Valid          | Output word in AX to I/O port address
|        |              |      |            |                | imm8.                                
| E7 ib  | OUT imm8, EAX| I    | Valid      | Valid          | Output doubleword in EAX to I/O port 
|        |              |      |            |                | address imm8.                        
| EE     | OUT DX, AL   | NP   | Valid      | Valid          | Output byte in AL to I/O port address
|        |              |      |            |                | in DX.                               
| EF     | OUT DX, AX   | NP   | Valid      | Valid          | Output word in AX to I/O port address
|        |              |      |            |                | in DX.                               
| EF     | OUT DX, EAX  | NP   | Valid      | Valid          | Output doubleword in EAX to I/O port 
|        |              |      |            |                | address in DX.                       
Notes: * See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| I    | imm8     | NA       | NA       | NA       
| NP   | NA       | NA       | NA       | NA       

Description:
Copies the value from the second operand (source operand) to the I/O port specified
with the destination operand (first operand). The source operand can be register
AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or
32 bits, respectively); the destination operand can be a byte-immediate or the
DX register. Using a byte immediate allows I/O port addresses 0 to 255 to be
accessed; using the DX register as a source operand allows I/O ports from 0
to 65,535 to be accessed.

The size of the I/O port being accessed is determined by the opcode for an 8-bit
I/O port or by the operand-size attribute of the instruction for a 16- or 32-bit
I/O port.

At the machine code level, I/O instructions are shorter when accessing 8-bit
I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's
I/O address space. See Chapter 16, “Input/Output,” in the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1, for more information on
accessing I/O ports in the I/O address space.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


IA-32 Architecture Compatibility:
After executing an OUT instruction, the Pentium® processor ensures that the
EWBE# pin has been sampled active before it begins to execute the next instruction.
(Note that the instruction can be prefetched if EWBE# is not active, but it
will not be executed until the EWBE# pin is sampled active.) Only the Pentium
processor family has the EWBE# pin.

Operation:

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
  THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
     IF (Any I/O Permission Bit for I/O port being accessed = 1)
       THEN (* I/O operation is not allowed *)
          #GP(0);
       ELSE ( * I/O operation is allowed *)
          DEST <- SRC; (* Writes to selected I/O port *)
     FI;
  ELSE (Real Mode or Protected Mode with CPL ≤ IOPL *)
     DEST <- SRC; (* Writes to selected I/O port *)
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the CPL is greater than (has less       
|       | privilege) the I/O privilege level (IOPL)  
|       | and any of the corresponding I/O permission
|       | bits in TSS for the I/O port being accessed
|       | is 1.                                      
| #UD   | If the LOCK prefix is used.                

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)         | If any of the I/O permission bits in   
|                | the TSS for the I/O port being accessed
|                | is 1.                                  
| #PF(fault-code)| If a page fault occurs.                
| #UD            | If the LOCK prefix is used.            

Compatibility Mode Exceptions:
Same as protected mode exceptions.


64-Bit Mode Exceptions:
Same as protected mode exceptions.


platform: x86
mnem: OUTS
description:
OUTS/OUTSB/OUTSW/OUTSD - Output String to Port:
| Opcode*| Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                               
| 6E     | OUTS DX, m8 | NP   | Valid      | Valid          | Output byte from memory location specified
|        |             |      |            |                | in DS:(E)SI or RSI to I/O port specified  
|        |             |      |            |                | in DX**.                                  
| 6F     | OUTS DX, m16| NP   | Valid      | Valid          | Output word from memory location specified
|        |             |      |            |                | in DS:(E)SI or RSI to I/O port specified  
|        |             |      |            |                | in DX**.                                  
| 6F     | OUTS DX, m32| NP   | Valid      | Valid          | Output doubleword from memory location    
|        |             |      |            |                | specified in DS:(E)SI or RSI to I/O       
|        |             |      |            |                | port specified in DX**.                   
| 6E     | OUTSB       | NP   | Valid      | Valid          | Output byte from memory location specified
|        |             |      |            |                | in DS:(E)SI or RSI to I/O port specified  
|        |             |      |            |                | in DX**.                                  
| 6F     | OUTSW       | NP   | Valid      | Valid          | Output word from memory location specified
|        |             |      |            |                | in DS:(E)SI or RSI to I/O port specified  
|        |             |      |            |                | in DX**.                                  
| 6F     | OUTSD       | NP   | Valid      | Valid          | Output doubleword from memory location    
|        |             |      |            |                | specified in DS:(E)SI or RSI to I/O       
|        |             |      |            |                | port specified in DX**.                   
Notes: * See IA-32 Architecture Compatibility section below. ** In 64-bit mode,
only 64-bit (RSI) and 32-bit (ESI) address sizes are supported. In non-64-bit
mode, only 32-bit (ESI) and 16-bit (SI) address sizes are supported.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Copies data from the source operand (second operand) to the I/O port specified
with the destination operand (first operand). The source operand is a memory
location, the address of which is read from either the DS:SI, DS:ESI or the
RSI registers (depending on the address-size attribute of the instruction, 16,
32 or 64, respectively). (The DS segment may be overridden with a segment override
prefix.) The destination operand is an I/O port address (from 0 to 65,535) that
is read from the DX register. The size of the I/O port being accessed (that
is, the size of the source and destination operands) is determined by the opcode
for an 8-bit I/O port or by the operand-size attribute of the instruction for
a 16- or 32-bit I/O port.

At the assembly-code level, two forms of this instruction are allowed: the “explicit-operands”
form and the “nooperands” form. The explicit-operands form (specified with the
OUTS mnemonic) allows the source and destination operands to be specified explicitly.
Here, the source operand should be a symbol that indicates the size of the I/O
port and the source address, and the destination operand must be DX. This explicit-operands
form is provided to allow documentation; however, note that the documentation
provided by this form can be misleading. That is, the source operand symbol
must specify the correct type (size) of the operand (byte, word, or doubleword),
but it does not have to specify the correct location. The location is always
specified by the DS:(E)SI or RSI registers, which must be loaded correctly before
the OUTS instruction is executed.

The no-operands form provides “short forms” of the byte, word, and doubleword
versions of the OUTS instructions. Here also DS:(E)SI is assumed to be the source
operand and DX is assumed to be the destination operand. The size of the I/O
port is specified with the choice of mnemonic: OUTSB (byte), OUTSW (word), or
OUTSD (doubleword).

After the byte, word, or doubleword is transferred from the memory location
to the I/O port, the SI/ESI/RSI register is incremented or decremented automatically
according to the setting of the DF flag in the EFLAGS register. (If the DF flag
is 0, the (E)SI register is incremented; if the DF flag is 1, the SI/ESI/RSI
register is decremented.) The SI/ESI/RSI register is incremented or decremented
by 1 for byte operations, by 2 for word operations, and by 4 for doubleword
operations.

The OUTS, OUTSB, OUTSW, and OUTSD instructions can be preceded by the REP prefix
for block input of ECX bytes, words, or doublewords. See “REP/REPE/REPZ /REPNE/REPNZ - Repeat
String Operation Prefix” in this chapter for a description of the REP prefix.
This instruction is only useful for accessing I/O ports located in the processor's
I/O address space. See Chapter 16, “Input/Output,” in the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1, for more information on
accessing I/O ports in the I/O address space.

In 64-bit mode, the default operand size is 32 bits; operand size is not promoted
by the use of REX.W. In 64-bit mode, the default address size is 64 bits, and
64-bit address is specified using RSI by default. 32-bit address using ESI is
support using the prefix 67H, but 16-bit address is not supported in 64-bit
mode.


IA-32 Architecture Compatibility:
After executing an OUTS, OUTSB, OUTSW, or OUTSD instruction, the Pentium processor
ensures that the EWBE#pin has been sampled active before it begins to execute
the next instruction. (Note that the instruction can be prefetched if EWBE#
is not active, but it will not be executed until the EWBE# pin is sampled active.)
Only the Pentium processor family has the EWBE# pin. For the Pentium 4, Intel®
Xeon®, and P6 processor family, upon execution of an OUTS, OUTSB, OUTSW, or
OUTSD instruction, the processor will not execute the next instruction until
the data phase of the transaction is complete.

Operation:

IF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))
  THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)
     IF (Any I/O Permission Bit for I/O port being accessed = 1)
       THEN (* I/O operation is not allowed *)
          #GP(0);
       ELSE (* I/O operation is allowed *)
          DEST <- SRC; (* Writes to I/O port *)
     FI;
  ELSE (Real Mode or Protected Mode or 64-Bit Mode with CPL ≤ IOPL *)
     DEST <- SRC; (* Writes to I/O port *)
FI;
Byte transfer:
  IF 64-bit mode
     Then
       IF 64-Bit Address Size
          THEN
             IF DF = 0
               THEN RSI <- RSI RSI + 1;
               ELSE RSI <- RSI or - 1;
             FI;
          ELSE (* 32-Bit Address Size *)
             IF DF = 0
               THEN
               ELSE
             FI;
       FI;
     ELSE
       IF DF = 0
          THEN
          ELSE (E)SI <- (E)SI - 1;
       FI;
  FI;
Word transfer:
  IF 64-bit mode
     Then
       IF 64-Bit Address Size
          THEN
             IF DF = 0
               THEN RSI <- RSI RSI + 2;
               ELSE RSI <- RSI or - 2;
             FI;
          ELSE (* 32-Bit Address Size *)
             IF DF = 0
               THEN
               ELSE
             FI;
       FI;
     ELSE
       IF DF = 0
          THEN
          ELSE (E)SI <- (E)SI - 2;
       FI;
  FI;
Doubleword transfer:
  IF 64-bit mode
     Then
       IF 64-Bit Address Size
          THEN
             IF DF = 0
               THEN RSI <- RSI RSI + 4;
               ELSE RSI <- RSI or - 4;
             FI;
          ELSE (* 32-Bit Address Size *)
             IF DF = 0
               THEN
               ELSE
             FI;
       FI;
     ELSE
       IF DF = 0
          THEN
          ELSE (E)SI <- (E)SI - 4;
       FI;
  FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the CPL is greater than (has less       
|                | privilege) the I/O privilege level (IOPL)  
|                | and any of the corresponding I/O permission
|                | bits in TSS for the I/O port being accessed
|                | is 1. If a memory operand effective        
|                | address is outside the limit of the        
|                | CS, DS, ES, FS, or GS segment. If the      
|                | segment register contains a NULL segment   
|                | selector.                                  
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If any of the I/O permission bits in   
|                | the TSS for the I/O port being accessed
|                | is 1.                                  
| #PF(fault-code)| If a page fault occurs.                
| #AC(0)         | If alignment checking is enabled and   
|                | an unaligned memory reference is made. 
| #UD            | If the LOCK prefix is used.            

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the CPL is greater than (has less       
|                | privilege) the I/O privilege level (IOPL)  
|                | and any of the corresponding I/O permission
|                | bits in TSS for the I/O port being accessed
|                | is 1. If the memory address is in a        
|                | non-canonical form.                        
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: PABSB
description:
PABSB/PABSW/PABSD  -  Packed Absolute Value:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 38 1C /r1 PABSB mm1, mm2/m64       | RM   | V/V                   | SSSE3             | Compute the absolute value of bytes     
|                                       |      |                       |                   | in mm2/m64 and store UNSIGNED result    
|                                       |      |                       |                   | in mm1.                                 
| 66 0F 38 1C /r PABSB xmm1, xmm2/m128  | RM   | V/V                   | SSSE3             | Compute the absolute value of bytes     
|                                       |      |                       |                   | in xmm2/m128 and store UNSIGNED result  
|                                       |      |                       |                   | in xmm1.                                
| 0F 38 1D /r1 PABSW mm1, mm2/m64       | RM   | V/V                   | SSSE3             | Compute the absolute value of 16-bit    
|                                       |      |                       |                   | integers in mm2/m64 and store UNSIGNED  
|                                       |      |                       |                   | result in mm1.                          
| 66 0F 38 1D /r PABSW xmm1, xmm2/m128  | RM   | V/V                   | SSSE3             | Compute the absolute value of 16-bit    
|                                       |      |                       |                   | integers in xmm2/m128 and store UNSIGNED
|                                       |      |                       |                   | result in xmm1.                         
| 0F 38 1E /r1 PABSD mm1, mm2/m64       | RM   | V/V                   | SSSE3             | Compute the absolute value of 32-bit    
|                                       |      |                       |                   | integers in mm2/m64 and store UNSIGNED  
|                                       |      |                       |                   | result in mm1.                          
| 66 0F 38 1E /r PABSD xmm1, xmm2/m128  | RM   | V/V                   | SSSE3             | Compute the absolute value of 32-bit    
|                                       |      |                       |                   | integers in xmm2/m128 and store UNSIGNED
|                                       |      |                       |                   | result in xmm1.                         
| VEX.128.66.0F38.WIG 1C /r VPABSB xmm1,| RM   | V/V                   | AVX               | Compute the absolute value of bytes     
| xmm2/m128                             |      |                       |                   | in xmm2/m128 and store UNSIGNED result  
|                                       |      |                       |                   | in xmm1.                                
| VEX.128.66.0F38.WIG 1D /r VPABSW xmm1,| RM   | V/V                   | AVX               | Compute the absolute value of 16- bit   
| xmm2/m128                             |      |                       |                   | integers in xmm2/m128 and store UNSIGNED
|                                       |      |                       |                   | result in xmm1.                         
| VEX.128.66.0F38.WIG 1E /r VPABSD xmm1,| RM   | V/V                   | AVX               | Compute the absolute value of 32- bit   
| xmm2/m128                             |      |                       |                   | integers in xmm2/m128 and store UNSIGNED
|                                       |      |                       |                   | result in xmm1.                         
| VEX.256.66.0F38.WIG 1C /r VPABSB ymm1,| RM   | V/V                   | AVX2              | Compute the absolute value of bytes     
| ymm2/m256                             |      |                       |                   | in ymm2/m256 and store UNSIGNED result  
|                                       |      |                       |                   | in ymm1.                                
| VEX.256.66.0F38.WIG 1D /r VPABSW ymm1,| RM   | V/V                   | AVX2              | Compute the absolute value of 16-bit    
| ymm2/m256                             |      |                       |                   | integers in ymm2/m256 and store UNSIGNED
|                                       |      |                       |                   | result in ymm1.                         
| VEX.256.66.0F38.WIG 1E /r VPABSD ymm1,| RM   | V/V                   | AVX2              | Compute the absolute value of 32-bit    
| ymm2/m256                             |      |                       |                   | integers in ymm2/m256 and store UNSIGNED
|                                       |      |                       |                   | result in ymm1.                         
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
(V)PABSB/W/D computes the absolute value of each data element of the source
operand (the second operand) and stores the UNSIGNED results in the destination
operand (the first operand). (V)PABSB operates on signed bytes, (V)PABSW operates
on 16-bit words, and (V)PABSD operates on signed 32-bit integers. The source
operand can be an MMX register or a 64-bit memory location, or it can be an
XMM register, a YMM register, a 128-bit memory location, or a 256-bit memory
location. The destination operand can be an MMX, an XMM or a YMM register. Both
operands can be MMX registers or XMM registers. When the source operand is a
128-bit memory operand, the operand must be aligned on a 16byte boundary or
a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers. 128-bit Legacy
SSE version: The source operand can be an XMM register or a 128-bit memory location.
The destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.
VEX.128 encoded version: The source operand is an XMM register or 128-bit memory
location. The destination operand is an XMM register. The upper bits (VLMAX-1:128)
of the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register or a 256-bit memory location. The
destination operand is a YMM register.

Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0; otherwise instructions
will #UD.

Operation:

PABSB (with 64 bit operands)
  Unsigned DEST[7:0] <- ABS(SRC[7:0])
  Repeat operation for 2nd through 7th bytes
  Unsigned DEST[63:56] <- ABS(SRC[63:56])
PABSB (with 128 bit operands)
  Unsigned DEST[7:0] <- ABS(SRC[7:.0])
  Repeat operation for 2nd through 15th bytes
  Unsigned DEST[127:120] <- ABS(SRC[127:120])
PABSW (with 64 bit operands)
  Unsigned DEST[15:0] <- ABS(SRC[15:0])
  Repeat operation for 2nd through 3rd 16-bit words
  Unsigned DEST[63:48] <- ABS(SRC[63:48])
PABSW (with 128 bit operands)
  Unsigned DEST[15:0] <- ABS(SRC[15:0])
  Repeat operation for 2nd through 7th 16-bit words
  Unsigned DEST[127:112] <- ABS(SRC[127:112])
PABSD (with 64 bit operands)
  Unsigned DEST[31:0] <- ABS(SRC[31:0])
  Unsigned DEST[63:32] <- ABS(SRC[63:32])
PABSD (with 128 bit operands)
  Unsigned DEST[31:0] <- ABS(SRC[31:0])
  Repeat operation for 2nd through 3rd 32-bit double words
  Unsigned DEST[127:96] <- ABS(SRC[127:96])
PABSB (128-bit Legacy SSE version)
  DEST[127:0] <- BYTE_ABS(SRC)
  DEST[VLMAX-1:128] (Unmodified)
VPABSB (VEX.128 encoded version)
  DEST[127:0] <- BYTE_ABS(SRC)
  DEST[VLMAX-1:128] <- 0
VPABSB (VEX.256 encoded version)
  Unsigned DEST[7:0]<- ABS(SRC[7:.0])
  Repeat operation for 2nd through 31st bytes
  Unsigned DEST[255:248] <- ABS(SRC[255:248])
PABSW (128-bit Legacy SSE version)
  DEST[127:0] <- WORD_ABS(SRC)
  DEST[VLMAX-1:128] (Unmodified)
VPABSW (VEX.128 encoded version)
  DEST[127:0] <- WORD_ABS(SRC)
  DEST[VLMAX-1:128] <- 0
VPABSW (VEX.256 encoded version)
  Unsigned DEST[15:0]<- ABS(SRC[15:0])
  Repeat operation for 2nd through 15th 16-bit words
  Unsigned DEST[255:240] <- ABS(SRC[255:240])
PABSD (128-bit Legacy SSE version)
  DEST[127:0] <- DWORD_ABS(SRC)
  DEST[VLMAX-1:128] (Unmodified)
VPABSD (VEX.128 encoded version)
  DEST[127:0] <- DWORD_ABS(SRC)
  DEST[VLMAX-1:128] <- 0
VPABSD (VEX.256 encoded version)
  Unsigned DEST[31:0] <- ABS(SRC[31:0])
  Repeat operation for 2nd through 7th 32-bit double words
  Unsigned DEST[255:224] <- ABS(SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalents:
| PABSB:   | __m64 _mm_abs_pi8 (__m64 a)         
| (V)PABSB:| __m128i _mm_abs_epi8 (__m128i a)    
| VPABSB:  | __m256i _mm256_abs_epi8 (__m256i a) 
| PABSW:   | __m64 _mm_abs_pi16 (__m64 a)        
| (V)PABSW:| __m128i _mm_abs_epi16 (__m128i a)   
| VPABSW:  | __m256i _mm256_abs_epi16 (__m256i a)
| PABSD:   | __m64 _mm_abs_pi32 (__m64 a)        
| (V)PABSD:| __m128i _mm_abs_epi32 (__m128i a)   
| VPABSD:  | __m256i _mm256_abs_epi32 (__m256i a)

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PACKSSWB
description:
PACKSSWB/PACKSSDW - Pack with Signed Saturation:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 63 /r1 PACKSSWB mm1, mm2/m64      | RM   | V/V                   | MMX               | Converts 4 packed signed word integers  
|                                      |      |                       |                   | from mm1 and from mm2/m64 into 8 packed 
|                                      |      |                       |                   | signed byte integers in mm1 using signed
|                                      |      |                       |                   | saturation.                             
| 66 0F 63 /r PACKSSWB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Converts 8 packed signed word integers  
|                                      |      |                       |                   | from xmm1 and from xxm2/m128 into 16    
|                                      |      |                       |                   | packed signed byte integers in xxm1     
|                                      |      |                       |                   | using signed saturation.                
| 0F 6B /r1 PACKSSDW mm1, mm2/m64      | RM   | V/V                   | MMX               | Converts 2 packed signed doubleword     
|                                      |      |                       |                   | integers from mm1 and from mm2/m64 into 
|                                      |      |                       |                   | 4 packed signed word integers in mm1    
|                                      |      |                       |                   | using signed saturation.                
| 66 0F 6B /r PACKSSDW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Converts 4 packed signed doubleword     
|                                      |      |                       |                   | integers from xmm1 and from xxm2/m128   
|                                      |      |                       |                   | into 8 packed signed word integers in   
|                                      |      |                       |                   | xxm1 using signed saturation.           
| VEX.NDS.128.66.0F.WIG 63 /r VPACKSSWB| RVM  | V/V                   | AVX               | Converts 8 packed signed word integers  
| xmm1,xmm2, xmm3/m128                 |      |                       |                   | from xmm2 and from xmm3/m128 into 16    
|                                      |      |                       |                   | packed signed byte integers in xmm1     
|                                      |      |                       |                   | using signed saturation.                
| VEX.NDS.128.66.0F.WIG 6B /r VPACKSSDW| RVM  | V/V                   | AVX               | Converts 4 packed signed doubleword     
| xmm1,xmm2, xmm3/m128                 |      |                       |                   | integers from xmm2 and from xmm3/m128   
|                                      |      |                       |                   | into 8 packed signed word integers in   
|                                      |      |                       |                   | xmm1 using signed saturation.           
| VEX.NDS.256.66.0F.WIG 63 /r VPACKSSWB| RVM  | V/V                   | AVX2              | Converts 16 packed signed word integers 
| ymm1, ymm2, ymm3/m256                |      |                       |                   | from ymm2 and from ymm3/m256 into 32    
|                                      |      |                       |                   | packed signed byte integers in ymm1     
|                                      |      |                       |                   | using signed saturation.                
| VEX.NDS.256.66.0F.WIG 6B /r VPACKSSDW| RVM  | V/V                   | AVX2              | Converts 8 packed signed doubleword     
| ymm1, ymm2, ymm3/m256                |      |                       |                   | integers from ymm2 and from ymm3/m256   
|                                      |      |                       |                   | into 16 packed signed word integers     
|                                      |      |                       |                   | in ymm1using signed saturation.         
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts packed signed word integers into packed signed byte integers (PACKSSWB)
or converts packed signed doubleword integers into packed signed word integers
(PACKSSDW), using saturation to handle overflow conditions. See Figure 4-2 for
an example of the packing operation.

| 64-Bit SRC                           | 64-Bit DEST
| C                                    | A          
| D'64-Bit DEST                        | A'         
| Operation of the PACKSSDW Instruction| Figure 4-2.
| Using 64-bit Operands                |            
The (V)PACKSSWB instruction converts 4, 8 or 16 signed word integers from the
destination operand (first operand) and 4, 8 or 16 signed word integers from
the source operand (second operand) into 8, 16 or 32 signed byte integers and
stores the result in the destination operand. If a signed word integer value
is beyond the range of a signed byte integer (that is, greater than 7FH for
a positive integer or greater than 80H for a negative integer), the saturated
signed byte integer value of 7FH or 80H, respectively, is stored in the destination.

The (V)PACKSSDW instruction packs 2, 4 or 8 signed doublewords from the destination
operand (first operand) and 2, 4 or 8 signed doublewords from the source operand
(second operand) into 4, 8 or 16 signed words in the destination operand (see
Figure 4-2). If a signed doubleword integer value is beyond the range of a signed
word (that is, greater than 7FFFH for a positive integer or greater than 8000H
for a negative integer), the saturated signed word integer value of 7FFFH or
8000H, respectively, is stored into the destination.

The (V)PACKSSWB and (V)PACKSSDW instructions operate on either 64-bit, 128-bit
operands or 256-bit operands. When operating on 64-bit operands, the destination
operand must be an MMX technology register and the source operand can be either
an MMX technology register or a 64-bit memory location. In 64-bit mode, using
a REX prefix in the form of REX.R permits this instruction to access additional
registers (XMM8-XMM15). 128-bit Legacy SSE version: The first source operand
is an XMM register. The second operand can be an XMM register or a 128-bit memory
location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: The first source operand is an XMM
register. The second source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PACKSSWB (with 64-bit operands)
  DEST[7:0] <- SaturateSignedWordToSignedByte DEST[15:0];
  DEST[15:8] <- SaturateSignedWordToSignedByte DEST[31:16];
  DEST[23:16] <- SaturateSignedWordToSignedByte DEST[47:32];
  DEST[31:24] <- SaturateSignedWordToSignedByte DEST[63:48];
  DEST[39:32] <- SaturateSignedWordToSignedByte SRC[15:0];
  DEST[47:40] <- SaturateSignedWordToSignedByte SRC[31:16];
  DEST[55:48] <- SaturateSignedWordToSignedByte SRC[47:32];
  DEST[63:56] <- SaturateSignedWordToSignedByte SRC[63:48];
PACKSSDW (with 64-bit operands)
  DEST[15:0] <- SaturateSignedDoublewordToSignedWord DEST[31:0];
  DEST[31:16] <- SaturateSignedDoublewordToSignedWord DEST[63:32];
  DEST[47:32] <- SaturateSignedDoublewordToSignedWord SRC[31:0];
  DEST[63:48] <- SaturateSignedDoublewordToSignedWord SRC[63:32];
PACKSSWB instruction (128-bit Legacy SSE version)
  DEST[7:0]<- SaturateSignedWordToSignedByte (DEST[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (DEST[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (DEST[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (DEST[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (DEST[79:64]);
  DEST[47:40] <-SaturateSignedWordToSignedByte (DEST[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (DEST[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (DEST[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC[127:112]);
PACKSSDW instruction (128-bit Legacy SSE version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (DEST[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (DEST[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (DEST[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (DEST[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC[127:96]);
VPACKSSWB instruction (VEX.128 encoded version)
  DEST[7:0]<- SaturateSignedWordToSignedByte (SRC1[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);
  DEST[VLMAX-1:128]<- 0;
VPACKSSDW instruction (VEX.128 encoded version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);
  DEST[VLMAX-1:128]<- 0;
VPACKSSWB instruction (VEX.256 encoded version)
  DEST[7:0]<- SaturateSignedWordToSignedByte (SRC1[15:0]);
  DEST[15:8] <- SaturateSignedWordToSignedByte (SRC1[31:16]);
  DEST[23:16] <- SaturateSignedWordToSignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToSignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToSignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToSignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToSignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToSignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToSignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToSignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToSignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToSignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToSignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToSignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToSignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToSignedByte (SRC2[127:112]);
  DEST[135:128]<- SaturateSignedWordToSignedByte (SRC1[143:128]);
  DEST[143:136] <- SaturateSignedWordToSignedByte (SRC1[159:144]);
  DEST[151:144] <- SaturateSignedWordToSignedByte (SRC1[175:160]);
  DEST[159:152] <- SaturateSignedWordToSignedByte (SRC1[191:176]);
  DEST[167:160] <- SaturateSignedWordToSignedByte (SRC1[207:192]);
  DEST[175:168] <- SaturateSignedWordToSignedByte (SRC1[223:208]);
  DEST[183:176] <- SaturateSignedWordToSignedByte (SRC1[239:224]);
  DEST[191:184] <- SaturateSignedWordToSignedByte (SRC1[255:240]);
  DEST[199:192] <- SaturateSignedWordToSignedByte (SRC2[143:128]);
  DEST[207:200] <- SaturateSignedWordToSignedByte (SRC2[159:144]);
  DEST[215:208] <- SaturateSignedWordToSignedByte (SRC2[175:160]);
  DEST[223:216] <- SaturateSignedWordToSignedByte (SRC2[191:176]);
  DEST[231:224] <- SaturateSignedWordToSignedByte (SRC2[207:192]);
  DEST[239:232] <- SaturateSignedWordToSignedByte (SRC2[223:208]);
  DEST[247:240] <- SaturateSignedWordToSignedByte (SRC2[239:224]);
  DEST[255:248] <- SaturateSignedWordToSignedByte (SRC2[255:240]);
VPACKSSDW instruction (VEX.256 encoded version)
  DEST[15:0] <- SaturateSignedDwordToSignedWord (SRC1[31:0]);
  DEST[31:16] <- SaturateSignedDwordToSignedWord (SRC1[63:32]);
  DEST[47:32] <- SaturateSignedDwordToSignedWord (SRC1[95:64]);
  DEST[63:48] <- SaturateSignedDwordToSignedWord (SRC1[127:96]);
  DEST[79:64] <- SaturateSignedDwordToSignedWord (SRC2[31:0]);
  DEST[95:80] <- SaturateSignedDwordToSignedWord (SRC2[63:32]);
  DEST[111:96] <- SaturateSignedDwordToSignedWord (SRC2[95:64]);
  DEST[127:112] <- SaturateSignedDwordToSignedWord (SRC2[127:96]);
  DEST[143:128] <- SaturateSignedDwordToSignedWord (SRC1[159:128]);
  DEST[159:144] <- SaturateSignedDwordToSignedWord (SRC1[191:160]);
  DEST[175:160] <- SaturateSignedDwordToSignedWord (SRC1[223:192]);
  DEST[191:176] <- SaturateSignedDwordToSignedWord (SRC1[255:224]);
  DEST[207:192] <- SaturateSignedDwordToSignedWord (SRC2[159:128]);
  DEST[223:208] <- SaturateSignedDwordToSignedWord (SRC2[191:160]);
  DEST[239:224] <- SaturateSignedDwordToSignedWord (SRC2[223:192]);
  DEST[255:240] <- SaturateSignedDwordToSignedWord (SRC2[255:224]);

Intel C/C++ Compiler Intrinsic Equivalents:
| PACKSSWB:   | __m64 _mm_packs_pi16(__m64 m1, __m64  
|             | m2)                                   
| (V)PACKSSWB:| __m128i _mm_packs_epi16(__m128i m1,   
|             | __m128i m2)                           
| VPACKSSWB:  | __m256i _mm256_packs_epi16(__m256i m1,
|             | __m256i m2)                           
| PACKSSDW:   | __m64 _mm_packs_pi32 (__m64 m1, __m64 
|             | m2)                                   
| (V)PACKSSDW:| __m128i _mm_packs_epi32(__m128i m1,   
|             | __m128i m2)                           
| VPACKSSDW:  | __m256i _mm256_packs_epi32(__m256i m1,
|             | __m256i m2)                           

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PACKUSDW
description:
PACKUSDW  -  Pack with Unsigned Saturation:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 66 0F 38 2B /r PACKUSDW xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Convert 4 packed signed doubleword integers
|                                        |      |                       |                   | from xmm1 and 4 packed signed doubleword   
|                                        |      |                       |                   | integers from xmm2/m128 into 8 packed      
|                                        |      |                       |                   | unsigned word integers in xmm1 using       
|                                        |      |                       |                   | unsigned saturation.                       
| VEX.NDS.128.66.0F38.WIG 2B /r VPACKUSDW| RVM  | V/V                   | AVX               | Convert 4 packed signed doubleword integers
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | from xmm2 and 4 packed signed doubleword   
|                                        |      |                       |                   | integers from xmm3/m128 into 8 packed      
|                                        |      |                       |                   | unsigned word integers in xmm1 using       
|                                        |      |                       |                   | unsigned saturation.                       
| VEX.NDS.256.66.0F38.WIG 2B /r VPACKUSDW| RVM  | V/V                   | AVX2              | Convert 8 packed signed doubleword integers
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | from ymm2 and 8 packed signed doubleword   
|                                        |      |                       |                   | integers from ymm3/m128 into 16 packed     
|                                        |      |                       |                   | unsigned word integers in ymm1 using       
|                                        |      |                       |                   | unsigned saturation.                       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts packed signed doubleword integers into packed unsigned word integers
using unsigned saturation to

| handle overflow conditions. greater          | If the signed doubleword value is beyond
| than FFFFH or less than 0000H), the          | the range of an unsigned word (that     
| saturated unsigned word integer value        | is,                                     
| of FFFFH or 0000H, respectively, is          |                                         
| stored in the destination. 128-bit Legacy    |                                         
| SSE version: The first source operand        |                                         
| is an XMM register. The second operand       |                                         
| can be an XMM register or a 128-bit          |                                         
| memory location. The destination is          |                                         
| not distinct from the first source XMM       |                                         
| register and the upper bits (VLMAX-1:128)    |                                         
| of the corresponding YMM register destination|                                         
| are unmodified. VEX.128 encoded version:     |                                         
| The first source operand is an XMM register. |                                         
| The second source operand is an XMM          |                                         
| register or 128-bit memory location.         |                                         
| The destination operand is an XMM register.  |                                         
| The upper bits (VLMAX-1:128) of the          |                                         
| corresponding YMM register destination       |                                         
| are zeroed. VEX.256 encoded version:         |                                         
| The first source operand is a YMM register.  |                                         
| The second source operand is a YMM register  |                                         
| or a 256-bit memory location. The destination|                                         
| operand is a YMM register. Note: VEX.L       |                                         
| must be 0, otherwise the instruction         |                                         
| will #UD.                                    |                                         
Operation:

PACKUSDW (Legacy SSE instruction)
TMP[15:0] <- (DEST[31:0] < 0) ? 0 : DEST[15:0];
DEST[15:0] <- (DEST[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (DEST[63:32] < 0) ? 0 : DEST[47:32];
DEST[31:16] <- (DEST[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (DEST[95:64] < 0) ? 0 : DEST[79:64];
DEST[47:32] <- (DEST[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (DEST[127:96] < 0) ? 0 : DEST[111:96];
DEST[63:48] <- (DEST[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC[31:0] < 0) ? 0 : SRC[15:0];
DEST[63:48] <- (SRC[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC[63:32] < 0) ? 0 : SRC[47:32];
DEST[95:80] <- (SRC[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC[95:64] < 0) ? 0 : SRC[79:64];
DEST[111:96] <- (SRC[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (SRC[127:96] < 0) ? 0 : SRC[111:96];
DEST[127:112] <- (SRC[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
PACKUSDW (VEX.128 encoded version)
TMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[63:48] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[127:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112];
DEST[VLMAX-1:128] <- 0;
VPACKUSDW (VEX.256 encoded version)
TMP[15:0] <- (SRC1[31:0] < 0) ? 0 : SRC1[15:0];
DEST[15:0] <- (SRC1[31:0] > FFFFH) ? FFFFH : TMP[15:0] ;
TMP[31:16] <- (SRC1[63:32] < 0) ? 0 : SRC1[47:32];
DEST[31:16] <- (SRC1[63:32] > FFFFH) ? FFFFH : TMP[31:16] ;
TMP[47:32] <- (SRC1[95:64] < 0) ? 0 : SRC1[79:64];
DEST[47:32] <- (SRC1[95:64] > FFFFH) ? FFFFH : TMP[47:32] ;
TMP[63:48] <- (SRC1[127:96] < 0) ? 0 : SRC1[111:96];
DEST[63:48] <- (SRC1[127:96] > FFFFH) ? FFFFH : TMP[63:48] ;
TMP[79:64] <- (SRC2[31:0] < 0) ? 0 : SRC2[15:0];
DEST[63:48] <- (SRC2[31:0] > FFFFH) ? FFFFH : TMP[79:64] ;
TMP[95:80] <- (SRC2[63:32] < 0) ? 0 : SRC2[47:32];
DEST[95:80] <- (SRC2[63:32] > FFFFH) ? FFFFH : TMP[95:80] ;
TMP[111:96] <- (SRC2[95:64] < 0) ? 0 : SRC2[79:64];
DEST[111:96] <- (SRC2[95:64] > FFFFH) ? FFFFH : TMP[111:96] ;
TMP[127:112] <- (SRC2[127:96] < 0) ? 0 : SRC2[111:96];
DEST[128:112] <- (SRC2[127:96] > FFFFH) ? FFFFH : TMP[127:112] ;
TMP[143:128] <- (SRC1[159:128] < 0) ? 0 : SRC1[143:128];
DEST[143:128] <- (SRC1[159:128] > FFFFH) ? FFFFH : TMP[143:128] ;
TMP[159:144] <- (SRC1[191:160] < 0) ? 0 : SRC1[175:160];
DEST[159:144] <- (SRC1[191:160] > FFFFH) ? FFFFH : TMP[159:144] ;
TMP[175:160] <- (SRC1[223:192] < 0) ? 0 : SRC1[207:192];
DEST[175:160] <- (SRC1[223:192] > FFFFH) ? FFFFH : TMP[175:160] ;
TMP[191:176] <- (SRC1[255:224] < 0) ? 0 : SRC1[239:224];
DEST[191:176] <- (SRC1[255:224] > FFFFH) ? FFFFH : TMP[191:176] ;
TMP[207:192] <- (SRC2[159:128] < 0) ? 0 : SRC2[143:128];
DEST[207:192] <- (SRC2[159:128] > FFFFH) ? FFFFH : TMP[207:192] ;
TMP[223:208] <- (SRC2[191:160] < 0) ? 0 : SRC2[175:160];
DEST[223:208] <- (SRC2[191:160] > FFFFH) ? FFFFH : TMP[223:208] ;
TMP[239:224] <- (SRC2[223:192] < 0) ? 0 : SRC2[207:192];
DEST[239:224] <- (SRC2[223:192] > FFFFH) ? FFFFH : TMP[239:224] ;
TMP[255:240] <- (SRC2[255:224] < 0) ? 0 : SRC2[239:224];
DEST[255:240] <- (SRC2[255:224] > FFFFH) ? FFFFH : TMP[255:240] ;

Intel C/C++ Compiler Intrinsic Equivalent:
(V)PACKUSDW: __m128i _mm_packus_epi32(__m128i m1, __m128i m2);

| VPACKUSDW:| __m256i _mm256_packus_epi32(__m256i
|           | m1, __m256i m2);                   

Flags Affected:
None.


SIMD Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PACKUSWB
description:
PACKUSWB - Pack with Unsigned Saturation:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F 67 /r1 PACKUSWB mm, mm/m64        | RM   | V/V                   | MMX               | Converts 4 signed word integers from     
|                                      |      |                       |                   | mm and 4 signed word integers from mm/m64
|                                      |      |                       |                   | into 8 unsigned byte integers in mm      
|                                      |      |                       |                   | using unsigned saturation.               
| 66 0F 67 /r PACKUSWB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Converts 8 signed word integers from     
|                                      |      |                       |                   | xmm1 and 8 signed word integers from     
|                                      |      |                       |                   | xmm2/m128 into 16 unsigned byte integers 
|                                      |      |                       |                   | in xmm1 using unsigned saturation.       
| VEX.NDS.128.66.0F.WIG 67 /r VPACKUSWB| RVM  | V/V                   | AVX               | Converts 8 signed word integers from     
| xmm1, xmm2, xmm3/m128                |      |                       |                   | xmm2 and 8 signed word integers from     
|                                      |      |                       |                   | xmm3/m128 into 16 unsigned byte integers 
|                                      |      |                       |                   | in xmm1 using unsigned saturation.       
| VEX.NDS.256.66.0F.WIG 67 /r VPACKUSWB| RVM  | V/V                   | AVX2              | Converts 16 signed word integers from    
| ymm1, ymm2, ymm3/m256                |      |                       |                   | ymm2 and 16signed word integers from     
|                                      |      |                       |                   | ymm3/m256 into 32 unsigned byte integers 
|                                      |      |                       |                   | in ymm1 using unsigned saturation.       
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Converts 4, 8 or 16 signed word integers from the destination operand (first
operand) and 4, 8 or 16 signed word integers from the source operand (second
operand) into 8, 16 or 32 unsigned byte integers and stores the result in the
destination operand. (See Figure 4-2 for an example of the packing operation.)
If a signed word integer value is beyond the range of an unsigned byte integer
(that is, greater than FFH or less than 00H), the saturated unsigned byte integer
value of FFH or 00H, respectively, is stored in the destination.

The PACKUSWB instruction operates on either 64-bit, 128-bit or 256-bit operands.
When operating on 64-bit operands, the destination operand must be an MMX technology
register and the source operand can be either an MMX technology register or
a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of
REX.R permits this instruction to access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The first source operand is an XMM register. The
second operand can be an XMM register or a 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register.

Operation:

PACKUSWB (with 64-bit operands)
  DEST[7:0] <- SaturateSignedWordToUnsignedByte DEST[15:0];
  DEST[15:8] <- SaturateSignedWordToUnsignedByte DEST[31:16];
  DEST[23:16] <- SaturateSignedWordToUnsignedByte DEST[47:32];
  DEST[31:24] <- SaturateSignedWordToUnsignedByte DEST[63:48];
  DEST[39:32] <- SaturateSignedWordToUnsignedByte SRC[15:0];
  DEST[47:40] <- SaturateSignedWordToUnsignedByte SRC[31:16];
  DEST[55:48] <- SaturateSignedWordToUnsignedByte SRC[47:32];
  DEST[63:56] <- SaturateSignedWordToUnsignedByte SRC[63:48];
PACKUSWB (Legacy SSE instruction)
  DEST[7:0]<-SaturateSignedWordToUnsignedByte (DEST[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (DEST[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (DEST[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (DEST[63:48]);
  DEST[39:32] <- SaturateSignedWordToUnsignedByte (DEST[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (DEST[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (DEST[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (DEST[127:112]);
  DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC[95:80]);
  DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC[111:96]);
  DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC[127:112]);
PACKUSWB (VEX.128 encoded version)
  DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);
  DEST[39:32] <- SaturateSignedWordToUnsignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);
  DEST[71:64] <- SaturateSignedWordToUnsignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);
  DEST[VLMAX-1:128] <- 0;
VPACKUSWB (VEX.256 encoded version)
  DEST[7:0]<- SaturateSignedWordToUnsignedByte (SRC1[15:0]);
  DEST[15:8] <-SaturateSignedWordToUnsignedByte (SRC1[31:16]);
  DEST[23:16] <-SaturateSignedWordToUnsignedByte (SRC1[47:32]);
  DEST[31:24] <- SaturateSignedWordToUnsignedByte (SRC1[63:48]);
  DEST[39:32] <-SaturateSignedWordToUnsignedByte (SRC1[79:64]);
  DEST[47:40] <- SaturateSignedWordToUnsignedByte (SRC1[95:80]);
  DEST[55:48] <- SaturateSignedWordToUnsignedByte (SRC1[111:96]);
  DEST[63:56] <- SaturateSignedWordToUnsignedByte (SRC1[127:112]);
  DEST[71:64] <-SaturateSignedWordToUnsignedByte (SRC2[15:0]);
  DEST[79:72] <- SaturateSignedWordToUnsignedByte (SRC2[31:16]);
  DEST[87:80] <- SaturateSignedWordToUnsignedByte (SRC2[47:32]);
  DEST[95:88] <- SaturateSignedWordToUnsignedByte (SRC2[63:48]);
  DEST[103:96] <- SaturateSignedWordToUnsignedByte (SRC2[79:64]);
  DEST[111:104] <- SaturateSignedWordToUnsignedByte (SRC2[95:80]);
  DEST[119:112] <- SaturateSignedWordToUnsignedByte (SRC2[111:96]);
  DEST[127:120] <- SaturateSignedWordToUnsignedByte (SRC2[127:112]);
  DEST[135:128]<- SaturateSignedWordToUnsignedByte (SRC1[143:128]);
  DEST[143:136] <-SaturateSignedWordToUnsignedByte (SRC1[159:144]);
  DEST[151:144] <-SaturateSignedWordToUnsignedByte (SRC1[175:160]);
  DEST[159:152] <-SaturateSignedWordToUnsignedByte (SRC1[191:176]);
  DEST[167:160] <- SaturateSignedWordToUnsignedByte (SRC1[207:192]);
  DEST[175:168] <- SaturateSignedWordToUnsignedByte (SRC1[223:208]);
  DEST[183:176] <- SaturateSignedWordToUnsignedByte (SRC1[239:224]);
  DEST[191:184] <- SaturateSignedWordToUnsignedByte (SRC1[255:240]);
  DEST[199:192] <- SaturateSignedWordToUnsignedByte (SRC2[143:128]);
  DEST[207:200] <- SaturateSignedWordToUnsignedByte (SRC2[159:144]);
  DEST[215:208] <- SaturateSignedWordToUnsignedByte (SRC2[175:160]);
  DEST[223:216] <- SaturateSignedWordToUnsignedByte (SRC2[191:176]);
  DEST[231:224] <- SaturateSignedWordToUnsignedByte (SRC2[207:192]);
  DEST[239:232] <- SaturateSignedWordToUnsignedByte (SRC2[223:208]);
  DEST[247:240] <- SaturateSignedWordToUnsignedByte (SRC2[239:224]);
  DEST[255:248] <- SaturateSignedWordToUnsignedByte (SRC2[255:240]);

Intel C/C++ Compiler Intrinsic Equivalent:
| PACKUSWB:   | __m64 _mm_packs_pu16(__m64 m1, __m64
|             | m2)                                 
| (V)PACKUSWB:| __m128i _mm_packus_epi16(__m128i m1,
|             | __m128i m2)                         
| VPACKUSWB:  | __m256i _mm256_packus_epi16(__m256i 
|             | m1, __m256i m2);                    

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PADDB
description:
PADDB/PADDW/PADDD - Add Packed Integers:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F FC /r1 PADDB mm, mm/m64              | RM   | V/V                   | MMX               | Add packed byte integers from mm/m64   
|                                         |      |                       |                   | and mm.                                
| 66 0F FC /r PADDB xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Add packed byte integers from xmm2/m128
|                                         |      |                       |                   | and xmm1.                              
| 0F FD /r1 PADDW mm, mm/m64              | RM   | V/V                   | MMX               | Add packed word integers from mm/m64   
|                                         |      |                       |                   | and mm.                                
| 66 0F FD /r PADDW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Add packed word integers from xmm2/m128
|                                         |      |                       |                   | and xmm1.                              
| 0F FE /r1 PADDD mm, mm/m64              | RM   | V/V                   | MMX               | Add packed doubleword integers from    
|                                         |      |                       |                   | mm/m64 and mm.                         
| 66 0F FE /r PADDD xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Add packed doubleword integers from    
|                                         |      |                       |                   | xmm2/m128 and xmm1.                    
| VEX.NDS.128.66.0F.WIG FC /r VPADDB xmm1,| RVM  | V/V                   | AVX               | Add packed byte integers from xmm3/m128
| xmm2, xmm3/m128                         |      |                       |                   | and xmm2.                              
| VEX.NDS.128.66.0F.WIG FD /r VPADDW xmm1,| RVM  | V/V                   | AVX               | Add packed word integers from xmm3/m128
| xmm2, xmm3/m128                         |      |                       |                   | and xmm2.                              
| VEX.NDS.128.66.0F.WIG FE /r VPADDD xmm1,| RVM  | V/V                   | AVX               | Add packed doubleword integers from    
| xmm2, xmm3/m128                         |      |                       |                   | xmm3/m128 and xmm2.                    
| VEX.NDS.256.66.0F.WIG FC /r VPADDB ymm1,| RVM  | V/V                   | AVX2              | Add packed byte integers from ymm2,    
| ymm2, ymm3/m256                         |      |                       |                   | and ymm3/m256 and store in ymm1.       
| VEX.NDS.256.66.0F.WIG FD /r VPADDW ymm1,| RVM  | V/V                   | AVX2              | Add packed word integers from ymm2,    
| ymm2, ymm3/m256                         |      |                       |                   | ymm3/m256 and store in ymm1.           
| VEX.NDS.256.66.0F.WIG FE /r VPADDD ymm1,| RVM  | V/V                   | AVX2              | Add packed doubleword integers from    
| ymm2, ymm3/m256                         |      |                       |                   | ymm2, ymm3/m256 and store in ymm1.     
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD add of the packed integers from the source operand (second operand)
and the destination operand (first operand), and stores the packed integer results
in the destination operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1, for an illustration of a SIMD operation.
Overflow is handled with wraparound, as described in the following paragraphs.
Adds the packed byte, word, doubleword, or quadword integers in the first source
operand to the second source operand and stores the result in the destination
operand. When a result is too large to be represented in the

8/16/32 integer (overflow), the result is wrapped around and the low bits are
written to the destination element (that is, the carry is ignored).

Note that these instructions can operate on either unsigned or signed (two's
complement notation) integers; however, it does not set bits in the EFLAGS register
to indicate overflow and/or a carry. To prevent undetected overflow conditions,
software must control the ranges of the values operated on.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands.
When operating on 64-bit operands, the destination operand must be an MMX technology
register and the source operand can be either an MMX technology register or
a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of
REX.R permits this instruction to access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The first source operand is an XMM register. The
second operand can be an XMM register or a 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PADDB (with 64-bit operands)
  DEST[7:0] <- DEST[7:0] + SRC[7:0];
  (* Repeat add operation for 2nd through 7th byte *)
  DEST[63:56] <- DEST[63:56] + SRC[63:56];
PADDB (with 128-bit operands)
  DEST[7:0] <- DEST[7:0] + SRC[7:0];
  (* Repeat add operation for 2nd through 14th byte *)
  DEST[127:120] <- DEST[111:120] + SRC[127:120];
VPADDB (VEX.128 encoded version)
  DEST[7:0] <- SRC1[7:0]+SRC2[7:0]
  DEST[15:8] <- SRC1[15:8]+SRC2[15:8]
  DEST[23:16] <- SRC1[23:16]+SRC2[23:16]
  DEST[31:24] <- SRC1[31:24]+SRC2[31:24]
  DEST[39:32] <- SRC1[39:32]+SRC2[39:32]
  DEST[47:40] <- SRC1[47:40]+SRC2[47:40]
  DEST[55:48] <- SRC1[55:48]+SRC2[55:48]
  DEST[63:56] <- SRC1[63:56]+SRC2[63:56]
  DEST[71:64] <- SRC1[71:64]+SRC2[71:64]
  DEST[79:72] <- SRC1[79:72]+SRC2[79:72]
  DEST[87:80] <- SRC1[87:80]+SRC2[87:80]
  DEST[95:88] <- SRC1[95:88]+SRC2[95:88]
  DEST[103:96] <- SRC1[103:96]+SRC2[103:96]
  DEST[111:104] <- SRC1[111:104]+SRC2[111:104]
  DEST[119:112] <- SRC1[119:112]+SRC2[119:112]
  DEST[127:120] <- SRC1[127:120]+SRC2[127:120]
  DEST[VLMAX-1:128] <- 0
VPADDB (VEX.256 encoded instruction)
  DEST[7:0]<- SRC1[7:0] + SRC2[7:0];
  (* Repeat add operation for 2nd through 31th byte *)
  DEST[255:248]<- SRC1[255:248] + SRC2[255:248];
PADDW (with 64-bit operands)
  DEST[15:0] <- DEST[15:0] + SRC[15:0];
  (* Repeat add operation for 2nd and 3th word *)
  DEST[63:48] <- DEST[63:48] + SRC[63:48];
PADDW (with 128-bit operands)
  DEST[15:0]
  (* Repeat add operation for 2nd through 7th word *)
  DEST[127:112] <- DEST[127:112] + SRC[127:112];
VPADDW (VEX.128 encoded version)
  DEST[15:0] <- SRC1[15:0]+SRC2[15:0]
  DEST[31:16] <- SRC1[31:16]+SRC2[31:16]
  DEST[47:32] <- SRC1[47:32]+SRC2[47:32]
  DEST[63:48] <- SRC1[63:48]+SRC2[63:48]
  DEST[79:64] <- SRC1[79:64]+SRC2[79:64]
  DEST[95:80] <- SRC1[95:80]+SRC2[95:80]
  DEST[111:96] <- SRC1[111:96]+SRC2[111:96]
  DEST[127:112] <- SRC1[127:112]+SRC2[127:112]
  DEST[VLMAX-1:128] <- 0
VPADDW (VEX.256 encoded instruction)
  DEST[15:0] <- SRC1[15:0] + SRC2[15:0];
  (* Repeat add operation for 2nd through 15th word *)
  DEST[255:240]<- SRC1[255:240] + SRC2[255:240];
PADDD (with 64-bit operands)
  DEST[31:0] <- DEST[31:0] + SRC[31:0];
  DEST[63:32] <- DEST[63:32] + SRC[63:32];
PADDD (with 128-bit operands)
  DEST[31:0] <- DEST[31:0]
  (* Repeat add operation for 2nd and 3th doubleword *)
  DEST[127:96] <- DEST[127:96] + SRC[127:96];
VPADDD (VEX.128 encoded version)
  DEST[31:0] <- SRC1[31:0]+SRC2[31:0]
  DEST[63:32] <- SRC1[63:32]+SRC2[63:32]
  DEST[95:64] <- SRC1[95:64]+SRC2[95:64]
  DEST[127:96] <- SRC1[127:96]+SRC2[127:96]
  DEST[VLMAX-1:128] <- 0
VPADDD (VEX.256 encoded instruction)
  DEST[31:0]<- SRC1[31:0]
  (* Repeat add operation for 2nd and 7th doubleword *)
  DEST[255:224] <- SRC1[255:224] + SRC2[255:224];

Intel C/C++ Compiler Intrinsic Equivalents:
| PADDB:   | __m64 _mm_add_pi8(__m64 m1, __m64 m2)     
| (V)PADDB:| __m128i _mm_add_epi8 (__m128ia,__m128ib   
|          | )                                         
| VPADDB:  | __m256i _mm256_add_epi8 (__m256ia,__m256i 
|          | b )                                       
| PADDW:   | __m64 _mm_add_pi16(__m64 m1, __m64 m2)    
| (V)PADDW:| __m128i _mm_add_epi16 ( __m128i a, __m128i
|          | b)                                        
| VPADDW:  | __m256i _mm256_add_epi16 ( __m256i a,     
|          | __m256i b)                                
| PADDD:   | __m64 _mm_add_pi32(__m64 m1, __m64 m2)    
| (V)PADDD:| __m128i _mm_add_epi32 ( __m128i a, __m128i
|          | b)                                        
| VPADDD:  | __m256i _mm256_add_epi32 ( __m256i a,     
|          | __m256i b)                                

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PADDQ
description:
PADDQ - Add Packed Quadword Integers:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F D4 /r1 PADDQ mm1, mm2/m64            | RM   | V/V                   | SSE2              | Add quadword integer mm2/m64 to mm1.   
| 66 0F D4 /r PADDQ xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Add packed quadword integers xmm2/m128 
|                                         |      |                       |                   | to xmm1.                               
| VEX.NDS.128.66.0F.WIG D4 /r VPADDQ xmm1,| RVM  | V/V                   | AVX               | Add packed quadword integers xmm3/m128 
| xmm2, xmm3/m128                         |      |                       |                   | and xmm2.                              
| VEX.NDS.256.66.0F.WIG D4 /r VPADDQ ymm1,| RVM  | V/V                   | AVX2              | Add packed quadword integers from ymm2,
| ymm2, ymm3/m256                         |      |                       |                   | ymm3/m256 and store in ymm1.           
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Adds the first operand (destination operand) to the second operand (source operand)
and stores the result in the destination operand. The source operand can be
a quadword integer stored in an MMX technology register or a 64bit memory location,
or it can be two packed quadword integers stored in an XMM register or an 128-bit
memory location. The destination operand can be a quadword integer stored in
an MMX technology register or two packed quadword integers stored in an XMM
register. When packed quadword operands are used, a SIMD add is performed. When
a quadword result is too large to be represented in 64 bits (overflow), the
result is wrapped around and the low 64 bits are written to the destination
element (that is, the carry is ignored).

Note that the (V)PADDQ instruction can operate on either unsigned or signed
(two's complement notation) integers; however, it does not set bits in the EFLAGS
register to indicate overflow and/or a carry. To prevent undetected overflow
conditions, software must control the ranges of the values operated on.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
first source operand is an XMM register. The second operand can be an XMM register
or a 128-bit memory location. The destination is not distinct from the first
source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM
register destination are unmodified. VEX.128 encoded version: The first source
operand is an XMM register. The second source operand is an XMM register or
128-bit memory location. The destination operand is an XMM register. The upper
bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second
source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PADDQ (with 64-Bit operands)
  DEST[63:0] <- DEST[63:0] + SRC[63:0];
PADDQ (with 128-Bit operands)
  DEST[63:0] <- DEST[63:0] + SRC[63:0];
  DEST[127:64] <- DEST[127:64] + SRC[127:64];
VPADDQ (VEX.128 encoded instruction)
  DEST[63:0]<- SRC1[63:0]
  DEST[127:64] <- SRC1[127:64] + SRC2[127:64];
  DEST[VLMAX-1:128] <- 0;
VPADDQ (VEX.256 encoded instruction)
  DEST[63:0]<- SRC1[63:0]
  DEST[127:64] <- SRC1[127:64] + SRC2[127:64];
  DEST[191:128]<- SRC1[191:128]
  DEST[255:192] <- SRC1[255:192] + SRC2[255:192];

Intel C/C++ Compiler Intrinsic Equivalents:
| PADDQ:   | __m64 _mm_add_si64 (__m64 a, __m64 b)     
| (V)PADDQ:| __m128i _mm_add_epi64 ( __m128i a, __m128i
|          | b)                                        
| VPADDQ:  | __m256i _mm256_add_epi64 ( __m256i a,     
|          | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PADDSB
description:
PADDSB/PADDSW - Add Packed Signed Integers with Signed Saturation:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F EC /r1 PADDSB mm, mm/m64        | RM   | V/V                   | MMX               | Add packed signed byte integers from       
|                                    |      |                       |                   | mm/m64 and mm and saturate the results.    
| 66 0F EC /r PADDSB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Add packed signed byte integers from       
|                                    |      |                       |                   | xmm2/m128 and xmm1 saturate the results.   
| 0F ED /r1 PADDSW mm, mm/m64        | RM   | V/V                   | MMX               | Add packed signed word integers from       
|                                    |      |                       |                   | mm/m64 and mm and saturate the results.    
| 66 0F ED /r PADDSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Add packed signed word integers from       
|                                    |      |                       |                   | xmm2/m128 and xmm1 and saturate the        
|                                    |      |                       |                   | results.                                   
| VEX.NDS.128.66.0F.WIG EC /r VPADDSB| RVM  | V/V                   | AVX               | Add packed signed byte integers from       
| xmm1, xmm2, xmm3/m128              |      |                       |                   | xmm3/m128 and xmm2 saturate the results.   
| VEX.NDS.128.66.0F.WIG ED /r VPADDSW| RVM  | V/V                   | AVX               | Add packed signed word integers from       
| xmm1, xmm2, xmm3/m128              |      |                       |                   | xmm3/m128 and xmm2 and saturate the        
|                                    |      |                       |                   | results.                                   
| VEX.NDS.256.66.0F.WIG EC /r VPADDSB| RVM  | V/V                   | AVX2              | Add packed signed byte integers from       
| ymm1, ymm2, ymm3/m256              |      |                       |                   | ymm2, and ymm3/m256 and store the saturated
|                                    |      |                       |                   | results in ymm1.                           
| VEX.NDS.256.66.0F.WIG ED /r VPADDSW| RVM  | V/V                   | AVX2              | Add packed signed word integers from       
| ymm1, ymm2, ymm3/m256              |      |                       |                   | ymm2, and ymm3/m256 and store the saturated
|                                    |      |                       |                   | results in ymm1.                           
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD add of the packed signed integers from the source operand (second
operand) and the destination operand (first operand), and stores the packed
integer results in the destination operand. See Figure 9-4 in the Intel® 64
and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a SIMD operation. Overflow is handled with signed saturation, as described
in the following paragraphs.

The PADDSB instruction adds packed signed byte integers. When an individual
byte result is beyond the range of a signed byte integer (that is, greater than
7FH or less than 80H), the saturated value of 7FH or 80H, respectively, is written
to the destination operand.

The PADDSW instruction adds packed signed word integers. When an individual
word result is beyond the range of a signed word integer (that is, greater than
7FFFH or less than 8000H), the saturated value of 7FFFH or 8000H, respectively,
is written to the destination operand.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands.
When operating on 64-bit operands, the destination operand must be an MMX technology
register and the source operand can be either an MMX technology register or
a 64-bit memory location. In 64-bit mode, using a REX prefix in the form of
REX.R permits this instruction to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The first source operand is an XMM register. The
second operand can be an XMM register or a 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PADDSB (with 64-bit operands)
  DEST[7:0] <- SaturateToSignedByte(DEST[7:0] + SRC (7:0]);
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToSignedByte(DEST[63:56] + SRC[63:56] );
PADDSB (with 128-bit operands)
  DEST[7:0] <-SaturateToSignedByte (DEST[7:0] + SRC[7:0]);
  (* Repeat add operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToSignedByte (DEST[111:120] + SRC[127:120]);
VPADDSB (VEX.128 encoded version)
  DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat subtract operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToSignedByte (SRC1[111:120] + SRC2[127:120]);
  DEST[VLMAX-1:128] <- 0
VPADDSB (VEX.256 encoded version)
  DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat add operation for 2nd through 31st bytes *)
  DEST[255:248]<- SaturateToSignedByte (SRC1[255:248] + SRC2[255:248]);
PADDSW (with 64-bit operands)
  DEST[15:0] <- SaturateToSignedWord(DEST[15:0] + SRC[15:0] );
  (* Repeat add operation for 2nd and 7th words *)
  DEST[63:48] <- SaturateToSignedWord(DEST[63:48] + SRC[63:48] );
PADDSW (with 128-bit operands)
  DEST[15:0]
  (* Repeat add operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToSignedWord (DEST[127:112] + SRC[127:112]);
VPADDSW (VEX.128 encoded version)
  DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat subtract operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToSignedWord (SRC1[127:112] + SRC2[127:112]);
  DEST[VLMAX-1:128] <- 0
VPADDSW (VEX.256 encoded version)
  DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat add operation for 2nd through 15th words *)
  DEST[255:240] <- SaturateToSignedWord (SRC1[255:240] + SRC2[255:240])

Intel C/C++ Compiler Intrinsic Equivalents:
| PADDSB:   | __m64 _mm_adds_pi8(__m64 m1, __m64 m2)    
| (V)PADDSB:| __m128i _mm_adds_epi8 ( __m128i a, __m128i
|           | b)                                        
| VPADDSB:  | __m256i _mm256_adds_epi8 ( __m256i a,     
|           | __m256i b)                                
| PADDSW:   | __m64 _mm_adds_pi16(__m64 m1, __m64       
|           | m2)                                       
| (V)PADDSW:| __m128i _mm_adds_epi16 ( __m128i a,       
|           | __m128i b)                                
| VPADDSW:  | __m256i _mm256_adds_epi16 ( __m256i       
|           | a, __m256i b)                             

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PADDUSB
description:
PADDUSB/PADDUSW - Add Packed Unsigned Integers with Unsigned Saturation:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F DC /r1 PADDUSB mm, mm/m64        | RM   | V/V                   | MMX               | Add packed unsigned byte integers from     
|                                     |      |                       |                   | mm/m64 and mm and saturate the results.    
| 66 0F DC /r PADDUSB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Add packed unsigned byte integers from     
|                                     |      |                       |                   | xmm2/m128 and xmm1 saturate the results.   
| 0F DD /r1 PADDUSW mm, mm/m64        | RM   | V/V                   | MMX               | Add packed unsigned word integers from     
|                                     |      |                       |                   | mm/m64 and mm and saturate the results.    
| 66 0F DD /r PADDUSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Add packed unsigned word integers from     
|                                     |      |                       |                   | xmm2/m128 to xmm1 and saturate the results.
| VEX.NDS.128.660F.WIG DC /r VPADDUSB | RVM  | V/V                   | AVX               | Add packed unsigned byte integers from     
| xmm1, xmm2, xmm3/m128               |      |                       |                   | xmm3/m128 to xmm2 and saturate the results.
| VEX.NDS.128.66.0F.WIG DD /r VPADDUSW| RVM  | V/V                   | AVX               | Add packed unsigned word integers from     
| xmm1, xmm2, xmm3/m128               |      |                       |                   | xmm3/m128 to xmm2 and saturate the results.
| VEX.NDS.256.66.0F.WIG DC /r VPADDUSB| RVM  | V/V                   | AVX2              | Add packed unsigned byte integers from     
| ymm1, ymm2, ymm3/m256               |      |                       |                   | ymm2, and ymm3/m256 and store the saturated
|                                     |      |                       |                   | results in ymm1.                           
| VEX.NDS.256.66.0F.WIG DD /r VPADDUSW| RVM  | V/V                   | AVX2              | Add packed unsigned word integers from     
| ymm1, ymm2, ymm3/m256               |      |                       |                   | ymm2, and ymm3/m256 and store the saturated
|                                     |      |                       |                   | results in ymm1.                           
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD add of the packed unsigned integers from the source operand
(second operand) and the destination operand (first operand), and stores the
packed integer results in the destination operand. See Figure 9-4 in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a SIMD operation. Overflow is handled with unsigned saturation, as described
in the following paragraphs.

The (V)PADDUSB instruction adds packed unsigned byte integers. When an individual
byte result is beyond the range of an unsigned byte integer (that is, greater
than FFH), the saturated value of FFH is written to the destination operand.

The (V)PADDUSW instruction adds packed unsigned word integers. When an individual
word result is beyond the range of an unsigned word integer (that is, greater
than FFFFH), the saturated value of FFFFH is written to the destination operand.

These instructions can operate on either 64-bit, 128-bit or 256-bit operands.
When operating on 64-bit operands, the destination operand must be an MMX technology
register and the source operand can be either an MMX tech-

nology register or a 64-bit memory location. In 64-bit mode, using a REX prefix
in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15). 128-bit Legacy SSE version: The first source operand is an XMM
register. The second operand can be an XMM register or a 128-bit memory location.
The destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand is a YMM register or a
256-bit memory location. The destination operand is a YMM register. Note: VEX.L
must be 0, otherwise the instruction will #UD.

Operation:

PADDUSB (with 64-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte(DEST[7:0] + SRC (7:0] );
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToUnsignedByte(DEST[63:56] + SRC[63:56]
PADDUSB (with 128-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] + SRC[7:0]);
  (* Repeat add operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToUnSignedByte (DEST[127:120] + SRC[127:120]);
VPADDUSB (VEX.128 encoded version)
  DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat subtract operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToUnsignedByte (SRC1[111:120] + SRC2[127:120]);
  DEST[VLMAX-1:128] <- 0
VPADDUSB (VEX.256 encoded version)
  DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] + SRC2[7:0]);
  (* Repeat add operation for 2nd through 31st bytes *)
  DEST[255:248]<- SaturateToUnsignedByte (SRC1[255:248] + SRC2[255:248]);
PADDUSW (with 64-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord(DEST[15:0] + SRC[15:0] );
  (* Repeat add operation for 2nd and 3rd words *)
  DEST[63:48] <- SaturateToUnsignedWord(DEST[63:48] + SRC[63:48] );
PADDUSW (with 128-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] + SRC[15:0]);
  (* Repeat add operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToUnSignedWord (DEST[127:112] + SRC[127:112]);
VPADDUSW (VEX.128 encoded version)
  DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat subtract operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] + SRC2[127:112]);
  DEST[VLMAX-1:128] <- 0
VPADDUSW (VEX.256 encoded version)
  DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] + SRC2[15:0]);
  (* Repeat add operation for 2nd through 15th words *)
  DEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] + SRC2[255:240])

Intel C/C++ Compiler Intrinsic Equivalents:
| PADDUSB:   | __m64 _mm_adds_pu8(__m64 m1, __m64 m2)    
| PADDUSW:   | __m64 _mm_adds_pu16(__m64 m1, __m64       
|            | m2)                                       
| (V)PADDUSB:| __m128i _mm_adds_epu8 ( __m128i a, __m128i
|            | b)                                        
| (V)PADDUSW:| __m128i _mm_adds_epu16 ( __m128i a,       
|            | __m128i b)                                
| VPADDUSB:  | __m256i _mm256_adds_epu8 ( __m256i a,     
|            | __m256i b)                                
| VPADDUSW:  | __m256i _mm256_adds_epu16 ( __m256i       
|            | a, __m256i b)                             

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PALIGNR
description:
PALIGNR  -  Packed Align Right:
| Opcode/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 0F 3A 0F /r ib1 PALIGNR mm1, mm2/m64,     | RMI  | V/V                   | SSSE3             | Concatenate destination and source operands,
| imm8                                      |      |                       |                   | extract byte-aligned result shifted         
|                                           |      |                       |                   | to the right by constant value in imm8      
|                                           |      |                       |                   | into mm1.                                   
| 66 0F 3A 0F /r ib PALIGNR xmm1, xmm2/m128,| RMI  | V/V                   | SSSE3             | Concatenate destination and source operands,
| imm8                                      |      |                       |                   | extract byte-aligned result shifted         
|                                           |      |                       |                   | to the right by constant value in imm8      
|                                           |      |                       |                   | into xmm1.                                  
| VEX.NDS.128.66.0F3A.WIG 0F /r ib VPALIGNR | RVMI | V/V                   | AVX               | Concatenate xmm2 and xmm3/m128, extract     
| xmm1, xmm2, xmm3/m128, imm8               |      |                       |                   | byte aligned result shifted to the right    
|                                           |      |                       |                   | by constant value in imm8 and result        
|                                           |      |                       |                   | is stored in xmm1.                          
| VEX.NDS.256.66.0F3A.WIG 0F /r ib VPALIGNR | RVMI | V/V                   | AVX2              | Concatenate pairs of 16 bytes in ymm2       
| ymm1, ymm2, ymm3/m256, imm8               |      |                       |                   | and ymm3/m256 into 32-byte intermediate     
|                                           |      |                       |                   | result, extract byte-aligned, 16-byte       
|                                           |      |                       |                   | result shifted to the right by constant     
|                                           |      |                       |                   | values in imm8 from each intermediate       
|                                           |      |                       |                   | result, and two 16-byte results are         
|                                           |      |                       |                   | stored in ymm1.                             
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
(V)PALIGNR concatenates the destination operand (the first operand) and the
source operand (the second operand) into an intermediate composite, shifts the
composite at byte granularity to the right by a constant immediate, and extracts
the right-aligned result into the destination. The first and the second operands
can be an MMX, XMM or a YMM register. The immediate value is considered unsigned.
Immediate shift counts larger than the 2L (i.e. 32 for 128-bit operands, or
16 for 64-bit operands) produce a zero result. Both operands can be MMX registers,
XMM registers or YMM registers. When the source operand is a 128-bit memory
operand, the operand must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers. 128-bit Legacy
SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The first source operand is an XMM
register. The second source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register and contains two 16-byte blocks.
The second source operand is a YMM register or a 256-bit memory location containing
two 16-byte block. The destination operand is a YMM register and contain two
16-byte results. The imm8[7:0] is the common shift count used for the two lower
16-byte block sources and the two upper 16-byte block sources. The low 16-byte
block of the two source

operands produce the low 16-byte result of the destination operand, the high
16-byte block of the two source operands produce the high 16-byte result of
the destination operand. Concatenation is done with 128-bit data in the first
and second source operand for both 128-bit and 256-bit instructions. The high
128-bits of the intermediate composite 256-bit result came from the 128-bit
data from the first source operand; the low 128-bits of the intermediate result
came from the 128-bit data of the second source operand. Note: VEX.L must be
0, otherwise the instruction will #UD.

| 127| 0| 127| 0 SRC2
Imm8[7:0]*8

| 255| 128| 255| 128 SRC2
Imm8[7:0]*8

| 255 Figure 4-3.| 128 256-bit VPALIGN Instruction Operation| 127| 0 DEST
Operation:

PALIGNR (with 64-bit operands)
  temp1[127:0] = CONCATENATE(DEST,SRC)>>(imm8*8)
  DEST[63:0] = temp1[63:0]
PALIGNR (with 128-bit operands)
temp1[255:0] <- ((DEST[127:0] << 128) OR SRC[127:0])>>(imm8*8);
DEST[127:0] <- temp1[127:0]
DEST[VLMAX-1:128] (Unmodified)
VPALIGNR (VEX.128 encoded version)
temp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8*8);
DEST[127:0] <- temp1[127:0]
DEST[VLMAX-1:128] <- 0
VPALIGNR (VEX.256 encoded version)
temp1[255:0] <- ((SRC1[127:0] << 128) OR SRC2[127:0])>>(imm8[7:0]*8);
DEST[127:0] <- temp1[127:0]
temp1[255:0] <- ((SRC1[255:128] << 128) OR SRC2[255:128])>>(imm8[7:0]*8);
DEST[255:128] <- temp1[127:0]

Intel C/C++ Compiler Intrinsic Equivalents:
| PALIGNR:   | __m64 _mm_alignr_pi8 (__m64 a, __m64
|            | b, int n)                           
| (V)PALIGNR:| __m128i _mm_alignr_epi8 (__m128i a, 
|            | __m128i b, int n)                   
| VPALIGNR:  | __m256i _mm256_alignr_epi8 (__m256i 
|            | a, __m256i b, const int n)          

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PAND
description:
PAND - Logical AND:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 0F DB /r1 PAND mm, mm/m64              | RM   | V/V                   | MMX               | Bitwise AND mm/m64 and mm.            
| 66 0F DB /r PAND xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Bitwise AND of xmm2/m128 and xmm1.    
| VEX.NDS.128.66.0F.WIG DB /r VPAND xmm1,| RVM  | V/V                   | AVX               | Bitwise AND of xmm3/m128 and xmm.     
| xmm2, xmm3/m128                        |      |                       |                   |                                       
| VEX.NDS.256.66.0F.WIG DB /r VPAND ymm1,| RVM  | V/V                   | AVX2              | Bitwise AND of ymm2, and ymm3/m256 and
| ymm2, ymm3/.m256                       |      |                       |                   | store result in ymm1.                 
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical AND operation on the first source operand and second
source operand and stores the result in the destination operand. Each bit of
the result is set to 1 if the corresponding bits of the first and second operands
are 1, otherwise it is set to 0.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand can be an MMX technology
register.

128-bit Legacy SSE version: The first source operand is an XMM register. The
second operand can be an XMM register or a 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an
XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register
destination are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PAND (128-bit Legacy SSE version)
DEST <- DEST AND SRC
DEST[VLMAX-1:128] (Unmodified)
VPAND (VEX.128 encoded version)
DEST <- SRC1 AND SRC2
DEST[VLMAX-1:128] <- 0
VPAND (VEX.256 encoded instruction)
DEST[255:0] <- (SRC1[255:0] AND SRC2[255:0])

Intel C/C++ Compiler Intrinsic Equivalent:
| PAND:   | __m64 _mm_and_si64 (__m64 m1, __m64       
|         | m2)                                       
| (V)PAND:| __m128i _mm_and_si128 ( __m128i a, __m128i
|         | b)                                        
| VPAND:  | __m256i _mm256_and_si256 ( __m256i a,     
|         | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PANDN
description:
PANDN - Logical AND NOT:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 0F DF /r1 PANDN mm, mm/m64              | RM   | V/V                   | MMX               | Bitwise AND NOT of mm/m64 and mm.     
| 66 0F DF /r PANDN xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Bitwise AND NOT of xmm2/m128 and xmm1.
| VEX.NDS.128.66.0F.WIG DF /r VPANDN xmm1,| RVM  | V/V                   | AVX               | Bitwise AND NOT of xmm3/m128 and xmm2.
| xmm2, xmm3/m128                         |      |                       |                   |                                       
| VEX.NDS.256.66.0F.WIG DF /r VPANDN ymm1,| RVM  | V/V                   | AVX2              | Bitwise AND NOT of ymm2, and ymm3/m256
| ymm2, ymm3/m256                         |      |                       |                   | and store result in ymm1.             
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical NOT operation on the first source operand, then performs
bitwise AND with second source operand and stores the result in the destination
operand. Each bit of the result is set to 1 if the corresponding bit in the
first operand is 0 and the corresponding bit in the second operand is 1, otherwise
it is set to 0.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand can be an MMX technology
register. 128-bit Legacy SSE version: The first source operand is an XMM register.
The second operand can be an XMM register or a 128-bit memory location. The
destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.
VEX.128 encoded version: The first source operand is an XMM register. The second
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand is a YMM register or a
256-bit memory location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PANDN(128-bit Legacy SSE version)
DEST <- NOT(DEST) AND SRC
DEST[VLMAX-1:128] (Unmodified)
VPANDN (VEX.128 encoded version)
DEST <- NOT(SRC1) AND SRC2
DEST[VLMAX-1:128] <- 0
VPANDN (VEX.256 encoded instruction)
DEST[255:0] <- ((NOT SRC1[255:0]) AND SRC2[255:0])

Intel C/C++ Compiler Intrinsic Equivalent:
| PANDN:   | __m64 _mm_andnot_si64 (__m64 m1, __m64
|          | m2)                                   
| (V)PANDN:| __m128i _mm_andnot_si128 ( __m128i a, 
|          | __m128i b)                            
| VPANDN:  | __m256i _mm256_andnot_si256 ( __m256i 
|          | a, __m256i b)                         

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PAUSE
description:
PAUSE - Spin Loop Hint:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| F3 90 | PAUSE      | NP   | Valid      | Valid          | Gives hint to processor that improves
|       |            |      |            |                | performance of spin-wait loops.      

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Improves the performance of spin-wait loops. When executing a “spin-wait loop,”
processors will suffer a severe performance penalty when exiting the loop because
it detects a possible memory order violation. The PAUSE instruction provides
a hint to the processor that the code sequence is a spin-wait loop. The processor
uses this hint to avoid the memory order violation in most situations, which
greatly improves processor performance. For this reason, it is recommended that
a PAUSE instruction be placed in all spin-wait loops.

An additional function of the PAUSE instruction is to reduce the power consumed
by a processor while executing a spin loop. A processor can execute a spin-wait
loop extremely quickly, causing the processor to consume a lot of power while
it waits for the resource it is spinning on to become available. Inserting a
pause instruction in a spinwait loop greatly reduces the processor's power consumption.

This instruction was introduced in the Pentium 4 processors, but is backward
compatible with all IA-32 processors. In earlier IA-32 processors, the PAUSE
instruction operates like a NOP instruction. The Pentium 4 and Intel Xeon processors
implement the PAUSE instruction as a delay. The delay is finite and can be zero
for some processors. This instruction does not change the architectural state
of the processor (that is, it performs essentially a delaying no-op operation).

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

Execute_Next_Instruction(DELAY);

Numeric Exceptions:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: PAVGB
description:
PAVGB/PAVGW - Average Packed Integers:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 0F E0 /r1 PAVGB mm1, mm2/m64            | RM   | V/V                   | SSE               | Average packed unsigned byte integers 
|                                         |      |                       |                   | from mm2/m64 and mm1 with rounding.   
| 66 0F E0, /r PAVGB xmm1, xmm2/m128      | RM   | V/V                   | SSE2              | Average packed unsigned byte integers 
|                                         |      |                       |                   | from xmm2/m128 and xmm1 with rounding.
| 0F E3 /r1 PAVGW mm1, mm2/m64            | RM   | V/V                   | SSE               | Average packed unsigned word integers 
|                                         |      |                       |                   | from mm2/m64 and mm1 with rounding.   
| 66 0F E3 /r PAVGW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Average packed unsigned word integers 
|                                         |      |                       |                   | from xmm2/m128 and xmm1 with rounding.
| VEX.NDS.128.66.0F.WIG E0 /r VPAVGB xmm1,| RVM  | V/V                   | AVX               | Average packed unsigned byte integers 
| xmm2, xmm3/m128                         |      |                       |                   | from xmm3/m128 and xmm2 with rounding.
| VEX.NDS.128.66.0F.WIG E3 /r VPAVGW xmm1,| RVM  | V/V                   | AVX               | Average packed unsigned word integers 
| xmm2, xmm3/m128                         |      |                       |                   | from xmm3/m128 and xmm2 with rounding.
| VEX.NDS.256.66.0F.WIG E0 /r VPAVGB ymm1,| RVM  | V/V                   | AVX2              | Average packed unsigned byte integers 
| ymm2, ymm3/m256                         |      |                       |                   | from ymm2, and ymm3/m256 with rounding
|                                         |      |                       |                   | and store to ymm1.                    
| VEX.NDS.256.66.0F.WIG E3 /r VPAVGW ymm1,| RVM  | V/V                   | AVX2              | Average packed unsigned word integers 
| ymm2, ymm3/m256                         |      |                       |                   | from ymm2, ymm3/m256 with rounding to 
|                                         |      |                       |                   | ymm1.                                 
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD average of the packed unsigned integers from the source operand
(second operand) and the destination operand (first operand), and stores the
results in the destination operand. For each corresponding pair of data elements
in the first and second operands, the elements are added together, a 1 is added
to the temporary sum, and that result is shifted right one bit position.

The (V)PAVGB instruction operates on packed unsigned bytes and the (V)PAVGW
instruction operates on packed unsigned words.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand can be an MMX technology
register. 128-bit Legacy SSE version: The first source operand is an XMM register.
The second operand can be an XMM register or a 128-bit memory location. The
destination is not distinct from the first source XMM register and the upper
bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified.

VEX.128 encoded version: The first source operand is an XMM register. The second
source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding
YMM register destination are zeroed. VEX.256 encoded version: The first source
operand is a YMM register. The second source operand is a YMM register or a
256-bit memory location. The destination operand is a YMM register.

Operation:

PAVGB (with 64-bit operands)
  DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 6 *)
  DEST[63:56] <- (SRC[63:56] + DEST[63:56] + 1) >> 1;
PAVGW (with 64-bit operands)
  DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
  (* Repeat operation performed for words 2 and 3 *)
  DEST[63:48] <- (SRC[63:48] + DEST[63:48] + 1) >> 1;
PAVGB (with 128-bit operands)
  DEST[7:0] <- (SRC[7:0] + DEST[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 14 *)
  DEST[127:120] <- (SRC[127:120] + DEST[127:120] + 1) >> 1;
PAVGW (with 128-bit operands)
  DEST[15:0] <- (SRC[15:0] + DEST[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
  (* Repeat operation performed for words 2 through 6 *)
  DEST[127:112] <- (SRC[127:112] + DEST[127:112] + 1) >> 1;
VPAVGB (VEX.128 encoded version)
  DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1;
  (* Repeat operation performed for bytes 2 through 15 *)
  DEST[127:120] <- (SRC1[127:120] + SRC2[127:120] + 1) >> 1
  DEST[VLMAX-1:128] <- 0
VPAVGW (VEX.128 encoded version)
  DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1;
  (* Repeat operation performed for 16-bit words 2 through 7 *)
  DEST[127:112] <- (SRC1[127:112] + SRC2[127:112] + 1) >> 1
  DEST[VLMAX-1:128] <- 0
VPAVGB (VEX.256 encoded instruction)
  DEST[7:0] <- (SRC1[7:0] + SRC2[7:0] + 1) >> 1; (* Temp sum before shifting is 9 bits *)
  (* Repeat operation performed for bytes 2 through 31)
  DEST[255:248] <- (SRC1[255:248] + SRC2[255:248] + 1) >> 1;
VPAVGW (VEX.256 encoded instruction)
  DEST[15:0] <- (SRC1[15:0] + SRC2[15:0] + 1) >> 1; (* Temp sum before shifting is 17 bits *)
  (* Repeat operation performed for words 2 through 15)
  DEST[255:14]) <- (SRC1[255:240] + SRC2[255:240] + 1) >> 1;

Intel C/C++ Compiler Intrinsic Equivalent:
| PAVGB:   | __m64 _mm_avg_pu8 (__m64 a, __m64 b)      
| PAVGW:   | __m64 _mm_avg_pu16 (__m64 a, __m64 b)     
| (V)PAVGB:| __m128i _mm_avg_epu8 ( __m128i a, __m128i 
|          | b)                                        
| (V)PAVGW:| __m128i _mm_avg_epu16 ( __m128i a, __m128i
|          | b)                                        
| VPAVGB:  | __m256i _mm256_avg_epu8 ( __m256i a,      
|          | __m256i b)                                
| VPAVGW:  | __m256i _mm256_avg_epu16 ( __m256i a,     
|          | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PBLENDVB
description:
PBLENDVB  -  Variable Blend Packed Bytes:
| Opcode/Instruction                         | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 66 0F 38 10 /r PBLENDVB xmm1, xmm2/m128,   | RM   | V/V                   | SSE4_1            | Select byte values from xmm1 and xmm2/m128
| <XMM0>                                     |      |                       |                   | from mask specified in the high bit       
|                                            |      |                       |                   | of each byte in XMM0 and store the values 
|                                            |      |                       |                   | into xmm1.                                
| VEX.NDS.128.66.0F3A.W0 4C /r /is4 VPBLENDVB| RVMR | V/V                   | AVX               | Select byte values from xmm2 and xmm3/m128
| xmm1, xmm2, xmm3/m128, xmm4                |      |                       |                   | using mask bits in the specified mask     
|                                            |      |                       |                   | register, xmm4, and store the values      
|                                            |      |                       |                   | into xmm1.                                
| VEX.NDS.256.66.0F3A.W0 4C /r /is4 VPBLENDVB| RVMR | V/V                   | AVX2              | Select byte values from ymm2 and ymm3/m256
| ymm1, ymm2, ymm3/m256, ymm4                |      |                       |                   | from mask specified in the high bit       
|                                            |      |                       |                   | of each byte in ymm4 and store the values 
|                                            |      |                       |                   | into ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| <XMM0>       | NA       
| RVMR | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8[7:4]

Description:
Conditionally copies byte elements from the source operand (second operand)
to the destination operand (first operand) depending on mask bits defined in
the implicit third register argument, XMM0. The mask bits are the most significant
bit in each byte element of the XMM0 register. If a mask bit is “1", then the
corresponding byte element in the source operand is copied to the destination,
else the byte element in the destination operand is left unchanged. The register
assignment of the implicit third operand is defined to be the architectural
register XMM0. 128-bit Legacy SSE version: The first source operand and the
destination operand is the same. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged. The mask register operand is implicitly
defined to be the architectural register XMM0. An attempt to execute PBLENDVB
with a VEX prefix will cause #UD. VEX.128 encoded version: The first source
operand and the destination operand are XMM registers. The second source operand
is an XMM register or 128-bit memory location. The mask operand is the third
source register, and encoded in bits[7:4] of the immediate byte(imm8). The bits[3:0]
of imm8 are ignored. In 32-bit mode, imm8[7] is ignored. The upper bits (VLMAX-1:128)
of the corresponding YMM register (destination register) are zeroed. VEX.L must
be 0, otherwise the instruction will #UD. VEX.W must be 0, otherwise, the instruction
will #UD. VEX.256 encoded version: The first source operand and the destination
operand are YMM registers. The second source operand is an YMM register or 256-bit
memory location. The third source register is an YMM register and encoded in
bits[7:4] of the immediate byte(imm8). The bits[3:0] of imm8 are ignored. In
32-bit mode, imm8[7] is ignored. VPBLENDVB permits the mask to be any XMM or
YMM register. In contrast, PBLENDVB treats XMM0 implicitly as the mask and do
not support non-destructive destination operation. An attempt to execute PBLENDVB
encoded with a VEX prefix will cause a #UD exception.

Operation:

PBLENDVB (128-bit Legacy SSE version)
MASK <- XMM0
IF (MASK[7] = 1) THEN DEST[7:0] <- SRC[7:0];
ELSE DEST[7:0] <- DEST[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] <- SRC[15:8];
ELSE DEST[15:8] <- DEST[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] <- SRC[23:16]
ELSE DEST[23:16] <- DEST[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] <- SRC[31:24]
ELSE DEST[31:24] <- DEST[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] <- SRC[39:32]
ELSE DEST[39:32] <- DEST[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] <- SRC[47:40]
ELSE DEST[47:40] <- DEST[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] <- SRC[55:48]
ELSE DEST[55:48] <- DEST[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] <- SRC[63:56]
ELSE DEST[63:56] <- DEST[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] <- SRC[71:64]
ELSE DEST[71:64] <- DEST[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] <- SRC[79:72]
ELSE DEST[79:72] <- DEST[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] <- SRC[87:80]
ELSE DEST[87:80] <- DEST[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] <- SRC[95:88]
ELSE DEST[95:88] <-DEST[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] <- SRC[103:96]
ELSE DEST[103:96] <-DEST[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] <- SRC[111:104]
ELSE DEST[111:104] <- DEST[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] <- SRC[119:112]
ELSE DEST[119:112] <- DEST[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] <- SRC[127:120]
ELSE DEST[127:120] <- DEST[127:120])
DEST[VLMAX-1:128] (Unmodified)
VPBLENDVB (VEX.128 encoded version)
MASK <- SRC3
IF (MASK[7] = 1) THEN DEST[7:0] <- SRC2[7:0];
ELSE DEST[7:0] <- SRC1[7:0];
IF (MASK[15] = 1) THEN DEST[15:8] <- SRC2[15:8];
ELSE DEST[15:8] <- SRC1[15:8];
IF (MASK[23] = 1) THEN DEST[23:16] <- SRC2[23:16]
ELSE DEST[23:16] <- SRC1[23:16];
IF (MASK[31] = 1) THEN DEST[31:24] <- SRC2[31:24]
ELSE DEST[31:24] <- SRC1[31:24];
IF (MASK[39] = 1) THEN DEST[39:32] <- SRC2[39:32]
ELSE DEST[39:32] <- SRC1[39:32];
IF (MASK[47] = 1) THEN DEST[47:40] <- SRC2[47:40]
ELSE DEST[47:40] <- SRC1[47:40];
IF (MASK[55] = 1) THEN DEST[55:48] <- SRC2[55:48]
ELSE DEST[55:48] <- SRC1[55:48];
IF (MASK[63] = 1) THEN DEST[63:56] <- SRC2[63:56]
ELSE DEST[63:56] <- SRC1[63:56];
IF (MASK[71] = 1) THEN DEST[71:64] <- SRC2[71:64]
ELSE DEST[71:64] <- SRC1[71:64];
IF (MASK[79] = 1) THEN DEST[79:72] <- SRC2[79:72]
ELSE DEST[79:72] <- SRC1[79:72];
IF (MASK[87] = 1) THEN DEST[87:80] <- SRC2[87:80]
ELSE DEST[87:80] <- SRC1[87:80];
IF (MASK[95] = 1) THEN DEST[95:88] <- SRC2[95:88]
ELSE DEST[95:88] <-SRC1[95:88];
IF (MASK[103] = 1) THEN DEST[103:96] <- SRC2[103:96]
ELSE DEST[103:96] <-SRC1[103:96];
IF (MASK[111] = 1) THEN DEST[111:104] <- SRC2[111:104]
ELSE DEST[111:104] <- SRC1[111:104];
IF (MASK[119] = 1) THEN DEST[119:112] <- SRC2[119:112]
ELSE DEST[119:112] <- SRC1[119:112];
IF (MASK[127] = 1) THEN DEST[127:120] <- SRC2[127:120]
ELSE DEST[127:120] <- SRC1[127:120])
DEST[VLMAX-1:128] <- 0
VPBLENDVB (VEX.256 encoded version)
MASK <- SRC3
IF (MASK[7] == 1) THEN DEST[7:0] <- SRC2[7:0];
ELSE DEST[7:0] <- SRC1[7:0];
IF (MASK[15] == 1) THEN DEST[15:8] <-SRC2[15:8];
ELSE DEST[15:8] <- SRC1[15:8];
IF (MASK[23] == 1) THEN DEST[23:16] <-SRC2[23:16]
ELSE DEST[23:16] <- SRC1[23:16];
IF (MASK[31] == 1) THEN DEST[31:24] <- SRC2[31:24]
ELSE DEST[31:24] <- SRC1[31:24];
IF (MASK[39] == 1) THEN DEST[39:32] <- SRC2[39:32]
ELSE DEST[39:32] <- SRC1[39:32];
IF (MASK[47] == 1) THEN DEST[47:40] <- SRC2[47:40]
ELSE DEST[47:40] <- SRC1[47:40];
IF (MASK[55] == 1) THEN DEST[55:48] <- SRC2[55:48]
ELSE DEST[55:48] <- SRC1[55:48];
IF (MASK[63] == 1) THEN DEST[63:56] <-SRC2[63:56]
ELSE DEST[63:56] <- SRC1[63:56];
IF (MASK[71] == 1) THEN DEST[71:64] <-SRC2[71:64]
ELSE DEST[71:64] <- SRC1[71:64];
IF (MASK[79] == 1) THEN DEST[79:72] <- SRC2[79:72]
ELSE DEST[79:72] <- SRC1[79:72];
IF (MASK[87] == 1) THEN DEST[87:80] <- SRC2[87:80]
ELSE DEST[87:80] <- SRC1[87:80];
IF (MASK[95] == 1) THEN DEST[95:88] <- SRC2[95:88]
ELSE DEST[95:88] <- SRC1[95:88];
IF (MASK[103] == 1) THEN DEST[103:96] <- SRC2[103:96]
ELSE DEST[103:96] <- SRC1[103:96];
IF (MASK[111] == 1) THEN DEST[111:104] <- SRC2[111:104]
ELSE DEST[111:104] <- SRC1[111:104];
IF (MASK[119] == 1) THEN DEST[119:112] <- SRC2[119:112]
ELSE DEST[119:112] <- SRC1[119:112];
IF (MASK[127] == 1) THEN DEST[127:120] <- SRC2[127:120]
ELSE DEST[127:120] <- SRC1[127:120])
IF (MASK[135] == 1) THEN DEST[135:128] <- SRC2[135:128];
ELSE DEST[135:128] <- SRC1[135:128];
IF (MASK[143] == 1) THEN DEST[143:136] <- SRC2[143:136];
ELSE DEST[[143:136] <- SRC1[143:136];
IF (MASK[151] == 1) THEN DEST[151:144] <- SRC2[151:144]
ELSE DEST[151:144] <- SRC1[151:144];
IF (MASK[159] == 1) THEN DEST[159:152] <- SRC2[159:152]
ELSE DEST[159:152] <- SRC1[159:152];
IF (MASK[167] == 1) THEN DEST[167:160] <- SRC2[167:160]
ELSE DEST[167:160] <- SRC1[167:160];
IF (MASK[175] == 1) THEN DEST[175:168] <- SRC2[175:168]
ELSE DEST[175:168] <- SRC1[175:168];
IF (MASK[183] == 1) THEN DEST[183:176] <- SRC2[183:176]
ELSE DEST[183:176] <- SRC1[183:176];
IF (MASK[191] == 1) THEN DEST[191:184] <- SRC2[191:184]
ELSE DEST[191:184] <- SRC1[191:184];
IF (MASK[199] == 1) THEN DEST[199:192] <- SRC2[199:192]
ELSE DEST[199:192] <- SRC1[199:192];
IF (MASK[207] == 1) THEN DEST[207:200] <- SRC2[207:200]
ELSE DEST[207:200] <- SRC1[207:200]
IF (MASK[215] == 1) THEN DEST[215:208] <- SRC2[215:208]
ELSE DEST[215:208] <- SRC1[215:208];
IF (MASK[223] == 1) THEN DEST[223:216] <- SRC2[223:216]
ELSE DEST[223:216] <- SRC1[223:216];
IF (MASK[231] == 1) THEN DEST[231:224] <- SRC2[231:224]
ELSE DEST[231:224] <- SRC1[231:224];
IF (MASK[239] == 1) THEN DEST[239:232] <- SRC2[239:232]
ELSE DEST[239:232] <- SRC1[239:232];
IF (MASK[247] == 1) THEN DEST[247:240] <- SRC2[247:240]
ELSE DEST[247:240] <- SRC1[247:240];
IF (MASK[255] == 1) THEN DEST[255:248] <- SRC2[255:248]
ELSE DEST[255:248] <- SRC1[255:248]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PBLENDVB:| __m128i _mm_blendv_epi8 (__m128i v1,
|             | __m128i v2, __m128i mask);          
| VPBLENDVB:  | __m256i _mm256_blendv_epi8 (__m256i 
|             | v1, __m256i v2, __m256i mask);      

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.W = 1.


platform: x86
mnem: PBLENDW
description:
PBLENDW  -  Blend Packed Words:
| Opcode/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| 66 0F 3A 0E /r ib PBLENDW xmm1, xmm2/m128,| RMI  | V/V                   | SSE4_1            | Select words from xmm1 and xmm2/m128 
| imm8                                      |      |                       |                   | from mask specified in imm8 and store
|                                           |      |                       |                   | the values into xmm1.                
| VEX.NDS.128.66.0F3A.WIG 0E /r ib VPBLENDW | RVMI | V/V                   | AVX               | Select words from xmm2 and xmm3/m128 
| xmm1, xmm2, xmm3/m128, imm8               |      |                       |                   | from mask specified in imm8 and store
|                                           |      |                       |                   | the values into xmm1.                
| VEX.NDS.256.66.0F3A.WIG 0E /r ib VPBLENDW | RVMI | V/V                   | AVX2              | Select words from ymm2 and ymm3/m256 
| ymm1, ymm2, ymm3/m256, imm8               |      |                       |                   | from mask specified in imm8 and store
|                                           |      |                       |                   | the values into ymm1.                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Words from the source operand (second operand) are conditionally written to
the destination operand (first operand) depending on bits in the immediate operand
(third operand). The immediate bits (bits 7:0) form a mask that determines whether
the corresponding word in the destination is copied from the source. If a bit
in the mask, corresponding to a word, is “1", then the word is copied, else
the word element in the destination operand is unchanged. 128-bit Legacy SSE
version: The second source operand can be an XMM register or a 128-bit memory
location. The first source and destination operands are XMM registers. Bits
(VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand can be an XMM register or
a 128-bit memory location. The first source and destination operands are XMM
registers. Bits (VLMAX-1:128) of the corresponding YMM register are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second
source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Operation:

PBLENDW (128-bit Legacy SSE version)
IF (imm8[0] = 1) THEN DEST[15:0] <- SRC[15:0]
ELSE DEST[15:0] <- DEST[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] <- SRC[31:16]
ELSE DEST[31:16] <- DEST[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] <- SRC[47:32]
ELSE DEST[47:32] <- DEST[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] <- SRC[63:48]
ELSE DEST[63:48] <- DEST[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] <- SRC[79:64]
ELSE DEST[79:64] <- DEST[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] <- SRC[95:80]
ELSE DEST[95:80] <- DEST[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] <- SRC[111:96]
ELSE DEST[111:96] <- DEST[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] <- SRC[127:112]
ELSE DEST[127:112] <- DEST[127:112]
VPBLENDW (VEX.128 encoded version)
IF (imm8[0] = 1) THEN DEST[15:0] <- SRC2[15:0]
ELSE DEST[15:0] <- SRC1[15:0]
IF (imm8[1] = 1) THEN DEST[31:16] <- SRC2[31:16]
ELSE DEST[31:16] <- SRC1[31:16]
IF (imm8[2] = 1) THEN DEST[47:32] <- SRC2[47:32]
ELSE DEST[47:32] <- SRC1[47:32]
IF (imm8[3] = 1) THEN DEST[63:48] <- SRC2[63:48]
ELSE DEST[63:48] <- SRC1[63:48]
IF (imm8[4] = 1) THEN DEST[79:64] <- SRC2[79:64]
ELSE DEST[79:64] <- SRC1[79:64]
IF (imm8[5] = 1) THEN DEST[95:80] <- SRC2[95:80]
ELSE DEST[95:80] <- SRC1[95:80]
IF (imm8[6] = 1) THEN DEST[111:96] <- SRC2[111:96]
ELSE DEST[111:96] <- SRC1[111:96]
IF (imm8[7] = 1) THEN DEST[127:112] <- SRC2[127:112]
ELSE DEST[127:112] <- SRC1[127:112]
DEST[VLMAX-1:128] <- 0
VPBLENDW (VEX.256 encoded version)
IF (imm8[0] == 1) THEN DEST[15:0] <- SRC2[15:0]
ELSE DEST[15:0] <- SRC1[15:0]
IF (imm8[1] == 1) THEN DEST[31:16] <- SRC2[31:16]
ELSE DEST[31:16] <- SRC1[31:16]
IF (imm8[2] == 1) THEN DEST[47:32] <- SRC2[47:32]
ELSE DEST[47:32] <- SRC1[47:32]
IF (imm8[3] == 1) THEN DEST[63:48] <- SRC2[63:48]
ELSE DEST[63:48] <- SRC1[63:48]
IF (imm8[4] == 1) THEN DEST[79:64] <- SRC2[79:64]
ELSE DEST[79:64] <- SRC1[79:64]
IF (imm8[5] == 1) THEN DEST[95:80] <- SRC2[95:80]
ELSE DEST[95:80] <- SRC1[95:80]
IF (imm8[6] == 1) THEN DEST[111:96] <- SRC2[111:96]
ELSE DEST[111:96] <- SRC1[111:96]
IF (imm8[7] == 1) THEN DEST[127:112] <- SRC2[127:112]
ELSE DEST[127:112] <- SRC1[127:112]
IF (imm8[0] == 1) THEN DEST[143:128] <- SRC2[143:128]
ELSE DEST[143:128] <- SRC1[143:128]
IF (imm8[1] == 1) THEN DEST[159:144] <- SRC2[159:144]
ELSE DEST[159:144] <- SRC1[159:144]
IF (imm8[2] == 1) THEN DEST[175:160] <- SRC2[175:160]
ELSE DEST[175:160] <- SRC1[175:160]
IF (imm8[3] == 1) THEN DEST[191:176] <- SRC2[191:176]
ELSE DEST[191:176] <- SRC1[191:176]
IF (imm8[4] == 1) THEN DEST[207:192] <- SRC2[207:192]
ELSE DEST[207:192] <- SRC1[207:192]
IF (imm8[5] == 1) THEN DEST[223:208] <- SRC2[223:208]
ELSE DEST[223:208] <- SRC1[223:208]
IF (imm8[6] == 1) THEN DEST[239:224] <- SRC2[239:224]
ELSE DEST[239:224] <- SRC1[239:224]
IF (imm8[7] == 1) THEN DEST[255:240] <- SRC2[255:240]
ELSE DEST[255:240] <- SRC1[255:240]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PBLENDW:| __m128i _mm_blend_epi16 (__m128i v1,
|            | __m128i v2, const int mask);        
| VPBLENDW:  | __m256i _mm256_blend_epi16 (__m256i 
|            | v1, __m256i v2, const int mask)     

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PCLMULQDQ
description:
PCLMULQDQ - Carry-Less Multiplication Quadword:
| Opcode/Instruction                          | Op/En| 64/32 bit Mode Support| CPUID Feature Flag      | Description                              
| 66 0F 3A 44 /r ib PCLMULQDQ xmm1, xmm2/m128,| RMI  | V/V                   | CLMUL                   | Carry-less multiplication of one quadword
| imm8                                        |      |                       |                         | of xmm1 by one quadword of xmm2/m128,    
|                                             |      |                       |                         | stores the 128-bit result in xmm1. The   
|                                             |      |                       |                         | immediate is used to determine which     
|                                             |      |                       |                         | quadwords of xmm1 and xmm2/m128 should   
|                                             |      |                       |                         | be used.                                 
| VEX.NDS.128.66.0F3A.WIG 44 /r ib VPCLMULQDQ | RVMI | V/V                   | Both CLMUL and AVX flags| Carry-less multiplication of one quadword
| xmm1, xmm2, xmm3/m128, imm8                 |      |                       |                         | of xmm2 by one quadword of xmm3/m128,    
|                                             |      |                       |                         | stores the 128-bit result in xmm1. The   
|                                             |      |                       |                         | immediate is used to determine which     
|                                             |      |                       |                         | quadwords of xmm2 and xmm3/m128 should   
|                                             |      |                       |                         | be used.                                 

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand2     | Operand3     | Operand4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA      
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8    

Description:
Performs a carry-less multiplication of two quadwords, selected from the first
source and second source operand according to the value of the immediate byte.
Bits 4 and 0 are used to select which 64-bit half of each operand to use according
to Table 4-10, other bits of the immediate byte are ignored.


Table 4-10. PCLMULQDQ Quadword Selection of Immediate Byte:
| Imm[4]| Imm[0]CL_MUL( SRC21[63:0], SRC1[63:0]     | PCLMULQDQ Operation 0 0 1 1
|       | ) CL_MUL( SRC2[63:0], SRC1[127:64] )      |                            
|       | CL_MUL( SRC2[127:64], SRC1[63:0] ) CL_MUL(|                            
|       | SRC2[127:64], SRC1[127:64] )              |                            
Notes: 1. SRC2 denotes the second source operand, which can be a register or
memory; SRC1 denotes the first source and destination operand.

The first source operand and the destination operand are the same and must be
an XMM register. The second source operand can be an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged.

Compilers and assemblers may implement the following pseudo-op syntax to simply
programming and emit the required encoding for Imm8.


Table 4-11. Pseudo-Op and PCLMULQDQ Implementation:
| Pseudo-Op              | Imm8 Encoding
| PCLMULLQLQDQ xmm1, xmm2| 0000_0000B   
| PCLMULHQLQDQ xmm1, xmm2| 0000_0001B   
| PCLMULLQHDQ xmm1, xmm2 | 0001_0000B   
| PCLMULHQHDQ xmm1, xmm2 | 0001_0001B   
Operation:

PCLMULQDQ
IF (Imm8[0] = 0 )
  THEN
     TEMP1 <- SRC1 [63:0];
  ELSE
     TEMP1 <- SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
  THEN
     TEMP2 <- SRC2 [63:0];
  ELSE
     TEMP2 <- SRC2 [127:64];
FI
For i = 0 to 63 {
  TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);
  For j = 1 to i {
     TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
  }
  DEST[ i ] <- TmpB[ i ];
}
For i = 64 to 126 {
  TmpB [ i ] <- 0;
  For j = i - 63 to 63 {
     TmpB [ i ] <- TmpB [ i ] xor (TEMP1[ j ] and TEMP2[ i - j ])
  }
  DEST[ i ] <- TmpB[ i ];
}
DEST[127] <- 0;
DEST[VLMAX-1:128] (Unmodified)
VPCLMULQDQ
IF (Imm8[0] = 0 )
  THEN
     TEMP1 <- SRC1 [63:0];
  ELSE
     TEMP1 <- SRC1 [127:64];
FI
IF (Imm8[4] = 0 )
  THEN
     TEMP2 <- SRC2 [63:0];
  ELSE
     TEMP2 <- SRC2 [127:64];
FI
For i = 0 to 63 {
  TmpB [ i ] <- (TEMP1[ 0 ] and TEMP2[ i ]);
  For j = 1 to i {
     TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
  }
  DEST[i] <- TmpB[i];
}
For i = 64 to 126 {
  TmpB [ i ] <- 0;
  For j = i - 63 to 63 {
     TmpB [i] <- TmpB [i] xor (TEMP1[ j ] and TEMP2[ i - j ])
  }
  DEST[i] <- TmpB[i];
}
DEST[VLMAX-1:127] <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PCLMULQDQ:| __m128i| _mm_clmulepi64_si128 (__m128i, __m128i,
|              |        | const int)                             

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: PCMPEQB
description:
PCMPEQB/PCMPEQW/PCMPEQD -  Compare Packed Data for Equal:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F 74 /r1 PCMPEQB mm, mm/m64          | RM   | V/V                   | MMX               | Compare packed bytes in mm/m64 and mm  
|                                       |      |                       |                   | for equality.                          
| 66 0F 74 /r PCMPEQB xmm1, xmm2/m128   | RM   | V/V                   | SSE2              | Compare packed bytes in xmm2/m128 and  
|                                       |      |                       |                   | xmm1 for equality.                     
| 0F 75 /r1 PCMPEQW mm, mm/m64          | RM   | V/V                   | MMX               | Compare packed words in mm/m64 and mm  
|                                       |      |                       |                   | for equality.                          
| 66 0F 75 /r PCMPEQW xmm1, xmm2/m128   | RM   | V/V                   | SSE2              | Compare packed words in xmm2/m128 and  
|                                       |      |                       |                   | xmm1 for equality.                     
| 0F 76 /r1 PCMPEQD mm, mm/m64          | RM   | V/V                   | MMX               | Compare packed doublewords in mm/m64   
|                                       |      |                       |                   | and mm for equality.                   
| 66 0F 76 /r PCMPEQD xmm1, xmm2/m128   | RM   | V/V                   | SSE2              | Compare packed doublewords in xmm2/m128
|                                       |      |                       |                   | and xmm1 for equality.                 
| VEX.NDS.128.66.0F.WIG 74 /r VPCMPEQB  | RVM  | V/V                   | AVX               | Compare packed bytes in xmm3/m128 and  
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | xmm2 for equality.                     
| VEX.NDS.128.66.0F.WIG 75 /r VPCMPEQW  | RVM  | V/V                   | AVX               | Compare packed words in xmm3/m128 and  
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | xmm2 for equality.                     
| VEX.NDS.128.66.0F.WIG 76 /r VPCMPEQD  | RVM  | V/V                   | AVX               | Compare packed doublewords in xmm3/m128
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | and xmm2 for equality.                 
| VEX.NDS.256.66.0F.WIG 75 /r VPCMPEQW  | RVM  | V/V                   | AVX2              | Compare packed words in ymm3/m256 and  
| ymm1, ymm2, ymm3 /m256                |      |                       |                   | ymm2 for equality.                     
| VEX.NDS.256.66.0F.WIG 76 /r VPCMPEQD  | RVM  | V/V                   | AVX2              | Compare packed doublewords in ymm3/m256
| ymm1, ymm2, ymm3 /m256                |      |                       |                   | and ymm2 for equality.                 
| VEX.NDS.256.66.0F38.WIG 29 /r VPCMPEQQ| RVM  | V/V                   | AVX2              | Compare packed quadwords in ymm3/m256  
| ymm1, ymm2, ymm3 /m256                |      |                       |                   | and ymm2 for equality.                 
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD compare for equality of the packed bytes, words, or doublewords
in the destination operand (first operand) and the source operand (second operand).
If a pair of data elements is equal, the corresponding data element in the destination
operand is set to all 1s; otherwise, it is set to all 0s.

The (V)PCMPEQB instruction compares the corresponding bytes in the destination
and source operands; the (V)PCMPEQW instruction compares the corresponding words
in the destination and source operands; and the (V)PCMPEQD instruction compares
the corresponding doublewords in the destination and source operands.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand can be an MMX technology
register. 128-bit Legacy SSE version: The second source operand can be an XMM
register or a 128-bit memory location. The first source and destination operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The second source operand can be
an XMM register or a 128-bit memory location. The first source and destination
operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand is a YMM register or a 256-bit memory location. The
destination operand is a YMM register. Note: VEX.L must be 0, otherwise the
instruction will #UD.

Operation:

PCMPEQB (with 64-bit operands)
  IF DEST[7:0] = SRC[7:0]
     THEN DEST[7:0) <- FFH;
     ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
  IF DEST[63:56] = SRC[63:56]
     THEN DEST[63:56] <- FFH;
     ELSE DEST[63:56] <- 0; FI;
PCMPEQB (with 128-bit operands)
  IF DEST[7:0] = SRC[7:0]
     THEN DEST[7:0) <- FFH;
     ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 15th bytes in DEST and SRC *)
  IF DEST[127:120] = SRC[127:120]
     THEN DEST[127:120] <- FFH;
     ELSE DEST[127:120] <- 0; FI;
VPCMPEQB (VEX.128 encoded version)
DEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] <- 0
VPCMPEQB (VEX.256 encoded version)
DEST[127:0] <-COMPARE_BYTES_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_BYTES_EQUAL(SRC1[255:128],SRC2[255:128])
PCMPEQW (with 64-bit operands)
  IF DEST[15:0] = SRC[15:0]
     THEN DEST[15:0] <- FFFFH;
     ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
  IF DEST[63:48] = SRC[63:48]
     THEN DEST[63:48] <- FFFFH;
     ELSE DEST[63:48] <- 0; FI;
PCMPEQW (with 128-bit operands)
  IF DEST[15:0] = SRC[15:0]
     THEN DEST[15:0] <- FFFFH;
     ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th words in DEST and SRC *)
  IF DEST[127:112] = SRC[127:112]
     THEN DEST[127:112] <- FFFFH;
     ELSE DEST[127:112] <- 0; FI;
VPCMPEQW (VEX.128 encoded version)
DEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] <- 0
VPCMPEQW (VEX.256 encoded version)
DEST[127:0] <-COMPARE_WORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_WORDS_EQUAL(SRC1[255:128],SRC2[255:128])
PCMPEQD (with 64-bit operands)
  IF DEST[31:0] = SRC[31:0]
     THEN DEST[31:0] <- FFFFFFFFH;
     ELSE DEST[31:0] <- 0; FI;
  IF DEST[63:32] = SRC[63:32]
     THEN DEST[63:32] <- FFFFFFFFH;
     ELSE DEST[63:32] <- 0; FI;
PCMPEQD (with 128-bit operands)
  IF DEST[31:0] = SRC[31:0]
     THEN DEST[31:0] <- FFFFFFFFH;
     ELSE DEST[31:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)
  IF DEST[127:96] = SRC[127:96]
     THEN DEST[127:96] <- FFFFFFFFH;
     ELSE DEST[127:96] <- 0; FI;
VPCMPEQD (VEX.128 encoded version)
DEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[VLMAX-1:128] <- 0
VPCMPEQD (VEX.256 encoded version)
DEST[127:0] <-COMPARE_DWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_DWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalents:
| PCMPEQB:   | __m64 _mm_cmpeq_pi8 (__m64 m1, __m64 
|            | m2)                                  
| PCMPEQW:   | __m64 _mm_cmpeq_pi16 (__m64 m1, __m64
|            | m2)                                  
| PCMPEQD:   | __m64 _mm_cmpeq_pi32 (__m64 m1, __m64
|            | m2)                                  
| (V)PCMPEQB:| __m128i _mm_cmpeq_epi8 ( __m128i a,  
|            | __m128i b)                           
| (V)PCMPEQW:| __m128i _mm_cmpeq_epi16 ( __m128i a, 
|            | __m128i b)                           
| (V)PCMPEQD:| __m128i _mm_cmpeq_epi32 ( __m128i a, 
|            | __m128i b)                           
| VPCMPEQB:  | __m256i _mm256_cmpeq_epi8 ( __m256i  
|            | a, __m256i b)                        
| VPCMPEQW:  | __m256i _mm256_cmpeq_epi16 ( __m256i 
|            | a, __m256i b)                        
| VPCMPEQD:  | __m256i _mm256_cmpeq_epi32 ( __m256i 
|            | a, __m256i b)                        

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PCMPEQQ
description:
PCMPEQQ  -  Compare Packed Qword Data for Equal:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 29 /r PCMPEQQ xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed qwords in xmm2/m128 and
|                                       |      |                       |                   | xmm1 for equality.                    
| VEX.NDS.128.66.0F38.WIG 29 /r VPCMPEQQ| RVM  | V/V                   | AVX               | Compare packed quadwords in xmm3/m128 
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | and xmm2 for equality.                
| VEX.NDS.256.66.0F38.WIG 29 /r VPCMPEQQ| RVM  | V/V                   | AVX2              | Compare packed quadwords in ymm3/m256 
| ymm1, ymm2, ymm3 /m256                |      |                       |                   | and ymm2 for equality.                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an SIMD compare for equality of the packed quadwords in the destination
operand (first operand) and the

| source operand (second operand). nation       | If a pair of data elements is equal, 
| is set to all 1s; otherwise, it is set        | the corresponding data element in the
| to 0s. 128-bit Legacy SSE version: The        | desti-                               
| second source operand can be an XMM           |                                      
| register or a 128-bit memory location.        |                                      
| The first source and destination operands     |                                      
| are XMM registers. Bits (VLMAX-1:128)         |                                      
| of the corresponding YMM destination          |                                      
| register remain unchanged. VEX.128 encoded    |                                      
| version: The second source operand can        |                                      
| be an XMM register or a 128-bit memory        |                                      
| location. The first source and destination    |                                      
| operands are XMM registers. Bits (VLMAX-1:128)|                                      
| of the corresponding YMM register are         |                                      
| zeroed. VEX.256 encoded version: The          |                                      
| first source operand is a YMM register.       |                                      
| The second source operand is a YMM register   |                                      
| or a 256-bit memory location. The destination |                                      
| operand is a YMM register. Note: VEX.L        |                                      
| must be 0, otherwise the instruction          |                                      
| will #UD.                                     |                                      
Operation:

IF (DEST[63:0] = SRC[63:0])
  THEN DEST[63:0] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[63:0] <- 0; FI;
IF (DEST[127:64] = SRC[127:64])
  THEN DEST[127:64] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[127:64] <- 0; FI;
VPCMPEQQ (VEX.128 encoded version)
DEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0
VPCMPEQQ (VEX.256 encoded version)
DEST[127:0] <-COMPARE_QWORDS_EQUAL(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_QWORDS_EQUAL(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PCMPEQQ:| __m128i _mm_cmpeq_epi64(__m128i a, __m128i
|            | b);                                       
| VPCMPEQQ:  | __m256i _mm256_cmpeq_epi64( __m256i       
|            | a, __m256i b);                            

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PCMPESTRI
description:
PCMPESTRI  -  Packed Compare Explicit Length Strings, Return Index:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 3A 61 /r imm8 PCMPESTRI xmm1,    | RMI  | V/V                   | SSE4_2            | Perform a packed comparison of string 
| xmm2/m128, imm8                        |      |                       |                   | data with explicit lengths, generating
|                                        |      |                       |                   | an index, and storing the result in   
|                                        |      |                       |                   | ECX.                                  
| VEX.128.66.0F3A.WIG 61 /r ib VPCMPESTRI| RMI  | V/V                   | AVX               | Perform a packed comparison of string 
| xmm1, xmm2/m128, imm8                  |      |                       |                   | data with explicit lengths, generating
|                                        |      |                       |                   | an index, and storing the result in   
|                                        |      |                       |                   | ECX.                                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (r)| ModRM:r/m (r)| imm8     | NA       

Description:
The instruction compares and processes data from two string fragments based
on the encoded value in the Imm8 Control Byte (see Section 4.1, “Imm8 Control
Byte Operation for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates
an index stored to the count register (ECX/RCX).

Each string fragment is represented by two values. The first value is an xmm
(or possibly m128 for the second

| operand) which contains the data elements| The second value is stored in an input
| of the string (byte or word data). length|                                       
| register. The input length register      |                                       
| is EAX/RAX (for xmm1) or EDX/RDX (for    |                                       
| xmm2/m128). The length represents the    |                                       
| number of bytes/words which are valid    |                                       
| for the respective xmm/m128 data. The    |                                       
| length of each input is interpreted      |                                       
| as being the absolute-value of the value |                                       
| in the length register. The absolutevalue|                                       
| computation saturates to 16 (for bytes)  |                                       
| and 8 (for words), based on the value    |                                       
| of imm8[bit3] when the value in the      |                                       
| length register is greater than 16 (8)   |                                       
| or less than -16 (-8). The comparison    |                                       
| and aggregation operations are performed |                                       
| according to the encoded value of Imm8   |                                       
| bit fields (see Section 4.1). The index  |                                       
| of the first (or last, according to      |                                       
| imm8[6]) set bit of IntRes2 (see Section |                                       
| 4.1.4) is returned in ECX. If no bits    |                                       
| are set in IntRes2, ECX is set to 16     |                                       
| (8). Note that the Arithmetic Flags      |                                       
| are written in a non-standard manner     |                                       
| in order to supply the most relevant     |                                       
| information:                             |                                       
CFlag - Reset if IntRes2 is equal to zero, set otherwise ZFlag - Set if absolute-value
of EDX is < 16 (8), reset otherwise SFlag - Set if absolute-value of EAX is
< 16 (8), reset otherwise OFlag - IntRes2[0]AFlag - Reset PFlag - Reset


Effective Operand Size:
| Operating mode/size| Operand 1| Operand 2| Length 1| Length 2| Result
| 16 bit             | xmm      | xmm/m128 | EAX     | EDX     | ECX   
| 32 bit             | xmm      | xmm/m128 | EAX     | EDX     | ECX   
| 64 bit             | xmm      | xmm/m128 | EAX     | EDX     | ECX   
| 64 bit + REX.W     | xmm      | xmm/m128 | RAX     | RDX     | RCX   

Intel C/C++ Compiler Intrinsic Equivalent For Returning Index:
| int| _mm_cmpestri (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             

Intel C/C++ Compiler Intrinsics For Reading EFlag Results:
| int| _mm_cmpestra (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrc (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestro (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrs (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrz (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally, this instruction does not cause #GP if
the memory operand is not aligned to 16 Byte boundary, and

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PCMPESTRM
description:
PCMPESTRM  -  Packed Compare Explicit Length Strings, Return Mask:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 3A 60 /r imm8 PCMPESTRM xmm1,    | RMI  | V/V                   | SSE4_2            | Perform a packed comparison of string  
| xmm2/m128, imm8                        |      |                       |                   | data with explicit lengths, generating 
|                                        |      |                       |                   | a mask, and storing the result in XMM0 
| VEX.128.66.0F3A.WIG 60 /r ib VPCMPESTRM| RMI  | V/V                   | AVX               | Perform a packed comparison of string  
| xmm1, xmm2/m128, imm8                  |      |                       |                   | data with explicit lengths, generating 
|                                        |      |                       |                   | a mask, and storing the result in XMM0.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (r)| ModRM:r/m (r)| imm8     | NA       

Description:
The instruction compares data from two string fragments based on the encoded
value in the imm8 contol byte (see Section 4.1, “Imm8 Control Byte Operation
for PCMPESTRI / PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates a mask stored
to XMM0.

Each string fragment is represented by two values. The first value is an xmm
(or possibly m128 for the second operand) which contains the data elements of
the string (byte or word data). The second value is stored in an input length
register. The input length register is EAX/RAX (for xmm1) or EDX/RDX (for xmm2/m128).
The length represents the number of bytes/words which are valid for the respective
xmm/m128 data.

The length of each input is interpreted as being the absolute-value of the value
in the length register. The absolutevalue computation saturates to 16 (for bytes)
and 8 (for words), based on the value of imm8[bit3] when the value in the length
register is greater than 16 (8) or less than -16 (-8).

The comparison and aggregation operations are performed according to the encoded
value of Imm8 bit fields (see Section 4.1). As defined by imm8[6], IntRes2 is
then either stored to the least significant bits of XMM0 (zero extended to 128
bits) or expanded into a byte/word-mask and then stored to XMM0.

Note that the Arithmetic Flags are written in a non-standard manner in order
to supply the most relevant information:

CFlag - Reset if IntRes2 is equal to zero, set otherwise ZFlag - Set if absolute-value
of EDX is < 16 (8), reset otherwise SFlag - Set if absolute-value of EAX is
< 16 (8), reset otherwise OFlag -IntRes2[0]AFlag - Reset PFlag - Reset

Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv
is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will
#UD.


Effective Operand Size:
| Operating mode/size| Operand1| Operand 2| Length1| Length2| Result
| 16 bit             | xmm     | xmm/m128 | EAX    | EDX    | XMM0  
| 32 bit             | xmm     | xmm/m128 | EAX    | EDX    | XMM0  
| 64 bit             | xmm     | xmm/m128 | EAX    | EDX    | XMM0  
| 64 bit + REX.W     | xmm     | xmm/m128 | RAX    | RDX    | XMM0  

Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask:
__m128i _mm_cmpestrm (__m128i a, int la, __m128i b, int lb, const int mode);


Intel C/C++ Compiler Intrinsics For Reading EFlag Results:
| int| _mm_cmpestra (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrc (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestro (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrs (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             
| int| _mm_cmpestrz (__m128i a, int la, __m128i
|    | b, int lb, const int mode);             

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally, this instruction does not cause #GP if
the memory operand is not aligned to 16 Byte boundary, and

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PCMPGTB
description:
PCMPGTB/PCMPGTW/PCMPGTD - Compare Packed Signed Integers for Greater Than:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F 64 /r1 PCMPGTB mm, mm/m64        | RM   | V/V                   | MMX               | Compare packed signed byte integers      
|                                     |      |                       |                   | in mm and mm/m64 for greater than.       
| 66 0F 64 /r PCMPGTB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare packed signed byte integers      
|                                     |      |                       |                   | in xmm1 and xmm2/m128 for greater than.  
| 0F 65 /r1 PCMPGTW mm, mm/m64        | RM   | V/V                   | MMX               | Compare packed signed word integers      
|                                     |      |                       |                   | in mm and mm/m64 for greater than.       
| 66 0F 65 /r PCMPGTW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare packed signed word integers      
|                                     |      |                       |                   | in xmm1 and xmm2/m128 for greater than.  
| 0F 66 /r1 PCMPGTD mm, mm/m64        | RM   | V/V                   | MMX               | Compare packed signed doubleword integers
|                                     |      |                       |                   | in mm and mm/m64 for greater than.       
| 66 0F 66 /r PCMPGTD xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare packed signed doubleword integers
|                                     |      |                       |                   | in xmm1 and xmm2/m128 for greater than.  
| VEX.NDS.128.66.0F.WIG 64 /r VPCMPGTB| RVM  | V/V                   | AVX               | Compare packed signed byte integers      
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm2 and xmm3/m128 for greater than.  
| VEX.NDS.128.66.0F.WIG 65 /r VPCMPGTW| RVM  | V/V                   | AVX               | Compare packed signed word integers      
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm2 and xmm3/m128 for greater than.  
| VEX.NDS.128.66.0F.WIG 66 /r VPCMPGTD| RVM  | V/V                   | AVX               | Compare packed signed doubleword integers
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm2 and xmm3/m128 for greater than.  
| VEX.NDS.256.66.0F.WIG 64 /r VPCMPGTB| RVM  | V/V                   | AVX2              | Compare packed signed byte integers      
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm2 and ymm3/m256 for greater than.  
| VEX.NDS.256.66.0F.WIG 65 /r VPCMPGTW| RVM  | V/V                   | AVX2              | Compare packed signed word integers      
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm2 and ymm3/m256 for greater than.  
| VEX.NDS.256.66.0F.WIG 66 /r VPCMPGTD| RVM  | V/V                   | AVX2              | Compare packed signed doubleword integers
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm2 and ymm3/m256 for greater than.  
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an SIMD signed compare for the greater value of the packed byte, word,
or doubleword integers in the destination operand (first operand) and the source
operand (second operand). If a data element in the destination operand is greater
than the corresponding date element in the source operand, the corresponding
data element in the destination operand is set to all 1s; otherwise, it is set
to all 0s.

The PCMPGTB instruction compares the corresponding signed byte integers in the
destination and source operands; the PCMPGTW instruction compares the corresponding
signed word integers in the destination and source

operands; and the PCMPGTD instruction compares the corresponding signed doubleword
integers in the destination and source operands. In 64-bit mode, using a REX
prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand can be an MMX technology
register. 128-bit Legacy SSE version: The second source operand can be an XMM
register or a 128-bit memory location. The first source operand and destination
operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: The second source operand
can be an XMM register or a 128-bit memory location. The first source operand
and destination operand are XMM registers. Bits (VLMAX-1:128) of the corresponding
YMM register are zeroed. VEX.256 encoded version: The first source operand is
a YMM register. The second source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PCMPGTB (with 64-bit operands)
  IF DEST[7:0] > SRC[7:0]
     THEN DEST[7:0) <- FFH;
     ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th bytes in DEST and SRC *)
  IF DEST[63:56] > SRC[63:56]
     THEN DEST[63:56] <- FFH;
     ELSE DEST[63:56] <- 0; FI;
PCMPGTB (with 128-bit operands)
  IF DEST[7:0] > SRC[7:0]
     THEN DEST[7:0) <- FFH;
     ELSE DEST[7:0] <- 0; FI;
  (* Continue comparison of 2nd through 15th bytes in DEST and SRC *)
  IF DEST[127:120] > SRC[127:120]
     THEN DEST[127:120] <- FFH;
     ELSE DEST[127:120] <- 0; FI;
VPCMPGTB (VEX.128 encoded version)
DEST[127:0] <-COMPARE_BYTES_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0
VPCMPGTB (VEX.256 encoded version)
DEST[127:0] <-COMPARE_BYTES_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_BYTES_GREATER(SRC1[255:128],SRC2[255:128])
PCMPGTW (with 64-bit operands)
  IF DEST[15:0] > SRC[15:0]
     THEN DEST[15:0] <- FFFFH;
     ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd words in DEST and SRC *)
  IF DEST[63:48] > SRC[63:48]
     THEN DEST[63:48] <- FFFFH;
     ELSE DEST[63:48] <- 0; FI;
PCMPGTW (with 128-bit operands)
  IF DEST[15:0] > SRC[15:0]
     THEN DEST[15:0] <- FFFFH;
     ELSE DEST[15:0] <- 0; FI;
  (* Continue comparison of 2nd through 7th words in DEST and SRC *)
  IF DEST[63:48] > SRC[127:112]
     THEN DEST[127:112] <- FFFFH;
     ELSE DEST[127:112] <- 0; FI;
VPCMPGTW (VEX.128 encoded version)
DEST[127:0] <-COMPARE_WORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0
VPCMPGTW (VEX.256 encoded version)
DEST[127:0] <-COMPARE_WORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_WORDS_GREATER(SRC1[255:128],SRC2[255:128])
PCMPGTD (with 64-bit operands)
  IF DEST[31:0] > SRC[31:0]
     THEN DEST[31:0] <- FFFFFFFFH;
     ELSE DEST[31:0] <- 0; FI;
  IF DEST[63:32] > SRC[63:32]
     THEN DEST[63:32] <- FFFFFFFFH;
     ELSE DEST[63:32] <- 0; FI;
PCMPGTD (with 128-bit operands)
  IF DEST[31:0] > SRC[31:0]
     THEN DEST[31:0] <- FFFFFFFFH;
     ELSE DEST[31:0] <- 0; FI;
  (* Continue comparison of 2nd and 3rd doublewords in DEST and SRC *)
  IF DEST[127:96] > SRC[127:96]
     THEN DEST[127:96] <- FFFFFFFFH;
     ELSE DEST[127:96] <- 0; FI;
VPCMPGTD (VEX.128 encoded version)
DEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0
VPCMPGTD (VEX.256 encoded version)
DEST[127:0] <-COMPARE_DWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_DWORDS_GREATER(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalents:
| PCMPGTB:   | __m64 _mm_cmpgt_pi8 (__m64 m1, __m64  
|            | m2)                                   
| PCMPGTW:   | __m64 _mm_pcmpgt_pi16 (__m64 m1, __m64
|            | m2)                                   
| DCMPGTD:   | __m64 _mm_pcmpgt_pi32 (__m64 m1, __m64
|            | m2)                                   
| (V)PCMPGTB:| __m128i _mm_cmpgt_epi8 ( __m128i a,   
|            | __m128i b)                            
| (V)PCMPGTW:| __m128i _mm_cmpgt_epi16 ( __m128i a,  
|            | __m128i b)                            
| (V)DCMPGTD:| __m128i _mm_cmpgt_epi32 ( __m128i a,  
|            | __m128i b)                            
| VPCMPGTB:  | __m256i _mm256_cmpgt_epi8 ( __m256i   
|            | a, __m256i b)                         
| VPCMPGTW:  | __m256i _mm256_cmpgt_epi16 ( __m256i  
|            | a, __m256i b)                         
| VPCMPGTD:  | __m256i _mm256_cmpgt_epi32 ( __m256i  
|            | a, __m256i b)                         

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PCMPGTQ
description:
PCMPGTQ  -  Compare Packed Data for Greater Than:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 66 0F 38 37 /r PCMPGTQ xmm1,xmm2/m128 | RM   | V/V                   | SSE4_2            | Compare packed signed qwords in xmm2/m128
|                                       |      |                       |                   | and xmm1 for greater than.               
| VEX.NDS.128.66.0F38.WIG 37 /r VPCMPGTQ| RVM  | V/V                   | AVX               | Compare packed signed qwords in xmm2     
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | and xmm3/m128 for greater than.          
| VEX.NDS.256.66.0F38.WIG 37 /r VPCMPGTQ| RVM  | V/V                   | AVX2              | Compare packed signed qwords in ymm2     
| ymm1, ymm2, ymm3/m256                 |      |                       |                   | and ymm3/m256 for greater than.          

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an SIMD signed compare for the packed quadwords in the destination
operand (first operand) and the source operand (second operand). If the data
element in the first (destination) operand is greater than the corresponding
element in the second (source) operand, the corresponding data element in the
destination is set to all 1s; otherwise, it is set to 0s.

128-bit Legacy SSE version: The second source operand can be an XMM register
or a 128-bit memory location. The first source operand and destination operand
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The second source operand can be
an XMM register or a 128-bit memory location. The first source operand and destination
operand are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM register
are zeroed. VEX.256 encoded version: The first source operand is a YMM register.
The second source operand is a YMM register or a 256-bit memory location. The
destination operand is a YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[63-0] > SRC[63-0])
  THEN DEST[63-0] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[63-0] <- 0; FI
IF (DEST[127-64] > SRC[127-64])
  THEN DEST[127-64] <- FFFFFFFFFFFFFFFFH;
  ELSE DEST[127-64] <- 0; FI
VPCMPGTQ (VEX.128 encoded version)
DEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1,SRC2)
DEST[VLMAX-1:128] <- 0
VPCMPGTQ (VEX.256 encoded version)
DEST[127:0] <-COMPARE_QWORDS_GREATER(SRC1[127:0],SRC2[127:0])
DEST[255:128] <-COMPARE_QWORDS_GREATER(SRC1[255:128],SRC2[255:128])

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PCMPGTQ:| __m128i _mm_cmpgt_epi64(__m128i a, __m128i
|            | b)                                        
| VPCMPGTQ:  | __m256i _mm256_cmpgt_epi64( __m256i       
|            | a, __m256i b);                            

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PCMPISTRI
description:
PCMPISTRI  -  Packed Compare Implicit Length Strings, Return Index:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 3A 63 /r imm8 PCMPISTRI xmm1,    | RM   | V/V                   | SSE4_2            | Perform a packed comparison of string 
| xmm2/m128, imm8                        |      |                       |                   | data with implicit lengths, generating
|                                        |      |                       |                   | an index, and storing the result in   
|                                        |      |                       |                   | ECX.                                  
| VEX.128.66.0F3A.WIG 63 /r ib VPCMPISTRI| RM   | V/V                   | AVX               | Perform a packed comparison of string 
| xmm1, xmm2/m128, imm8                  |      |                       |                   | data with implicit lengths, generating
|                                        |      |                       |                   | an index, and storing the result in   
|                                        |      |                       |                   | ECX.                                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| imm8     | NA       

Description:
The instruction compares data from two strings based on the encoded value in
the Imm8 Control Byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI
/ PCMPESTRM / PCMPISTRI / PCMPISTRM”), and generates an index stored to ECX.

| Each string is represented by a single        | The value is an xmm (or possibly m128     
| value. contains the data elements of          | for the second operand) which Each input  
| the string (byte or word data). valid/invalid | byte/word is augmented with a A byte/word 
| tag. byte/word. The comparison and aggregation| is considered valid only if it has a      
| operations are performed according to         | lower index than the least significant    
| the encoded value of Imm8 bit fields          | null (The least significant null byte/word
| (see Section 4.1). The index of the           | is also considered invalid.)              
| first (or last, according to imm8[6])         |                                           
| set bit of IntRes2 is returned in ECX.        |                                           
| If no bits are set in IntRes2, ECX is         |                                           
| set to 16 (8). Note that the Arithmetic       |                                           
| Flags are written in a non-standard           |                                           
| manner in order to supply the most relevant   |                                           
| information:                                  |                                           
CFlag - Reset if IntRes2 is equal to zero, set otherwise ZFlag - Set if any
byte/word of xmm2/mem128 is null, reset otherwise SFlag - Set if any byte/word
of xmm1 is null, reset otherwise OFlag -IntRes2[0]AFlag - Reset PFlag - Reset
Note: In VEX.128 encoded version, VEX.vvvv is reserved and must be 1111b, VEX.L
must be 0, otherwise the instruction will #UD.


Effective Operand Size:
| Operating mode/size| Operand1| Operand 2| Result
| 16 bit             | xmm     | xmm/m128 | ECX   
| 32 bit             | xmm     | xmm/m128 | ECX   
| 64 bit             | xmm     | xmm/m128 | ECX   
| 64 bit + REX.W     | xmm     | xmm/m128 | RCX   

Intel C/C++ Compiler Intrinsic Equivalent For Returning Index:
| int| _mm_cmpistri (__m128i a, __m128i b,
|    | const int mode);                   

Intel C/C++ Compiler Intrinsics For Reading EFlag Results:
| int| _mm_cmpistra (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrc (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistro (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrs (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrz (__m128i a, __m128i b,
|    | const int mode);                   

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally, this instruction does not cause #GP if
the memory operand is not aligned to 16 Byte boundary, and

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PCMPISTRM
description:
PCMPISTRM  -  Packed Compare Implicit Length Strings, Return Mask:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 3A 62 /r imm8 PCMPISTRM xmm1,    | RM   | V/V                   | SSE4_2            | Perform a packed comparison of string  
| xmm2/m128, imm8                        |      |                       |                   | data with implicit lengths, generating 
|                                        |      |                       |                   | a mask, and storing the result in XMM0.
| VEX.128.66.0F3A.WIG 62 /r ib VPCMPISTRM| RM   | V/V                   | AVX               | Perform a packed comparison of string  
| xmm1, xmm2/m128, imm8                  |      |                       |                   | data with implicit lengths, generating 
|                                        |      |                       |                   | a Mask, and storing the result in XMM0.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| imm8     | NA       

Description:
The instruction compares data from two strings based on the encoded value in
the imm8 byte (see Section 4.1, “Imm8 Control Byte Operation for PCMPESTRI /
PCMPESTRM / PCMPISTRI / PCMPISTRM”) generating a mask stored to XMM0.

Each string is represented by a single value. The value is an xmm (or possibly
m128 for the second operand) which

| contains the data elements of the string | Each input byte/word is augmented with     
| (byte or word data). valid/invalid tag.  | a A byte/word is considered valid only     
| byte/word. The comparison and aggregation| if it has a lower index than the least     
| operation are performed according to     | significant null (The least significant    
| the encoded value of Imm8 bit fields     | null byte/word is also considered invalid.)
| (see Section 4.1). As defined by imm8[6],|                                            
| IntRes2 is then either stored to the     |                                            
| least significant bits of XMM0 (zero     |                                            
| extended to 128 bits) or expanded into   |                                            
| a byte/word-mask and then stored to      |                                            
| XMM0. Note that the Arithmetic Flags     |                                            
| are written in a non-standard manner     |                                            
| in order to supply the most relevant     |                                            
| information:                             |                                            
CFlag - Reset if IntRes2 is equal to zero, set otherwise ZFlag - Set if any
byte/word of xmm2/mem128 is null, reset otherwise SFlag - Set if any byte/word
of xmm1 is null, reset otherwise OFlag - IntRes2[0]AFlag - Reset PFlag - Reset
Note: In VEX.128 encoded versions, bits (VLMAX-1:128) of XMM0 are zeroed. VEX.vvvv
is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will
#UD.


Effective Operand Size:
| Operating mode/size| Operand1| Operand 2| Result
| 16 bit             | xmm     | xmm/m128 | XMM0  
| 32 bit             | xmm     | xmm/m128 | XMM0  
| 64 bit             | xmm     | xmm/m128 | XMM0  
| 64 bit + REX.W     | xmm     | xmm/m128 | XMM0  

Intel C/C++ Compiler Intrinsic Equivalent For Returning Mask:
__m128i _mm_cmpistrm (__m128i a, __m128i b, const int mode);


Intel C/C++ Compiler Intrinsics For Reading EFlag Results:
| int| _mm_cmpistra (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrc (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistro (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrs (__m128i a, __m128i b,
|    | const int mode);                   
| int| _mm_cmpistrz (__m128i a, __m128i b,
|    | const int mode);                   

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally, this instruction does not cause #GP if
the memory operand is not aligned to 16 Byte boundary, and

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PDEP
description:
PDEP  -  Parallel Bits Deposit:
| Opcode/Instruction                    | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDS.LZ.F2.0F38.W0 F5 /r PDEP r32a,| RVM  | V/V            | BMI2              | Parallel deposit of bits from r32b using
| r32b, r/m32                           |      |                |                   | mask in r/m32, result is written to     
|                                       |      |                |                   | r32a.                                   
| VEX.NDS.LZ.F2.0F38.W1 F5 /r PDEP r64a,| RVM  | V/N.E.         | BMI2              | Parallel deposit of bits from r64b using
| r64b, r/m64                           |      |                |                   | mask in r/m64, result is written to     
|                                       |      |                |                   | r64a.                                   

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2   | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
PDEP uses a mask in the second source operand (the third operand) to transfer/scatter
contiguous low order bits in the first source operand (the second operand) into
the destination (the first operand). PDEP takes the low bits from the first
source operand and deposit them in the destination operand at the corresponding
bit locations that are set in the second source operand (mask). All other bits
(bits not set in mask) in destination are set to zero.

| SRC1| S<sub>31</sub>| S<sub>30</sub>| S<sub>29</sub> S<sub>28</sub>| S<sub>27</sub>| S<sub>7</sub>| S<sub>6</sub>| S<sub>5</sub>| S<sub>4</sub>| S<sub>3</sub>| S<sub>2</sub>| S<sub>1</sub>| S 0
SRC2

| 0| 0| 0| 1            | 0            | 1                         | 0| 1            | 0| 0| 1            | 0| 0 (mask)
| 0| 0| 0| S<sub>3</sub>| 0 Figure 4-4.| S<sub>2</sub> PDEP Example| 0| S<sub>1</sub>| 0| 0| S<sub>0</sub>| 0| 0 bit 0 
This instruction is not supported in real mode and virtual-8086 mode. The operand
size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64
requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute
this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

TEMP <- SRC1;
MASK <- SRC2;
DEST <- 0 ;
m<- 0, k<- 0;
DO WHILE m< OperandSize
     IF MASK[ m] = 1 THEN
       DEST[ m] <- TEMP[ k];
       k <- k+ 1;
     FI
     m <- m+ 1;
OD

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| PDEP:| unsigned __int32 _pdep_u32(unsigned 
|      | __int32 src, unsigned __int32 mask);
| PDEP:| unsigned __int64 _pdep_u64(unsigned 
|      | __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: PEXT
description:
PEXT  -  Parallel Bits Extract:
| Opcode/Instruction                    | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                             
| VEX.NDS.LZ.F3.0F38.W0 F5 /r PEXT r32a,| RVM  | V/V            | BMI2              | Parallel extract of bits from r32b using
| r32b, r/m32                           |      |                |                   | mask in r/m32, result is written to     
|                                       |      |                |                   | r32a.                                   
| VEX.NDS.LZ.F3.0F38.W1 F5 /r PEXT r64a,| RVM  | V/N.E.         | BMI2              | Parallel extract of bits from r64b using
| r64b, r/m64                           |      |                |                   | mask in r/m64, result is written to     
|                                       |      |                |                   | r64a.                                   

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2   | Operand 3    | Operand 4
| RVM  | ModRM:reg (w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
PEXT uses a mask in the second source operand (the third operand) to transfer
either contiguous or non-contiguous bits in the first source operand (the second
operand) to contiguous low order bit positions in the destination (the first
operand). For each bit set in the MASK, PEXT extracts the corresponding bits
from the first source operand and writes them into contiguous lower bits of
destination operand. The remaining upper bits of destination are zeroed.

SRC1

| S<sub>31</sub>| S<sub>30</sub>| S<sub>29</sub> S<sub>28</sub>| S<sub>27</sub>| S<sub>7</sub>| S<sub>6</sub>| S<sub>5</sub>| S<sub>4</sub>| S<sub>3</sub>| S<sub>2</sub>| S<sub>1</sub>| S<sub>0</sub>
SRC2

| 0| 0| 0| 1| 0            | 1             | 0| 1| 0| 0             | 1            | 0            | 0 (mask)           
| 0| 0| 0| 0| 0 Figure 4-5.| 0 PEXT Example| 0| 0| 0| S<sub>28</sub>| S<sub>7</sub>| S<sub>5</sub>| S<sub>2</sub> bit 0
This instruction is not supported in real mode and virtual-8086 mode. The operand
size is always 32 bits if not in 64-bit mode. In 64-bit mode operand size 64
requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt to execute
this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

TEMP <- SRC1;
MASK <- SRC2;
DEST <- 0 ;
m<- 0, k<- 0;
DO WHILE m< OperandSize
     IF MASK[ m] = 1 THEN
       DEST[ k] <- TEMP[ m];
       k <- k+ 1;
     FI
     m <- m+ 1;
OD

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
| PEXT:| unsigned __int32 _pext_u32(unsigned 
|      | __int32 src, unsigned __int32 mask);
| PEXT:| unsigned __int64 _pext_u64(unsigned 
|      | __int64 src, unsigned __int32 mask);

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: PEXTRB
description:
PEXTRB/PEXTRD/PEXTRQ  -  Extract Byte/Dword/Qword:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 3A 14 /r ib PEXTRB reg/m8, xmm2,| MRI  | V/V                   | SSE4_1            | Extract a byte integer value from xmm2 
| imm8                                  |      |                       |                   | at the source byte offset specified    
|                                       |      |                       |                   | by imm8 into reg or m8. The upper bits 
|                                       |      |                       |                   | of r32 or r64 are zeroed.              
| 66 0F 3A 16 /r ib PEXTRD r/m32, xmm2, | MRI  | V/V                   | SSE4_1            | Extract a dword integer value from xmm2
| imm8                                  |      |                       |                   | at the source dword offset specified   
|                                       |      |                       |                   | by imm8 into r/m32.                    
| 66 REX.W 0F 3A 16 /r ib PEXTRQ r/m64, | MRI  | V/N.E.                | SSE4_1            | Extract a qword integer value from xmm2
| xmm2, imm8                            |      |                       |                   | at the source qword offset specified   
|                                       |      |                       |                   | by imm8 into r/m64.                    
| VEX.128.66.0F3A.W0 14 /r ib VPEXTRB   | MRI  | V1/V                  | AVX               | Extract a byte integer value from xmm2 
| reg/m8, xmm2, imm8                    |      |                       |                   | at the source byte offset specified    
|                                       |      |                       |                   | by imm8 into reg or m8. The upper bits 
|                                       |      |                       |                   | of r64/r32 is filled with zeros.       
| VEX.128.66.0F3A.W0 16 /r ib VPEXTRD   | MRI  | V/V                   | AVX               | Extract a dword integer value from xmm2
| r32/m32, xmm2, imm8                   |      |                       |                   | at the source dword offset specified   
|                                       |      |                       |                   | by imm8 into r32/m32.                  
| VEX.128.66.0F3A.W1 16 /r ib VPEXTRQ   | MRI  | V/i                   | AVX               | Extract a qword integer value from xmm2
| r64/m64, xmm2, imm8                   |      |                       |                   | at the source dword offset specified   
|                                       |      |                       |                   | by imm8 into r64/m64.                  
Notes: 1. In 64-bit mode, VEX.W1 is ignored for VPEXTRB (similar to legacy REX.W=1
prefix in PEXTRB).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MRI  | ModRM:r/m (w)| ModRM:reg (r)| imm8     | NA       

Description:
Extract a byte/dword/qword integer value from the source XMM register at a byte/dword/qword
offset determined from imm8[3:0]. The destination can be a register or byte/dword/qword
memory location. If the destination is a register, the upper bits of the register
are zero extended. In legacy non-VEX encoded version and if the destination
operand is a register, the default operand size in 64-bit mode for PEXTRB/PEXTRD
is 64 bits, the bits above the least significant byte/dword data are filled
with zeros. PEXTRQ is not encodable in non-64-bit modes and requires REX.W in
64-bit mode. Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must
be 1111b, VEX.L must be 0, otherwise the instruction will #UD. If the destination
operand is a register, the default operand size in 64-bit mode for VPEXTRB/VPEXTRD
is 64 bits, the bits above the least significant byte/word/dword data are filled
with zeros. Attempt to execute VPEXTRQ in non-64-bit mode will cause #UD.

Operation:

CASE of
  PEXTRB: SEL <- COUNT[3:0];
       TEMP <- (Src >> SEL*8) AND FFH;
       IF (DEST = Mem8)
          THEN
          Mem8 <- TEMP[7:0];
       ELSE IF (64-Bit Mode and 64-bit register selected)
          THEN
             R64[7:0] <- TEMP[7:0];
             r64[63:8] <- ZERO_FILL; };
       ELSE
             R32[7:0] <- TEMP[7:0];
             r32[31:8] <- ZERO_FILL; };
       FI;
  PEXTRD:SEL <- COUNT[1:0];
       TEMP <- (Src >> SEL*32) AND FFFF_FFFFH;
       DEST <- TEMP;
  PEXTRQ: SEL <- COUNT[0];
       TEMP <- (Src >> SEL*64);
       DEST <- TEMP;
EASC:
(V)PEXTRTD/(V)PEXTRQ
IF (64-Bit Mode and 64-bit dest operand)
THEN
  Src_Offset <- Imm8[0]
  r64/m64 <-(Src >> Src_Offset * 64)
ELSE
  Src_Offset <- Imm8[1:0]
  r32/m32 <- ((Src >> Src_Offset *32) AND 0FFFFFFFFh);
FI
(V)PEXTRB ( dest=m8)
SRC_Offset <- Imm8[3:0]
Mem8 <- (Src >> Src_Offset*8)
(V)PEXTRB ( dest=reg)
IF (64-Bit Mode )
THEN
  SRC_Offset <- Imm8[3:0]
  DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh)
  DEST[63:8] <-ZERO_FILL;
ELSE
  SRC_Offset <-. Imm8[3:0];
  DEST[7:0] <- ((Src >> Src_Offset*8) AND 0FFh);
  DEST[31:8] <-ZERO_FILL;
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| PEXTRB:| int _mm_extract_epi8 (__m128i src, const
|        | int ndx);                               
| PEXTRD:| int _mm_extract_epi32 (__m128i src,     
|        | const int ndx);                         
| PEXTRQ:| __int64 _mm_extract_epi64 (__m128i src, 
|        | const int ndx);                         

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.    
|    | If VPEXTRQ in non-64-bit mode, VEX.W=1.


platform: x86
mnem: PEXTRW
description:
PEXTRW - Extract Word:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F C5 /r ib1 PEXTRW reg, mm, imm8     | RMI  | V/V                   | SSE               | Extract the word specified by imm8 from
|                                       |      |                       |                   | mm and move it to reg, bits 15-0. The  
|                                       |      |                       |                   | upper bits of r32 or r64 is zeroed.    
| 66 0F C5 /r ib PEXTRW reg, xmm, imm8  | RMI  | V/V                   | SSE2              | Extract the word specified by imm8 from
|                                       |      |                       |                   | xmm and move it to reg, bits 15-0. The 
|                                       |      |                       |                   | upper bits of r32 or r64 is zeroed.    
| 66 0F 3A 15 /r ib PEXTRW reg/m16, xmm,| MRI  | V/V                   | SSE4_1            | Extract the word specified by imm8 from
| imm8                                  |      |                       |                   | xmm and copy it to lowest 16 bits of   
|                                       |      |                       |                   | reg or m16. Zero-extend the result in  
|                                       |      |                       |                   | the destination, r32 or r64.           
| VEX.128.66.0F.W0 C5 /r ib VPEXTRW reg,| RMI  | V2/V                  | AVX               | Extract the word specified by imm8 from
| xmm1, imm8                            |      |                       |                   | xmm1 and move it to reg, bits 15:0.    
|                                       |      |                       |                   | Zeroextend the result. The upper bits  
|                                       |      |                       |                   | of r64/r32 is filled with zeros.       
| VEX.128.66.0F3A.W0 15 /r ib VPEXTRW   | MRI  | V/V                   | AVX               | Extract a word integer value from xmm2 
| reg/m16, xmm2, imm8                   |      |                       |                   | at the source word offset specified    
|                                       |      |                       |                   | by imm8 into reg or m16. The upper bits
|                                       |      |                       |                   | of r64/r32 is filled with zeros.       
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A. 2. In 64-bit mode, VEX.W1 is ignored for VPEXTRW (similar
to legacy REX.W=1 prefix in PEXTRW).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       
| MRI  | ModRM:r/m (w)| ModRM:reg (r)| imm8     | NA       

Description:
Copies the word in the source operand (second operand) specified by the count
operand (third operand) to the destination operand (first operand). The source
operand can be an MMX technology register or an XMM register. The destination
operand can be the low word of a general-purpose register or a 16-bit memory
address. The count operand is an 8-bit immediate. When specifying a word location
in an MMX technology register, the 2 least-significant bits of the count operand
specify the location; for an XMM register, the 3 least-significant bits specify
the location. The content of the destination register above bit 16 is cleared
(set to all 0s).

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15, R8-15). If the destination operand
is a general-purpose register, the default operand size is 64-bits in 64-bit
mode. Note: In VEX.128 encoded versions, VEX.vvvv is reserved and must be 1111b,
VEX.L must be 0, otherwise the instruction will #UD. If the destination operand
is a register, the default operand size in 64-bit mode for VPEXTRW is 64 bits,
the bits above the least significant byte/word/dword data are filled with zeros.

Operation:

IF (DEST = Mem16)
THEN
  SEL <- COUNT[2:0];
  TEMP <- (Src >> SEL*16) AND FFFFH;
  Mem16 <- TEMP[15:0];
ELSE IF (64-Bit Mode and destination is a general-purpose register)
  THEN
     FOR (PEXTRW instruction with 64-bit source operand)
      { SEL <- COUNT[1:0];
       TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
       r64[15:0] <- TEMP[15:0];
       r64[63:16] <- ZERO_FILL; };
     FOR (PEXTRW instruction with 128-bit source operand)
      { SEL <- COUNT[2:0];
       TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
       r64[15:0] <- TEMP[15:0];
       r64[63:16] <- ZERO_FILL; }
  ELSE
     FOR (PEXTRW instruction with 64-bit source operand)
      {
       TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
       r32[15:0] <- TEMP[15:0];
       r32[31:16] <- ZERO_FILL; };
     FOR (PEXTRW instruction with 128-bit source operand)
      {
       TEMP <- (SRC >> (SEL * 16)) AND FFFFH;
       r32[15:0] <- TEMP[15:0];
       r32[31:16] <- ZERO_FILL; };
  FI;
FI;
(V)PEXTRW ( dest=m16)
SRC_Offset <- Imm8[2:0]
Mem16 <- (Src >> Src_Offset*16)
(V)PEXTRW ( dest=reg)
IF (64-Bit Mode )
THEN
  SRC_Offset <- Imm8[2:0]
  DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)
  DEST[63:16] <-ZERO_FILL;
ELSE
  SRC_Offset <- Imm8[2:0]
  DEST[15:0] <- ((Src >> Src_Offset*16) AND 0FFFFh)
  DEST[31:16] <-ZERO_FILL;
FI

Intel C/C++ Compiler Intrinsic Equivalent:
| PEXTRW:| int _mm_extract_pi16 (__m64 a, int n) 
| PEXTRW:| int _mm_extract_epi16 ( __m128i a, int
|        | imm)                                  

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PHADDW
description:
PHADDW/PHADDD  -  Packed Horizontal Add:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 38 01 /r1 PHADDW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Add 16-bit integers horizontally, pack  
|                                      |      |                       |                   | to mm1.                                 
| 66 0F 38 01 /r PHADDW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Add 16-bit integers horizontally, pack  
|                                      |      |                       |                   | to xmm1.                                
| 0F 38 02 /r PHADDD mm1, mm2/m64      | RM   | V/V                   | SSSE3             | Add 32-bit integers horizontally, pack  
|                                      |      |                       |                   | to mm1.                                 
| 66 0F 38 02 /r PHADDD xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Add 32-bit integers horizontally, pack  
|                                      |      |                       |                   | to xmm1.                                
| VEX.NDS.128.66.0F38.WIG 01 /r VPHADDW| RVM  | V/V                   | AVX               | Add 16-bit integers horizontally, pack  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | to xmm1.                                
| VEX.NDS.128.66.0F38.WIG 02 /r VPHADDD| RVM  | V/V                   | AVX               | Add 32-bit integers horizontally, pack  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | to xmm1.                                
| VEX.NDS.256.66.0F38.WIG 01 /r VPHADDW| RVM  | V/V                   | AVX2              | Add 16-bit signed integers horizontally,
| ymm1, ymm2, ymm3/m256                |      |                       |                   | pack to ymm1.                           
| VEX.NDS.256.66.0F38.WIG 02 /r VPHADDD| RVM  | V/V                   | AVX2              | Add 32-bit signed integers horizontally,
| ymm1, ymm2, ymm3/m256                |      |                       |                   | pack to ymm1.                           
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PHADDW adds two adjacent 16-bit signed integers horizontally from the source
and destination operands and packs the 16-bit signed results to the destination
operand (first operand). (V)PHADDD adds two adjacent 32-bit signed integers
horizontally from the source and destination operands and packs the 32-bit signed
results to the destination operand (first operand). When the source operand
is a 128-bit memory operand, the operand must be aligned on a 16-byte boundary
or a general-protection exception (#GP) will be generated.

Note that these instructions can operate on either unsigned or signed (two's
complement notation) integers; however, it does not set bits in the EFLAGS register
to indicate overflow and/or a carry. To prevent undetected overflow conditions,
software must control the ranges of the values operated on.

Legacy SSE instructions: Both operands can be MMX registers. The second source
operand can be an MMX register or a 64-bit memory location. 128-bit Legacy SSE
version: The first source and destination operands are XMM registers. The second
source operand can be an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers.

VEX.128 encoded version: The first source and destination operands are XMM registers.
The second source operand can be an XMM register or a 128-bit memory location.
Bits (VLMAX-1:128) of the corresponding YMM register are zeroed. VEX.256 encoded
version: Horizontal addition of two adjacent data elements of the low 16-bytes
of the first and second source operands are packed into the low 16-bytes of
the destination operand. Horizontal addition of two adjacent data elements of
the high 16-bytes of the first and second source operands are packed into the
high 16bytes of the destination operand. The first source and destination operands
are YMM registers. The second source operand can be an YMM register or a 256-bit
memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

| SRC2| Y7| Y6 S7| Y5 Figure 4-6.| Y4 S3| Y3 Dest| Y2 S3 255 256-bit VPHADDD Instruction| Y1| Y0 S4| X7 S3| X6| X5| X4 S2| X3 S1| X2 0| X1| X0 S0| SRC1
|     |   |      |               |      |        | Operation                            |   |      |      |   |   |      |      |     |   |      |     
Operation:

PHADDW (with 64-bit operands)
  mm1[15-0]
  mm1[31-16] = mm1[63-48] + mm1[47-32];
  mm1[47-32] = mm2/m64[31-16] + mm2/m64[15-0];
  mm1[63-48] = mm2/m64[63-48] + mm2/m64[47-32];
PHADDW (with 128-bit operands)
  xmm1[15-0] = xmm1[31-16] + xmm1[15-0];
  xmm1[31-16] = xmm1[63-48] + xmm1[47-32];
  xmm1[47-32] = xmm1[95-80] + xmm1[79-64];
  xmm1[63-48] = xmm1[127-112] + xmm1[111-96];
  xmm1[79-64] = xmm2/m128[31-16] + xmm2/m128[15-0];
  xmm1[95-80] = xmm2/m128[63-48] + xmm2/m128[47-32];
  xmm1[111-96] = xmm2/m128[95-80] + xmm2/m128[79-64];
  xmm1[127-112] = xmm2/m128[127-112] + xmm2/m128[111-96];
VPHADDW (VEX.128 encoded version)
DEST[15:0] <- SRC1[31:16] + SRC1[15:0]
DEST[31:16] <- SRC1[63:48] + SRC1[47:32]
DEST[47:32] <- SRC1[95:80] + SRC1[79:64]
DEST[63:48] <- SRC1[127:112] + SRC1[111:96]
DEST[79:64] <- SRC2[31:16] + SRC2[15:0]
DEST[95:80] <- SRC2[63:48] + SRC2[47:32]
DEST[111:96] <- SRC2[95:80] + SRC2[79:64]
DEST[127:112] <- SRC2[127:112] + SRC2[111:96]
DEST[VLMAX-1:128] <- 0
VPHADDW (VEX.256 encoded version)
DEST[15:0] <- SRC1[31:16] + SRC1[15:0]
DEST[31:16] <- SRC1[63:48] + SRC1[47:32]
DEST[47:32] <- SRC1[95:80] + SRC1[79:64]
DEST[63:48] <- SRC1[127:112] + SRC1[111:96]
DEST[79:64] <- SRC2[31:16] + SRC2[15:0]
DEST[95:80] <- SRC2[63:48] + SRC2[47:32]
DEST[111:96] <- SRC2[95:80] + SRC2[79:64]
DEST[127:112] <- SRC2[127:112] + SRC2[111:96]
DEST[143:128] <- SRC1[159:144] + SRC1[143:128]
DEST[159:144] <- SRC1[191:176] + SRC1[175:160]
DEST[175:160] <- SRC1[223:208] + SRC1[207:192]
DEST[191:176] <- SRC1[255:240] + SRC1[239:224]
DEST[207:192] <- SRC2[127:112] + SRC2[143:128]
DEST[223:208] <- SRC2[159:144] + SRC2[175:160]
DEST[239:224] <- SRC2[191:176] + SRC2[207:192]
DEST[255:240] <- SRC2[223:208] + SRC2[239:224]
PHADDD (with 64-bit operands)
  mm1[31-0]
  mm1[63-32] = mm2/m64[63-32] + mm2/m64[31-0];
PHADDD (with 128-bit operands)
  xmm1[31-0] = xmm1[63-32] + xmm1[31-0];
  xmm1[63-32] = xmm1[127-96] + xmm1[95-64];
  xmm1[95-64] = xmm2/m128[63-32] + xmm2/m128[31-0];
  xmm1[127-96] = xmm2/m128[127-96] + xmm2/m128[95-64];
VPHADDD (VEX.128 encoded version)
DEST[31-0] <- SRC1[63-32] + SRC1[31-0]
DEST[63-32] <- SRC1[127-96] + SRC1[95-64]
DEST[95-64] <- SRC2[63-32] + SRC2[31-0]
DEST[127-96] <- SRC2[127-96] + SRC2[95-64]
DEST[VLMAX-1:128] <- 0
VPHADDD (VEX.256 encoded version)
DEST[31-0] <- SRC1[63-32] + SRC1[31-0]
DEST[63-32] <- SRC1[127-96] + SRC1[95-64]
DEST[95-64] <- SRC2[63-32] + SRC2[31-0]
DEST[127-96] <- SRC2[127-96] + SRC2[95-64]
DEST[159-128] <- SRC1[191-160] + SRC1[159-128]
DEST[191-160] <- SRC1[255-224] + SRC1[223-192]
DEST[223-192] <- SRC2[191-160] + SRC2[159-128]
DEST[255-224] <- SRC2[255-224] + SRC2[223-192]

Intel C/C++ Compiler Intrinsic Equivalents:
| PHADDW:   | __m64 _mm_hadd_pi16 (__m64 a, __m64       
|           | b)                                        
| PHADDD:   | __m64 _mm_hadd_pi32 (__m64 a, __m64       
|           | b)                                        
| (V)PHADDW:| __m128i _mm_hadd_epi16 (__m128i a, __m128i
|           | b)                                        
| (V)PHADDD:| __m128i _mm_hadd_epi32 (__m128i a, __m128i
|           | b)                                        
| VPHADDW:  | __m256i _mm256_hadd_epi16 (__m256i a,     
|           | __m256i b)                                
| VPHADDD:  | __m256i _mm256_hadd_epi32 (__m256i a,     
|           | __m256i b)                                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PHADDSW
description:
PHADDSW  -  Packed Horizontal Add and Saturate:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 38 03 /r1 PHADDSW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Add 16-bit signed integers horizontally,
|                                       |      |                       |                   | pack saturated integers to mm1.         
| 66 0F 38 03 /r PHADDSW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Add 16-bit signed integers horizontally,
|                                       |      |                       |                   | pack saturated integers to xmm1.        
| VEX.NDS.128.66.0F38.WIG 03 /r VPHADDSW| RVM  | V/V                   | AVX               | Add 16-bit signed integers horizontally,
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | pack saturated integers to xmm1.        
| VEX.NDS.256.66.0F38.WIG 03 /r VPHADDSW| RVM  | V/V                   | AVX2              | Add 16-bit signed integers horizontally,
| ymm1, ymm2, ymm3/m256                 |      |                       |                   | pack saturated integers to ymm1.        
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PHADDSW adds two adjacent signed 16-bit integers horizontally from the source
and destination operands and saturates the signed results; packs the signed,
saturated 16-bit results to the destination operand (first operand) When the
source operand is a 128-bit memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand
can be an MMX register or a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.

In 64-bit mode, use the REX prefix to access additional registers. VEX.128 encoded
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The first
source and destination operands are YMM registers. The second source operand
can be an YMM register or a 256-bit memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PHADDSW (with 64-bit operands)
  mm1[15-0]
  mm1[31-16] = SaturateToSignedWord(mm1[63-48] + mm1[47-32]);
  mm1[47-32] = SaturateToSignedWord(mm2/m64[31-16] + mm2/m64[15-0]);
  mm1[63-48] = SaturateToSignedWord(mm2/m64[63-48] + mm2/m64[47-32]);
PHADDSW (with 128-bit operands)
  xmm1[15-0]= SaturateToSignedWord(xmm1[31-16] + xmm1[15-0]);
  xmm1[31-16] = SaturateToSignedWord(xmm1[63-48] + xmm1[47-32]);
  xmm1[47-32] = SaturateToSignedWord(xmm1[95-80] + xmm1[79-64]);
  xmm1[63-48] = SaturateToSignedWord(xmm1[127-112] + xmm1[111-96]);
  xmm1[79-64] = SaturateToSignedWord(xmm2/m128[31-16] + xmm2/m128[15-0]);
  xmm1[95-80] = SaturateToSignedWord(xmm2/m128[63-48] + xmm2/m128[47-32]);
  xmm1[111-96] = SaturateToSignedWord(xmm2/m128[95-80] + xmm2/m128[79-64]);
  xmm1[127-112] = SaturateToSignedWord(xmm2/m128[127-112] + xmm2/m128[111-96]);
VPHADDSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[VLMAX-1:128] <- 0
VPHADDSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[31:16] + SRC1[15:0])
DEST[31:16] = SaturateToSignedWord(SRC1[63:48] + SRC1[47:32])
DEST[47:32] = SaturateToSignedWord(SRC1[95:80] + SRC1[79:64])
DEST[63:48] = SaturateToSignedWord(SRC1[127:112] + SRC1[111:96])
DEST[79:64] = SaturateToSignedWord(SRC2[31:16] + SRC2[15:0])
DEST[95:80] = SaturateToSignedWord(SRC2[63:48] + SRC2[47:32])
DEST[111:96] = SaturateToSignedWord(SRC2[95:80] + SRC2[79:64])
DEST[127:112] = SaturateToSignedWord(SRC2[127:112] + SRC2[111:96])
DEST[143:128]= SaturateToSignedWord(SRC1[159:144] + SRC1[143:128])
DEST[159:144] = SaturateToSignedWord(SRC1[191:176] + SRC1[175:160])
DEST[175:160] = SaturateToSignedWord( SRC1[223:208] + SRC1[207:192])
DEST[191:176] = SaturateToSignedWord(SRC1[255:240] + SRC1[239:224])
DEST[207:192] = SaturateToSignedWord(SRC2[127:112] + SRC2[143:128])
DEST[223:208] = SaturateToSignedWord(SRC2[159:144] + SRC2[175:160])
DEST[239:224] = SaturateToSignedWord(SRC2[191-160] + SRC2[159-128])
DEST[255:240] = SaturateToSignedWord(SRC2[255:240] + SRC2[239:224])

Intel C/C++ Compiler Intrinsic Equivalent:
| PHADDSW:   | __m64 _mm_hadds_pi16 (__m64 a, __m64
|            | b)                                  
| (V)PHADDSW:| __m128i _mm_hadds_epi16 (__m128i a, 
|            | __m128i b)                          
| VPHADDSW:  | __m256i _mm256_hadds_epi16 (__m256i 
|            | a, __m256i b)                       

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PHMINPOSUW
description:
PHMINPOSUW  -  Packed Horizontal Word Minimum:
| Opcode/Instruction                       | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 66 0F 38 41 /r PHMINPOSUW xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Find the minimum unsigned word in xmm2/m128
|                                          |      |                       |                   | and place its value in the low word        
|                                          |      |                       |                   | of xmm1 and its index in the secondlowest  
|                                          |      |                       |                   | word of xmm1.                              
| VEX.128.66.0F38.WIG 41 /r VPHMINPOSUW    | RM   | V/V                   | AVX               | Find the minimum unsigned word in xmm2/m128
| xmm1, xmm2/m128                          |      |                       |                   | and place its value in the low word        
|                                          |      |                       |                   | of xmm1 and its index in the secondlowest  
|                                          |      |                       |                   | word of xmm1.                              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Determine the minimum unsigned word value in the source operand (second operand)
and place the unsigned

| word in the low word (bits 0-15) of        | The word index of the minimum value        
| the destination operand (first operand).   | The remaining upper bits of the destination
| is stored in bits 16-18 of the destination | are set to zero.                           
| operand. 128-bit Legacy SSE version:       |                                            
| Bits (VLMAX-1:128) of the corresponding    |                                            
| YMM destination register remain unchanged. |                                            
| VEX.128 encoded version: Bits (VLMAX-1:128)|                                            
| of the destination YMM register are        |                                            
| zeroed. VEX.vvvv is reserved and must      |                                            
| be 1111b, VEX.L must be 0, otherwise       |                                            
| the instruction will #UD.                  |                                            
Operation:

PHMINPOSUW (128-bit Legacy SSE version)
INDEX <- 0;
MIN <- SRC[15:0]
IF (SRC[31:16] < MIN)
  THEN INDEX <- 1;
IF (SRC[47:32] < MIN)
  THEN INDEX <- 2;
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN)
  THEN INDEX <- 7;
DEST[15:0] <- MIN;
DEST[18:16] <- INDEX;
DEST[127:19] <- 0000000000000000000000000000H;
VPHMINPOSUW (VEX.128 encoded version)
INDEX <- 0
MIN <- SRC[15:0]
IF (SRC[31:16] < MIN) THEN INDEX <- 1; MIN <- SRC[31:16]
IF (SRC[47:32] < MIN) THEN INDEX <- 2; MIN <- SRC[47:32]
* Repeat operation for words 3 through 6
IF (SRC[127:112] < MIN) THEN INDEX <- 7; MIN <- SRC[127:112]
DEST[15:0] <- MIN
DEST[18:16] <- INDEX
DEST[127:19] <- 0000000000000000000000000000H
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| PHMINPOSUW:| __m128i _mm_minpos_epu16( __m128i packed_words);

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PHSUBW
description:
PHSUBW/PHSUBD  -  Packed Horizontal Subtract:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                  
| 0F 38 05 /r1 PHSUBW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Subtract 16-bit signed integers horizontally,
|                                      |      |                       |                   | pack to mm1.                                 
| 66 0F 38 05 /r PHSUBW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Subtract 16-bit signed integers horizontally,
|                                      |      |                       |                   | pack to xmm1.                                
| 0F 38 06 /r PHSUBD mm1, mm2/m64      | RM   | V/V                   | SSSE3             | Subtract 32-bit signed integers horizontally,
|                                      |      |                       |                   | pack to mm1.                                 
| 66 0F 38 06 /r PHSUBD xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Subtract 32-bit signed integers horizontally,
|                                      |      |                       |                   | pack to xmm1.                                
| VEX.NDS.128.66.0F38.WIG 05 /r VPHSUBW| RVM  | V/V                   | AVX               | Subtract 16-bit signed integers horizontally,
| xmm1, xmm2, xmm3/m128                |      |                       |                   | pack to xmm1.                                
| VEX.NDS.128.66.0F38.WIG 06 /r VPHSUBD| RVM  | V/V                   | AVX               | Subtract 32-bit signed integers horizontally,
| xmm1, xmm2, xmm3/m128                |      |                       |                   | pack to xmm1.                                
| VEX.NDS.256.66.0F38.WIG 05 /r VPHSUBW| RVM  | V/V                   | AVX2              | Subtract 16-bit signed integers horizontally,
| ymm1, ymm2, ymm3/m256                |      |                       |                   | pack to ymm1.                                
| VEX.NDS.256.66.0F38.WIG 06 /r VPHSUBD| RVM  | V/V                   | AVX2              | Subtract 32-bit signed integers horizontally,
| ymm1, ymm2, ymm3/m256                |      |                       |                   | pack to ymm1.                                
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (r, w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PHSUBW performs horizontal subtraction on each adjacent pair of 16-bit signed
integers by subtracting the most significant word from the least significant
word of each pair in the source and destination operands, and packs the signed
16-bit results to the destination operand (first operand). (V)PHSUBD performs
horizontal subtraction on each adjacent pair of 32-bit signed integers by subtracting
the most significant doubleword from the least significant doubleword of each
pair, and packs the signed 32-bit result to the destination operand. When the
source operand is a 128-bit memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.

Legacy SSE version: Both operands can be MMX registers. The second source operand
can be an MMX register or a 64-bit memory location. 128-bit Legacy SSE version:
The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged.

In 64-bit mode, use the REX prefix to access additional registers. VEX.128 encoded
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the destination YMM register are zeroed.

VEX.256 encoded version: The first source and destination operands are YMM registers.
The second source operand can be an YMM register or a 256-bit memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PHSUBW (with 64-bit operands)
  mm1[15-0] = mm1[15-0] - mm1[31-16];
  mm1[31-16] = mm1[47-32] - mm1[63-48];
  mm1[47-32] = mm2/m64[15-0] - mm2/m64[31-16];
  mm1[63-48] = mm2/m64[47-32] - mm2/m64[63-48];
PHSUBW (with 128-bit operands)
  xmm1[15-0] = xmm1[15-0] - xmm1[31-16];
  xmm1[31-16] = xmm1[47-32] - xmm1[63-48];
  xmm1[47-32] = xmm1[79-64] - xmm1[95-80];
  xmm1[63-48] = xmm1[111-96] - xmm1[127-112];
  xmm1[79-64] = xmm2/m128[15-0] - xmm2/m128[31-16];
  xmm1[95-80] = xmm2/m128[47-32] - xmm2/m128[63-48];
  xmm1[111-96] = xmm2/m128[79-64] - xmm2/m128[95-80];
  xmm1[127-112] = xmm2/m128[111-96] - xmm2/m128[127-112];
VPHSUBW (VEX.128 encoded version)
DEST[15:0] <- SRC1[15:0] - SRC1[31:16]
DEST[31:16] <- SRC1[47:32] - SRC1[63:48]
DEST[47:32] <- SRC1[79:64] - SRC1[95:80]
DEST[63:48] <- SRC1[111:96] - SRC1[127:112]
DEST[79:64] <- SRC2[15:0] - SRC2[31:16]
DEST[95:80] <- SRC2[47:32] - SRC2[63:48]
DEST[111:96] <- SRC2[79:64] - SRC2[95:80]
DEST[127:112] <- SRC2[111:96] - SRC2[127:112]
DEST[VLMAX-1:128] <- 0
VPHSUBW (VEX.256 encoded version)
DEST[15:0] <- SRC1[15:0] - SRC1[31:16]
DEST[31:16] <- SRC1[47:32] - SRC1[63:48]
DEST[47:32] <- SRC1[79:64] - SRC1[95:80]
DEST[63:48] <- SRC1[111:96] - SRC1[127:112]
DEST[79:64] <- SRC2[15:0] - SRC2[31:16]
DEST[95:80] <- SRC2[47:32] - SRC2[63:48]
DEST[111:96] <- SRC2[79:64] - SRC2[95:80]
DEST[127:112] <- SRC2[111:96] - SRC2[127:112]
DEST[143:128] <- SRC1[143:128] - SRC1[159:144]
DEST[159:144] <- SRC1[175:160] - SRC1[191:176]
DEST[175:160] <- SRC1[207:192] - SRC1[223:208]
DEST[191:176] <- SRC1[239:224] - SRC1[255:240]
DEST[207:192] <- SRC2[143:128] - SRC2[159:144]
DEST[223:208] <- SRC2[175:160] - SRC2[191:176]
DEST[239:224] <- SRC2[207:192] - SRC2[223:208]
DEST[255:240] <- SRC2[239:224] - SRC2[255:240]
PHSUBD (with 64-bit operands)
  mm1[31-0] = mm1[31-0] - mm1[63-32];
  mm1[63-32] = mm2/m64[31-0] - mm2/m64[63-32];
PHSUBD (with 128-bit operands)
  xmm1[31-0] = xmm1[31-0] - xmm1[63-32];
  xmm1[63-32] = xmm1[95-64] - xmm1[127-96];
  xmm1[95-64] = xmm2/m128[31-0] - xmm2/m128[63-32];
  xmm1[127-96] = xmm2/m128[95-64] - xmm2/m128[127-96];
VPHSUBD (VEX.128 encoded version)
DEST[31-0] <- SRC1[31-0] - SRC1[63-32]
DEST[63-32] <- SRC1[95-64] - SRC1[127-96]
DEST[95-64] <- SRC2[31-0] - SRC2[63-32]
DEST[127-96] <- SRC2[95-64] - SRC2[127-96]
DEST[VLMAX-1:128] <- 0
VPHSUBD (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC1[63:32]
DEST[63:32] <- SRC1[95:64] - SRC1[127:96]
DEST[95:64] <- SRC2[31:0] - SRC2[63:32]
DEST[127:96] <- SRC2[95:64] - SRC2[127:96]
DEST[159:128] <- SRC1[159:128] - SRC1[191:160]
DEST[191:160] <- SRC1[223:192] - SRC1[255:224]
DEST[223:192] <- SRC2[159:128] - SRC2[191:160]
DEST[255:224] <- SRC2[223:192] - SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalents:
| PHSUBW:   | __m64 _mm_hsub_pi16 (__m64 a, __m64       
|           | b)                                        
| PHSUBD:   | __m64 _mm_hsub_pi32 (__m64 a, __m64       
|           | b)                                        
| (V)PHSUBW:| __m128i _mm_hsub_epi16 (__m128i a, __m128i
|           | b)                                        
| (V)PHSUBD:| __m128i _mm_hsub_epi32 (__m128i a, __m128i
|           | b)                                        
| VPHSUBW:  | __m256i _mm256_hsub_epi16 (__m256i a,     
|           | __m256i b)                                
| VPHSUBD:  | __m256i _mm256_hsub_epi32 (__m256i a,     
|           | __m256i b)                                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PHSUBSW
description:
PHSUBSW  -  Packed Horizontal Subtract and Saturate:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 0F 38 07 /r1 PHSUBSW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Subtract 16-bit signed integer horizontally,
|                                       |      |                       |                   | pack saturated integers to mm1.             
| 66 0F 38 07 /r PHSUBSW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Subtract 16-bit signed integer horizontally,
|                                       |      |                       |                   | pack saturated integers to xmm1.            
| VEX.NDS.128.66.0F38.WIG 07 /r VPHSUBSW| RVM  | V/V                   | AVX               | Subtract 16-bit signed integer horizontally,
| xmm1, xmm2, xmm3/m128                 |      |                       |                   | pack saturated integers to xmm1.            
| VEX.NDS.256.66.0F38.WIG 07 /r VPHSUBSW| RVM  | V/V                   | AVX2              | Subtract 16-bit signed integer horizontally,
| ymm1, ymm2, ymm3/m256                 |      |                       |                   | pack saturated integers to ymm1.            
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (r, w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PHSUBSW performs horizontal subtraction on each adjacent pair of 16-bit signed
integers by subtracting the most significant word from the least significant
word of each pair in the source and destination operands. The signed, saturated
16-bit results are packed to the destination operand (first operand). When the
source operand is a 128-bit memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated.
Legacy SSE version: Both operands can be MMX registers. The second source operand
can be an MMX register or a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged.

In 64-bit mode, use the REX prefix to access additional registers. VEX.128 encoded
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The first
source and destination operands are YMM registers. The second source operand
can be an YMM register or a 256-bit memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PHSUBSW (with 64-bit operands)
  mm1[15-0] = SaturateToSignedWord(mm1[15-0] - mm1[31-16]);
  mm1[31-16] = SaturateToSignedWord(mm1[47-32] - mm1[63-48]);
  mm1[47-32] = SaturateToSignedWord(mm2/m64[15-0] - mm2/m64[31-16]);
  mm1[63-48] = SaturateToSignedWord(mm2/m64[47-32] - mm2/m64[63-48]);
PHSUBSW (with 128-bit operands)
  xmm1[15-0] = SaturateToSignedWord(xmm1[15-0] - xmm1[31-16]);
  xmm1[31-16] = SaturateToSignedWord(xmm1[47-32] - xmm1[63-48]);
  xmm1[47-32] = SaturateToSignedWord(xmm1[79-64] - xmm1[95-80]);
  xmm1[63-48] = SaturateToSignedWord(xmm1[111-96] - xmm1[127-112]);
  xmm1[79-64] = SaturateToSignedWord(xmm2/m128[15-0] - xmm2/m128[31-16]);
  xmm1[95-80] =SaturateToSignedWord(xmm2/m128[47-32] - xmm2/m128[63-48]);
  xmm1[111-96] =SaturateToSignedWord(xmm2/m128[79-64] - xmm2/m128[95-80]);
  xmm1[127-112]= SaturateToSignedWord(xmm2/m128[111-96] - xmm2/m128[127-112]);
VPHSUBSW (VEX.128 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[VLMAX-1:128] <- 0
VPHSUBSW (VEX.256 encoded version)
DEST[15:0]= SaturateToSignedWord(SRC1[15:0] - SRC1[31:16])
DEST[31:16] = SaturateToSignedWord(SRC1[47:32] - SRC1[63:48])
DEST[47:32] = SaturateToSignedWord(SRC1[79:64] - SRC1[95:80])
DEST[63:48] = SaturateToSignedWord(SRC1[111:96] - SRC1[127:112])
DEST[79:64] = SaturateToSignedWord(SRC2[15:0] - SRC2[31:16])
DEST[95:80] = SaturateToSignedWord(SRC2[47:32] - SRC2[63:48])
DEST[111:96] = SaturateToSignedWord(SRC2[79:64] - SRC2[95:80])
DEST[127:112] = SaturateToSignedWord(SRC2[111:96] - SRC2[127:112])
DEST[143:128]= SaturateToSignedWord(SRC1[143:128] - SRC1[159:144])
DEST[159:144] = SaturateToSignedWord(SRC1[175:160] - SRC1[191:176])
DEST[175:160] = SaturateToSignedWord(SRC1[207:192] - SRC1[223:208])
DEST[191:176] = SaturateToSignedWord(SRC1[239:224] - SRC1[255:240])
DEST[207:192] = SaturateToSignedWord(SRC2[143:128] - SRC2[159:144])
DEST[223:208] = SaturateToSignedWord(SRC2[175:160] - SRC2[191:176])
DEST[239:224] = SaturateToSignedWord(SRC2[207:192] - SRC2[223:208])
DEST[255:240] = SaturateToSignedWord(SRC2[239:224] - SRC2[255:240])

Intel C/C++ Compiler Intrinsic Equivalent:
| PHSUBSW:   | __m64 _mm_hsubs_pi16 (__m64 a, __m64
|            | b)                                  
| (V)PHSUBSW:| __m128i _mm_hsubs_epi16 (__m128i a, 
|            | __m128i b)                          
| VPHSUBSW:  | __m256i _mm256_hsubs_epi16 (__m256i 
|            | a, __m256i b)                       

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PINSRB
description:
PINSRB/PINSRD/PINSRQ  -  Insert Byte/Dword/Qword:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 66 0F 3A 20 /r ib PINSRB xmm1, r32/m8, | RMI  | V/V                   | SSE4_1            | Insert a byte integer value from r32/m8  
| imm8                                   |      |                       |                   | into xmm1 at the destination element     
|                                        |      |                       |                   | in xmm1 specified by imm8.               
| 66 0F 3A 22 /r ib PINSRD xmm1, r/m32,  | RMI  | V/V                   | SSE4_1            | Insert a dword integer value from r/m32  
| imm8                                   |      |                       |                   | into the xmm1 at the destination element 
|                                        |      |                       |                   | specified by imm8.                       
| 66 REX.W 0F 3A 22 /r ib PINSRQ xmm1,   | RMI  | V/N. E.               | SSE4_1            | Insert a qword integer value from r/m64  
| r/m64, imm8                            |      |                       |                   | into the xmm1 at the destination element 
|                                        |      |                       |                   | specified by imm8.                       
| VEX.NDS.128.66.0F3A.W0 20 /r ib VPINSRB| RVMI | V1/V                  | AVX               | Merge a byte integer value from r32/m8   
| xmm1, xmm2, r32/m8, imm8               |      |                       |                   | and rest from xmm2 into xmm1 at the      
|                                        |      |                       |                   | byte offset in imm8.                     
| VEX.NDS.128.66.0F3A.W0 22 /r ib VPINSRD| RVMI | V/V                   | AVX               | Insert a dword integer value from r32/m32
| xmm1, xmm2, r/m32, imm8                |      |                       |                   | and rest from xmm2 into xmm1 at the      
|                                        |      |                       |                   | dword offset in imm8.                    
| VEX.NDS.128.66.0F3A.W1 22 /r ib VPINSRQ| RVMI | V/I                   | AVX               | Insert a qword integer value from r64/m64
| xmm1, xmm2, r/m64, imm8                |      |                       |                   | and rest from xmm2 into xmm1 at the      
|                                        |      |                       |                   | qword offset in imm8.                    
Notes: 1. In 64-bit mode, VEX.W1 is ignored for VPINSRB (similar to legacy REX.W=1
prefix with PINSRB).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Copies a byte/dword/qword from the source operand (second operand) and inserts
it in the destination operand (first operand) at the location specified with
the count operand (third operand). (The other elements in the destination register
are left untouched.) The source operand can be a general-purpose register or
a memory location. (When the source operand is a general-purpose register, PINSRB
copies the low byte of the register.) The destination operand is an XMM register.
The count operand is an 8-bit immediate. When specifying a qword[dword, byte]location
in an an XMM register, the [2, 4] least-significant bit(s) of the count operand
specify the location. In 64-bit mode, using a REX prefix in the form of REX.R
permits this instruction to access additional registers (XMM8-XMM15, R8-15).
Use of REX.W permits the use of 64 bit general purpose registers. 128-bit Legacy
SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.L must be 0, otherwise the instruction will #UD.
Attempt to execute VPINSRQ in non-64-bit mode will cause #UD.

Operation:

CASE OF
  PINSRB: SEL <- COUNT[3:0];
       MASK <- (0FFH << (SEL * 8));
       TEMP <- (((SRC[7:0] << (SEL *8)) AND MASK);
  PINSRD: SEL <- COUNT[1:0];
       MASK <- (0FFFFFFFFH << (SEL * 32));
       TEMP <- (((SRC << (SEL *32)) AND MASK)
  PINSRQ: SEL <- COUNT[0]
       MASK <- (0FFFFFFFFFFFFFFFFH << (SEL * 64));
       TEMP <- (((SRC << (SEL *32)) AND MASK)
ESAC;
     DEST <- ((DEST AND NOT MASK) OR TEMP);
VPINSRB (VEX.128 encoded version)
SEL <- imm8[3:0]
DEST[127:0] <- write_b_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0
VPINSRD (VEX.128 encoded version)
SEL <- imm8[1:0]
DEST[127:0] <- write_d_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0
VPINSRQ (VEX.128 encoded version)
SEL <- imm8[0]
DEST[127:0] <- write_q_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| PINSRB:| __m128i _mm_insert_epi8 (__m128i s1, 
|        | int s2, const int ndx);              
| PINSRD:| __m128i _mm_insert_epi32 (__m128i s2,
|        | int s, const int ndx);               
| PINSRQ:| __m128i _mm_insert_epi64(__m128i s2, 
|        | __int64 s, const int ndx);           

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VPINSRQ in non-64-bit
|    | mode with VEX.W=1.                    


platform: x86
mnem: PINSRW
description:
PINSRW - Insert Word:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 0F C4 /r ib1 PINSRW mm, r32/m16, imm8| RMI  | V/V                   | SSE               | Insert the low word from r32 or from      
|                                      |      |                       |                   | m16 into mm at the word position specified
|                                      |      |                       |                   | by imm8.                                  
| 66 0F C4 /r ib PINSRW xmm, r32/m16,  | RMI  | V/V                   | SSE2              | Move the low word of r32 or from m16      
| imm8                                 |      |                       |                   | into xmm at the word position specified   
|                                      |      |                       |                   | by imm8.                                  
| VEX.NDS.128.66.0F.W0 C4 /r ib VPINSRW| RVMI | V2/V                  | AVX               | Insert a word integer value from r32/m16  
| xmm1, xmm2, r32/m16, imm8            |      |                       |                   | and rest from xmm2 into xmm1 at the       
|                                      |      |                       |                   | word offset in imm8.                      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A. 2. In 64-bit mode, VEX.W1 is ignored for VPINSRW (similar
to legacy REX.W=1 prefix in PINSRW).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Copies a word from the source operand (second operand) and inserts it in the
destination operand (first operand) at the location specified with the count
operand (third operand). (The other words in the destination register are left
untouched.) The source operand can be a general-purpose register or a 16-bit
memory location. (When the source operand is a general-purpose register, the
low word of the register is copied.) The destination operand can be an MMX technology
register or an XMM register. The count operand is an 8-bit immediate. When specifying
a word location in an MMX technology register, the 2 least-significant bits
of the count operand specify the location; for an XMM register, the 3 least-significant
bits specify the location.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15, R8-15). 128-bit Legacy SSE version:
Bits (VLMAX-1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register
are zeroed. VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PINSRW (with 64-bit source operand)
  SEL <- COUNT AND 3H;
     CASE (Determine word position) OF
       SEL <- 0:
       SEL <- 1:
       SEL <- 2:
       SEL <- 3:
  DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);
PINSRW (with 128-bit source operand)
  SEL <- COUNT AND 7H;
     CASE (Determine word position) OF
       SEL <- 0:
       SEL <- 1:
       SEL <- 2:
       SEL <- 3:
       SEL <- 4:
       SEL <- 5:
       SEL <- 6:
       SEL <- 7:
  DEST <- (DEST AND NOT MASK) OR (((SRC << (SEL * 16)) AND MASK);
VPINSRW (VEX.128 encoded version)
SEL <- imm8[2:0]
DEST[127:0] <- write_w_element(SEL, SRC2, SRC1)
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| PINSRW:| __m64 _mm_insert_pi16 (__m64 a, int  
|        | d, int n)                            
| PINSRW:| __m128i _mm_insert_epi16 ( __m128i a,
|        | int b, int imm)                      

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VPINSRW in non-64-bit
|    | mode with VEX.W=1.                    


platform: x86
mnem: PMADDUBSW
description:
PMADDUBSW  -  Multiply and Add Packed Signed and Unsigned Bytes:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                         
| 0F 38 04 /r1 PMADDUBSW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Multiply signed and unsigned bytes, 
|                                         |      |                       |                   | add horizontal pair of signed words,
|                                         |      |                       |                   | pack saturated signed-words to mm1. 
| 66 0F 38 04 /r PMADDUBSW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Multiply signed and unsigned bytes, 
|                                         |      |                       |                   | add horizontal pair of signed words,
|                                         |      |                       |                   | pack saturated signed-words to xmm1.
| VEX.NDS.128.66.0F38.WIG 04 /r VPMADDUBSW| RVM  | V/V                   | AVX               | Multiply signed and unsigned bytes, 
| xmm1, xmm2, xmm3/m128                   |      |                       |                   | add horizontal pair of signed words,
|                                         |      |                       |                   | pack saturated signed-words to xmm1.
| VEX.NDS.256.66.0F38.WIG 04 /r VPMADDUBSW| RVM  | V/V                   | AVX2              | Multiply signed and unsigned bytes, 
| ymm1, ymm2, ymm3/m256                   |      |                       |                   | add horizontal pair of signed words,
|                                         |      |                       |                   | pack saturated signed-words to ymm1.
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PMADDUBSW multiplies vertically each unsigned byte of the destination operand
(first operand) with the corresponding signed byte of the source operand (second
operand), producing intermediate signed 16-bit integers. Each adjacent pair
of signed words is added and the saturated result is packed to the destination
operand. For example, the lowest-order bytes (bits 7-0) in the source and destination
operands are multiplied and the intermediate signed word result is added with
the corresponding intermediate result from the 2nd lowest-order bytes (bits
15-8) of the operands; the sign-saturated result is stored in the lowest word
of the destination register (15-0). The same operation is performed on the other
pairs of adjacent bytes. Both operands can be MMX register or XMM registers.
When the source operand is a 128-bit memory operand, the operand must be aligned
on a 16-byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers. 128-bit Legacy
SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The first source and destination
operands are YMM registers. The second source operand can be an YMM register
or a 256-bit memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMADDUBSW (with 64 bit operands)
  DEST[15-0] = SaturateToSignedWord(SRC[15-8]*DEST[15-8]+SRC[7-0]*DEST[7-0]);
  DEST[31-16] = SaturateToSignedWord(SRC[31-24]*DEST[31-24]+SRC[23-16]*DEST[23-16]);
  DEST[47-32] = SaturateToSignedWord(SRC[47-40]*DEST[47-40]+SRC[39-32]*DEST[39-32]);
  DEST[63-48] = SaturateToSignedWord(SRC[63-56]*DEST[63-56]+SRC[55-48]*DEST[55-48]);
PMADDUBSW (with 128 bit operands)
  DEST[15-0] = SaturateToSignedWord(SRC[15-8]* DEST[15-8]+SRC[7-0]*DEST[7-0]);
  // Repeat operation for 2nd through 7th word
  SRC1/DEST[127-112] = SaturateToSignedWord(SRC[127-120]*DEST[127-120]+ SRC[119-112]* DEST[119-112]);
VPMADDUBSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 7th word
DEST[127:112] <- SaturateToSignedWord(SRC2[127:120]*SRC1[127:120]+ SRC2[119:112]* SRC1[119:112])
DEST[VLMAX-1:128] <- 0
VPMADDUBSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToSignedWord(SRC2[15:8]* SRC1[15:8]+SRC2[7:0]*SRC1[7:0])
// Repeat operation for 2nd through 15th word
DEST[255:240] <- SaturateToSignedWord(SRC2[255:248]*SRC1[255:248]+ SRC2[247:240]* SRC1[247:240])

Intel C/C++ Compiler Intrinsic Equivalents:
| PMADDUBSW:   | __m64 _mm_maddubs_pi16 (__m64 a, __m64
|              | b)                                    
| (V)PMADDUBSW:| __m128i _mm_maddubs_epi16 (__m128i a, 
|              | __m128i b)                            
| VPMADDUBSW:  | __m256i _mm256_maddubs_epi16 (__m256i 
|              | a, __m256i b)                         

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMADDWD
description:
PMADDWD - Multiply and Add Packed Integers:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F F5 /r1 PMADDWD mm, mm/m64        | RM   | V/V                   | MMX               | Multiply the packed words in mm by the     
|                                     |      |                       |                   | packed words in mm/m64, add adjacent       
|                                     |      |                       |                   | doubleword results, and store in mm.       
| 66 0F F5 /r PMADDWD xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Multiply the packed word integers in       
|                                     |      |                       |                   | xmm1 by the packed word integers in        
|                                     |      |                       |                   | xmm2/m128, add adjacent doubleword results,
|                                     |      |                       |                   | and store in xmm1.                         
| VEX.NDS.128.66.0F.WIG F5 /r VPMADDWD| RVM  | V/V                   | AVX               | Multiply the packed word integers in       
| xmm1, xmm2, xmm3/m128               |      |                       |                   | xmm2 by the packed word integers in        
|                                     |      |                       |                   | xmm3/m128, add adjacent doubleword results,
|                                     |      |                       |                   | and store in xmm1.                         
| VEX.NDS.256.66.0F.WIG F5 /r VPMADDWD| RVM  | V/V                   | AVX2              | Multiply the packed word integers in       
| ymm1, ymm2, ymm3/m256               |      |                       |                   | ymm2 by the packed word integers in        
|                                     |      |                       |                   | ymm3/m256, add adjacent doubleword results,
|                                     |      |                       |                   | and store in ymm1.                         
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Multiplies the individual signed words of the destination operand (first operand)
by the corresponding signed words of the source operand (second operand), producing
temporary signed, doubleword results. The adjacent doubleword results are then
summed and stored in the destination operand. For example, the corresponding
low-order words (15-0) and (31-16) in the source and destination operands are
multiplied by one another and the doubleword results are added together and
stored in the low doubleword of the destination register (31-0). The same operation
is performed on the other pairs of adjacent words. (Figure 4-7 shows this operation
when using 64-bit operands).

The (V)PMADDWD instruction wraps around only in one situation: when the 2 pairs
of words being operated on in a group are all 8000H. In this case, the result
wraps around to 80000000H.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The first source
and destination operands are MMX registers. The second source operand is an
MMX register or a 64-bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

| SRC | X3        | X2| X1        | X0        
| DEST| Y3 X2 * Y2| Y2| Y1 X1 * Y1| Y0 X0 * Y0
DEST

| (X3*Y3) + (X2*Y2)                   | (X1*Y1) + (X0*Y0)
| PMADDWD Execution Model Using 64-bit| Figure 4-7.      
| Operands                            |                  
Operation:

PMADDWD (with 64-bit operands)
  DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);
  DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);
PMADDWD (with 128-bit operands)
  DEST[31:0] <- (DEST[15:0] * SRC[15:0]) + (DEST[31:16] * SRC[31:16]);
  DEST[63:32] <- (DEST[47:32] * SRC[47:32]) + (DEST[63:48] * SRC[63:48]);
  DEST[95:64] <- (DEST[79:64] * SRC[79:64]) + (DEST[95:80] * SRC[95:80]);
  DEST[127:96] <- (DEST[111:96] * SRC[111:96]) + (DEST[127:112] * SRC[127:112]);
VPMADDWD (VEX.128 encoded version)
DEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])
DEST[VLMAX-1:128] <- 0
VPMADDWD (VEX.256 encoded version)
DEST[31:0] <- (SRC1[15:0] * SRC2[15:0]) + (SRC1[31:16] * SRC2[31:16])
DEST[63:32] <- (SRC1[47:32] * SRC2[47:32]) + (SRC1[63:48] * SRC2[63:48])
DEST[95:64] <- (SRC1[79:64] * SRC2[79:64]) + (SRC1[95:80] * SRC2[95:80])
DEST[127:96] <- (SRC1[111:96] * SRC2[111:96]) + (SRC1[127:112] * SRC2[127:112])
DEST[159:128] <- (SRC1[143:128] * SRC2[143:128]) + (SRC1[159:144] * SRC2[159:144])
DEST[191:160] <- (SRC1[175:160] * SRC2[175:160]) + (SRC1[191:176] * SRC2[191:176])
DEST[223:192] <- (SRC1[207:192] * SRC2[207:192]) + (SRC1[223:208] * SRC2[223:208])
DEST[255:224] <- (SRC1[239:224] * SRC2[239:224]) + (SRC1[255:240] * SRC2[255:240])

Intel C/C++ Compiler Intrinsic Equivalent:
| PMADDWD:   | __m64 _mm_madd_pi16(__m64 m1, __m64
|            | m2)                                
| (V)PMADDWD:| __m128i _mm_madd_epi16 ( __m128i a,
|            | __m128i b)                         
| VPMADDWD:  | __m256i _mm256_madd_epi16 ( __m256i
|            | a, __m256i b)                      

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMAXSB
description:
PMAXSB  -  Maximum of Packed Signed Byte Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 3C /r PMAXSB xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed signed byte integers   
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 3C /r VPMAXSB| RVM  | V/V                   | AVX               | Compare packed signed byte integers   
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 3C /r VPMAXSB| RVM  | V/V                   | AVX2              | Compare packed signed byte integers   
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m128 and store packed
|                                      |      |                       |                   | maximum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed signed byte integers in the destination operand (first operand)
and the source operand (second operand), and returns the maximum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[7:0] > SRC[7:0])
  THEN DEST[7:0] <- DEST[7:0];
  ELSE DEST[7:0] <- SRC[7:0]; FI;
IF (DEST[15:8] > SRC[15:8])
  THEN DEST[15:8] <- DEST[15:8];
  ELSE DEST[15:8] <- SRC[15:8]; FI;
IF (DEST[23:16] > SRC[23:16])
  THEN DEST[23:16] <- DEST[23:16];
  ELSE DEST[23:16] <- SRC[23:16]; FI;
IF (DEST[31:24] > SRC[31:24])
  THEN DEST[31:24] <- DEST[31:24];
  ELSE DEST[31:24] <- SRC[31:24]; FI;
IF (DEST[39:32] > SRC[39:32])
  THEN DEST[39:32] <- DEST[39:32];
  ELSE DEST[39:32] <- SRC[39:32]; FI;
IF (DEST[47:40] > SRC[47:40])
  THEN DEST[47:40] <- DEST[47:40];
  ELSE DEST[47:40] <- SRC[47:40]; FI;
IF (DEST[55:48] > SRC[55:48])
  THEN DEST[55:48] <- DEST[55:48];
  ELSE DEST[55:48] <- SRC[55:48]; FI;
IF (DEST[63:56] > SRC[63:56])
  THEN DEST[63:56] <- DEST[63:56];
  ELSE DEST[63:56] <- SRC[63:56]; FI;
IF (DEST[71:64] > SRC[71:64])
  THEN DEST[71:64] <- DEST[71:64];
  ELSE DEST[71:64] <- SRC[71:64]; FI;
IF (DEST[79:72] > SRC[79:72])
  THEN DEST[79:72] <- DEST[79:72];
  ELSE DEST[79:72] <- SRC[79:72]; FI;
IF (DEST[87:80] > SRC[87:80])
  THEN DEST[87:80] <- DEST[87:80];
  ELSE DEST[87:80] <- SRC[87:80]; FI;
IF (DEST[95:88] > SRC[95:88])
  THEN DEST[95:88] <- DEST[95:88];
  ELSE DEST[95:88] <- SRC[95:88]; FI;
IF (DEST[103:96] > SRC[103:96])
  THEN DEST[103:96] <- DEST[103:96];
  ELSE DEST[103:96] <- SRC[103:96]; FI;
IF (DEST[111:104] > SRC[111:104])
  THEN DEST[111:104] <- DEST[111:104];
  ELSE DEST[111:104] <- SRC[111:104]; FI;
IF (DEST[119:112] > SRC[119:112])
  THEN DEST[119:112] <- DEST[119:112];
  ELSE DEST[119:112] <- SRC[119:112]; FI;
IF (DEST[127:120] > SRC[127:120])
  THEN DEST[127:120] <- DEST[127:120];
  ELSE DEST[127:120] <- SRC[127:120]; FI;
VPMAXSB (VEX.128 encoded version)
  IF SRC1[7:0] >SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[7:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF SRC1[127:120] >SRC2[127:120] THEN
     DEST[127:120] <- SRC1[127:120];
  ELSE
     DEST[127:120] <- SRC2[127:120]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXSB (VEX.256 encoded version)
  IF SRC1[7:0] >SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[15:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
  IF SRC1[255:248] >SRC2[255:248] THEN
     DEST[255:248] <- SRC1[255:248];
  ELSE
     DEST[255:248] <- SRC2[255:248]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMAXSB:| __m128i _mm_max_epi8 ( __m128i a, __m128i
|           | b);                                      
| VPMAXSB:  | __m256i _mm256_max_epi8 ( __m256i a,     
|           | __m256i b);                              

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMAXSD
description:
PMAXSD  -  Maximum of Packed Signed Dword Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 3D /r PMAXSD xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed signed dword integers  
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 3D /r VPMAXSD| RVM  | V/V                   | AVX               | Compare packed signed dword integers  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 3D /r VPMAXSD| RVM  | V/V                   | AVX2              | Compare packed signed dword integers  
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m128 and store packed
|                                      |      |                       |                   | maximum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed signed dword integers in the destination operand (first operand)
and the source operand (second operand), and returns the maximum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[31:0] > SRC[31:0])
  THEN DEST[31:0] <- DEST[31:0];
  ELSE DEST[31:0] <- SRC[31:0]; FI;
IF (DEST[63:32] > SRC[63:32])
  THEN DEST[63:32] <- DEST[63:32];
  ELSE DEST[63:32] <- SRC[63:32]; FI;
IF (DEST[95:64] > SRC[95:64])
  THEN DEST[95:64] <- DEST[95:64];
  ELSE DEST[95:64] <- SRC[95:64]; FI;
IF (DEST[127:96] > SRC[127:96])
  THEN DEST[127:96] <- DEST[127:96];
  ELSE DEST[127:96] <- SRC[127:96]; FI;
VPMAXSD (VEX.128 encoded version)
  IF SRC1[31:0] > SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
  IF SRC1[127:95] > SRC2[127:95] THEN
     DEST[127:95] <- SRC1[127:95];
  ELSE
     DEST[127:95] <- SRC2[127:95]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXSD (VEX.256 encoded version)
  IF SRC1[31:0] > SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
  IF SRC1[255:224] > SRC2[255:224] THEN
     DEST[255:224] <- SRC1[255:224];
  ELSE
     DEST[255:224] <- SRC2[255:224]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMAXSD: | __m128i _mm_max_epi32 ( __m128i a, __m128i
|         | b);                                       
| VPMAXSD:| __m256i _mm256_max_epi32 ( __m256i a,     
|         | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMAXSW
description:
PMAXSW - Maximum of Packed Signed Word Integers:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F EE /r1 PMAXSW mm1, mm2/m64      | RM   | V/V                   | SSE               | Compare signed word integers in mm2/m64  
|                                    |      |                       |                   | and mm1 and return maximum values.       
| 66 0F EE /r PMAXSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare signed word integers in xmm2/m128
|                                    |      |                       |                   | and xmm1 and return maximum values.      
| VEX.NDS.128.66.0F.WIG EE /r VPMAXSW| RVM  | V/V                   | AVX               | Compare packed signed word integers      
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm3/m128 and xmm2 and store packed   
|                                    |      |                       |                   | maximum values in xmm1.                  
| VEX.NDS.256.66.0F.WIG EE /r VPMAXSW| RVM  | V/V                   | AVX2              | Compare packed signed word integers      
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm3/m128 and ymm2 and store packed   
|                                    |      |                       |                   | maximum values in ymm1.                  
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD compare of the packed signed word integers in the destination
operand (first operand) and the source operand (second operand), and returns
the maximum value for each pair of word integers to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand can be an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMAXSW (64-bit operands)
  IF DEST[15:0] > SRC[15:0]) THEN
     DEST[15:0] <- DEST[15:0];
  ELSE
     DEST[15:0] <- SRC[15:0]; FI;
  (* Repeat operation for 2nd and 3rd words in source and destination operands *)
  IF DEST[63:48] > SRC[63:48]) THEN
     DEST[63:48] <- DEST[63:48];
  ELSE
     DEST[63:48] <- SRC[63:48]; FI;
PMAXSW (128-bit operands)
  IF DEST[15:0] > SRC[15:0]) THEN
     DEST[15:0] <- DEST[15:0];
  ELSE
     DEST[15:0] <- SRC[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF DEST[127:112] > SRC[127:112]) THEN
     DEST[127:112] <- DEST[127:112];
  ELSE
     DEST[127:112] <- SRC[127:112]; FI;
VPMAXSW (VEX.128 encoded version)
  IF SRC1[15:0] > SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF SRC1[127:112] >SRC2[127:112] THEN
     DEST[127:112] <- SRC1[127:112];
  ELSE
     DEST[127:112] <- SRC2[127:112]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXSW (VEX.256 encoded version)
  IF SRC1[15:0] > SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 15th words in source and destination operands *)
  IF SRC1[255:240] >SRC2[255:240] THEN
     DEST[255:240] <- SRC1[255:240];
  ELSE
     DEST[255:240] <- SRC2[255:240]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMAXSW:   | __m64 _mm_max_pi16(__m64 a, __m64 b)      
| (V)PMAXSW:| __m128i _mm_max_epi16 ( __m128i a, __m128i
|           | b)                                        
| VPMAXSW:  | __m256i _mm256_max_epi16 ( __m256i a,     
|           | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMAXUB
description:
PMAXUB - Maximum of Packed Unsigned Byte Integers:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F DE /r1 PMAXUB mm1, mm2/m64      | RM   | V/V                   | SSE               | Compare unsigned byte integers in mm2/m64  
|                                    |      |                       |                   | and mm1 and returns maximum values.        
| 66 0F DE /r PMAXUB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare unsigned byte integers in xmm2/m128
|                                    |      |                       |                   | and xmm1 and returns maximum values.       
| VEX.NDS.128.66.0F.WIG DE /r VPMAXUB| RVM  | V/V                   | AVX               | Compare packed unsigned byte integers      
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm2 and xmm3/m128 and store packed     
|                                    |      |                       |                   | maximum values in xmm1.                    
| VEX.NDS.256.66.0F.WIG DE /r VPMAXUB| RVM  | V/V                   | AVX2              | Compare packed unsigned byte integers      
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm2 and ymm3/m256 and store packed     
|                                    |      |                       |                   | maximum values in ymm1.                    
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD compare of the packed unsigned byte integers in the destination
operand (first operand) and the source operand (second operand), and returns
the maximum value for each pair of byte integers to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand can be an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMAXUB (64-bit operands)
  IF DEST[7:0] > SRC[17:0]) THEN
     DEST[7:0] <- DEST[7:0];
  ELSE
     DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 7th bytes in source and destination operands *)
  IF DEST[63:56] > SRC[63:56]) THEN
     DEST[63:56] <- DEST[63:56];
  ELSE
     DEST[63:56] <- SRC[63:56]; FI;
PMAXUB (128-bit operands)
  IF DEST[7:0] > SRC[17:0]) THEN
     DEST[7:0] <- DEST[7:0];
  ELSE
     DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF DEST[127:120] > SRC[127:120]) THEN
     DEST[127:120] <- DEST[127:120];
  ELSE
     DEST[127:120] <- SRC[127:120]; FI;
VPMAXUB (VEX.128 encoded version)
  IF SRC1[7:0] >SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[7:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF SRC1[127:120] >SRC2[127:120] THEN
     DEST[127:120] <- SRC1[127:120];
  ELSE
     DEST[127:120] <- SRC2[127:120]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXUB (VEX.256 encoded version)
  IF SRC1[7:0] >SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[15:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
  IF SRC1[255:248] >SRC2[255:248] THEN
     DEST[255:248] <- SRC1[255:248];
  ELSE
     DEST[255:248] <- SRC2[255:248]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMAXUB:   | __m64 _mm_max_pu8(__m64 a, __m64 b)      
| (V)PMAXUB:| __m128i _mm_max_epu8 ( __m128i a, __m128i
|           | b)                                       
| VPMAXUB:  | __m256i _mm256_max_epu8 ( __m256i a,     
|           | __m256i b);                              

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


