# instructions

platform: ARM
mnem: SSAT
description:
Signed Saturate saturates an optionally-shifted signed value to a selectable signed range.       (F7.1.204)

This instruction sets PSTATE.Q to 1 if the operation saturates.


A1


  31       28 27 26 25 24 23 22 21 20             16 15       12 11             7 6 5 4 3            0
     !=1111    0 1 1 0 1 0 1            sat_imm          Rd             imm5      sh 0 1       Rn
      cond


Arithmetic shift right variant

Applies when sh = 1.

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>


Logical shift left variant

Applies when sh = 0.

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}


Decode for all variants of this encoding

 d = UInt(Rd);   n = UInt(Rn);   saturate_to = UInt(sat_imm)+1;
 (shift_t, shift_n) = DecodeImmShift(sh:'0', imm5);
 if d == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14    12 11          8 7 6 5 4                0
  1 1 1 1 0 (0) 1 1 0 0 sh 0                 Rn      0    imm3         Rd      imm2 (0)    sat_imm




Arithmetic shift right variant

Applies when sh = 1 && !(imm3 == 000 && imm2 == 00).

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>


Logical shift left variant

Applies when sh = 0.

SSAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}


Decode for all variants of this encoding

 if sh == '1' && (imm3:imm2) == '00000' then SEE SSAT16;
 d = UInt(Rd);   n = UInt(Rn);   saturate_to = UInt(sat_imm)+1;
 (shift_t, shift_n) = DecodeImmShift(sh:'0', imm3:imm2);
 if d == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.
        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

        <imm>          Is the bit position for saturation, in the range 1 to 32, encoded in the "sat_imm" field as <imm>-1.

        <Rn>           Is the general-purpose source register, encoded in the "Rn" field.

        <amount>       For encoding A1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in
                       the "imm5" field.

                       For encoding A1: is the shift amount, in the range 1 to 32 encoded in the "imm5" field as <amount>
                       modulo 32.

                       For encoding T1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in
                       the "imm3:imm2" field.

                       For encoding T1: is the shift amount, in the range 1 to 31 encoded in the "imm3:imm2" field as
                       <amount>.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             operand = Shift(R[n], shift_t, shift_n, PSTATE.C);         // PSTATE.C ignored
             (result, sat) = SignedSatQ(SInt(operand), saturate_to);
             R[d] = SignExtend(result, 32);
             if sat then
                 PSTATE.Q = '1';


platform: ARM
mnem: SSAT16
description:
Signed Saturate 16 saturates two signed 16-bit values to a selected signed range.       (F7.1.205)

This instruction sets PSTATE.Q to 1 if the operation saturates.


A1


  31       28 27 26 25 24 23 22 21 20 19             16 15       12 11 10 9 8 7 6 5 4 3                 0
     !=1111    0 1 1 0 1 0 1 0              sat_imm          Rd      (1) (1) (1) (1) 0 0 1 1       Rn
      cond


A1 variant

SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     saturate_to = UInt(sat_imm)+1;
 if d == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 0 (0) 1 1 0 0 1 0                    Rn        0 0 0 0          Rd         0 0 (0) (0) sat_imm




T1 variant

SSAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     saturate_to = UInt(sat_imm)+1;
 if d == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<imm>           Is the bit position for saturation, in the range 1 to 16, encoded in the "sat_imm" field as <imm>-1.

<Rn>            Is the general-purpose source register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     (result1, sat1) = SignedSatQ(SInt(R[n]<15:0>), saturate_to);
     (result2, sat2) = SignedSatQ(SInt(R[n]<31:16>), saturate_to);
             R[d]<15:0> = SignExtend(result1, 16);
             R[d]<31:16> = SignExtend(result2, 16);
             if sat1 || sat2 then
                 PSTATE.Q = '1';


platform: ARM
mnem: SSAX
description:
Signed Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit       (F7.1.206)
integer subtraction and one 16-bit addition, and writes the results to the destination register. It sets PSTATE.GE
according to the results.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                    0
     !=1111    0 1 1 0 0 0 0 1                Rn           Rd      (1) (1) (1) (1) 0 1 0 1          Rm
      cond


A1 variant

SSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3               0
   1 1 1 1 1 0 1 0 1 1 1 0                    Rn       1 1 1 1          Rd        0 0 0 0           Rm




T1 variant

SSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum  = SInt(R[n]<15:0>) + SInt(R[m]<31:16>);
     diff = SInt(R[n]<31:16>) - SInt(R[m]<15:0>);
             R[d]<15:0>  = sum<15:0>;
             R[d]<31:16> = diff<15:0>;
             PSTATE.GE<1:0> = if sum    >= 0 then '11' else '00';
             PSTATE.GE<3:2> = if diff >= 0 then '11' else '00';


platform: ARM
mnem: SSUB16
description:
Signed Subtract 16 performs two 16-bit signed integer subtractions, and writes the results to the destination register.       (F7.1.207)
It sets PSTATE.GE according to the results of the subtractions.


A1


   31       28 27 26 25 24 23 22 21 20 19        16 15         12 11 10 9 8 7 6 5 4 3                   0
      !=1111   0 1 1 0 0 0 0 1               Rn           Rd      (1) (1) (1) (1) 0 1 1 1         Rm
       cond


A1 variant

SSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


   15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14 13 12 11             8 7 6 5 4 3              0
   1 1 1 1 1 0 1 0 1 1 0 1                   Rn       1 1 1 1          Rd        0 0 0 0          Rm




T1 variant

SSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      diff1 = SInt(R[n]<15:0>) - SInt(R[m]<15:0>);
      diff2 = SInt(R[n]<31:16>) - SInt(R[m]<31:16>);
      R[d]<15:0>  = diff1<15:0>;
             R[d]<31:16> = diff2<15:0>;
             PSTATE.GE<1:0> = if diff1 >= 0 then '11' else '00';
             PSTATE.GE<3:2> = if diff2 >= 0 then '11' else '00';


platform: ARM
mnem: SSUB8
description:
Signed Subtract 8 performs four 8-bit signed integer subtractions, and writes the results to the destination register.       (F7.1.208)
It sets PSTATE.GE according to the results of the subtractions.


A1


   31       28 27 26 25 24 23 22 21 20 19        16 15         12 11 10 9 8 7 6 5 4 3                  0
      !=1111   0 1 1 0 0 0 0 1               Rn           Rd      (1) (1) (1) (1) 1 1 1 1        Rm
       cond


A1 variant

SSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


   15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14 13 12 11             8 7 6 5 4 3             0
   1 1 1 1 1 0 1 0 1 1 0 0                   Rn       1 1 1 1          Rd        0 0 0 0         Rm




T1 variant

SSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      diff1 = SInt(R[n]<7:0>) - SInt(R[m]<7:0>);
      diff2 = SInt(R[n]<15:8>) - SInt(R[m]<15:8>);
      diff3 = SInt(R[n]<23:16>) - SInt(R[m]<23:16>);
             diff4 = SInt(R[n]<31:24>) - SInt(R[m]<31:24>);
             R[d]<7:0>   = diff1<7:0>;
             R[d]<15:8>  = diff2<7:0>;
             R[d]<23:16> = diff3<7:0>;
             R[d]<31:24> = diff4<7:0>;
             PSTATE.GE<0>   = if diff1 >= 0 then '1' else '0';
             PSTATE.GE<1>   = if diff2 >= 0 then '1' else '0';
             PSTATE.GE<2>   = if diff3 >= 0 then '1' else '0';
             PSTATE.GE<3>   = if diff4 >= 0 then '1' else '0';


platform: ARM
mnem: STC
description:
Store Coprocessor stores data from a conceptual coprocessor to a sequence of consecutive memory addresses.       (F7.1.209)

This is a generic coprocessor instruction. The coproc field identifies the target conceptual coprocessor. This must be
one of CP10, CP11, CP14, or CP15, and for these CP values, this manual defines the imm8, CRd, and D field values
that are valid STC and STC2 instructions. Other encodings are UNDEFINED. For more information see Conceptual
coprocessor support on page E1-2414 and General behavior of System registers on page G4-4172.

In an implementation that includes EL2, the permitted STC access to a system control register can be trapped to Hyp
mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would
be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see
Trapping general CP14 accesses to debug registers on page G1-3923.

For simplicity, the STC pseudocode does not show this possible trap to Hyp mode.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11          8 7                      0
     !=1111     1 1 0 P U D W 0               Rn          CRd          !=101x              imm8
      cond                                                              coproc


Offset variant

Applies when P = 1 && W = 0.

STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 1.

STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


Unindexed variant

Applies when P = 0 && U = 1 && W = 0.

STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


Decode for all variants of this encoding

 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MCRR, MCRR2;
 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 n = UInt(Rn);    cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);       index = (P == '1');    add = (U == '1');     wback = (W == '1');
 if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19          16 15        12 11          8 7                      0
   1 1 1 1 1 1 0 P U D W 0                    Rn          CRd          !=101x              imm8
      cond                                                              coproc
        Offset variant

        Applies when P = 1 && W = 0.

        STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 1.

        STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.

        STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


        Unindexed variant

        Applies when P = 0 && U = 1 && W = 0.

        STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


        Decode for all variants of this encoding

         if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
         if P == '0' && U == '0' && D == '1' && W == '0' then SEE MCRR, MCRR2;
         if coproc == '101x' then UNDEFINED;
         n = UInt(Rn);  cp = UInt(coproc);
         imm32 = ZeroExtend(imm8:'00', 32);      index = (P == '1');add = (U == '1');wback = (W == '1');
         if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15      12 11       8 7                  0
           1 1 1 0 1 1 0 P U D W 0                    Rn         CRd     !=101x         imm8
                                                                         coproc


        Offset variant

        Applies when P = 1 && W = 0.

        STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


        Post-indexed variant

        Applies when P = 0 && W = 1.

        STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


        Pre-indexed variant

        Applies when P = 1 && W = 1.

        STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


        Unindexed variant

        Applies when P = 0 && U = 1 && W = 0.

        STC{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>
Decode for all variants of this encoding

 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MCRR, MCRR2;
 if coproc == '101x' then SEE "Advanced SIMD and Floating-point";
 n = UInt(Rn);  cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);      index = (P == '1');   add = (U == '1');    wback = (W == '1');
 if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11         8 7                       0
  1 1 1 1 1 1 0 P U D W 0                    Rn          CRd         !=101x              imm8
                                                                     coproc


Offset variant

Applies when P = 1 && W = 0.

STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>{, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 1.

STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>, #{+/-}<imm>]!


Unindexed variant

Applies when P = 0 && U = 1 && W = 0.

STC2{L}{<c>}{<q>} <coproc>, <CRd>, [<Rn>], <option>


Decode for all variants of this encoding

 if P == '0' && U == '0' && D == '0' && W == '0' then UNDEFINED;
 if P == '0' && U == '0' && D == '1' && W == '0' then SEE MCRR, MCRR2;
 if coproc == '101x' then UNDEFINED;
 n = UInt(Rn);  cp = UInt(coproc);
 imm32 = ZeroExtend(imm8:'00', 32);      index = (P == '1');   add = (U == '1');    wback = (W == '1');
 if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly STC, STC2 on page J1-5359.

Advanced SIMD and floating-point: Advanced SIMD and floating-point register load/store instructions on
page F5-2602.


Assembler symbols

L              If specified, selects the D == 1 form of the encoding. If omitted, selects the D == 0 form.

<c>            For encoding A1, T1 and T2: see Standard assembler syntax fields on page F2-2506.

               For encoding A2: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.
        <q>            See Standard assembler syntax fields on page F2-2506.

        <coproc>       Is the name of the coprocessor, encoded in the "coproc" field. The valid coprocessor names are p10,
                       p11, p14, and p15.

        <CRd>          Is the coprocessor register to be transferred, encoded in the "CRd" field.

        <Rn>           For encoding A1, A2: is the general-purpose base register, encoded in the "Rn" field. The PC can
                       be used, but this is deprecated.

                       For encoding A1, A2, T1, T2: is the general-purpose base register, encoded in the "Rn" field.

        <option>       Is a coprocessor option, in the range 0 to 255 enclosed in { }, encoded in the "imm8" field.

        +/-            Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
                       encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <imm>          Is the immediate offset used for forming the address, a multiple of 4 in the range 0-1020, defaulting
                       to 0 and encoded in the "imm8" field, as <imm>/4.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             Coproc_CheckInstr(cp, ThisInstr());
             offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
             address = if index then offset_addr else R[n];
             repeat
                 MemA[address,4] = Coproc_GetWordToStore(cp, ThisInstr());
                 address = address + 4;
             until Coproc_DoneStoring(cp, ThisInstr());
             if wback then R[n] = offset_addr;


platform: ARM
mnem: STL
description:
Store-Release Word stores a word from a register to memory. The instruction also has memory ordering semantics       (F7.1.210)
as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15 14 13 12 11 10 9 8 7 6 5 4 3                     0
     !=1111    0 0 0 1 1 0 0 0               Rn       (1) (1) (1) (1) (1) (1) 0 0 1 0 0 1          Rt
      cond


A1 variant

STL{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15           12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 0                   Rn            Rt         (1) (1) (1) (1) 1 0 1 0 (1) (1) (1) (1)




T1 variant

STL{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     MemO[address, 4] = R[t];


platform: ARM
mnem: STLB
description:
Store-Release Byte stores a byte from a register to memory. The instruction also has memory ordering semantics as       (F7.1.211)
described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11 10 9 8 7 6 5 4 3                     0
     !=1111    0 0 0 1 1 1 0 0                Rn     (1) (1) (1) (1) (1) (1) 0 0 1 0 0 1          Rt
      cond


A1 variant

STLB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 0                    Rn          Rt         (1) (1) (1) (1) 1 0 0 0 (1) (1) (1) (1)




T1 variant

STLB{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     MemO[address, 1] = R[t]<7:0>;


platform: ARM
mnem: STLEX
description:
Store-Release Exclusive Word stores a word from a register to memory if the executing PE has exclusive access to       (F7.1.212)
the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was
performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                   0
     !=1111    0 0 0 1 1 0 0 0               Rn           Rd       (1) (1) 1 0 1 0 0 1             Rt
      cond


A1 variant

STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 0 1 0 0 0 1 1 0 0                   Rn           Rt       (1) (1) (1) (1) 1 1 1 0         Rd




T1 variant

STLEX{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the destination general-purpose register into which the status result of the store exclusive is
               written, encoded in the "Rd" field. The value returned is:

               0           If the operation updates memory.

               1           If the operation fails to update memory.
        <Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>            Is the general-purpose base register, encoded in the "Rn" field.

        Aborts and alignment

        If a synchronous Data Abort exception is generated by the execution of this instruction:

        .      Memory is not updated.

        .      <Rd> is not updated.

        A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to
        the following rules:

        .      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

        .      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

        If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
        synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


        Operation for all encodings

         if ConditionPassed() then
              EncodingSpecificOperations();
              address = R[n];
              if AArch32.ExclusiveMonitorsPass(address,4) then
                  MemO[address, 4] = R[t];
                  R[d] = ZeroExtend('0');
              else
                  R[d] = ZeroExtend('1');


platform: ARM
mnem: STLEXB
description:
Store-Release Exclusive Byte stores a byte from a register to memory if the executing PE has exclusive access to       (F7.1.213)
the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store was
performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                   0
     !=1111    0 0 0 1 1 1 0 0               Rn           Rd       (1) (1) 1 0 1 0 0 1             Rt
      cond


A1 variant

STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 0 1 0 0 0 1 1 0 0                   Rn           Rt       (1) (1) (1) (1) 1 1 0 0         Rd




T1 variant

STLEXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the destination general-purpose register into which the status result of the store exclusive is
               written, encoded in the "Rd" field. The value returned is:

               0           If the operation updates memory.

               1           If the operation fails to update memory.
        <Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>            Is the general-purpose base register, encoded in the "Rn" field.


        Aborts

        If a synchronous Data Abort exception is generated by the execution of this instruction:

        .      Memory is not updated.

        .      <Rd> is not updated.

        If ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data
        Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


        Operation for all encodings

         if ConditionPassed() then
              EncodingSpecificOperations();
              address = R[n];
              if AArch32.ExclusiveMonitorsPass(address,1) then
                  MemO[address, 1] = R[t]<7:0>;
                  R[d] = ZeroExtend('0');
              else
                  R[d] = ZeroExtend('1');


platform: ARM
mnem: STLEXD
description:
Store-Release Exclusive Doubleword stores a doubleword from two registers to memory if the executing PE has       (F7.1.214)
exclusive access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if
no store was performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
     !=1111    0 0 0 1 1 0 1 0               Rn           Rd       (1) (1) 1 0 1 0 0 1            Rt
      cond


A1 variant

STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    t2 = t+1;  n = UInt(Rn);
 if d == 15 || Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t || d == t2 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11         8 7 6 5 4 3               0
   1 1 1 0 1 0 0 0 1 1 0 0                   Rn           Rt            Rt2     1 1 1 1           Rd




T1 variant

STLEXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    t2 = UInt(Rt2);    n = UInt(Rn);
 if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t || d == t2 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly STLEXD on page J1-5376.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the destination general-purpose register into which the status result of the store exclusive is
               written, encoded in the "Rd" field. The value returned is:

               0           If the operation updates memory.

               1           If the operation fails to update memory.
        <Rt>            For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
                        <Rt> must be even-numbered and not R14.

                        For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.

        <Rt2>           For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

                        For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

        <Rn>            Is the general-purpose base register, encoded in the "Rn" field.


        Aborts and alignment

        If a synchronous Data Abort exception is generated by the execution of this instruction:

        .      Memory is not updated.

        .      <Rd> is not updated.

        A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to
        the following rules:

        .      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

        .      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

        If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
        synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


        Operation for all encodings

         if ConditionPassed() then
              EncodingSpecificOperations();
              address = R[n];
              // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.
              value = if BigEndian() then R[t]:R[t2] else R[t2]:R[t];
              if AArch32.ExclusiveMonitorsPass(address, 8) then
                  MemO[address, 8] = value;
                  R[d] = ZeroExtend('0');
              else
                  R[d] = ZeroExtend('1');


platform: ARM
mnem: STLEXH
description:
Store-Release Exclusive Halfword stores a halfword from a register to memory if the executing PE has exclusive       (F7.1.215)
access to the memory at that address, and returns a status value of 0 if the store was successful, or of 1 if no store
was performed.

The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3                   0
     !=1111    0 0 0 1 1 1 1 0               Rn           Rd       (1) (1) 1 0 1 0 0 1            Rt
      cond


A1 variant

STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 0 1 0 0 0 1 1 0 0                   Rn           Rt       (1) (1) (1) (1) 1 1 0 1        Rd




T1 variant

STLEXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


Decode for this encoding

 d = UInt(Rd);   t = UInt(Rt);    n = UInt(Rn);
 if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
 if d == n || d == t then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the destination general-purpose register into which the status result of the store exclusive is
               written, encoded in the "Rd" field. The value returned is:

               0           If the operation updates memory.

               1           If the operation fails to update memory.
        <Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>            Is the general-purpose base register, encoded in the "Rn" field.


        Aborts and alignment

        If a synchronous Data Abort exception is generated by the execution of this instruction:

        .      Memory is not updated

        .      <Rd> is not updated.

        A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to
        the following rules:

        .      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

        .      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

        If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
        synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


        Operation for all encodings

         if ConditionPassed() then
              EncodingSpecificOperations();
              address = R[n];
              if AArch32.ExclusiveMonitorsPass(address,2) then
                  MemO[address, 2] = R[t]<15:0>;
                  R[d] = ZeroExtend('0');
              else
                  R[d] = ZeroExtend('1');


platform: ARM
mnem: STLH
description:
Store-Release Halfword stores a halfword from a register to memory. The instruction also has memory ordering       (F7.1.216)
semantics as described in Load-Acquire, Store-Release on page B2-88.

For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
information about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11 10 9 8 7 6 5 4 3                     0
     !=1111   0 0 0 1 1 1 1 0               Rn       (1) (1) (1) (1) (1) (1) 0 0 1 0 0 1          Rt
      cond


A1 variant

STLH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15           12 11 10 9 8 7 6 5 4 3 2 1 0
   1 1 1 0 1 0 0 0 1 1 0 0                  Rn            Rt         (1) (1) (1) (1) 1 0 0 1 (1) (1) (1) (1)




T1 variant

STLH{<c>}{<q>} <Rt>, [<Rn>]


Decode for this encoding

 t = UInt(Rt); n = UInt(Rn);
 if t == 15 || n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     MemO[address, 2] = R[t]<15:0>;


platform: ARM
mnem: STM
description:
        Store Multiple (Increment After, Empty Ascending) stores multiple registers to consecutive memory locations using       (F7.1.217)
        an address from a base register. The consecutive memory locations start at this address, and the address just above
        the last of those locations can optionally be written back to the base register.

        The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
        from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
        page F2-2514.

        For details of related system instructions see STM (User registers).


        A1


          31         28 27 26 25 24 23 22 21 20 19         16 15                                             0
             !=1111     1 0 0 0 1 0 W 0               Rn                          register_list
              cond


        A1 variant

        STM{IA}{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        STMEA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Ascending stack


        Decode for this encoding

         n = UInt(Rn);     registers = register_list;    wback = (W == '1');
         if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10       8 7                       0
           1 1 0 0 0          Rn           register_list




        T1 variant

        STM{IA}{<c>}{<q>} <Rn>!, <registers>// Preferred syntax
        STMEA{<c>}{<q>} <Rn>!, <registers>// Alternate syntax, Empty Ascending stack


        Decode for this encoding

         n = UInt(Rn);     registers = '00000000':register_list;     wback = TRUE;
         if BitCount(registers) < 1 then UNPREDICTABLE;


        T2


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12                                    0
           1 1 1 0 1 0 0 0 1 0 W 0                    Rn      (0) M (0)                 register_list




        T2 variant

        STM{IA}{<c>}.W <Rn>{!}, <registers>// Preferred syntax, if <Rn>, '!' and <registers> can be represented
        in T1
        STMEA{<c>}.W <Rn>{!}, <registers>// Alternate syntax, Empty Ascending stack, if <Rn>, '!' and <registers>
        can be represented in T1
        STM{IA}{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        STMEA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Ascending stack
Decode for this encoding

 n = UInt(Rn);   registers = '0':M:'0':register_list;        wback = (W == '1');
 if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
 if wback && registers<n> == '1' then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly STM (STMIA, STMEA) on
page J1-5359.


Assembler symbols

IA             Is an optional suffix for the Increment After form.

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rn>           Is the general-purpose base register, encoded in the "Rn" field.

!              The address adjusted by the size of the data loaded is written back to the base register. If specified,
               it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<registers>    For encoding A1: is a list of one or more registers to be stored, separated by commas and surrounded
               by { and }. The PC can be in the list. However, ARM deprecates the use of instructions that include
               the PC in the list. If base register writeback is specified, and the base register is not the
               lowest-numbered register in the list, such an instruction stores an UNKNOWN value for the base
               register.

               For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded
               by { and }. The registers in the list must be in the range R0-R7, encoded in the "register_list" field.
               If the base register is not the lowest-numbered register in the list, such an instruction stores an
               UNKNOWN value for the base register.

               For encoding T2: is a list of one or more registers to be stored, separated by commas and surrounded
               by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field,
               and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it
               defaults to 0.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     address = R[n];
     for i = 0 to 14
         if registers<i> == '1' then
              if i == n && wback && i != LowestSetBit(registers) then
                  MemA[address,4] = bits(32) UNKNOWN;        // Only possible for encodings T1 and A1
              else
                  MemA[address,4] = R[i];
              address = address + 4;
     if registers<15> == '1' then      // Only possible for encoding A1
         MemA[address,4] = PCStoreValue();
     if wback then R[n] = R[n] + 4*BitCount(registers);


platform: ARM
mnem: STMDA
description:
     Store Multiple Decrement After (Empty Descending) stores multiple registers to consecutive memory locations       (F7.1.219)
     using an address from a base register. The consecutive memory locations end at this address, and the address just
     below the lowest of those locations can optionally be written back to the base register.

     The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
     from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
     page F2-2514.

     For details of related system instructions see STM (User registers).


     A1


       31        28 27 26 25 24 23 22 21 20 19            16 15                                                0
          !=1111     1 0 0 0 0 0 W 0                Rn                            register_list
           cond


     A1 variant

     STMDA{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
     STMED{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Empty Descending stack


     Decode for this encoding

      n = UInt(Rn);    registers = register_list;       wback = (W == '1');
      if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors, and particularly STMDA (STMED) on page J1-5360.


     Assembler symbols

     <c>             See Standard assembler syntax fields on page F2-2506.

     <q>             See Standard assembler syntax fields on page F2-2506.

     <Rn>            Is the general-purpose base register, encoded in the "Rn" field.

     !               The address adjusted by the size of the data loaded is written back to the base register. If specified,
                     it is encoded in the "W" field as 1, otherwise this field defaults to 0.

     <registers>     Is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The
                     PC can be in the list. However, ARM deprecates the use of instructions that include the PC in the
                     list. If base register writeback is specified, and the base register is not the lowest-numbered register
                     in the list, such an instruction stores an UNKNOWN value for the base register.


     Operation

      if ConditionPassed() then
          EncodingSpecificOperations();
          address = R[n] - 4*BitCount(registers) + 4;
          for i = 0 to 14
               if registers<i> == '1' then
                    if i == n && wback && i != LowestSetBit(registers) then
                        MemA[address,4] = bits(32) UNKNOWN;
                    else
                        MemA[address,4] = R[i];
                    address = address + 4;
if registers<15> == '1' then
   MemA[address,4] = PCStoreValue();
if wback then R[n] = R[n] - 4*BitCount(registers);


platform: ARM
mnem: STMDB
description:
        Store Multiple Decrement Before (Full Descending) stores multiple registers to consecutive memory locations       (F7.1.220)
        using an address from a base register. The consecutive memory locations end just below this address, and the
        address of the first of those locations can optionally be written back to the base register.

        The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
        from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
        page F2-2514.

        For details of related system instructions see STM (User registers).

        This instruction is used by the alias PUSH (multiple registers). See the Alias conditions on page F7-3099 table for
        details of when each alias is preferred.


        A1


          31        28 27 26 25 24 23 22 21 20 19          16 15                                             0
             !=1111     1 0 0 1 0 0 W 0               Rn                           register_list
              cond


        A1 variant

        STMDB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        STMFD{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Descending stack


        Decode for this encoding

         n = UInt(Rn);    registers = register_list;     wback = (W == '1');
         if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12                                    0
           1 1 1 0 1 0 0 1 0 0 W 0                    Rn       (0) M (0)               register_list




        T1 variant

        STMDB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
        STMFD{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Descending stack


        Decode for this encoding

         n = UInt(Rn);    registers = '0':M:'0':register_list;      wback = (W == '1');
         if n == 15 || BitCount(registers) < 2 then UNPREDICTABLE;
         if wback && registers<n> == '1' then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STMDB (STMFD) on page J1-5361.
Alias conditions


              Alias                           is preferred when

              PUSH (multiple registers)       W == '1' && Rn == '1101' && BitCount(register_list) > 1



Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rn>          Is the general-purpose base register, encoded in the "Rn" field.

!             The address adjusted by the size of the data loaded is written back to the base register. If specified,
              it is encoded in the "W" field as 1, otherwise this field defaults to 0.

<registers>   For encoding A1: is a list of one or more registers to be stored, separated by commas and surrounded
              by { and }. The PC can be in the list. However, ARM deprecates the use of instructions that include
              the PC in the list. If base register writeback is specified, and the base register is not the
              lowest-numbered register in the list, such an instruction stores an UNKNOWN value for the base
              register.

              For encoding T1: is a list of one or more registers to be stored, separated by commas and surrounded
              by { and }. The registers in the list must be in the range R0-R12, encoded in the "register_list" field,
              and can optionally contain the LR. If the LR is in the list, the "M" field is set to 1, otherwise it
              defaults to 0.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    address = R[n] - 4*BitCount(registers);
    for i = 0 to 14
        if registers<i> == '1' then
            if i == n && wback && i != LowestSetBit(registers) then
                 MemA[address,4] = bits(32) UNKNOWN;        // Only possible for encoding A1
            else
                 MemA[address,4] = R[i];
            address = address + 4;
    if registers<15> == '1' then      // Only possible for encoding A1
        MemA[address,4] = PCStoreValue();
    if wback then R[n] = R[n] - 4*BitCount(registers);


platform: ARM
mnem: STMIB
description:
     Store Multiple Increment Before (Full Ascending) stores multiple registers to consecutive memory locations using       (F7.1.221)
     an address from a base register. The consecutive memory locations start just above this address, and the address of
     the last of those locations can optionally be written back to the base register.

     The lowest-numbered register is loaded from the lowest memory address, through to the highest-numbered register
     from the highest memory address. See also Encoding of lists of general-purpose registers and the PC on
     page F2-2514.

     For details of related system instructions see STM (User registers).


     A1


       31         28 27 26 25 24 23 22 21 20 19            16 15                                                0
          !=1111     1 0 0 1 1 0 W 0                 Rn                            register_list
           cond


     A1 variant

     STMIB{<c>}{<q>} <Rn>{!}, <registers>// Preferred syntax
     STMFA{<c>}{<q>} <Rn>{!}, <registers>// Alternate syntax, Full Ascending stack


     Decode for this encoding

      n = UInt(Rn);     registers = register_list;       wback = (W == '1');
      if n == 15 || BitCount(registers) < 1 then UNPREDICTABLE;


     Notes for all encodings

     For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
     Architectural Constraints on UNPREDICTABLE behaviors, and particularly STMIB (STMFA) on page J1-5361.


     Assembler symbols

     <c>              See Standard assembler syntax fields on page F2-2506.

     <q>              See Standard assembler syntax fields on page F2-2506.

     <Rn>             Is the general-purpose base register, encoded in the "Rn" field.

     !                The address adjusted by the size of the data loaded is written back to the base register. If specified,
                      it is encoded in the "W" field as 1, otherwise this field defaults to 0.

     <registers>      Is a list of one or more registers to be stored, separated by commas and surrounded by { and }. The
                      PC can be in the list. However, ARM deprecates the use of instructions that include the PC in the
                      list. If base register writeback is specified, and the base register is not the lowest-numbered register
                      in the list, such an instruction stores an UNKNOWN value for the base register.


     Operation

      if ConditionPassed() then
          EncodingSpecificOperations();
          address = R[n] + 4;
          for i = 0 to 14
               if registers<i> == '1' then
                    if i == n && wback && i != LowestSetBit(registers) then
                         MemA[address,4] = bits(32) UNKNOWN;
                    else
                         MemA[address,4] = R[i];
                    address = address + 4;
if registers<15> == '1' then
   MemA[address,4] = PCStoreValue();
if wback then R[n] = R[n] + 4*BitCount(registers);


platform: ARM
mnem: STRBT
description:
Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses       (F7.1.226)
see Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

STRBT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or an optionally-shifted register value.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11                                 0
     !=1111     0 1 0 0 U 1 1 0              Rn           Rt                      imm12
      cond


A1 variant

STRBT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   postindex = TRUE;   add = (U == '1');
 register_form = FALSE;     imm32 = ZeroExtend(imm12, 32);
 if t == 15 || n == 15 || n == t then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11            7 6 5 4 3            0
     !=1111     0 1 1 0 U 1 1 0              Rn           Rt            imm5       type 0      Rm
      cond


A2 variant

STRBT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   m = UInt(Rm);   postindex = TRUE;     add = (U == '1');
 register_form = TRUE;     (shift_t, shift_n) = DecodeImmShift(type, imm5);
 if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7                        0
  1 1 1 1 1 0 0 0 0 0 0 0                  !=1111         Rt      1 1 1 0               imm8
                                             Rn


T1 variant

STRBT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then UNDEFINED;
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;   add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRBT on page J1-5367.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           For encoding A1: is the general-purpose register to be transferred, encoded in the "Rt" field. The PC
                       can be used, but this is deprecated.

                       For encoding A2 and T1: is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>           For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The SP can be
                       used.

                       For encoding A2 and T1: is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        <shift>        The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts
                       applied to a register on page F2-2510.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
                       defaulting to 0 and encoded in the "imm12" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then Shift(R[m], shift_t, shift_n, PSTATE.C) else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             MemU_unpriv[address,1] = R[t]<7:0>;
             if postindex then R[n] = offset_addr;


platform: ARM
mnem: STRD
description:
Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores       (F7.1.227)
two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information
about memory accesses see Memory accesses on page F2-2513.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11         8 7 6 5 4 3             0
    !=1111     0 0 0 P U 1 W 0              Rn             Rt        imm4H      1 1 1 1       imm4L
      cond


Offset variant

Applies when P = 1 && W = 0.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 0.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!


Decode for all variants of this encoding

 if Rt<0> == '1' then UNPREDICTABLE;
 t = UInt(Rt);  t2 = t+1;   n = UInt(Rn);    imm32 = ZeroExtend(imm4H:imm4L, 32);
 index = (P == '1');   add = (U == '1');    wback = (P == '0') || (W == '1');
 if P == '0' && W == '1' then UNPREDICTABLE;
 if wback && (n == 15 || n == t || n == t2) then UNPREDICTABLE;
 if t2 == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15          12 11         8 7                     0
  1 1 1 0 1 0 0 P U 1 W 0                 !=1111           Rt          Rt2               imm8
                                            Rn


Offset variant

Applies when P = 1 && W = 0.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}]


Post-indexed variant

Applies when P = 0 && W = 1.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm>


Pre-indexed variant

Applies when P = 1 && W = 1.

STRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]!
        Decode for all variants of this encoding

         if P == '0' && W == '0' then SEE "Related encodings";
         t = UInt(Rt);   t2 = UInt(Rt2);    n = UInt(Rn);   imm32 = ZeroExtend(imm8:'00', 32);
         index = (P == '1');   add = (U == '1');     wback = (W == '1');
         if wback && (n == t || n == t2) then UNPREDICTABLE;
         if n == 15 || t == 15 || t2 == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRD (immediate) on page J1-5372.

        Related encodings: Load/Store dual, Load/Store-Exclusive, Load-Acquire/Store-Release, table branch on
        page F3-2536.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
                       This register must be even-numbered and not R14.

                       For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.

        <Rt2>          For encoding A1: is the second general-purpose register to be transferred. This register must be
                       <R(t+1)>.

                       For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

        <Rn>           For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The PC can be
                       used, but this is deprecated.

                       For the offset, post-indexed or pre-indexed variant: is the general-purpose base register, encoded in
                       the "Rn" field.

        +/-            Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
                       encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm4H:imm4L" field.

                       For the post-indexed or pre-indexed variant: is the unsigned immediate byte offset, a multiple of 4,
                       in the range 0 to 1020, encoded in the "imm8" field as <imm>/4.

                       For the post-indexed or pre-indexed variant: is the 8-bit unsigned immediate byte offset, in the range
                       0 to 255, encoded in the "imm4H:imm4L" field.

                       For encoding T1: is the optional unsigned immediate byte offset, a multiple of 4, in the range 0 to
                       1020, defaulting to 0 and encoded in the "imm8" field as <imm>/4.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
             address = if index then offset_addr else R[n];
             if address == Align(address, 8) then
                 bits(64) data;
                 if BigEndian() then
                      data<63:32> = R[t];
                      data<31:0> = R[t2];
      else
          data<31:0> = R[t];
          data<63:32> = R[t2];
      MemA[address,8] = data;
   else
      MemA[address,4] = R[t];
      MemA[address+4,4] = R[t2];
   if wback then R[n] = offset_addr;


platform: ARM
mnem: STREX
description:
        Store Register Exclusive calculates an address from a base register value and an immediate offset, stores a word       (F7.1.229)
        from a register to the calculated address if the PE has exclusive access to the memory at that address, and returns a
        status value of 0 if the store was successful, or of 1 if no store was performed.

        For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
        information about memory accesses see Memory accesses on page F2-2513.


        A1


          31       28 27 26 25 24 23 22 21 20 19             16 15        12 11 10 9 8 7 6 5 4 3                0
             !=1111     0 0 0 1 1 0 0 0                Rn            Rd     (1) (1) 1 1 1 0 0 1            Rt
              cond


        A1 variant

        STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn> {, {#}<imm>}]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);    n = UInt(Rn);     imm32 = Zeros(32); // Zero offset
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
         if d == n || d == t then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11       8 7                       0
           1 1 1 0 1 0 0 0 0 1 0 0                     Rn            Rt          Rd               imm8




        T1 variant

        STREX{<c>}{<q>} <Rd>, <Rt>, [<Rn> {, #<imm>}]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);    n = UInt(Rn);     imm32 = ZeroExtend(imm8:'00', 32);
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
         if d == n || d == t then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STREX on page J1-5374.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the destination general-purpose register into which the status result of the store exclusive is
                        written, encoded in the "Rd" field. The value returned is:

                        0            If the operation updates memory.

                        1            If the operation fails to update memory.

        <Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

<imm>           For encoding A1: the immediate offset added to the value of <Rn> to calculate the address. <imm> can
                only be 0 or omitted.

                For encoding T1: the immediate offset added to the value of <Rn> to calculate the address. <imm> can
                be omitted, meaning an offset of 0. Values are multiples of 4 in the range 0-1020.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

.      Memory is not updated.

.      <Rd> is not updated.

A non word-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject to
the following rules:

.      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

.      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      address = R[n] + imm32;
      if AArch32.ExclusiveMonitorsPass(address,4) then
          MemA[address,4] = R[t];
          R[d] = ZeroExtend('0');
      else
          R[d] = ZeroExtend('1');


platform: ARM
mnem: STREXB
description:
        Store Register Exclusive Byte derives an address from a base register value, stores a byte from a register to the       (F7.1.230)
        derived address if the executing PE has exclusive access to the memory at that address, and returns a status value
        of 0 if the store was successful, or of 1 if no store was performed.

        For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
        information about memory accesses see Memory accesses on page F2-2513.


        A1


          31         28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
             !=1111      0 0 0 1 1 1 0 0                Rn          Rd      (1) (1) 1 1 1 0 0 1             Rt
              cond


        A1 variant

        STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);     n = UInt(Rn);
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
         if d == n || d == t then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15       12 11 10 9 8 7 6 5 4 3                  0
           1 1 1 0 1 0 0 0 1 1 0 0                      Rn          Rt      (1) (1) (1) (1) 0 1 0 0        Rd




        T1 variant

        STREXB{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);     n = UInt(Rn);
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
         if d == n || d == t then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STREXB on page J1-5374.


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.

        <q>              See Standard assembler syntax fields on page F2-2506.

        <Rd>             Is the destination general-purpose register into which the status result of the store exclusive is
                         written, encoded in the "Rd" field. The value returned is:

                         0           If the operation updates memory.

                         1           If the operation fails to update memory.

        <Rt>             Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

Aborts

If a synchronous Data Abort exception is generated by the execution of this instruction:

.      Memory is not updated.

.      <Rd> is not updated.

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      address = R[n];
      if AArch32.ExclusiveMonitorsPass(address,1) then
         MemA[address,1] = R[t]<7:0>;
         R[d] = ZeroExtend('0');
      else
         R[d] = ZeroExtend('1');


platform: ARM
mnem: STREXD
description:
        Store Register Exclusive Doubleword derives an address from a base register value, stores a 64-bit doubleword from       (F7.1.231)
        two registers to the derived address if the executing PE has exclusive access to the memory at that address, and
        returns a status value of 0 if the store was successful, or of 1 if no store was performed.

        For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
        information about memory accesses see Memory accesses on page F2-2513.


        A1


          31        28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                 0
             !=1111     0 0 0 1 1 0 1 0                Rn           Rd       (1) (1) 1 1 1 0 0 1            Rt
              cond


        A1 variant

        STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);     t2 = t+1;  n = UInt(Rn);
         if d == 15 || Rt<0> == '1' || t2 == 15 || n == 15 then UNPREDICTABLE;
         if d == n || d == t || d == t2 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11        8 7 6 5 4 3               0
           1 1 1 0 1 0 0 0 1 1 0 0                     Rn           Rt            Rt2     0 1 1 1          Rd




        T1 variant

        STREXD{<c>}{<q>} <Rd>, <Rt>, <Rt2>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);     t2 = UInt(Rt2);    n = UInt(Rn);
         if d == 15 || t == 15 || t2 == 15 || n == 15 then UNPREDICTABLE;
         // ARMv8-A removes UNPREDICTABLE for R13
         if d == n || d == t || d == t2 then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STREXD on page J1-5374.


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.

        <q>              See Standard assembler syntax fields on page F2-2506.

        <Rd>             Is the destination general-purpose register into which the status result of the store exclusive is
                         written, encoded in the "Rd" field. The value returned is:

                         0           If the operation updates memory.

                         1           If the operation fails to update memory.

                         <Rd> must not be the same as <Rn>, <Rt>, or <Rt2>.
<Rt>            For encoding A1: is the first general-purpose register to be transferred, encoded in the "Rt" field.
                <Rt> must be even-numbered and not R14.

                For encoding T1: is the first general-purpose register to be transferred, encoded in the "Rt" field.

<Rt2>           For encoding A1: is the second general-purpose register to be transferred. <Rt2> must be <R(t+1)>.

                For encoding T1: is the second general-purpose register to be transferred, encoded in the "Rt2" field.

<Rn>            Is the general-purpose base register, encoded in the "Rn" field.

Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

.      Memory is not updated.

.      <Rd> is not updated.

A non doubleword-aligned memory address causes an Alignment fault Data Abort exception to be generated,
subject to the following rules:

.      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

.      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      address = R[n];
      // Create doubleword to store such that R[t] will be stored at address and R[t2] at address+4.
      value = if BigEndian() then R[t]:R[t2] else R[t2]:R[t];
      if AArch32.ExclusiveMonitorsPass(address,8) then
          MemA[address,8] = value;    R[d] = ZeroExtend('0');
      else
          R[d] = ZeroExtend('1');


platform: ARM
mnem: STREXH
description:
        Store Register Exclusive Halfword derives an address from a base register value, stores a halfword from a register       (F7.1.232)
        to the derived address if the executing PE has exclusive access to the memory at that address, and returns a status
        value of 0 if the store was successful, or of 1 if no store was performed.

        For more information about support for shared memory see Synchronization and semaphores on page E2-2456. For
        information about memory accesses see Memory accesses on page F2-2513.


        A1


          31        28 27 26 25 24 23 22 21 20 19            16 15       12 11 10 9 8 7 6 5 4 3                 0
             !=1111     0 0 0 1 1 1 1 0                Rn           Rd      (1) (1) 1 1 1 0 0 1            Rt
              cond


        A1 variant

        STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);    n = UInt(Rn);
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE;
         if d == n || d == t then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15        12 11 10 9 8 7 6 5 4 3                 0
           1 1 1 0 1 0 0 0 1 1 0 0                     Rn           Rt      (1) (1) (1) (1) 0 1 0 1       Rd




        T1 variant

        STREXH{<c>}{<q>} <Rd>, <Rt>, [<Rn>]


        Decode for this encoding

         d = UInt(Rd);    t = UInt(Rt);    n = UInt(Rn);
         if d == 15 || t == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
         if d == n || d == t then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STREXH on page J1-5375.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the destination general-purpose register into which the status result of the store exclusive is
                        written, encoded in the "Rd" field. The value returned is:

                        0            If the operation updates memory.

                        1            If the operation fails to update memory.

        <Rt>            Is the general-purpose register to be transferred, encoded in the "Rt" field.
<Rn>            Is the general-purpose base register, encoded in the "Rn" field.


Aborts and alignment

If a synchronous Data Abort exception is generated by the execution of this instruction:

.      Memory is not updated.

.      <Rd> is not updated.

A non halfword-aligned memory address causes an Alignment fault Data Abort exception to be generated, subject
to the following rules:

.      If AArch32.ExclusiveMonitorsPass() returns TRUE, the exception is generated.

.      Otherwise, it is IMPLEMENTATION DEFINED whether the exception is generated.

If AArch32.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a
synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      address = R[n];
      if AArch32.ExclusiveMonitorsPass(address,2) then
           MemA[address,2] = R[t]<15:0>;
           R[d] = ZeroExtend('0');
      else
           R[d] = ZeroExtend('1');


platform: ARM
mnem: STRHT
description:
Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory       (F7.1.235)
accesses see Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

STRHT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or a register value.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11          8 7 6 5 4 3            0
     !=1111     0 0 0 0 U 1 1 0              Rn           Rt         imm4H       1 0 1 1      imm4L
      cond


A1 variant

STRHT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   postindex = TRUE;   add = (U == '1');
 register_form = FALSE;     imm32 = ZeroExtend(imm4H:imm4L, 32);
 if t == 15 || n == 15 || n == t then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 0 0 0 U 0 1 0              Rn           Rt      (0) (0) (0) (0) 1 0 1 1      Rm
      cond


A2 variant

STRHT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   m = UInt(Rm);   postindex = TRUE;     add = (U == '1');
 register_form = TRUE;
 if t == 15 || n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7                        0
  1 1 1 1 1 0 0 0 0 0 1 0                  !=1111         Rt       1 1 1 0              imm8
                                             Rn


T1 variant

STRHT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then UNDEFINED;
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;    add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRHT on page J1-5370.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           Is the general-purpose register to be transferred, encoded in the "Rt" field.

        <Rn>           Is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:

                       -            when U = 0

                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm4H:imm4L" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then R[m] else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             MemU_unpriv[address,2] = R[t]<15:0>;
             if postindex then R[n] = offset_addr;


platform: ARM
mnem: STRT
description:
Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see       (F7.1.236)
Memory accesses on page F2-2513.

The memory access is restricted as if the PE were running in User mode. This makes no difference if the PE is
actually running in User mode.

STRT is UNPREDICTABLE in Hyp mode.

The T32 instruction uses an offset addressing mode, that calculates the address used for the memory access from a
base register value and an immediate offset, and leaves the base register unchanged.

The A32 instruction uses a post-indexed addressing mode, that uses a base register value as the address for the
memory access, and calculates a new address from a base register value and an offset and writes it back to the base
register. The offset can be an immediate value or an optionally-shifted register value.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11                                  0
     !=1111     0 1 0 0 U 0 1 0              Rn           Rt                      imm12
      cond


A1 variant

STRT{<c>}{<q>} <Rt>, [<Rn>] {, #{+/-}<imm>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   postindex = TRUE;   add = (U == '1');
 register_form = FALSE;     imm32 = ZeroExtend(imm12, 32);
 if n == 15 || n == t then UNPREDICTABLE;


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11             7 6 5 4 3            0
     !=1111     0 1 1 0 U 0 1 0              Rn           Rt            imm5       type 0      Rm
      cond


A2 variant

STRT{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>}


Decode for this encoding

 t = UInt(Rt);    n = UInt(Rn);   m = UInt(Rm);   postindex = TRUE;     add = (U == '1');
 register_form = TRUE;     (shift_t, shift_n) = DecodeImmShift(type, imm5);
 if n == 15 || n == t || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11 10 9 8 7                         0
  1 1 1 1 1 0 0 0 0 1 0 0                  !=1111         Rt      1 1 1 0               imm8
                                             Rn


T1 variant

STRT{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}]
        Decode for this encoding

         if Rn == '1111' then UNDEFINED;
         t = UInt(Rt);  n = UInt(Rn);     postindex = FALSE;    add = TRUE;
         register_form = FALSE;   imm32 = ZeroExtend(imm8, 32);
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly STRT on page J1-5371.


        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rt>           For the offset variant: is the general-purpose register to be transferred, encoded in the "Rt" field.

                       For the post-indexed variant: is the general-purpose register to be transferred, encoded in the "Rt"
                       field. The PC can be used, but this is deprecated.

        <Rn>           For encoding A1: is the general-purpose base register, encoded in the "Rn" field. The SP can be
                       used.

                       For encoding A2 and T1: is the general-purpose base register, encoded in the "Rn" field.

        +/-            For encoding A1: specifies the offset is added to or subtracted from the base register, defaulting to
                       + if omitted and encoded in the "U" field. It can have the following values:
                       -            when U = 0
                       +            when U = 1

                       For encoding A2: specifies the index register is added to or subtracted from the base register,
                       defaulting to + if omitted and encoded in the "U" field. It can have the following values:
                       -            when U = 0
                       +            when U = 1

        <Rm>           Is the general-purpose index register, encoded in the "Rm" field.

        <shift>        The shift to apply to the value read from <Rm>. If absent, no shift is applied. Otherwise, see Shifts
                       applied to a register on page F2-2510.

        +              Specifies the offset is added to the base register.

        <imm>          For encoding A1: is the optional 12-bit unsigned immediate byte offset, in the range 0 to 4095,
                       defaulting to 0 and encoded in the "imm12" field.

                       For encoding T1: is an optional 8-bit unsigned immediate byte offset, in the range 0 to 255,
                       defaulting to 0 and encoded in the "imm8" field.


        Operation for all encodings

         if ConditionPassed() then
             if PSTATE.EL == EL2 then UNPREDICTABLE;                      // Hyp mode
             EncodingSpecificOperations();
             offset = if register_form then Shift(R[m], shift_t, shift_n, PSTATE.C) else imm32;
             offset_addr = if add then (R[n] + offset) else (R[n] - offset);
             address = if postindex then R[n] else offset_addr;
             if t == 15 then   // Only possible for encodings A1 and A2
                 data = PCStoreValue();
             else
                 data = R[t];
             MemU_unpriv[address,4] = data;
             if postindex then R[n] = offset_addr;


platform: ARM
mnem: SXTAB
description:
        Signed Extend and Add Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, adds the result to the       (F7.1.244)
        value in another register, and writes the final result to the destination register. The instruction can specify a rotation
        by 0, 8, 16, or 24 bits before extracting the 8-bit value.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15          12 11 10 9 8 7 6 5 4 3                  0
             !=1111     0 1 1 0 1 0 1 0              !=1111           Rd      rotate (0) (0) 0 1 1 1         Rm
              cond                                     Rn


        A1 variant

        SXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTB;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);     rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3              0
           1 1 1 1 1 0 1 0 0 1 0 0                   !=1111       1 1 1 1          Rd        1 (0) rotate    Rm
                                                       Rn


        T1 variant

        SXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTB;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);     rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

        <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

        <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

        <amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                        (omitted)    when rotate = 00

                        8            when rotate = 01
              16         when rotate = 10

              24         when rotate = 11


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = R[n] + SignExtend(rotated<7:0>, 32);


platform: ARM
mnem: SXTAB16
description:
        Signed Extend and Add Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, adds       (F7.1.245)
        the results to two 16-bit values from another register, and writes the final results to the destination register. The
        instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.


        A1


          31         28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                   0
             !=1111     0 1 1 0 1 0 0 0              !=1111         Rd      rotate (0) (0) 0 1 1 1          Rm
              cond                                    Rn


        A1 variant

        SXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTB16;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3               0
           1 1 1 1 1 0 1 0 0 0 1 0                   !=1111     1 1 1 1          Rd       1 (0) rotate      Rm
                                                      Rn


        T1 variant

        SXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTB16;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

        <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

        <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

        <amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                        (omitted)    when rotate = 00

                        8            when rotate = 01
              16         when rotate = 10

              24         when rotate = 11


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d]<15:0>  = R[n]<15:0> + SignExtend(rotated<7:0>, 16);
    R[d]<31:16> = R[n]<31:16> + SignExtend(rotated<23:16>, 16);


platform: ARM
mnem: SXTAH
description:
        Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result       (F7.1.246)
        to a value from another register, and writes the final result to the destination register. The instruction can specify a
        rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.


        A1


          31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                  0
             !=1111     0 1 1 0 1 0 1 1              !=1111         Rd       rotate (0) (0) 0 1 1 1         Rm
              cond                                     Rn


        A1 variant

        SXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTH;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11            8 7 6 5 4 3              0
           1 1 1 1 1 0 1 0 0 0 0 0                   !=1111     1 1 1 1           Rd       1 (0) rotate     Rm
                                                       Rn


        T1 variant

        SXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


        Decode for this encoding

         if Rn == '1111' then SEE SXTH;
         d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>             See Standard assembler syntax fields on page F2-2506.

        <q>             See Standard assembler syntax fields on page F2-2506.

        <Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

        <Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

        <Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

        <amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                        (omitted)    when rotate = 00

                        8            when rotate = 01
              16         when rotate = 10

              24         when rotate = 11


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d] = R[n] + SignExtend(rotated<15:0>, 32);


platform: ARM
mnem: SXTB16
description:
        Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the       (F7.1.248)
        results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the
        8-bit values.


        A1


          31         28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                    0
             !=1111     0 1 1 0 1 0 0 0 1 1 1 1                     Rd       rotate (0) (0) 0 1 1 1          Rm
              cond


        A1 variant

        SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}


        Decode for this encoding

         d = UInt(Rd);    m = UInt(Rm);      rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE;


        T1


          15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11                           8 7 6 5 4 3               0
           1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1                                Rd       1 (0) rotate      Rm




        T1 variant

        SXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}


        Decode for this encoding

         d = UInt(Rd);    m = UInt(Rm);      rotation = UInt(rotate:'000');
         if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>              See Standard assembler syntax fields on page F2-2506.

        <q>              See Standard assembler syntax fields on page F2-2506.

        <Rd>             Is the general-purpose destination register, encoded in the "Rd" field.

        <Rm>             Is the general-purpose source register, encoded in the "Rm" field.

        <amount>         Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                         (omitted)    when rotate = 00

                         8            when rotate = 01

                         16           when rotate = 10

                         24           when rotate = 11
Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    rotated = ROR(R[m], rotation);
    R[d]<15:0>  = SignExtend(rotated<7:0>, 16);
    R[d]<31:16> = SignExtend(rotated<23:16>, 16);


platform: ARM
mnem: TBB
description:
Table Branch Byte or Halfword causes a PC-relative forward branch using a table of single byte or halfword offsets.       (F7.1.250)
A base register provides a pointer to the table, and a second register supplies an index into the table. The branch
length is twice the value returned from the table.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11 10 9 8 7 6 5 4 3                     0
   1 1 1 0 1 0 0 0 1 1 0 1                    Rn      (1) (1) (1) (1) (0) (0) (0) (0) 0 0 0 H      Rm




Byte variant

Applies when H = 0.

TBB{<c>}{<q>} [<Rn>, <Rm>]// Outside or last in IT block


Halfword variant

Applies when H = 1.

TBH{<c>}{<q>} [<Rn>, <Rm>, LSL #1]// Outside or last in IT block


Decode for all variants of this encoding

 n = UInt(Rn);    m = UInt(Rm);   is_tbh = (H == '1');
 if m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
 if InITBlock() && !LastInITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rn>            Is the general-purpose base register holding the address of the table of branch lengths, encoded in
                the "Rn" field. The PC can be used. If it is, the table immediately follows this instruction.

<Rm>            For the byte variant: is the general-purpose index register, encoded in the "Rm" field. This register
                contains an integer pointing to a single byte in the table. The offset in the table is the value of the
                index.

                For the halfword variant: is the general-purpose index register, encoded in the "Rm" field. This
                register contains an integer pointing to a halfword in the table. The offset in the table is twice the
                value of the index.


Operation

 if ConditionPassed() then
     EncodingSpecificOperations();
     if is_tbh then
          halfwords = UInt(MemU[R[n]+LSL(R[m],1), 2]);
     else
          halfwords = UInt(MemU[R[n]+R[m], 1]);
     BranchWritePC(PC + 2*halfwords);


platform: ARM
mnem: TEQ
description:
Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate       (F7.1.251)
value. It updates the condition flags based on the result, and discards the result.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15 14 13 12 11                                  0
     !=1111    0 0 1 1 0 0 1 1               Rn       (0) (0) (0) (0)              imm12
      cond


A1 variant

TEQ{<c>}{<q>} <Rn>, #<const>


Decode for this encoding

 n = UInt(Rn);
 (imm32, carry) = A32ExpandImm_C(imm12, PSTATE.C);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14        12 11 10 9 8 7                      0
  1 1 1 1 0        i  0 0 1 0 0 1            Rn        0    imm3     1 1 1 1            imm8




T1 variant

TEQ{<c>}{<q>} <Rn>, #<const>


Decode for this encoding

 n = UInt(Rn);
 (imm32, carry) = T32ExpandImm_C(i:imm3:imm8, PSTATE.C);
 if n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rn>            For encoding A1: is the general-purpose source register, encoded in the "Rn" field. The PC can be
                used.

                For encoding T1: is the general-purpose source register, encoded in the "Rn" field.

<const>         For encoding A1: an immediate value. See Modified immediate constants in A32 instructions on
                page F4-2559 for the range of values.

                For encoding T1: an immediate value. See Modified immediate constants in T32 instructions on
                page F3-2530 for the range of values.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             result = R[n] EOR imm32;
             PSTATE.N = result<31>;
             PSTATE.Z = IsZeroBit(result);
             PSTATE.C = carry;
             // PSTATE.V unchanged


platform: ARM
mnem: UADD16
description:
Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register.       (F7.1.257)
It sets PSTATE.GE according to the results of the additions.


A1


   31       28 27 26 25 24 23 22 21 20 19        16 15         12 11 10 9 8 7 6 5 4 3                0
      !=1111   0 1 1 0 0 1 0 1               Rn           Rd      (1) (1) (1) (1) 0 0 0 1      Rm
       cond


A1 variant

UADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


   15 14 13 12 11 10 9 8 7 6 5 4 3                0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 0 0 1                   Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

UADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
      EncodingSpecificOperations();
      sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);
      sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);
      R[d]<15:0>  = sum1<15:0>;
             R[d]<31:16> = sum2<15:0>;
             PSTATE.GE<1:0> = if sum1 >= 0x10000 then '11' else '00';
             PSTATE.GE<3:2> = if sum2 >= 0x10000 then '11' else '00';


platform: ARM
mnem: UADD8
description:
Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It       (F7.1.258)
sets PSTATE.GE according to the results of the additions.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                 0
     !=1111   0 1 1 0 0 1 0 1                Rn           Rd      (1) (1) (1) (1) 1 0 0 1      Rm
      cond


A1 variant

UADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 0 0 0                   Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

UADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);  n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m     == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum1 = UInt(R[n]<7:0>) + UInt(R[m]<7:0>);
     sum2 = UInt(R[n]<15:8>) + UInt(R[m]<15:8>);
     sum3 = UInt(R[n]<23:16>) + UInt(R[m]<23:16>);
             sum4 = UInt(R[n]<31:24>) + UInt(R[m]<31:24>);
             R[d]<7:0>   = sum1<7:0>;
             R[d]<15:8>  = sum2<7:0>;
             R[d]<23:16> = sum3<7:0>;
             R[d]<31:24> = sum4<7:0>;
             PSTATE.GE<0>   = if sum1 >= 0x100 then '1' else '0';
             PSTATE.GE<1>   = if sum2 >= 0x100 then '1' else '0';
             PSTATE.GE<2>   = if sum3 >= 0x100 then '1' else '0';
             PSTATE.GE<3>   = if sum4 >= 0x100 then '1' else '0';


platform: ARM
mnem: UASX
description:
Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.259)
unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination
register. It sets PSTATE.GE according to the results.


A1


  31         28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111       0 1 1 0 0 1 0 1               Rn           Rd      (1) (1) (1) (1) 0 0 1 1      Rm
      cond


A1 variant

UASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 0 1 0                       Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

UASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>               See Standard assembler syntax fields on page F2-2506.

<q>               See Standard assembler syntax fields on page F2-2506.

<Rd>              Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>              Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>              Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff = UInt(R[n]<15:0>) - UInt(R[m]<31:16>);
     sum     = UInt(R[n]<31:16>) + UInt(R[m]<15:0>);
             R[d]<15:0>  = diff<15:0>;
             R[d]<31:16> = sum<15:0>;
             PSTATE.GE<1:0> = if diff >= 0 then '11' else '00';
             PSTATE.GE<3:2> = if sum    >= 0x10000 then '11' else '00';


platform: ARM
mnem: UDF
description:
Permanently Undefined generates an Undefined Instruction exception.       (F7.1.261)

The encodings for UDF used in this section are defined as permanently UNDEFINED in the ARMv8-A architecture.
However:

.     With the T32 instruction set, ARM deprecates using the UDF instruction in an IT block.

.     In the A32 instruction set, UDF is not conditional.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19                                     8 7 6 5 4 3              0
  1 1 1 0 0 1 1 1 1 1 1 1                                imm12                  1 1 1 1        imm4




A1 variant

UDF{<c>}{<q>} {#}<imm>


Decode for this encoding

 imm32 = ZeroExtend(imm12:imm4, 32);
 // imm32 is for assembly and disassembly only, and is ignored by hardware.


T1


  15 14 13 12 11 10 9 8 7                          0
  1 1 0 1 1 1 1 0                    imm8




T1 variant

UDF{<c>}{<q>} {#}<imm>


Decode for this encoding

 imm32 = ZeroExtend(imm8, 32);
 // imm32 is for assembly and disassembly only, and is ignored by hardware.


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11                                   0
  1 1 1 1 0 1 1 1 1 1 1 1                   imm4      1 0 1 0                     imm12




T2 variant

UDF{<c>}.W {#}<imm>// <imm> can be represented in T1
UDF{<c>}{<q>} {#}<imm>


Decode for this encoding

 imm32 = ZeroExtend(imm4:imm12, 32);
 // imm32 is for assembly and disassembly only, and is ignored by hardware.
        Assembler symbols

        <c>            For encoding A1: see Standard assembler syntax fields on page F2-2506. <c> must be AL or omitted.

                       For encoding T1 and T2: see Standard assembler syntax fields on page F2-2506. ARM deprecates
                       using any <c> value other than AL.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <imm>          For encoding A1: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
                       "imm12:imm4" field. The PE ignores the value of this constant.

                       For encoding T1: is a 8-bit unsigned immediate, in the range 0 to 255, encoded in the "imm8" field.
                       The PE ignores the value of this constant.

                       For encoding T2: is a 16-bit unsigned immediate, in the range 0 to 65535, encoded in the
                       "imm4:imm12" field. The PE ignores the value of this constant.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             UNDEFINED;


platform: ARM
mnem: UHADD16
description:
Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results       (F7.1.263)
to the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1               Rn           Rd      (1) (1) (1) (1) 0 0 0 1      Rm
      cond


A1 variant

UHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 0 0 1                    Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);
             sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);
             R[d]<15:0>  = sum1<16:1>;
             R[d]<31:16> = sum2<16:1>;


platform: ARM
mnem: UHADD8
description:
Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to       (F7.1.264)
the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1               Rn           Rd      (1) (1) (1) (1) 1 0 0 1      Rm
      cond


A1 variant

UHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 0 0 0                     Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum1 = UInt(R[n]<7:0>) + UInt(R[m]<7:0>);
     sum2 = UInt(R[n]<15:8>) + UInt(R[m]<15:8>);
     sum3 = UInt(R[n]<23:16>) + UInt(R[m]<23:16>);
             sum4 = UInt(R[n]<31:24>) + UInt(R[m]<31:24>);
             R[d]<7:0>   = sum1<8:1>;
             R[d]<15:8>  = sum2<8:1>;
             R[d]<23:16> = sum3<8:1>;
             R[d]<31:24> = sum4<8:1>;


platform: ARM
mnem: UHASX
description:
Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs       (F7.1.265)
one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results
to the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1               Rn           Rd      (1) (1) (1) (1) 0 0 1 1      Rm
      cond


A1 variant

UHASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 0 1 0                    Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff = UInt(R[n]<15:0>) - UInt(R[m]<31:16>);
             sum  = UInt(R[n]<31:16>) + UInt(R[m]<15:0>);
             R[d]<15:0>  = diff<16:1>;
             R[d]<31:16> = sum<16:1>;


platform: ARM
mnem: UHSAX
description:
Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs       (F7.1.266)
one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results
to the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1               Rn           Rd      (1) (1) (1) (1) 0 1 0 1      Rm
      cond


A1 variant

UHSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 1 1 0                    Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum   = UInt(R[n]<15:0>) + UInt(R[m]<31:16>);
             diff = UInt(R[n]<31:16>) - UInt(R[m]<15:0>);
             R[d]<15:0>  = sum<16:1>;
             R[d]<31:16> = diff<16:1>;


platform: ARM
mnem: UHSUB16
description:
Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the       (F7.1.267)
results to the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1                Rn           Rd      (1) (1) (1) (1) 0 1 1 1      Rm
      cond


A1 variant

UHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 1                      Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>              See Standard assembler syntax fields on page F2-2506.

<q>              See Standard assembler syntax fields on page F2-2506.

<Rd>             Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>             Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>             Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
             diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
             R[d]<15:0>  = diff1<16:1>;
             R[d]<31:16> = diff2<16:1>;


platform: ARM
mnem: UHSUB8
description:
Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the       (F7.1.268)
results to the destination register.


A1


  31        28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111     0 1 1 0 0 1 1 1                Rn           Rd      (1) (1) (1) (1) 1 1 1 1      Rm
      cond


A1 variant

UHSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 0                      Rn       1 1 1 1          Rd        0 1 1 0       Rm




T1 variant

UHSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);    n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>              See Standard assembler syntax fields on page F2-2506.

<q>              See Standard assembler syntax fields on page F2-2506.

<Rd>             Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>             Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>             Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<7:0>) - UInt(R[m]<7:0>);
     diff2 = UInt(R[n]<15:8>) - UInt(R[m]<15:8>);
     diff3 = UInt(R[n]<23:16>) - UInt(R[m]<23:16>);
             diff4 = UInt(R[n]<31:24>) - UInt(R[m]<31:24>);
             R[d]<7:0>   = diff1<8:1>;
             R[d]<15:8>  = diff2<8:1>;
             R[d]<23:16> = diff3<8:1>;
             R[d]<31:24> = diff4<8:1>;


platform: ARM
mnem: UMAAL
description:
Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value,       (F7.1.269)
adds two unsigned 32-bit values, and writes the 64-bit result to two registers.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11         8 7 6 5 4 3              0
     !=1111   0 0 0 0 0 1 0 0               RdHi         RdLo           Rm      1 0 0 1         Rn
      cond


A1 variant

UMAAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for this encoding

 dLo = UInt(RdLo);   dHi = UInt(RdHi);     n = UInt(Rn);   m = UInt(Rm);
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 if dHi == dLo then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11         8 7 6 5 4 3               0
  1 1 1 1 1 0 1 1 1 1 1 0                    Rn          RdLo          RdHi     0 1 1 0         Rm




T1 variant

UMAAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for this encoding

 dLo = UInt(RdLo);   dHi = UInt(RdHi);     n = UInt(Rn);   m = UInt(Rm);
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13
 if dHi == dLo then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly UMAAL on page J1-5358.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<RdLo>         Is the general-purpose source register holding the first addend and the destination register for the
               lower 32 bits of the result, encoded in the "RdLo" field.

<RdHi>         Is the general-purpose source register holding the second addend and the destination register for the
               upper 32 bits of the result, encoded in the "RdHi" field.

<Rn>           Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             result = UInt(R[n]) * UInt(R[m]) + UInt(R[dHi]) + UInt(R[dLo]);
             R[dHi] = result<63:32>;
             R[dLo] = result<31:0>;


platform: ARM
mnem: UMLALS
description:
Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and       (F7.1.270)
accumulates this with a 64-bit value.

In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely
affects performance on many implementations.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11          8 7 6 5 4 3               0
     !=1111    0 0 0 0 1 0 1 S              RdHi         RdLo           Rm      1 0 0 1          Rn
      cond


Flag setting variant

Applies when S = 1.

UMLALS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Not flag setting variant

Applies when S = 0.

UMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for all variants of this encoding

 dLo = UInt(RdLo);    dHi = UInt(RdHi);    n = UInt(Rn);   m = UInt(Rm);     setflags = (S == '1');
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 if dHi == dLo then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11          8 7 6 5 4 3               0
   1 1 1 1 1 0 1 1 1 1 1 0                   Rn          RdLo          RdHi     0 0 0 0         Rm




T1 variant

UMLAL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for this encoding

 dLo = UInt(RdLo);    dHi = UInt(RdHi);    n = UInt(Rn);   m = UInt(Rm);     setflags = FALSE;
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13
 if dHi == dLo then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly UMLAL on page J1-5359.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.
        <RdLo>         Is the general-purpose source register holding the lower 32 bits of the addend, and the destination
                       register for the lower 32 bits of the result, encoded in the "RdLo" field.

        <RdHi>         Is the general-purpose source register holding the upper 32 bits of the addend, and the destination
                       register for the upper 32 bits of the result, encoded in the "RdHi" field.

        <Rn>           Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

        <Rm>           Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             result = UInt(R[n]) * UInt(R[m]) + UInt(R[dHi]:R[dLo]);
             R[dHi] = result<63:32>;
             R[dLo] = result<31:0>;
             if setflags then
                 PSTATE.N = result<63>;
                 PSTATE.Z = IsZeroBit(result<63:0>);
                 // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: UMULLS
description:
Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result.       (F7.1.271)

In A32 instructions, the condition flags can optionally be updated based on the result. Use of this option adversely
affects performance on many implementations.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15       12 11          8 7 6 5 4 3               0
     !=1111    0 0 0 0 1 0 0 S              RdHi         RdLo           Rm      1 0 0 1          Rn
      cond


Flag setting variant

Applies when S = 1.

UMULLS{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Not flag setting variant

Applies when S = 0.

UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for all variants of this encoding

 dLo = UInt(RdLo);    dHi = UInt(RdHi);    n = UInt(Rn);   m = UInt(Rm);     setflags = (S == '1');
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 if dHi == dLo then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11          8 7 6 5 4 3               0
   1 1 1 1 1 0 1 1 1 0 1 0                   Rn          RdLo          RdHi     0 0 0 0         Rm




T1 variant

UMULL{<c>}{<q>} <RdLo>, <RdHi>, <Rn>, <Rm>


Decode for this encoding

 dLo = UInt(RdLo);    dHi = UInt(RdHi);    n = UInt(Rn);   m = UInt(Rm);     setflags = FALSE;
 if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
 // ARMv8-A removes UNPREDICTABLE for R13
 if dHi == dLo then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly UMULL on page J1-5358.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.
        <RdLo>         Is the general-purpose destination register for the lower 32 bits of the result, encoded in the "RdLo"
                       field.

        <RdHi>         Is the general-purpose destination register for the upper 32 bits of the result, encoded in the "RdHi"
                       field.

        <Rn>           Is the first general-purpose source register holding the multiplicand, encoded in the "Rn" field.

        <Rm>           Is the second general-purpose source register holding the multiplier, encoded in the "Rm" field.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             result = UInt(R[n]) * UInt(R[m]);
             R[dHi] = result<63:32>;
             R[dLo] = result<31:0>;
             if setflags then
                 PSTATE.N = result<63>;
                 PSTATE.Z = IsZeroBit(result<63:0>);
                 // PSTATE.C, PSTATE.V unchanged


platform: ARM
mnem: UQADD16
description:
Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit       (F7.1.272)
unsigned integer range 0 <= x <= 216 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111   0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 0 0 0 1      Rm
      cond


A1 variant

UQADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 0 0 1                    Rn       1 1 1 1           Rd       0 1 0 1       Rm




T1 variant

UQADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);
             sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);
             R[d]<15:0>  = UnsignedSat(sum1, 16);
             R[d]<31:16> = UnsignedSat(sum2, 16);


platform: ARM
mnem: UQADD8
description:
Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned       (F7.1.273)
integer range 0 <= x <= 28 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                 0
     !=1111    0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 1 0 0 1       Rm
      cond


A1 variant

UQADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11             8 7 6 5 4 3            0
   1 1 1 1 1 0 1 0 1 0 0 0                    Rn       1 1 1 1          Rd        0 1 0 1        Rm




T1 variant

UQADD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum1 = UInt(R[n]<7:0>) + UInt(R[m]<7:0>);
     sum2 = UInt(R[n]<15:8>) + UInt(R[m]<15:8>);
     sum3 = UInt(R[n]<23:16>) + UInt(R[m]<23:16>);
             sum4 = UInt(R[n]<31:24>) + UInt(R[m]<31:24>);
             R[d]<7:0>   = UnsignedSat(sum1, 8);
             R[d]<15:8>  = UnsignedSat(sum2, 8);
             R[d]<23:16> = UnsignedSat(sum3, 8);
             R[d]<31:24> = UnsignedSat(sum4, 8);


platform: ARM
mnem: UQASX
description:
Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand,       (F7.1.274)
performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit
unsigned integer range 0 <= x <= 216 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                  0
     !=1111   0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 0 0 1 1       Rm
      cond


A1 variant

UQASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3             0
  1 1 1 1 1 0 1 0 1 0 1 0                    Rn       1 1 1 1           Rd       0 1 0 1        Rm




T1 variant

UQASX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff = UInt(R[n]<15:0>) - UInt(R[m]<31:16>);
             sum  = UInt(R[n]<31:16>) + UInt(R[m]<15:0>);
             R[d]<15:0>  = UnsignedSat(diff, 16);
             R[d]<31:16> = UnsignedSat(sum, 16);


platform: ARM
mnem: UQSAX
description:
Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand,       (F7.1.275)
performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit
unsigned integer range 0 <= x <= 216 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                  0
     !=1111   0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 0 1 0 1       Rm
      cond


A1 variant

UQSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3             0
  1 1 1 1 1 0 1 0 1 1 1 0                    Rn       1 1 1 1           Rd       0 1 0 1        Rm




T1 variant

UQSAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum  = UInt(R[n]<15:0>) + UInt(R[m]<31:16>);
             diff = UInt(R[n]<31:16>) - UInt(R[m]<15:0>);
             R[d]<15:0>  = UnsignedSat(sum, 16);
             R[d]<31:16> = UnsignedSat(diff, 16);


platform: ARM
mnem: UQSUB16
description:
Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the       (F7.1.276)
16-bit unsigned integer range 0 <= x <= 216 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                0
     !=1111   0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 0 1 1 1         Rm
      cond


A1 variant

UQSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 1                    Rn       1 1 1 1          Rd        0 1 0 1          Rm




T1 variant

UQSUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
             diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
             R[d]<15:0>  = UnsignedSat(diff1, 16);
             R[d]<31:16> = UnsignedSat(diff2, 16);


platform: ARM
mnem: UQSUB8
description:
Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit       (F7.1.277)
unsigned integer range 0 <= x <= 28 - 1, and writes the results to the destination register.


A1


  31       28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111   0 1 1 0 0 1 1 0                Rn           Rd      (1) (1) (1) (1) 1 1 1 1      Rm
      cond


A1 variant

UQSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 0                    Rn       1 1 1 1          Rd        0 1 0 1       Rm




T1 variant

UQSUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<7:0>) - UInt(R[m]<7:0>);
     diff2 = UInt(R[n]<15:8>) - UInt(R[m]<15:8>);
     diff3 = UInt(R[n]<23:16>) - UInt(R[m]<23:16>);
             diff4 = UInt(R[n]<31:24>) - UInt(R[m]<31:24>);
             R[d]<7:0>   = UnsignedSat(diff1, 8);
             R[d]<15:8>  = UnsignedSat(diff2, 8);
             R[d]<23:16> = UnsignedSat(diff3, 8);
             R[d]<31:24> = UnsignedSat(diff4, 8);


platform: ARM
mnem: USAD8
description:
Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of       (F7.1.278)
the differences together.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15 14 13 12 11           8 7 6 5 4 3             0
     !=1111     0 1 1 1 1 0 0 0               Rd       1 1 1 1          Rm      0 0 0 1         Rn
      cond


A1 variant

USAD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15 14 13 12 11           8 7 6 5 4 3              0
  1 1 1 1 1 0 1 1 0 1 1 1                     Rn       1 1 1 1          Rd      0 0 0 0         Rm




T1 variant

USAD8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     absdiff1 = Abs(UInt(R[n]<7:0>)       - UInt(R[m]<7:0>));
     absdiff2 = Abs(UInt(R[n]<15:8>)      - UInt(R[m]<15:8>));
     absdiff3 = Abs(UInt(R[n]<23:16>) - UInt(R[m]<23:16>));
             absdiff4 = Abs(UInt(R[n]<31:24>) - UInt(R[m]<31:24>));
             result = absdiff1 + absdiff2 + absdiff3 + absdiff4;
             R[d] = result<31:0>;


platform: ARM
mnem: USADA8
description:
Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the       (F7.1.279)
absolute values of the differences to a 32-bit accumulate operand.


A1


  31       28 27 26 25 24 23 22 21 20 19          16 15        12 11          8 7 6 5 4 3              0
     !=1111    0 1 1 1 1 0 0 0                Rd        !=1111           Rm      0 0 0 1         Rn
      cond                                                Ra


A1 variant

USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


Decode for this encoding

 if Ra == '1111' then SEE USAD8;
 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);    a = UInt(Ra);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11          8 7 6 5 4 3               0
  1 1 1 1 1 0 1 1 0 1 1 1                     Rn        !=1111           Rd      0 0 0 0         Rm
                                                          Ra


T1 variant

USADA8{<c>}{<q>} <Rd>, <Rn>, <Rm>, <Ra>


Decode for this encoding

 if Ra == '1111' then SEE USAD8;
 d = UInt(Rd);   n = UInt(Rn);    m = UInt(Rm);    a = UInt(Ra);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>           Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>           Is the second general-purpose source register, encoded in the "Rm" field.

<Ra>           Is the third general-purpose source register holding the addend, encoded in the "Ra" field.
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             absdiff1 = Abs(UInt(R[n]<7:0>)       - UInt(R[m]<7:0>));
             absdiff2 = Abs(UInt(R[n]<15:8>)      - UInt(R[m]<15:8>));
             absdiff3 = Abs(UInt(R[n]<23:16>) - UInt(R[m]<23:16>));
             absdiff4 = Abs(UInt(R[n]<31:24>) - UInt(R[m]<31:24>));
             result = UInt(R[a]) + absdiff1 + absdiff2 + absdiff3 + absdiff4;
             R[d] = result<31:0>;


platform: ARM
mnem: USAT
description:
Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range.       (F7.1.280)

This instruction sets PSTATE.Q to 1 if the operation saturates.


A1


  31       28 27 26 25 24 23 22 21 20            16 15        12 11            7 6 5 4 3             0
     !=1111    0 1 1 0 1 1 1            sat_imm          Rd             imm5     sh 0 1        Rn
      cond


Arithmetic shift right variant

Applies when sh = 1.

USAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>


Logical shift left variant

Applies when sh = 0.

USAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}


Decode for all variants of this encoding

 d = UInt(Rd);   n = UInt(Rn);  saturate_to = UInt(sat_imm);
 (shift_t, shift_n) = DecodeImmShift(sh:'0', imm5);
 if d == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15 14     12 11         8 7 6 5 4                 0
  1 1 1 1 0 (0) 1 1 1 0 sh 0                Rn       0   imm3          Rd     imm2 (0)     sat_imm




Arithmetic shift right variant

Applies when sh = 1 && !(imm3 == 000 && imm2 == 00).

USAT{<c>}{<q>} <Rd>, #<imm>, <Rn>, ASR #<amount>


Logical shift left variant

Applies when sh = 0.

USAT{<c>}{<q>} <Rd>, #<imm>, <Rn> {, LSL #<amount>}


Decode for all variants of this encoding

 if sh == '1' && (imm3:imm2) == '00000' then SEE USAT16;
 d = UInt(Rd);   n = UInt(Rn);  saturate_to = UInt(sat_imm);
 (shift_t, shift_n) = DecodeImmShift(sh:'0', imm3:imm2);
 if d == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.
        Assembler symbols

        <c>            See Standard assembler syntax fields on page F2-2506.

        <q>            See Standard assembler syntax fields on page F2-2506.

        <Rd>           Is the general-purpose destination register, encoded in the "Rd" field.

        <imm>          Is the bit position for saturation, in the range 0 to 31, encoded in the "sat_imm" field.

        <Rn>           Is the general-purpose source register, encoded in the "Rn" field.

        <amount>       For encoding A1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in
                       the "imm5" field.

                       For encoding A1: is the shift amount, in the range 1 to 32 encoded in the "imm5" field as <amount>
                       modulo 32.

                       For encoding T1: is the optional shift amount, in the range 0 to 31, defaulting to 0 and encoded in
                       the "imm3:imm2" field.

                       For encoding T1: is the shift amount, in the range 1 to 31 encoded in the "imm3:imm2" field as
                       <amount>.


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             operand = Shift(R[n], shift_t, shift_n, PSTATE.C);         // PSTATE.C ignored
             (result, sat) = UnsignedSatQ(SInt(operand), saturate_to);
             R[d] = ZeroExtend(result, 32);
             if sat then
                 PSTATE.Q = '1';


platform: ARM
mnem: USAT16
description:
Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range.       (F7.1.281)

This instruction sets PSTATE.Q to 1 if the operation saturates.


A1


  31       28 27 26 25 24 23 22 21 20 19             16 15       12 11 10 9 8 7 6 5 4 3                 0
     !=1111    0 1 1 0 1 1 1 0              sat_imm          Rd      (1) (1) (1) (1) 0 0 1 1       Rn
      cond


A1 variant

USAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     saturate_to = UInt(sat_imm);
 if d == 15 || n == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 0 (0) 1 1 1 0 1 0                    Rn        0 0 0 0          Rd         0 0 (0) (0) sat_imm




T1 variant

USAT16{<c>}{<q>} <Rd>, #<imm>, <Rn>


Decode for this encoding

 d = UInt(Rd);   n = UInt(Rn);     saturate_to = UInt(sat_imm);
 if d == 15 || n == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<imm>           Is the bit position for saturation, in the range 0 to 15, encoded in the "sat_imm" field.

<Rn>            Is the general-purpose source register, encoded in the "Rn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     (result1, sat1) = UnsignedSatQ(SInt(R[n]<15:0>), saturate_to);
     (result2, sat2) = UnsignedSatQ(SInt(R[n]<31:16>), saturate_to);
             R[d]<15:0> = ZeroExtend(result1, 16);
             R[d]<31:16> = ZeroExtend(result2, 16);
             if sat1 || sat2 then
                 PSTATE.Q = '1';


platform: ARM
mnem: USAX
description:
Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one       (F7.1.282)
unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination
register. It sets PSTATE.GE according to the results.


A1


  31         28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111       0 1 1 0 0 1 0 1               Rn           Rd      (1) (1) (1) (1) 0 1 0 1      Rm
      cond


A1 variant

USAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 1 0                       Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

USAX{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>               See Standard assembler syntax fields on page F2-2506.

<q>               See Standard assembler syntax fields on page F2-2506.

<Rd>              Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>              Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>              Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     sum     = UInt(R[n]<15:0>) + UInt(R[m]<31:16>);
     diff = UInt(R[n]<31:16>) - UInt(R[m]<15:0>);
             R[d]<15:0>  = sum<15:0>;
             R[d]<31:16> = diff<15:0>;
             PSTATE.GE<1:0> = if sum    >= 0x10000 then '11' else '00';
             PSTATE.GE<3:2> = if diff >= 0 then '11' else '00';


platform: ARM
mnem: USUB16
description:
Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination       (F7.1.283)
register. It sets PSTATE.GE according to the results of the subtractions.


A1


  31         28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111       0 1 1 0 0 1 0 1               Rn           Rd      (1) (1) (1) (1) 0 1 1 1      Rm
      cond


A1 variant

USUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 1                       Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

USUB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>               See Standard assembler syntax fields on page F2-2506.

<q>               See Standard assembler syntax fields on page F2-2506.

<Rd>              Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>              Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>              Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<15:0>) - UInt(R[m]<15:0>);
     diff2 = UInt(R[n]<31:16>) - UInt(R[m]<31:16>);
     R[d]<15:0>      = diff1<15:0>;
             R[d]<31:16> = diff2<15:0>;
             PSTATE.GE<1:0> = if diff1 >= 0 then '11' else '00';
             PSTATE.GE<3:2> = if diff2 >= 0 then '11' else '00';


platform: ARM
mnem: USUB8
description:
Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination       (F7.1.284)
register. It sets PSTATE.GE according to the results of the subtractions.


A1


  31         28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                0
     !=1111       0 1 1 0 0 1 0 1               Rn           Rd      (1) (1) (1) (1) 1 1 1 1      Rm
      cond


A1 variant

USUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11             8 7 6 5 4 3            0
  1 1 1 1 1 0 1 0 1 1 0 0                       Rn       1 1 1 1          Rd        0 1 0 0       Rm




T1 variant

USUB8{<c>}{<q>} {<Rd>,} <Rn>, <Rm>


Decode for this encoding

 d = UInt(Rd);     n = UInt(Rn);     m = UInt(Rm);
 if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>               See Standard assembler syntax fields on page F2-2506.

<q>               See Standard assembler syntax fields on page F2-2506.

<Rd>              Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>              Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>              Is the second general-purpose source register, encoded in the "Rm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();
     diff1 = UInt(R[n]<7:0>) - UInt(R[m]<7:0>);
     diff2 = UInt(R[n]<15:8>) - UInt(R[m]<15:8>);
     diff3 = UInt(R[n]<23:16>) - UInt(R[m]<23:16>);
             diff4 = UInt(R[n]<31:24>) - UInt(R[m]<31:24>);
             R[d]<7:0>   = diff1<7:0>;
             R[d]<15:8>  = diff2<7:0>;
             R[d]<23:16> = diff3<7:0>;
             R[d]<31:24> = diff4<7:0>;
             PSTATE.GE<0>   = if diff1 >= 0 then '1' else '0';
             PSTATE.GE<1>   = if diff2 >= 0 then '1' else '0';
             PSTATE.GE<2>   = if diff3 >= 0 then '1' else '0';
             PSTATE.GE<3>   = if diff4 >= 0 then '1' else '0';


platform: ARM
mnem: UXTAB
description:
Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to       (F7.1.285)
the value in another register, and writes the final result to the destination register. The instruction can specify a
rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value.


A1


  31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                  0
     !=1111     0 1 1 0 1 1 1 0              !=1111          Rd      rotate (0) (0) 0 1 1 1          Rm
      cond                                     Rn


A1 variant

UXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTB;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11            8 7 6 5 4 3              0
   1 1 1 1 1 0 1 0 0 1 0 1                   !=1111     1 1 1 1            Rd       1 (0) rotate     Rm
                                               Rn


T1 variant

UXTAB{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTB;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

<amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                (omitted)    when rotate = 00

                8            when rotate = 01
                       16           when rotate = 10

                       24           when rotate = 11


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             rotated = ROR(R[m], rotation);
             R[d] = R[n] + ZeroExtend(rotated<7:0>, 32);


platform: ARM
mnem: UXTAB16
description:
Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds       (F7.1.286)
the results to two 16-bit values from another register, and writes the final results to the destination register. The
instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values.


A1


  31         28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                   0
     !=1111     0 1 1 0 1 1 0 0              !=1111         Rd      rotate (0) (0) 0 1 1 1          Rm
      cond                                    Rn


A1 variant

UXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTB16;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15 14 13 12 11            8 7 6 5 4 3               0
  1 1 1 1 1 0 1 0 0 0 1 1                    !=1111     1 1 1 1          Rd       1 (0) rotate      Rm
                                              Rn


T1 variant

UXTAB16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTB16;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

<amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                (omitted)    when rotate = 00

                8            when rotate = 01
                       16           when rotate = 10

                       24           when rotate = 11


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             rotated = ROR(R[m], rotation);
             R[d]<15:0>  = R[n]<15:0> + ZeroExtend(rotated<7:0>, 16);
             R[d]<31:16> = R[n]<31:16> + ZeroExtend(rotated<23:16>, 16);


platform: ARM
mnem: UXTAH
description:
Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result       (F7.1.287)
to a value from another register, and writes the final result to the destination register. The instruction can specify a
rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value.


A1


  31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                  0
     !=1111     0 1 1 0 1 1 1 1              !=1111         Rd       rotate (0) (0) 0 1 1 1         Rm
      cond                                     Rn


A1 variant

UXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTH;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15 14 13 12 11            8 7 6 5 4 3              0
   1 1 1 1 1 0 1 0 0 0 0 1                   !=1111     1 1 1 1           Rd       1 (0) rotate     Rm
                                               Rn


T1 variant

UXTAH{<c>}{<q>} {<Rd>,} <Rn>, <Rm> {, ROR #<amount>}


Decode for this encoding

 if Rn == '1111' then SEE UXTH;
 d = UInt(Rd);    n = UInt(Rn);    m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506.

<q>             See Standard assembler syntax fields on page F2-2506.

<Rd>            Is the general-purpose destination register, encoded in the "Rd" field.

<Rn>            Is the first general-purpose source register, encoded in the "Rn" field.

<Rm>            Is the second general-purpose source register, encoded in the "Rm" field.

<amount>        Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                (omitted)    when rotate = 00

                8            when rotate = 01
                       16           when rotate = 10

                       24           when rotate = 11


        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             rotated = ROR(R[m], rotation);
             R[d] = R[n] + ZeroExtend(rotated<15:0>, 32);


platform: ARM
mnem: UXTB16
description:
Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes       (F7.1.289)
the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting
the 8-bit values.


A1


  31         28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                    0
     !=1111      0 1 1 0 1 1 0 0 1 1 1 1                     Rd       rotate (0) (0) 0 1 1 1         Rm
      cond


A1 variant

UXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}


Decode for this encoding

 d = UInt(Rd);     m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11                            8 7 6 5 4 3              0
  1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1                                  Rd       1 (0) rotate     Rm




T1 variant

UXTB16{<c>}{<q>} {<Rd>,} <Rm> {, ROR #<amount>}


Decode for this encoding

 d = UInt(Rd);     m = UInt(Rm);    rotation = UInt(rotate:'000');
 if d == 15 || m == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>              See Standard assembler syntax fields on page F2-2506.

<q>              See Standard assembler syntax fields on page F2-2506.

<Rd>             Is the general-purpose destination register, encoded in the "Rd" field.

<Rm>             For encoding A1: is the general-purpose source register, encoded in the "Rm" field.

                 For encoding T1: is the second general-purpose source register, encoded in the "Rm" field.

<amount>         Is the rotate amount, encoded in the "rotate" field. It can have the following values:

                 (omitted)    when rotate = 00

                 8            when rotate = 01

                 16           when rotate = 10

                 24           when rotate = 11
        Operation for all encodings

         if ConditionPassed() then
             EncodingSpecificOperations();
             rotated = ROR(R[m], rotation);
             R[d]<15:0>  = ZeroExtend(rotated<7:0>, 16);
             R[d]<31:16> = ZeroExtend(rotated<23:16>, 16);


platform: ARM
mnem: FLDMDBX
description:
        FLDMDBX loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register       (F8.1.5)
        file using an address from a general-purpose register. ARM deprecates use of FLDMDBX, except for disassembly
        purposes, and reassembly of disassembled code.

        This instruction is an alias of the VLDM, VLDMDB, VLDMIA instruction. This means that:

        .       The encodings in this description are named to match the encodings of VLDM, VLDMDB, VLDMIA.

        .       The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


        A1


           31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7                         0
              !=1111     1 1 0 1 0 D 1 1                Rn           Vd         1 0 1 1               imm8
               cond                 P U       W


        Decrement Before variant

        FLDMDBX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VLDMDB{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11 10 9 8 7                         0
            1 1 1 0 1 1 0 1 0 D 1 1                     Rn           Vd         1 0 1 1               imm8
                                    P U       W


        Decrement Before variant

        FLDMDBX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VLDMDB{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Rn>              For encoding A1: is the general-purpose base register, encoded in the "Rn" field. If writeback is not
                          specified, the PC can be used.

                          For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

        !                 Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus
                          one. The list must contain at least one register, all registers must be in the range D0-D15, and must
                          not contain more than 16 registers.
Operation for all encodings

The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: FLDMIAX
description:
        FLDMIAX loads multiple registers from consecutive locations in the Advanced SIMD and floating-point register       (F8.1.6)
        file using an address from a general-purpose register. ARM deprecates use of FLDMIAX, except for disassembly
        purposes, and reassembly of disassembled code.

        This instruction is an alias of the VLDM, VLDMDB, VLDMIA instruction. This means that:

        .       The encodings in this description are named to match the encodings of VLDM, VLDMDB, VLDMIA.

        .       The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


        A1


           31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7                         0
              !=1111     1 1 0 0 1 D W 1                Rn           Vd         1 0 1 1               imm8
               cond                 P U


        Increment After variant

        FLDMIAX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VLDM{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11 10 9 8 7                         0
            1 1 1 0 1 1 0 0 1 D W 1                     Rn           Vd         1 0 1 1               imm8
                                    P U


        Increment After variant

        FLDMIAX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VLDM{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Rn>              For encoding A1: is the general-purpose base register, encoded in the "Rn" field. If writeback is not
                          specified, the PC can be used.

                          For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

        !                 Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus
                          one. The list must contain at least one register, all registers must be in the range D0-D15, and must
                          not contain more than 16 registers.
Operation for all encodings

The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: FSTMDBX
description:
        FSTMDBX stores multiple registers from the Advanced SIMD and floating-point register file to consecutive       (F8.1.7)
        memory locations using an address from a general-purpose register. ARM deprecates use of FSTMDBX, except for
        disassembly purposes, and reassembly of disassembled code.

        This instruction is an alias of the VSTM, VSTMDB, VSTMIA instruction. This means that:

        .       The encodings in this description are named to match the encodings of VSTM, VSTMDB, VSTMIA.

        .       The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


        A1


           31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7                         0
              !=1111     1 1 0 1 0 D 1 0                Rn           Vd         1 0 1 1               imm8
               cond                 P U       W


        Decrement Before variant

        FSTMDBX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VSTMDB{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11 10 9 8 7                         0
            1 1 1 0 1 1 0 1 0 D 1 0                     Rn           Vd         1 0 1 1               imm8
                                    P U       W


        Decrement Before variant

        FSTMDBX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VSTMDB{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Rn>              For encoding A1: is the general-purpose base register, encoded in the "Rn" field. If writeback is not
                          specified, the PC can be used.

                          For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

        !                 Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus
                          one. The list must contain at least one register, all registers must be in the range D0-D15, and must
                          not contain more than 16 registers.
Operation for all encodings

The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: FSTMIAX
description:
        FSTMIAX stores multiple registers from the Advanced SIMD and floating-point register file to consecutive       (F8.1.8)
        memory locations using an address from a general-purpose register. ARM deprecates use of FSTMIAX, except for
        disassembly purposes, and reassembly of disassembled code.

        This instruction is an alias of the VSTM, VSTMDB, VSTMIA instruction. This means that:

        .       The encodings in this description are named to match the encodings of VSTM, VSTMDB, VSTMIA.

        .       The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


        A1


           31        28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7                         0
              !=1111     1 1 0 0 1 D W 0                Rn           Vd         1 0 1 1               imm8
               cond                 P U


        Increment After variant

        FSTMIAX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VSTM{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15         12 11 10 9 8 7                         0
            1 1 1 0 1 1 0 0 1 D W 0                     Rn           Vd         1 0 1 1               imm8
                                    P U


        Increment After variant

        FSTMIAX{<c>}{<q>} <Rn>{!}, <dreglist>

        is equivalent to

        VSTM{<c>}{<q>} <Rn>{!}, <dreglist>

        and is the preferred disassembly when imm8<0> == '1'.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Rn>              For encoding A1: is the general-purpose base register, encoded in the "Rn" field. If writeback is not
                          specified, the PC can be used.

                          For encoding T1: is the general-purpose base register, encoded in the "Rn" field.

        !                 Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list plus
                          one. The list must contain at least one register, all registers must be in the range D0-D15, and must
                          not contain more than 16 registers.
Operation for all encodings

The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: VABA
description:
Vector Absolute Difference and Accumulate subtracts the elements of one vector from the corresponding elements       (F8.1.19)
of another vector, and accumulates the absolute values of the results into the elements of the destination vector.

Operand and result elements are all integers of the same length.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction that is not also available as a
floating-point instruction, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 0 D size                  Vn            Vd       0 1 1 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 unsigned = (U == '1');     long_destination = FALSE;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 U 1 1 1 1 0 D size                  Vn            Vd       0 1 1 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VABA{<c>}{<q>}.<dt> <Dd>, <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VABA{<c>}{<q>}.<dt> <Qd>, <Qn>, <Qm>
        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         unsigned = (U == '1');       long_destination = FALSE;
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VABA or VABAL instruction must be
                          unconditional. ARM strongly recommends that a T32 VABA or VABAL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
                          following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

                          It is RESERVED when:

                          .      U = 0, size = 11.

                          .      U = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[Din[n+r],e,esize];
                        op2 = Elem[Din[m+r],e,esize];
                        absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
                        if long_destination then
                             Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + absdiff;
                        else
                             Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + absdiff;


platform: ARM
mnem: VABAL
description:
Vector Absolute Difference and Accumulate Long subtracts the elements of one vector from the corresponding       (F8.1.20)
elements of another vector, and accumulates the absolute values of the results into the elements of the destination
vector.

Operand elements are all integers of the same length, and the result elements are double the length of the operands.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction that is not also available as a
floating-point instruction, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 U 1 D !=11                  Vn            Vd       0 1 0 1 N 0 M 0              Vm
                                   size


A1 variant

VABAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 unsigned = (U == '1');     long_destination = TRUE;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = 1;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 U 1 1 1 1 1 D !=11                  Vn            Vd       0 1 0 1 N 0 M 0              Vm
                                   size


T1 variant

VABAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 unsigned = (U == '1');     long_destination = TRUE;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = 1;


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.
        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VABA or VABAL instruction must be
                          unconditional. ARM strongly recommends that a T32 VABA or VABAL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
                          following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[Din[n+r],e,esize];
                        op2 = Elem[Din[m+r],e,esize];
                        absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
                        if long_destination then
                             Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + absdiff;
                        else
                             Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + absdiff;


platform: ARM
mnem: VABD
description:
Vector Absolute Difference (floating-point) subtracts the elements of one vector from the corresponding elements       (F8.1.21)
of another vector, and places the absolute values of the results in the elements of the destination vector.

Operand and result elements are all single-precision floating-point numbers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 0 D 1 sz                   Vn           Vd        1 1 0 1 N Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VABD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VABD{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 esize = 32;    elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 1 1 1 1 0 D 1 sz                   Vn           Vd        1 1 0 1 N Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VABD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VABD{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>
        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);      n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VABD instruction must be
                          unconditional. ARM strongly recommends that a T32 VABD instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[D[n+r],e,esize];      op2 = Elem[D[m+r],e,esize];
                        Elem[D[d+r],e,esize] = FPAbs(FPSub(op1,op2,StandardFPSCRValue()));


platform: ARM
mnem: VABDL
description:
Vector Absolute Difference Long (integer) subtracts the elements of one vector from the corresponding elements       (F8.1.23)
of another vector, and places the absolute values of the results in the elements of the destination vector.

Operand elements are all integers of the same length, and the result elements are double the length of the operands.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction that is not also available as a
floating-point instruction, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 1 D !=11                  Vn            Vd        0 1 1 1 N 0 M 0              Vm
                                   size


A1 variant

VABDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 unsigned = (U == '1');     long_destination = TRUE;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = 1;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 U 1 1 1 1 1 D !=11                  Vn            Vd        0 1 1 1 N 0 M 0              Vm
                                   size


T1 variant

VABDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 unsigned = (U == '1');     long_destination = TRUE;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = 1;


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VABD or VABDL instruction must be
                unconditional. ARM strongly recommends that a T32 VABD or VABDL instruction is unconditional, see
                Conditional execution on page F2-2507.
        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
                          following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[Din[n+r],e,esize];
                        op2 = Elem[Din[m+r],e,esize];
                        absdiff = Abs(Int(op1,unsigned) - Int(op2,unsigned));
                        if long_destination then
                             Elem[Q[d>>1],e,2*esize] = absdiff<2*esize-1:0>;
                        else
                             Elem[D[d+r],e,esize] = absdiff<esize-1:0>;


platform: ARM
mnem: VABS
description:
Vector Absolute takes the absolute value of each element in a vector, and places the results in a second vector. The       (F8.1.24)
floating-point version only clears the sign bit.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                       Vd         0 F 1 1 0 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VABS{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VABS{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 advsimd = TRUE;    floating_point = (F == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


A2


  31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
     !=1111    1 1 1 0 1 D 1 1 0 0 0 0                    Vd         1 0 1 sz 1 1 M 0             Vm
      cond


Single-precision scalar variant

Applies when sz = 0.

VABS{<c>}{<q>}.F32 <Sd>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VABS{<c>}{<q>}.F64 <Dd>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;    dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3          0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                      Vd       0 F 1 1 0 Q M 0        Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VABS{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VABS{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         advsimd = TRUE;     floating_point = (F == '1');
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3          0
            1 1 1 0 1 1 1 0 1 D 1 1 0 0 0 0                       Vd       1 0 1 sz 1 1 M 0       Vm




        Single-precision scalar variant

        Applies when sz = 0.

        VABS{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VABS{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE;     dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 Advanced SIMD VABS instruction
                          must be unconditional. ARM strongly recommends that a T32 Advanced SIMD VABS instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.
<dt>          Is the data type for the elements of the vectors, encoded in the "F:size" field. It can have the
              following values:

              S8           when F = 0, size = 00

              S16          when F = 0, size = 01

              S32          when F = 0, size = 10

              F32          when F = 1, size = 10

              It is RESERVED when:

              .      F = 0, size = 11.

              .      F = 1, size = 0x.

              .      F = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>          Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then   // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                 if floating_point then
                     Elem[D[d+r],e,esize] = FPAbs(Elem[D[m+r],e,esize]);
                 else
                     result = Abs(SInt(Elem[D[m+r],e,esize]));
                     Elem[D[d+r],e,esize] = result<esize-1:0>;
    else              // VFP instruction
        if dp_operation then
            D[d] = FPAbs(D[m]);
        else
            S[d] = FPAbs(S[m]);


platform: ARM
mnem: VACGE
description:
        Vector Absolute Compare Greater Than or Equal takes the absolute value of each element in a vector, and compares       (F8.1.25)
        it with the absolute value of the corresponding element of a second vector. If the first is greater than or equal to the
        second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

        The operands and result can be quadword or doubleword vectors. They must all be the same size.

        The operand vector elements must be 32-bit floating-point numbers.

        The result vector elements are 32-bit fields.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction that is not also available as a
        floating-point instruction, see Conditional execution on page F2-2507.

        This instruction is used by the alias VACLE. See the Alias conditions on page F8-3305 table for details of when
        each alias is preferred.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 1 0 0 1 1 0 D 0 0                  Vn            Vd      1 1 1 0 N Q M 1                  Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACGE{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VACGE{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         or_equal = (op == '0');     esize = 32;   elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 1 1 1 1 1 0 D 0 0                  Vn            Vd      1 1 1 0 N Q M 1                  Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACGE{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.
VACGE{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 or_equal = (op == '0');   esize = 32;   elements = 2;
 d = UInt(D:Vd);  n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Alias conditions


                   Alias                     is preferred when

                   VACLE                     Never



Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VACGE, VACGT, VACLE, or VACLT
              instruction must be unconditional. ARM strongly recommends that a T32 VACGE, VACGT, VACLE, or
              VACLT instruction is unconditional, see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();    CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             op1 = FPAbs(Elem[D[n+r],e,esize]);     op2 = FPAbs(Elem[D[m+r],e,esize]);
             if or_equal then
                 test_passed = FPCompareGE(op1, op2, StandardFPSCRValue());
             else
                 test_passed = FPCompareGT(op1, op2, StandardFPSCRValue());
             Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VACLE
description:
        Vector Absolute Compare Less Than or Equal takes the absolute value of each element in a vector, and compares       (F8.1.26)
        it with the absolute value of the corresponding element of a second vector. If the first is less than or equal to the
        second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros

        This instruction is an alias of the VACGE instruction. This means that:

        .       The encodings in this description are named to match the encodings of VACGE.

        .       The description of VACGE gives the operational pseudocode for this instruction.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19         16 15       12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 0 0 1 1 0 D 0 0                   Vn          Vd       1 1 1 0 N Q M 1                 Vm
                                            op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACLE{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>

        is equivalent to

        VACGE{<c>}{<q>}.F32 <Dd>, <Dm>, <Dn>

        and is never the preferred disassembly.

        128-bit SIMD vector variant

        Applies when Q = 1.

        VACLE{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>

        is equivalent to

        VACGE{<c>}{<q>}.F32 <Qd>, <Qm>, <Qn>

        and is never the preferred disassembly.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15       12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 1 1 1 1 0 D 0 0                   Vn          Vd       1 1 1 0 N Q M 1                 Vm
                                            op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACLE{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>

        is equivalent to

        VACGE{<c>}{<q>}.F32 <Dd>, <Dm>, <Dn>

        and is never the preferred disassembly.

        128-bit SIMD vector variant

        Applies when Q = 1.
VACLE{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>

is equivalent to

VACGE{<c>}{<q>}.F32 <Qd>, <Qm>, <Qn>

and is never the preferred disassembly.


Assembler symbols

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Qm>            Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                <Qm>*2.

<Qn>            Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VACGE, VACGT, VACLE, or VACLT
                instruction must be unconditional. ARM strongly recommends that a T32 VACGE, VACGT, VACLE, or
                VACLT instruction is unconditional, see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.


Operation for all encodings

The description of VACGE gives the operational pseudocode for this instruction.


platform: ARM
mnem: VACGT
description:
        Vector Absolute Compare Greater Than takes the absolute value of each element in a vector, and compares it with       (F8.1.27)
        the absolute value of the corresponding element of a second vector. If the first is greater than the second, the
        corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

        The operands and result can be quadword or doubleword vectors. They must all be the same size.

        The operand vector elements must be 32-bit floating-point numbers.

        The result vector elements are 32-bit fields.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction that is not also available as a
        floating-point instruction, see Conditional execution on page F2-2507.

        This instruction is used by the alias VACLT. See the Alias conditions on page F8-3309 table for details of when
        each alias is preferred.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 0 D 1 0                  Vn            Vd       1 1 1 0 N Q M 1                 Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACGT{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VACGT{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         or_equal = (op == '0');     esize = 32;   elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 0 D 1 0                  Vn            Vd       1 1 1 0 N Q M 1                 Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACGT{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.
VACGT{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 or_equal = (op == '0');   esize = 32;   elements = 2;
 d = UInt(D:Vd);  n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Alias conditions


                   Alias                     is preferred when

                   VACLT                     Never



Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VACGE, VACGT, VACLE, or VACLT
              instruction must be unconditional. ARM strongly recommends that a T32 VACGE, VACGT, VACLE, or
              VACLT instruction is unconditional, see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();    CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             op1 = FPAbs(Elem[D[n+r],e,esize]);     op2 = FPAbs(Elem[D[m+r],e,esize]);
             if or_equal then
                 test_passed = FPCompareGE(op1, op2, StandardFPSCRValue());
             else
                 test_passed = FPCompareGT(op1, op2, StandardFPSCRValue());
             Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VACLT
description:
        Vector Absolute Compare Less Than takes the absolute value of each element in a vector, and compares it with the       (F8.1.28)
        absolute value of the corresponding element of a second vector. If the first is less than the second, the corresponding
        element in the destination vector is set to all ones. Otherwise, it is set to all zeros

        This instruction is an alias of the VACGT instruction. This means that:

        .       The encodings in this description are named to match the encodings of VACGT.

        .       The description of VACGT gives the operational pseudocode for this instruction.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 1 0 D 1 0                    Vn          Vd         1 1 1 0 N Q M 1              Vm
                                            op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACLT{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>

        is equivalent to

        VACGT{<c>}{<q>}.F32 <Dd>, <Dm>, <Dn>

        and is never the preferred disassembly.

        128-bit SIMD vector variant

        Applies when Q = 1.

        VACLT{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>

        is equivalent to

        VACGT{<c>}{<q>}.F32 <Qd>, <Qm>, <Qn>

        and is never the preferred disassembly.


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 1 1 1 1 0 D 1 0                    Vn          Vd         1 1 1 0 N Q M 1              Vm
                                            op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VACLT{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>

        is equivalent to

        VACGT{<c>}{<q>}.F32 <Dd>, <Dm>, <Dn>

        and is never the preferred disassembly.

        128-bit SIMD vector variant

        Applies when Q = 1.
VACLT{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>

is equivalent to

VACGT{<c>}{<q>}.F32 <Qd>, <Qm>, <Qn>

and is never the preferred disassembly.


Assembler symbols

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Qm>            Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                <Qm>*2.

<Qn>            Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VACGE, VACGT, VACLE, or VACLT
                instruction must be unconditional. ARM strongly recommends that a T32 VACGE, VACGT, VACLE, or
                VACLT instruction is unconditional, see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.


Operation for all encodings

The description of VACGT gives the operational pseudocode for this instruction.


platform: ARM
mnem: VADD
description:
        Vector Add (floating-point) adds corresponding elements in two vectors, and places the results in the destination       (F8.1.29)
        vector.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 0 0 D 0 sz                  Vn          Vd       1 1 0 1 N Q M 0            Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VADD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VADD{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE;     esize = 32;  elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        A2


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3               0
              !=1111     1 1 1 0 0 D 1 1              Vn          Vd       1 0 1 sz N 0 M 0           Vm
               cond


        Single-precision scalar variant

        Applies when sz = 0.

        VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE;     dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3              0 15        12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 0 1 1 1 1 0 D 0 sz                Vn          Vd         1 1 0 1 N Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VADD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VADD{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE;  esize = 32;  elements = 2;
 d = UInt(D:Vd);  n = UInt(N:Vn);   m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3              0 15        12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 0 1 1 1 0 0 D 1 1                 Vn          Vd         1 0 1 sz N 0 M 0             Vm




Single-precision scalar variant

Applies when sz = 0.

VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;  dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


Assembler symbols

<c>           For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
              Advanced SIMD VADD instruction must be unconditional. ARM strongly recommends that a T32
              Advanced SIMD VADD instruction is unconditional, see Conditional execution on page F2-2507

              For encoding T2: see Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
               if advsimd then    // Advanced SIMD instruction
                   for r = 0 to regs-1
                        for e = 0 to elements-1
                             Elem[D[d+r],e,esize] = FPAdd(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
                                                             StandardFPSCRValue());
               else               // VFP instruction
                   if dp_operation then
                        D[d] = FPAdd(D[n], D[m], FPSCR);
                   else
                        S[d] = FPAdd(S[n], S[m], FPSCR);


platform: ARM
mnem: VADDHN
description:
Vector Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and places the       (F8.1.31)
most significant half of each result in a doubleword vector. The results are truncated. For rounded results, see
VRADDHN.

The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned
integers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 0 0 1 0 1 D !=11                   Vn           Vd       0 1 0 0 N 0 M 0              Vm
                                   size


A1 variant

VADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);     m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                0
   1 1 1 0 1 1 1 1 1 D !=11                   Vn           Vd       0 1 0 0 N 0 M 0              Vm
                                   size


T1 variant

VADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);     m = UInt(M:Vm);


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VADDHN instruction must be
                unconditional.ARM strongly recommends that a T32 VADDHN instruction is unconditional, see
                Conditional execution on page F2-2507.
        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "size" field. It can have the
                          following values:

                          I16          when size = 00

                          I32          when size = 01

                          I64          when size = 10

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for e = 0 to elements-1
                   result = Elem[Qin[n>>1],e,2*esize] + Elem[Qin[m>>1],e,2*esize];
                   Elem[D[d],e,esize] = result<2*esize-1:esize>;


platform: ARM
mnem: VADDL
description:
Vector Add Long adds corresponding elements in two doubleword vectors, and places the results in a quadword       (F8.1.32)
vector. Before adding, it sign-extends or zero-extends the elements of both operands.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 U 1 D !=11                   Vn           Vd       0 0 0 0 N 0 M 0              Vm
                                   size                                        op


A1 variant

VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' || (op == '1' && Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;     is_vaddw = (op == '1');
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 U 1 1 1 1 1 D !=11                   Vn           Vd       0 0 0 0 N 0 M 0              Vm
                                   size                                        op


T1 variant

VADDL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' || (op == '1' && Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;     is_vaddw = (op == '1');
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VADDL or VADDW instruction must be
                unconditional. ARM strongly recommends that a T32 VADDL or VADDW instruction is unconditional,
                see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.
        <dt>              Is the data type for the elements of the second operand vector, encoded in the "U:size" field. It can
                          have the following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for e = 0 to elements-1
                   if is_vaddw then
                        op1 = Int(Elem[Qin[n>>1],e,2*esize], unsigned);
                   else
                        op1 = Int(Elem[Din[n],e,esize], unsigned);
                   result = op1 + Int(Elem[Din[m],e,esize],unsigned);
                   Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;


platform: ARM
mnem: VADDW
description:
Vector Add Wide adds corresponding elements in one quadword and one doubleword vector, and places the results       (F8.1.33)
in a quadword vector. Before adding, it sign-extends or zero-extends the elements of the doubleword operand.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 U 1 D !=11                   Vn           Vd       0 0 0 1 N 0 M 0              Vm
                                   size                                        op


A1 variant

VADDW{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' || (op == '1' && Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;     is_vaddw = (op == '1');
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 U 1 1 1 1 1 D !=11                   Vn           Vd       0 0 0 1 N 0 M 0              Vm
                                   size                                        op


T1 variant

VADDW{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' || (op == '1' && Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;     is_vaddw = (op == '1');
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VADDL or VADDW instruction must be
                unconditional. ARM strongly recommends that a T32 VADDL or VADDW instruction is unconditional,
                see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.
        <dt>              Is the data type for the elements of the second operand vector, encoded in the "U:size" field. It can
                          have the following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for e = 0 to elements-1
                   if is_vaddw then
                        op1 = Int(Elem[Qin[n>>1],e,2*esize], unsigned);
                   else
                        op1 = Int(Elem[Din[n],e,esize], unsigned);
                   result = op1 + Int(Elem[Din[m],e,esize],unsigned);
                   Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;


platform: ARM
mnem: VAND
description:
Vector Bitwise AND (immediate) performs a bitwise AND between a register value and an immediate value, and       (F8.1.34)
returns the result into the destination vector

This instruction is an alias of the VBIC (immediate) instruction. This means that:

.      The encodings in this description are named to match the encodings of VBIC (immediate).

.      The description of VBIC (immediate) gives the operational pseudocode for this instruction.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18        16 15      12 11            8 7 6 5 4 3            0
   1 1 1 1 0 0 1 i 1 D 0 0 0                  imm3         Vd         cmode       0 Q 1 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VAND{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>

is equivalent to

VBIC{<c>}{<q>}.<dt> <Dd>, #~<imm>

and is never the preferred disassembly.

128-bit SIMD vector variant

Applies when Q = 1.

VAND{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>

is equivalent to

VBIC{<c>}{<q>}.<dt> <Qd>, #~<imm>

and is never the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2                0 15       12 11            8 7 6 5 4 3            0
   1 1 1 i 1 1 1 1 1 D 0 0 0                  imm3         Vd         cmode       0 Q 1 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VAND{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>

is equivalent to

VBIC{<c>}{<q>}.<dt> <Dd>, #~<imm>

and is never the preferred disassembly.

128-bit SIMD vector variant

Applies when Q = 1.

VAND{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>
        is equivalent to

        VBIC{<c>}{<q>}.<dt> <Qd>, #~<imm>

        and is never the preferred disassembly.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VORR instruction must be
                          unconditional. ARM strongly recommends that a T32 VORR instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              The data type used for <imm>. It can be either I16 or I32. I8, I64, and F32 are also permitted, but the
                          resulting syntax is a pseudo-instruction.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <imm>             Is a constant of the type specified by <dt> that is replicated to fill the destination register. For details
                          of the range of constants available and the encoding of <dt> and <imm>, see One register and a
                          modified immediate value on page F5-2596.


        Operation for all encodings

        The description of VBIC (immediate) gives the operational pseudocode for this instruction.


platform: ARM
mnem: VBIC
description:
Vector Bitwise Bit Clear (immediate) performs a bitwise AND between a register value and the complement of an       (F8.1.36)
immediate value, and returns the result into the destination vector.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.

This instruction is used by the alias VAND (immediate). See the Alias conditions on page F8-3328 table for details
of when each alias is preferred.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18        16 15       12 11           8 7 6 5 4 3            0
   1 1 1 1 0 0 1 i 1 D 0 0 0                  imm3         Vd         cmode       0 Q 1 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VBIC{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIC{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>


Decode for all variants of this encoding

 if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
 if Q == '1' && Vd<0> == '1' then UNDEFINED;
 imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4);
 d = UInt(D:Vd);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2                 0 15       12 11           8 7 6 5 4 3            0
   1 1 1 i 1 1 1 1 1 D 0 0 0                  imm3         Vd         cmode       0 Q 1 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VBIC{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIC{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>
        Decode for all variants of this encoding

         if cmode<0> == '0' || cmode<3:2> == '11' then SEE "Related encodings";
         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4);
         d = UInt(D:Vd);      regs = if Q == '0' then 1 else 2;


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Alias conditions


                               Alias                     is preferred when

                               VAND (immediate)          Never



        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VBIC instruction must be
                          unconditional. ARM strongly recommends that a T32 VBIC instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              The data type used for <imm>. It can be either I16 or I32. I8, I64, and F32 are also permitted, but the
                          resulting syntax is a pseudo-instruction.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <imm>             Is a constant of the type specified by <dt> that is replicated to fill the destination register. For details
                          of the range of constants available and the encoding of <dt> and <imm>, see One register and a
                          modified immediate value on page F5-2596.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   D[d+r] = D[d+r] AND NOT(imm64);


platform: ARM
mnem: VBIF
description:
Vector Bitwise Insert if False inserts each bit from the first source register into the destination register if the       (F8.1.38)
corresponding bit of the second source register is 0, otherwise leaves the bit in the destination register unchanged.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 1 0 D 1 1                    Vn            Vd       0 0 0 1 N Q M 1                Vm
                                    op


64-bit SIMD vector variant

Applies when Q = 0.

VBIF{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIF{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
 if op == '10' then operation = VBitOps_VBIT;
 if op == '11' then operation = VBitOps_VBIF;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 1 1 1 1 0 D 1 1                    Vn            Vd       0 0 0 1 N Q M 1                Vm
                                    op


64-bit SIMD vector variant

Applies when Q = 0.

VBIF{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIF{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
         if op == '10' then operation = VBitOps_VBIT;
         if op == '11' then operation = VBitOps_VBIF;
         d = UInt(D:Vd);      n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VBIF, VBIT, or VBSL instruction must
                          be unconditional. ARM strongly recommends that a T32 VBIF, VBIT, or VBSL instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              An optional data type. It is ignored by assemblers, and does not affect the encoding.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL};

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   case operation of
                        when VBitOps_VBIF    D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]));
                        when VBitOps_VBIT    D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]));
                        when VBitOps_VBSL    D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));


platform: ARM
mnem: VBIT
description:
Vector Bitwise Insert if True inserts each bit from the first source register into the destination register if the       (F8.1.39)
corresponding bit of the second source register is 1, otherwise leaves the bit in the destination register unchanged.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 1 0 D 1 0                    Vn           Vd       0 0 0 1 N Q M 1                Vm




64-bit SIMD vector variant

Applies when Q = 0.

VBIT{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIT{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
 if op == '10' then operation = VBitOps_VBIT;
 if op == '11' then operation = VBitOps_VBIF;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 1 1 1 1 0 D 1 0                    Vn           Vd       0 0 0 1 N Q M 1                Vm




64-bit SIMD vector variant

Applies when Q = 0.

VBIT{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBIT{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
         if op == '10' then operation = VBitOps_VBIT;
         if op == '11' then operation = VBitOps_VBIF;
         d = UInt(D:Vd);      n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VBIF, VBIT, or VBSL instruction must
                          be unconditional. ARM strongly recommends that a T32 VBIF, VBIT, or VBSL instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              An optional data type. It is ignored by assemblers, and does not affect the encoding.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL};

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   case operation of
                        when VBitOps_VBIF    D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]));
                        when VBitOps_VBIT    D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]));
                        when VBitOps_VBSL    D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));


platform: ARM
mnem: VBSL
description:
Vector Bitwise Select sets each bit in the destination to the corresponding bit from the first source operand when       (F8.1.40)
the original destination bit was 1, otherwise from the second source operand.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 1 0 D 0 1                    Vn           Vd       0 0 0 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VBSL{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBSL{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
 if op == '10' then operation = VBitOps_VBIT;
 if op == '11' then operation = VBitOps_VBIF;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 1 1 1 1 0 D 0 1                    Vn           Vd       0 0 0 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VBSL{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VBSL{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if op == '00' then SEE VEOR;
 if op == '01' then operation = VBitOps_VBSL;
         if op == '10' then operation = VBitOps_VBIT;
         if op == '11' then operation = VBitOps_VBIF;
         d = UInt(D:Vd);      n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VBIF, VBIT, or VBSL instruction must
                          be unconditional. ARM strongly recommends that a T32 VBIF, VBIT, or VBSL instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              An optional data type. It is ignored by assemblers, and does not affect the encoding.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VBitOps {VBitOps_VBIF, VBitOps_VBIT, VBitOps_VBSL};

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   case operation of
                        when VBitOps_VBIF    D[d+r] = (D[d+r] AND D[m+r]) OR (D[n+r] AND NOT(D[m+r]));
                        when VBitOps_VBIT    D[d+r] = (D[n+r] AND D[m+r]) OR (D[d+r] AND NOT(D[m+r]));
                        when VBitOps_VBSL    D[d+r] = (D[n+r] AND D[d+r]) OR (D[m+r] AND NOT(D[d+r]));


platform: ARM
mnem: VCEQ
description:
Vector Compare Equal to Zero takes each element in a vector, and compares it with zero. If it is equal to zero, the       (F8.1.41)
corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

The operand vector elements can be any one of:

.      8-bit, 16-bit, or 32-bit integers. There is no distinction between signed and unsigned integers.

.      32-bit floating-point numbers.

The result vector elements are fields the same size as the operand vector elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15              12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                          Vd       0 F 0 1 0 Q M 0               Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCEQ{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


128-bit SIMD vector variant

Applies when Q = 1.

VCEQ{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 floating_point = (F == '1');
 esize = 8 << UInt(size);       elements = 64 DIV esize;
 d = UInt(D:Vd);     m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                        12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                          Vd       0 F 0 1 0 Q M 0               Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCEQ{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


128-bit SIMD vector variant

Applies when Q = 1.
        VCEQ{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         floating_point = (F == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VCEQ instruction must be
                          unconditional. ARM strongly recommends that a T32 VCEQ instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "F:size" field. It can have the
                          following values:

                          I8           when F = 0, size = 00

                          I16          when F = 0, size = 01

                          I32          when F = 0, size = 10

                          F32          when F = 1, size = 10

                          It is RESERVED when:

                          .      F = 0, size = 11.

                          .      F = 1, size = 0x.

                          .      F = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        if floating_point then
                             bits(esize) zero = FPZero('0');
                             test_passed = FPCompareEQ(Elem[D[m+r],e,esize], zero, StandardFPSCRValue());
                        else
                             test_passed = (Elem[D[m+r],e,esize] == Zeros(esize));
                        Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VCGE
description:
        Vector Compare Greater Than or Equal to Zero takes each element in a vector, and compares it with zero. If it is       (F8.1.43)
        greater than or equal to zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is
        set to all zeros.

        The operand vector elements can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       32-bit floating-point numbers.

        The result vector elements are fields the same size as the operand vector elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                       Vd      0 F 0 0 1 Q M 0                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCGE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCGE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         floating_point = (F == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                       Vd      0 F 0 0 1 Q M 0                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCGE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.
VCGE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 floating_point = (F == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VCGE instruction must be
              unconditional. ARM strongly recommends that a T32 VCGE instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "F:size" field. It can have the
              following values:

              S8           when F = 0, size = 00

              S16          when F = 0, size = 01

              S32          when F = 0, size = 10

              F32          when F = 1, size = 10

              It is RESERVED when:

              .      F = 0, size = 11.

              .      F = 1, size = 0x.

              .      F = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             if floating_point then
                 bits(esize) zero = FPZero('0');
                 test_passed = FPCompareGE(Elem[D[m+r],e,esize], zero, StandardFPSCRValue());
             else
                 test_passed = (SInt(Elem[D[m+r],e,esize]) >= 0);
             Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VCGT
description:
        Vector Compare Greater Than Zero takes each element in a vector, and compares it with zero. If it is greater than       (F8.1.45)
        zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

        The operand vector elements can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       32-bit floating-point numbers.

        The result vector elements are fields the same size as the operand vector elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                       Vd       0 F 0 0 0 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCGT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCGT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         floating_point = (F == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                       Vd       0 F 0 0 0 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCGT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.
VCGT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 floating_point = (F == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VCGT instruction must be
              unconditional. ARM strongly recommends that a T32 VCGT instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "F:size" field. It can have the
              following values:

              S8           when F = 0, size = 00

              S16          when F = 0, size = 01

              S32          when F = 0, size = 10

              F32          when F = 1, size = 10

              It is RESERVED when:

              .      F = 0, size = 11.

              .      F = 1, size = 0x.

              .      F = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             if floating_point then
                 bits(esize) zero = FPZero('0');
                 test_passed = FPCompareGT(Elem[D[m+r],e,esize], zero, StandardFPSCRValue());
             else
                 test_passed = (SInt(Elem[D[m+r],e,esize]) > 0);
             Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VCLE
description:
        Vector Compare Less Than or Equal to Zero takes each element in a vector, and compares it with zero. If it is less       (F8.1.47)
        than or equal to zero, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all
        zeros.

        The operand vector elements can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       32-bit floating-point numbers.

        The result vector elements are fields the same size as the operand vector elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                       Vd      0 F 0 1 1 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCLE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCLE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         floating_point = (F == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                       Vd      0 F 0 1 1 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCLE{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


        128-bit SIMD vector variant

        Applies when Q = 1.
VCLE{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 floating_point = (F == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VCLE instruction must be
              unconditional. ARM strongly recommends that a T32 VCLE instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "F:size" field. It can have the
              following values:

              S8           when F = 0, size = 00

              S16          when F = 0, size = 01

              S32          when F = 0, size = 10

              F32          when F = 1, size = 10

              It is RESERVED when:

              .      F = 0, size = 11.

              .      F = 1, size = 0x.

              .      F = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             if floating_point then
                 bits(esize) zero = FPZero('0');
                 test_passed = FPCompareGE(zero, Elem[D[m+r],e,esize], StandardFPSCRValue());
             else
                 test_passed = (SInt(Elem[D[m+r],e,esize]) <= 0);
             Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VCLS
description:
Vector Count Leading Sign Bits counts the number of consecutive bits following the topmost bit, that are the same       (F8.1.49)
as the topmost bit, in each element in a vector, and places the results in a second vector. The count does not include
the topmost bit itself.

The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit signed integers.

The result vector elements are the same data type as the operand vector elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                        Vd        0 1 0 0 0 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCLS{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VCLS{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                        Vd        0 1 0 0 0 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCLS{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VCLS{<c>}{<q>}.<dt> <Qd>, <Qm>
        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VCLS instruction must be
                          unconditional. ARM strongly recommends that a T32 VCLS instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "size" field. It can have the
                          following values:

                          S8           when size = 00

                          S16          when size = 01

                          S32          when size = 10

                          It is RESERVED when size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        Elem[D[d+r],e,esize] = CountLeadingSignBits(Elem[D[m+r],e,esize])<esize-1:0>;


platform: ARM
mnem: VCLT
description:
Vector Compare Less Than Zero takes each element in a vector, and compares it with zero. If it is less than zero,       (F8.1.50)
the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros.

The operand vector elements can be any one of:

.      8-bit, 16-bit, or 32-bit signed integers.

.      32-bit floating-point numbers.

The result vector elements are fields the same size as the operand vector elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                    0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                        Vd         0 F 1 0 0 Q M 0               Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCLT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


128-bit SIMD vector variant

Applies when Q = 1.

VCLT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 floating_point = (F == '1');
 esize = 8 << UInt(size);      elements = 64 DIV esize;
 d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9 8 7 6 5 4 3                    0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                        Vd         0 F 1 0 0 Q M 0               Vm




64-bit SIMD vector variant

Applies when Q = 0.

VCLT{<c>}{<q>}.<dt> {<Dd>,} <Dm>, #0


128-bit SIMD vector variant

Applies when Q = 1.
        VCLT{<c>}{<q>}.<dt> {<Qd>,} <Qm>, #0


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         floating_point = (F == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VCLT instruction must be
                          unconditional. ARM strongly recommends that a T32 VCLT instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "F:size" field. It can have the
                          following values:

                          S8           when F = 0, size = 00

                          S16          when F = 0, size = 01

                          S32          when F = 0, size = 10

                          F32          when F = 1, size = 10

                          It is RESERVED when:

                          .      F = 0, size = 11.

                          .      F = 1, size = 0x.

                          .      F = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        if floating_point then
                             bits(esize) zero = FPZero('0');
                             test_passed = FPCompareGT(zero, Elem[D[m+r],e,esize], StandardFPSCRValue());
                        else
                             test_passed = (SInt(Elem[D[m+r],e,esize]) < 0);
                        Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);


platform: ARM
mnem: VCLZ
description:
        Vector Count Leading Zeros counts the number of consecutive zeros, starting from the most significant bit, in each       (F8.1.52)
        element in a vector, and places the results in a second vector.

        The operand vector elements can be any one of 8-bit, 16-bit, or 32-bit integers. There is no distinction between
        signed and unsigned integers.

        The result vector elements are the same data type as the operand vector elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 1 0 0 1 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 1 0 0 1 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCLZ{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCLZ{<c>}{<q>}.<dt> <Qd>, <Qm>
Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VCLZ instruction must be
              unconditional. ARM strongly recommends that a T32 VCLZ instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              I8           when size = 00

              I16          when size = 01

              I32          when size = 10

              It is RESERVED when size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             Elem[D[d+r],e,esize] = CountLeadingZeroBits(Elem[D[m+r],e,esize])<esize-1:0>;


platform: ARM
mnem: VCMP
description:
        Vector Compare compares two floating-point registers, or one floating-point register and zero. It writes the result       (F8.1.53)
        to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C, V} Condition flags by a subsequent
        VMRS instruction.

        It raises an Invalid Operation exception only if either operand is a signaling NaN.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15         12 11 10 9 8 7 6 5 4 3               0
              !=1111     1 1 1 0 1 D 1 1 0 1 0 0                   Vd       1 0 1 sz 0 1 M 0           Vm
               cond                                                                     E


        Single-precision scalar variant

        Applies when sz = 0.

        VCMP{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VCMP{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         dp_operation = (sz == '1');     quiet_nan_exc = (E == '1');     with_zero = FALSE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        A2


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15         12 11 10 9 8 7 6 5 4 3 2 1 0
              !=1111     1 1 1 0 1 D 1 1 0 1 0 1                   Vd       1 0 1 sz 0 1 (0) 0 (0) (0) (0) (0)
               cond                                                                     E


        Single-precision scalar variant

        Applies when sz = 0.

        VCMP{<c>}{<q>}.F32 <Sd>, #0.0


        Double-precision scalar variant

        Applies when sz = 1.

        VCMP{<c>}{<q>}.F64 <Dd>, #0.0


        Decode for all variants of this encoding

         dp_operation = (sz == '1');     quiet_nan_exc = (E == '1');     with_zero = TRUE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                  12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 0 1 1 1 0 1 D 1 1 0 1 0 0                      Vd         1 0 1 sz 0 1 M 0             Vm
                                                                                E


Single-precision scalar variant

Applies when sz = 0.

VCMP{<c>}{<q>}.F32 <Sd>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VCMP{<c>}{<q>}.F64 <Dd>, <Dm>


Decode for all variants of this encoding

 dp_operation = (sz == '1');   quiet_nan_exc = (E == '1');     with_zero = FALSE;
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                  12 11 10 9 8 7 6 5 4 3 2 1 0
  1 1 1 0 1 1 1 0 1 D 1 1 0 1 0 1                      Vd         1 0 1 sz 0 1 (0) 0 (0) (0) (0) (0)
                                                                                E


Single-precision scalar variant

Applies when sz = 0.

VCMP{<c>}{<q>}.F32 <Sd>, #0.0


Double-precision scalar variant

Applies when sz = 1.

VCMP{<c>}{<q>}.F64 <Dd>, #0.0


Decode for all variants of this encoding

 dp_operation = (sz == '1');   quiet_nan_exc = (E == '1');     with_zero = TRUE;
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506.

<q>            See Standard assembler syntax fields on page F2-2506.

<Sd>           Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>           Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        NaNs

        The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either
        or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 ==
        Operand2) and (Operand1 > Operand2) are false. This results in the FPSCR flags being set as N=0, Z=0, C=1 and
        V=1.

        VCMPE raises an Invalid Operation exception if either operand is any type of NaN, and is suitable for testing for <,
        <=, >, >=, and other predicates that raise an exception when the operands are unordered.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();     CheckVFPEnabled(TRUE);
               if dp_operation then
                   bits(64) op64 = if with_zero then FPZero('0') else D[m];
                   FPSCR.<N,Z,C,V> = FPCompare(D[d], op64, quiet_nan_exc, FPSCR);
               else
                   bits(32) op32 = if with_zero then FPZero('0') else S[m];
                   FPSCR.<N,Z,C,V> = FPCompare(S[d], op32, quiet_nan_exc, FPSCR);


platform: ARM
mnem: VCMPE
description:
Vector Compare, raising Invalid Operation on NaN compares two floating-point registers, or one floating-point       (F8.1.54)
register and zero. It writes the result to the FPSCR flags. These are normally transferred to the PSTATE.{N, Z, C,
V} Condition flags by a subsequent VMRS instruction.

It raises an Invalid Operation exception if either operand is any type of NaN, or if either operand is a signaling NaN.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


   31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                    0
      !=1111    1 1 1 0 1 D 1 1 0 1 0 0                     Vd        1 0 1 sz 1 1 M 0             Vm
       cond                                                                         E


Single-precision scalar variant

Applies when sz = 0.

VCMPE{<c>}{<q>}.F32 <Sd>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VCMPE{<c>}{<q>}.F64 <Dd>, <Dm>


Decode for all variants of this encoding

 dp_operation = (sz == '1');      quiet_nan_exc = (E == '1');      with_zero = FALSE;
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


A2


   31        28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3 2 1 0
      !=1111    1 1 1 0 1 D 1 1 0 1 0 1                     Vd        1 0 1 sz 1 1 (0) 0 (0) (0) (0) (0)
       cond                                                                         E


Single-precision scalar variant

Applies when sz = 0.

VCMPE{<c>}{<q>}.F32 <Sd>, #0.0


Double-precision scalar variant

Applies when sz = 1.

VCMPE{<c>}{<q>}.F64 <Dd>, #0.0


Decode for all variants of this encoding

 dp_operation = (sz == '1');      quiet_nan_exc = (E == '1');      with_zero = TRUE;
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3               0
            1 1 1 0 1 1 1 0 1 D 1 1 0 1 0 0                       Vd        1 0 1 sz 1 1 M 0          Vm
                                                                                      E


        Single-precision scalar variant

        Applies when sz = 0.

        VCMPE{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VCMPE{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         dp_operation = (sz == '1');      quiet_nan_exc = (E == '1');    with_zero = FALSE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3 2 1 0
            1 1 1 0 1 1 1 0 1 D 1 1 0 1 0 1                       Vd        1 0 1 sz 1 1 (0) 0 (0) (0) (0) (0)
                                                                                      E


        Single-precision scalar variant

        Applies when sz = 0.

        VCMPE{<c>}{<q>}.F32 <Sd>, #0.0


        Double-precision scalar variant

        Applies when sz = 1.

        VCMPE{<c>}{<q>}.F64 <Dd>, #0.0


        Decode for all variants of this encoding

         dp_operation = (sz == '1');      quiet_nan_exc = (E == '1');    with_zero = TRUE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sm>              Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.
<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>            Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


NaNs

The IEEE 754 standard specifies that the result of a comparison is precisely one of <, ==, > or unordered. If either
or both of the operands are NaNs, they are unordered, and all three of (Operand1 < Operand2), (Operand1 ==
Operand2) and (Operand1 > Operand2) are false. This results in the FPSCR flags being set as N=0, Z=0, C=1 and
V=1.

VCMPE raises an Invalid Operation exception if either operand is any type of NaN, and is suitable for testing for <,
<=, >, >=, and other predicates that raise an exception when the operands are unordered.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();      CheckVFPEnabled(TRUE);
     if dp_operation then
          bits(64) op64 = if with_zero then FPZero('0') else D[m];
          FPSCR.<N,Z,C,V> = FPCompare(D[d], op64, quiet_nan_exc, FPSCR);
     else
          bits(32) op32 = if with_zero then FPZero('0') else S[m];
          FPSCR.<N,Z,C,V> = FPCompare(S[d], op32, quiet_nan_exc, FPSCR);


platform: ARM
mnem: VCNT
description:
        Vector Count Set Bits counts the number of bits that are one in each element in a vector, and places the results in a       (F8.1.55)
        second vector.

        The operand vector elements must be 8-bit fields.

        The result vector elements are 8-bit integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 1 0 1 0 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCNT{<c>}{<q>}.8 <Dd>, <Dm>// Encoded as Q = 0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCNT{<c>}{<q>}.8 <Qd>, <Qm>// Encoded as Q = 1


        Decode for all variants of this encoding

         if size != '00' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8;     elements = 8;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 1 0 1 0 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VCNT{<c>}{<q>}.8 <Dd>, <Dm>// Encoded as Q = 0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCNT{<c>}{<q>}.8 <Qd>, <Qm>// Encoded as Q = 1
Decode for all variants of this encoding

 if size != '00' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8; elements = 8;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VCNT instruction must be
              unconditional. ARM strongly recommends that a T32 VCNT instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();   CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             Elem[D[d+r],e,esize] = BitCount(Elem[D[m+r],e,esize])<esize-1:0>;


platform: ARM
mnem: VCVT
description:
        Convert between double-precision and single-precision does one of the following:       (F8.1.56)

        .       Converts the value in a double-precision register to single-precision and writes the result to a single-precision
                register.

        .       Converts the value in a single-precision register to double-precision and writes the result to a
                double-precision register.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                   0
              !=1111     1 1 1 0 1 D 1 1 0 1 1 1                     Vd      1 0 1 sz 1 1 M 0                Vm
               cond


        Encoding

        Applies when sz = 0.

        VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm>


        Encoding

        Applies when sz = 1.

        VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm>


        Decode for all variants of this encoding

         double_to_single = (sz == '1');
         d = if double_to_single then UInt(Vd:D) else UInt(D:Vd);
         m = if double_to_single then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                       12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 0 1 D 1 1 0 1 1 1                          Vd      1 0 1 sz 1 1 M 0                Vm




        Encoding

        Applies when sz = 0.

        VCVT{<c>}{<q>}.F64.F32 <Dd>, <Sm>


        Encoding

        Applies when sz = 1.

        VCVT{<c>}{<q>}.F32.F64 <Sd>, <Dm>


        Decode for all variants of this encoding

         double_to_single = (sz == '1');
         d = if double_to_single then UInt(Vd:D) else UInt(D:Vd);
         m = if double_to_single then UInt(M:Vm) else UInt(Vm:M);
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Sm>          Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckVFPEnabled(TRUE);
    if double_to_single then
        S[d] = FPConvert(D[m], FPSCR);
    else
        D[d] = FPConvert(S[m], FPSCR);


platform: ARM
mnem: VCVTA
description:
Vector Convert floating-point to integer with Round to Nearest with Ties to Away converts each element in a vector       (F8.1.63)
from floating-point to integer using the Round to Nearest with Ties to Away rounding mode, and places the results
in a second vector.

The operand vector elements must be 32-bit floating-point numbers.

The result vector elements are 32-bit integers. Signed and unsigned integers are distinct.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                       Vd        0 0 0 0 op Q M 0             Vm
                                                                            RM


64-bit SIMD vector variant

Applies when Q = 0.

VCVTA{<q>}.<dt>.F32 <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VCVTA{<q>}.<dt>.F32 <Qd>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 rounding = FPDecodeRM(RM);     unsigned = (op == '1');
 esize = 32;   elements = 2;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                       Vd        0 0 0 0 op Q M 0             Vm
                                                                            RM


64-bit SIMD vector variant

Applies when Q = 0.

VCVTA{<q>}.<dt>.F32 <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VCVTA{<q>}.<dt>.F32 <Qd>, <Qm>
        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPDecodeRM(RM);       unsigned = (op == '1');
         esize = 32;     elements = 2;
         d = UInt(D:Vd);      m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        Assembler symbols

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              For encoding A1: is the data type for the elements of the destination, encoded in the "op" field. It
                          can have the following values:

                          S32         when op = 0

                          U32         when op = 1

                          For encoding T1: is the data type for the elements of the destination, encoded in the "op" field. It
                          can have the following values:

                          S32         when op = 0

                          U32         when op = 1

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         EncodingSpecificOperations(); CheckAdvSIMDEnabled();
         bits(esize) result;
         for r = 0 to regs-1
               for e = 0 to elements-1
                   Elem[D[d+r],e,esize] = FPToFixed(Elem[D[m+r],e,esize], 0, unsigned,
                                                        StandardFPSCRValue(), rounding);


platform: ARM
mnem: VCVTB
description:
Convert to or from a half-precision value in the bottom half of a single-precision register does one of the following:       (F8.1.65)

.     Converts the half-precision value in the bottom half of a single-precision register to single-precision and
      writes the result to a single-precision register.

.     Converts the half-precision value in the bottom half of a single-precision register to double-precision and
      writes the result to a double-precision register.

.     Converts the single-precision value in a single-precision register to half-precision and writes the result into
      the bottom half of a single-precision register, preserving the other half of the destination register.

.     Converts the double-precision value in a double-precision register to half-precision and writes the result into
      the bottom half of a single-precision register, preserving the other half of the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31       28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                  0
    !=1111     1 1 1 0 1 D 1 1 0 0 1 op                   Vd         1 0 1 sz 0 1 M 0             Vm
     cond                                                                          T


Encoding

Applies when op = 0 && sz = 0.

VCVTB{<c>}{<q>}.F32.F16 <Sd>, <Sm>


Encoding

Applies when op = 0 && sz = 1.

VCVTB{<c>}{<q>}.F64.F16 <Dd>, <Sm>


Encoding

Applies when op = 1 && sz = 0.

VCVTB{<c>}{<q>}.F16.F32 <Sd>, <Sm>


Encoding

Applies when op = 1 && sz = 1.

VCVTB{<c>}{<q>}.F16.F64 <Sd>, <Dm>


Decode for all variants of this encoding

 uses_double = (sz == '1'); convert_from_half = (op == '0');
 lowbit = (if T == '1' then 16 else 0);
 if uses_double then
    if convert_from_half then
         d = UInt(D:Vd); m = UInt(Vm:M);
    else
         d = UInt(Vd:D); m = UInt(M:Vm);
 else
    d = UInt(Vd:D); m = UInt(Vm:M);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3               0
            1 1 1 0 1 1 1 0 1 D 1 1 0 0 1 op                      Vd        1 0 1 sz 0 1 M 0          Vm
                                                                                      T


        Encoding

        Applies when op = 0 && sz = 0.

        VCVTB{<c>}{<q>}.F32.F16 <Sd>, <Sm>


        Encoding

        Applies when op = 0 && sz = 1.

        VCVTB{<c>}{<q>}.F64.F16 <Dd>, <Sm>


        Encoding

        Applies when op = 1 && sz = 0.

        VCVTB{<c>}{<q>}.F16.F32 <Sd>, <Sm>


        Encoding

        Applies when op = 1 && sz = 1.

        VCVTB{<c>}{<q>}.F16.F64 <Sd>, <Dm>


        Decode for all variants of this encoding

         uses_double = (sz == '1'); convert_from_half = (op == '0');
         lowbit = (if T == '1' then 16 else 0);
         if uses_double then
               if convert_from_half then
                   d = UInt(D:Vd); m = UInt(Vm:M);
               else
                   d = UInt(Vd:D); m = UInt(M:Vm);
         else
               d = UInt(Vd:D); m = UInt(Vm:M);


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Sm>              Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
               bits(16) hp;
               if convert_from_half then
                   hp = S[m]<lowbit+15:lowbit>;
                   if uses_double then
         D[d] = FPConvert(hp, FPSCR);
      else
         S[d] = FPConvert(hp, FPSCR);
   else
      if uses_double then
         hp = FPConvert(D[m], FPSCR);
      else
         hp = FPConvert(S[m], FPSCR);
      S[d]<lowbit+15:lowbit> = hp;


platform: ARM
mnem: VCVTM
description:
        Vector Convert floating-point to integer with Round towards -Infinity converts each element in a vector from       (F8.1.66)
        floating-point to integer using the Round towards -Infinity rounding mode, and places the results in a second vector.

        The operand vector elements must be 32-bit floating-point numbers.

        The result vector elements are 32-bit integers. Signed and unsigned integers are distinct.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                      Vd       0 0 1 1 op Q M 0             Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTM{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTM{<q>}.<dt>.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPDecodeRM(RM);      unsigned = (op == '1');
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                      Vd       0 0 1 1 op Q M 0             Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTM{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTM{<q>}.<dt>.F32 <Qd>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 rounding = FPDecodeRM(RM);   unsigned = (op == '1');
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          For encoding A1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

              For encoding T1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 bits(esize) result;
 for r = 0 to regs-1
     for e = 0 to elements-1
         Elem[D[d+r],e,esize] = FPToFixed(Elem[D[m+r],e,esize], 0, unsigned,
                                            StandardFPSCRValue(), rounding);


platform: ARM
mnem: VCVTN
description:
        Vector Convert floating-point to integer with Round to Nearest converts each element in a vector from       (F8.1.68)
        floating-point to integer using the Round to Nearest rounding mode, and places the results in a second vector.

        The operand vector elements must be 32-bit floating-point numbers.

        The result vector elements are 32-bit integers. Signed and unsigned integers are distinct.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                      Vd       0 0 0 1 op Q M 0            Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTN{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTN{<q>}.<dt>.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPDecodeRM(RM);      unsigned = (op == '1');
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                      Vd       0 0 0 1 op Q M 0            Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTN{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTN{<q>}.<dt>.F32 <Qd>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 rounding = FPDecodeRM(RM);   unsigned = (op == '1');
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          For encoding A1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

              For encoding T1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 bits(esize) result;
 for r = 0 to regs-1
     for e = 0 to elements-1
         Elem[D[d+r],e,esize] = FPToFixed(Elem[D[m+r],e,esize], 0, unsigned,
                                            StandardFPSCRValue(), rounding);


platform: ARM
mnem: VCVTP
description:
        Vector Convert floating-point to integer with Round towards +Infinity converts each element in a vector from       (F8.1.70)
        floating-point to integer using the Round towards +Infinity rounding mode, and places the results in a second vector.

        The operand vector elements must be 32-bit floating-point numbers.

        The result vector elements are 32-bit integers. Signed and unsigned integers are distinct.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                      Vd       0 0 1 0 op Q M 0             Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTP{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTP{<q>}.<dt>.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPDecodeRM(RM);      unsigned = (op == '1');
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                      Vd       0 0 1 0 op Q M 0             Vm
                                                                                 RM


        64-bit SIMD vector variant

        Applies when Q = 0.

        VCVTP{<q>}.<dt>.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VCVTP{<q>}.<dt>.F32 <Qd>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 rounding = FPDecodeRM(RM);   unsigned = (op == '1');
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          For encoding A1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

              For encoding T1: is the data type for the elements of the destination, encoded in the "op" field. It
              can have the following values:

              S32         when op = 0

              U32         when op = 1

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 bits(esize) result;
 for r = 0 to regs-1
     for e = 0 to elements-1
         Elem[D[d+r],e,esize] = FPToFixed(Elem[D[m+r],e,esize], 0, unsigned,
                                            StandardFPSCRValue(), rounding);


platform: ARM
mnem: VCVTR
description:
        Convert floating-point to integer converts a value in a register from floating-point to a 32-bit integer, using the       (F8.1.72)
        rounding mode specified by the FPSCR and places the result in a second register.

        VCVT (between floating-point and fixed-point, floating-point) describes conversions between floating-point and
        16-bit integers.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19 18     16 15         12 11 10 9 8 7 6 5 4 3                  0
              !=1111     1 1 1 0 1 D 1 1 1 1 0 x                  Vd        1 0 1 sz 0 1 M 0              Vm
               cond                                  opc2                               op


        Single-precision scalar variant

        Applies when opc2 = 100 && sz = 0.

        VCVTR{<c>}{<q>}.U32.F32 <Sd>, <Sm>


        Single-precision scalar variant

        Applies when opc2 = 101 && sz = 0.

        VCVTR{<c>}{<q>}.S32.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when opc2 = 100 && sz = 1.

        VCVTR{<c>}{<q>}.U32.F64 <Sd>, <Dm>


        Double-precision scalar variant

        Applies when opc2 = 101 && sz = 1.

        VCVTR{<c>}{<q>}.S32.F64 <Sd>, <Dm>


        Decode for all variants of this encoding

         if opc2 != '000' && opc2 != '10x' then SEE "Related encodings";
         to_integer = (opc2<2> == '1');     dp_operation = (sz == '1');
         if to_integer then
               unsigned = (opc2<0> == '0');
               rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
               d = UInt(Vd:D);  m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
         else
               unsigned = (op == '0');
               rounding = FPRoundingMode(FPSCR);
               m = UInt(Vm:M);  d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2               0 15         12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 0 1 1 1 0 1 D 1 1 1 1 0 x                       Vd        1 0 1 sz 0 1 M 0              Vm
                                                     opc2                               op
Single-precision scalar variant

Applies when opc2 = 100 && sz = 0.

VCVTR{<c>}{<q>}.U32.F32 <Sd>, <Sm>


Single-precision scalar variant

Applies when opc2 = 101 && sz = 0.

VCVTR{<c>}{<q>}.S32.F32 <Sd>, <Sm>


Double-precision scalar variant

Applies when opc2 = 100 && sz = 1.

VCVTR{<c>}{<q>}.U32.F64 <Sd>, <Dm>


Double-precision scalar variant

Applies when opc2 = 101 && sz = 1.

VCVTR{<c>}{<q>}.S32.F64 <Sd>, <Dm>


Decode for all variants of this encoding

 if opc2 != '000' && opc2 != '10x' then SEE "Related encodings";
 to_integer = (opc2<2> == '1');   dp_operation = (sz == '1');
 if to_integer then
     unsigned = (opc2<0> == '0');
     rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
     d = UInt(Vd:D);  m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
 else
     unsigned = (op == '0');
     rounding = FPRoundingMode(FPSCR);
     m = UInt(Vm:M);  d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);


Notes for all encodings

Related encodings: Floating-point data-processing instructions on page F5-2599.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>          Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();   CheckVFPEnabled(TRUE);
     if to_integer then
         if dp_operation then
            S[d] = FPToFixed(D[m], 0, unsigned, FPSCR, rounding);
         else
            S[d] = FPToFixed(S[m], 0, unsigned, FPSCR, rounding);
     else
         if dp_operation then
                        D[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);
                   else
                        S[d] = FixedToFP(S[m], 0, unsigned, FPSCR, rounding);


platform: ARM
mnem: VCVTT
description:
Convert to or from a half-precision value in the top half of a single-precision register does one of the following:       (F8.1.73)

.     Converts the half-precision value in the top half of a single-precision register to single-precision and writes
      the result to a single-precision register.

.     Converts the half-precision value in the top half of a single-precision register to double-precision and writes
      the result to a double-precision register.

.     Converts the single-precision value in a single-precision register to half-precision and writes the result into
      the top half of a single-precision register, preserving the other half of the destination register.

.     Converts the double-precision value in a double-precision register to half-precision and writes the result into
      the top half of a single-precision register, preserving the other half of the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31       28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                   0
    !=1111     1 1 1 0 1 D 1 1 0 0 1 op                    Vd        1 0 1 sz 1 1 M 0              Vm
     cond                                                                          T


Encoding

Applies when op = 0 && sz = 0.

VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm>


Encoding

Applies when op = 0 && sz = 1.

VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm>


Encoding

Applies when op = 1 && sz = 0.

VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm>


Encoding

Applies when op = 1 && sz = 1.

VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm>


Decode for all variants of this encoding

 uses_double = (sz == '1'); convert_from_half = (op == '0');
 lowbit = (if T == '1' then 16 else 0);
 if uses_double then
    if convert_from_half then
         d = UInt(D:Vd); m = UInt(Vm:M);
    else
         d = UInt(Vd:D); m = UInt(M:Vm);
 else
    d = UInt(Vd:D); m = UInt(Vm:M);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3               0
            1 1 1 0 1 1 1 0 1 D 1 1 0 0 1 op                      Vd        1 0 1 sz 1 1 M 0          Vm
                                                                                      T


        Encoding

        Applies when op = 0 && sz = 0.

        VCVTT{<c>}{<q>}.F32.F16 <Sd>, <Sm>


        Encoding

        Applies when op = 0 && sz = 1.

        VCVTT{<c>}{<q>}.F64.F16 <Dd>, <Sm>


        Encoding

        Applies when op = 1 && sz = 0.

        VCVTT{<c>}{<q>}.F16.F32 <Sd>, <Sm>


        Encoding

        Applies when op = 1 && sz = 1.

        VCVTT{<c>}{<q>}.F16.F64 <Sd>, <Dm>


        Decode for all variants of this encoding

         uses_double = (sz == '1'); convert_from_half = (op == '0');
         lowbit = (if T == '1' then 16 else 0);
         if uses_double then
               if convert_from_half then
                   d = UInt(D:Vd); m = UInt(Vm:M);
               else
                   d = UInt(Vd:D); m = UInt(M:Vm);
         else
               d = UInt(Vd:D); m = UInt(Vm:M);


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Sm>              Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
               bits(16) hp;
               if convert_from_half then
                   hp = S[m]<lowbit+15:lowbit>;
                   if uses_double then
         D[d] = FPConvert(hp, FPSCR);
      else
         S[d] = FPConvert(hp, FPSCR);
   else
      if uses_double then
         hp = FPConvert(D[m], FPSCR);
      else
         hp = FPConvert(S[m], FPSCR);
      S[d]<lowbit+15:lowbit> = hp;


platform: ARM
mnem: VDIV
description:
        Divide divides one floating-point value by another floating-point value and writes the result to a third floating-point       (F8.1.74)
        register.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                    0
              !=1111     1 1 1 0 1 D 0 0             Vn           Vd       1 0 1 sz N 0 M 0               Vm
               cond


        Single-precision scalar variant

        Applies when sz = 0.

        VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                0 15         12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 0 1 1 1 0 1 D 0 0                  Vn           Vd       1 0 1 sz N 0 M 0               Vm




        Single-precision scalar variant

        Applies when sz = 0.

        VDIV{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VDIV{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckVFPEnabled(TRUE);
    if dp_operation then
        D[d] = FPDiv(D[n], D[m], FPSCR);
    else
        S[d] = FPDiv(S[n], S[m], FPSCR);


platform: ARM
mnem: VDUP
description:
        Duplicate general-purpose register to vector duplicates an element from a general-purpose register into every       (F8.1.75)
        element of the destination vector.

        The destination vector elements can be 8-bit, 16-bit, or 32-bit fields. The source element is the least significant 8,
        16, or 32 bits of the general-purpose register. There is no distinction between data types.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31        28 27 26 25 24 23 22 21 20 19         16 15         12 11 10 9 8 7 6 5 4 3 2 1 0
              !=1111     1 1 1 0 1 B Q 0              Vd            Rt       1 0 1 1 D 0 E 1 (0) (0) (0) (0)
               cond


        A1 variant

        VDUP{<c>}{<q>}.<size> <Qd>, <Rt>// Encoded as Q = 1
        VDUP{<c>}{<q>}.<size> <Dd>, <Rt>// Encoded as Q = 0


        Decode for this encoding

         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         d = UInt(D:Vd);     t = UInt(Rt);   regs = if Q == '0' then 1 else 2;
         case B:E of
               when '00'   esize = 32;   elements = 2;
               when '01'   esize = 16;   elements = 4;
               when '10'   esize = 8;    elements = 8;
               when '11'   UNDEFINED;
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
            1 1 1 0 1 1 1 0 1 B Q 0                   Vd            Rt       1 0 1 1 D 0 E 1 (0) (0) (0) (0)




        T1 variant

        VDUP{<c>}{<q>}.<size> <Qd>, <Rt>// Encoded as Q = 1
        VDUP{<c>}{<q>}.<size> <Dd>, <Rt>// Encoded as Q = 0


        Decode for this encoding

         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         d = UInt(D:Vd);     t = UInt(Rt);   regs = if Q == '0' then 1 else 2;
         case B:E of
               when '00'   esize = 32;   elements = 2;
               when '01'   esize = 16;   elements = 4;
               when '10'   esize = 8;    elements = 8;
               when '11'   UNDEFINED;
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. ARM strongly recommends that any VDUP
               instruction is unconditional, see Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size for the elements of the destination vector. It must be one of:

               8           Encoded as [b, e] = 0b10.

               16          Encoded as [b, e] = 0b01.

               32          Encoded as [b, e] = 0b00.

<Qd>           The destination vector for a quadword operation.

<Dd>           The destination vector for a doubleword operation.

<Rt>           The ARM source register.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     scalar = R[t]<esize-1:0>;
     for r = 0 to regs-1
         for e = 0 to elements-1
              Elem[D[d+r],e,esize] = scalar;


platform: ARM
mnem: VEOR
description:
        Vector Bitwise Exclusive OR performs a bitwise Exclusive OR operation between two registers, and places the       (F8.1.77)
        result in the destination register. The operand and result registers can be quadword or doubleword. They must all be
        the same size.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3              0
            1 1 1 1 0 0 1 1 0 D 0 0                    Vn            Vd       0 0 0 1 N Q M 1           Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VEOR{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VEOR{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         d = UInt(D:Vd);     n = UInt(N:Vn);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3              0
            1 1 1 1 1 1 1 1 0 D 0 0                    Vn            Vd       0 0 0 1 N Q M 1           Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VEOR{<c>}{<q>}{.<dt>} {<Dd>,} <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VEOR{<c>}{<q>}{.<dt>} {<Qd>,} <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         d = UInt(D:Vd);     n = UInt(N:Vn);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VEOR instruction must be
              unconditional. ARM strongly recommends that a T32 VEOR instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          An optional data type. It is ignored by assemblers, and does not affect the encoding.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();     CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        D[d+r] = D[n+r] EOR D[m+r];


platform: ARM
mnem: VEXT
description:
        Vector Extract extracts elements from the bottom end of the second operand vector and the top end of the first,       (F8.1.78)
        concatenates them and places the result in the destination vector.

        The elements of the vectors are treated as being 8-bit fields. There is no distinction between data types.

        The following figure shows an example of the operation of VEXT doubleword operation for imm = 3.
                                                                     7 6 5 4 3 2 1 0                7 6 5 4 3 2 1 0
                                                                Vm                              Vn




                                                                                                Vd

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.

        This instruction is used by the alias VEXT (multibyte elements). See the Alias conditions on page F8-3427 table for
        details of when each alias is preferred.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11         8 7 6 5 4 3              0
            1 1 1 1 0 0 1 0 1 D 1 1                   Vn           Vd          imm4      N Q M 0         Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VEXT{<c>}{<q>}.8 {<Dd>,} <Dn>, <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VEXT{<c>}{<q>}.8 {<Qd>,} <Qn>, <Qm>, #<imm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if Q == '0' && imm4<3> == '1' then UNDEFINED;
         quadword_operation = (Q == '1');      position = 8 * UInt(imm4);
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11         8 7 6 5 4 3              0
            1 1 1 0 1 1 1 1 1 D 1 1                   Vn           Vd          imm4      N Q M 0         Vm
64-bit SIMD vector variant

Applies when Q = 0.

VEXT{<c>}{<q>}.8 {<Dd>,} <Dn>, <Dm>, #<imm>


128-bit SIMD vector variant

Applies when Q = 1.

VEXT{<c>}{<q>}.8 {<Qd>,} <Qn>, <Qm>, #<imm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if Q == '0' && imm4<3> == '1' then UNDEFINED;
 quadword_operation = (Q == '1');   position = 8 * UInt(imm4);
 d = UInt(D:Vd);  n = UInt(N:Vn);   m = UInt(M:Vm);


Alias conditions


            Alias                            is preferred when

            VEXT (multibyte elements)        Never



Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VEXT instruction must be
              unconditional. ARM strongly recommends that a T32 VEXT instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         For the 64-bit SIMD vector variant: is the location of the extracted result in the concatenation of the
              operands, as a number of bytes from the least significant end, in the range 0 to 7, encoded in the
              "imm4" field.

              For the 128-bit SIMD vector variant: is the location of the extracted result in the concatenation of
              the operands, as a number of bytes from the least significant end, in the range 0 to 15, encoded in
              the "imm4" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();   CheckAdvSIMDEnabled();
     if quadword_operation then
         Q[d>>1] = (Q[m>>1]:Q[n>>1])<position+127:position>;
     else
         D[d] = (D[m]:D[n])<position+63:position>;


platform: ARM
mnem: VFMA
description:
        Vector Fused Multiply Accumulate multiplies corresponding elements of two vectors, and accumulates the results       (F8.1.80)
        into the elements of the destination vector. The instruction does not round the result of the multiply before the
        accumulation.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 0 D 0 0                   Vn           Vd      1 1 0 0 N Q M 1               Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VFMA{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VFMA{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE; op1_neg = (op == '1'); esize = 32; elements = 2;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
         regs = if Q == '0' then 1 else 2;


        A2


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                  0
              !=1111     1 1 1 0 1 D 1 0              Vn           Vd      1 0 1 sz N 0 M 0              Vm
               cond                                                                        op


        Single-precision scalar variant

        Applies when sz = 0.

        VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE; dp_operation = (sz == '1'); op1_neg = (op == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 0 1 1 1 1 0 D 0 0                Vn          Vd         1 1 0 0 N Q M 1             Vm
                               op sz


64-bit SIMD vector variant

Applies when Q = 0.

VFMA{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VFMA{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE; op1_neg = (op == '1'); esize = 32; elements = 2;
 d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
 regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 0 1 1 1 0 1 D 1 0                Vn          Vd         1 0 1 sz N 0 M 0            Vm
                                                                                op


Single-precision scalar variant

Applies when sz = 0.

VFMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VFMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE; dp_operation = (sz == '1'); op1_neg = (op == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        Assembler symbols

        <c>               For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
                          Advanced SIMD VFMA or VMFS instruction must be unconditional. ARM strongly recommends that a
                          T32 Advanced SIMD VFMA or VMFS instruction is unconditional, see Conditional execution on
                          page F2-2507.

                          For encoding T2: see Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
               if advsimd then // Advanced SIMD instruction
                   for r = 0 to regs-1
                        for e = 0 to elements-1
                             bits(esize) op1 = Elem[D[n+r],e,esize];
                             if op1_neg then op1 = FPNeg(op1);
                             Elem[D[d+r],e,esize] = FPMulAdd(Elem[D[d+r],e,esize],
                                                      op1, Elem[D[m+r],e,esize], StandardFPSCRValue());

               else // VFP instruction
                   if dp_operation then
                        op64 = if op1_neg then FPNeg(D[n]) else D[n];
                        D[d] = FPMulAdd(D[d], op64, D[m], FPSCR);
                   else
                        op32 = if op1_neg then FPNeg(S[n]) else S[n];
                        S[d] = FPMulAdd(S[d], op32, S[m], FPSCR);


platform: ARM
mnem: VFMS
description:
Vector Fused Multiply Subtract negates the elements of one vector and multiplies them with the corresponding       (F8.1.81)
elements of another vector, adds the products to the corresponding elements of the destination vector, and places the
results in the destination vector. The instruction does not round the result of the multiply before the addition.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 0 0 D 1 0                     Vn           Vd        1 1 0 0 N Q M 1              Vm
                                   op sz


64-bit SIMD vector variant

Applies when Q = 0.

VFMS{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VFMS{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE; op1_neg = (op == '1'); esize = 32; elements = 2;
 d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
 regs = if Q == '0' then 1 else 2;


A2


  31        28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
     !=1111     1 1 1 0 1 D 1 0                Vn           Vd        1 0 1 sz N 1 M 0             Vm
      cond                                                                             op


Single-precision scalar variant

Applies when sz = 0.

VFMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VFMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE; dp_operation = (sz == '1'); op1_neg = (op == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3              0 15          12 11 10 9 8 7 6 5 4 3   0
            1 1 1 0 1 1 1 1 0 D 1 0                  Vn         Vd         1 1 0 0 N Q M 1   Vm
                                         op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VFMS{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VFMS{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE; op1_neg = (op == '1'); esize = 32; elements = 2;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm);
         regs = if Q == '0' then 1 else 2;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3              0 15          12 11 10 9 8 7 6 5 4 3   0
            1 1 1 0 1 1 1 0 1 D 1 0                  Vn         Vd         1 0 1 sz N 1 M 0  Vm
                                                                                     op


        Single-precision scalar variant

        Applies when sz = 0.

        VFMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE; dp_operation = (sz == '1'); op1_neg = (op == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
Assembler symbols

<c>           For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
              Advanced SIMD VFMA or VMFS instruction must be unconditional. ARM strongly recommends that a
              T32 Advanced SIMD VFMA or VMFS instruction is unconditional, see Conditional execution on
              page F2-2507.

              For encoding T2: see Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();     CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                 bits(esize) op1 = Elem[D[n+r],e,esize];
                 if op1_neg then op1 = FPNeg(op1);
                 Elem[D[d+r],e,esize] = FPMulAdd(Elem[D[d+r],e,esize],
                                          op1, Elem[D[m+r],e,esize], StandardFPSCRValue());

    else // VFP instruction
        if dp_operation then
            op64 = if op1_neg then FPNeg(D[n]) else D[n];
            D[d] = FPMulAdd(D[d], op64, D[m], FPSCR);
        else
            op32 = if op1_neg then FPNeg(S[n]) else S[n];
            S[d] = FPMulAdd(S[d], op32, S[m], FPSCR);


platform: ARM
mnem: VFNMA
description:
        Vector Fused Negate Multiply Accumulate negates one floating-point register value and multiplies it by another       (F8.1.82)
        floating-point register value, adds the negation of the floating-point value in the destination register to the product,
        and writes the result back to the destination register. The instruction does not round the result of the multiply before
        the addition.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                  0
              !=1111     1 1 1 0 1 D 0 1               Vn            Vd       1 0 1 sz N 1 M 0              Vm
               cond                                                                          op


        Single-precision scalar variant

        Applies when sz = 0.

        VFNMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFNMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         op1_neg = (op == '1');
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 0 1 1 1 0 1 D 0 1                    Vn            Vd       1 0 1 sz N 1 M 0              Vm
                                                                                             op


        Single-precision scalar variant

        Applies when sz = 0.

        VFNMA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFNMA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         op1_neg = (op == '1');
         dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
     if dp_operation then
        op64 = if op1_neg then FPNeg(D[n]) else D[n];
        D[d] = FPMulAdd(FPNeg(D[d]), op64, D[m], FPSCR);
     else
        op32 = if op1_neg then FPNeg(S[n]) else S[n];
        S[d] = FPMulAdd(FPNeg(S[d]), op32, S[m], FPSCR);


platform: ARM
mnem: VFNMS
description:
        Vector Fused Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of       (F8.1.83)
        the floating-point value in the destination register to the product, and writes the result back to the destination
        register. The instruction does not round the result of the multiply before the addition.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3                   0
              !=1111     1 1 1 0 1 D 0 1              Vn            Vd       1 0 1 sz N 0 M 0               Vm
               cond                                                                          op


        Single-precision scalar variant

        Applies when sz = 0.

        VFNMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFNMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         op1_neg = (op == '1');
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 0 1 D 0 1                   Vn            Vd       1 0 1 sz N 0 M 0               Vm
                                                                                             op


        Single-precision scalar variant

        Applies when sz = 0.

        VFNMS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VFNMS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         op1_neg = (op == '1');
         dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
     if dp_operation then
        op64 = if op1_neg then FPNeg(D[n]) else D[n];
        D[d] = FPMulAdd(FPNeg(D[d]), op64, D[m], FPSCR);
     else
        op32 = if op1_neg then FPNeg(S[n]) else S[n];
        S[d] = FPMulAdd(FPNeg(S[d]), op32, S[m], FPSCR);


platform: ARM
mnem: VHADD
description:
        Vector Halving Add adds corresponding elements in two vectors of integers, shifts each result right one bit, and       (F8.1.84)
        places the final results in the destination vector. The results of the halving operations are truncated. For rounded
        results, see VRHADD.

        The operand and result elements are all the same type, and can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       8-bit, 16-bit, or 32-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15         12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 U 0 D size                    Vn          Vd        0 0 0 0 N Q M 0              Vm
                                                                                    op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size == '11' then UNDEFINED;
         add = (op == '0');       unsigned = (U == '1');
         esize = 8 << UInt(size);        elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 U 1 1 1 1 0 D size                    Vn          Vd        0 0 0 0 N Q M 0              Vm
                                                                                    op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size == '11' then UNDEFINED;
 add = (op == '0');  unsigned = (U == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VHADD or VHSUB instruction must be
              unconditional. ARM strongly recommends that a T32 VHADD or VHSUB instruction is unconditional,
              see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
              following values:

              S8           when U = 0, size = 00

              S16          when U = 0, size = 01

              S32          when U = 0, size = 10

              U8           when U = 1, size = 00

              U16          when U = 1, size = 01

              U32          when U = 1, size = 10

              It is RESERVED when:

              .      U = 0, size = 11.

              .      U = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             op1 = Int(Elem[D[n+r],e,esize], unsigned);
             op2 = Int(Elem[D[m+r],e,esize], unsigned);
             result = if add then op1+op2 else op1-op2;
             Elem[D[d+r],e,esize] = result<esize:1>;


platform: ARM
mnem: VHSUB
description:
        Vector Halving Subtract subtracts the elements of the second operand from the corresponding elements of the first       (F8.1.85)
        operand, shifts each result right one bit, and places the final results in the destination vector. The results of the
        halving operations are truncated. There is no rounding version.

        The operand and result elements are all the same type, and can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       8-bit, 16-bit, or 32-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 U 0 D size                    Vn          Vd        0 0 1 0 N Q M 0               Vm
                                                                                    op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size == '11' then UNDEFINED;
         add = (op == '0');       unsigned = (U == '1');
         esize = 8 << UInt(size);        elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15         12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 U 1 1 1 1 0 D size                    Vn          Vd        0 0 1 0 N Q M 0               Vm
                                                                                    op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VHSUB{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VHSUB{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size == '11' then UNDEFINED;
 add = (op == '0');  unsigned = (U == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VHADD or VHSUB instruction must be
              unconditional. ARM strongly recommends that a T32 VHADD or VHSUB instruction is unconditional,
              see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
              following values:

              S8           when U = 0, size = 00

              S16          when U = 0, size = 01

              S32          when U = 0, size = 10

              U8           when U = 1, size = 00

              U16          when U = 1, size = 01

              U32          when U = 1, size = 10

              It is RESERVED when:

              .      U = 0, size = 11.

              .      U = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             op1 = Int(Elem[D[n+r],e,esize], unsigned);
             op2 = Int(Elem[D[m+r],e,esize], unsigned);
             result = if add then op1+op2 else op1-op2;
             Elem[D[d+r],e,esize] = result<esize:1>;


platform: ARM
mnem: VLD1
description:
        Load single 1-element structure to one lane of one register loads one element from memory into one element of a       (F8.1.86)
        register. Elements of the register that are not loaded are unchanged. For details of the addressing mode see Advanced
        SIMD addressing mode on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19            16 15       12 11 10 9 8 7              4 3         0
            1 1 1 1 0 1 0 0 1 D 1 0                      Rn          Vd      !=11 0 0 index_align           Rm
                                                                             size


        Offset variant

        Applies when Rm = 1111.

        VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then SEE VLD1 (single element to all lanes);
         case size of
               when '00'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 1;   index = UInt(index_align<3:1>);       alignment = 1;
               when '01'
                   if index_align<1> != '0' then UNDEFINED;
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   alignment = if index_align<0> == '0' then 1 else 2;
               when '10'
                   if index_align<2> != '0' then UNDEFINED;
                   if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   alignment = if index_align<1:0> == '00' then 1 else 4;
         d = UInt(D:Vd);     n = UInt(Rn);    m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7              4 3         0
            1 1 1 1 1 0 0 1 1 D 1 0                      Rn          Vd      !=11 0 0 index_align           Rm
                                                                             size
Offset variant

Applies when Rm = 1111.

VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VLD1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then SEE VLD1 (single element to all lanes);
 case size of
     when '00'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 1;   index = UInt(index_align<3:1>);     alignment = 1;
     when '01'
         if index_align<1> != '0' then UNDEFINED;
         ebytes = 2;   index = UInt(index_align<3:2>);
         alignment = if index_align<0> == '0' then 1 else 2;
     when '10'
         if index_align<2> != '0' then UNDEFINED;
         if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         alignment = if index_align<1:0> == '00' then 1 else 4;
 d = UInt(D:Vd);  n = UInt(Rn);    m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VLD1 instruction must be
               unconditional. ARM strongly recommends that a T32 VLD1 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The register containing the element to load. It must be {<Dd[x]>}. The register <Dd> is encoded in
               D:Vd.

<Rn>           Contains the base address for the access.

<align>        The alignment. It can be one of:

               16          2-byte alignment, available only if <size> is 16.
                          32           4-byte alignment, available only if <size> is 32.

                          omitted      Standard alignment, see Unaligned data access on page E2-2427.

                          : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
                          see Advanced SIMD addressing mode on page F5-2605.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

        Table F8-1 shows the encoding of index and alignment for the different <size> values.

                                                                          Table F8-1 Encoding of index and alignment

                                              <size> == 8              <size> == 16                 <size> == 32

                         Index                index_align[3:1] = x     index_align[3:2] = x         index_align[3] = x

                         <align> omitted      index_align[0] = 0       index_align[1:0] = '00'      index_align[2:0] = '000'

                         <align> == 16        -                        index_align[1:0] = '01'      -

                         <align> == 32        -                        -                            index_align[2:0] = '011'



        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + ebytes;
               Elem[D[d],index] = MemU[address,ebytes];


platform: ARM
mnem: VLD2
description:
Load single 2-element structure to one lane of two registers loads one 2-element structure from memory into       (F8.1.89)
corresponding elements of two registers. Elements of the registers that are not loaded are unchanged. For details of
the addressing mode see Advanced SIMD addressing mode on page F5-2605.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7               4 3       0
   1 1 1 1 0 1 0 0 1 D 1 0                    Rn           Vd       !=11 0 1 index_align         Rm
                                                                    size


Offset variant

Applies when Rm = 1111.

VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then SEE VLD2 (single 2-element structure to all lanes);
 case size of
      when '00'
           ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
           alignment = if index_align<0> == '0' then 1 else 2;
      when '01'
           ebytes = 2;   index = UInt(index_align<3:2>);
           inc = if index_align<1> == '0' then 1 else 2;
           alignment = if index_align<0> == '0' then 1 else 4;
      when '10'
           if index_align<1> != '0' then UNDEFINED;
           ebytes = 4;   index = UInt(index_align<3>);
           inc = if index_align<2> == '0' then 1 else 2;
           alignment = if index_align<0> == '0' then 1 else 8;
 d = UInt(D:Vd);    d2 = d + inc;    n = UInt(Rn);   m = UInt(Rm);
 wback = (m != 15);     register_index = (m != 15 && m != 13);
 if n == 15 || d2 > 31 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7               4 3       0
   1 1 1 1 1 0 0 1 1 D 1 0                    Rn           Vd       !=11 0 1 index_align         Rm
                                                                    size
        Offset variant

        Applies when Rm = 1111.

        VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VLD2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then SEE VLD2 (single 2-element structure to all lanes);
         case size of
               when '00'
                   ebytes = 1;   index = UInt(index_align<3:1>);      inc = 1;
                   alignment = if index_align<0> == '0' then 1 else 2;
               when '01'
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 4;
               when '10'
                   if index_align<1> != '0' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 8;
         d = UInt(D:Vd);     d2 = d + inc;    n = UInt(Rn);   m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d2 > 31 then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD2 (single 2-element structure to
        one lane) on page J1-5385.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VLD2 instruction must be
                          unconditional. ARM strongly recommends that a T32 VLD2 instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            The data size. It must be one of:

                          8          Encoded as size = 0b00.

                          16         Encoded as size = 0b01.

                          32         Encoded as size = 0b10.

        <list>            The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

                          {<Dd[x]>, <Dd+1[x]>}
                                     Single-spaced registers, see Table F8-2 on page F8-3455.

                          {<Dd[x]>, <Dd+2[x]>}
                                     Double-spaced registers, see Table F8-2 on page F8-3455.
              This is not available if <size> == 8.

<Rn>          Contains the base address for the access.

<align>       The alignment. It can be one of:

              16            2-byte alignment, available only if <size> is 8.

              32            4-byte alignment, available only if <size> is 16.

              64            8-byte alignment, available only if <size> is 32.

              omitted       Standard alignment, see Unaligned data access on page E2-2427.

               : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
              see Advanced SIMD addressing mode on page F5-2605.

<Rm>          Contains an address offset applied after the access.

For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                         Table F8-2 Encoding of index, alignment, and register spacing

                                       <size> == 8              <size> == 16               <size> == 32

                  Index                index_align[3:1] = x     index_align[3:2] = x       index_align[3] = x

                  Single-spacing       -                        index_align[1] = 0         index_align[2] = 0

                  Double-spacing       -                        index_align[1] = 1         index_align[2] = 1

                  <align> omitted      index_align[0] = 0       index_align[0] = 0         index_align[1:0] = '00'

                  <align> == 16        index_align[0] = 1       -                          -

                  <align> == 32        -                        index_align[0] = 1         -

                  <align> == 64        -                        -                          index_align[1:0] = '01'



Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDEnabled();
    address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
    if wback then
        if register_index then
             R[n] = R[n] + R[m];
        else
             R[n] = R[n] + 2*ebytes;
    Elem[D[d], index] = MemU[address,ebytes];
    Elem[D[d2],index] = MemU[address+ebytes,ebytes];


