# instructions

platform: x86
mnem: RET
description:
RET - Return from Procedure:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| C3     | RET        | NP   | Valid      | Valid          | Near return to calling procedure.   
| CB     | RET        | NP   | Valid      | Valid          | Far return to calling procedure.    
| C2 iw  | RET imm16  | I    | Valid      | Valid          | Near return to calling procedure and
|        |            |      |            |                | pop imm16 bytes from stack.         
| CA iw  | RET imm16  | I    | Valid      | Valid          | Far return to calling procedure and 
|        |            |      |            |                | pop imm16 bytes from stack.         

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       
| I    | imm16    | NA       | NA       | NA       

Description:
Transfers program control to a return address located on the top of the stack.
The address is usually placed on the stack by a CALL instruction, and the return
is made to the instruction that follows the CALL instruction.

The optional source operand specifies the number of stack bytes to be released
after the return address is popped; the default is none. This operand can be
used to release parameters from the stack that were passed to the called procedure
and are no longer needed. It must be used when the CALL instruction used to
switch to a new procedure uses a call gate with a non-zero word count to access
the new procedure. Here, the source operand for the RET instruction must specify
the same number of bytes as is specified in the word count field of the call
gate.

The RET instruction can be used to execute three different types of returns:

 - Near return  -  A return to a calling procedure within the current code segment
(the segment currently pointed to by the CS register), sometimes referred to
as an intrasegment return.
 - Far return  -  A return to a calling procedure located in a different segment
than the current code segment, sometimes referred to as an intersegment return.
 - Inter-privilege-level far return  -  A far return to a different privilege level
than that of the currently executing program or procedure.

The inter-privilege-level return type can only be executed in protected mode.
See the section titled “Calling Procedures Using Call and RET” in Chapter 6
of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, for detailed information on near, far, and inter-privilege-level returns.

When executing a near return, the processor pops the return instruction pointer
(offset) from the top of the stack into the EIP register and begins program
execution at the new instruction pointer. The CS register is unchanged.

When executing a far return, the processor pops the return instruction pointer
from the top of the stack into the EIP register, then pops the segment selector
from the top of the stack into the CS register. The processor then begins program
execution in the new code segment at the new instruction pointer.

The mechanics of an inter-privilege-level far return are similar to an intersegment
return, except that the processor examines the privilege levels and access rights
of the code and stack segments being returned to determine if the control transfer
is allowed to be made. The DS, ES, FS, and GS segment registers are cleared
by the RET instruction during an inter-privilege-level return if they refer
to segments that are not allowed to be accessed at the new privilege level.
Since a stack switch also occurs on an inter-privilege level return, the ESP
and SS registers are loaded from the stack.

If parameters are passed to the called procedure during an inter-privilege level
call, the optional source operand must be used with the RET instruction to release
the parameters on the return. Here, the parameters are released both from the
called procedure's stack and the calling procedure's stack (that is, the stack
being returned to).

In 64-bit mode, the default operation size of this instruction is the stack-address
size, i.e. 64 bits.

Operation:

(* Near return *)
IF instruction = near return
  THEN;
     IF OperandSize = 32
       THEN
          IF top 4 bytes of stack not within stack limits
             THEN #SS(0); FI;
          EIP <- Pop();
       ELSE
          IF OperandSize = 64
             THEN
               IF top 8 bytes of stack not within stack limits
                  THEN #SS(0); FI;
               RIP <- Pop();
             ELSE (* OperandSize = 16 *)
               IF top 2 bytes of stack not within stack limits
                  THEN #SS(0); FI;
               tempEIP <- Pop();
               tempEIP <- tempEIP AND 0000FFFFH;
               IF tempEIP not within code segment limits
                  THEN #GP(0); FI;
               EIP <- tempEIP;
          FI;
     FI;
  IF instruction has immediate operand
     THEN (* Release parameters from stack *)
       IF StackAddressSize = 32
          THEN
             ESP <- ESP + SRC;
          ELSE
             IF StackAddressSize = 64
               THEN
                  RSP <- RSP + SRC;
               ELSE (* StackAddressSize = 16 *)
                  SP <- SP + SRC;
             FI;
       FI;
  FI;
FI;
(* Real-address mode or virtual-8086 mode *)
IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return
  THEN
     IF OperandSize = 32
       THEN
          IF top 8 bytes of stack not within stack limits
             THEN #SS(0); FI;
          EIP <- Pop();
          CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
       ELSE (* OperandSize = 16 *)
          IF top 4 bytes of stack not within stack limits
             THEN #SS(0); FI;
          tempEIP <- Pop();
          tempEIP <- tempEIP AND 0000FFFFH;
          IF tempEIP not within code segment limits
             THEN #GP(0); FI;
          EIP <- tempEIP;
          CS <- Pop(); (* 16-bit pop *)
     FI;
  IF instruction has immediate operand
     THEN (* Release parameters from stack *)
       SP <- SP + (SRC AND FFFFH);
  FI;
FI;
(* Protected mode, not virtual-8086 mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 0) and instruction = far return
  THEN
     IF OperandSize = 32
       THEN
          IF second doubleword on stack is not within stack limits
             THEN #SS(0); FI;
       ELSE (* OperandSize = 16 *)
          IF second word on stack is not within stack limits
             THEN #SS(0); FI;
     FI;
  IF return code segment selector is NULL
     THEN #GP(0); FI;
  IF return code segment selector addresses descriptor beyond descriptor table limit
     THEN #GP(selector); FI;
  Obtain descriptor to which return code segment selector points from descriptor table;
  IF return code segment descriptor is not a code segment
     THEN #GP(selector); FI;
  IF return code segment selector RPL < CPL
     THEN #GP(selector); FI;
  IF return code segment descriptor is conforming
  and return code segment DPL > return code segment selector RPL
     THEN #GP(selector); FI;
  IF return code segment descriptor is non-conforming and return code
  segment DPL != return code segment selector RPL
     THEN #GP(selector); FI;
  IF return code segment descriptor is not present
     THEN #NP(selector); FI:
  IF return code segment selector RPL > CPL
     THEN GOTO RETURN-OUTER-PRIVILEGE-LEVEL;
     ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;
  FI;
FI;
RETURN-SAME-PRIVILEGE-LEVEL:
  IF the return instruction pointer is not within the return code segment limit
     THEN #GP(0); FI;
  IF OperandSize = 32
     THEN
       EIP <- Pop();
       CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
     ELSE (* OperandSize = 16 *)
       EIP <- Pop();
       EIP <- EIP AND 0000FFFFH;
       CS <- Pop(); (* 16-bit pop *)
  FI;
  IF instruction has immediate operand
     THEN (* Release parameters from stack *)
       IF StackAddressSize = 32
          THEN
             ESP <- ESP + SRC;
          ELSE (* StackAddressSize = 16 *)
             SP <- SP + SRC;
       FI;
  FI;
RETURN-OUTER-PRIVILEGE-LEVEL:
  IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
  or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
       THEN #SS(0); FI;
  Read return segment selector;
  IF stack segment selector is NULL
     THEN #GP(0); FI;
  IF return stack segment selector index is not within its descriptor table limits
     THEN #GP(selector); FI;
  Read segment descriptor pointed to by return segment selector;
  IF stack segment selector RPL != RPL of the return code segment selector
  or stack segment is not a writable data segment
  or stack segment descriptor DPL != RPL of the return code segment selector
       THEN #GP(selector); FI;
  IF stack segment not present
     THEN #SS(StackSegmentSelector); FI;
  IF the return instruction pointer is not within the return code segment limit
     THEN #GP(0); FI;
  CPL <- ReturnCodeSegmentSelector(RPL);
  IF OperandSize = 32
     THEN
       EIP <- Pop();
       CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)
       CS(RPL) <- CPL;
       IF instruction has immediate operand
          THEN (* Release parameters from called procedure's stack *)
             IF StackAddressSize = 32
               THEN
                  ESP <- ESP + SRC;
               ELSE (* StackAddressSize = 16 *)
                  SP <- SP + SRC;
             FI;
       FI;
       tempESP <- Pop();
       tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)
       ESP <- tempESP;
       SS <- tempSS;
     ELSE (* OperandSize = 16 *)
       EIP <- Pop();
       EIP <- EIP AND 0000FFFFH;
       CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
       CS(RPL) <- CPL;
       IF instruction has immediate operand
          THEN (* Release parameters from called procedure's stack *)
             IF StackAddressSize = 32
               THEN
                  ESP <- ESP + SRC;
               ELSE (* StackAddressSize = 16 *)
                  SP <- SP + SRC;
             FI;
       FI;
       tempESP <- Pop();
       tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
       ESP <- tempESP;
       SS <- tempSS;
  FI;
  FOR each of segment register (ES, FS, GS, and DS)
     DO
       IF segment register points to data or non-conforming code segment
       and CPL > segment descriptor DPL (* DPL in hidden part of segment register *)
          THEN SegmentSelector <- 0; (* Segment selector invalid *)
       FI;
     OD;
  IF instruction has immediate operand
     THEN (* Release parameters from calling procedure's stack *)
       IF StackAddressSize = 32
          THEN
             ESP <- ESP + SRC;
          ELSE (* StackAddressSize = 16 *)
             SP <- SP + SRC;
       FI;
  FI;
(* IA-32e Mode *)
  IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return
     THEN
       IF OperandSize = 32
          THEN
             IF second doubleword on stack is not within stack limits
               THEN #SS(0); FI;
             IF first or second doubleword on stack is not in canonical space
               THEN #SS(0); FI;
          ELSE
             IF OperandSize = 16
               THEN
                  IF second word on stack is not within stack limits
                     THEN #SS(0); FI;
                  IF first or second word on stack is not in canonical space
                     THEN #SS(0); FI;
               ELSE (* OperandSize = 64 *)
                  IF first or second quadword on stack is not in canonical space
                     THEN #SS(0); FI;
             FI
       FI;
     IF return code segment selector is NULL
       THEN GP(0); FI;
     IF return code segment selector addresses descriptor beyond descriptor table limit
       THEN GP(selector); FI;
     IF return code segment selector addresses descriptor in non-canonical space
       THEN GP(selector); FI;
     Obtain descriptor to which return code segment selector points from descriptor table;
     IF return code segment descriptor is not a code segment
       THEN #GP(selector); FI;
     IF return code segment descriptor has L-bit = 1 and D-bit = 1
       THEN #GP(selector); FI;
     IF return code segment selector RPL < CPL
       THEN #GP(selector); FI;
     IF return code segment descriptor is conforming
     and return code segment DPL > return code segment selector RPL
       THEN #GP(selector); FI;
     IF return code segment descriptor is non-conforming
     and return code segment DPL != return code segment selector RPL
       THEN #GP(selector); FI;
     IF return code segment descriptor is not present
       THEN #NP(selector); FI:
     IF return code segment selector RPL > CPL
       THEN GOTO IA-32E-MODE-RETURN-OUTER-PRIVILEGE-LEVEL;
       ELSE GOTO IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL;
     FI;
  FI;
IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
  THEN #GP(0); FI;
IF the return instruction pointer is not within canonical address space
  THEN #GP(0); FI;
IF OperandSize = 32
  THEN
     EIP <- Pop();
     CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
  ELSE
     IF OperandSize = 16
       THEN
          EIP <- Pop();
          EIP <- EIP AND 0000FFFFH;
          CS <- Pop(); (* 16-bit pop *)
       ELSE (* OperandSize = 64 *)
          RIP <- Pop();
          CS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)
     FI;
FI;
IF instruction has immediate operand
  THEN (* Release parameters from stack *)
     IF StackAddressSize = 32
       THEN
          ESP <- ESP + SRC;
       ELSE
          IF StackAddressSize = 16
             THEN
               SP <- SP + SRC;
             ELSE (* StackAddressSize = 64 *)
               RSP <- RSP + SRC;
          FI;
     FI;
FI;
IA-32E-MODE-RETURN-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
  THEN #SS(0); FI;
IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32)
or top (8 + SRC) bytes of stack are not in canonical address space (OperandSize = 16)
or top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)
  THEN #SS(0); FI;
Read return stack segment selector;
IF stack segment selector is NULL
  THEN
     IF new CS descriptor L-bit = 0
       THEN #GP(selector);
     IF stack segment selector RPL = 3
       THEN #GP(selector);
FI;
IF return stack segment descriptor is not within descriptor table limits
     THEN #GP(selector); FI;
IF return stack segment descriptor is in non-canonical address space
     THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL != RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL != RPL of the return code segment selector
  THEN #GP(selector); FI;
IF stack segment not present
  THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
  THEN #GP(0); FI:
IF the return instruction pointer is not within canonical address space
  THEN #GP(0); FI;
CPL <- ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
  THEN
     EIP <- Pop();
     CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
     CS(RPL) <- CPL;
     IF instruction has immediate operand
       THEN (* Release parameters from called procedure's stack *)
          IF StackAddressSize = 32
             THEN
               ESP <- ESP + SRC;
             ELSE
               IF StackAddressSize = 16
                  THEN
                     SP <- SP + SRC;
                  ELSE (* StackAddressSize = 64 *)
                     RSP <- RSP + SRC;
               FI;
          FI;
     FI;
     tempESP <- Pop();
     tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
     ESP <- tempESP;
     SS <- tempSS;
  ELSE
     IF OperandSize = 16
       THEN
          EIP <- Pop();
          EIP <- EIP AND 0000FFFFH;
          CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
          CS(RPL) <- CPL;
          IF instruction has immediate operand
             THEN (* Release parameters from called procedure's stack *)
               IF StackAddressSize = 32
                  THEN
                     ESP <- ESP + SRC;
                  ELSE
                     IF StackAddressSize = 16
                       THEN
                          SP <- SP + SRC;
                       ELSE (* StackAddressSize = 64 *)
                          RSP <- RSP + SRC;
                     FI;
               FI;
          FI;
          tempESP <- Pop();
          tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
          ESP <- tempESP;
          SS <- tempSS;
       ELSE (* OperandSize = 64 *)
          RIP <- Pop();
          CS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)
          CS(RPL) <- CPL;
          IF instruction has immediate operand
             THEN (* Release parameters from called procedure's stack *)
               RSP <- RSP + SRC;
          FI;
          tempESP <- Pop();
          tempSS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)
          ESP <- tempESP;
          SS <- tempSS;
     FI;
FI;
FOR each of segment register (ES, FS, GS, and DS)
  DO
     IF segment register points to data or non-conforming code segment
     and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)
       THEN SegmentSelector <- 0; (* SegmentSelector invalid *)
     FI;
  OD;
IF instruction has immediate operand
  THEN (* Release parameters from calling procedure's stack *)
     IF StackAddressSize = 32
       THEN
          ESP <- ESP + SRC;
       ELSE
          IF StackAddressSize = 16
             THEN
               SP <- SP + SRC;
             ELSE (* StackAddressSize = 64 *)
               RSP <- RSP + SRC;
          FI;
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the return code or stack segment          
|                | selector NULL. If the return instruction     
|                | pointer is not within the return code        
|                | segment limit                                
| #GP(selector)  | If the RPL of the return code segment        
|                | selector is less then the CPL. If the        
|                | return code or stack segment selector        
|                | index is not within its descriptor table     
|                | limits. If the return code segment descriptor
|                | does not indicate a code segment. If         
|                | the return code segment is non-conforming    
|                | and the segment selector's DPL is not        
|                | equal to the RPL of the code segment's       
|                | segment selector If the return code          
|                | segment is conforming and the segment        
|                | selector's DPL greater than the RPL          
|                | of the code segment's segment selector       
|                | If the stack segment is not a writable       
|                | data segment. If the stack segment selector  
|                | RPL is not equal to the RPL of the return    
|                | code segment selector. If the stack          
|                | segment descriptor DPL is not equal          
|                | to the RPL of the return code segment        
|                | selector.                                    
| #SS(0)         | If the top bytes of stack are not within     
|                | stack limits. If the return stack segment    
|                | is not present.                              
| #NP(selector)  | If the return code segment is not present.   
| #PF(fault-code)| If a page fault occurs.                      
| #AC(0)         | If an unaligned memory access occurs         
|                | when the CPL is 3 and alignment checking     
|                | is enabled.                                  

Real-Address Mode Exceptions:
| #GP| If the return instruction pointer is    
|    | not within the return code segment limit
| #SS| If the top bytes of stack are not within
|    | stack limits.                           

Virtual-8086 Mode Exceptions:
| #GP(0)         | If the return instruction pointer is    
|                | not within the return code segment limit
| #SS(0)         | If the top bytes of stack are not within
|                | stack limits.                           
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If an unaligned memory access occurs    
|                | when alignment checking is enabled.     

Compatibility Mode Exceptions:
Same as 64-bit mode exceptions.


64-Bit Mode Exceptions:
| #GP(0)         | If the return instruction pointer is        
|                | non-canonical. If the return instruction    
|                | pointer is not within the return code       
|                | segment limit. If the stack segment         
|                | selector is NULL going back to compatibility
|                | mode. If the stack segment selector         
|                | is NULL going back to CPL3 64-bit mode.     
|                | If a NULL stack segment selector RPL        
|                | is not equal to CPL going back to non-CPL3  
|                | 64-bit mode. If the return code segment     
|                | selector is NULL.                           
| #GP(selector)  | If the proposed segment descriptor for      
|                | a code segment does not indicate it         
|                | is a code segment. If the proposed new      
|                | code segment descriptor has both the        
|                | D-bit and L-bit set. If the DPL for         
|                | a nonconforming-code segment is not         
|                | equal to the RPL of the code segment        
|                | selector. If CPL is greater than the        
|                | RPL of the code segment selector. If        
|                | the DPL of a conforming-code segment        
|                | is greater than the return code segment     
|                | selector RPL. If a segment selector         
|                | index is outside its descriptor table       
|                | limits. If a segment descriptor memory      
|                | address is non-canonical. If the stack      
|                | segment is not a writable data segment.     
|                | If the stack segment descriptor DPL         
|                | is not equal to the RPL of the return       
|                | code segment selector. If the stack         
|                | segment selector RPL is not equal to        
|                | the RPL of the return code segment selector.
| #SS(0)         | If an attempt to pop a value off the        
|                | stack violates the SS limit. If an attempt  
|                | to pop a value off the stack causes         
|                | a non-canonical address to be referenced.   
| #NP(selector)  | If the return code or stack segment         
|                | is not present.                             
| #PF(fault-code)| If a page fault occurs.                     
| #AC(0)         | If alignment checking is enabled and        
|                | an unaligned memory reference is made       
|                | while the current privilege level is        
|                | 3.                                          


platform: x86
mnem: RORX
description:
RORX  -  Rotate Right Logical Without Affecting Flags:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                         
| VEX.LZ.F2.0F3A.W0 F0 /r ib RORX r32,| RMI  | V/V            | BMI2              | Rotate 32-bit r/m32 right imm8 times
| r/m32, imm8                         |      |                |                   | without affecting arithmetic flags. 
| VEX.LZ.F2.0F3A.W1 F0 /r ib RORX r64,| RMI  | V/N.E.         | BMI2              | Rotate 64-bit r/m64 right imm8 times
| r/m64, imm8                         |      |                |                   | without affecting arithmetic flags. 

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| Imm8     | NA       

Description:
Rotates the bits of second operand right by the count value specified in imm8
without affecting arithmetic flags. The RORX instruction does not read or write
the arithmetic flags. This instruction is not supported in real mode and virtual-8086
mode. The operand size is always 32 bits if not in 64-bit mode. In 64-bit mode
operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An attempt
to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation:

IF (OperandSize = 32)
  y <- imm8 AND 1FH;
  DEST <- (SRC >> y) | (SRC << (32-y));
ELSEIF (OperandSize = 64 )
  y <- imm8 AND 3FH;
  DEST <- (SRC >> y) | (SRC << (64-y));
ENDIF

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
Auto-generated from high-level language.


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: ROUNDPD
description:
ROUNDPD  -  Round Packed Double Precision Floating-Point Values:
| Opcode*/Instruction                       | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 66 0F 3A 09 /r ib ROUNDPD xmm1, xmm2/m128,| RMI  | V/V                   | SSE4_1            | Round packed double precision floating-point
| imm8                                      |      |                       |                   | values in xmm2/m128 and place the result    
|                                           |      |                       |                   | in The rounding mode is determined by       
|                                           |      |                       |                   | imm8.                                       
| VEX.128.66.0F3A.WIG 09 /r ib VROUNDPD     | RMI  | V/V                   | AVX               | Round packed double-precision floating-point
| xmm1, xmm2/m128, imm8                     |      |                       |                   | values in xmm2/m128 and place the result    
|                                           |      |                       |                   | in xmm1. The rounding mode is determined    
|                                           |      |                       |                   | by imm8.                                    
| VEX.256.66.0F3A.WIG 09 /r ib VROUNDPD     | RMI  | V/V                   | AVX               | Round packed double-precision floating-point
| ymm1, ymm2/m256, imm8                     |      |                       |                   | values in ymm2/m256 and place the result    
|                                           |      |                       |                   | in ymm1. The rounding mode is determined    
|                                           |      |                       |                   | by imm8.                                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Round the 2 double-precision floating-point values in the source operand (second
operand) using the rounding mode specified in the immediate operand (third operand)
and place the results in the destination operand (first operand). The rounding
process rounds each input floating-point value to an integer value and returns
the integer result as a single-precision floating-point value.

The immediate operand specifies control fields for the rounding operation, three
bit fields are defined and shown in Figure 4-20. Bit 3 of the immediate byte
controls processor behavior for a precision exception, bit 2 selects the source
of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value
(Table 4-14 lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate
operand. If any source operand is an SNaN then it will be converted to a QNaN.
If DAZ is set to ‘1 then denormals will be converted to zero before rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the source operand second source operand
or a 128-bit memory location. The destination operand is an XMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register. Note: In VEX-encoded versions,
VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

| 8| 3 2 1 0
Reserved

P  -  Precision Mask; 0: normal, 1: inexact RS  -  Rounding select; 1: MXCSR.RC,
0: Imm8.RC RC  -  Rounding mode

| Figure 4-20.                                 | Bit Control Fields of Immediate Byte   
|                                              | for ROUNDxx Instruction                
| Table 4-14.                                  | Rounding Modes and Encoding of Rounding
|                                              | Control (RC) Field                     
| Description                                  | RC Field Setting                       
| Rounded result is the closest to the         | 00B nearest (even)                     
| infinitely precise result. If two values     |                                        
| are equally close, the result is the         |                                        
| even value (i.e., the integer value          |                                        
| with the least-significant bit of zero).     |                                        
| Rounded result is closest to but no          | 01B (toward −∞)                        
| greater than the infinitely precise          |                                        
| result.                                      |                                        
| Rounded result is closest to but no          | 10B (toward +∞)                        
| less than the infinitely precise result.     |                                        
| Rounded result is closest to but no          | 11B zero (Truncate)                    
| greater in absolute value than the infinitely|                                        
| precise result.                              |                                        
Operation:

IF (imm[2] = ‘1)
  THEN
     DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);
     DEST[127:64] <- ConvertDPFPToInteger_M(SRC[127:64]);
  ELSE
     DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);
     DEST[127:64] <- ConvertDPFPToInteger_Imm(SRC[127:64]);
FI
ROUNDPD (128-bit Legacy SSE version)
DEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)
VROUNDPD (VEX.128 encoded version)
DEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] <- 0
VROUNDPD (VEX.256 encoded version)
DEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[191:128] <- RoundToInteger(SRC[191:128]], ROUND_CONTROL)
DEST[255:192] <- RoundToInteger(SRC[255:192] ], ROUND_CONTROL)

Intel C/C++ Compiler Intrinsic Equivalent:
__m128 _mm_round_pd(__m128d s1, int iRoundMode);

__m128 _mm_floor_pd(__m128d s1);

__m128 _mm_ceil_pd(__m128d s1)

__m256 _mm256_round_pd(__m256d s1, int iRoundMode);

__m256 _mm256_floor_pd(__m256d s1);

__m256 _mm256_ceil_pd(__m256d s1)


SIMD Floating-Point Exceptions:
Invalid (signaled only if SRC = SNaN) Precision (signaled only if imm[3] = ‘0;
if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision
exception is not signaled.) Note that Denormal is not signaled by ROUNDPD.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: ROUNDPS
description:
ROUNDPS  -  Round Packed Single Precision Floating-Point Values:
| Opcode*/Instruction                       | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 66 0F 3A 08 /r ib ROUNDPS xmm1, xmm2/m128,| RMI  | V/V                   | SSE4_1            | Round packed single precision floating-point
| imm8                                      |      |                       |                   | values in xmm2/m128 and place the result    
|                                           |      |                       |                   | in The rounding mode is determined by       
|                                           |      |                       |                   | imm8.                                       
| VEX.128.66.0F3A.WIG 08 /r ib VROUNDPS     | RMI  | V/V                   | AVX               | Round packed single-precision floating-point
| xmm1, xmm2/m128, imm8                     |      |                       |                   | values in xmm2/m128 and place the result    
|                                           |      |                       |                   | in xmm1. The rounding mode is determined    
|                                           |      |                       |                   | by imm8.                                    
| VEX.256.66.0F3A.WIG 08 /r ib VROUNDPS     | RMI  | V/V                   | AVX               | Round packed single-precision floating-point
| ymm1, ymm2/m256, imm8                     |      |                       |                   | values in ymm2/m256 and place the result    
|                                           |      |                       |                   | in ymm1. The rounding mode is determined    
|                                           |      |                       |                   | by imm8.                                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Round the 4 single-precision floating-point values in the source operand (second
operand) using the rounding mode specified in the immediate operand (third operand)
and place the results in the destination operand (first operand). The rounding
process rounds each input floating-point value to an integer value and returns
the integer result as a single-precision floating-point value.

The immediate operand specifies control fields for the rounding operation, three
bit fields are defined and shown in Figure 4-20. Bit 3 of the immediate byte
controls processor behavior for a precision exception, bit 2 selects the source
of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value
(Table 4-14 lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate
operand. If any source operand is an SNaN then it will be converted to a QNaN.
If DAZ is set to ‘1 then denormals will be converted to zero before rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the source operand second source operand
or a 128-bit memory location. The destination operand is an XMM register. The
upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory
location. The destination operand is a YMM register. Note: In VEX-encoded versions,
VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation:

IF (imm[2] = ‘1)
  THEN
     DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);
     DEST[63:32] <- ConvertSPFPToInteger_M(SRC[63:32]);
     DEST[95:64] <- ConvertSPFPToInteger_M(SRC[95:64]);
     DEST[127:96] <- ConvertSPFPToInteger_M(SRC[127:96]);
  ELSE
     DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);
     DEST[63:32] <- ConvertSPFPToInteger_Imm(SRC[63:32]);
     DEST[95:64] <- ConvertSPFPToInteger_Imm(SRC[95:64]);
     DEST[127:96] <- ConvertSPFPToInteger_Imm(SRC[127:96]);
FI;
ROUNDPS(128-bit Legacy SSE version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)
VROUNDPS (VEX.128 encoded version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] <- 0
VROUNDPS (VEX.256 encoded version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[159:128] <- RoundToInteger(SRC[159:128]], ROUND_CONTROL)
DEST[191:160] <- RoundToInteger(SRC[191:160]], ROUND_CONTROL)
DEST[223:192] <- RoundToInteger(SRC[223:192] ], ROUND_CONTROL)
DEST[255:224] <- RoundToInteger(SRC[255:224] ], ROUND_CONTROL)

Intel C/C++ Compiler Intrinsic Equivalent:
__m128 _mm_round_ps(__m128 s1, int iRoundMode);

__m128 _mm_floor_ps(__m128 s1);

__m128 _mm_ceil_ps(__m128 s1)

__m256 _mm256_round_ps(__m256 s1, int iRoundMode);

__m256 _mm256_floor_ps(__m256 s1);

__m256 _mm256_ceil_ps(__m256 s1)


SIMD Floating-Point Exceptions:
Invalid (signaled only if SRC = SNaN) Precision (signaled only if imm[3] = ‘0;
if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision
exception is not signaled.) Note that Denormal is not signaled by ROUNDPS.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: ROUNDSD
description:
ROUNDSD  -  Round Scalar Double Precision Floating-Point Values:
| Opcode*/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 66 0F 3A 0B /r ib ROUNDSD xmm1, xmm2/m64,| RMI  | V/V                   | SSE4_1            | Round the low packed double precision   
| imm8                                     |      |                       |                   | floating-point value in xmm2/m64 and    
|                                          |      |                       |                   | place the result in xmm1. The rounding  
|                                          |      |                       |                   | mode is determined by imm8.             
| VEX.NDS.LIG.66.0F3A.WIG 0B /r ib VROUNDSD| RVMI | V/V                   | AVX               | Round the low packed double precision   
| xmm1, xmm2, xmm3/m64, imm8               |      |                       |                   | floating-point value in xmm3/m64 and    
|                                          |      |                       |                   | place the result in xmm1. The rounding  
|                                          |      |                       |                   | mode is determined by imm8. Upper packed
|                                          |      |                       |                   | double precision floating-point value   
|                                          |      |                       |                   | (bits[127:64]) from xmm2 is copied to   
|                                          |      |                       |                   | xmm1[127:64].                           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Round the DP FP value in the lower qword of the source operand (second operand)
using the rounding mode specified in the immediate operand (third operand) and
place the result in the destination operand (first operand). The rounding process
rounds a double-precision floating-point input to an integer value and returns
the integer result as a double precision floating-point value in the lowest
position. The upper double precision floating-point value in the destination
is retained.

The immediate operand specifies control fields for the rounding operation, three
bit fields are defined and shown in Figure 4-20. Bit 3 of the immediate byte
controls processor behavior for a precision exception, bit 2 selects the source
of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value
(Table 4-14 lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate
operand. If any source operand is an SNaN then it will be converted to a QNaN.
If DAZ is set to ‘1 then denormals will be converted to zero before rounding.
128-bit Legacy SSE version: The first source operand and the destination operand
are the same. Bits (VLMAX1:64) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed.

Operation:

IF (imm[2] = ‘1)
  THEN
     DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);
  ELSE
     DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);
FI;
DEST[127:63] remains unchanged ;
ROUNDSD (128-bit Legacy SSE version)
DEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[VLMAX-1:64] (Unmodified)
VROUNDSD (VEX.128 encoded version)
DEST[63:0] <- RoundToInteger(SRC2[63:0], ROUND_CONTROL)
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| ROUNDSD:| __m128d mm_round_sd(__m128d dst, __m128d        
|         | s1, int iRoundMode); __m128d mm_floor_sd(__m128d
|         | dst, __m128d s1); __m128d mm_ceil_sd(__m128d    
|         | dst, __m128d s1);                               

SIMD Floating-Point Exceptions:
Invalid (signaled only if SRC = SNaN) Precision (signaled only if imm[3] = ‘0;
if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision
exception is not signaled.) Note that Denormal is not signaled by ROUNDSD.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: ROUNDSS
description:
ROUNDSS  -  Round Scalar Single Precision Floating-Point Values:
| Opcode*/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 3A 0A /r ib ROUNDSS xmm1, xmm2/m32,| RMI  | V/V                   | SSE4_1            | Round the low packed single precision  
| imm8                                     |      |                       |                   | floating-point value in xmm2/m32 and   
|                                          |      |                       |                   | place The rounding mode is determined  
|                                          |      |                       |                   | by imm8.                               
| VEX.NDS.LIG.66.0F3A.WIG 0A /r ib VROUNDSS| RVMI | V/V                   | AVX               | Round the low packed single precision  
| xmm1, xmm2, xmm3/m32, imm8               |      |                       |                   | floating-point value in xmm3/m32 and   
|                                          |      |                       |                   | place the result in xmm1. The rounding 
|                                          |      |                       |                   | mode is determined by imm8. Also, upper
|                                          |      |                       |                   | packed single precision floating-point 
|                                          |      |                       |                   | values (bits[127:32]) from xmm2 are    
|                                          |      |                       |                   | copied to xmm1[127:32].                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Round the single-precision floating-point value in the lowest dword of the source
operand (second operand) using the rounding mode specified in the immediate
operand (third operand) and place the result in the destination operand (first
operand). The rounding process rounds a single-precision floating-point input
to an integer value and returns the result as a single-precision floating-point
value in the lowest position. The upper three single-precision floating-point
values in the destination are retained.

The immediate operand specifies control fields for the rounding operation, three
bit fields are defined and shown in Figure 4-20. Bit 3 of the immediate byte
controls processor behavior for a precision exception, bit 2 selects the source
of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value
(Table 4-14 lists the encoded values for rounding-mode field).

The Precision Floating-Point Exception is signaled according to the immediate
operand. If any source operand is an SNaN then it will be converted to a QNaN.
If DAZ is set to ‘1 then denormals will be converted to zero before rounding.
128-bit Legacy SSE version: The first source operand and the destination operand
are the same. Bits (VLMAX1:32) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination
YMM register are zeroed.

Operation:

IF (imm[2] = ‘1)
  THEN
     DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);
  ELSE
     DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);
FI;
DEST[127:32] remains unchanged ;
ROUNDSS (128-bit Legacy SSE version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[VLMAX-1:32] (Unmodified)
VROUNDSS (VEX.128 encoded version)
DEST[31:0] <- RoundToInteger(SRC2[31:0], ROUND_CONTROL)
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| ROUNDSS:| __m128 mm_round_ss(__m128 dst, __m128         
|         | s1, int iRoundMode); __m128 mm_floor_ss(__m128
|         | dst, __m128 s1); __m128 mm_ceil_ss(__m128     
|         | dst, __m128 s1);                              

SIMD Floating-Point Exceptions:
Invalid (signaled only if SRC = SNaN) Precision (signaled only if imm[3] = ‘0;
if imm[3] = ‘1, then the Precision Mask in the MXSCSR is ignored and precision
exception is not signaled.) Note that Denormal is not signaled by ROUNDSS.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: RSM
description:
RSM - Resume from System Management Mode:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F AA  | RSM        | NP   | Invalid    | Valid          | Resume operation of interrupted program.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Returns program control from system management mode (SMM) to the application
program or operating-system procedure that was interrupted when the processor
received an SMM interrupt. The processor's state is restored from the dump created
upon entering SMM. If the processor detects invalid state information during
state restoration, it enters the shutdown state. The following invalid information
can cause a shutdown:

 - Any reserved bit of CR4 is set to 1.
 - Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and
CD=0).
 - (Intel Pentium and Intel486™ processors only.) The value stored in the state
dump base field is not a 32-KByte aligned address.

The contents of the model-specific registers are not affected by a return from
SMM.

The SMM state map used by RSM supports resuming processor context for non-64-bit
modes and 64-bit mode.

See Chapter 34, “System Management Mode,” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3C, for more information about SMM and the
behavior of the RSM instruction.

Operation:

ReturnFromSMM;
IF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )
  THEN
     ProcessorState <- Restore(SMMDump(IA-32e SMM STATE MAP));
  Else
     ProcessorState <- Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
FI

Flags Affected:
All.


Protected Mode Exceptions:
| #UD| If an attempt is made to execute this
|    | instruction when the processor is not
|    | in SMM. If the LOCK prefix is used.  

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: RSQRTPS
description:
RSQRTPS - Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point Values:
| Opcode*/Instruction                | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                       
| 0F 52 /r RSQRTPS xmm1, xmm2/m128   | RM   | V/V                   | SSE               | Computes the approximate reciprocals              
|                                    |      |                       |                   | of the square roots of the packed single-precision
|                                    |      |                       |                   | floating-point values in xmm2/m128 and            
|                                    |      |                       |                   | stores the results in xmm1.                       
| VEX.128.0F.WIG 52 /r VRSQRTPS xmm1,| RM   | V/V                   | AVX               | Computes the approximate reciprocals              
| xmm2/m128                          |      |                       |                   | of the square roots of packed single-precision    
|                                    |      |                       |                   | values in xmm2/mem and stores the results         
|                                    |      |                       |                   | in xmm1.                                          
| VEX.256.0F.WIG 52 /r VRSQRTPS ymm1,| RM   | V/V                   | AVX               | Computes the approximate reciprocals              
| ymm2/m256                          |      |                       |                   | of the square roots of packed single-precision    
|                                    |      |                       |                   | values in ymm2/mem and stores the results         
|                                    |      |                       |                   | in ymm1.                                          

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a SIMD computation of the approximate reciprocals of the square roots
of the four packed single-precision floating-point values in the source operand
(second operand) and stores the packed single-precision floatingpoint results
in the destination operand. The source operand can be an XMM register or a 128-bit
memory location. The destination operand is an XMM register. See Figure 10-5
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, for an illustration of a SIMD single-precision floating-point operation.

The relative error for this approximation is:

|Relative Error| ≤ 1.5 * 2−12

The RSQRTPS instruction is not affected by the rounding control bits in the
MXCSR register. When a source value is a 0.0, an ∞ of the sign of the source
value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than −0.0), a floating-point
indefinite is returned. When a source value is an SNaN or QNaN, the SNaN is
converted to a QNaN or the source QNaN is returned.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b,
otherwise instructions will #UD.

Operation:

RSQRTPS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] (Unmodified)
VRSQRTPS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] <- 0
VRSQRTPS (VEX.256 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[159:128] <- APPROXIMATE(1/SQRT(SRC2[159:128]))
DEST[191:160] <- APPROXIMATE(1/SQRT(SRC2[191:160]))
DEST[223:192] <- APPROXIMATE(1/SQRT(SRC2[223:192]))
DEST[255:224] <- APPROXIMATE(1/SQRT(SRC2[255:224]))

Intel C/C++ Compiler Intrinsic Equivalent:
| RSQRTPS:| __m128 _mm_rsqrt_ps(__m128 a)     
| RSQRTPS:| __m256 _mm256_rsqrt_ps (__m256 a);

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: RSQRTSS
description:
RSQRTSS - Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value:
| Opcode*/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                   
| F3 0F 52 /r RSQRTSS xmm1, xmm2/m32  | RM   | V/V                   | SSE               | Computes the approximate reciprocal           
|                                     |      |                       |                   | of the square root of the low single-precision
|                                     |      |                       |                   | floating-point value in xmm2/m32 and          
|                                     |      |                       |                   | stores the results in xmm1.                   
| VEX.NDS.LIG.F3.0F.WIG 52 /r VRSQRTSS| RVM  | V/V                   | AVX               | Computes the approximate reciprocal           
| xmm1, xmm2, xmm3/m32                |      |                       |                   | of the square root of the low single          
|                                     |      |                       |                   | precision floating-point value in xmm3/m32    
|                                     |      |                       |                   | and stores the results in xmm1. Also,         
|                                     |      |                       |                   | upper single precision floating-point         
|                                     |      |                       |                   | values (bits[127:32]) from xmm2 are           
|                                     |      |                       |                   | copied to xmm1[127:32].                       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Computes an approximate reciprocal of the square root of the low single-precision
floating-point value in the source operand (second operand) stores the single-precision
floating-point result in the destination operand. The source operand can be
an XMM register or a 32-bit memory location. The destination operand is an XMM
register. The three high-order doublewords of the destination operand remain
unchanged. See Figure 10-6 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for an illustration of a scalar single-precision
floating-point operation.

The relative error for this approximation is:

|Relative Error| ≤ 1.5 * 2−12

The RSQRTSS instruction is not affected by the rounding control bits in the
MXCSR register. When a source value is a 0.0, an ∞ of the sign of the source
value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than −0.0), a floating-point
indefinite is returned. When a source value is an SNaN or QNaN, the SNaN is
converted to a QNaN or the source QNaN is returned.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
first source operand and the destination operand are the same. Bits (VLMAX1:32)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

RSQRTSS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[VLMAX-1:32] (Unmodified)
VRSQRTSS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[127:32] <- SRC1[31:0]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| RSQRTSS:| __m128 _mm_rsqrt_ss(__m128 a)

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5.


platform: x86
mnem: SAHF
description:
SAHF - Store AH into Flags:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| 9E     | SAHF       | NP   | Invalid*   | Valid          | Loads SF, ZF, AF, PF, and CF from AH
|        |            |      |            |                | into EFLAGS register.               
Notes: * Valid in specific steppings. See Description section.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from
the corresponding bits in the AH register (bits 7, 6, 4, 2, and 0, respectively).
Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved bits
(1, 3, and 5) in the EFLAGS register remain as shown in the “Operation” section
below.

This instruction executes as described above in compatibility mode and legacy
mode. It is valid in 64-bit mode only if CPUID.80000001H:ECX.LAHF-SAHF[bit 0]
= 1.

Operation:

IF IA-64 Mode
  THEN
     IF CPUID.80000001H.ECX[0] = 1;
       THEN
          RFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;
       ELSE
          #UD;
     FI
  ELSE
     EFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;
FI;

Flags Affected:
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register.
Bits 1, 3, and 5 of the EFLAGS register are unaffected, with the values remaining
1, 0, and 0, respectively.


Protected Mode Exceptions:
None.


Real-Address Mode Exceptions:
None.


Virtual-8086 Mode Exceptions:
None.


Compatibility Mode Exceptions:
None.


64-Bit Mode Exceptions:
| #UD| If CPUID.80000001H.ECX[0] = 0. If the
|    | LOCK prefix is used.                 


platform: x86
mnem: SAL
description:
SAL/SAR/SHL/SHR - Shift:
| Opcode***       | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| D0 /4           | SAL r/m8, 1     | M1   | Valid      | Valid          | Multiply r/m8 by 2, once.              
| REX + D0 /4     | SAL r/m8**, 1   | M1   | Valid      | N.E.           | Multiply r/m8 by 2, once.              
| D2 /4           | SAL r/m8, CL    | MC   | Valid      | Valid          | Multiply r/m8 by 2, CL times.          
| REX + D2 /4     | SAL r/m8**, CL  | MC   | Valid      | N.E.           | Multiply r/m8 by 2, CL times.          
| C0 /4 ib        | SAL r/m8, imm8  | MI   | Valid      | Valid          | Multiply r/m8 by 2, imm8 times.        
| REX + C0 /4 ib  | SAL r/m8**, imm8| MI   | Valid      | N.E.           | Multiply r/m8 by 2, imm8 times.        
| D1 /4           | SAL r/m16, 1    | M1   | Valid      | Valid          | Multiply r/m16 by 2, once.             
| D3 /4           | SAL r/m16, CL   | MC   | Valid      | Valid          | Multiply r/m16 by 2, CL times.         
| C1 /4 ib        | SAL r/m16, imm8 | MI   | Valid      | Valid          | Multiply r/m16 by 2, imm8 times.       
| D1 /4           | SAL r/m32, 1    | M1   | Valid      | Valid          | Multiply r/m32 by 2, once.             
| REX.W + D1 /4   | SAL r/m64, 1    | M1   | Valid      | N.E.           | Multiply r/m64 by 2, once.             
| D3 /4           | SAL r/m32, CL   | MC   | Valid      | Valid          | Multiply r/m32 by 2, CL times.         
| REX.W + D3 /4   | SAL r/m64, CL   | MC   | Valid      | N.E.           | Multiply r/m64 by 2, CL times.         
| C1 /4 ib        | SAL r/m32, imm8 | MI   | Valid      | Valid          | Multiply r/m32 by 2, imm8 times.       
| REX.W + C1 /4 ib| SAL r/m64, imm8 | MI   | Valid      | N.E.           | Multiply r/m64 by 2, imm8 times.       
| D0 /7           | SAR r/m8, 1     | M1   | Valid      | Valid          | Signed divide* r/m8 by 2, once.        
| REX + D0 /7     | SAR r/m8**, 1   | M1   | Valid      | N.E.           | Signed divide* r/m8 by 2, once.        
| D2 /7           | SAR r/m8, CL    | MC   | Valid      | Valid          | Signed divide* r/m8 by 2, CL times.    
| REX + D2 /7     | SAR r/m8**, CL  | MC   | Valid      | N.E.           | Signed divide* r/m8 by 2, CL times.    
| C0 /7 ib        | SAR r/m8, imm8  | MI   | Valid      | Valid          | Signed divide* r/m8 by 2, imm8 time.   
| REX + C0 /7 ib  | SAR r/m8**, imm8| MI   | Valid      | N.E.           | Signed divide* r/m8 by 2, imm8 times.  
| D1 /7           | SAR r/m16,1     | M1   | Valid      | Valid          | Signed divide* r/m16 by 2, once.       
| D3 /7           | SAR r/m16, CL   | MC   | Valid      | Valid          | Signed divide* r/m16 by 2, CL times.   
| C1 /7 ib        | SAR r/m16, imm8 | MI   | Valid      | Valid          | Signed divide* r/m16 by 2, imm8 times. 
| D1 /7           | SAR r/m32, 1    | M1   | Valid      | Valid          | Signed divide* r/m32 by 2, once.       
| REX.W + D1 /7   | SAR r/m64, 1    | M1   | Valid      | N.E.           | Signed divide* r/m64 by 2, once.       
| D3 /7           | SAR r/m32, CL   | MC   | Valid      | Valid          | Signed divide* r/m32 by 2, CL times.   
| REX.W + D3 /7   | SAR r/m64, CL   | MC   | Valid      | N.E.           | Signed divide* r/m64 by 2, CL times.   
| C1 /7 ib        | SAR r/m32, imm8 | MI   | Valid      | Valid          | Signed divide* r/m32 by 2, imm8 times. 
| REX.W + C1 /7 ib| SAR r/m64, imm8 | MI   | Valid      | N.E.           | Signed divide* r/m64 by 2, imm8 times  
| D0 /4           | SHL r/m8, 1     | M1   | Valid      | Valid          | Multiply r/m8 by 2, once.              
| REX + D0 /4     | SHL r/m8**, 1   | M1   | Valid      | N.E.           | Multiply r/m8 by 2, once.              
| D2 /4           | SHL r/m8, CL    | MC   | Valid      | Valid          | Multiply r/m8 by 2, CL times.          
| REX + D2 /4     | SHL r/m8**, CL  | MC   | Valid      | N.E.           | Multiply r/m8 by 2, CL times.          
| C0 /4 ib        | SHL r/m8, imm8  | MI   | Valid      | Valid          | Multiply r/m8 by 2, imm8 times.        
| REX + C0 /4 ib  | SHL r/m8**, imm8| MI   | Valid      | N.E.           | Multiply r/m8 by 2, imm8 times.        
| D1 /4           | SHL r/m16,1     | M1   | Valid      | Valid          | Multiply r/m16 by 2, once.             
| D3 /4           | SHL r/m16, CL   | MC   | Valid      | Valid          | Multiply r/m16 by 2, CL times.         
| C1 /4 ib        | SHL r/m16, imm8 | MI   | Valid      | Valid          | Multiply r/m16 by 2, imm8 times.       
| D1 /4           | SHL r/m32,1     | M1   | Valid      | Valid          | Multiply r/m32 by 2, once.             
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| REX.W + D1 /4   | SHL r/m64,1     | M1   | Valid      | N.E.           | Multiply r/m64 by 2, once.             
| D3 /4           | SHL r/m32, CL   | MC   | Valid      | Valid          | Multiply r/m32 by 2, CL times.         
| REX.W + D3 /4   | SHL r/m64, CL   | MC   | Valid      | N.E.           | Multiply r/m64 by 2, CL times.         
| C1 /4 ib        | SHL r/m32, imm8 | MI   | Valid      | Valid          | Multiply r/m32 by 2, imm8 times.       
| REX.W + C1 /4 ib| SHL r/m64, imm8 | MI   | Valid      | N.E.           | Multiply r/m64 by 2, imm8 times.       
| D0 /5           | SHR r/m8,1      | M1   | Valid      | Valid          | Unsigned divide r/m8 by 2, once.       
| REX + D0 /5     | SHR r/m8**, 1   | M1   | Valid      | N.E.           | Unsigned divide r/m8 by 2, once.       
| D2 /5           | SHR r/m8, CL    | MC   | Valid      | Valid          | Unsigned divide r/m8 by 2, CL times.   
| REX + D2 /5     | SHR r/m8**, CL  | MC   | Valid      | N.E.           | Unsigned divide r/m8 by 2, CL times.   
| C0 /5 ib        | SHR r/m8, imm8  | MI   | Valid      | Valid          | Unsigned divide r/m8 by 2, imm8 times. 
| REX + C0 /5 ib  | SHR r/m8**, imm8| MI   | Valid      | N.E.           | Unsigned divide r/m8 by 2, imm8 times. 
| D1 /5           | SHR r/m16, 1    | M1   | Valid      | Valid          | Unsigned divide r/m16 by 2, once.      
| D3 /5           | SHR r/m16, CL   | MC   | Valid      | Valid          | Unsigned divide r/m16 by 2, CL times   
| C1 /5 ib        | SHR r/m16, imm8 | MI   | Valid      | Valid          | Unsigned divide r/m16 by 2, imm8 times.
| D1 /5           | SHR r/m32, 1    | M1   | Valid      | Valid          | Unsigned divide r/m32 by 2, once.      
| REX.W + D1 /5   | SHR r/m64, 1    | M1   | Valid      | N.E.           | Unsigned divide r/m64 by 2, once.      
| D3 /5           | SHR r/m32, CL   | MC   | Valid      | Valid          | Unsigned divide r/m32 by 2, CL times.  
| REX.W + D3 /5   | SHR r/m64, CL   | MC   | Valid      | N.E.           | Unsigned divide r/m64 by 2, CL times.  
| C1 /5 ib        | SHR r/m32, imm8 | MI   | Valid      | Valid          | Unsigned divide r/m32 by 2, imm8 times.
| REX.W + C1 /5 ib| SHR r/m64, imm8 | MI   | Valid      | N.E.           | Unsigned divide r/m64 by 2, imm8 times.
Notes: * Not the same form of division as IDIV; rounding is toward negative
infinity. ** In 64-bit mode, r/m8 can not be encoded to access the following
byte registers if a REX prefix is used: AH, BH, CH, DH. ***See IA-32 Architecture
Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2| Operand 3| Operand 4
| M1   | ModRM:r/m (r, w)| 1        | NA       | NA       
| MC   | ModRM:r/m (r, w)| CL       | NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8     | NA       | NA       

Description:
Shifts the bits in the first operand (destination operand) to the left or right
by the number of bits specified in the second operand (count operand). Bits
shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains
the last bit shifted out of the destination operand.

The destination operand can be a register or a memory location. The count operand
can be an immediate value or the CL register. The count is masked to 5 bits
(or 6 bits if in 64-bit mode and REX.W is used). The count range is limited
to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding
is provided for a count of 1.

The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform
the same operation; they shift the bits in the destination operand to the left
(toward more significant bit locations). For each shift count, the most significant
bit of the destination operand is shifted into the CF flag, and the least significant
bit is cleared (see Figure 7-7 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1).

The shift arithmetic right (SAR) and shift logical right (SHR) instructions
shift the bits of the destination operand to the right (toward less significant
bit locations). For each shift count, the least significant bit of the destination
operand is shifted into the CF flag, and the most significant bit is either
set or cleared depending on the instruction type. The SHR instruction clears
the most significant bit (see Figure 7-8 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1); the SAR instruction sets or clears the
most significant bit to correspond to the sign (most significant bit) of the
original value in the destination operand. In effect, the SAR instruction fills
the empty bit position's shifted value with the sign of the unshifted value
(see Figure 7-9 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1).

The SAR and SHR instructions can be used to perform signed or unsigned division,
respectively, of the destination operand by powers of 2. For example, using
the SAR instruction to shift a signed integer 1 bit to the right divides the
value by 2.

Using the SAR instruction to perform a division operation does not produce the
same result as the IDIV instruction. The quotient from the IDIV instruction
is rounded toward zero, whereas the “quotient” of the SAR instruction is rounded
toward negative infinity. This difference is apparent only for negative numbers.
For example, when the IDIV instruction is used to divide -9 by 4, the result
is -2 with a remainder of -1. If the SAR instruction is used to shift -9 right
by two bits, the result is -3 and the “remainder” is +3; however, the SAR instruction
stores only the most significant bit of the remainder (in the CF flag).

The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is
set to 0 if the most-significant bit of the result is the same as the CF flag
(that is, the top two bits of the original operand were the same); otherwise,
it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit
shifts. For the SHR instruction, the OF flag is set to the most-significant
bit of the original operand.

In 64-bit mode, the instruction's default operation size is 32 bits and the
mask width for CL is 5 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W
promotes operation to 64-bits and sets the mask width for CL to 6 bits. See
the summary chart at the beginning of this section for encoding data and limits.


IA-32 Architecture Compatibility:
The 8086 does not mask the shift count. However, all other IA-32 processors
(starting with the Intel 286 processor) do mask the shift count to 5 bits, resulting
in a maximum count of 31. This masking is done in all operating modes (including
the virtual-8086 mode) to reduce the maximum execution time of the instructions.

Operation:

IF 64-Bit Mode and using REX.W
  THEN
     countMASK <- 3FH;
  ELSE
     countMASK <- 1FH;
FI
tempCOUNT <- (COUNT AND countMASK);
tempDEST <- DEST;
WHILE (tempCOUNT != 0)
DO
  IF instruction is SAL or SHL
     THEN
       CF <- MSB(DEST);
     ELSE (* Instruction is SAR or SHR *)
       CF <- LSB(DEST);
  FI;
  IF instruction is SAL or SHL
     THEN
       DEST <- DEST * 2;
     ELSE
       IF instruction is SAR
          THEN
             DEST <- DEST / 2; (* Signed divide, rounding toward negative infinity *)
          ELSE (* Instruction is SHR *)
             DEST <- DEST / 2 ; (* Unsigned divide *)
       FI;
  FI;
  tempCOUNT <- tempCOUNT - 1;
OD;
(* Determine overflow for the various instructions *)
IF (COUNT and countMASK) = 1
  THEN
     IF instruction is SAL or SHL
       THEN
          OF <- MSB(DEST) XOR CF;
       ELSE
          IF instruction is SAR
             THEN
               OF <- 0;
             ELSE (* Instruction is SHR *)
               OF <- MSB(tempDEST);
          FI;
     FI;
  ELSE IF (COUNT AND countMASK) = 0
     THEN
       All flags unchanged;
     ELSE (* COUNT not 1 or 0 *)
       OF <- undefined;
  FI;
FI;

Flags Affected:
The CF flag contains the value of the last bit shifted out of the destination
operand; it is undefined for SHL and SHR instructions where the count is greater
than or equal to the size (in bits) of the destination operand. The OF flag
is affected only for 1-bit shifts (see “Description” above); otherwise, it is
undefined. The SF, ZF, and PF flags are set according to the result. If the
count is 0, the flags are not affected. For a non-zero count, the AF flag is
undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SARX
description:
SARX/SHLX/SHRX  -  Shift Without Affecting Flags:
| Opcode/Instruction                     | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                           
| VEX.NDS1.LZ.F3.0F38.W0 F7 /r SARX r32a,| RMV  | V/V            | BMI2              | Shift r/m32 arithmetically right with 
| r/m32, r32b                            |      |                |                   | count specified in r32b.              
| VEX.NDS1.LZ.66.0F38.W0 F7 /r SHLX r32a,| RMV  | V/V            | BMI2              | Shift r/m32 logically left with count 
| r/m32, r32b                            |      |                |                   | specified in r32b.                    
| VEX.NDS1.LZ.F2.0F38.W0 F7 /r SHRX r32a,| RMV  | V/V            | BMI2              | Shift r/m32 logically right with count
| r/m32, r32b                            |      |                |                   | specified in r32b.                    
| VEX.NDS1.LZ.F3.0F38.W1 F7 /r SARX r64a,| RMV  | V/N.E.         | BMI2              | Shift r/m64 arithmetically right with 
| r/m64, r64b                            |      |                |                   | count specified in r64b.              
| VEX.NDS1.LZ.66.0F38.W1 F7 /r SHLX r64a,| RMV  | V/N.E.         | BMI2              | Shift r/m64 logically left with count 
| r/m64, r64b                            |      |                |                   | specified in r64b.                    
| VEX.NDS1.LZ.F2.0F38.W1 F7 /r SHRX r64a,| RMV  | V/N.E.         | BMI2              | Shift r/m64 logically right with count
| r/m64, r64b                            |      |                |                   | specified in r64b.                    
Notes: 1. ModRM:r/m is used to encode the first source operand (second operand)
and VEX.vvvv encodes the second source operand (third operand).


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3   | Operand 4
| RMV  | ModRM:reg (w)| ModRM:r/m (r)| VEX.vvvv (r)| NA       

Description:
Shifts the bits of the first source operand (the second operand) to the left
or right by a COUNT value specified in the second source operand (the third
operand). The result is written to the destination operand (the first operand).
The shift arithmetic right (SARX) and shift logical right (SHRX) instructions
shift the bits of the destination operand to the right (toward less significant
bit locations), SARX keeps and propagates the most significant bit (sign bit)
while shifting. The logical shift left (SHLX) shifts the bits of the destination
operand to the left (toward more significant bit locations). This instruction
is not supported in real mode and virtual-8086 mode. The operand size is always
32 bits if not in 64-bit mode. In 64-bit mode operand size 64 requires VEX.W1.
VEX.W1 is ignored in non-64-bit modes. An attempt to execute this instruction
with VEX.L not equal to 0 will cause #UD. If the value specified in the first
source operand exceeds OperandSize -1, the COUNT value is masked. SARX,SHRX,
and SHLX instructions do not update flags.

Operation:

TEMP <- SRC1;
IF VEX.W1 and CS.L = 1
THEN
  countMASK <-3FH;
ELSE
  countMASK <-1FH;
FI
COUNT <- (SRC2 AND countMASK)
DEST[OperandSize -1] = TEMP[OperandSize -1];
DO WHILE (COUNT != 0)
  IF instruction is SHLX
     THEN
       DEST[] <- DEST *2;
     ELSE IF instruction is SHRX
       THEN
          DEST[] <- DEST /2; //unsigned divide
     ELSE
          DEST[] <- DEST /2; // signed divide, round toward negative infinity
  FI;
  COUNT <- COUNT - 1;
OD

Flags Affected:
None.


Intel C/C++ Compiler Intrinsic Equivalent:
Auto-generated from high-level language.


SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Section 2.5.1, “Exception Conditions for VEX-Encoded GPR Instructions”,
Table 2-29; additionally

| #UD| If VEX.W = 1.


platform: x86
mnem: SBB
description:
SBB - Integer Subtraction with Borrow:
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 1C ib           | SBB AL, imm8    | I    | Valid      | Valid          | Subtract with borrow imm8 from AL.       
| 1D iw           | SBB AX, imm16   | I    | Valid      | Valid          | Subtract with borrow imm16 from AX.      
| 1D id           | SBB EAX, imm32  | I    | Valid      | Valid          | Subtract with borrow imm32 from EAX.     
| REX.W + 1D id   | SBB RAX, imm32  | I    | Valid      | N.E.           | Subtract with borrow sign-extended imm.32
|                 |                 |      |            |                | to 64-bits from RAX.                     
| 80 /3 ib        | SBB r/m8, imm8  | MI   | Valid      | Valid          | Subtract with borrow imm8 from r/m8.     
| REX + 80 /3 ib  | SBB r/m8*, imm8 | MI   | Valid      | N.E.           | Subtract with borrow imm8 from r/m8.     
| 81 /3 iw        | SBB r/m16, imm16| MI   | Valid      | Valid          | Subtract with borrow imm16 from r/m16.   
| 81 /3 id        | SBB r/m32, imm32| MI   | Valid      | Valid          | Subtract with borrow imm32 from r/m32.   
| REX.W + 81 /3 id| SBB r/m64, imm32| MI   | Valid      | N.E.           | Subtract with borrow sign-extended imm32 
|                 |                 |      |            |                | to 64-bits from r/m64.                   
| 83 /3 ib        | SBB r/m16, imm8 | MI   | Valid      | Valid          | Subtract with borrow sign-extended imm8  
|                 |                 |      |            |                | from r/m16.                              
| 83 /3 ib        | SBB r/m32, imm8 | MI   | Valid      | Valid          | Subtract with borrow sign-extended imm8  
|                 |                 |      |            |                | from r/m32.                              
| REX.W + 83 /3 ib| SBB r/m64, imm8 | MI   | Valid      | N.E.           | Subtract with borrow sign-extended imm8  
|                 |                 |      |            |                | from r/m64.                              
| 18 /r           | SBB r/m8, r8    | MR   | Valid      | Valid          | Subtract with borrow r8 from r/m8.       
| REX + 18 /r     | SBB r/m8*, r8   | MR   | Valid      | N.E.           | Subtract with borrow r8 from r/m8.       
| 19 /r           | SBB r/m16, r16  | MR   | Valid      | Valid          | Subtract with borrow r16 from r/m16.     
| 19 /r           | SBB r/m32, r32  | MR   | Valid      | Valid          | Subtract with borrow r32 from r/m32.     
| REX.W + 19 /r   | SBB r/m64, r64  | MR   | Valid      | N.E.           | Subtract with borrow r64 from r/m64.     
| 1A /r           | SBB r8, r/m8    | RM   | Valid      | Valid          | Subtract with borrow r/m8 from r8.       
| REX + 1A /r     | SBB r8*, r/m8*  | RM   | Valid      | N.E.           | Subtract with borrow r/m8 from r8.       
| 1B /r           | SBB r16, r/m16  | RM   | Valid      | Valid          | Subtract with borrow r/m16 from r16.     
| 1B /r           | SBB r32, r/m32  | RM   | Valid      | Valid          | Subtract with borrow r/m32 from r32.     
| REX.W + 1B /r   | SBB r64, r/m64  | RM   | Valid      | N.E.           | Subtract with borrow r/m64 from r64.     
Notes: 

| *| In 64-bit mode, r/m8 can not be encoded
|  | to access the following byte registers 
|  | if a REX prefix is used: AH, BH, CH,   
|  | DH.                                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| I    | AL/AX/EAX/RAX| imm8/16/32   | NA       | NA       
| MI   | ModRM:r/m (w)| imm8/16/32   | NA       | NA       
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Adds the source operand (second operand) and the carry (CF) flag, and subtracts
the result from the destination operand (first operand). The result of the subtraction
is stored in the destination operand. The destination operand can be a register
or a memory location; the source operand can be an immediate, a register, or
a memory location. (However, two memory operands cannot be used in one instruction.)
The state of the CF flag represents a borrow from a previous subtraction.

When an immediate value is used as an operand, it is sign-extended to the length
of the destination operand format.

The SBB instruction does not distinguish between signed or unsigned operands.
Instead, the processor evaluates the result for both data types and sets the
OF and CF flags to indicate a borrow in the signed or unsigned result, respectively.
The SF flag indicates the sign of the signed result.

The SBB instruction is usually executed as part of a multibyte or multiword
subtraction in which a SUB instruction is followed by a SBB instruction.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

Operation:

DEST <- (DEST - (SRC + CF));

Intel C/C++ Compiler Intrinsic Equivalent:
| SBB:                    | extern unsigned char _subborrow_u8(unsigned 
|                         | char c_in, unsigned char src1, unsigned     
|                         | char src2, unsigned char *diff_out);        
| SBB: *diff_out);        | extern unsigned char _subborrow_u16(unsigned
|                         | char c_in, unsigned short src1, unsigned    
|                         | short src2, unsigned short                  
| SBB:                    | extern unsigned char _subborrow_u32(unsigned
|                         | char c_in, unsigned int src1, unsigned      
|                         | char int, unsigned int *diff_out);          
| SBB: __int64 *diff_out);| extern unsigned char _subborrow_u64(unsigned
|                         | char c_in, unsigned __int64 src1, unsigned  
|                         | __int64 src2, unsigned                      

Flags Affected:
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used but the destination 
|                | is not a memory operand.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: SCAS
description:
SCAS/SCASB/SCASW/SCASD - Scan String:
| Opcode    | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| AE        | SCAS m8    | NP   | Valid      | Valid          | Compare AL with byte at ES:(E)DI or    
|           |            |      |            |                | RDI, then set status flags.*           
| AF        | SCAS m16   | NP   | Valid      | Valid          | Compare AX with word at ES:(E)DI or    
|           |            |      |            |                | RDI, then set status flags.*           
| AF        | SCAS m32   | NP   | Valid      | Valid          | Compare EAX with doubleword at ES(E)DI 
|           |            |      |            |                | or RDI then set status flags.*         
| REX.W + AF| SCAS m64   | NP   | Valid      | N.E.           | Compare RAX with quadword at RDI or    
|           |            |      |            |                | EDI then set status flags.             
| AE        | SCASB      | NP   | Valid      | Valid          | Compare AL with byte at ES:(E)DI or    
|           |            |      |            |                | RDI then set status flags.*            
| AF        | SCASW      | NP   | Valid      | Valid          | Compare AX with word at ES:(E)DI or    
|           |            |      |            |                | RDI then set status flags.*            
| AF        | SCASD      | NP   | Valid      | Valid          | Compare EAX with doubleword at ES:(E)DI
|           |            |      |            |                | or RDI then set status flags.*         
| REX.W + AF| SCASQ      | NP   | Valid      | N.E.           | Compare RAX with quadword at RDI or    
|           |            |      |            |                | EDI then set status flags.             
Notes: * In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are
supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI) address sizes
are supported.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
In non-64-bit modes and in default 64-bit mode: this instruction compares a
byte, word, doubleword or quadword specified using a memory operand with the
value in AL, AX, or EAX. It then sets status flags in EFLAGS recording the results.
The memory operand address is read from ES:(E)DI register (depending on the
address-size attribute of the instruction and the current operational mode).
Note that ES cannot be overridden with a segment override prefix.

At the assembly-code level, two forms of this instruction are allowed. The explicit-operand
form and the no-operands form. The explicit-operand form (specified using the
SCAS mnemonic) allows a memory operand to be specified explicitly. The memory
operand must be a symbol that indicates the size and location of the operand
value. The register operand is then automatically selected to match the size
of the memory operand (AL register for byte comparisons, AX for word comparisons,
EAX for doubleword comparisons). The explicit-operand form is provided to allow
documentation. Note that the documentation provided by this form can be misleading.
That is, the memory operand symbol must specify the correct type (size) of the
operand (byte, word, or doubleword) but it does not have to specify the correct
location. The location is always specified by ES:(E)DI.

The no-operands form of the instruction uses a short form of SCAS. Again, ES:(E)DI
is assumed to be the memory operand and AL, AX, or EAX is assumed to be the
register operand. The size of operands is selected by the mnemonic: SCASB (byte
comparison), SCASW (word comparison), or SCASD (doubleword comparison).

After the comparison, the (E)DI register is incremented or decremented automatically
according to the setting of the DF flag in the EFLAGS register. If the DF flag
is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI register
is decremented. The register is incremented or decremented by 1 for byte operations,
by 2 for word operations, and by 4 for doubleword operations.

SCAS, SCASB, SCASW, SCASD, and SCASQ can be preceded by the REP prefix for block
comparisons of ECX bytes, words, doublewords, or quadwords. Often, however,
these instructions will be used in a LOOP construct that takes

some action based on the setting of status flags. See “REP/REPE/REPZ /REPNE/REPNZ - Repeat
String Operation Prefix” in this chapter for a description of the REP prefix.

In 64-bit mode, the instruction's default address size is 64-bits, 32-bit address
size is supported using the prefix 67H. Using a REX prefix in the form of REX.W
promotes operation on doubleword operand to 64 bits. The 64-bit nooperand mnemonic
is SCASQ. Address of the memory operand is specified in either RDI or EDI, and
AL/AX/EAX/RAX may be used as the register operand. After a comparison, the destination
register is incremented or decremented by the current operand size (depending
on the value of the DF flag). See the summary chart at the beginning of this
section for encoding data and limits.

Operation:

Non-64-bit Mode:
IF (Byte comparison)
  THEN
     temp <- AL − SRC;
     SetStatusFlags(temp);
       THEN IF DF = 0
          THEN (E)DI <- (E)DI + 1;
          ELSE (E)DI <- (E)DI - 1; FI;
  ELSE IF (Word comparison)
     THEN
       temp <- AX − SRC;
       SetStatusFlags(temp);
       IF DF = 0
          THEN (E)DI <- (E)DI + 2;
          ELSE (E)DI <- (E)DI - 2; FI;
     FI;
  ELSE IF (Doubleword comparison)
     THEN
       temp <- EAX - SRC;
       SetStatusFlags(temp);
       IF DF = 0
          THEN (E)DI <- (E)DI + 4;
          ELSE (E)DI <- (E)DI - 4; FI;
     FI;
FI;
64-bit Mode:
IF (Byte cmparison)
  THEN
     temp <- AL − SRC;
     SetStatusFlags(temp);
       THEN IF DF = 0
          THEN (R|E)DI <- (R|E)DI + 1;
          ELSE (R|E)DI <- (R|E)DI - 1; FI;
  ELSE IF (Word comparison)
     THEN
       temp <- AX − SRC;
       SetStatusFlags(temp);
       IF DF = 0
          THEN (R|E)DI <- (R|E)DI + 2;
          ELSE (R|E)DI <- (R|E)DI - 2; FI;
     FI;
  ELSE IF (Doubleword comparison)
     THEN
       temp <- EAX - SRC;
       SetStatusFlags(temp);
       IF DF = 0
          THEN (R|E)DI <- (R|E)DI + 4;
          ELSE (R|E)DI <- (R|E)DI - 4; FI;
     FI;
  ELSE IF (Quadword comparison using REX.W )
     THEN
       temp <- RAX − SRC;
       SetStatusFlags(temp);
       IF DF = 0
          THEN (R|E)DI <- (R|E)DI + 8;
          ELSE (R|E)DI <- (R|E)DI - 8;
       FI;
  FI;
F

Flags Affected:
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result
of the comparison.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address     
|                | is outside the limit of the ES segment.   
|                | If the ES register contains a NULL segment
|                | selector. If an illegal memory operand    
|                | effective address in the ES segment       
|                | is given.                                 
| #PF(fault-code)| If a page fault occurs.                   
| #AC(0)         | If alignment checking is enabled and      
|                | an unaligned memory reference is made     
|                | while the current privilege level is      
|                | 3.                                        
| #UD            | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SETcc
description:
SETcc - Set Byte on Condition:
| Opcode     | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 0F 97      | SETA r/m8   | M    | Valid      | Valid          | Set byte if above (CF=0 and ZF=0).    
| REX + 0F 97| SETA r/m8*  | M    | Valid      | N.E.           | Set byte if above (CF=0 and ZF=0).    
| 0F 93      | SETAE r/m8  | M    | Valid      | Valid          | Set byte if above or equal (CF=0).    
| REX + 0F 93| SETAE r/m8* | M    | Valid      | N.E.           | Set byte if above or equal (CF=0).    
| 0F 92      | SETB r/m8   | M    | Valid      | Valid          | Set byte if below (CF=1).             
| REX + 0F 92| SETB r/m8*  | M    | Valid      | N.E.           | Set byte if below (CF=1).             
| 0F 96      | SETBE r/m8  | M    | Valid      | Valid          | Set byte if below or equal (CF=1 or   
|            |             |      |            |                | ZF=1).                                
| REX + 0F 96| SETBE r/m8* | M    | Valid      | N.E.           | Set byte if below or equal (CF=1 or   
|            |             |      |            |                | ZF=1).                                
| 0F 92      | SETC r/m8   | M    | Valid      | Valid          | Set byte if carry (CF=1).             
| REX + 0F 92| SETC r/m8*  | M    | Valid      | N.E.           | Set byte if carry (CF=1).             
| 0F 94      | SETE r/m8   | M    | Valid      | Valid          | Set byte if equal (ZF=1).             
| REX + 0F 94| SETE r/m8*  | M    | Valid      | N.E.           | Set byte if equal (ZF=1).             
| 0F 9F      | SETG r/m8   | M    | Valid      | Valid          | Set byte if greater (ZF=0 and SF=OF). 
| REX + 0F 9F| SETG r/m8*  | M    | Valid      | N.E.           | Set byte if greater (ZF=0 and SF=OF). 
| 0F 9D      | SETGE r/m8  | M    | Valid      | Valid          | Set byte if greater or equal (SF=OF). 
| REX + 0F 9D| SETGE r/m8* | M    | Valid      | N.E.           | Set byte if greater or equal (SF=OF). 
| 0F 9C      | SETL r/m8   | M    | Valid      | Valid          | Set byte if less (SF!= OF).            
| REX + 0F 9C| SETL r/m8*  | M    | Valid      | N.E.           | Set byte if less (SF!= OF).            
| 0F 9E      | SETLE r/m8  | M    | Valid      | Valid          | Set byte if less or equal (ZF=1 or SF!=
|            |             |      |            |                | OF).                                  
| REX + 0F 9E| SETLE r/m8* | M    | Valid      | N.E.           | Set byte if less or equal (ZF=1 or SF!=
|            |             |      |            |                | OF).                                  
| 0F 96      | SETNA r/m8  | M    | Valid      | Valid          | Set byte if not above (CF=1 or ZF=1). 
| REX + 0F 96| SETNA r/m8* | M    | Valid      | N.E.           | Set byte if not above (CF=1 or ZF=1). 
| 0F 92      | SETNAE r/m8 | M    | Valid      | Valid          | Set byte if not above or equal (CF=1).
| REX + 0F 92| SETNAE r/m8*| M    | Valid      | N.E.           | Set byte if not above or equal (CF=1).
| 0F 93      | SETNB r/m8  | M    | Valid      | Valid          | Set byte if not below (CF=0).         
| REX + 0F 93| SETNB r/m8* | M    | Valid      | N.E.           | Set byte if not below (CF=0).         
| 0F 97      | SETNBE r/m8 | M    | Valid      | Valid          | Set byte if not below or equal (CF=0  
|            |             |      |            |                | and ZF=0).                            
| REX + 0F 97| SETNBE r/m8*| M    | Valid      | N.E.           | Set byte if not below or equal (CF=0  
|            |             |      |            |                | and ZF=0).                            
| 0F 93      | SETNC r/m8  | M    | Valid      | Valid          | Set byte if not carry (CF=0).         
| REX + 0F 93| SETNC r/m8* | M    | Valid      | N.E.           | Set byte if not carry (CF=0).         
| 0F 95      | SETNE r/m8  | M    | Valid      | Valid          | Set byte if not equal (ZF=0).         
| REX + 0F 95| SETNE r/m8* | M    | Valid      | N.E.           | Set byte if not equal (ZF=0).         
| 0F 9E      | SETNG r/m8  | M    | Valid      | Valid          | Set byte if not greater (ZF=1 or SF!=  
|            |             |      |            |                | OF)                                   
| REX + 0F 9E| SETNG r/m8* | M    | Valid      | N.E.           | Set byte if not greater (ZF=1 or SF!=  
|            |             |      |            |                | OF).                                  
| 0F 9C      | SETNGE r/m8 | M    | Valid      | Valid          | Set byte if not greater or equal (SF!= 
|            |             |      |            |                | OF).                                  
| REX + 0F 9C| SETNGE r/m8*| M    | Valid      | N.E.           | Set byte if not greater or equal (SF!= 
|            |             |      |            |                | OF).                                  
| 0F 9D      | SETNL r/m8  | M    | Valid      | Valid          | Set byte if not less (SF=OF).         
| REX + 0F 9D| SETNL r/m8* | M    | Valid      | N.E.           | Set byte if not less (SF=OF).         
| 0F 9F      | SETNLE r/m8 | M    | Valid      | Valid          | Set byte if not less or equal (ZF=0   
|            |             |      |            |                | and SF=OF).                           
| Opcode     | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| REX + 0F 9F| SETNLE r/m8*| M    | Valid      | N.E.           | Set byte if not less or equal (ZF=0   
|            |             |      |            |                | and SF=OF).                           
| 0F 91      | SETNO r/m8  | M    | Valid      | Valid          | Set byte if not overflow (OF=0).      
| REX + 0F 91| SETNO r/m8* | M    | Valid      | N.E.           | Set byte if not overflow (OF=0).      
| 0F 9B      | SETNP r/m8  | M    | Valid      | Valid          | Set byte if not parity (PF=0).        
| REX + 0F 9B| SETNP r/m8* | M    | Valid      | N.E.           | Set byte if not parity (PF=0).        
| 0F 99      | SETNS r/m8  | M    | Valid      | Valid          | Set byte if not sign (SF=0).          
| REX + 0F 99| SETNS r/m8* | M    | Valid      | N.E.           | Set byte if not sign (SF=0).          
| 0F 95      | SETNZ r/m8  | M    | Valid      | Valid          | Set byte if not zero (ZF=0).          
| REX + 0F 95| SETNZ r/m8* | M    | Valid      | N.E.           | Set byte if not zero (ZF=0).          
| 0F 90      | SETO r/m8   | M    | Valid      | Valid          | Set byte if overflow (OF=1)           
| REX + 0F 90| SETO r/m8*  | M    | Valid      | N.E.           | Set byte if overflow (OF=1).          
| 0F 9A      | SETP r/m8   | M    | Valid      | Valid          | Set byte if parity (PF=1).            
| REX + 0F 9A| SETP r/m8*  | M    | Valid      | N.E.           | Set byte if parity (PF=1).            
| 0F 9A      | SETPE r/m8  | M    | Valid      | Valid          | Set byte if parity even (PF=1).       
| REX + 0F 9A| SETPE r/m8* | M    | Valid      | N.E.           | Set byte if parity even (PF=1).       
| 0F 9B      | SETPO r/m8  | M    | Valid      | Valid          | Set byte if parity odd (PF=0).        
| REX + 0F 9B| SETPO r/m8* | M    | Valid      | N.E.           | Set byte if parity odd (PF=0).        
| 0F 98      | SETS r/m8   | M    | Valid      | Valid          | Set byte if sign (SF=1).              
| REX + 0F 98| SETS r/m8*  | M    | Valid      | N.E.           | Set byte if sign (SF=1).              
| 0F 94      | SETZ r/m8   | M    | Valid      | Valid          | Set byte if zero (ZF=1).              
| REX + 0F 94| SETZ r/m8*  | M    | Valid      | N.E.           | Set byte if zero (ZF=1).              
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Sets the destination operand to 0 or 1 depending on the settings of the status
flags (CF, SF, OF, ZF, and PF) in the EFLAGS register. The destination operand
points to a byte register or a byte in memory. The condition code suffix (cc)
indicates the condition being tested for.

The terms “above” and “below” are associated with the CF flag and refer to the
relationship between two unsigned integer values. The terms “greater” and “less”
are associated with the SF and OF flags and refer to the relationship between
two signed integer values.

Many of the SETcc instruction opcodes have alternate mnemonics. For example,
SETG (set byte if greater) and SETNLE (set if not less or equal) have the same
opcode and test for the same condition: ZF equals 0 and SF equals OF. These
alternate mnemonics are provided to make code more intelligible. Appendix B,
“EFLAGS Condition Codes,” in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, shows the alternate mnemonics for various test
conditions.

Some languages represent a logical one as an integer with all bits set. This
representation can be obtained by choosing the logically opposite condition
for the SETcc instruction, then decrementing the result. For example, to test
for overflow, use the SETNO instruction, then decrement the result.

In IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable
uniform addressing to additional byte registers. Otherwise, this instruction's
operation is the same as in legacy mode and compatibility mode.

Operation:

IF condition
  THEN DEST <- 1;
  ELSE DEST <- 0;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit.                       
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #UD            | If the LOCK prefix is used.          

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SFENCE
description:
SFENCE - Store Fence:
| Opcode* | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                 
| 0F AE /7| SFENCE     | NP   | Valid      | Valid          | Serializes store operations.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Performs a serializing operation on all store-to-memory instructions that were
issued prior the SFENCE instruction. This serializing operation guarantees that
every store instruction that precedes the SFENCE instruction in program order
becomes globally visible before any store instruction that follows the SFENCE
instruction. The SFENCE instruction is ordered with respect to store instructions,
other SFENCE instructions, any LFENCE and MFENCE instructions, and any serializing
instructions (such as the CPUID instruction). It is not ordered with respect
to load instructions.

Weakly ordered memory types can be used to achieve higher processor performance
through such techniques as out-of-order issue, write-combining, and write-collapsing.
The degree to which a consumer of data recognizes or knows that the data is
weakly ordered varies among applications and may be unknown to the producer
of this data. The SFENCE instruction provides a performance-efficient way of
ensuring store ordering between routines that produce weakly-ordered results
and routines that consume this data.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

Wait_On_Following_Stores_Until(preceding_stores_globally_visible);

Intel C/C++ Compiler Intrinsic Equivalent:
void _mm_sfence(void)


Exceptions (All Operating Modes):
| #UD| If CPUID.01H:EDX.SSE[bit 25] = 0. If
|    | the LOCK prefix is used.            


platform: x86
mnem: SGDT
description:
SGDT - Store Global Descriptor Table Register:
| Opcode* | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description     
| 0F 01 /0| SGDT m     | M    | Valid      | Valid          | Store GDTR to m.
Notes: * See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the content of the global descriptor table register (GDTR) in the destination
operand. The destination operand specifies a memory location.

In legacy or compatibility mode, the destination operand is a 6-byte memory
location. If the operand-size attribute is 16 bits, the limit is stored in the
low 2 bytes and the 24-bit base address is stored in bytes 3-5, and byte 6 is
zero-filled. If the operand-size attribute is 32 bits, the 16-bit limit field
of the register is stored in the low 2 bytes of the memory location and the
32-bit base address is stored in the high 4 bytes.

In IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores
an 8-byte base and a 2-byte limit.

SGDT is useful only by operating-system software. However, it can be used in
application programs without causing an exception to be generated. See “LGDT/LIDT - Load
Global/Interrupt Descriptor Table Register” in Chapter 3, Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 2A, for information on loading
the GDTR and IDTR.


IA-32 Architecture Compatibility:
The 16-bit form of the SGDT is compatible with the Intel 286 processor if the
upper 8 bits are not referenced. The Intel 286 processor fills these bits with
1s; the Pentium 4, Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386™
processors fill these bits with 0s.

Operation:

IF instruction is SGDT
     IF OperandSize = 16
       THEN
          DEST[0:15] <- GDTR(Limit);
          DEST[16:39] <- GDTR(Base); (* 24 bits of base address stored *)
          DEST[40:47] <- 0;
       ELSE IF (32-bit Operand Size)
          DEST[0:15] <- GDTR(Limit);
          DEST[16:47] <- GDTR(Base); (* Full 32-bit base address stored *)
          FI;
       ELSE (* 64-bit Operand Size *)
          DEST[0:15] <- GDTR(Limit);
          DEST[16:79] <- GDTR(Base); (* Full 64-bit base address stored *)
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #UD            | If the destination operand is a register.      
|                | If the LOCK prefix is used.                    
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             

Real-Address Mode Exceptions:
| #UD| If the destination operand is a register.
|    | If the LOCK prefix is used.              
| #GP| If a memory operand effective address    
|    | is outside the CS, DS, ES, FS, or GS     
|    | segment limit.                           
| #SS| If a memory operand effective address    
|    | is outside the SS segment limit.         

Virtual-8086 Mode Exceptions:
| #UD            | If the destination operand is a register.
|                | If the LOCK prefix is used.              
| #GP(0)         | If a memory operand effective address    
|                | is outside the CS, DS, ES, FS, or GS     
|                | segment limit.                           
| #SS(0)         | If a memory operand effective address    
|                | is outside the SS segment limit.         
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If alignment checking is enabled and     
|                | an unaligned memory reference is made.   

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #UD            | If the destination operand is a register.  
|                | If the LOCK prefix is used.                
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: SHLD
description:
SHLD - Double Precision Shift Left:
| Opcode*            | Instruction          | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 0F A4 /r ib        | SHLD r/m16, r16, imm8| MRI  | Valid      | Valid          | Shift r/m16 to left imm8 places while    
|                    |                      |      |            |                | shifting bits from r16 in from the right.
| 0F A5 /r           | SHLD r/m16, r16, CL  | MRC  | Valid      | Valid          | Shift r/m16 to left CL places while      
|                    |                      |      |            |                | shifting bits from r16 in from the right.
| 0F A4 /r ib        | SHLD r/m32, r32, imm8| MRI  | Valid      | Valid          | Shift r/m32 to left imm8 places while    
|                    |                      |      |            |                | shifting bits from r32 in from the right.
| REX.W + 0F A4 /r ib| SHLD r/m64, r64, imm8| MRI  | Valid      | N.E.           | Shift r/m64 to left imm8 places while    
|                    |                      |      |            |                | shifting bits from r64 in from the right.
| 0F A5 /r           | SHLD r/m32, r32, CL  | MRC  | Valid      | Valid          | Shift r/m32 to left CL places while      
|                    |                      |      |            |                | shifting bits from r32 in from the right.
| REX.W + 0F A5 /r   | SHLD r/m64, r64, CL  | MRC  | Valid      | N.E.           | Shift r/m64 to left CL places while      
|                    |                      |      |            |                | shifting bits from r64 in from the right.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MRI  | ModRM:r/m (w)| ModRM:reg (r)| imm8     | NA       
| MRC  | ModRM:r/m (w)| ModRM:reg (r)| CL       | NA       

Description:
The SHLD instruction is used for multi-precision shifts of 64 bits or more.

The instruction shifts the first operand (destination operand) to the left the
number of bits specified by the third operand (count operand). The second operand
(source operand) provides bits to shift in from the right (starting with bit
0 of the destination operand).

The destination operand can be a register or a memory location; the source operand
is a register. The count operand is an unsigned integer that can be stored in
an immediate byte or in the CL register. If the count operand is CL, the shift
count is the logical AND of CL and a count mask. In non-64-bit modes and default
64-bit mode; only bits 0 through 4 of the count are used. This masks the count
to a value between 0 and 31. If a count is greater than the operand size, the
result is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted
out of the destination operand. For a 1-bit shift, the OF flag is set if a sign
change occurred; otherwise, it is cleared. If the count operand is 0, flags
are not affected.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits (upgrading
the count mask to 6 bits). See the summary chart at the beginning of this section
for encoding data and limits.

Operation:

IF (In 64-Bit Mode and REX.W = 1)
  THEN COUNT <- COUNT MOD 64;
  ELSE COUNT <- COUNT MOD 32;
FI
SIZE <- OperandSize;
IF COUNT = 0
  THEN
     No operation;
  ELSE
     IF COUNT > SIZE
       THEN (* Bad parameters *)
          DEST is undefined;
          CF, OF, SF, ZF, AF, PF are undefined;
       ELSE (* Perform the shift *)
          CF <- BIT[DEST, SIZE - COUNT];
          (* Last bit shifted out on exit *)
          FOR i <- SIZE - 1 DOWN TO COUNT
             DO
               Bit(DEST, i) <- Bit(DEST, i - COUNT);
             OD;
          FOR i <- COUNT - 1 DOWN TO 0
             DO
               BIT[DEST, i] <- BIT[SRC, i - COUNT + SIZE];
             OD;
     FI;
FI;

Flags Affected:
If the count is 1 or greater, the CF flag is filled with the last bit shifted
out of the destination operand and the SF, ZF, and PF flags are set according
to the value of the result. For a 1-bit shift, the OF flag is set if a sign
change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the
OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count
operand is 0, the flags are not affected. If the count is greater than the operand
size, the flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SHRD
description:
SHRD - Double Precision Shift Right:
| Opcode*            | Instruction          | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F AC /r ib        | SHRD r/m16, r16, imm8| MRI  | Valid      | Valid          | Shift r/m16 to right imm8 places while  
|                    |                      |      |            |                | shifting bits from r16 in from the left.
| 0F AD /r           | SHRD r/m16, r16, CL  | MRC  | Valid      | Valid          | Shift r/m16 to right CL places while    
|                    |                      |      |            |                | shifting bits from r16 in from the left.
| 0F AC /r ib        | SHRD r/m32, r32, imm8| MRI  | Valid      | Valid          | Shift r/m32 to right imm8 places while  
|                    |                      |      |            |                | shifting bits from r32 in from the left.
| REX.W + 0F AC /r ib| SHRD r/m64, r64, imm8| MRI  | Valid      | N.E.           | Shift r/m64 to right imm8 places while  
|                    |                      |      |            |                | shifting bits from r64 in from the left.
| 0F AD /r           | SHRD r/m32, r32, CL  | MRC  | Valid      | Valid          | Shift r/m32 to right CL places while    
|                    |                      |      |            |                | shifting bits from r32 in from the left.
| REX.W + 0F AD /r   | SHRD r/m64, r64, CL  | MRC  | Valid      | N.E.           | Shift r/m64 to right CL places while    
|                    |                      |      |            |                | shifting bits from r64 in from the left.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MRI  | ModRM:r/m (w)| ModRM:reg (r)| imm8     | NA       
| MRC  | ModRM:r/m (w)| ModRM:reg (r)| CL       | NA       

Description:
The SHRD instruction is useful for multi-precision shifts of 64 bits or more.

The instruction shifts the first operand (destination operand) to the right
the number of bits specified by the third operand (count operand). The second
operand (source operand) provides bits to shift in from the left (starting with
the most significant bit of the destination operand).

The destination operand can be a register or a memory location; the source operand
is a register. The count operand is an unsigned integer that can be stored in
an immediate byte or the CL register. If the count operand is CL, the shift
count is the logical AND of CL and a count mask. In non-64-bit modes and default
64-bit mode, the width of the count mask is 5 bits. Only bits 0 through 4 of
the count register are used (masking the count to a value between 0 and 31).
If the count is greater than the operand size, the result is undefined.

If the count is 1 or greater, the CF flag is filled with the last bit shifted
out of the destination operand. For a 1-bit shift, the OF flag is set if a sign
change occurred; otherwise, it is cleared. If the count operand is 0, flags
are not affected.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits (upgrading
the count mask to 6 bits). See the summary chart at the beginning of this section
for encoding data and limits.

Operation:

IF (In 64-Bit Mode and REX.W = 1)
  THEN COUNT <- COUNT MOD 64;
  ELSE COUNT <- COUNT MOD 32;
FI
SIZE <- OperandSize;
IF COUNT = 0
  THEN
     No operation;
  ELSE
     IF COUNT > SIZE
       THEN (* Bad parameters *)
          DEST is undefined;
          CF, OF, SF, ZF, AF, PF are undefined;
       ELSE (* Perform the shift *)
          CF <- BIT[DEST, COUNT - 1]; (* Last bit shifted out on exit *)
          FOR i <- 0 TO SIZE - 1 - COUNT
             DO
               BIT[DEST, i] <- BIT[DEST, i + COUNT];
             OD;
          FOR i <- SIZE - COUNT TO SIZE - 1
             DO
               BIT[DEST,i] <- BIT[SRC, i + COUNT - SIZE];
             OD;
     FI;
FI;

Flags Affected:
If the count is 1 or greater, the CF flag is filled with the last bit shifted
out of the destination operand and the SF, ZF, and PF flags are set according
to the value of the result. For a 1-bit shift, the OF flag is set if a sign
change occurred; otherwise, it is cleared. For shifts greater than 1 bit, the
OF flag is undefined. If a shift occurs, the AF flag is undefined. If the count
operand is 0, the flags are not affected. If the count is greater than the operand
size, the flags are undefined.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SHUFPD
description:
SHUFPD - Shuffle Packed Double-Precision Floating-Point Values:
| Opcode*/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                  
| 66 0F C6 /r ib SHUFPD xmm1, xmm2/m128,| RMI  | V/V                   | SSE2              | Shuffle packed double-precision floatingpoint
| imm8                                  |      |                       |                   | values selected by imm8 from xmm1 and        
|                                       |      |                       |                   | xmm2/m128 to xmm1.                           
| VEX.NDS.128.66.0F.WIG C6 /r ib VSHUFPD| RVMI | V/V                   | AVX               | Shuffle Packed double-precision floatingpoint
| xmm1, xmm2, xmm3/m128, imm8           |      |                       |                   | values selected by imm8 from xmm2 and        
|                                       |      |                       |                   | xmm3/mem.                                    
| VEX.NDS.256.66.0F.WIG C6 /r ib VSHUFPD| RVMI | V/V                   | AVX               | Shuffle Packed double-precision floatingpoint
| ymm1, ymm2, ymm3/m256, imm8           |      |                       |                   | values selected by imm8 from ymm2 and        
|                                       |      |                       |                   | ymm3/mem.                                    

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Moves either of the two packed double-precision floating-point values from destination
operand (first operand) into the low quadword of the destination operand; moves
either of the two packed double-precision floating-point values from the source
operand into to the high quadword of the destination operand (see Figure 4-21).
The select operand (third operand) determines which values are moved to the
destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register.

| X1                      | X0 DEST     
| Y1                      | Y0 X1 or X0 
| SHUFPD Shuffle Operation| Figure 4-21.
The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. The select operand is an 8-bit immediate:
bit 0 selects which value is moved from the destination operand to the result
(where 0 selects the low quadword and 1 selects the high quadword) and bit 1
selects which value is moved from the source operand to the result. Bits 2 through
7 of the select operand are reserved and must be set to 0.

Operation:

IF SELECT[0] = 0
  THEN DEST[63:0]
  ELSE DEST[63:0]
IF SELECT[1] = 0
  THEN DEST[127:64]
  ELSE DEST[127:64]
SHUFPD (128-bit Legacy SSE version)
IF IMM0[0] = 0
  THEN DEST[63:0] <- SRC1[63:0]
  ELSE DEST[63:0] <- SRC1[127:64] FI;
IF IMM0[1] = 0
  THEN DEST[127:64] <- SRC2[63:0]
  ELSE DEST[127:64] <- SRC2[127:64] FI;
DEST[VLMAX-1:128] (Unmodified)
VSHUFPD (VEX.128 encoded version)
IF IMM0[0] = 0
  THEN DEST[63:0] <- SRC1[63:0]
  ELSE DEST[63:0] <- SRC1[127:64] FI;
IF IMM0[1] = 0
  THEN DEST[127:64] <- SRC2[63:0]
  ELSE DEST[127:64] <- SRC2[127:64] FI;
DEST[VLMAX-1:128] <- 0
VSHUFPD (VEX.256 encoded version)
IF IMM0[0] = 0
  THEN DEST[63:0] <- SRC1[63:0]
  ELSE DEST[63:0] <- SRC1[127:64] FI;
IF IMM0[1] = 0
  THEN DEST[127:64] <- SRC2[63:0]
  ELSE DEST[127:64] <- SRC2[127:64] FI;
IF IMM0[2] = 0
  THEN DEST[191:128] <- SRC1[191:128]
  ELSE DEST[191:128] <- SRC1[255:192] FI;
IF IMM0[3] = 0
  THEN DEST[255:192] <- SRC2[191:128]
  ELSE DEST[255:192] <- SRC2[255:192] FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| SHUFPD: | __m128d _mm_shuffle_pd(__m128d a, __m128d
|         | b, unsigned int imm8)                    
| VSHUFPD:| __m256d _mm256_shuffle_pd (__m256d a,    
|         | __m256d b, const int select);            

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: SHUFPS
description:
SHUFPS - Shuffle Packed Single-Precision Floating-Point Values:
| Opcode*/Instruction                | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                   
| 0F C6 /r ib SHUFPS xmm1, xmm2/m128,| RMI  | V/V                   | SSE               | Shuffle packed single-precision floating-point
| imm8                               |      |                       |                   | values selected by imm8 from xmm1 and         
|                                    |      |                       |                   | xmm1/m128 to xmm1.                            
| VEX.NDS.128.0F.WIG C6 /r ib VSHUFPS| RVMI | V/V                   | AVX               | Shuffle Packed single-precision floating-point
| xmm1, xmm2, xmm3/m128, imm8        |      |                       |                   | values selected by imm8 from xmm2 and         
|                                    |      |                       |                   | xmm3/mem.                                     
| VEX.NDS.256.0F.WIG C6 /r ib VSHUFPS| RVMI | V/V                   | AVX               | Shuffle Packed single-precision floating-point
| ymm1, ymm2, ymm3/m256, imm8        |      |                       |                   | values selected by imm8 from ymm2 and         
|                                    |      |                       |                   | ymm3/mem.                                     

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RMI  | ModRM:reg (r, w)| ModRM:r/m (r)| imm8         | NA       
| RVMI | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| imm8     

Description:
Moves two of the four packed single-precision floating-point values from the
destination operand (first operand) into the low quadword of the destination
operand; moves two of the four packed single-precision floating-point values
from the source operand (second operand) into to the high quadword of the destination
operand (see Figure 4-22). The select operand (third operand) determines which
values are moved to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. determines which values
are moved to the destination operand.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand can be a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

| DEST| X3                    | X2                                | X1       | X0       
| SRC | Y3                    | Y2                                | Y1       | Y0       
| DEST| Y3 ... Y0 Figure 4-22.| Y3 ... Y0 SHUFPS Shuffle Operation| X3 ... X0| X3 ... X0
The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. The select operand is an 8-bit immediate:
bits 0 and 1 select the value to be moved from the destination operand to the
low doubleword of the result, bits 2 and 3 select the value to be moved from
the destination operand to the second doubleword of the result, bits 4 and 5
select the value to be moved from the source operand to the third doubleword
of the result, and bits 6 and 7 select the value to be moved from the source
operand to the high doubleword of the result.

Operation:

CASE (SELECT[1:0]) OF
  0:
  1:
  2:
  3:
ESAC;
CASE (SELECT[3:2]) OF
  0:
  1:
  2:
  3:
ESAC;
CASE (SELECT[5:4]) OF
  0:
  1:
  2:
  3:
ESAC;
CASE (SELECT[7:6]) OF
  0:
  1:
  2:
  3:
ESAC;
SHUFPS (128-bit Legacy SSE version)
DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <- Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <- Select4(SRC2[127:0], imm8[7:6]);
DEST[VLMAX-1:128] (Unmodified)
VSHUFPS (VEX.128 encoded version)
DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <- Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <- Select4(SRC2[127:0], imm8[7:6]);
DEST[VLMAX-1:128] <- 0
VSHUFPS (VEX.256 encoded version)
DEST[31:0] <- Select4(SRC1[127:0], imm8[1:0]);
DEST[63:32] <- Select4(SRC1[127:0], imm8[3:2]);
DEST[95:64] <- Select4(SRC2[127:0], imm8[5:4]);
DEST[127:96] <- Select4(SRC2[127:0], imm8[7:6]);
DEST[159:128] <- Select4(SRC1[255:128], imm8[1:0]);
DEST[191:160] <- Select4(SRC1[255:128], imm8[3:2]);
DEST[223:192] <- Select4(SRC2[255:128], imm8[5:4]);
DEST[255:224] <- Select4(SRC2[255:128], imm8[7:6]);

Intel C/C++ Compiler Intrinsic Equivalent:
| SHUFPS: | __m128 _mm_shuffle_ps(__m128 a, __m128
|         | b, unsigned int imm8)                 
| VSHUFPS:| __m256 _mm256_shuffle_ps (__m256 a,   
|         | __m256 b, const int select);          

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: SIDT
description:
SIDT - Store Interrupt Descriptor Table Register:
| Opcode* | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description     
| 0F 01 /1| SIDT m     | M    | Valid      | Valid          | Store IDTR to m.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the content the interrupt descriptor table register (IDTR) in the destination
operand. The destination operand specifies a 6-byte memory location.

In non-64-bit modes, if the operand-size attribute is 32 bits, the 16-bit limit
field of the register is stored in the low 2 bytes of the memory location and
the 32-bit base address is stored in the high 4 bytes. If the operand-size attribute
is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address
is stored in the third, fourth, and fifth byte, with the sixth byte filled with
0s.

In 64-bit mode, the operand size fixed at 8+2 bytes. The instruction stores
8-byte base and 2-byte limit values.

SIDT is only useful in operating-system software; however, it can be used in
application programs without causing an exception to be generated. See “LGDT/LIDT - Load
Global/Interrupt Descriptor Table Register” in Chapter 3, Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 2A, for information on loading
the GDTR and IDTR.


IA-32 Architecture Compatibility:
The 16-bit form of SIDT is compatible with the Intel 286 processor if the upper
8 bits are not referenced. The Intel 286 processor fills these bits with 1s;
the Pentium 4, Intel Xeon, P6 processor family, Pentium, Intel486, and Intel386
processors fill these bits with 0s.

Operation:

IF instruction is SIDT
  THEN
     IF OperandSize = 16
       THEN
          DEST[0:15] <- IDTR(Limit);
          DEST[16:39] <- IDTR(Base); (* 24 bits of base address stored; *)
          DEST[40:47] <- 0;
       ELSE IF (32-bit Operand Size)
          DEST[0:15] <- IDTR(Limit);
          DEST[16:47] <- IDTR(Base); FI; (* Full 32-bit base address stored *)
       ELSE (* 64-bit Operand Size *)
          DEST[0:15] <- IDTR(Limit);
          DEST[16:79] <- IDTR(Base); (* Full 64-bit base address stored *)
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #UD            | If the destination operand is a register.  
|                | If the LOCK prefix is used.                
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         


platform: x86
mnem: SLDT
description:
SLDT - Store Local Descriptor Table Register:
| Opcode*         | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| 0F 00 /0        | SLDT r/m16  | M    | Valid      | Valid          | Stores segment selector from LDTR in
|                 |             |      |            |                | r/m16.                              
| REX.W + 0F 00 /0| SLDT r64/m16| M    | Valid      | Valid          | Stores segment selector from LDTR in
|                 |             |      |            |                | r64/m16.                            

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the segment selector from the local descriptor table register (LDTR)
in the destination operand. The destination operand can be a general-purpose
register or a memory location. The segment selector stored with this instruction
points to the segment descriptor (located in the GDT) for the current LDT. This
instruction can only be executed in protected mode.

Outside IA-32e mode, when the destination operand is a 32-bit register, the
16-bit segment selector is copied into the low-order 16 bits of the register.
The high-order 16 bits of the register are cleared for the Pentium 4, Intel
Xeon, and P6 family processors. They are undefined for Pentium, Intel486, and
Intel386 processors. When the destination operand is a memory location, the
segment selector is written to memory as a 16-bit quantity, regardless of the
operand size.

In compatibility mode, when the destination operand is a 32-bit register, the
16-bit segment selector is copied into the low-order 16 bits of the register.
The high-order 16 bits of the register are cleared. When the destination operand
is a memory location, the segment selector is written to memory as a 16-bit
quantity, regardless of the operand size.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). The behavior of SLDT with a 64-bit register is to zero-extend
the 16-bit selector and store it in the register. If the destination is memory
and operand size is 64, SLDT will write the 16-bit selector to memory as a 16-bit
quantity, regardless of the operand size

Operation:

DEST <- LDTR(SegmentSelector);

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #UD| The SLDT instruction is not recognized
|    | in real-address mode.                 
If the LOCK prefix is used.


Virtual-8086 Mode Exceptions:
| #UD| The SLDT instruction is not recognized  
|    | in virtual-8086 mode. If the LOCK prefix
|    | is used.                                

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SMSW
description:
SMSW - Store Machine Status Word:
| Opcode*         | Instruction | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 0F 01 /4        | SMSW r/m16  | M    | Valid      | Valid          | Store machine status word to r/m16.   
| 0F 01 /4        | SMSW r32/m16| M    | Valid      | Valid          | Store machine status word in low-order
|                 |             |      |            |                | 16 bits of r32/m16; high-order 16 bits
|                 |             |      |            |                | of r32 are undefined.                 
| REX.W + 0F 01 /4| SMSW r64/m16| M    | Valid      | Valid          | Store machine status word in low-order
|                 |             |      |            |                | 16 bits of r64/m16; high-order 16 bits
|                 |             |      |            |                | of r32 are undefined.                 

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the machine status word (bits 0 through 15 of control register CR0) into
the destination operand. The destination operand can be a general-purpose register
or a memory location.

In non-64-bit modes, when the destination operand is a 32-bit register, the
low-order 16 bits of register CR0 are copied into the low-order 16 bits of the
register and the high-order 16 bits are undefined. When the destination operand
is a memory location, the low-order 16 bits of register CR0 are written to memory
as a 16-bit quantity, regardless of the operand size.

In 64-bit mode, the behavior of the SMSW instruction is defined by the following
examples:

 - SMSW r16 operand size 16, store CR0[15:0] in r16
 - SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32
 - SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64
 - SMSW m16 operand size 16, store CR0[15:0] in m16
 - SMSW m16 operand size 32, store CR0[15:0] in m16 (not m32)
 - SMSW m16 operands size 64, store CR0[15:0] in m16 (not m64)

SMSW is only useful in operating-system software. However, it is not a privileged
instruction and can be used in application programs. The is provided for compatibility
with the Intel 286 processor. Programs and procedures intended to run on the
Pentium 4, Intel Xeon, P6 family, Pentium, Intel486, and Intel386 processors
should use the MOV (control registers) instruction to load the machine status
word.

See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25
of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3C, for more information about the behavior of this instruction in VMX non-root
operation.

Operation:

DEST <- CR0[15:0];
(* Machine status word *)

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register is used to access           
|                | memory and it contains a NULL segment          
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP   | If a memory operand effective address
|       | is outside the CS, DS, ES, FS, or GS 
|       | segment limit.                       
| #SS(0)| If a memory operand effective address
|       | is outside the SS segment limit.     
| #UD   | If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SQRTPD
description:
SQRTPD - Compute Square Roots of Packed Double-Precision Floating-Point Values:
| Opcode*/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| 66 0F 51 /r SQRTPD xmm1, xmm2/m128   | RM   | V/V                   | SSE2              | Computes square roots of the packed  
|                                      |      |                       |                   | doubleprecision floating-point values
|                                      |      |                       |                   | in xmm2/m128 and stores the results  
|                                      |      |                       |                   | in xmm1.                             
| VEX.128.66.0F.WIG 51 /r VSQRTPD xmm1,| RM   | V/V                   | AVX               | Computes Square Roots of the packed  
| xmm2/m128                            |      |                       |                   | doubleprecision floating-point values
|                                      |      |                       |                   | in xmm2/m128 and stores the result in
|                                      |      |                       |                   | xmm1.                                
| VEX.256.66.0F.WIG 51/r VSQRTPD ymm1, | RM   | V/V                   | AVX               | Computes Square Roots of the packed  
| ymm2/m256                            |      |                       |                   | doubleprecision floating-point values
|                                      |      |                       |                   | in ymm2/m256 and stores the result in
|                                      |      |                       |                   | ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a SIMD computation of the square roots of the two packed double-precision
floating-point values in the source operand (second operand) stores the packed
double-precision floating-point results in the destination operand. The source
operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register. See Figure 11-3 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1, for an illustration of a SIMD double-precision
floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the source operand second source operand or a 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. Note: In VEX-encoded versions, VEX.vvvv is reserved
and must be 1111b otherwise instructions will #UD.

Operation:

SQRTPD (128-bit Legacy SSE version)
DEST[63:0] <- SQRT(SRC[63:0])
DEST[127:64] <- SQRT(SRC[127:64])
DEST[VLMAX-1:128] (Unmodified)
VSQRTPD (VEX.128 encoded version)
DEST[63:0] <- SQRT(SRC[63:0])
DEST[127:64] <- SQRT(SRC[127:64])
DEST[VLMAX-1:128] <- 0
VSQRTPD (VEX.256 encoded version)
DEST[63:0] <- SQRT(SRC[63:0])
DEST[127:64] <- SQRT(SRC[127:64])
DEST[191:128] <- SQRT(SRC[191:128])
DEST[255:192] <- SQRT(SRC[255:192])

Intel C/C++ Compiler Intrinsic Equivalent:
| SQRTPD:| __m128d _mm_sqrt_pd (m128d a)      
| SQRTPD:| __m256d _mm256_sqrt_pd (__m256d a);

SIMD Floating-Point Exceptions:
Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: SQRTPS
description:
SQRTPS - Compute Square Roots of Packed Single-Precision Floating-Point Values:
| Opcode*/Instruction                         | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| 0F 51 /r SQRTPS xmm1, xmm2/m128             | RM   | V/V                   | SSE               | Computes square roots of the packed  
|                                             |      |                       |                   | singleprecision floating-point values
|                                             |      |                       |                   | in xmm2/m128 and stores the results  
|                                             |      |                       |                   | in xmm1.                             
| VEX.128.0F.WIG 51 /r VSQRTPS xmm1, xmm2/m128| RM   | V/V                   | AVX               | Computes Square Roots of the packed  
|                                             |      |                       |                   | singleprecision floating-point values
|                                             |      |                       |                   | in xmm2/m128 and stores the result in
|                                             |      |                       |                   | xmm1.                                
| VEX.256.0F.WIG 51/r VSQRTPS ymm1, ymm2/m256 | RM   | V/V                   | AVX               | Computes Square Roots of the packed  
|                                             |      |                       |                   | singleprecision floating-point values
|                                             |      |                       |                   | in ymm2/m256 and stores the result in
|                                             |      |                       |                   | ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a SIMD computation of the square roots of the four packed single-precision
floating-point values in the source operand (second operand) stores the packed
single-precision floating-point results in the destination operand. The source
operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register. See Figure 10-5 in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1, for an illustration of a SIMD single-precision
floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the source operand second source operand or a 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register. Note: In VEX-encoded versions, VEX.vvvv is reserved
and must be 1111b otherwise instructions will #UD.

Operation:

SQRTPS (128-bit Legacy SSE version)
DEST[31:0] <- SQRT(SRC[31:0])
DEST[63:32] <- SQRT(SRC[63:32])
DEST[95:64] <- SQRT(SRC[95:64])
DEST[127:96] <- SQRT(SRC[127:96])
DEST[VLMAX-1:128] (Unmodified)
VSQRTPS (VEX.128 encoded version)
DEST[31:0] <- SQRT(SRC[31:0])
DEST[63:32] <- SQRT(SRC[63:32])
DEST[95:64] <- SQRT(SRC[95:64])
DEST[127:96] <- SQRT(SRC[127:96])
DEST[VLMAX-1:128] <- 0
VSQRTPS (VEX.256 encoded version)
DEST[31:0] <- SQRT(SRC[31:0])
DEST[63:32] <- SQRT(SRC[63:32])
DEST[95:64] <- SQRT(SRC[95:64])
DEST[127:96] <- SQRT(SRC[127:96])
DEST[159:128] <- SQRT(SRC[159:128])
DEST[191:160] <- SQRT(SRC[191:160])
DEST[223:192] <- SQRT(SRC[223:192])
DEST[255:224] <- SQRT(SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalent:
| SQRTPS:| __m128 _mm_sqrt_ps(__m128 a)     
| SQRTPS:| __m256 _mm256_sqrt_ps (__m256 a);

SIMD Floating-Point Exceptions:
Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: SQRTSD
description:
SQRTSD - Compute Square Root of Scalar Double-Precision Floating-Point Value:
| Opcode*/Instruction                          | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                    
| F2 0F 51 /r SQRTSD xmm1, xmm2/m64            | RM   | V/V                   | SSE2              | Computes square root of the low doubleprecision
|                                              |      |                       |                   | floating-point value in xmm2/m64 and           
|                                              |      |                       |                   | stores the results in xmm1.                    
| VEX.NDS.LIG.F2.0F.WIG 51/r VSQRTSD xmm1,xmm2,| RVM  | V/V                   | AVX               | Computes square root of the low doubleprecision
| xmm3/m64                                     |      |                       |                   | floating point value in xmm3/m64 and           
|                                              |      |                       |                   | stores the results in xmm2. Also, upper        
|                                              |      |                       |                   | double precision floating-point value          
|                                              |      |                       |                   | (bits[127:64]) from xmm2 are copied            
|                                              |      |                       |                   | to xmm1[127:64].                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Computes the square root of the low double-precision floating-point value in
the source operand (second operand) and stores the double-precision floating-point
result in the destination operand. The source operand can be an XMM register
or a 64-bit memory location. The destination operand is an XMM register. The
high quadword of the destination operand remains unchanged. See Figure 11-4
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, for an illustration of a scalar double-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
first source operand and the destination operand are the same. Bits (VLMAX1:64)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

SQRTSD (128-bit Legacy SSE version)
DEST[63:0] <- SQRT(SRC[63:0])
DEST[VLMAX-1:64] (Unmodified)
VSQRTSD (VEX.128 encoded version)
DEST[63:0] <- SQRT(SRC2[63:0])
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| SQRTSD:| __m128d _mm_sqrt_sd (m128d a, m128d
|        | b)                                 

SIMD Floating-Point Exceptions:
Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: SQRTSS
description:
SQRTSS - Compute Square Root of Scalar Single-Precision Floating-Point Value:
| Opcode*/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                    
| F3 0F 51 /r SQRTSS xmm1, xmm2/m32       | RM   | V/V                   | SSE               | Computes square root of the low singleprecision
|                                         |      |                       |                   | floating-point value in xmm2/m32 and           
|                                         |      |                       |                   | stores the results in xmm1.                    
| VEX.NDS.LIG.F3.0F.WIG 51/r VSQRTSS xmm1,| RVM  | V/V                   | AVX               | Computes square root of the low singleprecision
| xmm2, xmm3/m32                          |      |                       |                   | floating-point value in xmm3/m32 and           
|                                         |      |                       |                   | stores the results in xmm1. Also, upper        
|                                         |      |                       |                   | single precision floating-point values         
|                                         |      |                       |                   | (bits[127:32]) from xmm2 are copied            
|                                         |      |                       |                   | to xmm1[127:32].                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Computes the square root of the low single-precision floating-point value in
the source operand (second operand) and stores the single-precision floating-point
result in the destination operand. The source operand can be an XMM register
or a 32-bit memory location. The destination operand is an XMM register. The
three high-order doublewords of the destination operand remain unchanged. See
Figure 10-6 in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for an illustration of a scalar single-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
first source operand and the destination operand are the same. Bits (VLMAX1:32)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

SQRTSS (128-bit Legacy SSE version)
DEST[31:0] <- SQRT(SRC2[31:0])
DEST[VLMAX-1:32] (Unmodified)
VSQRTSS (VEX.128 encoded version)
DEST[31:0] <- SQRT(SRC2[31:0])
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| SQRTSS:| __m128 _mm_sqrt_ss(__m128 a)

SIMD Floating-Point Exceptions:
Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: STC
description:
STC - Set Carry Flag:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description 
| F9     | STC        | NP   | Valid      | Valid          | Set CF flag.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Sets the CF flag in the EFLAGS register.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

CF <- 1;

Flags Affected:
The CF flag is set. The OF, ZF, SF, AF, and PF flags are unaffected.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: STD
description:
STD - Set Direction Flag:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description 
| FD     | STD        | NP   | Valid      | Valid          | Set DF flag.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Sets the DF flag in the EFLAGS register. When the DF flag is set to 1, string
operations decrement the index registers (ESI and/or EDI).

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

DF <- 1;

Flags Affected:
The DF flag is set. The CF, OF, ZF, SF, AF, and PF flags are unaffected.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: STI
description:
STI - Set Interrupt Flag:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| FB     | STI        | NP   | Valid      | Valid          | Set interrupt flag; external, maskable
|        |            |      |            |                | interrupts enabled at the end of the  
|        |            |      |            |                | next instruction.                     

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
If protected-mode virtual interrupts are not enabled, STI sets the interrupt
flag (IF) in the EFLAGS register. After the IF flag is set, the processor begins
responding to external, maskable interrupts after the next instruction is executed.
The delayed effect of this instruction is provided to allow interrupts to be
enabled just before returning from a procedure (or subroutine). For instance,
if an STI instruction is followed by an RET instruction, the RET instruction
is allowed to execute before external interrupts are recognized1. If the STI
instruction is followed by a CLI instruction (which clears the IF flag), the
effect of the STI instruction is negated.

The IF flag and the STI and CLI instructions do not prohibit the generation
of exceptions and NMI interrupts. NMI interrupts (and SMIs) may be blocked for
one macroinstruction following an STI.

When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less
than 3; STI sets the VIF flag in the EFLAGS register, leaving IF unaffected.

Table 4-15 indicates the action of the STI instruction depending on the processor's
mode of operation and the CPL/IOPL settings of the running program or procedure.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.


Table 4-15. Decision Table for STI Results:
| PE| VM| IOPL | CPL| PVI| VIP| VME| STI Result
| 0 | X | X    | X  | X  | X  | X  | IF = 1    
| 1 | 0 | ≥ CPL| X  | X  | X  | X  | IF = 1    
| 1 | 0 | < CPL| 3  | 1  | 0  | X  | VIF = 1   
| 1 | 0 | < CPL| < 3| X  | X  | X  | GP Fault  
| 1 | 0 | < CPL| X  | 0  | X  | X  | GP Fault  
| 1 | 0 | < CPL| X  | X  | 1  | X  | GP Fault  
| 1 | 1 | 3    | X  | X  | X  | X  | IF = 1    
| 1 | 1 | < 3  | X  | X  | 0  | 1  | VIF = 1   
| 1 | 1 | < 3  | X  | X  | 1  | X  | GP Fault  
| 1 | 1 | < 3  | X  | X  | X  | 0  | GP Fault  
Notes: X = This setting has no impact.

| 1.| The STI instruction delays recognition      
|   | of interrupts only if it is executed        
|   | with EFLAGS.IF = 0. In a sequence of        
|   | STI instructions, only the first instruction
|   | in the sequence is guaranteed to delay      
|   | interrupts. In the following instruction    
|   | sequence, interrupts may be recognized      
|   | before RET executes: STI STI RET            
Operation:

IF PE = 0
  THEN
     IF <- 1; (* Set Interrupt Flag *)
  ELSE
     IF VM = 0
       THEN
          IF IOPL ≥ CPL
             THEN
               IF <- 1;
          ELSE
             IF (IOPL < CPL) and (CPL = 3) and (VIP = 0)
               THEN
                  VIF <- 1;
               ELSE
                  #GP(0);
             FI;
          FI;
       ELSE
          IF IOPL = 3
             THEN
               IF <- 1;
          ELSE
             IF ((IOPL < 3) and (VIP = 0) and (VME = 1))
               THEN
                  VIF <- 1;
             ELSE
               #GP(0); (* Trap to virtual-8086 monitor *)
             FI;)
          FI;
     FI;
FI;

Flags Affected:
The IF flag is set to 1; or the VIF flag is set to 1.


Protected Mode Exceptions:
| #GP(0)| If the CPL is greater (has less privilege)
|       | than the IOPL of the current program      
|       | or procedure.                             
| #UD   | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: STMXCSR
description:
STMXCSR - Store MXCSR Register State:
| Opcode*/Instruction             | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                        
| 0F AE /3 STMXCSR m32            | M    | V/V                   | SSE               | Store contents of MXCSR register to
|                                 |      |                       |                   | m32.                               
| VEX.LZ.0F.WIG AE /3 VSTMXCSR m32| M    | V/V                   | AVX               | Store contents of MXCSR register to
|                                 |      |                       |                   | m32.                               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the contents of the MXCSR control and status register to the destination
operand. The destination operand is a 32-bit memory location. The reserved bits
in the MXCSR register are stored as 0s.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.
VEX.L must be 0, otherwise instructions will #UD.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise
instructions will #UD.

Operation:

m32 <- MXCSR;

Intel C/C++ Compiler Intrinsic Equivalent:
_mm_getcsr(void)


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L= 1, If VEX.vvvv != 1111B.


platform: x86
mnem: STOS
description:
STOS/STOSB/STOSW/STOSD/STOSQ - Store String:
| Opcode    | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| AA        | STOS m8    | NA   | Valid      | Valid          | For legacy mode, store AL at address 
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store AL at
|           |            |      |            |                | address RDI or EDI.                  
| AB        | STOS m16   | NA   | Valid      | Valid          | For legacy mode, store AX at address 
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store AX at
|           |            |      |            |                | address RDI or EDI.                  
| AB        | STOS m32   | NA   | Valid      | Valid          | For legacy mode, store EAX at address
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store EAX  
|           |            |      |            |                | at address RDI or EDI.               
| REX.W + AB| STOS m64   | NA   | Valid      | N.E.           | Store RAX at address RDI or EDI.     
| AA        | STOSB      | NA   | Valid      | Valid          | For legacy mode, store AL at address 
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store AL at
|           |            |      |            |                | address RDI or EDI.                  
| AB        | STOSW      | NA   | Valid      | Valid          | For legacy mode, store AX at address 
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store AX at
|           |            |      |            |                | address RDI or EDI.                  
| AB        | STOSD      | NA   | Valid      | Valid          | For legacy mode, store EAX at address
|           |            |      |            |                | ES:(E)DI; For 64-bit mode store EAX  
|           |            |      |            |                | at address RDI or EDI.               
| REX.W + AB| STOSQ      | NA   | Valid      | N.E.           | Store RAX at address RDI or EDI.     

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NA   | NA       | NA       | NA       | NA       

Description:
In non-64-bit and default 64-bit mode; stores a byte, word, or doubleword from
the AL, AX, or EAX register (respectively) into the destination operand. The
destination operand is a memory location, the address of which is read from
either the ES:EDI or ES:DI register (depending on the address-size attribute
of the instruction and the mode of operation). The ES segment cannot be overridden
with a segment override prefix.

At the assembly-code level, two forms of the instruction are allowed: the “explicit-operands”
form and the “nooperands” form. The explicit-operands form (specified with the
STOS mnemonic) allows the destination operand to be specified explicitly. Here,
the destination operand should be a symbol that indicates the size and location
of the destination value. The source operand is then automatically selected
to match the size of the destination operand (the AL register for byte operands,
AX for word operands, EAX for doubleword operands). The explicit-operands form
is provided to allow documentation; however, note that the documentation provided
by this form can be misleading. That is, the destination operand symbol must
specify the correct type (size) of the operand (byte, word, or doubleword),
but it does not have to specify the correct location. The location is always
specified by the ES:(E)DI register. These must be loaded correctly before the
store string instruction is executed.

The no-operands form provides “short forms” of the byte, word, doubleword, and
quadword versions of the STOS instructions. Here also ES:(E)DI is assumed to
be the destination operand and AL, AX, or EAX is assumed to be the source operand.
The size of the destination and source operands is selected by the mnemonic:
STOSB (byte read from register AL), STOSW (word from AX), STOSD (doubleword
from EAX).

After the byte, word, or doubleword is transferred from the register to the
memory location, the (E)DI register is incremented or decremented according
to the setting of the DF flag in the EFLAGS register. If the DF flag is 0, the
register is incremented; if the DF flag is 1, the register is decremented (the
register is incremented or decremented by 1 for byte operations, by 2 for word
operations, by 4 for doubleword operations).


NOTE:
To improve performance, more recent processors support modifications to the
processor's operation during the string store operations initiated with STOS
and STOSB. See Section 7.3.9.3 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1 for additional information on fast-string operation.

In 64-bit mode, the default address size is 64 bits, 32-bit address size is
supported using the prefix 67H. Using a REX prefix in the form of REX.W promotes
operation on doubleword operand to 64 bits. The promoted no-operand mnemonic
is STOSQ. STOSQ (and its explicit operands variant) store a quadword from the
RAX register into the destination addressed by RDI or EDI. See the summary chart
at the beginning of this section for encoding data and limits.

The STOS, STOSB, STOSW, STOSD, STOSQ instructions can be preceded by the REP
prefix for block loads of ECX bytes, words, or doublewords. More often, however,
these instructions are used within a LOOP construct because data needs to be
moved into the AL, AX, or EAX register before it can be stored. See “REP/REPE/REPZ
/REPNE/REPNZ - Repeat String Operation Prefix” in this chapter for a description
of the REP prefix.

Operation:

Non-64-bit Mode:
IF (Byte store)
  THEN
     DEST <- AL;
       THEN IF DF = 0
          THEN (E)DI <- (E)DI + 1;
          ELSE (E)DI <- (E)DI - 1;
       FI;
  ELSE IF (Word store)
     THEN
       DEST <- AX;
          THEN IF DF = 0
             THEN (E)DI <- (E)DI + 2;
             ELSE (E)DI <- (E)DI - 2;
          FI;
     FI;
  ELSE IF (Doubleword store)
     THEN
       DEST <- EAX;
          THEN IF DF = 0
             THEN (E)DI <- (E)DI + 4;
             ELSE (E)DI <- (E)DI - 4;
          FI;
     FI;
FI;
64-bit Mode:
IF (Byte store)
  THEN
     DEST <- AL;
       THEN IF DF = 0
          THEN (R|E)DI <- (R|E)DI + 1;
          ELSE (R|E)DI <- (R|E)DI - 1;
       FI;
  ELSE IF (Word store)
     THEN
       DEST <- AX;
          THEN IF DF = 0
             THEN (R|E)DI <- (R|E)DI + 2;
             ELSE (R|E)DI <- (R|E)DI - 2;
          FI;
     FI;
  ELSE IF (Doubleword store)
     THEN
       DEST <- EAX;
          THEN IF DF = 0
             THEN (R|E)DI <- (R|E)DI + 4;
             ELSE (R|E)DI <- (R|E)DI - 4;
          FI;
     FI;
  ELSE IF (Quadword store using REX.W )
     THEN
       DEST <- RAX;
          THEN IF DF = 0
             THEN (R|E)DI <- (R|E)DI + 8;
             ELSE (R|E)DI <- (R|E)DI - 8;
          FI;
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the limit of the            
|                | ES segment. If the ES register contains        
|                | a NULL segment selector.                       
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used.                    

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the ES segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the ES segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: STR
description:
STR - Store Task Register:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 0F 00 /1| STR r/m16  | M    | Valid      | Valid          | Stores segment selector from TR in r/m16.

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Stores the segment selector from the task register (TR) in the destination operand.
The destination operand can be a general-purpose register or a memory location.
The segment selector stored with this instruction points to the task state segment
(TSS) for the currently running task.

When the destination operand is a 32-bit register, the 16-bit segment selector
is copied into the lower 16 bits of the register and the upper 16 bits of the
register are cleared. When the destination operand is a memory location, the
segment selector is written to memory as a 16-bit quantity, regardless of operand
size.

In 64-bit mode, operation is the same. The size of the memory operand is fixed
at 16 bits. In register stores, the 2byte TR is zero extended if stored to a
64-bit register.

The STR instruction is useful only in operating-system software. It can only
be executed in protected mode.

Operation:

DEST <- TR(SegmentSelector);

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If the destination is a memory operand   
|                | that is located in a non-writable segment
|                | or if the effective address is outside   
|                | the CS, DS, ES, FS, or GS segment limit. 
|                | If the DS, ES, FS, or GS register is     
|                | used to access memory and it contains    
|                | a NULL segment selector.                 
| #SS(0)         | If a memory operand effective address    
|                | is outside the SS segment limit.         
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If alignment checking is enabled and     
|                | an unaligned memory reference is made    
|                | while the current privilege level is     
|                | 3.                                       
| #UD            | If the LOCK prefix is used.              

Real-Address Mode Exceptions:
| #UD| The STR instruction is not recognized
|    | in real-address mode.                

Virtual-8086 Mode Exceptions:
| #UD| The STR instruction is not recognized
|    | in virtual-8086 mode.                

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #SS(U)         | If the stack address is in a non-canonical 
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: SUB
description:
SUB - Subtract:
| Opcode          | Instruction     | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 2C ib           | SUB AL, imm8    | I    | Valid      | Valid          | Subtract imm8 from AL.                 
| 2D iw           | SUB AX, imm16   | I    | Valid      | Valid          | Subtract imm16 from AX.                
| 2D id           | SUB EAX, imm32  | I    | Valid      | Valid          | Subtract imm32 from EAX.               
| REX.W + 2D id   | SUB RAX, imm32  | I    | Valid      | N.E.           | Subtract imm32 sign-extended to 64-bits
|                 |                 |      |            |                | from RAX.                              
| 80 /5 ib        | SUB r/m8, imm8  | MI   | Valid      | Valid          | Subtract imm8 from r/m8.               
| REX + 80 /5 ib  | SUB r/m8*, imm8 | MI   | Valid      | N.E.           | Subtract imm8 from r/m8.               
| 81 /5 iw        | SUB r/m16, imm16| MI   | Valid      | Valid          | Subtract imm16 from r/m16.             
| 81 /5 id        | SUB r/m32, imm32| MI   | Valid      | Valid          | Subtract imm32 from r/m32.             
| REX.W + 81 /5 id| SUB r/m64, imm32| MI   | Valid      | N.E.           | Subtract imm32 sign-extended to 64-bits
|                 |                 |      |            |                | from r/m64.                            
| 83 /5 ib        | SUB r/m16, imm8 | MI   | Valid      | Valid          | Subtract sign-extended imm8 from r/m16.
| 83 /5 ib        | SUB r/m32, imm8 | MI   | Valid      | Valid          | Subtract sign-extended imm8 from r/m32.
| REX.W + 83 /5 ib| SUB r/m64, imm8 | MI   | Valid      | N.E.           | Subtract sign-extended imm8 from r/m64.
| 28 /r           | SUB r/m8, r8    | MR   | Valid      | Valid          | Subtract r8 from r/m8.                 
| REX + 28 /r     | SUB r/m8*, r8*  | MR   | Valid      | N.E.           | Subtract r8 from r/m8.                 
| 29 /r           | SUB r/m16, r16  | MR   | Valid      | Valid          | Subtract r16 from r/m16.               
| 29 /r           | SUB r/m32, r32  | MR   | Valid      | Valid          | Subtract r32 from r/m32.               
| REX.W + 29 /r   | SUB r/m64, r64  | MR   | Valid      | N.E.           | Subtract r64 from r/m64.               
| 2A /r           | SUB r8, r/m8    | RM   | Valid      | Valid          | Subtract r/m8 from r8.                 
| REX + 2A /r     | SUB r8*, r/m8*  | RM   | Valid      | N.E.           | Subtract r/m8 from r8.                 
| 2B /r           | SUB r16, r/m16  | RM   | Valid      | Valid          | Subtract r/m16 from r16.               
| 2B /r           | SUB r32, r/m32  | RM   | Valid      | Valid          | Subtract r/m32 from r32.               
| REX.W + 2B /r   | SUB r64, r/m64  | RM   | Valid      | N.E.           | Subtract r/m64 from r64.               
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| I    | AL/AX/EAX/RAX   | imm8/26/32   | NA       | NA       
| MI   | ModRM:r/m (r, w)| imm8/26/32   | NA       | NA       
| MR   | ModRM:r/m (r, w)| ModRM:reg (r)| NA       | NA       
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA       | NA       

Description:
Subtracts the second operand (source operand) from the first operand (destination
operand) and stores the result in the destination operand. The destination operand
can be a register or a memory location; the source operand can be an immediate,
register, or memory location. (However, two memory operands cannot be used in
one instruction.) When an immediate value is used as an operand, it is sign-extended
to the length of the destination operand format.

The SUB instruction performs integer subtraction. It evaluates the result for
both signed and unsigned integer operands and sets the OF and CF flags to indicate
an overflow in the signed or unsigned result, respectively. The SF flag indicates
the sign of the signed result.

In 64-bit mode, the instruction's default operation size is 32 bits. Using a
REX prefix in the form of REX.R permits access to additional registers (R8-R15).
Using a REX prefix in the form of REX.W promotes operation to 64 bits. See the
summary chart at the beginning of this section for encoding data and limits.

This instruction can be used with a LOCK prefix to allow the instruction to
be executed atomically.

Operation:

DEST <- (DEST - SRC);

Flags Affected:
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.


Protected Mode Exceptions:
| #GP(0)         | If the destination is located in a non-writable
|                | segment. If a memory operand effective         
|                | address is outside the CS, DS, ES, FS,         
|                | or GS segment limit. If the DS, ES,            
|                | FS, or GS register contains a NULL segment     
|                | selector.                                      
| #SS(0)         | If a memory operand effective address          
|                | is outside the SS segment limit.               
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If alignment checking is enabled and           
|                | an unaligned memory reference is made          
|                | while the current privilege level is           
|                | 3.                                             
| #UD            | If the LOCK prefix is used but the destination 
|                | is not a memory operand.                       

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address         
|    | is outside the CS, DS, ES, FS, or GS          
|    | segment limit.                                
| #SS| If a memory operand effective address         
|    | is outside the SS segment limit.              
| #UD| If the LOCK prefix is used but the destination
|    | is not a memory operand.                      

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address         
|                | is outside the CS, DS, ES, FS, or GS          
|                | segment limit.                                
| #SS(0)         | If a memory operand effective address         
|                | is outside the SS segment limit.              
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made.        
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the           
|                | SS segment is in a non-canonical form.        
| #GP(0)         | If the memory address is in a non-canonical   
|                | form.                                         
| #PF(fault-code)| If a page fault occurs.                       
| #AC(0)         | If alignment checking is enabled and          
|                | an unaligned memory reference is made         
|                | while the current privilege level is          
|                | 3.                                            
| #UD            | If the LOCK prefix is used but the destination
|                | is not a memory operand.                      


platform: x86
mnem: SUBPD
description:
SUBPD - Subtract Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                   
| 66 0F 5C /r SUBPD xmm1, xmm2/m128            | RM   | V/V                   | SSE2              | Subtract packed double-precision floatingpoint
|                                              |      |                       |                   | values in xmm2/m128 from xmm1.                
| VEX.NDS.128.66.0F.WIG 5C /r VSUBPD xmm1,xmm2,| RVM  | V/V                   | AVX               | Subtract packed double-precision floatingpoint
| xmm3/m128                                    |      |                       |                   | values in xmm3/mem from xmm2 and stores       
|                                              |      |                       |                   | result in xmm1.                               
| VEX.NDS.256.66.0F.WIG 5C /r VSUBPD ymm1,     | RVM  | V/V                   | AVX               | Subtract packed double-precision floatingpoint
| ymm2, ymm3/m256                              |      |                       |                   | values in ymm3/mem from ymm2 and stores       
|                                              |      |                       |                   | result in ymm1.                               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD subtract of the two packed double-precision floating-point values
in the source operand (second operand) from the two packed double-precision
floating-point values in the destination operand (first operand), and stores
the packed double-precision floating-point results in the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. See Figure 11-3 in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a SIMD double-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: T second
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand can be a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Operation:

SUBPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] - SRC[63:0]
DEST[127:64] <- DEST[127:64] - SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VSUBPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
DEST[127:64] <- SRC1[127:64] - SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VSUBPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
DEST[127:64] <- SRC1[127:64] - SRC2[127:64]
DEST[191:128] <- SRC1[191:128] - SRC2[191:128]
DEST[255:192] <- SRC1[255:192] - SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| SUBPD: | __m128d _mm_sub_pd (m128d a, m128d b)    
| VSUBPD:| __m256d _mm256_sub_pd (__m256d a, __m256d
|        | b);                                      

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: SUBPS
description:
SUBPS - Subtract Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                    
| 0F 5C /r SUBPS xmm1 xmm2/m128             | RM   | V/V                   | SSE               | Subtract packed single-precision floating-point
|                                           |      |                       |                   | values in xmm2/mem from xmm1.                  
| VEX.NDS.128.0F.WIG 5C /r VSUBPS xmm1,xmm2,| RVM  | V/V                   | AVX               | Subtract packed single-precision floating-point
| xmm3/m128                                 |      |                       |                   | values in xmm3/mem from xmm2 and stores        
|                                           |      |                       |                   | result in xmm1.                                
| VEX.NDS.256.0F.WIG 5C /r VSUBPS ymm1,     | RVM  | V/V                   | AVX               | Subtract packed single-precision floating-point
| ymm2, ymm3/m256                           |      |                       |                   | values in ymm3/mem from ymm2 and stores        
|                                           |      |                       |                   | result in ymm1.                                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD subtract of the four packed single-precision floating-point
values in the source operand (second operand) from the four packed single-precision
floating-point values in the destination operand (first operand), and stores
the packed single-precision floating-point results in the destination operand.
The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. See Figure 10-5 in the Intel® 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a SIMD doubleprecision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

VEX.256 encoded version: The first source operand is a YMM register. The second
source operand can be a YMM register or a 256-bit memory location. The destination
operand is a YMM register.

Operation:

SUBPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VSUBPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VSUBPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[63:32] <- SRC1[63:32] - SRC2[63:32]
DEST[95:64] <- SRC1[95:64] - SRC2[95:64]
DEST[127:96] <- SRC1[127:96] - SRC2[127:96]
DEST[159:128] <- SRC1[159:128] - SRC2[159:128]
DEST[191:160]<- SRC1[191:160] - SRC2[191:160]
DEST[223:192] <- SRC1[223:192] - SRC2[223:192]
DEST[255:224] <- SRC1[255:224] - SRC2[255:224].

Intel C/C++ Compiler Intrinsic Equivalent:
| SUBPS: | __m128 _mm_sub_ps(__m128 a, __m128 b) 
| VSUBPS:| __m256 _mm256_sub_ps (__m256 a, __m256
|        | b);                                   

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 2.


platform: x86
mnem: SUBSD
description:
SUBSD - Subtract Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                     
| F2 0F 5C /r SUBSD xmm1, xmm2/m64             | RM   | V/V                   | SSE2              | Subtracts the low double-precision floatingpoint
|                                              |      |                       |                   | values in xmm2/mem64 from xmm1.                 
| VEX.NDS.LIG.F2.0F.WIG 5C /r VSUBSD xmm1,xmm2,| RVM  | V/V                   | AVX               | Subtract the low double-precision floatingpoint 
| xmm3/m64                                     |      |                       |                   | value in xmm3/mem from xmm2 and store           
|                                              |      |                       |                   | the result in xmm1.                             

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Subtracts the low double-precision floating-point value in the source operand
(second operand) from the low double-precision floating-point value in the destination
operand (first operand), and stores the double-precision floating-point result
in the destination operand. The source operand can be an XMM register or a 64-bit
memory location. The destination operand is an XMM register. The high quadword
of the destination operand remains unchanged. See Figure 11-4 in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a scalar double-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
destination and first source operand are the same. Bits (VLMAX-1:64) of the
corresponding YMM destination register remain unchanged. VEX.128 encoded version:
Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.

Operation:

SUBSD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] - SRC[63:0]
DEST[VLMAX-1:64] (Unmodified)
VSUBSD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] - SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| SUBSD:| __m128d _mm_sub_sd (m128d a, m128d b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: SUBSS
description:
SUBSS - Subtract Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                    
| F3 0F 5C /r SUBSS xmm1, xmm2/m32             | RM   | V/V                   | SSE               | Subtract the lower single-precision            
|                                              |      |                       |                   | floatingpoint values in xmm2/m32 from          
|                                              |      |                       |                   | xmm1.                                          
| VEX.NDS.LIG.F3.0F.WIG 5C /r VSUBSS xmm1,xmm2,| RVM  | V/V                   | AVX               | Subtract the low single-precision floatingpoint
| xmm3/m32                                     |      |                       |                   | value in xmm3/mem from xmm2 and store          
|                                              |      |                       |                   | the result in xmm1.                            

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Subtracts the low single-precision floating-point value in the source operand
(second operand) from the low singleprecision floating-point value in the destination
operand (first operand), and stores the single-precision floatingpoint result
in the destination operand. The source operand can be an XMM register or a 32-bit
memory location. The destination operand is an XMM register. The three high-order
doublewords of the destination operand remain unchanged. See Figure 10-6 in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1,
for an illustration of a scalar single-precision floating-point operation.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
destination and first source operand are the same. Bits (VLMAX-1:32) of the
corresponding YMM destination register remain unchanged. VEX.128 encoded version:
Bits (127:32) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (VLMAX-1:128) of the destination YMM
register are zeroed.

Operation:

SUBSS (128-bit Legacy SSE version)
DEST[31:0] <- DEST[31:0] - SRC[31:0]
DEST[VLMAX-1:32] (Unmodified)
VSUBSS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] - SRC2[31:0]
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| SUBSS:| __m128 _mm_sub_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal.


Other Exceptions:
See Exceptions Type 3.


platform: x86
mnem: SWAPGS
description:
SWAPGS - Swap GS Base Register:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 0F 01 F8| SWAPGS     | NP   | Valid      | Invalid        | Exchanges the current GS base register
|         |            |      |            |                | value with the value contained in MSR 
|         |            |      |            |                | address C0000102H.                    

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
SWAPGS exchanges the current GS base register value with the value contained
in MSR address C0000102H (IA32_KERNEL_GS_BASE). The SWAPGS instruction is a
privileged instruction intended for use by system software.

When using SYSCALL to implement system calls, there is no kernel stack at the
OS entry point. Neither is there a straightforward method to obtain a pointer
to kernel structures from which the kernel stack pointer could be read. Thus,
the kernel cannot save general purpose registers or reference memory.

By design, SWAPGS does not require any general purpose registers or memory operands.
No registers need to be saved before using the instruction. SWAPGS exchanges
the CPL 0 data pointer from the IA32_KERNEL_GS_BASE MSR with the GS base register.
The kernel can then use the GS prefix on normal memory references to access
kernel data structures. Similarly, when the OS kernel is entered using an interrupt
or exception (where the kernel stack is already set up), SWAPGS can be used
to quickly get a pointer to the kernel data structures.

The IA32_KERNEL_GS_BASE MSR itself is only accessible using RDMSR/WRMSR instructions.
Those instructions are only accessible at privilege level 0. The WRMSR instruction
ensures that the IA32_KERNEL_GS_BASE MSR contains a canonical address.

Operation:

IF CS.L != 1 (* Not in 64-Bit Mode *)
  THEN
     #UD; FI;
IF CPL != 0
  THEN #GP(0); FI;
tmp <- GS.base;
GS.base <- IA32_KERNEL_GS_BASE;
IA32_KERNEL_GS_BASE <- tmp;

Flags Affected:
None


Protected Mode Exceptions:
| #UD| If Mode != 64-Bit.

Real-Address Mode Exceptions:
| #UD| If Mode != 64-Bit.

Virtual-8086 Mode Exceptions:
| #UD| If Mode != 64-Bit.

Compatibility Mode Exceptions:
| #UD| If Mode != 64-Bit.

64-Bit Mode Exceptions:
| #GP(0)| If CPL != 0. If the LOCK prefix is used.


platform: x86
mnem: SYSCALL
description:
SYSCALL - Fast System Call:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 05 | SYSCALL    | NP   | Valid      | Invalid        | Fast call to privilege level 0 system
|       |            |      |            |                | procedures.                          

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
SYSCALL invokes an OS system-call handler at privilege level 0. It does so by
loading RIP from the IA32_LSTAR MSR (after saving the address of the instruction
following SYSCALL into RCX). (The WRMSR instruction ensures that the IA32_LSTAR
MSR always contain a canonical address.)

SYSCALL also saves RFLAGS into R11 and then masks RFLAGS using the IA32_FMASK
MSR (MSR address C0000084H); specifically, the processor clears in RFLAGS every
bit corresponding to a bit that is set in the IA32_FMASK MSR.

SYSCALL loads the CS and SS selectors with values derived from bits 47:32 of
the IA32_STAR MSR. However, the CS and SS descriptor caches are not loaded from
the descriptors (in GDT or LDT) referenced by those selectors. Instead, the
descriptor caches are loaded with fixed values. See the Operation section for
details. It is the responsibility of OS software to ensure that the descriptors
(in GDT or LDT) referenced by those selector values correspond to the fixed
values loaded into the descriptor caches; the SYSCALL instruction does not ensure
this correspondence.

The SYSCALL instruction does not save the stack pointer (RSP). If the OS system-call
handler will change the stack pointer, it is the responsibility of software
to save the previous value of the stack pointer. This might be done prior to
executing SYSCALL, with software restoring the stack pointer with the instruction
following SYSCALL (which will be executed after SYSRET). Alternatively, the
OS system-call handler may save the stack pointer and restore it before executing
SYSRET.

Operation:

IF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
  THEN #UD;
FI;
RCX <- RIP;
RIP <- IA32_LSTAR;
R11 <- RFLAGS;
RFLAGS <- RFLAGS AND NOT(IA32_FMASK);
CS.Selector <- IA32_STAR[47:32] AND FFFCH (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;
CS.Limit <- FFFFFH;
CS.Type <- 11;
CS.S <- 1;
CS.DPL <- 0;
CS.P <- 1;
CS.L <- 1;
CS.D <- 0;
CS.G <- 1;
CPL <- 0;
SS.Selector <- IA32_STAR[47:32] + 8;
(* Set rest of SS to a fixed value *)
SS.Base <- 0;
SS.Limit <- FFFFFH;
SS.Type <- 3;
SS.S <- 1;
SS.DPL <- 0;
SS.P <- 1;
SS.B <- 1;
SS.G <- 1;

Flags Affected:
All.


Protected Mode Exceptions:
| #UD| The SYSCALL instruction is not recognized
|    | in protected mode.                       

Real-Address Mode Exceptions:
| #UD| The SYSCALL instruction is not recognized
|    | in real-address mode.                    

Virtual-8086 Mode Exceptions:
| #UD| The SYSCALL instruction is not recognized
|    | in virtual-8086 mode.                    

Compatibility Mode Exceptions:
| #UD| The SYSCALL instruction is not recognized
|    | in compatibility mode.                   

64-Bit Mode Exceptions:
| #UD| If IA32_EFER.SCE = 0. If the LOCK prefix
|    | is used.                                


platform: x86
mnem: SYSENTER
description:
SYSENTER - Fast System Call:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 34 | SYSENTER   | NP   | Valid      | Valid          | Fast call to privilege level 0 system
|       |            |      |            |                | procedures.                          

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Executes a fast call to a level 0 system procedure or routine. SYSENTER is a
companion instruction to SYSEXIT. The instruction is optimized to provide the
maximum performance for system calls from user code running at privilege level
3 to operating system or executive procedures running at privilege level 0.

When executed in IA-32e mode, the SYSENTER instruction transitions the logical
processor to 64-bit mode; otherwise, the logical processor remains in protected
mode.

Prior to executing the SYSENTER instruction, software must specify the privilege
level 0 code segment and code entry point, and the privilege level 0 stack segment
and stack pointer by writing values to the following MSRs:

 - IA32_SYSENTER_CS (MSR address 174H)  -  The lower 16 bits of this MSR are the
segment selector for the privilege level 0 code segment. This value is also
used to determine the segment selector of the privilege level 0 stack segment
(see the Operation section). This value cannot indicate a null selector.
 - IA32_SYSENTER_EIP (MSR address 175H)  -  The value of this MSR is loaded into
RIP (thus, this value references the first instruction of the selected operating
procedure or routine). In protected mode, only bits 31:0 are loaded.
 - IA32_SYSENTER_ESP (MSR address 176H)  -  The value of this MSR is loaded into
RSP (thus, this value contains the stack pointer for the privilege level 0 stack).
This value cannot represent a non-canonical address. In protected mode, only
bits 31:0 are loaded.

These MSRs can be read from and written to using RDMSR/WRMSR. The WRMSR instruction
ensures that the IA32_SYSENTER_EIP and IA32_SYSENTER_ESP MSRs always contain
canonical addresses.

While SYSENTER loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS
MSR, the CS and SS descriptor caches are not loaded from the descriptors (in
GDT or LDT) referenced by those selectors. Instead, the descriptor caches are
loaded with fixed values. See the Operation section for details. It is the responsibility
of OS software to ensure that the descriptors (in GDT or LDT) referenced by
those selector values correspond to the fixed values loaded into the descriptor
caches; the SYSENTER instruction does not ensure this correspondence.

The SYSENTER instruction can be invoked from all operating modes except real-address
mode.

The SYSENTER and SYSEXIT instructions are companion instructions, but they do
not constitute a call/return pair. When executing a SYSENTER instruction, the
processor does not save state information for the user code (e.g., the instruction
pointer), and neither the SYSENTER nor the SYSEXIT instruction supports passing
parameters on the stack.

To use the SYSENTER and SYSEXIT instructions as companion instructions for transitions
between privilege level 3 code and privilege level 0 operating system procedures,
the following conventions must be followed:

 - The segment descriptors for the privilege level 0 code and stack segments and
for the privilege level 3 code and stack segments must be contiguous in a descriptor
table. This convention allows the processor to compute the segment selectors
from the value entered in the SYSENTER_CS_MSR MSR.
 - The fast system call “stub” routines executed by user code (typically in shared
libraries or DLLs) must save the required return IP and processor state information
if a return to the calling procedure is required. Likewise, the operating system
or executive procedures called with SYSENTER instructions must have access to
and use this saved return and state information when returning to the user code.

The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture
in the Pentium II processor. The availability of these instructions on a processor
is indicated with the SYSENTER/SYSEXIT present (SEP) feature flag returned to
the EDX register by the CPUID instruction. An operating system that qualifies
the SEP flag must also qualify the processor family and model to ensure that
the SYSENTER/SYSEXIT instructions are actually present. For example:

IF CPUID SEP bit is set THEN IF (Family = 6) and (Model < 3) and (Stepping <
3) THEN SYSENTER/SYSEXIT_Not_Supported; FI; ELSE SYSENTER/SYSEXIT_Supported;
FI; FI;

When the CPUID instruction is executed on the Pentium Pro processor (model 1),
the processor returns a the SEP flag as set, but does not support the SYSENTER/SYSEXIT
instructions.

Operation:

IF CR0.PE = 0 OR IA32_SYSENTER_CS[15:2] = 0 THEN #GP(0); FI;
RFLAGS.VM <- 0;
RFLAGS.IF <- 0;
IF in IA-32e mode
  THEN
     RSP <- IA32_SYSENTER_ESP;
     RIP <- IA32_SYSENTER_EIP;
ELSE
     ESP <- IA32_SYSENTER_ESP[31:0];
     EIP <- IA32_SYSENTER_EIP[31:0];
FI;
CS.Selector <- IA32_SYSENTER_CS[15:0] AND FFFCH;
                          (* Operating system provides CS; RPL forced to 0 *)
(* Set rest of CS to a fixed value *)
CS.Base <- 0;
CS.Limit <- FFFFFH;
CS.Type <- 11;
CS.S <- 1;
CS.DPL <- 0;
CS.P <- 1;
IF in IA-32e mode
  THEN
     CS.L <- 1;
     CS.D <- 0;
  ELSE
     CS.L <- 0;
     CS.D <- 1;
FI;
CS.G <- 1;
CPL <- 0;
SS.Selector <- CS.Selector + 8;
(* Set rest of SS to a fixed value *)
SS.Base <- 0;
SS.Limit <- FFFFFH;
SS.Type <- 3;
SS.S <- 1;
SS.DPL <- 0;
SS.P <- 1;
SS.B <- 1;
SS.G <- 1;

Flags Affected:
VM, IF (see Operation above)


Protected Mode Exceptions:
| #GP(0)| If IA32_SYSENTER_CS[15:2] = 0.
| #UD   | If the LOCK prefix is used.   

Real-Address Mode Exceptions:
| #GP| The SYSENTER instruction is not recognized
|    | in real-address mode.                     
| #UD| If the LOCK prefix is used.               

Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: SYSEXIT
description:
SYSEXIT - Fast Return from Fast System Call:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 35        | SYSEXIT    | NP   | Valid      | Valid          | Fast return to privilege level 3 user
|              |            |      |            |                | code.                                
| REX.W + 0F 35| SYSEXIT    | NP   | Valid      | Valid          | Fast return to 64-bit mode privilege 
|              |            |      |            |                | level 3 user code.                   

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Executes a fast return to privilege level 3 user code. SYSEXIT is a companion
instruction to the SYSENTER instruction. The instruction is optimized to provide
the maximum performance for returns from system procedures executing at protections
levels 0 to user procedures executing at protection level 3. It must be executed
from code executing at privilege level 0.

With a 64-bit operand size, SYSEXIT remains in 64-bit mode; otherwise, it either
enters compatibility mode (if the logical processor is in IA-32e mode) or remains
in protected mode (if it is not).

Prior to executing SYSEXIT, software must specify the privilege level 3 code
segment and code entry point, and the privilege level 3 stack segment and stack
pointer by writing values into the following MSR and general-purpose registers:

 - IA32_SYSENTER_CS (MSR address 174H)  -  Contains a 32-bit value that is used to
determine the segment selectors for the privilege level 3 code and stack segments
(see the Operation section)
 - RDX  -  The canonical address in this register is loaded into RIP (thus, this
value references the first instruction to be executed in the user code). If
the return is not to 64-bit mode, only bits 31:0 are loaded.
 - ECX  -  The canonical address in this register is loaded into RSP (thus, this
value contains the stack pointer for the privilege level 3 stack). If the return
is not to 64-bit mode, only bits 31:0 are loaded.

The IA32_SYSENTER_CS MSR can be read from and written to using RDMSR and WRMSR.

While SYSEXIT loads the CS and SS selectors with values derived from the IA32_SYSENTER_CS
MSR, the CS and SS descriptor caches are not loaded from the descriptors (in
GDT or LDT) referenced by those selectors. Instead, the descriptor caches are
loaded with fixed values. See the Operation section for details. It is the responsibility
of OS software to ensure that the descriptors (in GDT or LDT) referenced by
those selector values correspond to the fixed values loaded into the descriptor
caches; the SYSEXIT instruction does not ensure this correspondence.

The SYSEXIT instruction can be invoked from all operating modes except real-address
mode and virtual-8086 mode.

The SYSENTER and SYSEXIT instructions were introduced into the IA-32 architecture
in the Pentium II processor. The availability of these instructions on a processor
is indicated with the SYSENTER/SYSEXIT present (SEP) feature flag returned to
the EDX register by the CPUID instruction. An operating system that qualifies
the SEP flag must also qualify the processor family and model to ensure that
the SYSENTER/SYSEXIT instructions are actually present. For example:

IF CPUID SEP bit is set THEN IF (Family = 6) and (Model < 3) and (Stepping <
3) THEN SYSENTER/SYSEXIT_Not_Supported; FI; ELSE SYSENTER/SYSEXIT_Supported;
FI; FI;

When the CPUID instruction is executed on the Pentium Pro processor (model 1),
the processor returns a the SEP flag as set, but does not support the SYSENTER/SYSEXIT
instructions.

Operation:

IF IA32_SYSENTER_CS[15:2] = 0 OR CR0.PE = 0 OR CPL != 0 THEN #GP(0); FI;
IF operand size is 64-bit
  THEN
     RSP <- RCX;
     RIP <- RDX;
  ELSE
     RSP <- ECX;
     RIP <- EDX;
FI;
IF operand size is 64-bit
  THEN CS.Selector <- IA32_SYSENTER_CS[15:0] + 32;
  ELSE CS.Selector <- IA32_SYSENTER_CS[15:0] + 16;
FI;
CS.Selector <- CS.Selector OR 3;
(* Set rest of CS to a fixed value *)
CS.Base <- 0;
CS.Limit <- FFFFFH;
CS.Type <- 11;
CS.S <- 1;
CS.DPL <- 3;
CS.P <- 1;
IF operand size is 64-bit
  THEN
     CS.L <- 1;
     CS.D <- 0;
  ELSE
     CS.L <- 0;
     CS.D <- 1;
FI;
CS.G <- 1;
CPL <- 3;
SS.Selector <- CS.Selector + 8;
(* Set rest of SS to a fixed value *)
SS.Base <- 0;
SS.Limit <- FFFFFH;
SS.Type <- 3;
SS.S <- 1;
SS.DPL <- 3;
SS.P <- 1;
SS.B <- 1;
SS.G <- 1;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If IA32_SYSENTER_CS[15:2] = 0. If CPL
|       | != 0.                                 
| #UD   | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| The SYSEXIT instruction is not recognized
|    | in real-address mode.                    
| #UD| If the LOCK prefix is used.              

Virtual-8086 Mode Exceptions:
| #GP(0)| The SYSEXIT instruction is not recognized
|       | in virtual-8086 mode.                    

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)| If IA32_SYSENTER_CS = 0. If CPL != 0.  
|       | If RCX or RDX contains a non-canonical
|       | address.                              
| #UD   | If the LOCK prefix is used.           


platform: x86
mnem: SYSRET
description:
SYSRET - Return From Fast System Call:
| Opcode       | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 0F 07        | SYSRET     | NP   | Valid      | Invalid        | Return to compatibility mode from fast
|              |            |      |            |                | system call                           
| REX.W + 0F 07| SYSRET     | NP   | Valid      | Invalid        | Return to 64-bit mode from fast system
|              |            |      |            |                | call                                  

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
SYSRET is a companion instruction to the SYSCALL instruction. It returns from
an OS system-call handler to user code at privilege level 3. It does so by loading
RIP from RCX and loading RFLAGS from R11.1 With a 64-bit operand size, SYSRET
remains in 64-bit mode; otherwise, it enters compatibility mode and only the
low 32 bits of the registers are loaded.

SYSRET loads the CS and SS selectors with values derived from bits 63:48 of
the IA32_STAR MSR. However, the CS and SS descriptor caches are not loaded from
the descriptors (in GDT or LDT) referenced by those selectors. Instead, the
descriptor caches are loaded with fixed values. See the Operation section for
details. It is the responsibility of OS software to ensure that the descriptors
(in GDT or LDT) referenced by those selector values correspond to the fixed
values loaded into the descriptor caches; the SYSRET instruction does not ensure
this correspondence.

The SYSRET instruction does not modify the stack pointer (ESP or RSP). For that
reason, it is necessary for software to switch to the user stack. The OS may
load the user stack pointer (if it was saved after SYSCALL) before executing
SYSRET; alternatively, user code may load the stack pointer (if it was saved
before SYSCALL) after receiving control from SYSRET.

If the OS loads the stack pointer before executing SYSRET, it must ensure that
the handler of any interrupt or exception delivered between restoring the stack
pointer and successful execution of SYSRET is not invoked with the user stack.
It can do so using approaches such as the following:

 - External interrupts. The OS can prevent an external interrupt from being delivered
by clearing EFLAGS.IF before loading the user stack pointer.
 - Nonmaskable interrupts (NMIs). The OS can ensure that the NMI handler is invoked
with the correct stack by using the interrupt stack table (IST) mechanism for
gate 2 (NMI) in the IDT (see Section 6.14.5, “Interrupt Stack Table,” in Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 3A).
 - General-protection exceptions (#GP). The SYSRET instruction generates #GP(0)
if the value of RCX is not canonical. The OS can address this possibility using
one or more of the following approaches:  - Confirming that the value of RCX is
canonical before executing SYSRET.  - Using paging to ensure that the SYSCALL
instruction will never save a non-canonical value into RCX.  - Using the IST mechanism
for gate 13 (#GP) in the IDT.

Operation:

IF (CS.L != 1 ) or (IA32_EFER.LMA != 1) or (IA32_EFER.SCE != 1)
(* Not in 64-Bit Mode or SYSCALL/SYSRET not enabled in IA32_EFER *)
  THEN #UD; FI;
IF (CPL != 0) OR (RCX is not canonical) THEN #GP(0); FI;
1.
  in RFLAGS retain the fixed values.
IF (operand size is 64-bit)
  THEN (* Return to 64-Bit Mode *)
     RIP <- RCX;
  ELSE (* Return to Compatibility Mode *)
     RIP <- ECX;
FI;
RFLAGS <- (R11 & 3C7FD7H) | 2;
IF (operand size is 64-bit)
  THEN CS.Selector <- IA32_STAR[63:48]+16;
  ELSE CS.Selector <- IA32_STAR[63:48];
FI;
CS.Selector <- CS.Selector OR 3;
(* Set rest of CS to a fixed value *)
CS.Base <- 0;
CS.Limit <- FFFFFH;
CS.Type <- 11;
CS.S <- 1;
CS.DPL <- 3;
CS.P <- 1;
IF (operand size is 64-bit)
  THEN (* Return to 64-Bit Mode *)
     CS.L <- 1;
     CS.D <- 0;
  ELSE (* Return to Compatibility Mode *)
     CS.L <- 0;
     CS.D <- 1;
FI;
CS.G <- 1;
CPL <- 0;
SS.Selector <- (IA32_STAR[63:48]+8) OR 3;
(* Set rest of SS to a fixed value *)
SS.Base <- 0;
SS.Limit <- FFFFFH;
SS.Type <- 3;
SS.S <- 1;
SS.DPL <- 3;
SS.P <- 1;
SS.B <- 1;
SS.G <- 1;

Flags Affected:
All.


Protected Mode Exceptions:
| #UD| The SYSRET instruction is not recognized
|    | in protected mode.                      

Real-Address Mode Exceptions:
| #UD| The SYSRET instruction is not recognized
|    | in real-address mode.                   

Virtual-8086 Mode Exceptions:
| #UD| The SYSRET instruction is not recognized
|    | in virtual-8086 mode.                   

Compatibility Mode Exceptions:
| #UD| The SYSRET instruction is not recognized
|    | in compatibility mode.                  

64-Bit Mode Exceptions:
| #UD   | If IA32_EFER.SCE = 0. If the LOCK prefix   
|       | is used.                                   
| #GP(0)| If CPL != 0. If RCX contains a non-canonical
|       | address.                                   


platform: x86
mnem: TEST
description:
TEST - Logical Compare:
| Opcode          | Instruction      | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                 
| A8 ib           | TEST AL, imm8    | I    | Valid      | Valid          | AND imm8 with AL; set SF, ZF, PF according  
|                 |                  |      |            |                | to result.                                  
| A9 iw           | TEST AX, imm16   | I    | Valid      | Valid          | AND imm16 with AX; set SF, ZF, PF according 
|                 |                  |      |            |                | to result.                                  
| A9 id           | TEST EAX, imm32  | I    | Valid      | Valid          | AND imm32 with EAX; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
| REX.W + A9 id   | TEST RAX, imm32  | I    | Valid      | N.E.           | AND imm32 sign-extended to 64-bits with     
|                 |                  |      |            |                | RAX; set SF, ZF, PF according to result.    
| F6 /0 ib        | TEST r/m8, imm8  | MI   | Valid      | Valid          | AND imm8 with r/m8; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
| REX + F6 /0 ib  | TEST r/m8*, imm8 | MI   | Valid      | N.E.           | AND imm8 with r/m8; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
| F7 /0 iw        | TEST r/m16, imm16| MI   | Valid      | Valid          | AND imm16 with r/m16; set SF, ZF, PF        
|                 |                  |      |            |                | according to result.                        
| F7 /0 id        | TEST r/m32, imm32| MI   | Valid      | Valid          | AND imm32 with r/m32; set SF, ZF, PF        
|                 |                  |      |            |                | according to result.                        
| REX.W + F7 /0 id| TEST r/m64, imm32| MI   | Valid      | N.E.           | AND imm32 sign-extended to 64-bits with     
|                 |                  |      |            |                | r/m64; set SF, ZF, PF according to result.  
| 84 /r           | TEST r/m8, r8    | MR   | Valid      | Valid          | AND r8 with r/m8; set SF, ZF, PF according  
|                 |                  |      |            |                | to result.                                  
| REX + 84 /r     | TEST r/m8*, r8*  | MR   | Valid      | N.E.           | AND r8 with r/m8; set SF, ZF, PF according  
|                 |                  |      |            |                | to result.                                  
| 85 /r           | TEST r/m16, r16  | MR   | Valid      | Valid          | AND r16 with r/m16; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
| 85 /r           | TEST r/m32, r32  | MR   | Valid      | Valid          | AND r32 with r/m32; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
| REX.W + 85 /r   | TEST r/m64, r64  | MR   | Valid      | N.E.           | AND r64 with r/m64; set SF, ZF, PF according
|                 |                  |      |            |                | to result.                                  
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| I    | AL/AX/EAX/RAX| imm8/16/32   | NA       | NA       
| MI   | ModRM:r/m (r)| imm8/16/32   | NA       | NA       
| MR   | ModRM:r/m (r)| ModRM:reg (r)| NA       | NA       

Description:
Computes the bit-wise logical AND of first operand (source 1 operand) and the
second operand (source 2 operand) and sets the SF, ZF, and PF status flags according
to the result. The result is then discarded.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation
to 64 bits. See the summary chart at the beginning of this section for encoding
data and limits.

Operation:

TEMP <- SRC1 AND SRC2;
SF <- MSB(TEMP);
IF TEMP = 0
  THEN ZF <- 1;
  ELSE ZF <- 0;
FI:
PF <- BitwiseXNOR(TEMP[0:7]);
CF <- 0;
OF <- 0;
(* AF is undefined *)

Flags Affected:
The OF and CF flags are set to 0. The SF, ZF, and PF flags are set according
to the result (see the “Operation” section above). The state of the AF flag
is undefined.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address
|                | is outside the CS, DS, ES, FS, or GS 
|                | segment limit. If the DS, ES, FS, or 
|                | GS register contains a NULL segment  
|                | selector.                            
| #SS(0)         | If a memory operand effective address
|                | is outside the SS segment limit.     
| #PF(fault-code)| If a page fault occurs.              
| #AC(0)         | If alignment checking is enabled and 
|                | an unaligned memory reference is made
|                | while the current privilege level is 
|                | 3.                                   
| #UD            | If the LOCK prefix is used.          

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: TZCNT
description:
TZCNT  -  Count the Number of Trailing Zero Bits:
| Opcode/Instruction                  | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                           
| F3 0F BC /r TZCNT r16, r/m16        | RM   | V/V            | BMI1              | Count the number of trailing zero bits
|                                     |      |                |                   | in r/m16, return result in r16.       
| F3 0F BC /r TZCNT r32, r/m32        | RM   | V/V            | BMI1              | Count the number of trailing zero bits
|                                     |      |                |                   | in r/m32, return result in r32.       
| REX.W + F3 0F BC /r TZCNT r64, r/m64| RM   | V/N.E.         | BMI1              | Count the number of trailing zero bits
|                                     |      |                |                   | in r/m64, return result in r64.       

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| A    | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
TZCNT counts the number of trailing least significant zero bits in source operand
(second operand) and returns the result in destination operand (first operand).
TZCNT is an extension of the BSF instruction. The key difference between TZCNT
and BSF instruction is that TZCNT provides operand size as output when source
operand is zero while in the case of BSF instruction, if source operand is zero,
the content of destination operand are undefined. On processors that do not
support TZCNT, the instruction byte encoding is executed as BSF.

Operation:

temp <- 0
DEST <- 0
DO WHILE ( (temp < OperandSize) and (SRC[ temp] = 0) )
  temp <- temp +1
  DEST <- DEST+ 1
OD
IF DEST = OperandSize
  CF <- 1
ELSE
  CF <- 0
FI
IF DEST = 0
  ZF <- 1
ELSE
  ZF <- 0
FI

Flags Affected:
ZF is set to 1 in case of zero output (least significant bit of the source is
set), and to 0 otherwise, CF is set to 1 if the input was zero and cleared otherwise.
OF, SF, PF and AF flags are undefined.


Intel C/C++ Compiler Intrinsic Equivalent:
| TZCNT:| unsigned __int32 _tzcnt_u32(unsigned
|       | __int32 src);                       
| TZCNT:| unsigned __int64 _tzcnt_u64(unsigned
|       | __int64 src);                       

Protected Mode Exceptions:
| #GP(0)          | For an illegal memory operand effective    
|                 | address in the CS, DS, ES, FS or GS        
|                 | segments. If the DS, ES, FS, or GS register
|                 | is used to access memory and it contains   
|                 | a null segment selector.                   
| #SS(0)          | For an illegal address in the SS segment.  
| #PF (fault-code)| For a page fault.                          
| #AC(0)          | If alignment checking is enabled and       
|                 | an unaligned memory reference is made      
|                 | while the current privilege level is       
|                 | 3.                                         

Real-Address Mode Exceptions:
| #GP(0)| If any part of the operand lies outside  
|       | of the effective address space from      
|       | 0 to 0FFFFH.                             
| #SS(0)| For an illegal address in the SS segment.

Virtual 8086 Mode Exceptions:
| #GP(0)          | If any part of the operand lies outside  
|                 | of the effective address space from      
|                 | 0 to 0FFFFH.                             
| #SS(0)          | For an illegal address in the SS segment.
| #PF (fault-code)| For a page fault.                        
| #AC(0)          | If alignment checking is enabled and     
|                 | an unaligned memory reference is made    
|                 | while the current privilege level is     
|                 | 3.                                       

Compatibility Mode Exceptions:
Same exceptions as in Protected Mode.


64-Bit Mode Exceptions:
| #GP(0)          | If the memory address is in a non-canonical
|                 | form.                                      
| #SS(0)          | If a memory address referencing the        
|                 | SS segment is in a non-canonical form.     
| #PF (fault-code)| For a page fault.                          
| #AC(0)          | If alignment checking is enabled and       
|                 | an unaligned memory reference is made      
|                 | while the current privilege level is       
|                 | 3.                                         


platform: x86
mnem: UCOMISD
description:
UCOMISD - Unordered Compare Scalar Double-Precision Floating-Point Values and Set EFLAGS:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 66 0F 2E /r UCOMISD xmm1, xmm2/m64    | RM   | V/V                   | SSE2              | Compares (unordered) the low doubleprecision
|                                       |      |                       |                   | floating-point values in xmm1 and xmm2/m64  
|                                       |      |                       |                   | and set the EFLAGS accordingly.             
| VEX.LIG.66.0F.WIG 2E /r VUCOMISD xmm1,| RM   | V/V                   | AVX               | Compare low double precision floating-point 
| xmm2/m64                              |      |                       |                   | values in xmm1 and xmm2/mem64 and set       
|                                       |      |                       |                   | the EFLAGS flags accordingly.               

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
Performs an unordered compare of the double-precision floating-point values
in the low quadwords of source operand 1 (first operand) and source operand
2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS register
according to the result (unordered, greater than, less than, or equal). The
OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result
is returned if either source operand is a NaN (QNaN or SNaN). The sign of zero
is ignored for comparisons, so that -0.0 is equal to +0.0.

Source operand 1 is an XMM register; source operand 2 can be an XMM register
or a 64 bit memory location.

The UCOMISD instruction differs from the COMISD instruction in that it signals
a SIMD floating-point invalid operation exception (#I) only when a source operand
is an SNaN. The COMISD instruction signals an invalid operation exception if
a source operand is either a QNaN or an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception
is generated.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Note: In VEX-encoded versions,
VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation:

RESULT <- UnorderedCompare(SRC1[63:0] < > SRC2[63:0]) {
(* Set EFLAGS *)
CASE (RESULT) OF
  UNORDERED:
  GREATER_THAN:
  LESS_THAN:
  EQUAL:
ESAC;
OF, AF, SF <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_ucomieq_sd(__m128d a, __m128d b) int _mm_ucomilt_sd(__m128d a, __m128d
b) int _mm_ucomile_sd(__m128d a, __m128d b) int _mm_ucomigt_sd(__m128d a, __m128d
b) int _mm_ucomige_sd(__m128d a, __m128d b) int _mm_ucomineq_sd(__m128d a, __m128d
b)


SIMD Floating-Point Exceptions:
Invalid (if SNaN operands), Denormal.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: UCOMISS
description:
UCOMISS - Unordered Compare Scalar Single-Precision Floating-Point Values and Set EFLAGS:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                      
| 0F 2E /r UCOMISS xmm1, xmm2/m32    | RM   | V/V                   | SSE               | Compare lower single-precision floating-point    
|                                    |      |                       |                   | value in xmm1 register with lower singleprecision
|                                    |      |                       |                   | floating-point value in xmm2/mem and             
|                                    |      |                       |                   | set the status flags accordingly.                
| VEX.LIG.0F.WIG 2E /r VUCOMISS xmm1,| RM   | V/V                   | AVX               | Compare low single precision floating-point      
| xmm2/m32                           |      |                       |                   | values in xmm1 and xmm2/mem32 and set            
|                                    |      |                       |                   | the EFLAGS flags accordingly.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
Performs an unordered compare of the single-precision floating-point values
in the low doublewords of the source operand 1 (first operand) and the source
operand 2 (second operand), and sets the ZF, PF, and CF flags in the EFLAGS
register according to the result (unordered, greater than, less than, or equal).
The OF, SF and AF flags in the EFLAGS register are set to 0. The unordered result
is returned if either source operand is a NaN (QNaN or SNaN). The sign of zero
is ignored for comparisons, so that -0.0 is equal to +0.0.

Source operand 1 is an XMM register; source operand 2 can be an XMM register
or a 32 bit memory location.

The UCOMISS instruction differs from the COMISS instruction in that it signals
a SIMD floating-point invalid operation exception (#I) only when a source operand
is an SNaN. The COMISS instruction signals an invalid operation exception if
a source operand is either a QNaN or an SNaN.

The EFLAGS register is not updated if an unmasked SIMD floating-point exception
is generated.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Note: In VEX-encoded versions,
VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation:

RESULT <- UnorderedCompare(SRC1[31:0] <> SRC2[31:0]) {
(* Set EFLAGS *)
CASE (RESULT) OF
  UNORDERED:
  GREATER_THAN:
  LESS_THAN:
  EQUAL:
ESAC;
OF,AF,SF <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
int _mm_ucomieq_ss(__m128 a, __m128 b) int _mm_ucomilt_ss(__m128 a, __m128 b)
int _mm_ucomile_ss(__m128 a, __m128 b) int _mm_ucomigt_ss(__m128 a, __m128 b)
int _mm_ucomige_ss(__m128 a, __m128 b)

int _mm_ucomineq_ss(__m128 a, __m128 b)


SIMD Floating-Point Exceptions:
Invalid (if SNaN operands), Denormal.


Other Exceptions:
See Exceptions Type 3; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: UD2
description:
UD2 - Undefined Instruction:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                    
| 0F 0B | UD2        | NP   | Valid      | Valid          | Raise invalid opcode exception.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Generates an invalid opcode exception. This instruction is provided for software
testing to explicitly generate an invalid opcode exception. The opcode for this
instruction is reserved for this purpose.

Other than raising the invalid opcode exception, this instruction has no effect
on processor state or memory.

Even though it is the execution of the UD2 instruction that causes the invalid
opcode exception, the instruction pointer saved by delivery of the exception
references the UD2 instruction (and not the following instruction).

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

#UD (* Generates invalid opcode exception *);

Flags Affected:
None.


Exceptions (All Operating Modes):
| #UD| Raises an invalid opcode exception in
|    | all operating modes.                 


platform: x86
mnem: UNPCKHPD
description:
UNPCKHPD - Unpack and Interleave High Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 66 0F 15 /r UNPCKHPD xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Unpacks and Interleaves double-precision 
|                                      |      |                       |                   | floating-point values from high quadwords
|                                      |      |                       |                   | of xmm1 and xmm2/m128.                   
| VEX.NDS.128.66.0F.WIG 15 /r VUNPCKHPD| RVM  | V/V                   | AVX               | Unpacks and Interleaves double precision 
| xmm1,xmm2, xmm3/m128                 |      |                       |                   | floating-point values from high quadwords
|                                      |      |                       |                   | of xmm2 and xmm3/m128.                   
| VEX.NDS.256.66.0F.WIG 15 /r VUNPCKHPD| RVM  | V/V                   | AVX               | Unpacks and Interleaves double precision 
| ymm1,ymm2, ymm3/m256                 |      |                       |                   | floating-point values from high quadwords
|                                      |      |                       |                   | of ymm2 and ymm3/m256.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an interleaved unpack of the high double-precision floating-point values
from the source operand (second operand) and the destination operand (first
operand). See Figure 4-23.

| DEST| X1                                 | X0             
| SRC | Y1                                 | Y0             
| DEST| Y1 UNPCKHPD Instruction High Unpack| X1 Figure 4-23.
|     | and Interleave Operation           |                
When unpacking from a memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to 16-byte boundary and normal segment checking
will still be enforced.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit
memory location. The destination is not distinct from the first source XMM register
and the upper bits (VLMAX-1:128) of the corresponding YMM register destination
are unmodified. VEX.128 encoded version: the first source operand is an XMM
register or 128-bit memory location. The destination operand is an XMM register.
The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.

Operation:

UNPCKHPD (128-bit Legacy SSE version)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
DEST[VLMAX-1:128] (Unmodified)
VUNPCKHPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VUNPCKHPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
DEST[191:128]<-SRC1[255:192]
DEST[255:192]<-SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| UNPCKHPD:| __m128d _mm_unpackhi_pd(__m128d a, __m128d
|          | b)                                        
| UNPCKHPD:| __m256d _mm256_unpackhi_pd(__m256d a,     
|          | __m256d b)                                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: UNPCKHPS
description:
UNPCKHPS - Unpack and Interleave High Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F 15 /r UNPCKHPS xmm1, xmm2/m128                     | RM   | V/V                   | SSE               | Unpacks and Interleaves single-precision 
|                                                       |      |                       |                   | floating-point values from high quadwords
|                                                       |      |                       |                   | of xmm1 and xmm2/mem into xmm1.          
| VEX.NDS.128.0F.WIG 15 /r VUNPCKHPS xmm1,xmm2,         | RVM  | V/V                   | AVX               | Unpacks and Interleaves single-precision 
| xmm3/m128                                             |      |                       |                   | floating-point values from high quadwords
|                                                       |      |                       |                   | of xmm2 and xmm3/m128.                   
| VEX.NDS.256.0F.WIG 15 /r VUNPCKHPS ymm1,ymm2,ymm3/m256| RVM  | V/V                   | AVX               | Unpacks and Interleaves single-precision 
|                                                       |      |                       |                   | floating-point values from high quadwords
|                                                       |      |                       |                   | of ymm2 and ymm3/m256.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an interleaved unpack of the high-order single-precision floating-point
values from the source operand (second operand) and the destination operand
(first operand). See Figure 4-24. The source operand can be an XMM register
or a 128-bit memory location; the destination operand is an XMM register.

| DEST| X3                                 | X2| X1| X0             
| SRC | Y3                                 | Y2| Y1| Y0             
| DEST| Y3 UNPCKHPS Instruction High Unpack| X3| Y2| X2 Figure 4-24.
|     | and Interleave Operation           |   |   |                
When unpacking from a memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to 16-byte boundary and normal segment checking
will still be enforced.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: T second
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

Operation:

UNPCKHPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
DEST[VLMAX-1:128] (Unmodified)
VUNPCKHPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VUNPCKHPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
DEST[159:128] <- SRC1[223:192]
DEST[191:160] <- SRC2[223:192]
DEST[223:192] <- SRC1[255:224]
DEST[255:224] <- SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalent:
| UNPCKHPS:| __m128 _mm_unpackhi_ps(__m128 a, __m128
|          | b)                                     
| UNPCKHPS:| __m256 _mm256_unpackhi_ps (__m256 a,   
|          | __m256 b);                             

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: UNPCKLPD
description:
UNPCKLPD - Unpack and Interleave Low Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 66 0F 14 /r UNPCKLPD xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Unpacks and Interleaves double-precision
|                                      |      |                       |                   | floating-point values from low quadwords
|                                      |      |                       |                   | of xmm1 and xmm2/m128.                  
| VEX.NDS.128.66.0F.WIG 14 /r VUNPCKLPD| RVM  | V/V                   | AVX               | Unpacks and Interleaves double precision
| xmm1,xmm2, xmm3/m128                 |      |                       |                   | floating-point values low high quadwords
|                                      |      |                       |                   | of xmm2 and xmm3/m128.                  
| VEX.NDS.256.66.0F.WIG 14 /r VUNPCKLPD| RVM  | V/V                   | AVX               | Unpacks and Interleaves double precision
| ymm1,ymm2, ymm3/m256                 |      |                       |                   | floating-point values low high quadwords
|                                      |      |                       |                   | of ymm2 and ymm3/m256.                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an interleaved unpack of the low double-precision floating-point values
from the source operand (second operand) and the destination operand (first
operand). See Figure 4-25. The source operand can be an XMM register or a 128-bit
memory location; the destination operand is an XMM register.

| DEST| X1                                    | X0             
| SRC | Y1                                    | Y0             
| DEST| Y0 UNPCKLPD Instruction Low Unpack and| X0 Figure 4-25.
|     | Interleave Operation                  |                
When unpacking from a memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to 16-byte boundary and normal segment checking
will still be enforced.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: T second
source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

Operation:

UNPCKLPD (128-bit Legacy SSE version)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[VLMAX-1:128] (Unmodified)
VUNPCKLPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[VLMAX-1:128] <- 0
VUNPCKLPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[191:128] <- SRC1[191:128]
DEST[255:192] <- SRC2[191:128]

Intel C/C++ Compiler Intrinsic Equivalent:
| UNPCKHPD:| __m128d _mm_unpacklo_pd(__m128d a, __m128d
|          | b)                                        
| UNPCKLPD:| __m256d _mm256_unpacklo_pd(__m256d a,     
|          | __m256d b)                                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: UNPCKLPS
description:
UNPCKLPS - Unpack and Interleave Low Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F 14 /r UNPCKLPS xmm1, xmm2/m128                     | RM   | V/V                   | SSE               | Unpacks and Interleaves single-precision
|                                                       |      |                       |                   | floating-point values from low quadwords
|                                                       |      |                       |                   | of xmm1 and xmm2/mem into xmm1.         
| VEX.NDS.128.0F.WIG 14 /r VUNPCKLPS xmm1,xmm2,         | RVM  | V/V                   | AVX               | Unpacks and Interleaves single-precision
| xmm3/m128                                             |      |                       |                   | floating-point values from low quadwords
|                                                       |      |                       |                   | of xmm2 and xmm3/m128.                  
| VEX.NDS.256.0F.WIG 14 /r VUNPCKLPS ymm1,ymm2,ymm3/m256| RVM  | V/V                   | AVX               | Unpacks and Interleaves single-precision
|                                                       |      |                       |                   | floating-point values from low quadwords
|                                                       |      |                       |                   | of ymm2 and ymm3/m256.                  

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs an interleaved unpack of the low-order single-precision floating-point
values from the source operand (second operand) and the destination operand
(first operand). See Figure 4-26. The source operand can be an XMM register
or a 128-bit memory location; the destination operand is an XMM register.

| DEST| X3                                    | X2| X1| X0             
| SRC | Y3                                    | Y2| Y1| Y0             
| DEST| Y1 UNPCKLPS Instruction Low Unpack and| X1| Y0| X0 Figure 4-26.
|     | Interleave Operation                  |   |   |                
When unpacking from a memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to 16-byte boundary and normal segment checking
will still be enforced.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: The first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed.

Operation:

UNPCKLPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
DEST[VLMAX-1:128] (Unmodified)
VUNPCKLPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
DEST[VLMAX-1:128] <- 0
UNPCKLPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
DEST[159:128] <- SRC1[159:128]
DEST[191:160] <- SRC2[159:128]
DEST[223:192] <- SRC1[191:160]
DEST[255:224] <- SRC2[191:160]

Intel C/C++ Compiler Intrinsic Equivalent:
| UNPCKLPS:| __m128 _mm_unpacklo_ps(__m128 a, __m128
|          | b)                                     
| UNPCKLPS:| __m256 _mm256_unpacklo_ps (__m256 a,   
|          | __m256 b);                             

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4.


platform: x86
mnem: VBROADCAST
description:
VBROADCAST - Broadcast Floating-Point Data:
| Opcode/Instruction                     | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                                     
| VEX.128.66.0F38.W0 18 /r VBROADCASTSS  | RM   | V/V           | AVX               | Broadcast single-precision floating-point       
| xmm1, m32                              |      |               |                   | element in mem to four locations in             
|                                        |      |               |                   | xmm1.                                           
| VEX.256.66.0F38.W0 18 /r VBROADCASTSS  | RM   | V/V           | AVX               | Broadcast single-precision floating-point       
| ymm1, m32                              |      |               |                   | element in mem to eight locations in            
|                                        |      |               |                   | ymm1.                                           
| VEX.256.66.0F38.W0 19 /r VBROADCASTSD  | RM   | V/V           | AVX               | Broadcast double-precision floating-point       
| ymm1, m64                              |      |               |                   | element in mem to four locations in             
|                                        |      |               |                   | ymm1.                                           
| VEX.256.66.0F38.W0 1A /r VBROADCASTF128| RM   | V/V           | AVX               | Broadcast 128 bits of floating-point            
| ymm1, m128                             |      |               |                   | data in mem to low and high 128-bits            
|                                        |      |               |                   | in ymm1.                                        
| VEX.128.66.0F38.W0 18/r VBROADCASTSS   | RM   | V/V           | AVX2              | Broadcast the low single-precision floatingpoint
| xmm1, xmm2                             |      |               |                   | element in the source operand to four           
|                                        |      |               |                   | locations in xmm1.                              
| VEX.256.66.0F38.W0 18 /r VBROADCASTSS  | RM   | V/V           | AVX2              | Broadcast low single-precision floating-point   
| ymm1, xmm2                             |      |               |                   | element in the source operand to eight          
|                                        |      |               |                   | locations in ymm1.                              
| VEX.256.66.0F38.W0 19 /r VBROADCASTSD  | RM   | V/V           | AVX2              | Broadcast low double-precision floating-point   
| ymm1, xmm2                             |      |               |                   | element in the source operand to four           
|                                        |      |               |                   | locations in ymm1.                              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Load floating point values from the source operand (second operand) and broadcast
to all elements of the destination operand (first operand). VBROADCASTSD and
VBROADCASTF128 are only supported as 256-bit wide versions. VBROADCASTSS is
supported in both 128-bit and 256-bit wide versions. Memory and register source
operand syntax support of 256-bit instructions depend on the processor's enumeration
of the following conditions with respect to CPUID.1:ECX.AVX[bit 28] and CPUID.(EAX=07H,
ECX=0H):EBX.AVX2[bit 5]:

 - If CPUID.1:ECX.AVX = 1 and CPUID.(EAX=07H, ECX=0H):EBX.AVX2 = 0: the destination
operand is a YMM register. The source operand support can be either a 32-bit,
64-bit, or 128-bit memory location. Register source encodings are reserved and
will #UD.
 - If CPUID.1:ECX.AVX = 1 and CPUID.(EAX=07H, ECX=0H):EBX.AVX2 = 1: the destination
operand is a YMM register. The source operand support can be a register or memory
location.

Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise
instructions will #UD. An attempt to execute VBROADCASTSD or VBROADCASTF128
encoded with VEX.L= 0 will cause an #UD exception. Attempts to execute any VBROADCAST*
instruction with VEX.W = 1 will cause #UD.

| m32                                     | X0                
| X0                                      | X0                
| VBROADCASTSS Operation (VEX.256 encoded | Figure 4-27. X0   
| version)                                |                   
| X0                                      | X0                
| VBROADCASTSS Operation (128-bit version)| Figure 4-28.      
| X0                                      | m64               
| X0                                      | X0                
| VBROADCASTSD Operation                  | Figure 4-29. X0 X0
| VBROADCASTF128 Operation                | Figure 4-30.      
Operation:

VBROADCASTSS (128 bit version)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[VLMAX-1:128] <- 0
VBROADCASTSS (VEX.256 encoded version)
temp <- SRC[31:0]
DEST[31:0] <- temp
DEST[63:32] <- temp
DEST[95:64] <- temp
DEST[127:96] <- temp
DEST[159:128] <- temp
DEST[191:160] <- temp
DEST[223:192] <- temp
DEST[255:224] <- temp
VBROADCASTSD (VEX.256 encoded version)
temp <- SRC[63:0]
DEST[63:0] <- temp
DEST[127:64] <- temp
DEST[191:128] <- temp
DEST[255:192] <- temp
VBROADCASTF128
temp <- SRC[127:0]
DEST[127:0] <- temp
DEST[VLMAX-1:128] <- temp

Intel C/C++ Compiler Intrinsic Equivalent:
| VBROADCASTSS:  | __m128 _mm_broadcast_ss(float *a);     
| VBROADCASTSS:  | __m256 _mm256_broadcast_ss(float *a);  
| VBROADCASTSD:  | __m256d _mm256_broadcast_sd(double *a);
| VBROADCASTF128:| __m256 _mm256_broadcast_ps(__m128 *    
|                | a);                                    
| VBROADCASTF128:| __m256d _mm256_broadcast_pd(__m128d    
|                | * a);                                  

Flags Affected:
None.


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.L = 0 for VBROADCASTSD, If VEX.L
|    | = 0 for VBROADCASTF128, If VEX.W = 1.  


platform: x86
mnem: VCVTPH2PS
description:
VCVTPH2PS - Convert 16-bit FP Values to Single-Precision FP Values:
| Opcode/Instruction                      | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                
| VEX.256.66.0F38.W0 13 /r VCVTPH2PS ymm1,| RM   | V/V          | F16C              | Convert eight packed half precision        
| xmm2/m128                               |      |              |                   | (16-bit) floating-point values in xmm2/m128
|                                         |      |              |                   | to packed single-precision floating-point  
|                                         |      |              |                   | value in ymm1.                             
| VEX.128.66.0F38.W0 13 /r VCVTPH2PS xmm1,| RM   | V/V          | F16C              | Convert four packed half precision (16-bit)
| xmm2/m64                                |      |              |                   | floating-point values in xmm2/m64 to       
|                                         |      |              |                   | packed single-precision floating-point     
|                                         |      |              |                   | value in xmm1.                             

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Converts four/eight packed half precision (16-bits) floating-point values in
the low-order 64/128 bits of an XMM/YMM register or 64/128-bit memory location
to four/eight packed single-precision floating-point values and writes the converted
values into the destination XMM/YMM register. If case of a denormal operand,
the correct normal result is returned. MXCSR.DAZ is ignored and is treated as
if it 0. No denormal exception is reported on MXCSR. 128-bit version: The source
operand is a XMM register or 64-bit memory location. The destination operand
is a XMM register. The upper bits (VLMAX-1:128) of the corresponding destination
YMM register are zeroed. 256-bit version: The source operand is a XMM register
or 128-bit memory location. The destination operand is a YMM register. The diagram
below illustrates how data is converted from four packed half precision (in
64 bits) to four single precision (in 128 bits) FP values. Note: VEX.vvvv is
reserved (must be 1111b).

| VCVTPH2PS xmm1, xmm2/mem64, 95 convert| imm8 0 xmm2/mem64 convert convert
| 95 VS2                                | 0 xmm1                           
| Figure 4-31.                          | VCVTPH2PS (128-bit Version)      
Operation:

vCvt_h2s(SRC1[15:0])
{
RETURN Cvt_Half_Precision_To_Single_Precision(SRC1[15:0]);
}
VCVTPH2PS (VEX.256 encoded version)
DEST[31:0] <-vCvt_h2s(SRC1[15:0]);
DEST[63:32] <-vCvt_h2s(SRC1[31:16]);
DEST[95:64] <-vCvt_h2s(SRC1[47:32]);
DEST[127:96] <-vCvt_h2s(SRC1[63:48]);
DEST[159:128] <-vCvt_h2s(SRC1[79:64]);
DEST[191:160] <-vCvt_h2s(SRC1[95:80]);
DEST[223:192] <-vCvt_h2s(SRC1[111:96]);
DEST[255:224] <-vCvt_h2s(SRC1[127:112]);
VCVTPH2PS (VEX.128 encoded version)
DEST[31:0] <-vCvt_h2s(SRC1[15:0]);
DEST[63:32] <-vCvt_h2s(SRC1[31:16]);
DEST[95:64] <-vCvt_h2s(SRC1[47:32]);
DEST[127:96] <-vCvt_h2s(SRC1[63:48]);
DEST[VLMAX-1:128] <-0

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
__m128 _mm_cvtph_ps ( __m128i m1);

__m256 _mm256_cvtph_ps ( __m128i m1)


SIMD Floating-Point Exceptions:
Invalid


Other Exceptions:
Exceptions Type 11 (do not report #AC); additionally

| #UD| If VEX.W=1.


platform: x86
mnem: VCVTPS2PH
description:
VCVTPS2PH - Convert Single-Precision FP value to 16-bit FP value:
| Opcode/Instruction                   | Op/En  | 64/32bit Mode| CPUID Feature Flag| Description                              
| VEX.256.66.0F3A.W0 1D /r ib VCVTPS2PH| MR imm8| V/V          | F16C              | Convert eight packed single-precision    
| xmm1/m128, ymm2,                     |        |              |                   | floating-point value in ymm2 to packed   
|                                      |        |              |                   | half-precision (16-bit) floating-point   
|                                      |        |              |                   | value in xmm1/mem. Imm8 provides rounding
|                                      |        |              |                   | controls.                                
| VEX.128.66.0F3A.W0.1D /r ib VCVTPS2PH| MR imm8| V/V          | F16C              | Convert four packed single-precision     
| xmm1/m64, xmm2,                      |        |              |                   | floating-point value in xmm2 to packed   
|                                      |        |              |                   | halfprecision (16-bit) floating-point    
|                                      |        |              |                   | value in xmm1/mem. Imm8 provides rounding
|                                      |        |              |                   | controls.                                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
Convert four or eight packed single-precision floating values in first source
operand to four or eight packed halfprecision (16-bit) floating-point values.
The rounding mode is specified using the immediate field (imm8). Underflow results
(i.e. tiny results) are converted to denormals. MXCSR.FTZ is ignored. If a source
element is denormal relative to input format with MXCSR.DAZ not set, DM masked
and at least one of PM or UM unmasked; a SIMD exception will be raised with
DE, UE and PE set. 128-bit version: The source operand is a XMM register. The
destination operand is a XMM register or 64-bit memory location. The upper-bits
vector register zeroing behavior of VEX prefix encoding still applies if the
destination operand is a xmm register. So the upper bits (255:64) of corresponding
YMM register are zeroed. 256-bit version: The source operand is a YMM register.
The destination operand is a XMM register or 128-bit memory location. The upper-bits
vector register zeroing behavior of VEX prefix encoding still applies if the
destination operand is a xmm register. So the upper bits (255:128) of the corresponding
YMM register are zeroed. Note: VEX.vvvv is reserved (must be 1111b). The diagram
below illustrates how data is converted from four packed single precision (in
128 bits) to four half precision (in 64 bits) FP values.

| VCVTPS2PH xmm1/mem64, xmm2, 95 VS2| imm8 0 xmm2                
| convert                           | convert convert            
| 95                                | 0 xmm1/mem64               
| Figure 4-32.                      | VCVTPS2PH (128-bit Version)
The immediate byte defines several bit fields that controls rounding operation.
The effect and encoding of RC field are listed in Table 4-16.


Table 4-16. Immediate Byte Encoding for 16-bit Floating-Point Conversion Instructions:
| Bits          | Field Name/value           | Description                           | Comment        
| Imm[1:0]      | RC=00B RC=01B RC=10B RC=11B| Round to nearest even Round down Round| If Imm[2] = 0  
|               |                            | up Truncate                           |                
| Imm[2]Imm[7:3]| MS1=0 MS1=1 Ignored        | Use imm[1:0] for rounding Use MXCSR.RC| Ignore MXCSR.RC
|               |                            | for rounding Ignored by processor     |                
Operation:

vCvt_s2h(SRC1[31:0])
{
IF Imm[2] = 0
THEN // using Imm[1:0] for rounding control, see Table 4-16
     RETURN Cvt_Single_Precision_To_Half_Precision_FP_Imm(SRC1[31:0]);
ELSE // using MXCSR.RC for rounding control
     RETURN Cvt_Single_Precision_To_Half_Precision_FP_Mxcsr(SRC1[31:0]);
FI;
}
VCVTPS2PH (VEX.256 encoded version)
DEST[15:0] <- vCvt_s2h(SRC1[31:0]);
DEST[31:16] <- vCvt_s2h(SRC1[63:32]);
DEST[47:32] <- vCvt_s2h(SRC1[95:64]);
DEST[63:48] <- vCvt_s2h(SRC1[127:96]);
DEST[79:64] <- vCvt_s2h(SRC1[159:128]);
DEST[95:80] <- vCvt_s2h(SRC1[191:160]);
DEST[111:96] <- vCvt_s2h(SRC1[223:192]);
DEST[127:112] <- vCvt_s2h(SRC1[255:224]);
DEST[255:128] <- 0; // if DEST is a register
VCVTPS2PH (VEX.128 encoded version)
DEST[15:0] <- vCvt_s2h(SRC1[31:0]);
DEST[31:16] <- vCvt_s2h(SRC1[63:32]);
DEST[47:32] <- vCvt_s2h(SRC1[95:64]);
DEST[63:48] <- vCvt_s2h(SRC1[127:96]);
DEST[VLMAX-1:64] <-0; // if DEST is a register

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
__m128i _mm_cvtps_ph ( __m128 m1, const int imm);

__m128i _mm256_cvtps_ph(__m256 m1, const int imm);


SIMD Floating-Point Exceptions:
Invalid, Underflow, Overflow, Precision, Denormal (if MXCSR.DAZ=0);


Other Exceptions:
Exceptions Type 11 (do not report #AC); additionally

| #UD| If VEX.W=1.


platform: x86
mnem: VERR
description:
VERR/VERW - Verify a Segment for Reading or Writing:
| Opcode  | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                             
| 0F 00 /4| VERR r/m16 | M    | Valid      | Valid          | Set ZF=1 if segment specified with r/m16
|         |            |      |            |                | can be read.                            
| 0F 00 /5| VERW r/m16 | M    | Valid      | Valid          | Set ZF=1 if segment specified with r/m16
|         |            |      |            |                | can be written.                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Verifies whether the code or data segment specified with the source operand
is readable (VERR) or writable (VERW) from the current privilege level (CPL).
The source operand is a 16-bit register or a memory location that contains the
segment selector for the segment to be verified. If the segment is accessible
and readable (VERR) or writable (VERW), the ZF flag is set; otherwise, the ZF
flag is cleared. Code segments are never verified as writable. This check cannot
be performed on system segments.

To set the ZF flag, the following conditions must be met:

 - The segment selector is not NULL.
 - The selector must denote a descriptor within the bounds of the descriptor table
(GDT or LDT).
 - The selector must denote the descriptor of a code or data segment (not that
of a system segment or gate).
 - For the VERR instruction, the segment must be readable.
 - For the VERW instruction, the segment must be a writable data segment.
 - If the segment is not a conforming code segment, the segment's DPL must be greater
than or equal to (have less or the same privilege as) both the CPL and the segment
selector's RPL.

The validation performed is the same as is performed when a segment selector
is loaded into the DS, ES, FS, or GS register, and the indicated access (read
or write) is performed. The segment selector's value cannot result in a protection
exception, enabling the software to anticipate possible segment access problems.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.
The operand size is fixed at 16 bits.

Operation:

IF SRC(Offset) > (GDTR(Limit) or (LDTR(Limit))
  THEN ZF <- 0; FI;
Read segment descriptor;
IF SegmentDescriptor(DescriptorType) = 0 (* System segment *)
or (SegmentDescriptor(Type) != conforming code segment)
and (CPL > DPL) or (RPL > DPL)
  THEN
     ZF <- 0;
  ELSE
     IF ((Instruction = VERR) and (Segment readable))
     or ((Instruction = VERW) and (Segment writable))
       THEN
          ZF <- 1;
     FI;
FI;

Flags Affected:
The ZF flag is set to 1 if the segment is accessible and readable (VERR) or
writable (VERW); otherwise, it is set to 0.


Protected Mode Exceptions:
The only exceptions generated for these instructions are those related to illegal
addressing of the source operand.

| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #UD| The VERR and VERW instructions are not
|    | recognized in real-address mode. If   
|    | the LOCK prefix is used.              

Virtual-8086 Mode Exceptions:
| #UD| The VERR and VERW instructions are not
|    | recognized in virtual-8086 mode. If   
|    | the LOCK prefix is used.              

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the        
|                | SS segment is in a non-canonical form.     
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: VEXTRACTF128
description:
VEXTRACTF128  -  Extract Packed Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                              
| VEX.256.66.0F3A.W0 19 /r ib VEXTRACTF128| MR   | V/V           | AVX               | Extract 128 bits of packed floating-point
| xmm1/m128, ymm2, imm8                   |      |               |                   | values from ymm2 and store results in    
|                                         |      |               |                   | xmm1/mem.                                

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| MR   | ModRM:r/m (w)| ModRM:reg (r)| NA       | NA       

Description:
Extracts 128-bits of packed floating-point values from the source operand (second
operand) at an 128-bit offset from imm8[0] into the destination operand (first
operand). The destination may be either an XMM register or an 128-bit memory
location. VEX.vvvv is reserved and must be 1111b otherwise instructions will
#UD. The high 7 bits of the immediate are ignored. If VEXTRACTF128 is encoded
with VEX.L= 0, an attempt to execute the instruction encoded with VEX.L= 0 will
cause an #UD exception.

Operation:

VEXTRACTF128 (memory destination form)
CASE (imm8[0]) OF
  0: DEST[127:0] <- SRC1[127:0]
  1: DEST[127:0] <- SRC1[255:128]
ESAC.
VEXTRACTF128 (register destination form)
CASE (imm8[0]) OF
  0: DEST[127:0] <- SRC1[127:0]
  1: DEST[127:0] <- SRC1[255:128]
ESAC.
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| VEXTRACTF128:| __m128 _mm256_extractf128_ps (__m256   
|              | a, int offset);                        
| VEXTRACTF128:| __m128d _mm256_extractf128_pd (__m256d 
|              | a, int offset);                        
| VEXTRACTF128:| __m128i_mm256_extractf128_si256(__m256i
|              | a, int offset);                        

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| If VEX.L= 0 If VEX.W=1.


platform: x86
mnem: VEXTRACTI128
description:
VEXTRACTI128  -  Extract packed Integer Values:
| Opcode/Instruction                      | Op/En| 64/32-bit Mode| CPUID Feature Flag| Description                          
| VEX.256.66.0F3A.W0 39 /r ib VEXTRACTI128| RMI  | V/V           | AVX2              | Extract 128 bits of integer data from
| xmm1/m128, ymm2, imm8                   |      |               |                   | ymm2 and store results in xmm1/mem.  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:r/m (w)| ModRM:reg (r)| Imm8     | NA       

Description:
Extracts 128-bits of packed integer values from the source operand (second operand)
at a 128-bit offset from imm8[0] into the destination operand (first operand).
The destination may be either an XMM register or a 128-bit memory location.
VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. The
high 7 bits of the immediate are ignored. An attempt to execute VEXTRACTI128
encoded with VEX.L= 0 will cause an #UD exception.

Operation:

VEXTRACTI128 (memory destination form)
CASE (imm8[0]) OF
  0: DEST[127:0] <- SRC1[127:0]
  1: DEST[127:0] <- SRC1[255:128]
ESAC.
VEXTRACTI128 (register destination form)
CASE (imm8[0]) OF
  0: DEST[127:0] <- SRC1[127:0]
  1: DEST[127:0] <- SRC1[255:128]
ESAC.
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| VEXTRACTI128:| __m128i _mm256_extracti128_si256(__m256i
|              | a, int offset);                         

SIMD Floating-Point Exceptions:
None


Other Exceptions:
See Exceptions Type 6; additionally

| #UD| IF VEX.L = 0, If VEX.W = 1.


platform: x86
mnem: VFMADD132PD
description:
VFMADD132PD/VFMADD213PD/VFMADD231PD  -  Fused Multiply-Add of Packed DoublePrecision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 98 /r VFMADD132PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |              |                   | values from xmm0 and xmm2/mem, add to          
|                                         |      |              |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W1 A8 /r VFMADD213PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |              |                   | values from xmm0 and xmm1, add to xmm2/mem     
|                                         |      |              |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W1 B8 /r VFMADD231PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |              |                   | values from xmm1 and xmm2/mem, add to          
|                                         |      |              |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W1 98 /r VFMADD132PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |              |                   | values from ymm0 and ymm2/mem, add to          
|                                         |      |              |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W1 A8 /r VFMADD213PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |              |                   | values from ymm0 and ymm1, add to ymm2/mem     
|                                         |      |              |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.W1 B8 /r VFMADD231PD| A    | V/V          | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |              |                   | values from ymm1 and ymm2/mem, add to          
|                                         |      |              |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a set of SIMD multiply-add computation on packed double-precision floating-point
values using three source operands and writes the multiply-add results in the
destination operand. The destination operand is also the first source operand.
The second operand must be a SIMD register. The third source operand can be
a SIMD register or a memory location. VFMADD132PD: Multiplies the two or four
packed double-precision floating-point values from the first source operand
to the two or four packed double-precision floating-point values in the third
source operand, adds the infinite precision intermediate result to the two or
four packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VFMADD213PD:
Multiplies the two or four packed double-precision floating-point values from
the second source operand to the two or four packed double-precision floating-point
values in the first source operand, adds the infinite precision intermediate
result to the two or four packed double-precision floating-point values in the
third source operand, performs rounding and stores the resulting two or four
packed double-precision floating-point values to the destination operand (first
source operand). VFMADD231PD: Multiplies the two or four packed double-precision
floating-point values from the second source to the two or four packed double-precision
floating-point values in the third source operand, adds the infinite precision
intermediate result to the two or four packed double-precision floating-point
values in the first source operand, performs rounding and stores the resulting
two or four packed double-precision floating-point values to the destination
operand (first source operand). VEX.128 encoded version: The destination operand
(also first source operand) is a XMM register and encoded in reg_field. The
second source operand is a XMM register and encoded in VEX.vvvv. The third source
operand is a XMM register or a 128-bit memory location and encoded in rm_field.
The upper 128 bits of the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADD132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] + SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFMADD213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] + SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFMADD231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] + DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADD132PD: __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);

VFMADD213PD: __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);

VFMADD231PD: __m128d _mm_fmadd_pd (__m128d a, __m128d b, __m128d c);

VFMADD132PD: __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);

VFMADD213PD: __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);

VFMADD231PD: __m256d _mm256_fmadd_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMADD132PS
description:
VFMADD132PS/VFMADD213PS/VFMADD231PS  -  Fused Multiply-Add of Packed SinglePrecision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 98 /r VFMADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm2/mem, add to          
|                                         |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W0 A8 /r VFMADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm1, add to xmm2/mem     
|                                         |      |                |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W0 B8 /r VFMADD231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm1 and xmm2/mem, add to          
|                                         |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W0 98 /r VFMADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm2/mem, add to          
|                                         |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W0 A8 /r VFMADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm1, add to ymm2/mem     
|                                         |      |                |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.W0 B8 /r VFMADD231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm1 and ymm2/mem, add to          
|                                         |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a set of SIMD multiply-add computation on packed single-precision floating-point
values using three source operands and writes the multiply-add results in the
destination operand. The destination operand is also the first source operand.
The second operand must be a SIMD register. The third source operand can be
a SIMD register or a memory location. VFMADD132PS: Multiplies the four or eight
packed single-precision floating-point values from the first source operand
to the four or eight packed single-precision floating-point values in the third
source operand, adds the infinite precision intermediate result to the four
or eight packed single-precision floating-point values in the second source
operand, performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFMADD213PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the first source operand, adds the infinite precision intermediate
result to the four or eight packed single-precision floating-point values in
the third source operand, performs rounding and stores the resulting the four
or eight packed single-precision floating-point values to the destination operand
(first source operand). VFMADD231PS: Multiplies the four or eight packed single-precision
floating-point values from the second source operand to the four or eight packed
single-precision floating-point values in the third source operand, adds the
infinite precision intermediate result to the four or eight packed single-precision
floating-point values in the first source operand, performs rounding and stores
the resulting four or eight packed single-precision floating-point values to
the destination operand (first source operand). VEX.128 encoded version: The
destination operand (also first source operand) is a XMM register and encoded
in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv.
The third source operand is a XMM register or a 128-bit memory location and
encoded in rm_field. The upper 128 bits of the YMM destination register are
zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the “Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1”.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] + SRC3[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADD132PS: __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);

VFMADD213PS: __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);

VFMADD231PS: __m128 _mm_fmadd_ps (__m128 a, __m128 b, __m128 c);

VFMADD132PS: __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);

VFMADD213PS: __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);

VFMADD231PS: __m256 _mm256_fmadd_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMADD132SD
description:
VFMADD132SD/VFMADD213SD/VFMADD231SD  -  Fused Multiply-Add of Scalar DoublePrecision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W1 99 /r VFMADD132SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |              |                   | value from xmm0 and xmm2/mem, add to           
|                                             |      |              |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W1 A9 /r VFMADD213SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |              |                   | value from xmm0 and xmm1, add to xmm2/mem      
|                                             |      |              |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W1 B9 /r VFMADD231SD| A    | V/V          | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |              |                   | value from xmm1 and xmm2/mem, add to           
|                                             |      |              |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply-add computation on the low packed double-precision
floating-point values using three source operands and writes the multiply-add
result in the destination operand. The destination operand is also the first
source operand. The second operand must be a SIMD register. The third source
operand can be a SIMD register or a memory location. VFMADD132SD: Multiplies
the low packed double-precision floating-point value from the first source operand
to the low packed double-precision floating-point value in the third source
operand, adds the infinite precision intermediate result to the low packed double-precision
floating-point values in the second source operand, performs rounding and stores
the resulting packed double-precision floating-point value to the destination
operand (first source operand). VFMADD213SD: Multiplies the low packed double-precision
floating-point value from the second source operand to the low packed double-precision
floating-point value in the first source operand, adds the infinite precision
intermediate result to the low packed double-precision floating-point value
in the third source operand, performs rounding and stores the resulting packed
double-precision floating-point value to the destination operand (first source
operand). VFMADD231SD: Multiplies the low packed double-precision floating-point
value from the second source to the low packed double-precision floating-point
value in the third source operand, adds the infinite precision intermediate
result to the low packed double-precision floating-point value in the first
source operand, performs rounding and stores the resulting packed double-precision
floating-point value to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 64-bit
memory location and encoded in rm_field. The upper bits ([VLMAX-1:128]) of the
YMM destination register are zeroed. Compiler tools may optionally support a
complementary mnemonic for each instruction mnemonic listed in the opcode/instruction
column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined
in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction
Operand Order and Arithmetic Behavior” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADD132SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFMADD213SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFMADD231SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADD132SD: __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);

VFMADD213SD: __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);

VFMADD231SD: __m128d _mm_fmadd_sd (__m128d a, __m128d b, __m128d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFMADD132SS
description:
VFMADD132SS/VFMADD213SS/VFMADD231SS  -  Fused Multiply-Add of Scalar Single-Precision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W0 99 /r VFMADD132SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm0 and xmm2/mem, add to           
|                                             |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W0 A9 /r VFMADD213SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm0 and xmm1, add to xmm2/mem      
|                                             |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W0 B9 /r VFMADD231SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm1 and xmm2/mem, add to           
|                                             |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply-add computation on packed single-precision floating-point
values using three source operands and writes the multiply-add results in the
destination operand. The destination operand is also the first source operand.
The second operand must be a SIMD register. The third source operand can be
a SIMD register or a memory location. VFMADD132SS: Multiplies the low packed
single-precision floating-point value from the first source operand to the low
packed single-precision floating-point value in the third source operand, adds
the infinite precision intermediate result to the low packed single-precision
floating-point value in the second source operand, performs rounding and stores
the resulting packed single-precision floating-point value to the destination
operand (first source operand). VFMADD213SS: Multiplies the low packed single-precision
floating-point value from the second source operand to the low packed single-precision
floating-point value in the first source operand, adds the infinite precision
intermediate result to the low packed single-precision floating-point value
in the third source operand, performs rounding and stores the resulting packed
single-precision floating-point value to the destination operand (first source
operand). VFMADD231SS: Multiplies the low packed single-precision floating-point
value from the second source operand to the low packed single-precision floating-point
value in the third source operand, adds the infinite precision intermediate
result to the low packed single-precision floating-point value in the first
source operand, performs rounding and stores the resulting packed single-precision
floating-point value to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 32-bit
memory location and encoded in rm_field. The upper bits ([VLMAX-1:128]) of the
YMM destination register are zeroed. Compiler tools may optionally support a
complementary mnemonic for each instruction mnemonic listed in the opcode/instruction
column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined
in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction
Operand Order and Arithmetic Behavior” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADD132SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] + SRC2[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFMADD213SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] + SRC3[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFMADD231SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(SRC2[31:0]*SRC3[63:0] + DEST[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADD132SS: __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);

VFMADD213SS: __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);

VFMADD231SS: __m128 _mm_fmadd_ss (__m128 a, __m128 b, __m128 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFMADDSUB132PD
description:
VFMADDSUB132PD/VFMADDSUB213PD/VFMADDSUB231PD  -  Fused Multiply-Alternating Add/Subtract of Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 96 /r VFMADDSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm2/mem, add/subtract    
|                                            |      |                |                   | elements in xmm1 and put result in xmm0.       
| VEX.DDS.128.66.0F38.W1 A6 /r VFMADDSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm1, add/subtract        
|                                            |      |                |                   | elements in xmm2/mem and put result            
|                                            |      |                |                   | in xmm0.                                       
| VEX.DDS.128.66.0F38.W1 B6 /r VFMADDSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm1 and xmm2/mem, add/subtract    
|                                            |      |                |                   | elements in xmm0 and put result in xmm0.       
| VEX.DDS.256.66.0F38.W1 96 /r VFMADDSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm2/mem, add/subtract    
|                                            |      |                |                   | elements in ymm1 and put result in ymm0.       
| VEX.DDS.256.66.0F38.W1 A6 /r VFMADDSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm1, add/subtract        
|                                            |      |                |                   | elements in ymm2/mem and put result            
|                                            |      |                |                   | in ymm0.                                       
| VEX.DDS.256.66.0F38.W1 B6 /r VFMADDSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm1 and ymm2/mem, add/subtract    
|                                            |      |                |                   | elements in ymm0 and put result in ymm0.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFMADDSUB132PD: Multiplies the two or four packed double-precision floating-point
values from the first source operand to the two or four packed double-precision
floating-point values in the third source operand. From the infinite precision
intermediate result, adds the odd double-precision floating-point elements and
subtracts the even double-precision floating-point values in the second source
operand, performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VFMADDSUB213PD:
Multiplies the two or four packed double-precision floating-point values from
the second source operand to the two or four packed double-precision floating-point
values in the first source operand. From the infinite precision intermediate
result, adds the odd double-precision floating-point elements and subtracts
the even double-precision floating-point values in the third source operand,
performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VFMADDSUB231PD:
Multiplies the two or four packed double-precision floating-point values from
the second source operand to the two or four packed double-precision floating-point
values in the third source operand. From the infinite precision intermediate
result, adds the odd double-precision floating-point elements and subtracts
the even double-precision floating-point values in the first source operand,
performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit
memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field.

Compiler tools may optionally support a complementary mnemonic for each instruction
mnemonic listed in the opcode/instruction column of the summary table. The behavior
of the complementary mnemonic in situations involving NANs are governed by the
definition of the instruction mnemonic defined in the opcode/instruction column.
See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADDSUB132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] + SRC2[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] - SRC2[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] + SRC2[255:192]
FI
VFMADDSUB213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] + SRC3[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] - SRC3[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] + SRC3[255:192]
FI
VFMADDSUB231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] + DEST[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] - DEST[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] + DEST[255:192]
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADDSUB132PD: __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);

VFMADDSUB213PD: __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);

VFMADDSUB231PD: __m128d _mm_fmaddsub_pd (__m128d a, __m128d b, __m128d c);

VFMADDSUB132PD: __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);

VFMADDSUB213PD: __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);

VFMADDSUB231PD: __m256d _mm256_fmaddsub_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMADDSUB132PS
description:
VFMADDSUB132PS/VFMADDSUB213PS/VFMADDSUB231PS  -  Fused Multiply-Alternating Add/Subtract of Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 96 /r VFMADDSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm2/mem, add/subtract    
|                                            |      |                |                   | elements in xmm1 and put result in xmm0.       
| VEX.DDS.128.66.0F38.W0 A6 /r VFMADDSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm1, add/subtract        
|                                            |      |                |                   | elements in xmm2/mem and put result            
|                                            |      |                |                   | in xmm0.                                       
| VEX.DDS.128.66.0F38.W0 B6 /r VFMADDSUB231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm1 and xmm2/mem, add/subtract    
|                                            |      |                |                   | elements in xmm0 and put result in xmm0.       
| VEX.DDS.256.66.0F38.W0 96 /r VFMADDSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm2/mem, add/subtract    
|                                            |      |                |                   | elements in ymm1 and put result in ymm0.       
| VEX.DDS.256.66.0F38.W0 A6 /r VFMADDSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm1, add/subtract        
|                                            |      |                |                   | elements in ymm2/mem and put result            
|                                            |      |                |                   | in ymm0.                                       
| VEX.DDS.256.66.0F38.W0 B6 /r VFMADDSUB231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm1 and ymm2/mem, add/subtract    
|                                            |      |                |                   | elements in ymm0 and put result in ymm0.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFMADDSUB132PS: Multiplies the four or eight packed single-precision floating-point
values from the first source operand to the four or eight packed single-precision
floating-point values in the third source operand. From the infinite precision
intermediate result, adds the odd single-precision floating-point elements and
subtracts the even single-precision floating-point values in the second source
operand, performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFMADDSUB213PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the first source operand. From the infinite precision intermediate
result, adds the odd single-precision floating-point elements and subtracts
the even single-precision floating-point values in the third source operand,
performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFMADDSUB231PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the third source operand. From the infinite precision intermediate
result, adds the odd single-precision floating-point elements and subtracts
the even single-precision floating-point values in the first source operand,
performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit
memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field.

Compiler tools may optionally support a complementary mnemonic for each instruction
mnemonic listed in the opcode/instruction column of the summary table. The behavior
of the complementary mnemonic in situations involving NANs are governed by the
definition of the instruction mnemonic defined in the opcode/instruction column.
See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMADDSUB132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] + SRC2[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMADDSUB213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] + SRC3[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMADDSUB231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] + DEST[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMADDSUB132PS: __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);

VFMADDSUB213PS: __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);

VFMADDSUB231PS: __m128 _mm_fmaddsub_ps (__m128 a, __m128 b, __m128 c);

VFMADDSUB132PS: __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);

VFMADDSUB213PS: __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);

VFMADDSUB231PS: __m256 _mm256_fmaddsub_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMSUBADD132PD
description:
VFMSUBADD132PD/VFMSUBADD213PD/VFMSUBADD231PD  -  Fused Multiply-Alternating Subtract/Add of Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 97 /r VFMSUBADD132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm2/mem, subtract/add    
|                                            |      |                |                   | elements in xmm1 and put result in xmm0.       
| VEX.DDS.128.66.0F38.W1 A7 /r VFMSUBADD213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm1, subtract/add        
|                                            |      |                |                   | elements in xmm2/mem and put result            
|                                            |      |                |                   | in xmm0.                                       
| VEX.DDS.128.66.0F38.W1 B7 /r VFMSUBADD231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm1 and xmm2/mem, subtract/add    
|                                            |      |                |                   | elements in xmm0 and put result in xmm0.       
| VEX.DDS.256.66.0F38.W1 97 /r VFMSUBADD132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm2/mem, subtract/add    
|                                            |      |                |                   | elements in ymm1 and put result in ymm0.       
| VEX.DDS.256.66.0F38.W1 A7 /r VFMSUBADD213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm1, subtract/add        
|                                            |      |                |                   | elements in ymm2/mem and put result            
|                                            |      |                |                   | in ymm0.                                       
| VEX.DDS.256.66.0F38.W1 B7 /r VFMSUBADD231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm1 and ymm2/mem, subtract/add    
|                                            |      |                |                   | elements in ymm0 and put result in ymm0.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFMSUBADD132PD: Multiplies the two or four packed double-precision floating-point
values from the first source operand to the two or four packed double-precision
floating-point values in the third source operand. From the infinite precision
intermediate result, subtracts the odd double-precision floating-point elements
and adds the even double-precision floating-point values in the second source
operand, performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VFMSUBADD213PD:
Multiplies the two or four packed double-precision floating-point values from
the second source operand to the two or four packed double-precision floating-point
values in the first source operand. From the infinite precision intermediate
result, subtracts the odd double-precision floating-point elements and adds
the even double-precision floating-point values in the third source operand,
performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VFMSUBADD231PD:
Multiplies the two or four packed double-precision floating-point values from
the second source operand to the two or four packed double-precision floating-point
values in the third source operand. From the infinite precision intermediate
result, subtracts the odd double-precision floating-point elements and adds
the even double-precision floating-point values in the first source operand,
performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit
memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field.

Compiler tools may optionally support a complementary mnemonic for each instruction
mnemonic listed in the opcode/instruction column of the summary table. The behavior
of the complementary mnemonic in situations involving NANs are governed by the
definition of the instruction mnemonic defined in the opcode/instruction column.
See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUBADD132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] + SRC2[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(DEST[127:64]*SRC3[127:64] - SRC2[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(DEST[191:128]*SRC3[191:128] + SRC2[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(DEST[255:192]*SRC3[255:192] - SRC2[255:192]
FI
VFMSUBADD213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] + SRC3[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*DEST[127:64] - SRC3[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(SRC2[191:128]*DEST[191:128] + SRC3[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(SRC2[255:192]*DEST[255:192] - SRC3[255:192]
FI
VFMSUBADD231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
  DEST[VLMAX-1:128] <- 0
ELSEIF (VEX.256)
  DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] + DEST[63:0])
  DEST[127:64] <- RoundFPControl_MXCSR(SRC2[127:64]*SRC3[127:64] - DEST[127:64])
  DEST[191:128] <- RoundFPControl_MXCSR(SRC2[191:128]*SRC3[191:128] + DEST[191:128])
  DEST[255:192] <- RoundFPControl_MXCSR(SRC2[255:192]*SRC3[255:192] - DEST[255:192]
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUBADD132PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);

VFMSUBADD213PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);

VFMSUBADD231PD: __m128d _mm_fmsubadd_pd (__m128d a, __m128d b, __m128d c);

VFMSUBADD132PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);

VFMSUBADD213PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);

VFMSUBADD231PD: __m256d _mm256_fmsubadd_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMSUBADD132PS
description:
VFMSUBADD132PS/VFMSUBADD213PS/VFMSUBADD231PS  -  Fused Multiply-Alternating Subtract/Add of Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                         | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 97 /r VFMSUBADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm2/mem, subtract/add    
|                                            |      |                |                   | elements in xmm1 and put result in xmm0.       
| VEX.DDS.128.66.0F38.W0 A7 /r VFMSUBADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm0 and xmm1, subtract/add        
|                                            |      |                |                   | elements in xmm2/mem and put result            
|                                            |      |                |                   | in xmm0.                                       
| VEX.DDS.128.66.0F38.W0 B7 /r VFMSUBADD231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                      |      |                |                   | values from xmm1 and xmm2/mem, subtract/add    
|                                            |      |                |                   | elements in xmm0 and put result in xmm0.       
| VEX.DDS.256.66.0F38.W0 97 /r VFMSUBADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm2/mem, subtract/add    
|                                            |      |                |                   | elements in ymm1 and put result in ymm0.       
| VEX.DDS.256.66.0F38.W0 A7 /r VFMSUBADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm0 and ymm1, subtract/add        
|                                            |      |                |                   | elements in ymm2/mem and put result            
|                                            |      |                |                   | in ymm0.                                       
| VEX.DDS.256.66.0F38.W0 B7 /r VFMSUBADD231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                      |      |                |                   | values from ymm1 and ymm2/mem, subtract/add    
|                                            |      |                |                   | elements in ymm0 and put result in ymm0.       

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFMSUBADD132PS: Multiplies the four or eight packed single-precision floating-point
values from the first source operand to the four or eight packed single-precision
floating-point values in the third source operand. From the infinite precision
intermediate result, subtracts the odd single-precision floating-point elements
and adds the even single-precision floating-point values in the second source
operand, performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFMSUBADD213PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the first source operand. From the infinite precision intermediate
result, subtracts the odd single-precision floating-point elements and adds
the even single-precision floating-point values in the third source operand,
performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFMSUBADD231PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the third source operand. From the infinite precision intermediate
result, subtracts the odd single-precision floating-point elements and adds
the even single-precision floating-point values in the first source operand,
performs rounding and stores the resulting four or eight packed single-precision
floating-point values to the destination operand (first source operand). VEX.128
encoded version: The destination operand (also first source operand) is a XMM
register and encoded in reg_field. The second source operand is a XMM register
and encoded in VEX.vvvv. The third source operand is a XMM register or a 128-bit
memory location and encoded in rm_field. The upper 128 bits of the YMM destination
register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field.

Compiler tools may optionally support a complementary mnemonic for each instruction
mnemonic listed in the opcode/instruction column of the summary table. The behavior
of the complementary mnemonic in situations involving NANs are governed by the
definition of the instruction mnemonic defined in the opcode/instruction column.
See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUBADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] + SRC2[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(DEST[n+63:n+32]*SRC3[n+63:n+32] -SRC2[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMSUBADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] +SRC3[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(SRC2[n+63:n+32]*DEST[n+63:n+32] -SRC3[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMSUBADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL -1{
  n = 64*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] + DEST[n+31:n])
  DEST[n+63:n+32] <- RoundFPControl_MXCSR(SRC2[n+63:n+32]*SRC3[n+63:n+32] -DEST[n+63:n+32])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUBADD132PS: __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);

VFMSUBADD213PS: __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);

VFMSUBADD231PS: __m128 _mm_fmsubadd_ps (__m128 a, __m128 b, __m128 c);

VFMSUBADD132PS: __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);

VFMSUBADD213PS: __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);

VFMSUBADD231PS: __m256 _mm256_fmsubadd_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMSUB132PD
description:
VFMSUB132PD/VFMSUB213PD/VFMSUB231PD  -  Fused Multiply-Subtract of Packed DoublePrecision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 9A /r VFMSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm2/mem, subtract        
|                                         |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W1 AA /r VFMSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm1, subtract            
|                                         |      |                |                   | xmm2/mem and put result in xmm0.               
| VEX.DDS.128.66.0F38.W1 BA /r VFMSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm1 and xmm2/mem, subtract        
|                                         |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W1 9A /r VFMSUB132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm2/mem, subtract        
|                                         |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W1 AA /r VFMSUB213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm1, subtract            
|                                         |      |                |                   | ymm2/mem and put result in ymm0.               
| VEX.DDS.256.66.0F38.W1 BA /r VFMSUB231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm1 and ymm2/mem, subtract        
|                                         |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a set of SIMD multiply-subtract computation on packed double-precision
floating-point values using three source operands and writes the multiply-subtract
results in the destination operand. The destination operand is also the first
source operand. The second operand must be a SIMD register. The third source
operand can be a SIMD register or a memory location. VFMSUB132PD: Multiplies
the two or four packed double-precision floating-point values from the first
source operand to the two or four packed double-precision floating-point values
in the third source operand. From the infinite precision intermediate result,
subtracts the two or four packed double-precision floating-point values in the
second source operand, performs rounding and stores the resulting two or four
packed double-precision floatingpoint values to the destination operand (first
source operand). VFMSUB213PD: Multiplies the two or four packed double-precision
floating-point values from the second source operand to the two or four packed
double-precision floating-point values in the first source operand. From the
infinite precision intermediate result, subtracts the two or four packed double-precision
floating-point values in the third source operand, performs rounding and stores
the resulting two or four packed double-precision floatingpoint values to the
destination operand (first source operand). VFMSUB231PD: Multiplies the two
or four packed double-precision floating-point values from the second source
to the two or four packed double-precision floating-point values in the third
source operand. From the infinite precision intermediate result, subtracts the
two or four packed double-precision floating-point values in the first source
operand, performs rounding and stores the resulting two or four packed double-precision
floating-point values to the destination operand (first source operand).

VEX.128 encoded version: The destination operand (also first source operand)
is a XMM register and encoded in reg_field. The second source operand is a XMM
register and encoded in VEX.vvvv. The third source operand is a XMM register
or a 128-bit memory location and encoded in rm_field. The upper 128 bits of
the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUB132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(DEST[n+63:n]*SRC3[n+63:n] - SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFMSUB213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*DEST[n+63:n] - SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFMSUB231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(SRC2[n+63:n]*SRC3[n+63:n] - DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUB132PD: __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);

VFMSUB213PD: __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);

VFMSUB231PD: __m128d _mm_fmsub_pd (__m128d a, __m128d b, __m128d c);

VFMSUB132PD: __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);

VFMSUB213PD: __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);

VFMSUB231PD: __m256d _mm256_fmsub_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMSUB132PS
description:
VFMSUB132PS/VFMSUB213PS/VFMSUB231PS  -  Fused Multiply-Subtract of Packed SinglePrecision Floating-Point Values:
| Opcode/Instruction                      | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 9A /r VFMSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm2/mem, subtract        
|                                         |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W0 AA /r VFMSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm0 and xmm1, subtract            
|                                         |      |                |                   | xmm2/mem and put result in xmm0.               
| VEX.DDS.128.66.0F38.W0 BA /r VFMSUB231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                   |      |                |                   | values from xmm1 and xmm2/mem, subtract        
|                                         |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W0 9A /r VFMSUB132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm2/mem, subtract        
|                                         |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W0 AA /r VFMSUB213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm0 and ymm1, subtract            
|                                         |      |                |                   | ymm2/mem and put result in ymm0.               
| VEX.DDS.256.66.0F38.0 BA /r VFMSUB231PS | A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                   |      |                |                   | values from ymm1 and ymm2/mem, subtract        
|                                         |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a set of SIMD multiply-subtract computation on packed single-precision
floating-point values using three source operands and writes the multiply-subtract
results in the destination operand. The destination operand is also the first
source operand. The second operand must be a SIMD register. The third source
operand can be a SIMD register or a memory location. VFMSUB132PS: Multiplies
the four or eight packed single-precision floating-point values from the first
source operand to the four or eight packed single-precision floating-point values
in the third source operand. From the infinite precision intermediate result,
subtracts the four or eight packed single-precision floating-point values in
the second source operand, performs rounding and stores the resulting four or
eight packed single-precision floatingpoint values to the destination operand
(first source operand). VFMSUB213PS: Multiplies the four or eight packed single-precision
floating-point values from the second source operand to the four or eight packed
single-precision floating-point values in the first source operand. From the
infinite precision intermediate result, subtracts the four or eight packed single-precision
floating-point values in the third source operand, performs rounding and stores
the resulting four or eight packed single-precision floatingpoint values to
the destination operand (first source operand). VFMSUB231PS: Multiplies the
four or eight packed single-precision floating-point values from the second
source to the four or eight packed single-precision floating-point values in
the third source operand. From the infinite precision intermediate result, subtracts
the four or eight packed single-precision floating-point values in the first
source operand, performs rounding and stores the resulting four or eight packed
single-precision floating-point values to the destination operand (first source
operand). VEX.128 encoded version: The destination operand (also first source
operand) is a XMM register and encoded in reg_field. The second source operand
is a XMM register and encoded in VEX.vvvv. The third source operand is a XMM
register or a 128-bit memory location and encoded in rm_field. The upper 128
bits of the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUB132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(DEST[n+31:n]*SRC3[n+31:n] - SRC2[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMSUB213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*DEST[n+31:n] - SRC3[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFMSUB231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(SRC2[n+31:n]*SRC3[n+31:n] - DEST[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUB132PS: __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);

VFMSUB213PS: __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);

VFMSUB231PS: __m128 _mm_fmsub_ps (__m128 a, __m128 b, __m128 c);

VFMSUB132PS: __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);

VFMSUB213PS: __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);

VFMSUB231PS: __m256 _mm256_fmsub_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFMSUB132SD
description:
VFMSUB132SD/VFMSUB213SD/VFMSUB231SD  -  Fused Multiply-Subtract of Scalar DoublePrecision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W1 9B /r VFMSUB132SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |                |                   | value from xmm0 and xmm2/mem, subtract         
|                                             |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W1 AB /r VFMSUB213SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |                |                   | value from xmm0 and xmm1, subtract xmm2/mem    
|                                             |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W1 BB /r VFMSUB231SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                        |      |                |                   | value from xmm1 and xmm2/mem, subtract         
|                                             |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply-subtract computation on the low packed double-precision
floating-point values using three source operands and writes the multiply-add
result in the destination operand. The destination operand is also the first
source operand. The second operand must be a SIMD register. The third source
operand can be a SIMD register or a memory location. VFMSUB132SD: Multiplies
the low packed double-precision floating-point value from the first source operand
to the low packed double-precision floating-point value in the third source
operand. From the infinite precision intermediate result, subtracts the low
packed double-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed double-precision floating-point
value to the destination operand (first source operand). VFMSUB213SD: Multiplies
the low packed double-precision floating-point value from the second source
operand to the low packed double-precision floating-point value in the first
source operand. From the infinite precision intermediate result, subtracts the
low packed double-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed double-precision floating-point
value to the destination operand (first source operand). VFMSUB231SD: Multiplies
the low packed double-precision floating-point value from the second source
to the low packed double-precision floating-point value in the third source
operand. From the infinite precision intermediate result, subtracts the low
packed double-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed double-precision floating-point value
to the destination operand (first source operand). VEX.128 encoded version:
The destination operand (also first source operand) is a XMM register and encoded
in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv.
The third source operand is a XMM register or a 64-bit memory location and encoded
in rm_field. The upper bits ([VLMAX-1:128]) of the YMM destination register
are zeroed. Compiler tools may optionally support a complementary mnemonic for
each instruction mnemonic listed in the opcode/instruction column of the summary
table. The behavior of the complementary mnemonic in situations involving NANs
are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic
Behavior” in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUB132SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(DEST[63:0]*SRC3[63:0] - SRC2[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFMSUB213SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*DEST[63:0] - SRC3[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFMSUB231SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(SRC2[63:0]*SRC3[63:0] - DEST[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUB132SD: __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);

VFMSUB213SD: __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);

VFMSUB231SD: __m128d _mm_fmsub_sd (__m128d a, __m128d b, __m128d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFMSUB132SS
description:
VFMSUB132SS/VFMSUB213SS/VFMSUB231SS  -  Fused Multiply-Subtract of Scalar SinglePrecision Floating-Point Values:
| Opcode/Instruction                          | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W0 9B /r VFMSUB132SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm0 and xmm2/mem, subtract         
|                                             |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W0 AB /r VFMSUB213SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm0 and xmm1, subtract xmm2/mem    
|                                             |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W0 BB /r VFMSUB231SS| A    | V/V            | FMA               | Multiply scalar single-precision floating-point
| xmm0, xmm1, xmm2/m32                        |      |                |                   | value from xmm1 and xmm2/mem, subtract         
|                                             |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
Performs a SIMD multiply-subtract computation on the low packed single-precision
floating-point values using three source operands and writes the multiply-add
result in the destination operand. The destination operand is also the first
source operand. The second operand must be a SIMD register. The third source
operand can be a SIMD register or a memory location. VFMSUB132SS: Multiplies
the low packed single-precision floating-point value from the first source operand
to the low packed single-precision floating-point value in the third source
operand. From the infinite precision intermediate result, subtracts the low
packed single-precision floating-point values in the second source operand,
performs rounding and stores the resulting packed single-precision floating-point
value to the destination operand (first source operand). VFMSUB213SS: Multiplies
the low packed single-precision floating-point value from the second source
operand to the low packed single-precision floating-point value in the first
source operand. From the infinite precision intermediate result, subtracts the
low packed single-precision floating-point value in the third source operand,
performs rounding and stores the resulting packed single-precision floating-point
value to the destination operand (first source operand). VFMSUB231SS: Multiplies
the low packed single-precision floating-point value from the second source
to the low packed single-precision floating-point value in the third source
operand. From the infinite precision intermediate result, subtracts the low
packed single-precision floating-point value in the first source operand, performs
rounding and stores the resulting packed single-precision floating-point value
to the destination operand (first source operand). VEX.128 encoded version:
The destination operand (also first source operand) is a XMM register and encoded
in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv.
The third source operand is a XMM register or a 32-bit memory location and encoded
in rm_field. The upper bits ([VLMAX-1:128]) of the YMM destination register
are zeroed. Compiler tools may optionally support a complementary mnemonic for
each instruction mnemonic listed in the opcode/instruction column of the summary
table. The behavior of the complementary mnemonic in situations involving NANs
are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic
Behavior” in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFMSUB132SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(DEST[31:0]*SRC3[31:0] - SRC2[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFMSUB213SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(SRC2[31:0]*DEST[31:0] - SRC3[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0
VFMSUB231SS DEST, SRC2, SRC3
DEST[31:0] <- RoundFPControl_MXCSR(SRC2[31:0]*SRC3[63:0] - DEST[31:0])
DEST[127:32] <- DEST[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFMSUB132SS: __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);

VFMSUB213SS: __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);

VFMSUB231SS: __m128 _mm_fmsub_ss (__m128 a, __m128 b, __m128 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


platform: x86
mnem: VFNMADD132PD
description:
VFNMADD132PD/VFNMADD213PD/VFNMADD231PD  -  Fused Negative Multiply-Add of Packed Double-Precision Floating-Point Values:
| Opcode/Instruction                       | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W1 9C /r VFNMADD132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W1 AC /r VFNMADD213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm1, negate the          
|                                          |      |                |                   | multiplication result and add to xmm2/mem      
|                                          |      |                |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W1 BC /r VFNMADD231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm1 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W1 9C /r VFNMADD132PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W1 AC /r VFNMADD213PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm1, negate the          
|                                          |      |                |                   | multiplication result and add to ymm2/mem      
|                                          |      |                |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.W1 BC /r VFNMADD231PD| A    | V/V            | FMA               | Multiply packed double-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm1 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMADD132PD: Multiplies the two or four packed double-precision floating-point
values from the first source operand to the two or four packed double-precision
floating-point values in the third source operand, adds the negated infinite
precision intermediate result to the two or four packed double-precision floating-point
values in the second source operand, performs rounding and stores the resulting
two or four packed double-precision floatingpoint values to the destination
operand (first source operand). VFNMADD213PD: Multiplies the two or four packed
double-precision floating-point values from the second source operand to the
two or four packed double-precision floating-point values in the first source
operand, adds the negated infinite precision intermediate result to the two
or four packed double-precision floating-point values in the third source operand,
performs rounding and stores the resulting two or four packed double-precision
floatingpoint values to the destination operand (first source operand). VFNMADD231PD:
Multiplies the two or four packed double-precision floating-point values from
the second source to the two or four packed double-precision floating-point
values in the third source operand, adds the negated infinite precision intermediate
result to the two or four packed double-precision floating-point values in the
first source operand, performs rounding and stores the resulting two or four
packed double-precision floating-point values to the destination operand (first
source operand). VEX.128 encoded version: The destination operand (also first
source operand) is a XMM register and encoded in reg_field. The second source
operand is a XMM register and encoded in VEX.vvvv. The third source operand
is a

XMM register or a 128-bit memory location and encoded in rm_field. The upper
128 bits of the YMM destination register are zeroed.

VEX.256 encoded version: The destination operand (also first source operand)
is a YMM register and encoded in reg_field. The second source operand is a YMM
register and encoded in VEX.vvvv. The third source operand is a YMM register
or a 256-bit memory location and encoded in rm_field. Compiler tools may optionally
support a complementary mnemonic for each instruction mnemonic listed in the
opcode/instruction column of the summary table. The behavior of the complementary
mnemonic in situations involving NANs are governed by the definition of the
instruction mnemonic defined in the opcode/instruction column. See also Section
14.5.1, “FMA Instruction Operand Order and Arithmetic Behavior” in the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMADD132PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(-(DEST[n+63:n]*SRC3[n+63:n]) + SRC2[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFNMADD213PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*DEST[n+63:n]) + SRC3[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI
VFNMADD231PD DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =2
ELSEIF (VEX.256)
  MAXVL = 4
FI
For i = 0 to MAXVL-1 {
  n = 64*i;
  DEST[n+63:n] <- RoundFPControl_MXCSR(-(SRC2[n+63:n]*SRC3[n+63:n]) + DEST[n+63:n])
}
IF (VEX.128) THEN
DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMADD132PD: __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);

VFNMADD213PD: __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);

VFNMADD231PD: __m128d _mm_fnmadd_pd (__m128d a, __m128d b, __m128d c);

VFNMADD132PD: __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);

VFNMADD213PD: __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);

VFNMADD231PD: __m256d _mm256_fnmadd_pd (__m256d a, __m256d b, __m256d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFNMADD132PS
description:
VFNMADD132PS/VFNMADD213PS/VFNMADD231PS  -  Fused Negative Multiply-Add of Packed Single-Precision Floating-Point Values:
| Opcode/Instruction                       | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.128.66.0F38.W0 9C /r VFNMADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.128.66.0F38.W0 AC /r VFNMADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm0 and xmm1, negate the          
|                                          |      |                |                   | multiplication result and add to xmm2/mem      
|                                          |      |                |                   | and put result in xmm0.                        
| VEX.DDS.128.66.0F38.W0 BC /r VFNMADD231PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| xmm0, xmm1, xmm2/m128                    |      |                |                   | values from xmm1 and xmm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | xmm0 and put result in xmm0.                   
| VEX.DDS.256.66.0F38.W0 9C /r VFNMADD132PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | ymm1 and put result in ymm0.                   
| VEX.DDS.256.66.0F38.W0 AC /r VFNMADD213PS| A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm0 and ymm1, negate the          
|                                          |      |                |                   | multiplication result and add to ymm2/mem      
|                                          |      |                |                   | and put result in ymm0.                        
| VEX.DDS.256.66.0F38.0 BC /r VFNMADD231PS | A    | V/V            | FMA               | Multiply packed single-precision floating-point
| ymm0, ymm1, ymm2/m256                    |      |                |                   | values from ymm1 and ymm2/mem, negate          
|                                          |      |                |                   | the multiplication result and add to           
|                                          |      |                |                   | ymm0 and put result in ymm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMADD132PS: Multiplies the four or eight packed single-precision floating-point
values from the first source operand to the four or eight packed single-precision
floating-point values in the third source operand, adds the negated infinite
precision intermediate result to the four or eight packed single-precision floating-point
values in the second source operand, performs rounding and stores the resulting
four or eight packed single-precision floating-point values to the destination
operand (first source operand). VFNMADD213PS: Multiplies the four or eight packed
single-precision floating-point values from the second source operand to the
four or eight packed single-precision floating-point values in the first source
operand, adds the negated infinite precision intermediate result to the four
or eight packed single-precision floating-point values in the third source operand,
performs rounding and stores the resulting the four or eight packed single-precision
floating-point values to the destination operand (first source operand). VFNMADD231PS:
Multiplies the four or eight packed single-precision floating-point values from
the second source operand to the four or eight packed single-precision floating-point
values in the third source operand, adds the negated infinite precision intermediate
result to the four or eight packed single-precision floating-point values in
the first source operand, performs rounding and stores the resulting four or
eight packed single-precision floatingpoint values to the destination operand
(first source operand). VEX.256 encoded version: The destination operand (also
first source operand) is a YMM register and encoded in reg_field. The second
source operand is a YMM register and encoded in VEX.vvvv. The third source operand
is a YMM register or a 256-bit memory location and encoded in rm_field.

VEX.128 encoded version: The destination operand (also first source operand)
is a XMM register and encoded in reg_field. The second source operand is a XMM
register and encoded in VEX.vvvv. The third source operand is a XMM register
or a 128-bit memory location and encoded in rm_field. The upper 128 bits of
the YMM destination register are zeroed. Compiler tools may optionally support
a complementary mnemonic for each instruction mnemonic listed in the opcode/instruction
column of the summary table. The behavior of the complementary mnemonic in situations
involving NANs are governed by the definition of the instruction mnemonic defined
in the opcode/instruction column. See also Section 14.5.1, “FMA Instruction
Operand Order and Arithmetic Behavior” in the Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMADD132PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(- (DEST[n+31:n]*SRC3[n+31:n]) + SRC2[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFNMADD213PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*DEST[n+31:n]) + SRC3[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI
VFNMADD231PS DEST, SRC2, SRC3
IF (VEX.128) THEN
  MAXVL =4
ELSEIF (VEX.256)
  MAXVL = 8
FI
For i = 0 to MAXVL-1 {
  n = 32*i;
  DEST[n+31:n] <- RoundFPControl_MXCSR(- (SRC2[n+31:n]*SRC3[n+31:n]) + DEST[n+31:n])
}
IF (VEX.128) THEN
  DEST[VLMAX-1:128] <- 0
FI

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMADD132PS: __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);

VFNMADD213PS: __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);

VFNMADD231PS: __m128 _mm_fnmadd_ps (__m128 a, __m128 b, __m128 c);

VFNMADD132PS: __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);

VFNMADD213PS: __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);

VFNMADD231PS: __m256 _mm256_fnmadd_ps (__m256 a, __m256 b, __m256 c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 2


platform: x86
mnem: VFNMADD132SD
description:
VFNMADD132SD/VFNMADD213SD/VFNMADD231SD  -  Fused Negative Multiply-Add of Scalar Double-Precision Floating-Point Values:
| Opcode/Instruction                           | Op/En| 64/32 -bit Mode| CPUID Feature Flag| Description                                    
| VEX.DDS.LIG.128.66.0F38.W1 9D /r VFNMADD132SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |                |                   | value from xmm0 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and add to           
|                                              |      |                |                   | xmm1 and put result in xmm0.                   
| VEX.DDS.LIG.128.66.0F38.W1 AD /r VFNMADD213SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |                |                   | value from xmm0 and xmm1, negate the           
|                                              |      |                |                   | multiplication result and add to xmm2/mem      
|                                              |      |                |                   | and put result in xmm0.                        
| VEX.DDS.LIG.128.66.0F38.W1 BD /r VFNMADD231SD| A    | V/V            | FMA               | Multiply scalar double-precision floating-point
| xmm0, xmm1, xmm2/m64                         |      |                |                   | value from xmm1 and xmm2/mem, negate           
|                                              |      |                |                   | the multiplication result and add to           
|                                              |      |                |                   | xmm0 and put result in xmm0.                   

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2   | Operand 3    | Operand 4
| A    | ModRM:reg (r, w)| VEX.vvvv (r)| ModRM:r/m (r)| NA       

Description:
VFNMADD132SD: Multiplies the low packed double-precision floating-point value
from the first source operand to the low packed double-precision floating-point
value in the third source operand, adds the negated infinite precision intermediate
result to the low packed double-precision floating-point values in the second
source operand, performs rounding and stores the resulting packed double-precision
floating-point value to the destination operand (first source operand). VFNMADD213SD:
Multiplies the low packed double-precision floating-point value from the second
source operand to the low packed double-precision floating-point value in the
first source operand, adds the negated infinite precision intermediate result
to the low packed double-precision floating-point value in the third source
operand, performs rounding and stores the resulting packed double-precision
floating-point value to the destination operand (first source operand). VFNMADD231SD:
Multiplies the low packed double-precision floating-point value from the second
source to the low packed double-precision floating-point value in the third
source operand, adds the negated infinite precision intermediate result to the
low packed double-precision floating-point value in the first source operand,
performs rounding and stores the resulting packed double-precision floating-point
value to the destination operand (first source operand). VEX.128 encoded version:
The destination operand (also first source operand) is a XMM register and encoded
in reg_field. The second source operand is a XMM register and encoded in VEX.vvvv.
The third source operand is a XMM register or a 64-bit memory location and encoded
in rm_field. The upper bits ([VLMAX-1:128]) of the YMM destination register
are zeroed. Compiler tools may optionally support a complementary mnemonic for
each instruction mnemonic listed in the opcode/instruction column of the summary
table. The behavior of the complementary mnemonic in situations involving NANs
are governed by the definition of the instruction mnemonic defined in the opcode/instruction
column. See also Section 14.5.1, “FMA Instruction Operand Order and Arithmetic
Behavior” in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 1.

Operation:

In the operations below, "+", "-", and "*" symbols represent addition, subtraction, and multiplication operations
with infinite precision inputs and outputs (no rounding).
VFNMADD132SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (DEST[63:0]*SRC3[63:0]) + SRC2[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFNMADD213SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (SRC2[63:0]*DEST[63:0]) + SRC3[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0
VFNMADD231SD DEST, SRC2, SRC3
DEST[63:0] <- RoundFPControl_MXCSR(- (SRC2[63:0]*SRC3[63:0]) + DEST[63:0])
DEST[127:64] <- DEST[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
VFNMADD132SD: __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);

VFNMADD213SD: __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);

VFNMADD231SD: __m128d _mm_fnmadd_sd (__m128d a, __m128d b, __m128d c);


SIMD Floating-Point Exceptions:
Overflow, Underflow, Invalid, Precision, Denormal


Other Exceptions:
See Exceptions Type 3


