# instructions

platform: x86_64
mnem: KTESTW
description:
KTESTW/KTESTB/KTESTQ/KTESTD-Packed Bit Test Masks and Set Flags
 Opcode/                   Op      64/32       CPUID          Description
 Instruction               En      bit Mode    Feature
                                   Support     Flag
 VEX.L0.0F.W0 99 /r        RR      V/V         AVX512DQ       Set ZF and CF depending on sign bit AND and ANDN of 16 bits mask
 KTESTW k1, k2                                                register sources.
 VEX.L0.66.0F.W0 99 /r     RR      V/V         AVX512DQ       Set ZF and CF depending on sign bit AND and ANDN of 8 bits mask
 KTESTB k1, k2                                                register sources.
 VEX.L0.0F.W1 99 /r        RR      V/V         AVX512BW       Set ZF and CF depending on sign bit AND and ANDN of 64 bits mask
 KTESTQ k1, k2                                                register sources.
 VEX.L0.66.0F.W1 99 /r     RR      V/V         AVX512BW       Set ZF and CF depending on sign bit AND and ANDN of 32 bits mask
 KTESTD k1, k2                                                register sources.



                                                Instruction Operand Encoding
       Op/En                Operand 1                                             Operand2
        RR                ModRM:reg (r)                            ModRM:r/m (r, ModRM:[7:6] must be 11b)

Description
Performs a bitwise comparison of the bits of the first source operand and corresponding bits in the second source
operand. If the AND operation produces all zeros, the ZF is set else the ZF is clear. If the bitwise AND operation of
the inverted first source operand with the second source operand produces all zeros the CF is set else the CF is
clear. Only the EFLAGS register is updated.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
KTESTW
TEMP[15:0] <- SRC2[15:0] AND SRC1[15:0]
IF (TEMP[15:0] = = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;
FI;
TEMP[15:0] <- SRC2[15:0] AND NOT SRC1[15:0]
IF (TEMP[15:0] = = 0)
    THEN CF <-1;
    ELSE CF <- 0;
FI;
AF <- OF <- PF <- SF <- 0;

KTESTB
TEMP[7:0] <- SRC2[7:0] AND SRC1[7:0]
IF (TEMP[7:0] = = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;
FI;
TEMP[7:0] <- SRC2[7:0] AND NOT SRC1[7:0]
IF (TEMP[7:0] = = 0)
    THEN CF <-1;
    ELSE CF <- 0;
FI;
AF <- OF <- PF <- SF <- 0;





KTESTQ
TEMP[63:0] <- SRC2[63:0] AND SRC1[63:0]
IF (TEMP[63:0] = = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;
FI;
TEMP[63:0] <- SRC2[63:0] AND NOT SRC1[63:0]
IF (TEMP[63:0] = = 0)
    THEN CF <-1;
    ELSE CF <- 0;
FI;
AF <- OF <- PF <- SF <- 0;

KTESTD
TEMP[31:0] <- SRC2[31:0] AND SRC1[31:0]
IF (TEMP[31:0] = = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;
FI;
TEMP[31:0] <- SRC2[31:0] AND NOT SRC1[31:0]
IF (TEMP[31:0] = = 0)
    THEN CF <-1;
    ELSE CF <- 0;
FI;
AF <- OF <- PF <- SF <- 0;

Intel C/C++ Compiler Intrinsic Equivalent



SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type K20.






platform: x86_64
mnem: KUNPCKBW
description:
KUNPCKBW/KUNPCKWD/KUNPCKDQ-Unpack for Mask Registers
 Opcode/                        Op/En     64/32      CPUID         Description
 Instruction                              bit Mode   Feature
                                          Support    Flag
 VEX.NDS.L1.66.0F.W0 4B /r      RVR       V/V        AVX512F       Unpack and interleave 8 bits masks in k2 and k3 and write
 KUNPCKBW k1, k2, k3                                               word result in k1.
 VEX.NDS.L1.0F.W0 4B /r         RVR       V/V        AVX512BW      Unpack and interleave 16 bits in k2 and k3 and write double-
 KUNPCKWD k1, k2, k3                                               word result in k1.
 VEX.NDS.L1.0F.W1 4B /r         RVR       V/V        AVX512BW      Unpack and interleave 32 bits masks in k2 and k3 and write
 KUNPCKDQ k1, k2, k3                                               quadword result in k1.



                                                Instruction Operand Encoding
    Op/En                  Operand 1                           Operand 2                              Operand 3
    RVR                   ModRM:reg (w)                     VEX.1vvv (r)               ModRM:r/m (r, ModRM:[7:6] must be 11b)

Description
Unpacks the lower 8/16/32 bits of the second and third operands (source operands) into the low part of the first
operand (destination operand), starting from the low bytes. The result is zero-extended in the destination.

Operation
KUNPCKBW
DEST[7:0] <- SRC2[7:0]
DEST[15:8] <- SRC1[7:0]
DEST[MAX_KL-1:16] <- 0

KUNPCKWD
DEST[15:0] <- SRC2[15:0]
DEST[31:16] <- SRC1[15:0]
DEST[MAX_KL-1:32] <- 0

KUNPCKDQ
DEST[31:0] <- SRC2[31:0]
DEST[63:32] <- SRC1[31:0]
DEST[MAX_KL-1:64] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
KUNPCKBW __mmask16 _mm512_kunpackb(__mmask16 a, __mmask16 b);
KUNPCKDQ __mmask64 _mm512_kunpackd(__mmask64 a, __mmask64 b);
KUNPCKWD __mmask32 _mm512_kunpackw(__mmask32 a, __mmask32 b);

Flags Affected
None

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type K20.






platform: x86_64
mnem: KXNORW
description:
KXNORW/KXNORB/KXNORQ/KXNORD-Bitwise Logical XNOR Masks
 Opcode/                      Op/En   64/32         CPUID         Description
 Instruction                          bit Mode      Feature
                                      Support       Flag
 VEX.NDS.L1.0F.W0 46 /r       RVR     V/V           AVX512F       Bitwise XNOR 16 bits masks k2 and k3 and place result in k1.
 KXNORW k1, k2, k3
 VEX.L1.66.0F.W0 46 /r        RVR     V/V           AVX512DQ      Bitwise XNOR 8 bits masks k2 and k3 and place result in k1.
 KXNORB k1, k2, k3
 VEX.L1.0F.W1 46 /r           RVR     V/V           AVX512BW      Bitwise XNOR 64 bits masks k2 and k3 and place result in k1.
 KXNORQ k1, k2, k3
 VEX.L1.66.0F.W1 46 /r        RVR     V/V           AVX512BW      Bitwise XNOR 32 bits masks k2 and k3 and place result in k1.
 KXNORD k1, k2, k3



                                             Instruction Operand Encoding
   Op/En                  Operand 1                           Operand 2                              Operand 3
    RVR               ModRM:reg (w)                       VEX.1vvv (r)                ModRM:r/m (r, ModRM:[7:6] must be 11b)

Description
Performs a bitwise XNOR between the vector mask k2 and the vector mask k3, and writes the result into vector
mask k1 (three-operand form).

Operation
KXNORW
DEST[15:0] <- NOT (SRC1[15:0] BITWISE XOR SRC2[15:0])
DEST[MAX_KL-1:16] <- 0

KXNORB
DEST[7:0] <- NOT (SRC1[7:0] BITWISE XOR SRC2[7:0])
DEST[MAX_KL-1:8] <- 0

KXNORQ
DEST[63:0] <- NOT (SRC1[63:0] BITWISE XOR SRC2[63:0])
DEST[MAX_KL-1:64] <- 0

KXNORD
DEST[31:0] <- NOT (SRC1[31:0] BITWISE XOR SRC2[31:0])
DEST[MAX_KL-1:32] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
KXNORW __mmask16 _mm512_kxnor(__mmask16 a, __mmask16 b);

Flags Affected
None

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type K20.






platform: x86_64
mnem: KXORW
description:
KXORW/KXORB/KXORQ/KXORD-Bitwise Logical XOR Masks
 Opcode/                        Op/En     64/32      CPUID          Description
 Instruction                              bit Mode   Feature
                                          Support    Flag
 VEX.NDS.L1.0F.W0 47 /r         RVR       V/V        AVX512F        Bitwise XOR 16 bits masks k2 and k3 and place result in k1.
 KXORW k1, k2, k3
 VEX.L1.66.0F.W0 47 /r          RVR       V/V        AVX512DQ       Bitwise XOR 8 bits masks k2 and k3 and place result in k1.
 KXORB k1, k2, k3
 VEX.L1.0F.W1 47 /r             RVR       V/V        AVX512BW       Bitwise XOR 64 bits masks k2 and k3 and place result in k1.
 KXORQ k1, k2, k3
 VEX.L1.66.0F.W1 47 /r          RVR       V/V        AVX512BW       Bitwise XOR 32 bits masks k2 and k3 and place result in k1.
 KXORD k1, k2, k3



                                                Instruction Operand Encoding
    Op/En                  Operand 1                        Operand 2                                Operand 3
     RVR                  ModRM:reg (w)                     VEX.1vvv (r)              ModRM:r/m (r, ModRM:[7:6] must be 11b)

Description
Performs a bitwise XOR between the vector mask k2 and the vector mask k3, and writes the result into vector mask
k1 (three-operand form).

Operation
KXORW
DEST[15:0] <- SRC1[15:0] BITWISE XOR SRC2[15:0]
DEST[MAX_KL-1:16] <- 0

KXORB
DEST[7:0] <- SRC1[7:0] BITWISE XOR SRC2[7:0]
DEST[MAX_KL-1:8] <- 0

KXORQ
DEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[MAX_KL-1:64] <- 0

KXORD
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[MAX_KL-1:32] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
KXORW __mmask16 _mm512_kxor(__mmask16 a, __mmask16 b);

Flags Affected
None

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type K20.






platform: x86_64
mnem: LAHF
description:
LAHF-Load Status Flags into AH Register
 Opcode                    Instruction                      Op/   64-Bit     Compat/ Description
                                                            En    Mode       Leg Mode
 9F                        LAHF                             NP    Invalid*   Valid    Load: AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF).
 NOTES:
 *Valid in specific steppings. See Description section.



                                                    Instruction Operand Encoding
   Op/En               Operand 1                          Operand 2                  Operand 3                    Operand 4
      NP                   NA                                NA                         NA                            NA

Description
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

Operation
IF 64-Bit Mode
    THEN
         IF CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1;
              THEN AH <- RFLAGS(SF:ZF:0:AF:0:PF:1:CF);
              ELSE #UD;
         FI;
    ELSE
         AH <- EFLAGS(SF:ZF:0:AF:0:PF:1:CF);
FI;

Flags Affected
None. The state of the flags in the EFLAGS register is not affected.

Protected Mode Exceptions
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#UD                      If CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 0.
                         If the LOCK prefix is used.






platform: x86_64
mnem: LAR
description:
LAR-Load Access Rights Byte
Opcode                     Instruction                    Op/    64-Bit       Compat/ Description
                                                          En     Mode         Leg Mode
0F 02 /r                   LAR r16, r16/m16               RM     Valid        Valid        r16 <- access rights referenced by r16/m16
0F 02 /r                   LAR reg, r32/m161              RM     Valid        Valid        reg <- access rights referenced by r32/m16
NOTES:
1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored.



                                                   Instruction Operand Encoding
    Op/En                 Operand 1                      Operand 2                      Operand 3                   Operand 4
      RM               ModRM:reg (w)                   ModRM:r/m (r)                        NA                         NA

Description
Loads the access rights from the segment descriptor specified by the second operand (source operand) into the
first operand (destination operand) and sets the ZF flag in the flag register. The source operand (which can be a
register or a memory location) contains the segment selector for the segment descriptor being accessed. If the
source operand is a memory address, only 16 bits of data are accessed. The destination operand is a general-
purpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, soft-
ware can perform additional checks on the access rights information.
The access rights for a segment descriptor include fields located in the second doubleword (bytes 4-7) of the
segment descriptor. The following fields are loaded by the LAR instruction:
.   Bits 7:0 are returned as 0
.   Bits 11:8 return the segment type.
.   Bit 12 returns the S flag.
.   Bits 14:13 return the DPL.
.   Bit 15 returns the P flag.
.   The following fields are returned only if the operand size is greater than 16 bits:
    - Bits 19:16 are undefined.
    - Bit 20 returns the software-available bit in the descriptor.
    - Bit 21 returns the L flag.
    - Bit 22 returns the D/B flag.
    - Bit 23 returns the G flag.
    - Bits 31:24 are returned as 0.
This instruction performs the following checks before it loads the access rights in the destination register:
.   Checks that the segment selector is not NULL.
.   Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being
    accessed
.   Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for
    (can be accessed with) the LAR instruction. The valid system segment and gate descriptor types are given in
    Table 3-52.
.   If the segment is not a conforming code segment, it checks that the specified segment descriptor is visible at
    the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of the segment
    selector).
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no
access rights are loaded in the destination operand.



The LAR instruction can only be executed in protected mode and IA-32e mode.
                                             Table 3-52. Segment and Gate Types
      Type                            Protected Mode                                               IA-32e Mode
                                  Name                        Valid                       Name                         Valid
        0          Reserved                                    No          Reserved                                     No
        1          Available 16-bit TSS                        Yes         Reserved                                     No
        2          LDT                                         Yes         LDT                                          No
        3          Busy 16-bit TSS                             Yes         Reserved                                     No
        4          16-bit call gate                            Yes         Reserved                                     No
        5          16-bit/32-bit task gate                     Yes         Reserved                                     No
        6          16-bit interrupt gate                       No          Reserved                                     No
        7          16-bit trap gate                            No          Reserved                                     No
        8          Reserved                                    No          Reserved                                     No
        9          Available 32-bit TSS                        Yes         Available 64-bit TSS                         Yes
        A          Reserved                                    No          Reserved                                     No
        B          Busy 32-bit TSS                             Yes         Busy 64-bit TSS                              Yes
        C          32-bit call gate                            Yes         64-bit call gate                             Yes
        D          Reserved                                    No          Reserved                                     No
        E          32-bit interrupt gate                       No          64-bit interrupt gate                        No
        F          32-bit trap gate                            No          64-bit trap gate                             No

Operation
IF Offset(SRC) > descriptor table limit
    THEN
        ZF <- 0;
    ELSE
        SegmentDescriptor <- descriptor referenced by SRC;
        IF SegmentDescriptor(Type) != conforming code segment
        and (CPL > DPL) or (RPL > DPL)
        or SegmentDescriptor(Type) is not valid for instruction
             THEN
                  ZF <- 0;
             ELSE
                  DEST <- access rights from SegmentDescriptor as given in Description section;
                  ZF <- 1;
        FI;
FI;

Flags Affected
The ZF flag is set to 1 if the access rights are loaded successfully; otherwise, it is cleared to 0.





Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                        selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and the memory operand effective address is unaligned while
                        the current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                     The LAR instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                     The LAR instruction cannot be executed in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                  If the memory operand effective address referencing the SS segment is in a non-canonical
                        form.
#GP(0)                  If the memory operand effective address is in a non-canonical form.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and the memory operand effective address is unaligned while
                        the current privilege level is 3.
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: LDDQU
description:
LDDQU-Load Unaligned Integer 128 Bits
    Opcode/                                        Op/   64/32-bit CPUID       Description
    Instruction                                    En    Mode      Feature
                                                                   Flag
    F2 0F F0 /r                                    RM    V/V        SSE3       Load unaligned data from mem and return
    LDDQU xmm1, mem                                                            double quadword in xmm1.

    VEX.128.F2.0F.WIG F0 /r                        RM    V/V        AVX        Load unaligned packed integer values from
    VLDDQU xmm1, m128                                                          mem to xmm1.

    VEX.256.F2.0F.WIG F0 /r                        RM    V/V        AVX        Load unaligned packed integer values from
    VLDDQU ymm1, m256                                                          mem to ymm1.



                                              Instruction Operand Encoding
      Op/En             Operand 1                 Operand 2                  Operand 3                   Operand 4
       RM             ModRM:reg (w)             ModRM:r/m (r)                   NA                           NA

Description
The instruction is functionally similar to (V)MOVDQU ymm/xmm, m256/m128 for loading from memory. That is:
32/16 bytes of data starting at an address specified by the source memory operand (second operand) are fetched
from memory and placed in a destination register (first operand). The source operand need not be aligned on a
32/16-byte boundary. Up to 64/32 bytes may be loaded from memory; this is implementation dependent.
This instruction may improve performance relative to (V)MOVDQU if the source operand crosses a cache line
boundary. In situations that require the data loaded by (V)LDDQU be modified and stored to the same location, use
(V)MOVDQU or (V)MOVDQA instead of (V)LDDQU. To move a double quadword to or from memory locations that
are known to be aligned on 16-byte boundaries, use the (V)MOVDQA instruction.

Implementation Notes
.      If the source is aligned to a 32/16-byte boundary, based on the implementation, the 32/16 bytes may be
       loaded more than once. For that reason, the usage of (V)LDDQU should be avoided when using uncached or
       write-combining (WC) memory regions. For uncached or WC memory regions, keep using (V)MOVDQU.
.      This instruction is a replacement for (V)MOVDQU (load) in situations where cache line splits significantly affect
       performance. It should not be used in situations where store-load forwarding is performance critical. If
       performance of store-load forwarding is critical to the application, use (V)MOVDQA store-load pairs when data
       is 256/128-bit aligned or (V)MOVDQU store-load pairs when data is 256/128-bit unaligned.
.      If the memory address is not aligned on 32/16-byte boundary, some implementations may load up to 64/32
       bytes and return 32/16 bytes in the destination. Some processor implementations may issue multiple loads to
       access the appropriate 32/16 bytes. Developers of multi-threaded or multi-processor software should be aware
       that on these processors the loads will be performed in a non-atomic way.
.      If alignment checking is enabled (CR0.AM = 1, RFLAGS.AC = 1, and CPL = 3), an alignment-check exception
       (#AC) may or may not be generated (depending on processor implementation) when the memory address is
       not aligned on an 8-byte boundary.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.

Operation
LDDQU (128-bit Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] (Unmodified)





VLDDQU (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[VLMAX-1:128] <- 0

VLDDQU (VEX.256 encoded version)
DEST[255:0] <- SRC[255:0]

Intel C/C++ Compiler Intrinsic Equivalent
LDDQU:    __m128i _mm_lddqu_si128 (__m128i * p);

VLDDQU: __m256i _mm256_lddqu_si256 (__m256i * p);

Numeric Exceptions
None

Other Exceptions
See Exceptions Type 4;
Note treatment of #AC varies.






platform: x86_64
mnem: LDMXCSR
description:
LDMXCSR-Load MXCSR Register
 Opcode/                                            Op/     64/32-bit CPUID     Description
 Instruction                                        En      Mode      Feature
                                                                      Flag
 0F AE /2                                           M       V/V       SSE       Load MXCSR register from m32.
 LDMXCSR m32
 VEX.LZ.0F.WIG AE /2                                M       V/V       AVX       Load MXCSR register from m32.
 VLDMXCSR m32



                                               Instruction Operand Encoding
    Op/En              Operand 1                Operand 2                   Operand 3                  Operand 4
      M            ModRM:r/m (r)                   NA                           NA                        NA

Description
Loads the source operand into the MXCSR control/status register. The source operand is a 32-bit memory location.
See "MXCSR Control and Status Register" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Devel-
oper's Manual, Volume 1, for a description of the MXCSR register and its contents.
The LDMXCSR instruction is typically used in conjunction with the (V)STMXCSR instruction, which stores the
contents of the MXCSR register in memory.
The default MXCSR value at reset is 1F80H.
If a (V)LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets the corresponding exception
flag bit, a SIMD floating-point exception will not be immediately generated. The exception will be generated only
upon the execution of the next instruction that meets both conditions below:
.   the instruction must operate on an XMM or YMM register operand,
.   the instruction causes that particular SIMD floating-point exception to be reported.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
If VLDMXCSR is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
MXCSR <- m32;

C/C++ Compiler Intrinsic Equivalent
_mm_setcsr(unsigned int i)

Numeric Exceptions
None

Other Exceptions
See Exceptions Type 5; additionally
#GP                     For an attempt to set reserved bits in MXCSR.
#UD                     If VEX.vvvv != 1111B.






platform: x86_64
mnem: LDS
description:
LDS/LES/LFS/LGS/LSS-Load Far Pointer
 Opcode                   Instruction                 Op/    64-Bit    Compat/ Description
                                                      En     Mode      Leg Mode
 C5 /r                    LDS r16,m16:16              RM     Invalid   Valid      Load DS:r16 with far pointer from memory.
 C5 /r                    LDS r32,m16:32              RM     Invalid   Valid      Load DS:r32 with far pointer from memory.
 0F B2 /r                 LSS r16,m16:16              RM     Valid     Valid      Load SS:r16 with far pointer from memory.
 0F B2 /r                 LSS r32,m16:32              RM     Valid     Valid      Load SS:r32 with far pointer from memory.
 REX + 0F B2 /r           LSS r64,m16:64              RM     Valid     N.E.       Load SS:r64 with far pointer from memory.
 C4 /r                    LES r16,m16:16              RM     Invalid   Valid      Load ES:r16 with far pointer from memory.
 C4 /r                    LES r32,m16:32              RM     Invalid   Valid      Load ES:r32 with far pointer from memory.
 0F B4 /r                 LFS r16,m16:16              RM     Valid     Valid      Load FS:r16 with far pointer from memory.
 0F B4 /r                 LFS r32,m16:32              RM     Valid     Valid      Load FS:r32 with far pointer from memory.
 REX + 0F B4 /r           LFS r64,m16:64              RM     Valid     N.E.       Load FS:r64 with far pointer from memory.
 0F B5 /r                 LGS r16,m16:16              RM     Valid     Valid      Load GS:r16 with far pointer from memory.
 0F B5 /r                 LGS r32,m16:32              RM     Valid     Valid      Load GS:r32 with far pointer from memory.
 REX + 0F B5 /r           LGS r64,m16:64              RM     Valid     N.E.       Load GS:r64 with far pointer from memory.



                                                 Instruction Operand Encoding
   Op/En              Operand 1                     Operand 2                  Operand 3                   Operand 4
     RM             ModRM:reg (w)                 ModRM:r/m (r)                   NA                          NA

Description
Loads a far pointer (segment selector and offset) from the second operand (source operand) into a segment
register and the first operand (destination operand). The source operand specifies a 48-bit or a 32-bit pointer in
memory depending on the current setting of the operand-size attribute (32 bits or 16 bits, respectively). The
instruction opcode and the destination operand specify a segment register/general-purpose register pair. The 16-
bit segment selector from the source operand is loaded into the segment register specified with the opcode (DS,
SS, ES, FS, or GS). The 32-bit or 16-bit offset is loaded into the register specified with the destination operand.
If one of these instructions is executed in protected mode, additional information from the segment descriptor
pointed to by the segment selector in the source operand is loaded in the hidden part of the selected segment
register.
Also in protected mode, a NULL selector (values 0000 through 0003) can be loaded into DS, ES, FS, or GS registers
without causing a protection exception. (Any subsequent reference to a segment whose corresponding segment
register is loaded with a NULL selector, causes a general-protection exception (#GP) and no memory reference to
the segment occurs.)
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.W promotes
operation to specify a source operand referencing an 80-bit pointer (16-bit selector, 64-bit offset) in memory.
Using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). See the summary chart at
the beginning of this section for encoding data and limits.

Operation
64-BIT_MODE
   IF SS is loaded
        THEN
              IF SegmentSelector = NULL and ( (RPL = 3) or
                       (RPL != 3 and RPL != CPL) )
                   THEN #GP(0);
              ELSE IF descriptor is in non-canonical space



                  THEN #GP(0); FI;
            ELSE IF Segment selector index is not within descriptor table limits
                       or segment selector RPL != CPL
                       or access rights indicate nonwritable data segment
                       or DPL != CPL
                  THEN #GP(selector); FI;
            ELSE IF Segment marked not present
                  THEN #SS(selector); FI;
            FI;
            SS <- SegmentSelector(SRC);
            SS <- SegmentDescriptor([SRC]);
   ELSE IF attempt to load DS, or ES
       THEN #UD;
   ELSE IF FS, or GS is loaded with non-NULL segment selector
       THEN IF Segment selector index is not within descriptor table limits
            or access rights indicate segment neither data nor readable code segment
            or segment is data or nonconforming-code segment
            and ( RPL > DPL or CPL > DPL)
                  THEN #GP(selector); FI;
            ELSE IF Segment marked not present
                  THEN #NP(selector); FI;
            FI;
            SegmentRegister <- SegmentSelector(SRC) ;
            SegmentRegister <- SegmentDescriptor([SRC]);
       FI;
   ELSE IF FS, or GS is loaded with a NULL selector:
       THEN
            SegmentRegister <- NULLSelector;
            SegmentRegister(DescriptorValidBit) <- 0; FI; (* Hidden flag;
                  not accessible by software *)
   FI;
   DEST <- Offset(SRC);

PREOTECTED MODE OR COMPATIBILITY MODE;
   IF SS is loaded
        THEN
              IF SegementSelector = NULL
                   THEN #GP(0);
              ELSE IF Segment selector index is not within descriptor table limits
                       or segment selector RPL != CPL
                       or access rights indicate nonwritable data segment
                       or DPL != CPL
                   THEN #GP(selector); FI;
              ELSE IF Segment marked not present
                   THEN #SS(selector); FI;
              FI;
              SS <- SegmentSelector(SRC);
              SS <- SegmentDescriptor([SRC]);
   ELSE IF DS, ES, FS, or GS is loaded with non-NULL segment selector
        THEN IF Segment selector index is not within descriptor table limits
              or access rights indicate segment neither data nor readable code segment
              or segment is data or nonconforming-code segment
              and (RPL > DPL or CPL > DPL)
                   THEN #GP(selector); FI;




             ELSE IF Segment marked not present
                 THEN #NP(selector); FI;
             FI;
             SegmentRegister <- SegmentSelector(SRC) AND RPL;
             SegmentRegister <- SegmentDescriptor([SRC]);
       FI;
   ELSE IF DS, ES, FS, or GS is loaded with a NULL selector:
       THEN
            SegmentRegister <- NULLSelector;
            SegmentRegister(DescriptorValidBit) <- 0; FI; (* Hidden flag;
                 not accessible by software *)
   FI;
   DEST <- Offset(SRC);

Real-Address or Virtual-8086 Mode
   SegmentRegister <- SegmentSelector(SRC); FI;
   DEST <- Offset(SRC);

Flags Affected
None

Protected Mode Exceptions
#UD                     If source operand is not a memory location.
                        If the LOCK prefix is used.
#GP(0)                  If a NULL selector is loaded into the SS register.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                        selector.
#GP(selector)           If the SS register is being loaded and any of the following is true: the segment selector index
                        is not within the descriptor table limits, the segment selector RPL is not equal to CPL, the
                        segment is a non-writable data segment, or DPL is not equal to CPL.
                        If the DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and any of
                        the following is true: the segment selector index is not within descriptor table limits, the
                        segment is neither a data nor a readable code segment, or the segment is a data or noncon-
                        forming-code segment and both RPL and CPL are greater than DPL.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#SS(selector)           If the SS register is being loaded and the segment is marked not present.
#NP(selector)           If DS, ES, FS, or GS register is being loaded with a non-NULL segment selector and the
                        segment is marked not present.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If source operand is not a memory location.
                        If the LOCK prefix is used.





Virtual-8086 Mode Exceptions
#UD                 If source operand is not a memory location.
                    If the LOCK prefix is used.
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
                    If a NULL selector is attempted to be loaded into the SS register in compatibility mode.
                    If a NULL selector is attempted to be loaded into the SS register in CPL3 and 64-bit mode.
                    If a NULL selector is attempted to be loaded into the SS register in non-CPL3 and 64-bit mode
                    where its RPL is not equal to CPL.
#GP(Selector)       If the FS, or GS register is being loaded with a non-NULL segment selector and any of the
                    following is true: the segment selector index is not within descriptor table limits, the memory
                    address of the descriptor is non-canonical, the segment is neither a data nor a readable code
                    segment, or the segment is a data or nonconforming-code segment and both RPL and CPL are
                    greater than DPL.
                    If the SS register is being loaded and any of the following is true: the segment selector index
                    is not within the descriptor table limits, the memory address of the descriptor is non-canonical,
                    the segment selector RPL is not equal to CPL, the segment is a nonwritable data segment, or
                    DPL is not equal to CPL.
#SS(0)              If a memory operand effective address is non-canonical
#SS(Selector)       If the SS register is being loaded and the segment is marked not present.
#NP(selector)       If FS, or GS register is being loaded with a non-NULL segment selector and the segment is
                    marked not present.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If source operand is not a memory location.
                    If the LOCK prefix is used.






platform: x86_64
mnem: LEA
description:
LEA-Load Effective Address
Opcode                       Instruction                     Op/   64-Bit        Compat/ Description
                                                             En    Mode          Leg Mode
8D /r                        LEA r16,m                       RM    Valid         Valid       Store effective address for m in register r16.
8D /r                        LEA r32,m                       RM    Valid         Valid       Store effective address for m in register r32.
REX.W + 8D /r                LEA r64,m                       RM    Valid         N.E.        Store effective address for m in register r64.



                                                      Instruction Operand Encoding
    Op/En              Operand 1                         Operand 2                       Operand 3                       Operand 4
     RM             ModRM:reg (w)                      ModRM:r/m (r)                         NA                             NA

Description
Computes the effective address of the second operand (the source operand) and stores it in the first operand
(destination operand). The source operand is a memory address (offset part) specified with one of the processors
addressing modes; the destination operand is a general-purpose register. The address-size and operand-size attri-
butes affect the action performed by this instruction, as shown in the following table. The operand-size attribute of
the instruction is determined by the chosen register; the address-size attribute is determined by the attribute of
the code segment.
                 Table 3-53. Non-64-bit Mode LEA Operation with Address and Operand Size Attributes
  Operand Size       Address Size                                                 Action Performed
        16                   16            16-bit effective address is calculated and stored in requested 16-bit register destination.
        16                   32            32-bit effective address is calculated. The lower 16 bits of the address are stored in the
                                           requested 16-bit register destination.
        32                   16            16-bit effective address is calculated. The 16-bit address is zero-extended and stored in the
                                           requested 32-bit register destination.
        32                   32            32-bit effective address is calculated and stored in the requested 32-bit register destination.

Different assemblers may use different algorithms based on the size attribute and symbolic reference of the source
operand.
In 64-bit mode, the instruction's destination operand is governed by operand size attribute, the default operand
size is 32 bits. Address calculation is governed by address size attribute, the default address size is 64-bits. In 64-
bit mode, address size of 16 bits is not encodable. See Table 3-54.
                   Table 3-54. 64-bit Mode LEA Operation with Address and Operand Size Attributes
  Operand Size       Address Size                                                 Action Performed
        16                   32            32-bit effective address is calculated (using 67H prefix). The lower 16 bits of the address are
                                           stored in the requested 16-bit register destination (using 66H prefix).
        16                   64            64-bit effective address is calculated (default address size). The lower 16 bits of the address
                                           are stored in the requested 16-bit register destination (using 66H prefix).
        32                   32            32-bit effective address is calculated (using 67H prefix) and stored in the requested 32-bit
                                           register destination.
        32                   64            64-bit effective address is calculated (default address size) and the lower 32 bits of the
                                           address are stored in the requested 32-bit register destination.
        64                   32            32-bit effective address is calculated (using 67H prefix), zero-extended to 64-bits, and stored
                                           in the requested 64-bit register destination (using REX.W).
        64                   64            64-bit effective address is calculated (default address size) and all 64-bits of the address are
                                           stored in the requested 64-bit register destination (using REX.W).





Operation
IF OperandSize = 16 and AddressSize = 16
    THEN
        DEST <- EffectiveAddress(SRC); (* 16-bit address *)
    ELSE IF OperandSize = 16 and AddressSize = 32
        THEN
             temp <- EffectiveAddress(SRC); (* 32-bit address *)
             DEST <- temp[0:15]; (* 16-bit address *)
        FI;
    ELSE IF OperandSize = 32 and AddressSize = 16
        THEN
             temp <- EffectiveAddress(SRC); (* 16-bit address *)
             DEST <- ZeroExtend(temp); (* 32-bit address *)
        FI;
    ELSE IF OperandSize = 32 and AddressSize = 32
        THEN
             DEST <- EffectiveAddress(SRC); (* 32-bit address *)
        FI;
    ELSE IF OperandSize = 16 and AddressSize = 64
        THEN
             temp <- EffectiveAddress(SRC); (* 64-bit address *)
             DEST <- temp[0:15]; (* 16-bit address *)
        FI;
    ELSE IF OperandSize = 32 and AddressSize = 64
        THEN
             temp <- EffectiveAddress(SRC); (* 64-bit address *)
             DEST <- temp[0:31]; (* 16-bit address *)
        FI;
    ELSE IF OperandSize = 64 and AddressSize = 64
        THEN
             DEST <- EffectiveAddress(SRC); (* 64-bit address *)
        FI;
FI;

Flags Affected
None

Protected Mode Exceptions
#UD                    If source operand is not a memory location.
                       If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.




platform: x86_64
mnem: LEAVE
description:
LEAVE-High Level Procedure Exit
 Opcode                    Instruction          Op/     64-Bit   Compat/ Description
                                                En      Mode     Leg Mode
 C9                        LEAVE                NP      Valid    Valid       Set SP to BP, then pop BP.
 C9                        LEAVE                NP      N.E.     Valid       Set ESP to EBP, then pop EBP.
 C9                        LEAVE                NP      Valid    N.E.        Set RSP to RBP, then pop RBP.



                                           Instruction Operand Encoding
   Op/En              Operand 1             Operand 2                    Operand 3                    Operand 4
      NP                 NA                    NA                           NA                            NA

Description
Releases the stack frame set up by an earlier ENTER instruction. The LEAVE instruction copies the frame pointer (in
the EBP register) into the stack pointer register (ESP), which releases the stack space allocated to the stack frame.
The old frame pointer (the frame pointer for the calling procedure that was saved by the ENTER instruction) is then
popped from the stack into the EBP register, restoring the calling procedure's stack frame.
A RET instruction is commonly executed following a LEAVE instruction to return program control to the calling
procedure.
See "Procedure Calls for Block-Structured Languages" in Chapter 7 of the Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1, for detailed information on the use of the ENTER and LEAVE instructions.
In 64-bit mode, the instruction's default operation size is 64 bits; 32-bit operation cannot be encoded. See the
summary chart at the beginning of this section for encoding data and limits.

Operation
IF StackAddressSize = 32
    THEN
        ESP <- EBP;
    ELSE IF StackAddressSize = 64
        THEN RSP <- RBP; FI;
    ELSE IF StackAddressSize = 16
        THEN SP <- BP; FI;
FI;

IF OperandSize = 32
    THEN EBP <- Pop();
    ELSE IF OperandSize = 64
        THEN RBP <- Pop(); FI;
    ELSE IF OperandSize = 16
        THEN BP <- Pop(); FI;
FI;

Flags Affected
None





Protected Mode Exceptions
#SS(0)              If the EBP register points to a location that is not within the limits of the current stack
                    segment.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 If the EBP register points to a location outside of the effective address space from 0 to FFFFH.
#UD                 If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If the EBP register points to a location outside of the effective address space from 0 to FFFFH.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If the stack address is in a non-canonical form.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: LFENCE
description:
LFENCE-Load Fence
 Opcode                   Instruction                 Op/    64-Bit      Compat/ Description
                                                      En     Mode        Leg Mode
 0F AE E8                 LFENCE                      NP     Valid       Valid       Serializes load operations.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                       Operand 3                         Operand 4
    NP                   NA                           NA                            NA                                NA

Description
Performs a serializing operation on all load-from-memory instructions that were issued prior the LFENCE instruc-
tion. Specifically, LFENCE does not execute until all prior instructions have completed locally, and no later instruc-
tion begins execution until LFENCE completes. In particular, an instruction that loads from memory and that
precedes an LFENCE receives data from memory prior to completion of the LFENCE. (An LFENCE that follows an
instruction that stores to memory might complete before the data being stored have become globally visible.)
Instructions following an LFENCE may be fetched from memory before the LFENCE, but they will not execute until
the LFENCE completes.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue and speculative reads. The degree to which a consumer of data recognizes or knows that the
data is weakly ordered varies among applications and may be unknown to the producer of this data. The LFENCE
instruction provides a performance-efficient way of ensuring load ordering between routines that produce weakly-
ordered results and routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC,
and WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution.
Thus, it is not ordered with respect to executions of the LFENCE instruction; data can be brought into the caches
speculatively just before, during, or after the execution of an LFENCE instruction.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of E8. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, LFENCE is encoded by any opcode of the form 0F AE Ex, where x is
in the range 8-F.

Operation
Wait_On_Following_Instructions_Until(preceding_instructions_complete);

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_lfence(void)

Exceptions (All Modes of Operation)
#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.
                        If the LOCK prefix is used.






platform: x86_64
mnem: LGDT
description:
LGDT/LIDT-Load Global/Interrupt Descriptor Table Register
 Opcode                Instruction               Op/   64-Bit     Compat/ Description
                                                 En    Mode       Leg Mode
 0F 01 /2              LGDT m16&32               M     N.E.       Valid         Load m into GDTR.
 0F 01 /3              LIDT m16&32               M     N.E.       Valid         Load m into IDTR.
 0F 01 /2              LGDT m16&64               M     Valid      N.E.          Load m into GDTR.
 0F 01 /3              LIDT m16&64               M     Valid      N.E.          Load m into IDTR.



                                            Instruction Operand Encoding
   Op/En            Operand 1                  Operand 2                    Operand 3                       Operand 4
      M            ModRM:r/m (r)                  NA                            NA                              NA

Description
Loads the values in the source operand into the global descriptor table register (GDTR) or the interrupt descriptor
table register (IDTR). The source operand specifies a 6-byte memory location that contains the base address (a
linear address) and the limit (size of table in bytes) of the global descriptor table (GDT) or the interrupt descriptor
table (IDT). If operand-size attribute is 32 bits, a 16-bit limit (lower 2 bytes of the 6-byte data operand) and a 32-
bit base address (upper 4 bytes of the data operand) are loaded into the register. If the operand-size attribute
is 16 bits, a 16-bit limit (lower 2 bytes) and a 24-bit base address (third, fourth, and fifth byte) are loaded. Here,
the high-order byte of the operand is not used and the high-order byte of the base address in the GDTR or IDTR is
filled with zeros.
The LGDT and LIDT instructions are used only in operating-system software; they are not used in application
programs. They are the only instructions that directly load a linear address (that is, not a segment-relative
address) and a limit in protected mode. They are commonly executed in real-address mode to allow processor
initialization prior to switching to protected mode.
In 64-bit mode, the instruction's operand size is fixed at 8+2 bytes (an 8-byte base and a 2-byte limit). See the
summary chart at the beginning of this section for encoding data and limits.
See "SGDT-Store Global Descriptor Table Register" in Chapter 4, Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2B, for information on storing the contents of the GDTR and IDTR.





Operation
IF Instruction is LIDT
     THEN
         IF OperandSize = 16
               THEN
                    IDTR(Limit) <- SRC[0:15];
                    IDTR(Base) <- SRC[16:47] AND 00FFFFFFH;
               ELSE IF 32-bit Operand Size
                    THEN
                         IDTR(Limit) <- SRC[0:15];
                         IDTR(Base) <- SRC[16:47];
                    FI;
               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
                    THEN
                         IDTR(Limit) <- SRC[0:15];
                         IDTR(Base) <- SRC[16:79];
                    FI;
         FI;
     ELSE (* Instruction is LGDT *)
         IF OperandSize = 16
               THEN
                    GDTR(Limit) <- SRC[0:15];
                    GDTR(Base) <- SRC[16:47] AND 00FFFFFFH;
               ELSE IF 32-bit Operand Size
                    THEN
                         GDTR(Limit) <- SRC[0:15];
                         GDTR(Base) <- SRC[16:47];
                    FI;
               ELSE IF 64-bit Operand Size (* In 64-Bit Mode *)
                    THEN
                         GDTR(Limit) <- SRC[0:15];
                         GDTR(Base) <- SRC[16:79];
                    FI;
         FI;
FI;

Flags Affected
None

Protected Mode Exceptions
#UD                       If source operand is not a memory location.
                          If the LOCK prefix is used.
#GP(0)                    If the current privilege level is not 0.
                          If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                          selector.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.





Real-Address Mode Exceptions
#UD                 If source operand is not a memory location.
                    If the LOCK prefix is used.
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions
#UD                 If source operand is not a memory location.
                    If the LOCK prefix is used.
#GP(0)              The LGDT and LIDT instructions are not recognized in virtual-8086 mode.
#GP                 If the current privilege level is not 0.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the current privilege level is not 0.
                    If the memory address is in a non-canonical form.
#UD                 If source operand is not a memory location.
                    If the LOCK prefix is used.
#PF(fault-code)     If a page fault occurs.






platform: x86_64
mnem: LLDT
description:
LLDT-Load Local Descriptor Table Register
 Opcode                     Instruction          Op/    64-Bit    Compat/ Description
                                                 En     Mode      Leg Mode
 0F 00 /2                   LLDT r/m16           M      Valid     Valid      Load segment selector r/m16 into LDTR.



                                            Instruction Operand Encoding
   Op/En               Operand 1              Operand 2                   Operand 3                   Operand 4
     M               ModRM:r/m (r)               NA                          NA                          NA

Description
Loads the source operand into the segment selector field of the local descriptor table register (LDTR). The source
operand (a general-purpose register or a memory location) contains a segment selector that points to a local
descriptor table (LDT). After the segment selector is loaded in the LDTR, the processor uses the segment selector
to locate the segment descriptor for the LDT in the global descriptor table (GDT). It then loads the segment limit
and base address for the LDT from the segment descriptor into the LDTR. The segment registers DS, ES, SS, FS,
GS, and CS are not affected by this instruction, nor is the LDTR field in the task state segment (TSS) for the current
task.
If bits 2-15 of the source operand are 0, LDTR is marked invalid and the LLDT instruction completes silently.
However, all subsequent references to descriptors in the LDT (except by the LAR, VERR, VERW or LSL instructions)
cause a general protection exception (#GP).
The operand-size attribute has no effect on this instruction.
The LLDT instruction is provided for use in operating-system software; it should not be used in application
programs. This instruction can only be executed in protected mode or 64-bit mode.
In 64-bit mode, the operand size is fixed at 16 bits.

Operation
IF SRC(Offset) > descriptor table limit
    THEN #GP(segment selector); FI;

IF segment selector is valid

   Read segment descriptor;

   IF SegmentDescriptor(Type) != LDT
        THEN #GP(segment selector); FI;
   IF segment descriptor is not present
        THEN #NP(segment selector); FI;

    LDTR(SegmentSelector) <- SRC;
    LDTR(SegmentDescriptor) <- GDTSegmentDescriptor;
ELSE LDTR <- INVALID
FI;

Flags Affected
None





Protected Mode Exceptions
#GP(0)              If the current privilege level is not 0.
                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#GP(selector)       If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT
                    is not a Local Descriptor Table.
                    Segment selector is beyond GDT limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#NP(selector)       If the LDT descriptor is not present.
#PF(fault-code)     If a page fault occurs.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                 The LLDT instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                 The LLDT instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the current privilege level is not 0.
                    If the memory address is in a non-canonical form.
#GP(selector)       If the selector operand does not point into the Global Descriptor Table or if the entry in the GDT
                    is not a Local Descriptor Table.
                    Segment selector is beyond GDT limit.
#NP(selector)       If the LDT descriptor is not present.
#PF(fault-code)     If a page fault occurs.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: LMSW
description:
LMSW-Load Machine Status Word
 Opcode                   Instruction                 Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 0F 01 /6                 LMSW r/m16                  M     Valid    Valid      Loads r/m16 in machine status word of CR0.



                                                 Instruction Operand Encoding
   Op/En               Operand 1                   Operand 2                 Operand 3                   Operand 4
      M             ModRM:r/m (r)                      NA                       NA                          NA

Description
Loads the source operand into the machine status word, bits 0 through 15 of register CR0. The source operand can
be a 16-bit general-purpose register or a memory location. Only the low-order 4 bits of the source operand (which
contains the PE, MP, EM, and TS flags) are loaded into CR0. The PG, CD, NW, AM, WP, NE, and ET flags of CR0 are
not affected. The operand-size attribute has no effect on this instruction.
If the PE flag of the source operand (bit 0) is set to 1, the instruction causes the processor to switch to protected
mode. While in protected mode, the LMSW instruction cannot be used to clear the PE flag and force a switch back
to real-address mode.
The LMSW instruction is provided for use in operating-system software; it should not be used in application
programs. In protected or virtual-8086 mode, it can only be executed at CPL 0.
This instruction is provided for compatibility with the Intel 286 processor; programs and procedures intended to
run on IA-32 and Intel 64 processors beginning with Intel386 processors should use the MOV (control registers)
instruction to load the whole CR0 register. The MOV CR0 instruction can be used to set and clear the PE flag in CR0,
allowing a procedure or program to switch between protected and real-address modes.
This instruction is a serializing instruction.
This instruction's operation is the same in non-64-bit modes and 64-bit mode. Note that the operand size is fixed
at 16 bits.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
CR0[0:3] <- SRC[0:3];

Flags Affected
None

Protected Mode Exceptions
#GP(0)                  If the current privilege level is not 0.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                       selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#UD                     If the LOCK prefix is used.




Virtual-8086 Mode Exceptions
#GP(0)              The LMSW instruction is not recognized in real-address mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the current privilege level is not 0.
                    If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: LOCK
description:
LOCK-Assert LOCK# Signal Prefix
 Opcode                    Instruction                   Op/   64-Bit   Compat/ Description
                                                         En    Mode     Leg Mode
 F0                        LOCK                          NP    Valid    Valid       Asserts LOCK# signal for duration of the
                                                                                    accompanying instruction.
 NOTES:
 * See IA-32 Architecture Compatibility section below.



                                                 Instruction Operand Encoding
   Op/En               Operand 1                    Operand 2                   Operand 3                    Operand 4
      NP                   NA                            NA                        NA                            NA

Description
Causes the processor's LOCK# signal to be asserted during execution of the accompanying instruction (turns the
instruction into an atomic instruction). In a multiprocessor environment, the LOCK# signal ensures that the
processor has exclusive use of any shared memory while the signal is asserted.
In most IA-32 and all Intel 64 processors, locking may occur without the LOCK# signal being asserted. See the "IA-
32 Architecture Compatibility" section below for more details.
The LOCK prefix can be prepended only to the following instructions and only to those forms of the instructions
where the destination operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCH8B,
CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD, and XCHG. If the LOCK prefix is used with one of
these instructions and the source operand is a memory operand, an undefined opcode exception (#UD) may be
generated. An undefined opcode exception will also be generated if the LOCK prefix is used with any instruction not
in the above list. The XCHG instruction always asserts the LOCK# signal regardless of the presence or absence of
the LOCK prefix.
The LOCK prefix is typically used with the BTS instruction to perform a read-modify-write operation on a memory
location in shared memory environment.
The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed
for arbitrarily misaligned fields.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility
Beginning with the P6 family processors, when the LOCK prefix is prefixed to an instruction and the memory area
being accessed is cached internally in the processor, the LOCK# signal is generally not asserted. Instead, only the
processor's cache is locked. Here, the processor's cache coherency mechanism ensures that the operation is
carried out atomically with regards to memory. See "Effects of a Locked Operation on Internal Processor Caches"
in Chapter 8 of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, the for more informa-
tion on locking of caches.

Operation
AssertLOCK#(DurationOfAccompaningInstruction);

Flags Affected
None

Protected Mode Exceptions
#UD                     If the LOCK prefix is used with an instruction not listed: ADD, ADC, AND, BTC, BTR, BTS,
                        CMPXCHG, CMPXCH8B, CMPXCHG16B, DEC, INC, NEG, NOT, OR, SBB, SUB, XOR, XADD,
                        XCHG.
                        Other exceptions can be generated by the instruction when the LOCK prefix is applied.



Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: LODS
description:
LODS/LODSB/LODSW/LODSD/LODSQ-Load String
 Opcode                 Instruction               Op/     64-Bit   Compat/ Description
                                                  En      Mode     Leg Mode
 AC                     LODS m8                   NP      Valid    Valid       For legacy mode, Load byte at address DS:(E)SI
                                                                               into AL. For 64-bit mode load byte at address
                                                                               (R)SI into AL.
 AD                     LODS m16                  NP      Valid    Valid       For legacy mode, Load word at address
                                                                               DS:(E)SI into AX. For 64-bit mode load word at
                                                                               address (R)SI into AX.
 AD                     LODS m32                  NP      Valid    Valid       For legacy mode, Load dword at address
                                                                               DS:(E)SI into EAX. For 64-bit mode load dword
                                                                               at address (R)SI into EAX.
 REX.W + AD             LODS m64                  NP      Valid    N.E.        Load qword at address (R)SI into RAX.
 AC                     LODSB                     NP      Valid    Valid       For legacy mode, Load byte at address DS:(E)SI
                                                                               into AL. For 64-bit mode load byte at address
                                                                               (R)SI into AL.
 AD                     LODSW                     NP      Valid    Valid       For legacy mode, Load word at address
                                                                               DS:(E)SI into AX. For 64-bit mode load word at
                                                                               address (R)SI into AX.
 AD                     LODSD                     NP      Valid    Valid       For legacy mode, Load dword at address
                                                                               DS:(E)SI into EAX. For 64-bit mode load dword
                                                                               at address (R)SI into EAX.
 REX.W + AD             LODSQ                     NP      Valid    N.E.        Load qword at address (R)SI into RAX.



                                             Instruction Operand Encoding
   Op/En           Operand 1                  Operand 2                    Operand 3                     Operand 4
      NP               NA                        NA                           NA                             NA

Description
Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The
source operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers
(depending on the address-size attribute of the instruction, 32 or 16, respectively). The DS segment may be over-
ridden with a segment override prefix.
At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-
operands" form. The explicit-operands form (specified with the LODS mnemonic) allows the source operand to be
specified explicitly. Here, the source operand should be a symbol that indicates the size and location of the source
value. The destination operand is then automatically selected to match the size of the source operand (the AL
register for byte operands, AX for word operands, and EAX for doubleword operands). This explicit-operands form
is provided to allow documentation; however, note that the documentation provided by this form can be
misleading. That is, the source operand symbol must specify the correct type (size) of the operand (byte, word, or
doubleword), but it does not have to specify the correct location. The location is always specified by the DS:(E)SI
registers, which must be loaded correctly before the load string instruction is executed.
The no-operands form provides "short forms" of the byte, word, and doubleword versions of the LODS instructions.
Here also DS:(E)SI is assumed to be the source operand and the AL, AX, or EAX register is assumed to be the desti-
nation operand. The size of the source and destination operands is selected with the mnemonic: LODSB (byte
loaded into register AL), LODSW (word loaded into AX), or LODSD (doubleword loaded into EAX).
After the byte, word, or doubleword is transferred from the memory location into the AL, AX, or EAX register, the
(E)SI register is incremented or decremented automatically according to the setting of the DF flag in the EFLAGS
register. (If the DF flag is 0, the (E)SI register is incremented; if the DF flag is 1, the ESI register is decremented.)
The (E)SI register is incremented or decremented by 1 for byte operations, by 2 for word operations, or by 4 for
doubleword operations.



In 64-bit mode, use of the REX.W prefix promotes operation to 64 bits. LODS/LODSQ load the quadword at address
(R)SI into RAX. The (R)SI register is then incremented or decremented automatically according to the setting of
the DF flag in the EFLAGS register.
The LODS, LODSB, LODSW, and LODSD instructions can be preceded by the REP prefix for block loads of ECX bytes,
words, or doublewords. More often, however, these instructions are used within a LOOP construct because further
processing of the data moved into the register is usually necessary before the next transfer can be made. See
"REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation Prefix" in Chapter 4 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 2B, for a description of the REP prefix.

Operation
IF AL <- SRC; (* Byte load *)
    THEN AL <- SRC; (* Byte load *)
        IF DF = 0
             THEN (E)SI <- (E)SI + 1;
             ELSE (E)SI <- (E)SI - 1;
        FI;
ELSE IF AX <- SRC; (* Word load *)
    THEN IF DF = 0
             THEN (E)SI <- (E)SI + 2;
             ELSE (E)SI <- (E)SI - 2;
        IF;
    FI;
ELSE IF EAX <- SRC; (* Doubleword load *)
    THEN IF DF = 0
             THEN (E)SI <- (E)SI + 4;
             ELSE (E)SI <- (E)SI - 4;
        FI;
    FI;
ELSE IF RAX <- SRC; (* Quadword load *)
    THEN IF DF = 0
             THEN (R)SI <- (R)SI + 8;
             ELSE (R)SI <- (R)SI - 8;
        FI;
    FI;
FI;

Flags Affected
None

Protected Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                    If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                    If a memory operand effective address is outside the SS segment limit.
#UD                    If the LOCK prefix is used.



Virtual-8086 Mode Exceptions
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.
#UD                   If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                If the memory address is in a non-canonical form.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: LOOP
description:
LOOP/LOOPcc-Loop According to ECX Counter
Opcode                       Instruction               Op/    64-Bit   Compat/ Description
                                                       En     Mode     Leg Mode
E2 cb                        LOOP rel8                 D      Valid    Valid      Decrement count; jump short if count != 0.
E1 cb                        LOOPE rel8                D      Valid    Valid      Decrement count; jump short if count != 0 and
                                                                                  ZF = 1.
E0 cb                        LOOPNE rel8               D      Valid    Valid      Decrement count; jump short if count != 0 and
                                                                                  ZF = 0.



                                                 Instruction Operand Encoding
   Op/En             Operand 1                      Operand 2                  Operand 3                   Operand 4
     D                 Offset                           NA                        NA                           NA

Description
Performs a loop operation using the RCX, ECX or CX register as a counter (depending on whether address size is 64
bits, 32 bits, or 16 bits). Note that the LOOP instruction ignores REX.W; but 64-bit address size can be over-ridden
using a 67H prefix.
Each time the LOOP instruction is executed, the count register is decremented, then checked for 0. If the count is
0, the loop is terminated and program execution continues with the instruction following the LOOP instruction. If
the count is not zero, a near jump is performed to the destination (target) operand, which is presumably the
instruction at the beginning of the loop.
The target instruction is specified with a relative offset (a signed offset relative to the current value of the instruc-
tion pointer in the IP/EIP/RIP register). This offset is generally specified as a label in assembly code, but at the
machine code level, it is encoded as a signed, 8-bit immediate value, which is added to the instruction pointer.
Offsets of -128 to +127 are allowed with this instruction.
Some forms of the loop instruction (LOOPcc) also accept the ZF flag as a condition for terminating the loop before
the count reaches zero. With these forms of the instruction, a condition code (cc) is associated with each instruction
to indicate the condition being tested for. Here, the LOOPcc instruction itself does not affect the state of the ZF flag;
the ZF flag is changed by other instructions in the loop.

Operation
IF (AddressSize = 32)
    THEN Count is ECX;
ELSE IF (AddressSize = 64)
    Count is RCX;
ELSE Count is CX;
FI;

Count <- Count - 1;

IF Instruction is not LOOP
     THEN
         IF (Instruction <- LOOPE) or (Instruction <- LOOPZ)
               THEN IF (ZF = 1) and (Count != 0)
                         THEN BranchCond <- 1;
                         ELSE BranchCond <- 0;
                    FI;
               ELSE (Instruction = LOOPNE) or (Instruction = LOOPNZ)
                    IF (ZF = 0 ) and (Count != 0)
                         THEN BranchCond <- 1;
                         ELSE BranchCond <- 0;




                    FI;
          FI;
      ELSE (* Instruction = LOOP *)
          IF (Count != 0)
                THEN BranchCond <- 1;
                ELSE BranchCond <- 0;
          FI;
FI;

IF BranchCond = 1
    THEN
        IF OperandSize = 32
             THEN EIP <- EIP + SignExtend(DEST);
             ELSE IF OperandSize = 64
                 THEN RIP <- RIP + SignExtend(DEST);
                 FI;
             ELSE IF OperandSize = 16
                 THEN EIP <- EIP AND 0000FFFFH;
                 FI;
        FI;
        IF OperandSize = (32 or 64)
             THEN IF (R/E)IP < CS.Base or (R/E)IP > CS.Limit
                 #GP; FI;
                 FI;
        FI;
    ELSE
        Terminate loop and continue program execution at (R/E)IP;
FI;

Flags Affected
None

Protected Mode Exceptions
#GP(0)                  If the offset being jumped to is beyond the limits of the CS segment.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If the offset being jumped to is beyond the limits of the CS segment or is outside of the effec-
                        tive address space from 0 to FFFFH. This condition can occur if a 32-bit address size override
                        prefix is used.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                  If the offset being jumped to is in a non-canonical form.
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: LSL
description:
LSL-Load Segment Limit
Opcode                     Instruction                    Op/    64-Bit       Compat/ Description
                                                          En     Mode         Leg Mode
0F 03 /r                   LSL r16, r16/m16               RM     Valid        Valid        Load: r16 <- segment limit, selector r16/m16.
0F 03 /r                   LSL r32, r32/m16*              RM     Valid        Valid        Load: r32 <- segment limit, selector r32/m16.
REX.W + 0F 03 /r           LSL r64, r32/m16*              RM     Valid        Valid        Load: r64 <- segment limit, selector r32/m16
NOTES:
* For all loads (regardless of destination sizing), only bits 16-0 are used. Other bits are ignored.



                                                   Instruction Operand Encoding
    Op/En             Operand 1                         Operand 2                       Operand 3                   Operand 4
     RM             ModRM:reg (w)                     ModRM:r/m (r)                         NA                          NA

Description
Loads the unscrambled segment limit from the segment descriptor specified with the second operand (source
operand) into the first operand (destination operand) and sets the ZF flag in the EFLAGS register. The source
operand (which can be a register or a memory location) contains the segment selector for the segment descriptor
being accessed. The destination operand is a general-purpose register.
The processor performs access checks as part of the loading process. Once loaded in the destination register, soft-
ware can compare the segment limit with the offset of a pointer.
The segment limit is a 20-bit value contained in bytes 0 and 1 and in the first 4 bits of byte 6 of the segment
descriptor. If the descriptor has a byte granular segment limit (the granularity flag is set to 0), the destination
operand is loaded with a byte granular value (byte limit). If the descriptor has a page granular segment limit (the
granularity flag is set to 1), the LSL instruction will translate the page granular limit (page limit) into a byte limit
before loading it into the destination operand. The translation is performed by shifting the 20-bit "raw" limit left 12
bits and filling the low-order 12 bits with 1s.
When the operand size is 32 bits, the 32-bit byte limit is stored in the destination operand. When the operand size
is 16 bits, a valid 32-bit limit is computed; however, the upper 16 bits are truncated and only the low-order 16 bits
are loaded into the destination operand.
This instruction performs the following checks before it loads the segment limit into the destination register:
.    Checks that the segment selector is not NULL.
.    Checks that the segment selector points to a descriptor that is within the limits of the GDT or LDT being
     accessed
.    Checks that the descriptor type is valid for this instruction. All code and data segment descriptors are valid for
     (can be accessed with) the LSL instruction. The valid special segment and gate descriptor types are given in the
     following table.
.    If the segment is not a conforming code segment, the instruction checks that the specified segment descriptor
     is visible at the CPL (that is, if the CPL and the RPL of the segment selector are less than or equal to the DPL of
     the segment selector).
If the segment descriptor cannot be accessed or is an invalid type for the instruction, the ZF flag is cleared and no
value is loaded in the destination operand.





                                          Table 3-55. Segment and Gate Descriptor Types
       Type                               Protected Mode                                       IA-32e Mode
                                  Name                     Valid                    Name                        Valid
         0           Reserved                               No         Upper 8 byte of a 16-Byte                Yes
                                                                       descriptor
         1           Available 16-bit TSS                   Yes        Reserved                                  No
         2           LDT                                    Yes        LDT                                      Yes
         3           Busy 16-bit TSS                        Yes        Reserved                                  No
         4           16-bit call gate                       No         Reserved                                  No
         5           16-bit/32-bit task gate                No         Reserved                                  No
         6           16-bit interrupt gate                  No         Reserved                                  No
         7           16-bit trap gate                       No         Reserved                                  No
         8           Reserved                               No         Reserved                                  No
         9           Available 32-bit TSS                   Yes        64-bit TSS                               Yes
         A           Reserved                               No         Reserved                                  No
         B           Busy 32-bit TSS                        Yes        Busy 64-bit TSS                          Yes
         C           32-bit call gate                       No         64-bit call gate                          No
         D           Reserved                               No         Reserved                                  No
         E           32-bit interrupt gate                  No         64-bit interrupt gate                     No
         F           32-bit trap gate                       No         64-bit trap gate                          No

Operation
IF SRC(Offset) > descriptor table limit
    THEN ZF <- 0; FI;

Read segment descriptor;

IF SegmentDescriptor(Type) != conforming code segment
and (CPL > DPL) OR (RPL > DPL)
or Segment type is not valid for instruction
        THEN
            ZF <- 0;
        ELSE
            temp <- SegmentLimit([SRC]);
            IF (G <- 1)
                 THEN temp <- ShiftLeft(12, temp) OR 00000FFFH;
            ELSE IF OperandSize = 32
                 THEN DEST <- temp; FI;
            ELSE IF OperandSize = 64 (* REX.W used *)
                 THEN DEST (* Zero-extended *) <- temp; FI;
            ELSE (* OperandSize = 16 *)
                 DEST <- temp AND FFFFH;
            FI;
FI;

Flags Affected
The ZF flag is set to 1 if the segment limit is loaded successfully; otherwise, it is set to 0.




Protected Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                    selector.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and the memory operand effective address is unaligned while
                    the current privilege level is 3.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                 The LSL instruction cannot be executed in real-address mode.

Virtual-8086 Mode Exceptions
#UD                 The LSL instruction cannot be executed in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If the memory operand effective address referencing the SS segment is in a non-canonical
                    form.
#GP(0)              If the memory operand effective address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and the memory operand effective address is unaligned while
                    the current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: LTR
description:
LTR-Load Task Register
 Opcode                     Instruction                  Op/       64-Bit   Compat/ Description
                                                         En        Mode     Leg Mode
 0F 00 /3                   LTR r/m16                    M         Valid    Valid       Load r/m16 into task register.



                                                    Instruction Operand Encoding
   Op/En             Operand 1                      Operand 2                       Operand 3                    Operand 4
     M             ModRM:r/m (r)                        NA                             NA                            NA

Description
Loads the source operand into the segment selector field of the task register. The source operand (a general-
purpose register or a memory location) contains a segment selector that points to a task state segment (TSS).
After the segment selector is loaded in the task register, the processor uses the segment selector to locate the
segment descriptor for the TSS in the global descriptor table (GDT). It then loads the segment limit and base
address for the TSS from the segment descriptor into the task register. The task pointed to by the task register is
marked busy, but a switch to the task does not occur.
The LTR instruction is provided for use in operating-system software; it should not be used in application programs.
It can only be executed in protected mode when the CPL is 0. It is commonly used in initialization code to establish
the first task to be executed.
The operand-size attribute has no effect on this instruction.
In 64-bit mode, the operand size is still fixed at 16 bits. The instruction references a 16-byte descriptor to load the
64-bit base.

Operation
IF SRC is a NULL selector
    THEN #GP(0);

IF SRC(Offset) > descriptor table limit OR IF SRC(type) != global
    THEN #GP(segment selector); FI;

Read segment descriptor;

IF segment descriptor is not for an available TSS
    THEN #GP(segment selector); FI;
IF segment descriptor is not present
    THEN #NP(segment selector); FI;

TSSsegmentDescriptor(busy) <- 1;
(* Locked read-modify-write operation on the entire descriptor when setting busy flag *)

TaskRegister(SegmentSelector) <- SRC;
TaskRegister(SegmentDescriptor) <- TSSSegmentDescriptor;

Flags Affected
None





Protected Mode Exceptions
#GP(0)              If the current privilege level is not 0.
                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the source operand contains a NULL segment selector.
                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                    selector.
#GP(selector)       If the source selector points to a segment that is not a TSS or to one for a task that is already
                    busy.
                    If the selector points to LDT or is beyond the GDT limit.
#NP(selector)       If the TSS is marked not present.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#UD                 If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                 The LTR instruction is not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                  The LTR instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the current privilege level is not 0.
                    If the memory address is in a non-canonical form.
                    If the source operand contains a NULL segment selector.
#GP(selector)       If the source selector points to a segment that is not a TSS or to one for a task that is already
                    busy.
                    If the selector points to LDT or is beyond the GDT limit.
                    If the descriptor type of the upper 8-byte of the 16-byte descriptor is non-zero.
#NP(selector)       If the TSS is marked not present.
#PF(fault-code)     If a page fault occurs.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: LZCNT
description:
LZCNT- Count the Number of Leading Zero Bits
 Opcode/Instruction                Op/     64/32       CPUID        Description
                                   En      -bit        Feature
                                           Mode        Flag
 F3 0F BD /r                       RM      V/V         LZCNT        Count the number of leading zero bits in r/m16, return result in r16.
 LZCNT r16, r/m16

 F3 0F BD /r                       RM      V/V         LZCNT        Count the number of leading zero bits in r/m32, return result in r32.
 LZCNT r32, r/m32

 F3 REX.W 0F BD /r                 RM      V/N.E.      LZCNT        Count the number of leading zero bits in r/m64, return result in r64.
 LZCNT r64, r/m64



                                                     Instruction Operand Encoding
   Op/En             Operand 1                       Operand 2                       Operand 3                        Operand 4
    RM             ModRM:reg (w)                    ModRM:r/m (r)                        NA                               NA

Description
Counts the number of leading most significant zero bits in a source operand (second operand) returning the result
into a destination (first operand).
LZCNT differs from BSR. For example, LZCNT will produce the operand size when the input operand is zero. It
should be noted that on processors that do not support LZCNT, the instruction byte encoding is executed as BSR.
In 64-bit mode 64-bit operand size requires REX.W=1.

Operation
temp <- OperandSize - 1
DEST <- 0
WHILE (temp >= 0) AND (Bit(SRC, temp) = 0)
DO
   temp <- temp - 1
   DEST <- DEST+ 1
OD

IF DEST = OperandSize
    CF <- 1
ELSE
    CF <- 0
FI

IF DEST = 0
    ZF <- 1
ELSE
    ZF <- 0
FI

Flags Affected
ZF flag is set to 1 in case of zero output (most significant bit of the source is set), and to 0 otherwise, CF flag is set
to 1 if input was zero and cleared otherwise. OF, SF, PF and AF flags are undefined.





Intel C/C++ Compiler Intrinsic Equivalent
LZCNT:          unsigned __int32 _lzcnt_u32(unsigned __int32 src);

LZCNT:          unsigned __int64 _lzcnt_u64(unsigned __int64 src);

Protected Mode Exceptions
#GP(0)                   For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
                         If the DS, ES, FS, or GS register is used to access memory and it contains a null segment
                         selector.
#SS(0)                   For an illegal address in the SS segment.
#PF (fault-code)         For a page fault.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.

Real-Address Mode Exceptions
#GP(0)                   If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                   For an illegal address in the SS segment.

Virtual 8086 Mode Exceptions
#GP(0)                   If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)                   For an illegal address in the SS segment.
#PF (fault-code)         For a page fault.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.

Compatibility Mode Exceptions
Same exceptions as in Protected Mode.

64-Bit Mode Exceptions
#GP(0)                   If the memory address is in a non-canonical form.
#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)         For a page fault.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.






platform: x86_64
mnem: MASKMOVDQU
description:
MASKMOVDQU-Store Selected Bytes of Double Quadword
 Opcode/                                            Op/   64/32-bit CPUID       Description
 Instruction                                        En    Mode      Feature
                                                                    Flag
 66 0F F7 /r                                        RM    V/V       SSE2        Selectively write bytes from xmm1 to
 MASKMOVDQU xmm1, xmm2                                                          memory location using the byte mask in
                                                                                xmm2. The default memory location is
                                                                                specified by DS:DI/EDI/RDI.
 VEX.128.66.0F.WIG F7 /r                            RM    V/V       AVX         Selectively write bytes from xmm1 to
 VMASKMOVDQU xmm1, xmm2                                                         memory location using the byte mask in
                                                                                xmm2. The default memory location is
                                                                                specified by DS:DI/EDI/RDI.



                                           Instruction Operand Encoding1
    Op/En           Operand 1                    Operand 2                    Operand 3                  Operand 4
     RM            ModRM:reg (r)                ModRM:r/m (r)                    NA                          NA


Description
Stores selected bytes from the source operand (first operand) into an 128-bit memory location. The mask operand
(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-
ands are XMM registers. The memory location specified by the effective address in the DI/EDI/RDI register (the
default segment register is DS, but this may be overridden with a segment-override prefix). The memory location
does not need to be aligned on a natural boundary. (The size of the store address depends on the address-size
attribute.)
The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source
operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.
The MASKMOVDQU instruction generates a non-temporal hint to the processor to minimize cache pollution. The
non-temporal hint is implemented by using a write combining (WC) memory type protocol (see "Caching of
Temporal vs. Non-Temporal Data" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing opera-
tion implemented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVDQU
instructions if multiple processors might use different memory types to read/write the destination memory loca-
tions.
Behavior with a mask of all 0s is as follows:
.    No data will be written to memory.
.    Signaling of breakpoints (code or data) is not guaranteed; different processor implementations may signal or
     not signal these breakpoints.
.    Exceptions associated with addressing memory and page faults may still be signaled (implementation
     dependent).
.    If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these
     memory types is not guaranteed (that is, is reserved) and is implementation-specific.
The MASKMOVDQU instruction can be used to improve performance of algorithms that need to merge data on a
byte-by-byte basis. MASKMOVDQU should not cause a read for ownership; doing so generates unnecessary band-
width since data is to be written directly using the byte-mask without allocating old data prior to the store.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
If VMASKMOVDQU is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.

1.ModRM.MOD = 011B required



Operation

IF (MASK[7] = 1)
    THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;
IF (MASK[15] = 1)
    THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;
    (* Repeat operation for 3rd through 14th bytes in source operand *)
IF (MASK[127] = 1)
    THEN DEST[DI/EDI +15] <- SRC[127:120] ELSE (* Memory location unchanged *); FI;

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_maskmoveu_si128(__m128i d, __m128i n, char * p)

Other Exceptions
See Exceptions Type 4; additionally
#UD                    If VEX.L= 1
                       If VEX.vvvv != 1111B.






platform: x86_64
mnem: MASKMOVQ
description:
MASKMOVQ-Store Selected Bytes of Quadword
 Opcode/                                        Op/   64-Bit       Compat/ Description
 Instruction                                    En    Mode         Leg Mode
 0F F7 /r                                       RM    Valid        Valid     Selectively write bytes from mm1 to memory
 MASKMOVQ mm1, mm2                                                           location using the byte mask in mm2. The
                                                                             default memory location is specified by
                                                                             DS:DI/EDI/RDI.



                                           Instruction Operand Encoding
    Op/En          Operand 1                  Operand 2                    Operand 3                    Operand 4
     RM           ModRM:reg (r)             ModRM:r/m (r)                     NA                            NA


Description
Stores selected bytes from the source operand (first operand) into a 64-bit memory location. The mask operand
(second operand) selects which bytes from the source operand are written to memory. The source and mask oper-
ands are MMX technology registers. The memory location specified by the effective address in the DI/EDI/RDI
register (the default segment register is DS, but this may be overridden with a segment-override prefix). The
memory location does not need to be aligned on a natural boundary. (The size of the store address depends on the
address-size attribute.)
The most significant bit in each byte of the mask operand determines whether the corresponding byte in the source
operand is written to the corresponding byte location in memory: 0 indicates no write and 1 indicates write.
The MASKMOVQ instruction generates a non-temporal hint to the processor to minimize cache pollution. The non-
temporal hint is implemented by using a write combining (WC) memory type protocol (see "Caching of Temporal
vs. Non-Temporal Data" in Chapter 10, of the Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 1). Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation imple-
mented with the SFENCE or MFENCE instruction should be used in conjunction with MASKMOVQ instructions if
multiple processors might use different memory types to read/write the destination memory locations.
This instruction causes a transition from x87 FPU to MMX technology state (that is, the x87 FPU top-of-stack pointer
is set to 0 and the x87 FPU tag word is set to all 0s [valid]).
The behavior of the MASKMOVQ instruction with a mask of all 0s is as follows:
.    No data will be written to memory.
.    Transition from x87 FPU to MMX technology state will occur.
.    Exceptions associated with addressing memory and page faults may still be signaled (implementation
     dependent).
.    Signaling of breakpoints (code or data) is not guaranteed (implementation dependent).
.    If the destination memory region is mapped as UC or WP, enforcement of associated semantics for these
     memory types is not guaranteed (that is, is reserved) and is implementation-specific.
The MASKMOVQ instruction can be used to improve performance for algorithms that need to merge data on a byte-
by-byte basis. It should not cause a read for ownership; doing so generates unnecessary bandwidth since data is
to be written directly using the byte-mask without allocating old data prior to the store.
In 64-bit mode, the memory address is specified by DS:RDI.





Operation

IF (MASK[7] = 1)
    THEN DEST[DI/EDI] <- SRC[7:0] ELSE (* Memory location unchanged *); FI;
IF (MASK[15] = 1)
    THEN DEST[DI/EDI +1] <- SRC[15:8] ELSE (* Memory location unchanged *); FI;
    (* Repeat operation for 3rd through 6th bytes in source operand *)
IF (MASK[63] = 1)
    THEN DEST[DI/EDI +15] <- SRC[63:56] ELSE (* Memory location unchanged *); FI;

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_maskmove_si64(__m64d, __m64n, char * p)

Other Exceptions
See Table 22-8, "Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception," in the Intel 64
and IA-32 Architectures Software Developer's Manual, Volume 3A.






platform: x86_64
mnem: MAXPD
description:
MAXPD-Maximum of Packed Double-Precision Floating-Point Values
 Opcode/                                  Op /    64/32        CPUID          Description
 Instruction                              En      bit Mode     Feature
                                                  Support      Flag
 66 0F 5F /r                              RM      V/V          SSE2           Return the maximum double-precision floating-point
 MAXPD xmm1, xmm2/m128                                                        values between xmm1 and xmm2/m128.
 VEX.NDS.128.66.0F.WIG 5F /r              RVM     V/V          AVX            Return the maximum double-precision floating-point
 VMAXPD xmm1, xmm2, xmm3/m128                                                 values between xmm2 and xmm3/m128.
 VEX.NDS.256.66.0F.WIG 5F /r              RVM     V/V          AVX            Return the maximum packed double-precision
 VMAXPD ymm1, ymm2, ymm3/m256                                                 floating-point values between ymm2 and
                                                                              ymm3/m256.
 EVEX.NDS.128.66.0F.W1 5F /r              FV      V/V          AVX512VL       Return the maximum packed double-precision
 VMAXPD xmm1 {k1}{z}, xmm2,                                    AVX512F        floating-point values between xmm2 and
 xmm3/m128/m64bcst                                                            xmm3/m128/m64bcst and store result in xmm1
                                                                              subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 5F /r              FV      V/V          AVX512VL       Return the maximum packed double-precision
 VMAXPD ymm1 {k1}{z}, ymm2,                                    AVX512F        floating-point values between ymm2 and
 ymm3/m256/m64bcst                                                            ymm3/m256/m64bcst and store result in ymm1
                                                                              subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 5F /r              FV      V/V          AVX512F        Return the maximum packed double-precision
 VMAXPD zmm1 {k1}{z}, zmm2,                                                   floating-point values between zmm2 and
 zmm3/m512/m64bcst{sae}                                                       zmm3/m512/m64bcst and store result in zmm1
                                                                              subject to writemask k1.



                                                 Instruction Operand Encoding
      Op/En               Operand 1                      Operand 2                   Operand 3                    Operand 4
        RM             ModRM:reg (r, w)                 ModRM:r/m (r)                    NA                           NA
       RVM              ModRM:reg (w)                     VEX.vvvv                 ModRM:r/m (r)                      NA
        FV              ModRM:reg (w)                    EVEX.vvvv                 ModRM:r/m (r)                      NA

Description
Performs a SIMD compare of the packed double-precision floating-point values in the first source operand and the
second source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MAXPD can be emulated using a
sequence of instructions, such as a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.





128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.

Operation
MAX(SRC1, SRC2)
{
  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;
        ELSE DEST <-SRC2;
  FI;
}

VMAXPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[63:0])
                    ELSE
                         DEST[i+63:i] <- MAX(SRC1[i+63:i], SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMAXPD (VEX.256 encoded version)
DEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])
DEST[191:128] <-MAX(SRC1[191:128], SRC2[191:128])
DEST[255:192] <-MAX(SRC1[255:192], SRC2[255:192])
DEST[MAX_VL-1:256] <-0

VMAXPD (VEX.128 encoded version)
DEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-MAX(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] <-0





MAXPD (128-bit Legacy SSE version)
DEST[63:0] <-MAX(DEST[63:0], SRC[63:0])
DEST[127:64] <-MAX(DEST[127:64], SRC[127:64])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMAXPD __m512d _mm512_max_pd( __m512d a, __m512d b);
VMAXPD __m512d _mm512_mask_max_pd(__m512d s, __mmask8 k, __m512d a, __m512d b,);
VMAXPD __m512d _mm512_maskz_max_pd( __mmask8 k, __m512d a, __m512d b);
VMAXPD __m512d _mm512_max_round_pd( __m512d a, __m512d b, int);
VMAXPD __m512d _mm512_mask_max_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMAXPD __m512d _mm512_maskz_max_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMAXPD __m256d _mm256_mask_max_pd(__m5256d s, __mmask8 k, __m256d a, __m256d b);
VMAXPD __m256d _mm256_maskz_max_pd( __mmask8 k, __m256d a, __m256d b);
VMAXPD __m128d _mm_mask_max_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMAXPD __m128d _mm_maskz_max_pd( __mmask8 k, __m128d a, __m128d b);
VMAXPD __m256d _mm256_max_pd (__m256d a, __m256d b);
(V)MAXPD __m128d _mm_max_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MAXPS
description:
MAXPS-Maximum of Packed Single-Precision Floating-Point Values
 Opcode/                             Op /     64/32         CPUID      Description
 Instruction                         En       bit Mode      Feature
                                              Support       Flag
 0F 5F /r                            RM       V/V           SSE        Return the maximum single-precision floating-point values
 MAXPS xmm1, xmm2/m128                                                 between xmm1 and xmm2/mem.
 VEX.NDS.128.0F.WIG 5F /r            RVM      V/V           AVX        Return the maximum single-precision floating-point values
 VMAXPS xmm1, xmm2,                                                    between xmm2 and xmm3/mem.
 xmm3/m128
 VEX.NDS.256.0F.WIG 5F /r            RVM      V/V           AVX        Return the maximum single-precision floating-point values
 VMAXPS ymm1, ymm2,                                                    between ymm2 and ymm3/mem.
 ymm3/m256
 EVEX.NDS.128.0F.W0 5F /r            FV       V/V           AVX512VL   Return the maximum packed single-precision floating-point
 VMAXPS xmm1 {k1}{z}, xmm2,                                 AVX512F    values between xmm2 and xmm3/m128/m32bcst and store
 xmm3/m128/m32bcst                                                     result in xmm1 subject to writemask k1.
 EVEX.NDS.256.0F.W0 5F /r            FV       V/V           AVX512VL   Return the maximum packed single-precision floating-point
 VMAXPS ymm1 {k1}{z}, ymm2,                                 AVX512F    values between ymm2 and ymm3/m256/m32bcst and store
 ymm3/m256/m32bcst                                                     result in ymm1 subject to writemask k1.
 EVEX.NDS.512.0F.W0 5F /r            FV       V/V           AVX512F    Return the maximum packed single-precision floating-point
 VMAXPS zmm1 {k1}{z}, zmm2,                                            values between zmm2 and zmm3/m512/m32bcst and store
 zmm3/m512/m32bcst{sae}                                                result in zmm1 subject to writemask k1.



                                                    Instruction Operand Encoding
     Op/En               Operand 1                       Operand 2                   Operand 3                  Operand 4
      RM              ModRM:reg (r, w)               ModRM:r/m (r)                      NA                          NA
      RVM              ModRM:reg (w)                     VEX.vvvv               ModRM:r/m (r)                       NA
       FV              ModRM:reg (w)                     EVEX.vvvv               ModRM:r/m (r)                      NA

Description
Performs a SIMD compare of the packed single-precision floating-point values in the first source operand and the
second source operand and returns the maximum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MAXPS can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.




Operation
MAX(SRC1, SRC2)
{
  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;
        ELSE DEST <-SRC2;
  FI;
}

VMAXPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[31:0])
                    ELSE
                         DEST[i+31:i] <- MAX(SRC1[i+31:i], SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMAXPS (VEX.256 encoded version)
DEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])
DEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])
DEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])
DEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])
DEST[159:128] <-MAX(SRC1[159:128], SRC2[159:128])
DEST[191:160] <-MAX(SRC1[191:160], SRC2[191:160])
DEST[223:192] <-MAX(SRC1[223:192], SRC2[223:192])
DEST[255:224] <-MAX(SRC1[255:224], SRC2[255:224])
DEST[MAX_VL-1:256] <-0

VMAXPS (VEX.128 encoded version)
DEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])
DEST[63:32] <-MAX(SRC1[63:32], SRC2[63:32])
DEST[95:64] <-MAX(SRC1[95:64], SRC2[95:64])
DEST[127:96] <-MAX(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] <-0





MAXPS (128-bit Legacy SSE version)
DEST[31:0] <-MAX(DEST[31:0], SRC[31:0])
DEST[63:32] <-MAX(DEST[63:32], SRC[63:32])
DEST[95:64] <-MAX(DEST[95:64], SRC[95:64])
DEST[127:96] <-MAX(DEST[127:96], SRC[127:96])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMAXPS __m512 _mm512_max_ps( __m512 a, __m512 b);
VMAXPS __m512 _mm512_mask_max_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMAXPS __m512 _mm512_maskz_max_ps( __mmask16 k, __m512 a, __m512 b);
VMAXPS __m512 _mm512_max_round_ps( __m512 a, __m512 b, int);
VMAXPS __m512 _mm512_mask_max_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMAXPS __m512 _mm512_maskz_max_round_ps( __mmask16 k, __m512 a, __m512 b, int);
VMAXPS __m256 _mm256_mask_max_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMAXPS __m256 _mm256_maskz_max_ps( __mmask8 k, __m256 a, __m256 b);
VMAXPS __m128 _mm_mask_max_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMAXPS __m128 _mm_maskz_max_ps( __mmask8 k, __m128 a, __m128 b);
VMAXPS __m256 _mm256_max_ps (__m256 a, __m256 b);
MAXPS __m128 _mm_max_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MAXSD
description:
MAXSD-Return Maximum Scalar Double-Precision Floating-Point Value
 Opcode/                         Op /    64/32       CPUID        Description
 Instruction                     En      bit Mode    Feature
                                         Support     Flag
 F2 0F 5F /r                     RM      V/V         SSE2         Return the maximum scalar double-precision floating-point
 MAXSD xmm1, xmm2/m64                                             value between xmm2/m64 and xmm1.
 VEX.NDS.128.F2.0F.WIG 5F /r     RVM     V/V         AVX          Return the maximum scalar double-precision floating-point
 VMAXSD xmm1, xmm2,                                               value between xmm3/m64 and xmm2.
 xmm3/m64
 EVEX.NDS.LIG.F2.0F.W1 5F /r     T1S     V/V         AVX512F      Return the maximum scalar double-precision floating-point
 VMAXSD xmm1 {k1}{z}, xmm2,                                       value between xmm3/m64 and xmm2.
 xmm3/m64{sae}



                                               Instruction Operand Encoding
       Op/En             Operand 1                  Operand 2                   Operand 3                    Operand 4
        RM            ModRM:reg (r, w)            ModRM:r/m (r)                    NA                            NA
       RVM             ModRM:reg (w)                VEX.vvvv                 ModRM:r/m (r)                       NA
        T1S            ModRM:reg (w)                EVEX.vvvv                ModRM:r/m (r)                       NA

Description
Compares the low double-precision floating-point values in the first source operand and the second source
operand, and returns the maximum value to the low quadword of the destination operand. The second source
operand can be an XMM register or a 64-bit memory location. The first source and destination operands are XMM
registers. When the second source operand is a memory operand, only 64 bits are accessed.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN of either source
operand be returned, the action of MAXSD can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMAXSD is encoded with VEX.L=0. Encoding VMAXSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
MAX(SRC1, SRC2)
{
  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;
        ELSE DEST <-SRC2;
  FI;
}

VMAXSD (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- MAX(SRC1[63:0], SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VMAXSD (VEX.128 encoded version)
DEST[63:0] <-MAX(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

MAXSD (128-bit Legacy SSE version)
DEST[63:0] <-MAX(DEST[63:0], SRC[63:0])
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMAXSD __m128d _mm_max_round_sd( __m128d a, __m128d b, int);
VMAXSD __m128d _mm_mask_max_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMAXSD __m128d _mm_maskz_max_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MAXSD __m128d _mm_max_sd(__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: MAXSS
description:
MAXSS-Return Maximum Scalar Single-Precision Floating-Point Value
 Opcode/                              Op /   64/32        CPUID      Description
 Instruction                          En     bit Mode     Feature
                                             Support      Flag
 F3 0F 5F /r                          RM     V/V          SSE        Return the maximum scalar single-precision floating-point
 MAXSS xmm1, xmm2/m32                                                value between xmm2/m32 and xmm1.
 VEX.NDS.128.F3.0F.WIG 5F /r          RVM    V/V          AVX        Return the maximum scalar single-precision floating-point
 VMAXSS xmm1, xmm2,                                                  value between xmm3/m32 and xmm2.
 xmm3/m32
 EVEX.NDS.LIG.F3.0F.W0 5F /r          T1S    V/V          AVX512F    Return the maximum scalar single-precision floating-point
 VMAXSS xmm1 {k1}{z}, xmm2,                                          value between xmm3/m32 and xmm2.
 xmm3/m32{sae}



                                              Instruction Operand Encoding
      Op/En               Operand 1                     Operand 2                 Operand 3                     Operand 4
        RM             ModRM:reg (r, w)            ModRM:r/m (r)                      NA                            NA
       RVM              ModRM:reg (w)                   VEX.vvvv                ModRM:r/m (r)                       NA
       T1S             ModRM:reg (w)                    EVEX.vvvv               ModRM:r/m (r)                       NA

Description
Compares the low single-precision floating-point values in the first source operand and the second source operand,
and returns the maximum value to the low doubleword of the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN from either source
operand be returned, the action of MAXSS can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-
sponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by VEX.vvvv. Bits
(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMAXSS is encoded with VEX.L=0. Encoding VMAXSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
MAX(SRC1, SRC2)
{
  IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
        ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
        ELSE IF (SRC1 > SRC2) THEN DEST <-SRC1;
        ELSE DEST <-SRC2;
  FI;
}

VMAXSS (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- MAX(SRC1[31:0], SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VMAXSS (VEX.128 encoded version)
DEST[31:0] <-MAX(SRC1[31:0], SRC2[31:0])
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

MAXSS (128-bit Legacy SSE version)
DEST[31:0] <-MAX(DEST[31:0], SRC[31:0])
DEST[MAX_VL-1:32] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMAXSS __m128 _mm_max_round_ss( __m128 a, __m128 b, int);
VMAXSS __m128 _mm_mask_max_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMAXSS __m128 _mm_maskz_max_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MAXSS __m128 _mm_max_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: MFENCE
description:
MFENCE-Memory Fence
 Opcode                    Instruction                   Op/    64-Bit       Compat/ Description
                                                         En     Mode         Leg Mode
 0F AE F0                  MFENCE                        NP     Valid        Valid       Serializes load and store operations.



                                                   Instruction Operand Encoding
    Op/En               Operand 1                      Operand 2                      Operand 3                      Operand 4
      NP                    NA                             NA                             NA                            NA


Description
Performs a serializing operation on all load-from-memory and store-to-memory instructions that were issued prior
the MFENCE instruction. This serializing operation guarantees that every load and store instruction that precedes
the MFENCE instruction in program order becomes globally visible before any load or store instruction that follows
the MFENCE instruction.1 The MFENCE instruction is ordered with respect to all load and store instructions, other
MFENCE instructions, any LFENCE and SFENCE instructions, and any serializing instructions (such as the CPUID
instruction). MFENCE does not serialize the instruction stream.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue, speculative reads, write-combining, and write-collapsing. The degree to which a consumer of
data recognizes or knows that the data is weakly ordered varies among applications and may be unknown to the
producer of this data. The MFENCE instruction provides a performance-efficient way of ensuring load and store
ordering between routines that produce weakly-ordered results and routines that consume that data.
Processors are free to fetch and cache data speculatively from regions of system memory that use the WB, WC, and
WT memory types. This speculative fetching can occur at any time and is not tied to instruction execution. Thus, it
is not ordered with respect to executions of the MFENCE instruction; data can be brought into the caches specula-
tively just before, during, or after the execution of an MFENCE instruction.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded by any opcode of the form 0F AE Fx, where x
is in the range 0-7.

Operation

Wait_On_Following_Loads_And_Stores_Until(preceding_loads_and_stores_globally_visible);

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_mfence(void)

Exceptions (All Modes of Operation)
#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.
                        If the LOCK prefix is used.




1. A load instruction is considered to become globally visible when the value to be loaded into its destination register is determined.




platform: x86_64
mnem: MINPD
description:
MINPD-Minimum of Packed Double-Precision Floating-Point Values
 Opcode/                               Op /    64/32         CPUID         Description
 Instruction                           En      bit Mode      Feature
                                               Support       Flag
 66 0F 5D /r                           RM      V/V           SSE2          Return the minimum double-precision floating-point values
 MINPD xmm1, xmm2/m128                                                     between xmm1 and xmm2/mem
 VEX.NDS.128.66.0F.WIG 5D /r           RVM     V/V           AVX           Return the minimum double-precision floating-point values
 VMINPD xmm1, xmm2,                                                        between xmm2 and xmm3/mem.
 xmm3/m128
 VEX.NDS.256.66.0F.WIG 5D /r           RVM     V/V           AVX           Return the minimum packed double-precision floating-point
 VMINPD ymm1, ymm2,                                                        values between ymm2 and ymm3/mem.
 ymm3/m256
 EVEX.NDS.128.66.0F.W1 5D /r           FV      V/V           AVX512VL      Return the minimum packed double-precision floating-point
 VMINPD xmm1 {k1}{z}, xmm2,                                  AVX512F       values between xmm2 and xmm3/m128/m64bcst and store
 xmm3/m128/m64bcst                                                         result in xmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 5D /r           FV      V/V           AVX512VL      Return the minimum packed double-precision floating-point
 VMINPD ymm1 {k1}{z}, ymm2,                                  AVX512F       values between ymm2 and ymm3/m256/m64bcst and store
 ymm3/m256/m64bcst                                                         result in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 5D /r           FV      V/V           AVX512F       Return the minimum packed double-precision floating-point
 VMINPD zmm1 {k1}{z}, zmm2,                                                values between zmm2 and zmm3/m512/m64bcst and store
 zmm3/m512/m64bcst{sae}                                                    result in zmm1 subject to writemask k1.



                                                     Instruction Operand Encoding
        Op/En                  Operand 1                     Operand 2                   Operand 3                 Operand 4
          RM                ModRM:reg (r, w)               ModRM:r/m (r)                    NA                         NA
         RVM                 ModRM:reg (w)                   VEX.vvvv                 ModRM:r/m (r)                    NA
          FV                 ModRM:reg (w)                  EVEX.vvvv                 ModRM:r/m (r)                    NA

Description
Performs a SIMD compare of the packed double-precision floating-point values in the first source operand and the
second source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MINPD can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.




Operation
MIN(SRC1, SRC2)
{
   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;
         ELSE DEST <-SRC2;
   FI;
}

VMINPD (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[63:0])
                    ELSE
                         DEST[i+63:i] <- MIN(SRC1[i+63:i], SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMINPD (VEX.256 encoded version)
DEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])
DEST[191:128] <-MIN(SRC1[191:128], SRC2[191:128])
DEST[255:192] <-MIN(SRC1[255:192], SRC2[255:192])

VMINPD (VEX.128 encoded version)
DEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] <-0

MINPD (128-bit Legacy SSE version)
DEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-MIN(SRC1[127:64], SRC2[127:64])
DEST[MAX_VL-1:128] (Unmodified)





Intel C/C++ Compiler Intrinsic Equivalent
VMINPD __m512d _mm512_min_pd( __m512d a, __m512d b);
VMINPD __m512d _mm512_mask_min_pd(__m512d s, __mmask8 k, __m512d a, __m512d b);
VMINPD __m512d _mm512_maskz_min_pd( __mmask8 k, __m512d a, __m512d b);
VMINPD __m512d _mm512_min_round_pd( __m512d a, __m512d b, int);
VMINPD __m512d _mm512_mask_min_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m512d _mm512_maskz_min_round_pd( __mmask8 k, __m512d a, __m512d b, int);
VMINPD __m256d _mm256_mask_min_pd(__m256d s, __mmask8 k, __m256d a, __m256d b);
VMINPD __m256d _mm256_maskz_min_pd( __mmask8 k, __m256d a, __m256d b);
VMINPD __m128d _mm_mask_min_pd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VMINPD __m128d _mm_maskz_min_pd( __mmask8 k, __m128d a, __m128d b);
VMINPD __m256d _mm256_min_pd (__m256d a, __m256d b);
MINPD __m128d _mm_min_pd (__m128d a, __m128d b);

SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MINPS
description:
MINPS-Minimum of Packed Single-Precision Floating-Point Values
 Opcode/                         Op /    64/32        CPUID         Description
 Instruction                     En      bit Mode     Feature
                                         Support      Flag
 0F 5D /r                        RM      V/V          SSE           Return the minimum single-precision floating-point values
 MINPS xmm1, xmm2/m128                                              between xmm1 and xmm2/mem.
 VEX.NDS.128.0F.WIG 5D /r        RVM     V/V          AVX           Return the minimum single-precision floating-point values
 VMINPS xmm1, xmm2,                                                 between xmm2 and xmm3/mem.
 xmm3/m128
 VEX.NDS.256.0F.WIG 5D /r        RVM     V/V          AVX           Return the minimum single double-precision floating-point
 VMINPS ymm1, ymm2,                                                 values between ymm2 and ymm3/mem.
 ymm3/m256
 EVEX.NDS.128.0F.W0 5D /r        FV      V/V          AVX512VL      Return the minimum packed single-precision floating-point
 VMINPS xmm1 {k1}{z}, xmm2,                           AVX512F       values between xmm2 and xmm3/m128/m32bcst and store
 xmm3/m128/m32bcst                                                  result in xmm1 subject to writemask k1.
 EVEX.NDS.256.0F.W0 5D /r        FV      V/V          AVX512VL      Return the minimum packed single-precision floating-point
 VMINPS ymm1 {k1}{z}, ymm2,                           AVX512F       values between ymm2 and ymm3/m256/m32bcst and store
 ymm3/m256/m32bcst                                                  result in ymm1 subject to writemask k1.
 EVEX.NDS.512.0F.W0 5D /r        FV      V/V          AVX512F       Return the minimum packed single-precision floating-point
 VMINPS zmm1 {k1}{z}, zmm2,                                         values between zmm2 and zmm3/m512/m32bcst and store
 zmm3/m512/m32bcst{sae}                                             result in zmm1 subject to writemask k1.



                                               Instruction Operand Encoding
      Op/En              Operand 1                   Operand 2                     Operand 3                    Operand 4
        RM            ModRM:reg (r, w)              ModRM:r/m (r)                      NA                           NA
       RVM             ModRM:reg (w)                  VEX.vvvv                    ModRM:r/m (r)                     NA
        FV             ModRM:reg (w)                 EVEX.vvvv                    ModRM:r/m (r)                     NA

Description
Performs a SIMD compare of the packed single-precision floating-point values in the first source operand and the
second source operand and returns the minimum value for each pair of values to the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second operand (source operand) is
returned. If a value in the second operand is an SNaN, then SNaN is forwarded unchanged to the destination (that
is, a QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second operand (source operand), either a NaN
or a valid floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source
operand (from either the first or second operand) be returned, the action of MINPS can be emulated using a
sequence of instructions, such as, a comparison followed by AND, ANDN and OR.
EVEX encoded versions: The first source operand (the second operand) is a ZMM/YMM/XMM register. The second
source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally
updated with writemask k1.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256)
of the corresponding ZMM register destination are zeroed.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
ZMM register destination are unmodified.




Operation
MIN(SRC1, SRC2)
{
   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;
         ELSE DEST <-SRC2;
   FI;
}

VMINPS (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[31:0])
                    ELSE
                         DEST[i+31:i] <- MIN(SRC1[i+31:i], SRC2[i+31:i])
               FI;
               ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMINPS (VEX.256 encoded version)
DEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])
DEST[159:128] <-MIN(SRC1[159:128], SRC2[159:128])
DEST[191:160] <-MIN(SRC1[191:160], SRC2[191:160])
DEST[223:192] <-MIN(SRC1[223:192], SRC2[223:192])
DEST[255:224] <-MIN(SRC1[255:224], SRC2[255:224])

VMINPS (VEX.128 encoded version)
DEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] <-0





MINPS (128-bit Legacy SSE version)
DEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])
DEST[63:32] <-MIN(SRC1[63:32], SRC2[63:32])
DEST[95:64] <-MIN(SRC1[95:64], SRC2[95:64])
DEST[127:96] <-MIN(SRC1[127:96], SRC2[127:96])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMINPS __m512 _mm512_min_ps( __m512 a, __m512 b);
VMINPS __m512 _mm512_mask_min_ps(__m512 s, __mmask16 k, __m512 a, __m512 b);
VMINPS __m512 _mm512_maskz_min_ps( __mmask16 k, __m512 a, __m512 b);
VMINPS __m512 _mm512_min_round_ps( __m512 a, __m512 b, int);
VMINPS __m512 _mm512_mask_min_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m512 _mm512_maskz_min_round_ps( __mmask16 k, __m512 a, __m512 b, int);
VMINPS __m256 _mm256_mask_min_ps(__m256 s, __mmask8 k, __m256 a, __m256 b);
VMINPS __m256 _mm256_maskz_min_ps( __mmask8 k, __m256 a, __m25 b);
VMINPS __m128 _mm_mask_min_ps(__m128 s, __mmask8 k, __m128 a, __m128 b);
VMINPS __m128 _mm_maskz_min_ps( __mmask8 k, __m128 a, __m128 b);
VMINPS __m256 _mm256_min_ps (__m256 a, __m256 b);
MINPS __m128 _mm_min_ps (__m128 a, __m128 b);

SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MINSD
description:
MINSD-Return Minimum Scalar Double-Precision Floating-Point Value
 Opcode/                                    Op /   64/32            CPUID     Description
 Instruction                                En     bit Mode         Feature
                                                   Support          Flag
 F2 0F 5D /r                                RM     V/V              SSE2      Return the minimum scalar double-precision floating-
 MINSD xmm1, xmm2/m64                                                         point value between xmm2/m64 and xmm1.
 VEX.NDS.128.F2.0F.WIG 5D /r                RVM    V/V              AVX       Return the minimum scalar double-precision floating-
 VMINSD xmm1, xmm2, xmm3/m64                                                  point value between xmm3/m64 and xmm2.
 EVEX.NDS.LIG.F2.0F.W1 5D /r                T1S    V/V              AVX512F   Return the minimum scalar double-precision floating-
 VMINSD xmm1 {k1}{z}, xmm2,                                                   point value between xmm3/m64 and xmm2.
 xmm3/m64{sae}



                                                    Instruction Operand Encoding
        Op/En                   Operand 1                     Operand 2                 Operand 3                   Operand 4
         RM                 ModRM:reg (r, w)                ModRM:r/m (r)                   NA                         NA
         RVM                 ModRM:reg (w)                    VEX.vvvv                ModRM:r/m (r)                    NA
         T1S                 ModRM:reg (w)                    EVEX.vvvv               ModRM:r/m (r)                    NA

Description
Compares the low double-precision floating-point values in the first source operand and the second source
operand, and returns the minimum value to the low quadword of the destination operand. When the source
operand is a memory operand, only the 64 bits are accessed.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second source operand is an SNaN, then SNaN is returned unchanged to the destination (that is, a
QNaN version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN source operand
(from either the first or second source) be returned, the action of MINSD can be emulated using a sequence of
instructions, such as, a comparison followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 64-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL-1:64) of the
corresponding destination register remain unchanged.
VEX.128 and EVEX encoded version: Bits (127:64) of the XMM register destination are copied from corresponding
bits in the first source operand. Bits (MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low quadword element of the destination operand is updated according to the
writemask.
Software should ensure VMINSD is encoded with VEX.L=0. Encoding VMINSD with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
MIN(SRC1, SRC2)
{
   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;
         ELSE DEST <-SRC2;
   FI;
}

MINSD (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- MIN(SRC1[63:0], SRC2[63:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

MINSD (VEX.128 encoded version)
DEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

MINSD (128-bit Legacy SSE version)
DEST[63:0] <-MIN(SRC1[63:0], SRC2[63:0])
DEST[MAX_VL-1:64] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMINSD __m128d _mm_min_round_sd(__m128d a, __m128d b, int);
VMINSD __m128d _mm_mask_min_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VMINSD __m128d _mm_maskz_min_round_sd( __mmask8 k, __m128d a, __m128d b, int);
MINSD __m128d _mm_min_sd(__m128d a, __m128d b)

SIMD Floating-Point Exceptions
Invalid (including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 3.
EVEX-encoded instruction, see Exceptions Type E3.






platform: x86_64
mnem: MINSS
description:
MINSS-Return Minimum Scalar Single-Precision Floating-Point Value
 Opcode/                                    Op /     64/32          CPUID     Description
 Instruction                                En       bit Mode       Feature
                                                     Support        Flag
 F3 0F 5D /r                                RM       V/V            SSE       Return the minimum scalar single-precision floating-
 MINSS xmm1,xmm2/m32                                                          point value between xmm2/m32 and xmm1.
 VEX.NDS.128.F3.0F.WIG 5D /r                RVM      V/V            AVX       Return the minimum scalar single-precision floating-
 VMINSS xmm1,xmm2, xmm3/m32                                                   point value between xmm3/m32 and xmm2.
 EVEX.NDS.LIG.F3.0F.W0 5D /r                T1S      V/V            AVX512F   Return the minimum scalar single-precision floating-
 VMINSS xmm1 {k1}{z}, xmm2,                                                   point value between xmm3/m32 and xmm2.
 xmm3/m32{sae}



                                                     Instruction Operand Encoding
         Op/En                   Operand 1                      Operand 2               Operand 3                   Operand 4
           RM                 ModRM:reg (r, w)               ModRM:r/m (r)                  NA                          NA
          RVM                  ModRM:reg (w)                    VEX.vvvv               ModRM:r/m (r)                    NA
          T1S                  ModRM:reg (w)                    EVEX.vvvv              ModRM:r/m (r)                    NA

Description
Compares the low single-precision floating-point values in the first source operand and the second source operand
and returns the minimum value to the low doubleword of the destination operand.
If the values being compared are both 0.0s (of either sign), the value in the second source operand is returned. If
a value in the second operand is an SNaN, that SNaN is returned unchanged to the destination (that is, a QNaN
version of the SNaN is not returned).
If only one value is a NaN (SNaN or QNaN) for this instruction, the second source operand, either a NaN or a valid
floating-point value, is written to the result. If instead of this behavior, it is required that the NaN in either source
operand be returned, the action of MINSD can be emulated using a sequence of instructions, such as, a comparison
followed by AND, ANDN and OR.
The second source operand can be an XMM register or a 32-bit memory location. The first source and destination
operands are XMM registers.
128-bit Legacy SSE version: The destination and first source operand are the same. Bits (MAX_VL:32) of the corre-
sponding destination register remain unchanged.
VEX.128 and EVEX encoded version: The first source operand is an xmm register encoded by (E)VEX.vvvv. Bits
(127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
EVEX encoded version: The low doubleword element of the destination operand is updated according to the
writemask.
Software should ensure VMINSS is encoded with VEX.L=0. Encoding VMINSS with VEX.L=1 may encounter unpre-
dictable behavior across different processor generations.





Operation
MIN(SRC1, SRC2)
{
   IF ((SRC1 = 0.0) and (SRC2 = 0.0)) THEN DEST <-SRC2;
         ELSE IF (SRC1 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC2 = SNaN) THEN DEST <-SRC2; FI;
         ELSE IF (SRC1 < SRC2) THEN DEST <-SRC1;
         ELSE DEST <-SRC2;
   FI;
}

MINSS (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- MIN(SRC1[31:0], SRC2[31:0])
    ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                          ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

VMINSS (VEX.128 encoded version)
DEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

MINSS (128-bit Legacy SSE version)
DEST[31:0] <-MIN(SRC1[31:0], SRC2[31:0])
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMINSS __m128 _mm_min_round_ss( __m128 a, __m128 b, int);
VMINSS __m128 _mm_mask_min_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VMINSS __m128 _mm_maskz_min_round_ss( __mmask8 k, __m128 a, __m128 b, int);
MINSS __m128 _mm_min_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
Invalid (Including QNaN Source Operand), Denormal

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 2.
EVEX-encoded instruction, see Exceptions Type E2.






platform: x86_64
mnem: MONITOR
description:
MONITOR-Set Up Monitor Address
Opcode                   Instruction                  Op/   64-Bit      Compat/ Description
                                                      En    Mode        Leg Mode
0F 01 C8                 MONITOR                      NP    Valid       Valid       Sets up a linear address range to be
                                                                                    monitored by hardware and activates the
                                                                                    monitor. The address range should be a write-
                                                                                    back memory caching type. The address is
                                                                                    DS:EAX (DS:RAX in 64-bit mode).



                                               Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                    Operand 3                    Operand 4
    NP                   NA                           NA                            NA                           NA


Description
The MONITOR instruction arms address monitoring hardware using an address specified in EAX (the address range
that the monitoring hardware checks for store operations can be determined by using CPUID). A store to an
address within the specified address range triggers the monitoring hardware. The state of monitor hardware is
used by MWAIT.
The content of EAX is an effective address (in 64-bit mode, RAX is used). By default, the DS segment is used to
create a linear address that is monitored. Segment overrides can be used.
ECX and EDX are also used. They communicate other information to MONITOR. ECX specifies optional extensions.
EDX specifies optional hints; it does not change the architectural behavior of the instruction. For the Pentium 4
processor (family 15, model 3), no extensions or hints are defined. Undefined hints in EDX are ignored by the
processor; undefined extensions in ECX raises a general protection fault.
The address range must use memory of the write-back type. Only write-back memory will correctly trigger the
monitoring hardware. Additional information on determining what address range to use in order to prevent false
wake-ups is described in Chapter 8, "Multiple-Processor Management" of the Intel 64 and IA-32 Architectures
Software Developer's Manual, Volume 3A.
The MONITOR instruction is ordered as a load operation with respect to other memory transactions. The instruction
is subject to the permission checking and faults associated with a byte load. Like a load, MONITOR sets the A-bit
but not the D-bit in page tables.
CPUID.01H:ECX.MONITOR[bit 3] indicates the availability of MONITOR and MWAIT in the processor. When set,
MONITOR may be executed only at privilege level 0 (use at any other privilege level results in an invalid-opcode
exception). The operating system or system BIOS may disable this instruction by using the IA32_MISC_ENABLE
MSR; disabling MONITOR clears the CPUID feature flag and causes execution to generate an invalid-opcode excep-
tion.
The instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
MONITOR sets up an address range for the monitor hardware using the content of EAX (RAX in 64-bit mode) as an
effective address and puts the monitor hardware in armed state. Always use memory of the write-back caching
type. A store to the specified address range will trigger the monitor hardware. The content of ECX and EDX are
used to communicate other information to the monitor hardware.

Intel C/C++ Compiler Intrinsic Equivalent
MONITOR:      void _mm_monitor(void const *p, unsigned extensions,unsigned hints)

Numeric Exceptions
None




Protected Mode Exceptions
#GP(0)              If the value in EAX is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                    selector.
                    If ECX != 0.
#SS(0)              If the value in EAX is outside the SS segment limit.
#PF(fault-code)     For a page fault.
#UD                 If CPUID.01H:ECX.MONITOR[bit 3] = 0.
                    If current privilege level is not 0.

Real Address Mode Exceptions
#GP                 If the CS, DS, ES, FS, or GS register is used to access memory and the value in EAX is outside
                    of the effective address space from 0 to FFFFH.
                    If ECX != 0.
#SS                 If the SS register is used to access memory and the value in EAX is outside of the effective
                    address space from 0 to FFFFH.
#UD                 If CPUID.01H:ECX.MONITOR[bit 3] = 0.

Virtual 8086 Mode Exceptions
#UD                 The MONITOR instruction is not recognized in virtual-8086 mode (even if
                    CPUID.01H:ECX.MONITOR[bit 3] = 1).

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)              If the linear address of the operand in the CS, DS, ES, FS, or GS segment is in a non-canonical
                    form.
                    If RCX != 0.
#SS(0)              If the SS register is used to access memory and the value in EAX is in a non-canonical form.
#PF(fault-code)     For a page fault.
#UD                 If the current privilege level is not 0.
                    If CPUID.01H:ECX.MONITOR[bit 3] = 0.






platform: x86_64
mnem: MOV
description:
MOV-Move
 Opcode              Instruction           Op/   64-Bit   Compat/ Description
                                           En    Mode     Leg Mode
 88 /r               MOV r/m8,r8           MR    Valid    Valid    Move r8 to r/m8.
 REX + 88 /r         MOV r/m8***,r8***     MR    Valid    N.E.     Move r8 to r/m8.
 89 /r               MOV r/m16,r16         MR    Valid    Valid    Move r16 to r/m16.
 89 /r               MOV r/m32,r32         MR    Valid    Valid    Move r32 to r/m32.
 REX.W + 89 /r       MOV r/m64,r64         MR    Valid    N.E.     Move r64 to r/m64.
 8A /r               MOV r8,r/m8           RM    Valid    Valid    Move r/m8 to r8.
 REX + 8A /r         MOV r8***,r/m8***     RM    Valid    N.E.     Move r/m8 to r8.
 8B /r               MOV r16,r/m16         RM    Valid    Valid    Move r/m16 to r16.
 8B /r               MOV r32,r/m32         RM    Valid    Valid    Move r/m32 to r32.
 REX.W + 8B /r       MOV r64,r/m64         RM    Valid    N.E.     Move r/m64 to r64.
 8C /r               MOV r/m16,Sreg**      MR    Valid    Valid    Move segment register to r/m16.
 REX.W + 8C /r       MOV r/m64,Sreg**      MR    Valid    Valid    Move zero extended 16-bit segment register
                                                                   to r/m64.
 8E /r               MOV Sreg,r/m16**      RM    Valid    Valid    Move r/m16 to segment register.
 REX.W + 8E /r       MOV Sreg,r/m64**      RM    Valid    Valid    Move lower 16 bits of r/m64 to segment
                                                                   register.
 A0                  MOV AL,moffs8*        FD    Valid    Valid    Move byte at (seg:offset) to AL.
 REX.W + A0          MOV AL,moffs8*        FD    Valid    N.E.     Move byte at (offset) to AL.
 A1                  MOV AX,moffs16*       FD    Valid    Valid    Move word at (seg:offset) to AX.
 A1                  MOV EAX,moffs32*      FD    Valid    Valid    Move doubleword at (seg:offset) to EAX.
 REX.W + A1          MOV RAX,moffs64*      FD    Valid    N.E.     Move quadword at (offset) to RAX.
 A2                  MOV moffs8,AL         TD    Valid    Valid    Move AL to (seg:offset).
 REX.W + A2          MOV moffs8***,AL      TD    Valid    N.E.     Move AL to (offset).
 A3                  MOV moffs16*,AX       TD    Valid    Valid    Move AX to (seg:offset).
 A3                  MOV moffs32*,EAX      TD    Valid    Valid    Move EAX to (seg:offset).
 REX.W + A3          MOV moffs64*,RAX      TD    Valid    N.E.     Move RAX to (offset).
 B0+ rb ib           MOV r8, imm8          OI    Valid    Valid    Move imm8 to r8.
                            ***
 REX + B0+ rb ib     MOV r8       , imm8   OI    Valid    N.E.     Move imm8 to r8.
 B8+ rw iw           MOV r16, imm16        OI    Valid    Valid    Move imm16 to r16.
 B8+ rd id           MOV r32, imm32        OI    Valid    Valid    Move imm32 to r32.
 REX.W + B8+ rd io   MOV r64, imm64        OI    Valid    N.E.     Move imm64 to r64.
 C6 /0 ib            MOV r/m8, imm8        MI    Valid    Valid    Move imm8 to r/m8.
 REX + C6 /0 ib      MOV r/m8***, imm8     MI    Valid    N.E.     Move imm8 to r/m8.
 C7 /0 iw            MOV r/m16, imm16      MI    Valid    Valid    Move imm16 to r/m16.
 C7 /0 id            MOV r/m32, imm32      MI    Valid    Valid    Move imm32 to r/m32.
 REX.W + C7 /0 id    MOV r/m64, imm32      MI    Valid    N.E.     Move imm32 sign extended to 64-bits to
                                                                   r/m64.





 NOTES:
 * The moffs8, moffs16, moffs32 and moffs64 operands specify a simple offset relative to the segment base, where 8, 16, 32 and 64
    refer to the size of the data. The address-size attribute of the instruction determines the size of the offset, either 16, 32 or 64
    bits.
 ** In 32-bit mode, the assembler may insert the 16-bit operand-size prefix with this instruction (see the following "Description" sec-
    tion for further information).
 ***In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.




                                                  Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                       Operand 3                      Operand 4
    MR             ModRM:r/m (w)                   ModRM:reg (r)                         NA                             NA
    RM             ModRM:reg (w)                   ModRM:r/m (r)                         NA                             NA
    FD            AL/AX/EAX/RAX                         Moffs                            NA                             NA
    TD                Moffs (w)                   AL/AX/EAX/RAX                          NA                             NA
     OI            opcode + rd (w)                imm8/16/32/64                          NA                             NA
     MI            ModRM:r/m (w)                  imm8/16/32/64                          NA                             NA


Description
Copies the second operand (source operand) to the first operand (destination operand). The source operand can be
an immediate value, general-purpose register, segment register, or memory location; the destination register can
be a general-purpose register, segment register, or memory location. Both operands must be the same size, which
can be a byte, a word, a doubleword, or a quadword.
The MOV instruction cannot be used to load the CS register. Attempting to do so results in an invalid opcode excep-
tion (#UD). To load the CS register, use the far JMP, CALL, or RET instruction.
If the destination operand is a segment register (DS, ES, FS, GS, or SS), the source operand must be a valid
segment selector. In protected mode, moving a segment selector into a segment register automatically causes the
segment descriptor information associated with that segment selector to be loaded into the hidden (shadow) part
of the segment register. While loading this information, the segment selector and segment descriptor information
is validated (see the "Operation" algorithm below). The segment descriptor data is obtained from the GDT or LDT
entry for the specified segment selector.
A NULL segment selector (values 0000-0003) can be loaded into the DS, ES, FS, and GS registers without causing
a protection exception. However, any subsequent attempt to reference a segment whose corresponding segment
register is loaded with a NULL value causes a general protection exception (#GP) and no memory reference occurs.
Loading the SS register with a MOV instruction inhibits all interrupts until after the execution of the next instruc-
tion. This operation allows a stack pointer to be loaded into the ESP register with the next instruction (MOV ESP,
stack-pointer value) before an interrupt occurs1. Be aware that the LSS instruction offers a more efficient
method of loading the SS and ESP registers.
When executing MOV Reg, Sreg, the processor copies the content of Sreg to the 16 least significant bits of the
general-purpose register. The upper bits of the destination register are zero for most IA-32 processors (Pentium


1. If a code instruction breakpoint (for debug) is placed on an instruction located immediately after a MOV SS instruction, the break-
   point may not be triggered. However, in a sequence of instructions that load the SS register, only the first instruction in the
   sequence is guaranteed to delay an interrupt.
   In the following sequence, interrupts may be recognized before MOV ESP, EBP executes:
   MOV SS, EDX
   MOV SS, EAX
   MOV ESP, EBP





Pro processors and later) and all Intel 64 processors, with the exception that bits 31:16 are undefined for Intel
Quark X1000 processors, Pentium and earlier processors.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.

Operation
DEST <- SRC;
Loading a segment register while in protected mode results in special checks and actions, as described in the
following listing. These checks are performed on the segment selector and the segment descriptor to which it
points.

IF SS is loaded
    THEN
          IF segment selector is NULL
               THEN #GP(0); FI;
          IF segment selector index is outside descriptor table limits
          or segment selector's RPL != CPL
          or segment is not a writable data segment
          or DPL != CPL
               THEN #GP(selector); FI;
          IF segment not marked present
               THEN #SS(selector);
               ELSE
                   SS <- segment selector;
                   SS <- segment descriptor; FI;
FI;

IF DS, ES, FS, or GS is loaded with non-NULL selector
THEN
    IF segment selector index is outside descriptor table limits
    or segment is not a data or readable code segment
    or ((segment is a data or nonconforming code segment)
    or ((RPL > DPL) and (CPL > DPL))
          THEN #GP(selector); FI;
    IF segment not marked present
          THEN #NP(selector);
          ELSE
               SegmentRegister <- segment selector;
               SegmentRegister <- segment descriptor; FI;
FI;

IF DS, ES, FS, or GS is loaded with NULL selector
    THEN
         SegmentRegister <- segment selector;
         SegmentRegister <- segment descriptor;
FI;

Flags Affected
None





Protected Mode Exceptions
#GP(0)              If attempt is made to load SS register with NULL segment selector.
                    If the destination operand is in a non-writable segment.
                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#GP(selector)       If segment selector index is outside descriptor table limits.
                    If the SS register is being loaded and the segment selector's RPL and the segment descriptor's
                    DPL are not equal to the CPL.
                    If the SS register is being loaded and the segment pointed to is a
                    non-writable data segment.
                    If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
                    readable code segment.
                    If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
                    nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#SS(selector)       If the SS register is being loaded and the segment pointed to is marked not present.
#NP                 If the DS, ES, FS, or GS register is being loaded and the segment pointed to is marked not
                    present.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If attempt is made to load the CS register.
                    If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#UD                 If attempt is made to load the CS register.
                    If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If attempt is made to load the CS register.
                    If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#GP(0)             If the memory address is in a non-canonical form.
                   If an attempt is made to load SS register with NULL segment selector when CPL = 3.
                   If an attempt is made to load SS register with NULL segment selector when CPL < 3 and CPL
                  != RPL.
#GP(selector)      If segment selector index is outside descriptor table limits.
                   If the memory access to the descriptor table is non-canonical.
                  If the SS register is being loaded and the segment selector's RPL and the segment descriptor's
                  DPL are not equal to the CPL.
                   If the SS register is being loaded and the segment pointed to is a nonwritable data segment.
                  If the DS, ES, FS, or GS register is being loaded and the segment pointed to is not a data or
                  readable code segment.
                  If the DS, ES, FS, or GS register is being loaded and the segment pointed to is a data or
                  nonconforming code segment, but both the RPL and the CPL are greater than the DPL.
#SS(0)             If the stack address is in a non-canonical form.
#SS(selector)      If the SS register is being loaded and the segment pointed to is marked not present.
#PF(fault-code)    If a page fault occurs.
#AC(0)            If alignment checking is enabled and an unaligned memory reference is made while the
                  current privilege level is 3.
#UD                If attempt is made to load the CS register.
                   If the LOCK prefix is used.






platform: x86_64
mnem: MOV
description:
MOV-Move to/from Control Registers
Opcode/                                                 Op/    64-Bit       Compat/ Description
Instruction                                             En     Mode         Leg Mode
0F 20/r                                                 MR     N.E.         Valid        Move control register to r32.
MOV r32, CR0-CR7
0F 20/r                                                 MR     Valid        N.E.         Move extended control register to r64.
MOV r64, CR0-CR7
REX.R + 0F 20 /0                                        MR     Valid        N.E.         Move extended CR8 to r64.1
MOV r64, CR8
0F 22 /r                                                RM     N.E.         Valid        Move r32 to control register.
MOV CR0-CR7, r32
0F 22 /r                                                RM     Valid        N.E.         Move r64 to extended control register.
MOV CR0-CR7, r64
REX.R + 0F 22 /0                                        RM     Valid        N.E.         Move r64 to extended CR8.1
MOV CR8, r64
NOTE:
1. MOV CR* instructions, except for MOV CR8, are serializing instructions. MOV CR8 is not
   architecturally defined as a serializing instruction. For more information, see Chapter 8 in Intel 64 and IA-32 Architectures Soft-
   ware Developer's Manual, Volume 3A.



                                                  Instruction Operand Encoding
   Op/En             Operand 1                      Operand 2                       Operand 3                      Operand 4
    MR             ModRM:r/m (w)                   ModRM:reg (r)                       NA                                NA
    RM             ModRM:reg (w)                   ModRM:r/m (r)                       NA                                NA


Description
Moves the contents of a control register (CR0, CR2, CR3, CR4, or CR8) to a general-purpose register or the
contents of a general purpose register to a control register. The operand size for these instructions is always 32 bits
in non-64-bit modes, regardless of the operand-size attribute. (See "Control Registers" in Chapter 2 of the Intel
64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for a detailed description of the flags and
fields in the control registers.) This instruction can be executed only when the current privilege level is 0.
At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read.
The 2 bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.
Attempts to reference CR1, CR5, CR6, CR7, and CR9-CR15 result in undefined opcode (#UD) exceptions.
When loading control registers, programs should not attempt to change the reserved bits; that is, always set
reserved bits to the value previously read. An attempt to change CR4's reserved bits will cause a general protection
fault. Reserved bits in CR0 and CR3 remain clear after any load of those registers; attempts to set them have no
impact. On Pentium 4, Intel Xeon and P6 family processors, CR0.ET remains set after any load of CR0; attempts to
clear this bit have no impact.
In certain cases, these instructions have the side effect of invalidating entries in the TLBs and the paging-structure
caches. See Section 4.10.4.1, "Operations that Invalidate TLBs and Paging-Structure Caches," in the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A for details.
The following side effects are implementation-specific for the Pentium 4, Intel Xeon, and P6 processor family: when
modifying PE or PG in register CR0, or PSE or PAE in register CR4, all TLB entries are flushed, including global
entries. Software should not depend on this functionality in all Intel 64 or IA-32 processors.
In 64-bit mode, the instruction's default operation size is 64 bits. The REX.R prefix must be used to access CR8. Use
of REX.B permits access to additional registers (R8-R15). Use of the REX.W prefix or 66H prefix is ignored. Use of




the REX.R prefix to specify a register other than CR8 causes an invalid-opcode exception. See the summary chart
at the beginning of this section for encoding data and limits.
If CR4.PCIDE = 1, bit 63 of the source operand to MOV to CR3 determines whether the instruction invalidates
entries in the TLBs and the paging-structure caches (see Section 4.10.4.1, "Operations that Invalidate TLBs and
Paging-Structure Caches," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A). The
instruction does not modify bit 63 of CR3, which is reserved and always 0.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
DEST <- SRC;

Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.

Protected Mode Exceptions
#GP(0)                  If the current privilege level is not 0.
                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
                        when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
                        If an attempt is made to write a 1 to any reserved bit in CR4.
                        If an attempt is made to write 1 to CR4.PCIDE.
                        If any of the reserved bits are set in the page-directory pointers table (PDPT) and the loading
                        of a control register causes the PDPT to be loaded into the processor.
#UD                     If the LOCK prefix is used.
                        If an attempt is made to access CR1, CR5, CR6, or CR7.

Real-Address Mode Exceptions
#GP                     If an attempt is made to write a 1 to any reserved bit in CR4.
                        If an attempt is made to write 1 to CR4.PCIDE.
                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
                        when the PE flag is set to 0).
#UD                     If the LOCK prefix is used.
                        If an attempt is made to access CR1, CR5, CR6, or CR7.

Virtual-8086 Mode Exceptions
#GP(0)                  These instructions cannot be executed in virtual-8086 mode.

Compatibility Mode Exceptions
#GP(0)                  If the current privilege level is not 0.
                        If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
                        when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
                        If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.
                        If an attempt is made to clear CR0.PG[bit 31] while CR4.PCIDE = 1.
                        If an attempt is made to write a 1 to any reserved bit in CR3.
                        If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].
#UD                     If the LOCK prefix is used.
                        If an attempt is made to access CR1, CR5, CR6, or CR7.




64-Bit Mode Exceptions
#GP(0)              If the current privilege level is not 0.
                    If an attempt is made to write invalid bit combinations in CR0 (such as setting the PG flag to 1
                    when the PE flag is set to 0, or setting the CD flag to 0 when the NW flag is set to 1).
                    If an attempt is made to change CR4.PCIDE from 0 to 1 while CR3[11:0] != 000H.
                    If an attempt is made to clear CR0.PG[bit 31].
                    If an attempt is made to write a 1 to any reserved bit in CR4.
                    If an attempt is made to write a 1 to any reserved bit in CR8.
                    If an attempt is made to write a 1 to any reserved bit in CR3.
                    If an attempt is made to leave IA-32e mode by clearing CR4.PAE[bit 5].
#UD                 If the LOCK prefix is used.
                    If an attempt is made to access CR1, CR5, CR6, or CR7.
                    If the REX.R prefix is used to specify a register other than CR8.






platform: x86_64
mnem: MOV
description:
MOV-Move to/from Debug Registers
Opcode/                                             Op/   64-Bit   Compat/ Description
Instruction                                         En    Mode     Leg Mode
0F 21/r                                             MR    N.E.     Valid      Move debug register to r32.
MOV r32, DR0-DR7
0F 21/r                                             MR    Valid    N.E.       Move extended debug register to r64.
MOV r64, DR0-DR7
0F 23 /r                                            RM    N.E.     Valid      Move r32 to debug register.
MOV DR0-DR7, r32
0F 23 /r                                            RM    Valid    N.E.       Move r64 to extended debug register.
MOV DR0-DR7, r64



                                               Instruction Operand Encoding
      Op/En          Operand 1                   Operand 2                 Operand 3                   Operand 4
       MR          ModRM:r/m (w)                ModRM:reg (r)                 NA                            NA
       RM          ModRM:reg (w)                ModRM:r/m (r)                 NA                            NA


Description
Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose
register or vice versa. The operand size for these instructions is always 32 bits in non-64-bit modes, regardless of
the operand-size attribute. (See Section 17.2, "Debug Registers", of the Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 3A, for a detailed description of the flags and fields in the debug registers.)
The instructions must be executed at privilege level 0 or in real-address mode.
When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a
manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer
to DR6 and DR7, respectively. When the DE flag in CR4 is set, attempts to reference DR4 and DR5 result in an
undefined opcode (#UD) exception. (The CR4 register was added to the IA-32 Architecture beginning with the
Pentium processor.)
At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read.
The two bits in the mod field are ignored. The r/m field specifies the general-purpose register loaded or read.
In 64-bit mode, the instruction's default operation size is 64 bits. Use of the REX.B prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W or 66H prefix is ignored. Use of the REX.R prefix causes an invalid-
opcode exception. See the summary chart at the beginning of this section for encoding data and limits.

Operation
IF ((DE = 1) and (SRC or DEST = DR4 or DR5))
     THEN
         #UD;
     ELSE
         DEST <- SRC;

FI;

Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are undefined.





Protected Mode Exceptions
#GP(0)              If the current privilege level is not 0.
#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
                    DR5.
                    If the LOCK prefix is used.
#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.

Real-Address Mode Exceptions
#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
                    DR5.
                    If the LOCK prefix is used.
#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.

Virtual-8086 Mode Exceptions
#GP(0)              The debug registers cannot be loaded or read when in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)              If the current privilege level is not 0.
                    If an attempt is made to write a 1 to any of bits 63:32 in DR6.
                    If an attempt is made to write a 1 to any of bits 63:32 in DR7.
#UD                 If CR4.DE[bit 3] = 1 (debug extensions) and a MOV instruction is executed involving DR4 or
                    DR5.
                    If the LOCK prefix is used.
                    If the REX.R prefix is used.
#DB                 If any debug register is accessed while the DR7.GD[bit 13] = 1.






platform: x86_64
mnem: MOVAPD
description:
MOVAPD-Move Aligned Packed Double-Precision Floating-Point Values
 Opcode/                                      Op/En       64/32        CPUID      Description
 Instruction                                              bit Mode     Feature
                                                          Support      Flag
 66 0F 28 /r                                  RM          V/V          SSE2       Move aligned packed double-precision floating-
 MOVAPD xmm1, xmm2/m128                                                           point values from xmm2/mem to xmm1.
 66 0F 29 /r                                  MR          V/V          SSE2       Move aligned packed double-precision floating-
 MOVAPD xmm2/m128, xmm1                                                           point values from xmm1 to xmm2/mem.
 VEX.128.66.0F.WIG 28 /r                      RM          V/V          AVX        Move aligned packed double-precision floating-
 VMOVAPD xmm1, xmm2/m128                                                          point values from xmm2/mem to xmm1.
 VEX.128.66.0F.WIG 29 /r                      MR          V/V          AVX        Move aligned packed double-precision floating-
 VMOVAPD xmm2/m128, xmm1                                                          point values from xmm1 to xmm2/mem.
 VEX.256.66.0F.WIG 28 /r                      RM          V/V          AVX        Move aligned packed double-precision floating-
 VMOVAPD ymm1, ymm2/m256                                                          point values from ymm2/mem to ymm1.
 VEX.256.66.0F.WIG 29 /r                      MR          V/V          AVX        Move aligned packed double-precision floating-
 VMOVAPD ymm2/m256, ymm1                                                          point values from ymm1 to ymm2/mem.
 EVEX.128.66.0F.W1 28 /r                      FVM-RM      V/V          AVX512VL   Move aligned packed double-precision floating-
 VMOVAPD xmm1 {k1}{z}, xmm2/m128                                       AVX512F    point values from xmm2/m128 to xmm1 using
                                                                                  writemask k1.
 EVEX.256.66.0F.W1 28 /r                      FVM-RM      V/V          AVX512VL   Move aligned packed double-precision floating-
 VMOVAPD ymm1 {k1}{z}, ymm2/m256                                       AVX512F    point values from ymm2/m256 to ymm1 using
                                                                                  writemask k1.
 EVEX.512.66.0F.W1 28 /r                      FVM-RM      V/V          AVX512F    Move aligned packed double-precision floating-
 VMOVAPD zmm1 {k1}{z}, zmm2/m512                                                  point values from zmm2/m512 to zmm1 using
                                                                                  writemask k1.
 EVEX.128.66.0F.W1 29 /r                      FVM-MR      V/V          AVX512VL   Move aligned packed double-precision floating-
 VMOVAPD xmm2/m128 {k1}{z}, xmm1                                       AVX512F    point values from xmm1 to xmm2/m128 using
                                                                                  writemask k1.
 EVEX.256.66.0F.W1 29 /r                      FVM-MR      V/V          AVX512VL   Move aligned packed double-precision floating-
 VMOVAPD ymm2/m256 {k1}{z}, ymm1                                       AVX512F    point values from ymm1 to ymm2/m256 using
                                                                                  writemask k1.
 EVEX.512.66.0F.W1 29 /r                      FVM-MR      V/V          AVX512F    Move aligned packed double-precision floating-
 VMOVAPD zmm2/m512 {k1}{z}, zmm1                                                  point values from zmm1 to zmm2/m512 using
                                                                                  writemask k1.



                                                   Instruction Operand Encoding
      Op/En                  Operand 1                     Operand 2               Operand 3                   Operand 4
        RM                ModRM:reg (w)                  ModRM:r/m (r)                 NA                          NA
        MR                ModRM:r/m (w)                  ModRM:reg (r)                 NA                          NA
     FVM-RM               ModRM:reg (w)                  ModRM:r/m (r)                 NA                          NA
     FVM-MR               ModRM:r/m (w)                  ModRM:reg (r)                 NA                          NA





Description
Moves 2, 4 or 8 double-precision floating-point values from the source operand (second operand) to the destination
operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit, 256-
bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit or
512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit
versions), 32-byte (256-bit version) or 64-byte (EVEX.512 encoded version) boundary or a general-protection
exception (#GP) will be generated. For EVEX encoded versions, the operand must be aligned to the size of the
memory operand. To move double-precision floating-point values to and from unaligned memory locations, use the
VMOVUPD instruction.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float64
memory location, to store the contents of a ZMM register into a 512-bit float64 memory location, or to move data
between two ZMM registers. When the source or destination operand is a memory operand, the operand must be
aligned on a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision
floating-point values to and from unaligned memory locations, use the VMOVUPD instruction.
VEX.256 and EVEX.256 encoded versions:
Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte
boundary or a general-protection exception (#GP) will be generated. To move double-precision floating-point
values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit versions:
Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-
point values to and from unaligned memory locations, use the VMOVUPD instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register destination are zeroed.

Operation
VMOVAPD (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VMOVAPD (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i]<- SRC[i+63:i]
         ELSE
         ELSE *DEST[i+63:i] remains unchanged*           ; merging-masking

   FI;
ENDFOR;

VMOVAPD (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVAPD (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVAPD (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]

VMOVAPD (VEX.128 encoded version, load - and register copy)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

MOVAPD (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)

(V)MOVAPD (128-bit store-form version)
DEST[127:0] <- SRC[127:0]





Intel C/C++ Compiler Intrinsic Equivalent
VMOVAPD __m512d _mm512_load_pd( void * m);
VMOVAPD __m512d _mm512_mask_load_pd(__m512d s, __mmask8 k, void * m);
VMOVAPD __m512d _mm512_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm512_store_pd( void * d, __m512d a);
VMOVAPD void _mm512_mask_store_pd( void * d, __mmask8 k, __m512d a);
VMOVAPD __m256d _mm256_mask_load_pd(__m256d s, __mmask8 k, void * m);
VMOVAPD __m256d _mm256_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm256_mask_store_pd( void * d, __mmask8 k, __m256d a);
VMOVAPD __m128d _mm_mask_load_pd(__m128d s, __mmask8 k, void * m);
VMOVAPD __m128d _mm_maskz_load_pd( __mmask8 k, void * m);
VMOVAPD void _mm_mask_store_pd( void * d, __mmask8 k, __m128d a);
MOVAPD __m256d _mm256_load_pd (double * p);
MOVAPD void _mm256_store_pd(double * p, __m256d a);
MOVAPD __m128d _mm_load_pd (double * p);
MOVAPD void _mm_store_pd(double * p, __m128d a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1.
#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVAPS
description:
MOVAPS-Move Aligned Packed Single-Precision Floating-Point Values
 Opcode/                                     Op/En       64/32        CPUID      Description
 Instruction                                             bit Mode     Feature
                                                         Support      Flag
 0F 28 /r                                    RM          V/V          SSE        Move aligned packed single-precision floating-point
 MOVAPS xmm1, xmm2/m128                                                          values from xmm2/mem to xmm1.
 0F 29 /r                                    MR          V/V          SSE        Move aligned packed single-precision floating-point
 MOVAPS xmm2/m128, xmm1                                                          values from xmm1 to xmm2/mem.
 VEX.128.0F.WIG 28 /r                        RM          V/V          AVX        Move aligned packed single-precision floating-point
 VMOVAPS xmm1, xmm2/m128                                                         values from xmm2/mem to xmm1.
 VEX.128.0F.WIG 29 /r                        MR          V/V          AVX        Move aligned packed single-precision floating-point
 VMOVAPS xmm2/m128, xmm1                                                         values from xmm1 to xmm2/mem.
 VEX.256.0F.WIG 28 /r                        RM          V/V          AVX        Move aligned packed single-precision floating-point
 VMOVAPS ymm1, ymm2/m256                                                         values from ymm2/mem to ymm1.
 VEX.256.0F.WIG 29 /r                        MR          V/V          AVX        Move aligned packed single-precision floating-point
 VMOVAPS ymm2/m256, ymm1                                                         values from ymm1 to ymm2/mem.
 EVEX.128.0F.W0 28 /r                        FVM-RM      V/V          AVX512VL   Move aligned packed single-precision floating-point
 VMOVAPS xmm1 {k1}{z}, xmm2/m128                                      AVX512F    values from xmm2/m128 to xmm1 using
                                                                                 writemask k1.
 EVEX.256.0F.W0 28 /r                        FVM-RM      V/V          AVX512VL   Move aligned packed single-precision floating-point
 VMOVAPS ymm1 {k1}{z}, ymm2/m256                                      AVX512F    values from ymm2/m256 to ymm1 using
                                                                                 writemask k1.
 EVEX.512.0F.W0 28 /r                        FVM-RM      V/V          AVX512F    Move aligned packed single-precision floating-point
 VMOVAPS zmm1 {k1}{z}, zmm2/m512                                                 values from zmm2/m512 to zmm1 using
                                                                                 writemask k1.
 EVEX.128.0F.W0 29 /r                        FVM-MR      V/V          AVX512VL   Move aligned packed single-precision floating-point
 VMOVAPS xmm2/m128 {k1}{z}, xmm1                                      AVX512F    values from xmm1 to xmm2/m128 using
                                                                                 writemask k1.
 EVEX.256.0F.W0 29 /r                        FVM-MR      V/V          AVX512VL   Move aligned packed single-precision floating-point
 VMOVAPS ymm2/m256 {k1}{z}, ymm1                                      AVX512F    values from ymm1 to ymm2/m256 using
                                                                                 writemask k1.
 EVEX.512.0F.W0 29 /r                        FVM-MR      V/V          AVX512F    Move aligned packed single-precision floating-point
 VMOVAPS zmm2/m512 {k1}{z}, zmm1                                                 values from zmm1 to zmm2/m512 using
                                                                                 writemask k1.



                                                     Instruction Operand Encoding
        Op/En                   Operand 1                      Operand 2             Operand 3                   Operand 4
          RM                  ModRM:reg (w)                 ModRM:r/m (r)                NA                          NA
          MR                  ModRM:r/m (w)                 ModRM:reg (r)                NA                          NA
       FVM-RM                 ModRM:reg (w)                 ModRM:r/m (r)                NA                          NA
       FVM-MR                 ModRM:r/m (w)                 ModRM:reg (r)                NA                          NA

Description
Moves 4, 8 or 16 single-precision floating-point values from the source operand (second operand) to the destina-
tion operand (first operand). This instruction can be used to load an XMM, YMM or ZMM register from an 128-bit,
256-bit or 512-bit memory location, to store the contents of an XMM, YMM or ZMM register into a 128-bit, 256-bit
or 512-bit memory location, or to move data between two XMM, two YMM or two ZMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte (128-bit
version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512 encoded version) boundary or a general-
protection exception (#GP) will be generated. For EVEX.512 encoded versions, the operand must be aligned to the
size of the memory operand. To move single-precision floating-point values to and from unaligned memory loca-
tions, use the VMOVUPS instruction.



Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32
memory location, to store the contents of a ZMM register into a float32 memory location, or to move data between
two ZMM registers. When the source or destination operand is a memory operand, the operand must be aligned on
a 64-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-
point values to and from unaligned memory locations, use the VMOVUPS instruction.
VEX.256 and EVEX.256 encoded version:
Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte
boundary or a general-protection exception (#GP) will be generated.
128-bit versions:
Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers. When the source or destination operand is a memory operand, the operand must be aligned on a
16-byte boundary or a general-protection exception (#GP) will be generated. To move single-precision floating-
point values to and from unaligned memory locations, use the VMOVUPS instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
(E)VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination ZMM register are zeroed.

Operation
VMOVAPS (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVAPS (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i]<-
               SRC[i+31:i]
         ELSE *DEST[i+31:i] remains unchanged*        ; merging-masking
    FI;
ENDFOR;





VMOVAPS (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVAPS (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVAPS (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]

VMOVAPS (VEX.128 encoded version, load - and register copy)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

MOVAPS (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)

(V)MOVAPS (128-bit store-form version)
DEST[127:0] <- SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVAPS __m512 _mm512_load_ps( void * m);
VMOVAPS __m512 _mm512_mask_load_ps(__m512 s, __mmask16 k, void * m);
VMOVAPS __m512 _mm512_maskz_load_ps( __mmask16 k, void * m);
VMOVAPS void _mm512_store_ps( void * d, __m512 a);
VMOVAPS void _mm512_mask_store_ps( void * d, __mmask16 k, __m512 a);
VMOVAPS __m256 _mm256_mask_load_ps(__m256 a, __mmask8 k, void * s);
VMOVAPS __m256 _mm256_maskz_load_ps( __mmask8 k, void * s);
VMOVAPS void _mm256_mask_store_ps( void * d, __mmask8 k, __m256 a);
VMOVAPS __m128 _mm_mask_load_ps(__m128 a, __mmask8 k, void * s);
VMOVAPS __m128 _mm_maskz_load_ps( __mmask8 k, void * s);
VMOVAPS void _mm_mask_store_ps( void * d, __mmask8 k, __m128 a);
MOVAPS __m256 _mm256_load_ps (float * p);
MOVAPS void _mm256_store_ps(float * p, __m256 a);
MOVAPS __m128 _mm_load_ps (float * p);
MOVAPS void _mm_store_ps(float * p, __m128 a);

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally
#UD                 If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E1.






platform: x86_64
mnem: MOVBE
description:
MOVBE-Move Data After Swapping Bytes
 Opcode                   Instruction           Op/   64-Bit     Compat/ Description
                                                En    Mode       Leg Mode
 0F 38 F0 /r              MOVBE r16, m16        RM    Valid      Valid      Reverse byte order in m16 and move to r16.
 0F 38 F0 /r              MOVBE r32, m32        RM    Valid      Valid      Reverse byte order in m32 and move to r32.
 REX.W + 0F 38 F0 /r      MOVBE r64, m64        RM    Valid      N.E.       Reverse byte order in m64 and move to r64.
 0F 38 F1 /r              MOVBE m16, r16        MR    Valid      Valid      Reverse byte order in r16 and move to m16.
 0F 38 F1 /r              MOVBE m32, r32        MR    Valid      Valid      Reverse byte order in r32 and move to m32.
 REX.W + 0F 38 F1 /r      MOVBE m64, r64        MR    Valid      N.E.       Reverse byte order in r64 and move to m64.



                                           Instruction Operand Encoding
      Op/En            Operand 1              Operand 2                  Operand 3                   Operand 4
       RM          ModRM:reg (w)            ModRM:r/m (r)                   NA                          NA
       MR          ModRM:r/m (w)            ModRM:reg (r)                   NA                          NA


Description
Performs a byte swap operation on the data copied from the second operand (source operand) and store the result
in the first operand (destination operand). The source operand can be a general-purpose register, or memory loca-
tion; the destination register can be a general-purpose register, or a memory location; however, both operands can
not be registers, and only one operand can be a memory location. Both operands must be the same size, which can
be a word, a doubleword or quadword.
The MOVBE instruction is provided for swapping the bytes on a read from memory or on a write to memory; thus
providing support for converting little-endian values to big-endian format and vice versa.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.

Operation
TEMP <- SRC

IF ( OperandSize = 16)
     THEN
         DEST[7:0] <- TEMP[15:8];
         DEST[15:8] <- TEMP[7:0];
     ELES IF ( OperandSize = 32)
         DEST[7:0] <- TEMP[31:24];
         DEST[15:8] <- TEMP[23:16];
         DEST[23:16] <- TEMP[15:8];
         DEST[31:23] <- TEMP[7:0];
     ELSE IF ( OperandSize = 64)
         DEST[7:0] <- TEMP[63:56];
         DEST[15:8] <- TEMP[55:48];
         DEST[23:16] <- TEMP[47:40];
         DEST[31:24] <- TEMP[39:32];
         DEST[39:32] <- TEMP[31:24];
         DEST[47:40] <- TEMP[23:16];
         DEST[55:48] <- TEMP[15:8];
         DEST[63:56] <- TEMP[7:0];

FI;



Flags Affected
None

Protected Mode Exceptions
#GP(0)              If the destination operand is in a non-writable segment.
                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                    If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.
                    If the LOCK prefix is used.
                    If REP (F3H) prefix is used.

Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.
                    If the LOCK prefix is used.
                    If REP (F3H) prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.
                    If the LOCK prefix is used.
                    If REP (F3H) prefix is used.
                    If REPNE (F2H) prefix is used and CPUID.01H:ECX.SSE4_2[bit 20] = 0.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
#SS(0)              If the stack address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If CPUID.01H:ECX.MOVBE[bit 22] = 0.
                    If the LOCK prefix is used.
                    If REP (F3H) prefix is used.






platform: x86_64
mnem: MOVD
description:
MOVD/MOVQ-Move Doubleword/Move Quadword
Opcode/                               Op/ En   64/32-bit CPUID     Description
Instruction                                    Mode      Feature
                                                         Flag
0F 6E /r                              RM       V/V       MMX       Move doubleword from r/m32 to mm.
MOVD mm, r/m32
REX.W + 0F 6E /r                      RM       V/N.E.    MMX       Move quadword from r/m64 to mm.
MOVQ mm, r/m64
0F 7E /r                              MR       V/V       MMX       Move doubleword from mm to r/m32.
MOVD r/m32, mm
REX.W + 0F 7E /r                      MR       V/N.E.    MMX       Move quadword from mm to r/m64.
MOVQ r/m64, mm
66 0F 6E /r                           RM       V/V       SSE2      Move doubleword from r/m32 to xmm.
MOVD xmm, r/m32
66 REX.W 0F 6E /r                     RM       V/N.E.    SSE2      Move quadword from r/m64 to xmm.
MOVQ xmm, r/m64
66 0F 7E /r                           MR       V/V       SSE2      Move doubleword from xmm register to r/m32.
MOVD r/m32, xmm
 66 REX.W 0F 7E /r                    MR       V/N.E.    SSE2      Move quadword from xmm register to r/m64.
MOVQ r/m64, xmm
VEX.128.66.0F.W0 6E /                 RM       V/V       AVX       Move doubleword from r/m32 to xmm1.
VMOVD xmm1, r32/m32
VEX.128.66.0F.W1 6E /r                RM       V/N.E1.   AVX       Move quadword from r/m64 to xmm1.
VMOVQ xmm1, r64/m64
VEX.128.66.0F.W0 7E /r                MR       V/V       AVX       Move doubleword from xmm1 register to r/m32.
VMOVD r32/m32, xmm1
VEX.128.66.0F.W1 7E /r                MR       V/N.E1.   AVX       Move quadword from xmm1 register to r/m64.
VMOVQ r64/m64, xmm1
EVEX.128.66.0F.W0 6E /r               T1S-RM V/V         AVX512F   Move doubleword from r/m32 to xmm1.
VMOVD xmm1, r32/m32
EVEX.128.66.0F.W1 6E /r               T1S-RM V/N.E.1     AVX512F   Move quadword from r/m64 to xmm1.
VMOVQ xmm1, r64/m64
EVEX.128.66.0F.W0 7E /r               T1S-MR V/V         AVX512F   Move doubleword from xmm1 register to r/m32.
VMOVD r32/m32, xmm1
EVEX.128.66.0F.W1 7E /r               T1S-MR V/N.E.1     AVX512F   Move quadword from xmm1 register to r/m64.
VMOVQ r64/m64, xmm1

NOTES:
1. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 ver-
  sion is used.





                                           Instruction Operand Encoding
     Op/En              Operand 1                  Operand 2                 Operand 3               Operand 4
       RM             ModRM:reg (w)               ModRM:r/m (r)                 NA                      NA
       MR             ModRM:r/m (w)               ModRM:reg (r)                 NA                      NA
    T1S-RM            ModRM:reg (w)               ModRM:r/m (r)                 NA                      NA
    T1S-MR            ModRM:r/m (w)               ModRM:reg (r)                 NA                      NA


Description
Copies a doubleword from the source operand (second operand) to the destination operand (first operand). The
source and destination operands can be general-purpose registers, MMX technology registers, XMM registers, or
32-bit memory locations. This instruction can be used to move a doubleword to and from the low doubleword of an
MMX technology register and a general-purpose register or a 32-bit memory location, or to and from the low
doubleword of an XMM register and a general-purpose register or a 32-bit memory location. The instruction cannot
be used to transfer data between MMX technology registers, between XMM registers, between general-purpose
registers, or between memory locations.
When the destination operand is an MMX technology register, the source operand is written to the low doubleword
of the register, and the register is zero-extended to 64 bits. When the destination operand is an XMM register, the
source operand is written to the low doubleword of the register, and the register is zero-extended to 128 bits.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.
MOVD/Q with XMM destination:
Moves a dword/qword integer from the source operand and stores it in the low 32/64-bits of the destination XMM
register. The upper bits of the destination are zeroed. The source operand can be a 32/64-bit register or 32/64-bit
memory location.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding YMM destination register remain
unchanged. Qword operation requires the use of REX.W=1.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires
the use of VEX.W=1.
EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. Qword operation requires
the use of EVEX.W=1.


MOVD/Q with 32/64 reg/mem destination:
Stores the low dword/qword of the source XMM register to 32/64-bit memory location or general-purpose register.
Qword operation requires the use of REX.W=1, VEX.W=1, or EVEX.W=1.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
If VMOVD or VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.

Operation
MOVD (when destination operand is MMX technology register)
  DEST[31:0] <- SRC;
  DEST[63:32] <- 00000000H;

MOVD (when destination operand is XMM register)
  DEST[31:0] <- SRC;
  DEST[127:32] <- 000000000000000000000000H;
  DEST[VLMAX-1:128] (Unmodified)





MOVD (when source operand is MMX technology or XMM register)
  DEST <- SRC[31:0];

VMOVD (VEX-encoded version when destination is an XMM register)
  DEST[31:0] <- SRC[31:0]
  DEST[VLMAX-1:32] <- 0

MOVQ (when destination operand is XMM register)
  DEST[63:0] <- SRC[63:0];
  DEST[127:64] <- 0000000000000000H;
  DEST[VLMAX-1:128] (Unmodified)

MOVQ (when destination operand is r/m64)
  DEST[63:0] <- SRC[63:0];

MOVQ (when source operand is XMM register or r/m64)
  DEST <- SRC[63:0];

VMOVQ (VEX-encoded version when destination is an XMM register)
  DEST[63:0] <- SRC[63:0]
  DEST[VLMAX-1:64] <- 0

VMOVD (EVEX-encoded version when destination is an XMM register)
DEST[31:0] <- SRC[31:0]
DEST[511:32] <- 0H

VMOVQ (EVEX-encoded version when destination is an XMM register)
DEST[63:0] <- SRC[63:0]
DEST[511:64] <- 0H

Intel C/C++ Compiler Intrinsic Equivalent
MOVD:         __m64 _mm_cvtsi32_si64 (int i )
MOVD:         int _mm_cvtsi64_si32 ( __m64m )
MOVD:         __m128i _mm_cvtsi32_si128 (int a)
MOVD:         int _mm_cvtsi128_si32 ( __m128i a)
MOVQ:         __int64 _mm_cvtsi128_si64(__m128i);
MOVQ:         __m128i _mm_cvtsi64_si128(__int64);
VMOVD         __m128i _mm_cvtsi32_si128( int);
VMOVD         int _mm_cvtsi128_si32( __m128i );
VMOVQ         __m128i _mm_cvtsi64_si128 (__int64);
VMOVQ         __int64 _mm_cvtsi128_si64(__m128i );
VMOVQ         __m128i _mm_loadl_epi64( __m128i * s);
VMOVQ         void _mm_storel_epi64( __m128i * d, __m128i s);

Flags Affected
None

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5.
EVEX-encoded instruction, see Exceptions Type E9NF.
#UD                 If VEX.L = 1.
                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: MOVDDUP
description:
MOVDDUP-Replicate Double FP Values
 Opcode/                                Op / En    64/32        CPUID      Description
 Instruction                                       bit Mode     Feature
                                                   Support      Flag
 F2 0F 12 /r                            RM         V/V          SSE3       Move double-precision floating-point value from
 MOVDDUP xmm1, xmm2/m64                                                    xmm2/m64 and duplicate into xmm1.
 VEX.128.F2.0F.WIG 12 /r                RM         V/V          AVX        Move double-precision floating-point value from
 VMOVDDUP xmm1, xmm2/m64                                                   xmm2/m64 and duplicate into xmm1.
 VEX.256.F2.0F.WIG 12 /r                RM         V/V          AVX        Move even index double-precision floating-point
 VMOVDDUP ymm1, ymm2/m256                                                  values from ymm2/mem and duplicate each element
                                                                           into ymm1.
 EVEX.128.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512VL   Move double-precision floating-point value from
 VMOVDDUP xmm1 {k1}{z},                                         AVX512F    xmm2/m64 and duplicate each element into xmm1
 xmm2/m64                                                                  subject to writemask k1.
 EVEX.256.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512VL   Move even index double-precision floating-point
 VMOVDDUP ymm1 {k1}{z},                                         AVX512F    values from ymm2/m256 and duplicate each element
 ymm2/m256                                                                 into ymm1 subject to writemask k1.
 EVEX.512.F2.0F.W1 12 /r                DUP-RM     V/V          AVX512F    Move even index double-precision floating-point
 VMOVDDUP zmm1 {k1}{z},                                                    values from zmm2/m512 and duplicate each element
 zmm2/m512                                                                 into zmm1 subject to writemask k1.



                                                  Instruction Operand Encoding
      Op/En                 Operand 1                     Operand 2              Operand 3                 Operand 4
        RM                ModRM:reg (w)                  ModRM:r/m (r)              NA                        NA
     DUP-RM               ModRM:reg (w)                  ModRM:r/m (r)              NA                        NA

Description
For 256-bit or higher versions: Duplicates even-indexed double-precision floating-point values from the source
operand (the second operand) and into adjacent pair and store to the destination operand (the first operand).
For 128-bit versions: Duplicates the low double-precision floating-point value from the source operand (the second
operand) and store to the destination operand (the first operand).
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register are unchanged. The
source operand is XMM register or a 64-bit memory location.
VEX.128 and EVEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed. The source
operand is XMM register or a 64-bit memory location. The destination is updated conditionally under the writemask
for EVEX version.
VEX.256 and EVEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed. The source
operand is YMM register or a 256-bit memory location. The destination is updated conditionally under the
writemask for EVEX version.
EVEX.512 encoded version: The destination is updated according to the writemask. The source operand is ZMM
register or a 512-bit memory location.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.





                         SRC           X3                  X2          X1      X0




                         DEST          X2                 X2           X0      X0


                                              Figure 4-2. VMOVDDUP Operation


Operation
VMOVDDUP (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_SRC[63:0] <- SRC[63:0]
TMP_SRC[127:64] <- SRC[63:0]
IF VL >= 256
    TMP_SRC[191:128] <- SRC[191:128]
    TMP_SRC[255:192] <- SRC[191:128]
FI;
IF VL >= 512
    TMP_SRC[319:256] <- SRC[319:256]
    TMP_SRC[383:320] <- SRC[319:256]
    TMP_SRC[477:384] <- SRC[477:384]
    TMP_SRC[511:484] <- SRC[477:384]
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDDUP (VEX.256 encoded version)
DEST[63:0] <-SRC[63:0]
DEST[127:64] <-SRC[63:0]
DEST[191:128] <-SRC[191:128]
DEST[255:192] <-SRC[191:128]
DEST[MAX_VL-1:256] <-0

VMOVDDUP (VEX.128 encoded version)
DEST[63:0] <-SRC[63:0]
DEST[127:64] <-SRC[63:0]
DEST[MAX_VL-1:128] <-0




MOVDDUP (128-bit Legacy SSE version)
DEST[63:0] <-SRC[63:0]
DEST[127:64] <-SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMOVDDUP __m512d _mm512_movedup_pd( __m512d a);
VMOVDDUP __m512d _mm512_mask_movedup_pd(__m512d s, __mmask8 k, __m512d a);
VMOVDDUP __m512d _mm512_maskz_movedup_pd( __mmask8 k, __m512d a);
VMOVDDUP __m256d _mm256_mask_movedup_pd(__m256d s, __mmask8 k, __m256d a);
VMOVDDUP __m256d _mm256_maskz_movedup_pd( __mmask8 k, __m256d a);
VMOVDDUP __m128d _mm_mask_movedup_pd(__m128d s, __mmask8 k, __m128d a);
VMOVDDUP __m128d _mm_maskz_movedup_pd( __mmask8 k, __m128d a);
MOVDDUP __m256d _mm256_movedup_pd (__m256d a);
MOVDDUP __m128d _mm_movedup_pd (__m128d a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5;
EVEX-encoded instruction, see Exceptions Type E5NF.
#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVDQA
description:
MOVDQA/VMOVDQA/VMOVDQA32/VMOVDQA64-Move Aligned Packed Integer Values
 Opcode/                         Op/En    64/32      CPUID         Description
 Instruction                              bit Mode   Feature
                                          Support    Flag
 66 0F 6F /r                     RM       V/V        SSE2          Move aligned packed integer values from
 MOVDQA xmm1, xmm2/m128                                            xmm2/mem to xmm1.
 66 0F 7F /r                     MR       V/V        SSE2          Move aligned packed integer values from xmm1
 MOVDQA xmm2/m128, xmm1                                            to xmm2/mem.
 VEX.128.66.0F.WIG 6F /r         RM       V/V        AVX           Move aligned packed integer values from
 VMOVDQA xmm1, xmm2/m128                                           xmm2/mem to xmm1.
 VEX.128.66.0F.WIG 7F /r         MR       V/V        AVX           Move aligned packed integer values from xmm1
 VMOVDQA xmm2/m128, xmm1                                           to xmm2/mem.
 VEX.256.66.0F.WIG 6F /r         RM       V/V        AVX           Move aligned packed integer values from
 VMOVDQA ymm1, ymm2/m256                                           ymm2/mem to ymm1.
 VEX.256.66.0F.WIG 7F /r         MR       V/V        AVX           Move aligned packed integer values from ymm1
 VMOVDQA ymm2/m256, ymm1                                           to ymm2/mem.
 EVEX.128.66.0F.W0 6F /r         FVM-RM   V/V        AVX512VL      Move aligned packed doubleword integer values
 VMOVDQA32 xmm1 {k1}{z},                             AVX512F       from xmm2/m128 to xmm1 using writemask
 xmm2/m128                                                         k1.
 EVEX.256.66.0F.W0 6F /r         FVM-RM   V/V        AVX512VL      Move aligned packed doubleword integer values
 VMOVDQA32 ymm1 {k1}{z},                             AVX512F       from ymm2/m256 to ymm1 using writemask
 ymm2/m256                                                         k1.
 EVEX.512.66.0F.W0 6F /r         FVM-RM   V/V        AVX512F       Move aligned packed doubleword integer values
 VMOVDQA32 zmm1 {k1}{z},                                           from zmm2/m512 to zmm1 using writemask k1.
 zmm2/m512
 EVEX.128.66.0F.W0 7F /r         FVM-MR   V/V        AVX512VL      Move aligned packed doubleword integer values
 VMOVDQA32 xmm2/m128 {k1}{z},                        AVX512F       from xmm1 to xmm2/m128 using writemask
 xmm1                                                              k1.
 EVEX.256.66.0F.W0 7F /r         FVM-MR   V/V        AVX512VL      Move aligned packed doubleword integer values
 VMOVDQA32 ymm2/m256 {k1}{z},                        AVX512F       from ymm1 to ymm2/m256 using writemask
 ymm1                                                              k1.
 EVEX.512.66.0F.W0 7F /r         FVM-MR   V/V        AVX512F       Move aligned packed doubleword integer values
 VMOVDQA32 zmm2/m512 {k1}{z},                                      from zmm1 to zmm2/m512 using writemask k1.
 zmm1
 EVEX.128.66.0F.W1 6F /r         FVM-RM   V/V        AVX512VL      Move aligned quadword integer values from
 VMOVDQA64 xmm1 {k1}{z},                             AVX512F       xmm2/m128 to xmm1 using writemask k1.
 xmm2/m128
 EVEX.256.66.0F.W1 6F /r         FVM-RM   V/V        AVX512VL      Move aligned quadword integer values from
 VMOVDQA64 ymm1 {k1}{z},                             AVX512F       ymm2/m256 to ymm1 using writemask k1.
 ymm2/m256
 EVEX.512.66.0F.W1 6F /r         FVM-RM   V/V        AVX512F       Move aligned packed quadword integer values
 VMOVDQA64 zmm1 {k1}{z},                                           from zmm2/m512 to zmm1 using writemask k1.
 zmm2/m512
 EVEX.128.66.0F.W1 7F /r         FVM-MR   V/V        AVX512VL      Move aligned packed quadword integer values
 VMOVDQA64 xmm2/m128 {k1}{z},                        AVX512F       from xmm1 to xmm2/m128 using writemask
 xmm1                                                              k1.
 EVEX.256.66.0F.W1 7F /r         FVM-MR   V/V        AVX512VL      Move aligned packed quadword integer values
 VMOVDQA64 ymm2/m256 {k1}{z},                        AVX512F       from ymm1 to ymm2/m256 using writemask
 ymm1                                                              k1.
 EVEX.512.66.0F.W1 7F /r         FVM-MR   V/V        AVX512F       Move aligned packed quadword integer values
 VMOVDQA64 zmm2/m512 {k1}{z},                                      from zmm1 to zmm2/m512 using writemask k1.
 zmm1





                                              Instruction Operand Encoding
      Op/En               Operand 1                  Operand 2               Operand 3               Operand 4
       RM               ModRM:reg (w)              ModRM:r/m (r)                NA                       NA
       MR               ModRM:r/m (w)              ModRM:reg (r)                NA                       NA
     FVM-RM             ModRM:reg (w)              ModRM:r/m (r)                NA                       NA
     FVM-MR             ModRM:r/m (w)              ModRM:reg (r)                NA                       NA

Description
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX encoded versions:
Moves 128, 256 or 512 bits of packed doubleword/quadword integer values from the source operand (the second
operand) to the destination operand (the first operand). This instruction can be used to load a vector register from
an int32/int64 memory location, to store the contents of a vector register into an int32/int64 memory location, or
to move data between two ZMM registers. When the source or destination operand is a memory operand, the
operand must be aligned on a 16 (EVEX.128)/32(EVEX.256)/64(EVEX.512)-byte boundary or a general-protection
exception (#GP) will be generated. To move integer data to and from unaligned memory locations, use the
VMOVDQU instruction.
The destination operand is updated at 32-bit (VMOVDQA32) or 64-bit (VMOVDQA64) granularity according to the
writemask.
VEX.256 encoded version:
Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the
contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 32-byte boundary
or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory
locations, use the VMOVDQU instruction. Bits (MAX_VL-1:256) of the destination register are zeroed.
128-bit versions:
Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the
contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.
When the source or destination operand is a memory operand, the operand must be aligned on a 16-byte boundary
or a general-protection exception (#GP) will be generated. To move integer data to and from unaligned memory
locations, use the VMOVDQU instruction.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding ZMM destination register remain
unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.





Operation
VMOVDQA32 (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQA32 (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i]<- SRC[i+31:i]
         ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
    FI;
ENDFOR;

VMOVDQA32 (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VMOVDQA64 (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQA64 (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i]<- SRC[i+63:i]
         ELSE *DEST[i+63:i] remains unchanged* ; merging-masking
    FI;
ENDFOR;

VMOVDQA64 (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQA (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVDQA (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]
VMOVDQA (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

VMOVDQA (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)




(V)MOVDQA (128-bit store-form version)
DEST[127:0] <- SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVDQA32 __m512i _mm512_load_epi32( void * sa);
VMOVDQA32 __m512i _mm512_mask_load_epi32(__m512i s, __mmask16 k, void * sa);
VMOVDQA32 __m512i _mm512_maskz_load_epi32( __mmask16 k, void * sa);
VMOVDQA32 void _mm512_store_epi32(void * d, __m512i a);
VMOVDQA32 void _mm512_mask_store_epi32(void * d, __mmask16 k, __m512i a);
VMOVDQA32 __m256i _mm256_mask_load_epi32(__m256i s, __mmask8 k, void * sa);
VMOVDQA32 __m256i _mm256_maskz_load_epi32( __mmask8 k, void * sa);
VMOVDQA32 void _mm256_store_epi32(void * d, __m256i a);
VMOVDQA32 void _mm256_mask_store_epi32(void * d, __mmask8 k, __m256i a);
VMOVDQA32 __m128i _mm_mask_load_epi32(__m128i s, __mmask8 k, void * sa);
VMOVDQA32 __m128i _mm_maskz_load_epi32( __mmask8 k, void * sa);
VMOVDQA32 void _mm_store_epi32(void * d, __m128i a);
VMOVDQA32 void _mm_mask_store_epi32(void * d, __mmask8 k, __m128i a);
VMOVDQA64 __m512i _mm512_load_epi64( void * sa);
VMOVDQA64 __m512i _mm512_mask_load_epi64(__m512i s, __mmask8 k, void * sa);
VMOVDQA64 __m512i _mm512_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm512_store_epi64(void * d, __m512i a);
VMOVDQA64 void _mm512_mask_store_epi64(void * d, __mmask8 k, __m512i a);
VMOVDQA64 __m256i _mm256_mask_load_epi64(__m256i s, __mmask8 k, void * sa);
VMOVDQA64 __m256i _mm256_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm256_store_epi64(void * d, __m256i a);
VMOVDQA64 void _mm256_mask_store_epi64(void * d, __mmask8 k, __m256i a);
VMOVDQA64 __m128i _mm_mask_load_epi64(__m128i s, __mmask8 k, void * sa);
VMOVDQA64 __m128i _mm_maskz_load_epi64( __mmask8 k, void * sa);
VMOVDQA64 void _mm_store_epi64(void * d, __m128i a);
VMOVDQA64 void _mm_mask_store_epi64(void * d, __mmask8 k, __m128i a);
MOVDQA void __m256i _mm256_load_si256 (__m256i * p);
MOVDQA _mm256_store_si256(_m256i *p, __m256i a);
MOVDQA __m128i _mm_load_si128 (__m128i * p);
MOVDQA void _mm_store_si128(__m128i *p, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1.
#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVDQU
description:
MOVDQU/VMOVDQU/VMOVDQU8/VMOVDQU16/VMOVDQU32/VMOVDQU64-Move Unaligned Packed Integer Values
 Opcode/                                    Op/En       64/32      CPUID      Description
 Instruction                                            bit Mode   Feature
                                                        Support    Flag
 F3 0F 6F /r                                RM          V/V        SSE2       Move unaligned packed integer values from
 MOVDQU xmm1, xmm2/m128                                                       xmm2/m128 to xmm1.
 F3 0F 7F /r                                MR          V/V        SSE2       Move unaligned packed integer values from
 MOVDQU xmm2/m128, xmm1                                                       xmm1 to xmm2/m128.
 VEX.128.F3.0F.WIG 6F /r                    RM          V/V        AVX        Move unaligned packed integer values from
 VMOVDQU xmm1, xmm2/m128                                                      xmm2/m128 to xmm1.
 VEX.128.F3.0F.WIG 7F /r                    MR          V/V        AVX        Move unaligned packed integer values from
 VMOVDQU xmm2/m128, xmm1                                                      xmm1 to xmm2/m128.
 VEX.256.F3.0F.WIG 6F /r                    RM          V/V        AVX        Move unaligned packed integer values from
 VMOVDQU ymm1, ymm2/m256                                                      ymm2/m256 to ymm1.
 VEX.256.F3.0F.WIG 7F /r                    MR          V/V        AVX        Move unaligned packed integer values from
 VMOVDQU ymm2/m256, ymm1                                                      ymm1 to ymm2/m256.
 EVEX.128.F2.0F.W0 6F /r                    FVM-RM      V/V        AVX512VL   Move unaligned packed byte integer values
 VMOVDQU8 xmm1 {k1}{z}, xmm2/m128                                  AVX512BW   from xmm2/m128 to xmm1 using writemask
                                                                              k1.
 EVEX.256.F2.0F.W0 6F /r                    FVM-RM      V/V        AVX512VL   Move unaligned packed byte integer values
 VMOVDQU8 ymm1 {k1}{z}, ymm2/m256                                  AVX512BW   from ymm2/m256 to ymm1 using writemask
                                                                              k1.
 EVEX.512.F2.0F.W0 6F /r                    FVM-RM      V/V        AVX512BW   Move unaligned packed byte integer values
 VMOVDQU8 zmm1 {k1}{z}, zmm2/m512                                             from zmm2/m512 to zmm1 using writemask
                                                                              k1.
 EVEX.128.F2.0F.W0 7F /r                    FVM-MR      V/V        AVX512VL   Move unaligned packed byte integer values
 VMOVDQU8 xmm2/m128 {k1}{z}, xmm1                                  AVX512BW   from xmm1 to xmm2/m128 using writemask
                                                                              k1.
 EVEX.256.F2.0F.W0 7F /r                    FVM-MR      V/V        AVX512VL   Move unaligned packed byte integer values
 VMOVDQU8 ymm2/m256 {k1}{z}, ymm1                                  AVX512BW   from ymm1 to ymm2/m256 using writemask
                                                                              k1.
 EVEX.512.F2.0F.W0 7F /r                    FVM-MR      V/V        AVX512BW   Move unaligned packed byte integer values
 VMOVDQU8 zmm2/m512 {k1}{z}, zmm1                                             from zmm1 to zmm2/m512 using writemask
                                                                              k1.
 EVEX.128.F2.0F.W1 6F /r                    FVM-RM      V/V        AVX512VL   Move unaligned packed word integer values
 VMOVDQU16 xmm1 {k1}{z}, xmm2/m128                                 AVX512BW   from xmm2/m128 to xmm1 using writemask
                                                                              k1.
 EVEX.256.F2.0F.W1 6F /r                    FVM-RM      V/V        AVX512VL   Move unaligned packed word integer values
 VMOVDQU16 ymm1 {k1}{z}, ymm2/m256                                 AVX512BW   from ymm2/m256 to ymm1 using writemask
                                                                              k1.
 EVEX.512.F2.0F.W1 6F /r                    FVM-RM      V/V        AVX512BW   Move unaligned packed word integer values
 VMOVDQU16 zmm1 {k1}{z}, zmm2/m512                                            from zmm2/m512 to zmm1 using writemask
                                                                              k1.
 EVEX.128.F2.0F.W1 7F /r                    FVM-MR      V/V        AVX512VL   Move unaligned packed word integer values
 VMOVDQU16 xmm2/m128 {k1}{z}, xmm1                                 AVX512BW   from xmm1 to xmm2/m128 using writemask
                                                                              k1.
 EVEX.256.F2.0F.W1 7F /r                    FVM-MR      V/V        AVX512VL   Move unaligned packed word integer values
 VMOVDQU16 ymm2/m256 {k1}{z}, ymm1                                 AVX512BW   from ymm1 to ymm2/m256 using writemask
                                                                              k1.
 EVEX.512.F2.0F.W1 7F /r                    FVM-MR      V/V        AVX512BW   Move unaligned packed word integer values
 VMOVDQU16 zmm2/m512 {k1}{z}, zmm1                                            from zmm1 to zmm2/m512 using writemask
                                                                              k1.
 EVEX.128.F3.0F.W0 6F /r                    FVM-RM      V/V        AVX512VL   Move unaligned packed doubleword integer
 VMOVDQU32 xmm1 {k1}{z},                                           AVX512F    values from xmm2/m128 to xmm1 using
 xmm2/mm128                                                                   writemask k1.


 Opcode/                                Op/En       64/32        CPUID         Description
 Instruction                                        bit Mode     Feature
                                                    Support      Flag
 EVEX.256.F3.0F.W0 6F /r                FVM-RM      V/V          AVX512VL      Move unaligned packed doubleword integer
 VMOVDQU32 ymm1 {k1}{z}, ymm2/m256                               AVX512F       values from ymm2/m256 to ymm1 using
                                                                               writemask k1.
 EVEX.512.F3.0F.W0 6F /r                FVM-RM      V/V          AVX512F       Move unaligned packed doubleword integer
 VMOVDQU32 zmm1 {k1}{z}, zmm2/m512                                             values from zmm2/m512 to zmm1 using
                                                                               writemask k1.
 EVEX.128.F3.0F.W0 7F /r                FVM-MR      V/V          AVX512VL      Move unaligned packed doubleword integer
 VMOVDQU32 xmm2/m128 {k1}{z}, xmm1                               AVX512F       values from xmm1 to xmm2/m128 using
                                                                               writemask k1.
 EVEX.256.F3.0F.W0 7F /r                FVM-MR      V/V          AVX512VL      Move unaligned packed doubleword integer
 VMOVDQU32 ymm2/m256 {k1}{z}, ymm1                               AVX512F       values from ymm1 to ymm2/m256 using
                                                                               writemask k1.
 EVEX.512.F3.0F.W0 7F /r                FVM-MR      V/V          AVX512F       Move unaligned packed doubleword integer
 VMOVDQU32 zmm2/m512 {k1}{z}, zmm1                                             values from zmm1 to zmm2/m512 using
                                                                               writemask k1.
 EVEX.128.F3.0F.W1 6F /r                FVM-RM      V/V          AVX512VL      Move unaligned packed quadword integer
 VMOVDQU64 xmm1 {k1}{z}, xmm2/m128                               AVX512F       values from xmm2/m128 to xmm1 using
                                                                               writemask k1.
 EVEX.256.F3.0F.W1 6F /r                FVM-RM      V/V          AVX512VL      Move unaligned packed quadword integer
 VMOVDQU64 ymm1 {k1}{z}, ymm2/m256                               AVX512F       values from ymm2/m256 to ymm1 using
                                                                               writemask k1.
 EVEX.512.F3.0F.W1 6F /r                FVM-RM      V/V          AVX512F       Move unaligned packed quadword integer
 VMOVDQU64 zmm1 {k1}{z}, zmm2/m512                                             values from zmm2/m512 to zmm1 using
                                                                               writemask k1.
 EVEX.128.F3.0F.W1 7F /r                FVM-MR      V/V          AVX512VL      Move unaligned packed quadword integer
 VMOVDQU64 xmm2/m128 {k1}{z}, xmm1                               AVX512F       values from xmm1 to xmm2/m128 using
                                                                               writemask k1.
 EVEX.256.F3.0F.W1 7F /r                FVM-MR      V/V          AVX512VL      Move unaligned packed quadword integer
 VMOVDQU64 ymm2/m256 {k1}{z}, ymm1                               AVX512F       values from ymm1 to ymm2/m256 using
                                                                               writemask k1.
 EVEX.512.F3.0F.W1 7F /r                FVM-MR      V/V          AVX512F       Move unaligned packed quadword integer
 VMOVDQU64 zmm2/m512 {k1}{z}, zmm1                                             values from zmm1 to zmm2/m512 using
                                                                               writemask k1.


                                          Instruction Operand Encoding
       Op/En            Operand 1                 Operand 2                   Operand 3                  Operand 4
        RM            ModRM:reg (w)              ModRM:r/m (r)                    NA                        NA
        MR            ModRM:r/m (w)              ModRM:reg (r)                    NA                        NA
     FVM-RM           ModRM:reg (w)              ModRM:r/m (r)                    NA                        NA
     FVM-MR           ModRM:r/m (w)              ModRM:reg (r)                    NA                        NA

Description
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.
EVEX encoded versions:
Moves 128, 256 or 512 bits of packed byte/word/doubleword/quadword integer values from the source operand
(the second operand) to the destination operand (first operand). This instruction can be used to load a vector
register from a memory location, to store the contents of a vector register into a memory location, or to move data
between two vector registers.




The destination operand is updated at 8-bit (VMOVDQU8), 16-bit (VMOVDQU16), 32-bit (VMOVDQU32), or 64-bit
(VMOVDQU64) granularity according to the writemask.
VEX.256 encoded version:
Moves 256 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load a YMM register from a 256-bit memory location, to store the
contents of a YMM register into a 256-bit memory location, or to move data between two YMM registers.
Bits (MAX_VL-1:256) of the destination register are zeroed.


128-bit versions:
Moves 128 bits of packed integer values from the source operand (second operand) to the destination operand
(first operand). This instruction can be used to load an XMM register from a 128-bit memory location, to store the
contents of an XMM register into a 128-bit memory location, or to move data between two XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned to any alignment
without causing a general-protection exception (#GP) to be generated
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.

Operation
VMOVDQU8 (EVEX encoded versions, register-copy form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SRC[i+7:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE DEST[i+7:i] <- 0           ; zeroing-masking
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU8 (EVEX encoded versions, store-form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i]<-
              SRC[i+7:i]
         ELSE *DEST[i+7:i] remains unchanged*        ; merging-masking
    FI;
ENDFOR;





VMOVDQU8 (EVEX encoded versions, load-form)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SRC[i+7:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE DEST[i+7:i] <- 0           ; zeroing-masking
              FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU16 (EVEX encoded versions, register-copy form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC[i+15:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE DEST[i+15:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU16 (EVEX encoded versions, store-form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i]<-
               SRC[i+15:i]
         ELSE *DEST[i+15:i] remains unchanged* ; merging-masking
    FI;
ENDFOR;





VMOVDQU16 (EVEX encoded versions, load-form)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC[i+15:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE DEST[i+15:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU32 (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU32 (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i]<-
               SRC[i+31:i]
         ELSE *DEST[i+31:i] remains unchanged* ; merging-masking
    FI;
ENDFOR;





VMOVDQU32 (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU64 (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU64 (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i]<- SRC[i+63:i]
         ELSE *DEST[i+63:i] remains unchanged* ; merging-masking

   FI;
ENDFOR;





VMOVDQU64 (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVDQU (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVDQU (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]

VMOVDQU (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

VMOVDQU (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)

(V)MOVDQU (128-bit store-form version)
DEST[127:0] <- SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVDQU16 __m512i _mm512_mask_loadu_epi16(__m512i s, __mmask32 k, void * sa);
VMOVDQU16 __m512i _mm512_maskz_loadu_epi16( __mmask32 k, void * sa);
VMOVDQU16 void _mm512_mask_storeu_epi16(void * d, __mmask32 k, __m512i a);
VMOVDQU16 __m256i _mm256_mask_loadu_epi16(__m256i s, __mmask16 k, void * sa);
VMOVDQU16 __m256i _mm256_maskz_loadu_epi16( __mmask16 k, void * sa);
VMOVDQU16 void _mm256_mask_storeu_epi16(void * d, __mmask16 k, __m256i a);
VMOVDQU16 void _mm256_maskz_storeu_epi16(void * d, __mmask16 k);
VMOVDQU16 __m128i _mm_mask_loadu_epi16(__m128i s, __mmask8 k, void * sa);
VMOVDQU16 __m128i _mm_maskz_loadu_epi16( __mmask8 k, void * sa);
VMOVDQU16 void _mm_mask_storeu_epi16(void * d, __mmask8 k, __m128i a);
VMOVDQU32 __m512i _mm512_loadu_epi32( void * sa);
VMOVDQU32 __m512i _mm512_mask_loadu_epi32(__m512i s, __mmask16 k, void * sa);
VMOVDQU32 __m512i _mm512_maskz_loadu_epi32( __mmask16 k, void * sa);
VMOVDQU32 void _mm512_storeu_epi32(void * d, __m512i a);
VMOVDQU32 void _mm512_mask_storeu_epi32(void * d, __mmask16 k, __m512i a);
VMOVDQU32 __m256i _mm256_mask_loadu_epi32(__m256i s, __mmask8 k, void * sa);
VMOVDQU32 __m256i _mm256_maskz_loadu_epi32( __mmask8 k, void * sa);
VMOVDQU32 void _mm256_storeu_epi32(void * d, __m256i a);
VMOVDQU32 void _mm256_mask_storeu_epi32(void * d, __mmask8 k, __m256i a);
VMOVDQU32 __m128i _mm_mask_loadu_epi32(__m128i s, __mmask8 k, void * sa);



VMOVDQU32 __m128i _mm_maskz_loadu_epi32( __mmask8 k, void * sa);
VMOVDQU32 void _mm_storeu_epi32(void * d, __m128i a);
VMOVDQU32 void _mm_mask_storeu_epi32(void * d, __mmask8 k, __m128i a);
VMOVDQU64 __m512i _mm512_loadu_epi64( void * sa);
VMOVDQU64 __m512i _mm512_mask_loadu_epi64(__m512i s, __mmask8 k, void * sa);
VMOVDQU64 __m512i _mm512_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm512_storeu_epi64(void * d, __m512i a);
VMOVDQU64 void _mm512_mask_storeu_epi64(void * d, __mmask8 k, __m512i a);
VMOVDQU64 __m256i _mm256_mask_loadu_epi64(__m256i s, __mmask8 k, void * sa);
VMOVDQU64 __m256i _mm256_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm256_storeu_epi64(void * d, __m256i a);
VMOVDQU64 void _mm256_mask_storeu_epi64(void * d, __mmask8 k, __m256i a);
VMOVDQU64 __m128i _mm_mask_loadu_epi64(__m128i s, __mmask8 k, void * sa);
VMOVDQU64 __m128i _mm_maskz_loadu_epi64( __mmask8 k, void * sa);
VMOVDQU64 void _mm_storeu_epi64(void * d, __m128i a);
VMOVDQU64 void _mm_mask_storeu_epi64(void * d, __mmask8 k, __m128i a);
VMOVDQU8 __m512i _mm512_mask_loadu_epi8(__m512i s, __mmask64 k, void * sa);
VMOVDQU8 __m512i _mm512_maskz_loadu_epi8( __mmask64 k, void * sa);
VMOVDQU8 void _mm512_mask_storeu_epi8(void * d, __mmask64 k, __m512i a);
VMOVDQU8 __m256i _mm256_mask_loadu_epi8(__m256i s, __mmask32 k, void * sa);
VMOVDQU8 __m256i _mm256_maskz_loadu_epi8( __mmask32 k, void * sa);
VMOVDQU8 void _mm256_mask_storeu_epi8(void * d, __mmask32 k, __m256i a);
VMOVDQU8 void _mm256_maskz_storeu_epi8(void * d, __mmask32 k);
VMOVDQU8 __m128i _mm_mask_loadu_epi8(__m128i s, __mmask16 k, void * sa);
VMOVDQU8 __m128i _mm_maskz_loadu_epi8( __mmask16 k, void * sa);
VMOVDQU8 void _mm_mask_storeu_epi8(void * d, __mmask16 k, __m128i a);
MOVDQU __m256i _mm256_loadu_si256 (__m256i * p);
MOVDQU _mm256_storeu_si256(_m256i *p, __m256i a);
MOVDQU __m128i _mm_loadu_si128 (__m128i * p);
MOVDQU _mm_storeu_si128(__m128i *p, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD                  If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVDQ2Q
description:
MOVDQ2Q-Move Quadword from XMM to MMX Technology Register
 Opcode                   Instruction                 Op/    64-Bit   Compat/ Description
                                                      En     Mode     Leg Mode
 F2 0F D6 /r              MOVDQ2Q mm, xmm             RM     Valid    Valid       Move low quadword from xmm to mmx
                                                                                  register.



                                                Instruction Operand Encoding
  Op/En              Operand 1                   Operand 2                    Operand 3                Operand 4
    RM              ModRM:reg (w)               ModRM:r/m (r)                    NA                       NA


Description
Moves the low quadword from the source operand (second operand) to the destination operand (first operand).
The source operand is an XMM register and the destination operand is an MMX technology register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the MOVDQ2Q instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST <- SRC[63:0];

Intel C/C++ Compiler Intrinsic Equivalent
MOVDQ2Q:             __m64 _mm_movepi64_pi64 ( __m128i a)

SIMD Floating-Point Exceptions
None.

Protected Mode Exceptions
#NM                     If CR0.TS[bit 3] = 1.
#UD                     If CR0.EM[bit 2] = 1.
                        If CR4.OSFXSR[bit 9] = 0.
                        If CPUID.01H:EDX.SSE2[bit 26] = 0.
                        If the LOCK prefix is used.
#MF                     If there is a pending x87 FPU exception.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.





platform: x86_64
mnem: MOVHLPS
description:
MOVHLPS-Move Packed Single-Precision Floating-Point Values High to Low
 Opcode/                             Op /   64/32       CPUID             Description
 Instruction                         En     bit Mode    Feature
                                            Support     Flag
 0F 12 /r                            RM     V/V         SSE               Move two packed single-precision floating-point values
 MOVHLPS xmm1, xmm2                                                       from high quadword of xmm2 to low quadword of xmm1.
 VEX.NDS.128.0F.WIG 12 /r            RVM    V/V         AVX               Merge two packed single-precision floating-point values
 VMOVHLPS xmm1, xmm2, xmm3                                                from high quadword of xmm3 and low quadword of xmm2.
 EVEX.NDS.128.0F.W0 12 /r            RVM    V/V         AVX512F           Merge two packed single-precision floating-point values
 VMOVHLPS xmm1, xmm2, xmm3                                                from high quadword of xmm3 and low quadword of xmm2.



                                             Instruction Operand Encoding1
       Op/En                Operand 1                  Operand 2                        Operand 3                   Operand 4
        RM                ModRM:reg (w)            ModRM:r/m (r)                           NA                           NA
       RVM                ModRM:reg (w)                 vvvv (r)                     ModRM:r/m (r)                      NA

Description
This instruction cannot be used for memory to register moves.
128-bit two-argument form:
Moves two packed single-precision floating-point values from the high quadword of the second XMM argument
(second operand) to the low quadword of the first XMM register (first argument). The quadword at bits 127:64 of
the destination operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register remain
unchanged.
128-bit and EVEX three-argument form
Moves two packed single-precision floating-point values from the high quadword of the third XMM argument (third
operand) to the low quadword of the destination (first operand). Copies the high quadword from the second XMM
argument (second operand) to the high quadword of the destination (first operand). Bits (MAX_VL-1:128) of the
corresponding destination register are zeroed.
If VMOVHLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.

Operation
MOVHLPS (128-bit two-argument form)
DEST[63:0] <- SRC[127:64]
DEST[MAX_VL-1:64] (Unmodified)

VMOVHLPS (128-bit three-argument form - VEX & EVEX)
DEST[63:0] <- SRC2[127:64]
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
MOVHLPS __m128 _mm_movehl_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
None




1. ModRM.MOD = 011B required



Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7; additionally
#UD                      If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E7NM.128.






platform: x86_64
mnem: MOVHPD
description:
MOVHPD-Move High Packed Double-Precision Floating-Point Value
 Opcode/                            Op / En    64/32       CPUID        Description
 Instruction                                   bit Mode    Feature
                                               Support     Flag
 66 0F 16 /r                        RM         V/V         SSE2         Move double-precision floating-point value from m64
 MOVHPD xmm1, m64                                                       to high quadword of xmm1.
 VEX.NDS.128.66.0F.WIG 16 /r        RVM        V/V         AVX          Merge double-precision floating-point value from m64
 VMOVHPD xmm2, xmm1, m64                                                and the low quadword of xmm1.
 EVEX.NDS.128.66.0F.W1 16 /r        T1S        V/V         AVX512F      Merge double-precision floating-point value from m64
 VMOVHPD xmm2, xmm1, m64                                                and the low quadword of xmm1.
 66 0F 17 /r                        MR         V/V         SSE2         Move double-precision floating-point value from high
 MOVHPD m64, xmm1                                                       quadword of xmm1 to m64.
 VEX.128.66.0F.WIG 17 /r            MR         V/V         AVX          Move double-precision floating-point value from high
 VMOVHPD m64, xmm1                                                      quadword of xmm1 to m64.
 EVEX.128.66.0F.W1 17 /r            T1S-MR     V/V         AVX512F      Move double-precision floating-point value from high
 VMOVHPD m64, xmm1                                                      quadword of xmm1 to m64.



                                              Instruction Operand Encoding
        Op/En              Operand 1                  Operand 2                   Operand 3                   Operand 4
         RM             ModRM:reg (r, w)             ModRM:r/m (r)                    NA                          NA
        RVM              ModRM:reg (w)                 VEX.vvvv                 ModRM:r/m (r)                     NA
         MR              ModRM:r/m (w)               ModRM:reg (r)                    NA                          NA
         T1S             ModRM:reg (w)                EVEX.vvvv                 ModRM:r/m (r)                     NA
       T1S-MR            ModRM:r/m (w)               ModRM:reg (r)                    NA                          NA

Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the high 64-
bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of
the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads a double-precision floating-point value from the source 64-bit memory operand (the third operand) and
stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source
operand (second operand) are copied to the low 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-
sponding destination register are zeroed.
128-bit store:
Stores a double-precision floating-point value from the high 64-bits of the XMM register source (second operand)
to the 64-bit memory location (first operand).
Note: VMOVHPD (store) (VEX.128.66.0F 17 /r) is legal and has the same behavior as the existing 66 0F 17 store.
For VMOVHPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVHPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.





Operation
MOVHPD (128-bit Legacy SSE load)
DEST[63:0] (Unmodified)
DEST[127:64] <- SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)

VMOVHPD (VEX.128 & EVEX encoded load)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[MAX_VL-1:128] <- 0

VMOVHPD (store)
DEST[63:0] <- SRC[127:64]

Intel C/C++ Compiler Intrinsic Equivalent
MOVHPD __m128d _mm_loadh_pd ( __m128d a, double *p)
MOVHPD void _mm_storeh_pd (double *p, __m128d a)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                     If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.






platform: x86_64
mnem: MOVHPS
description:
MOVHPS-Move High Packed Single-Precision Floating-Point Values
 Opcode/                         Op / En   64/32      CPUID       Description
 Instruction                               bit Mode   Feature
                                           Support    Flag
 0F 16 /r                        RM        V/V        SSE         Move two packed single-precision floating-point values
 MOVHPS xmm1, m64                                                 from m64 to high quadword of xmm1.
 VEX.NDS.128.0F.WIG 16 /r        RVM       V/V        AVX         Merge two packed single-precision floating-point values
 VMOVHPS xmm2, xmm1, m64                                          from m64 and the low quadword of xmm1.
 EVEX.NDS.128.0F.W0 16 /r        T2        V/V        AVX512F     Merge two packed single-precision floating-point values
 VMOVHPS xmm2, xmm1, m64                                          from m64 and the low quadword of xmm1.
 0F 17 /r                        MR        V/V        SSE         Move two packed single-precision floating-point values
 MOVHPS m64, xmm1                                                 from high quadword of xmm1 to m64.
 VEX.128.0F.WIG 17 /r            MR        V/V        AVX         Move two packed single-precision floating-point values
 VMOVHPS m64, xmm1                                                from high quadword of xmm1 to m64.
 EVEX.128.0F.W0 17 /r            T2-MR     V/V        AVX512F     Move two packed single-precision floating-point values
 VMOVHPS m64, xmm1                                                from high quadword of xmm1 to m64.



                                           Instruction Operand Encoding
       Op/En             Operand 1                Operand 2                  Operand 3                    Operand 4
        RM            ModRM:reg (r, w)           ModRM:r/m (r)                  NA                            NA
        RVM            ModRM:reg (w)               VEX.vvvv                ModRM:r/m (r)                      NA
        MR             ModRM:r/m (w)             ModRM:reg (r)                  NA                            NA
         T2            ModRM:reg (w)              EVEX.vvvv                ModRM:r/m (r)                      NA
       T2-MR           ModRM:r/m (w)             ModRM:reg (r)                  NA                            NA

Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves two packed single-precision floating-point values from the source 64-bit memory operand and stores them
in the high 64-bits of the destination XMM register. The lower 64bits of the XMM register are preserved. Bits
(MAX_VL-1:128) of the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads two single-precision floating-point values from the source 64-bit memory operand (the third operand) and
stores it in the upper 64-bits of the destination XMM register (first operand). The low 64-bits from the first source
operand (the second operand) are copied to the lower 64-bits of the destination. Bits (MAX_VL-1:128) of the corre-
sponding destination register are zeroed.
128-bit store:
Stores two packed single-precision floating-point values from the high 64-bits of the XMM register source (second
operand) to the 64-bit memory location (first operand).
Note: VMOVHPS (store) (VEX.NDS.128.0F 17 /r) is legal and has the same behavior as the existing 0F 17 store.
For VMOVHPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.





Operation
MOVHPS (128-bit Legacy SSE load)
DEST[63:0] (Unmodified)
DEST[127:64] <- SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)

VMOVHPS (VEX.128 and EVEX encoded load)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[MAX_VL-1:128] <- 0

VMOVHPS (store)
DEST[63:0] <- SRC[127:64]

Intel C/C++ Compiler Intrinsic Equivalent
MOVHPS __m128 _mm_loadh_pi ( __m128 a, __m64 *p)
MOVHPS void _mm_storeh_pi (__m64 *p, __m128 a)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                      If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.






platform: x86_64
mnem: MOVLHPS
description:
MOVLHPS-Move Packed Single-Precision Floating-Point Values Low to High
 Opcode/                             Op /   64/32        CPUID         Description
 Instruction                         En     bit Mode     Feature
                                            Support      Flag
 0F 16 /r                            RM     V/V          SSE           Move two packed single-precision floating-point values from
 MOVLHPS xmm1, xmm2                                                    low quadword of xmm2 to high quadword of xmm1.
 VEX.NDS.128.0F.WIG 16 /r            RVM    V/V          AVX           Merge two packed single-precision floating-point values
 VMOVLHPS xmm1, xmm2, xmm3                                             from low quadword of xmm3 and low quadword of xmm2.
 EVEX.NDS.128.0F.W0 16 /r            RVM    V/V          AVX512F       Merge two packed single-precision floating-point values
 VMOVLHPS xmm1, xmm2, xmm3                                             from low quadword of xmm3 and low quadword of xmm2.



                                              Instruction Operand Encoding1
        Op/En                Operand 1                  Operand 2                    Operand 3                   Operand 4
         RM                ModRM:reg (w)               ModRM:r/m (r)                    NA                           NA
        RVM                ModRM:reg (w)                 vvvv (r)                 ModRM:r/m (r)                      NA

Description
This instruction cannot be used for memory to register moves.
128-bit two-argument form:
Moves two packed single-precision floating-point values from the low quadword of the second XMM argument
(second operand) to the high quadword of the first XMM register (first argument). The low quadword of the desti-
nation operand is left unchanged. Bits (MAX_VL-1:128) of the corresponding destination register are unmodified.
128-bit three-argument forms:
Moves two packed single-precision floating-point values from the low quadword of the third XMM argument (third
operand) to the high quadword of the destination (first operand). Copies the low quadword from the second XMM
argument (second operand) to the low quadword of the destination (first operand). Bits (MAX_VL-1:128) of the
corresponding destination register are zeroed.
If VMOVLHPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.

Operation
MOVLHPS (128-bit two-argument form)
DEST[63:0] (Unmodified)
DEST[127:64] <- SRC[63:0]
DEST[MAX_VL-1:128] (Unmodified)

VMOVLHPS (128-bit three-argument form - VEX & EVEX)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
MOVLHPS __m128 _mm_movelh_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
None




1. ModRM.MOD = 011B required



Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7; additionally
#UD                      If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E7NM.128.






platform: x86_64
mnem: MOVLPD
description:
MOVLPD-Move Low Packed Double-Precision Floating-Point Value
 Opcode/                         Op / En   64/32        CPUID     Description
 Instruction                               bit Mode     Feature
                                           Support      Flag
 66 0F 12 /r                     RM        V/V          SSE2      Move double-precision floating-point value from m64 to
 MOVLPD xmm1, m64                                                 low quadword of xmm1.
 VEX.NDS.128.66.0F.WIG 12 /r     RVM       V/V          AVX       Merge double-precision floating-point value from m64
 VMOVLPD xmm2, xmm1, m64                                          and the high quadword of xmm1.
 EVEX.NDS.128.66.0F.W1 12 /r     T1S       V/V          AVX512F   Merge double-precision floating-point value from m64
 VMOVLPD xmm2, xmm1, m64                                          and the high quadword of xmm1.
 66 0F 13/r                      MR        V/V          SSE2      Move double-precision floating-point value from low
 MOVLPD m64, xmm1                                                 quadword of xmm1 to m64.
 VEX.128.66.0F.WIG 13/r          MR        V/V          AVX       Move double-precision floating-point value from low
 VMOVLPD m64, xmm1                                                quadword of xmm1 to m64.
 EVEX.128.66.0F.W1 13/r          T1S-MR    V/V          AVX512F   Move double-precision floating-point value from low
 VMOVLPD m64, xmm1                                                quadword of xmm1 to m64.



                                            Instruction Operand Encoding
       Op/En              Operand 1               Operand 2                 Operand 3                    Operand 4
        RM             ModRM:reg (r, w)          ModRM:r/m (r)                  NA                           NA
        RVM             ModRM:r/m (r)                 VEX.vvvv            ModRM:r/m (r)                      NA
        MR             ModRM:r/m (w)             ModRM:reg (r)                  NA                           NA
        T1S            ModRM:reg (w)              EVEX.vvvv               ModRM:r/m (r)                      NA
      T1S-MR           ModRM:r/m (w)             ModRM:reg (r)                  NA                           NA

Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves a double-precision floating-point value from the source 64-bit memory operand and stores it in the low 64-
bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits (MAX_VL-1:128) of
the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads a double-precision floating-point value from the source 64-bit memory operand (third operand), merges it
with the upper 64-bits of the first source XMM register (second operand), and stores it in the low 128-bits of the
destination XMM register (first operand). Bits (MAX_VL-1:128) of the corresponding destination register are
zeroed.
128-bit store:
Stores a double-precision floating-point value from the low 64-bits of the XMM register source (second operand) to
the 64-bit memory location (first operand).
Note: VMOVLPD (store) (VEX.128.66.0F 13 /r) is legal and has the same behavior as the existing 66 0F 13 store.
For VMOVLPD (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.
If VMOVLPD is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.

Operation
MOVLPD (128-bit Legacy SSE load)
DEST[63:0] <- SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)
VMOVLPD (VEX.128 & EVEX encoded load)



DEST[63:0] <- SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VMOVLPD (store)
DEST[63:0] <- SRC[63:0]

Intel C/C++ Compiler Intrinsic Equivalent
MOVLPD __m128d _mm_loadl_pd ( __m128d a, double *p)
MOVLPD void _mm_storel_pd (double *p, __m128d a)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                     If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.






platform: x86_64
mnem: MOVLPS
description:
MOVLPS-Move Low Packed Single-Precision Floating-Point Values
 Opcode/                         Op / En   64/32         CPUID        Description
 Instruction                               bit Mode      Feature
                                           Support       Flag
 0F 12 /r                        RM        V/V           SSE          Move two packed single-precision floating-point values
 MOVLPS xmm1, m64                                                     from m64 to low quadword of xmm1.
 VEX.NDS.128.0F.WIG 12 /r        RVM       V/V           AVX          Merge two packed single-precision floating-point values
 VMOVLPS xmm2, xmm1, m64                                              from m64 and the high quadword of xmm1.
 EVEX.NDS.128.0F.W0 12 /r        T2        V/V           AVX512F      Merge two packed single-precision floating-point values
 VMOVLPS xmm2, xmm1, m64                                              from m64 and the high quadword of xmm1.
 0F 13/r                         MR        V/V           SSE          Move two packed single-precision floating-point values
 MOVLPS m64, xmm1                                                     from low quadword of xmm1 to m64.
 VEX.128.0F.WIG 13/r             MR        V/V           AVX          Move two packed single-precision floating-point values
 VMOVLPS m64, xmm1                                                    from low quadword of xmm1 to m64.
 EVEX.128.0F.W0 13/r             T2-MR     V/V           AVX512F      Move two packed single-precision floating-point values
 VMOVLPS m64, xmm1                                                    from low quadword of xmm1 to m64.



                                             Instruction Operand Encoding
        Op/En             Operand 1                    Operand 2                    Operand 3                   Operand 4
         RM            ModRM:reg (r, w)               ModRM:r/m (r)                    NA                          NA
        RVM             ModRM:reg (w)                   VEX.vvvv                 ModRM:r/m (r)                     NA
         MR             ModRM:r/m (w)                 ModRM:reg (r)                    NA                          NA
         T2             ModRM:reg (w)                  EVEX.vvvv                 ModRM:r/m (r)                     NA
       T2-MR            ModRM:r/m (w)                 ModRM:reg (r)                    NA                          NA

Description
This instruction cannot be used for register to register or memory to memory moves.
128-bit Legacy SSE load:
Moves two packed single-precision floating-point values from the source 64-bit memory operand and stores them
in the low 64-bits of the destination XMM register. The upper 64bits of the XMM register are preserved. Bits
(MAX_VL-1:128) of the corresponding destination register are preserved.
VEX.128 & EVEX encoded load:
Loads two packed single-precision floating-point values from the source 64-bit memory operand (the third
operand), merges them with the upper 64-bits of the first source operand (the second operand), and stores them
in the low 128-bits of the destination register (the first operand). Bits (MAX_VL-1:128) of the corresponding desti-
nation register are zeroed.
128-bit store:
Loads two packed single-precision floating-point values from the low 64-bits of the XMM register source (second
operand) to the 64-bit memory location (first operand).
Note: VMOVLPS (store) (VEX.128.0F 13 /r) is legal and has the same behavior as the existing 0F 13 store. For
VMOVLPS (store) VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instruction will #UD.


If VMOVLPS is encoded with VEX.L or EVEX.L'L= 1, an attempt to execute the instruction encoded with VEX.L or
EVEX.L'L= 1 will cause an #UD exception.





Operation
MOVLPS (128-bit Legacy SSE load)
DEST[63:0] <- SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)

VMOVLPS (VEX.128 & EVEX encoded load)
DEST[63:0] <- SRC2[63:0]
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

VMOVLPS (store)
DEST[63:0] <- SRC[63:0]

Intel C/C++ Compiler Intrinsic Equivalent
MOVLPS __m128 _mm_loadl_pi ( __m128 a, __m64 *p)
MOVLPS void _mm_storel_pi (__m64 *p, __m128 a)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                      If VEX.L = 1.
EVEX-encoded instruction, see Exceptions Type E9NF.






platform: x86_64
mnem: MOVMSKPD
description:
MOVMSKPD-Extract Packed Double-Precision Floating-Point Sign Mask
Opcode/                                 Op/    64/32-bit CPUID             Description
Instruction                             En     Mode      Feature
                                                         Flag
66 0F 50 /r                             RM     V/V            SSE2         Extract 2-bit sign mask from xmm and store in reg. The
MOVMSKPD reg, xmm                                                          upper bits of r32 or r64 are filled with zeros.

VEX.128.66.0F.WIG 50 /r                 RM     V/V            AVX          Extract 2-bit sign mask from xmm2 and store in reg.
VMOVMSKPD reg, xmm2                                                        The upper bits of r32 or r64 are zeroed.

VEX.256.66.0F.WIG 50 /r                 RM     V/V            AVX          Extract 4-bit sign mask from ymm2 and store in reg.
VMOVMSKPD reg, ymm2                                                        The upper bits of r32 or r64 are zeroed.



                                          Instruction Operand Encoding
   Op/En             Operand 1                 Operand 2                        Operand 3                      Operand 4
     RM            ModRM:reg (w)              ModRM:r/m (r)                         NA                             NA


Description
Extracts the sign bits from the packed double-precision floating-point values in the source operand (second
operand), formats them into a 2-bit mask, and stores the mask in the destination operand (first operand). The
source operand is an XMM register, and the destination operand is a general-purpose register. The mask is stored
in the 2 low-order bits of the destination operand. Zero-extend the upper bits of the destination.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose
register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
(V)MOVMSKPD (128-bit versions)
DEST[0] <- SRC[63]
DEST[1] <- SRC[127]
IF DEST = r32
    THEN DEST[31:2] <- 0;
    ELSE DEST[63:2] <- 0;
FI

VMOVMSKPD (VEX.256 encoded version)
DEST[0] <- SRC[63]
DEST[1] <- SRC[127]
DEST[2] <- SRC[191]
DEST[3] <- SRC[255]
IF DEST = r32
    THEN DEST[31:4] <- 0;
    ELSE DEST[63:4] <- 0;
FI





Intel C/C++ Compiler Intrinsic Equivalent
MOVMSKPD:           int _mm_movemask_pd ( __m128d a)
VMOVMSKPD:          _mm256_movemask_pd(__m256d a)

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type 7; additionally
#UD                      If VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVMSKPS
description:
MOVMSKPS-Extract Packed Single-Precision Floating-Point Sign Mask
 Opcode/                                 Op/    64/32-bit CPUID          Description
 Instruction                             En     Mode      Feature
                                                          Flag
 0F 50 /r                                RM     V/V        SSE           Extract 4-bit sign mask from xmm and store in reg.
 MOVMSKPS reg, xmm                                                       The upper bits of r32 or r64 are filled with zeros.

 VEX.128.0F.WIG 50 /r                    RM     V/V        AVX           Extract 4-bit sign mask from xmm2 and store in reg.
 VMOVMSKPS reg, xmm2                                                     The upper bits of r32 or r64 are zeroed.

 VEX.256.0F.WIG 50 /r                    RM     V/V        AVX           Extract 8-bit sign mask from ymm2 and store in reg.
 VMOVMSKPS reg, ymm2                                                     The upper bits of r32 or r64 are zeroed.



                                          Instruction Operand Encoding1
   Op/En              Operand 1               Operand 2                    Operand 3                        Operand 4
    RM            ModRM:reg (w)            ModRM:r/m (r)                       NA                               NA


Description
Extracts the sign bits from the packed single-precision floating-point values in the source operand (second
operand), formats them into a 4- or 8-bit mask, and stores the mask in the destination operand (first operand).
The source operand is an XMM or YMM register, and the destination operand is a general-purpose register. The
mask is stored in the 4 or 8 low-order bits of the destination operand. The upper bits of the destination operand
beyond the mask are filled with zeros.
In 64-bit mode, the instruction can access additional registers (XMM8-XMM15, R8-R15) when used with a REX.R
prefix. The default operand size is 64-bit in 64-bit mode.
128-bit versions: The source operand is a YMM register. The destination operand is a general purpose register.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a general purpose
register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
DEST[0] <- SRC[31];
DEST[1] <- SRC[63];
DEST[2] <- SRC[95];
DEST[3] <- SRC[127];

IF DEST = r32
    THEN DEST[31:4] <- ZeroExtend;
    ELSE DEST[63:4] <- ZeroExtend;
FI;




1. ModRM.MOD = 011B required



(V)MOVMSKPS (128-bit version)
DEST[0] <- SRC[31]
DEST[1] <- SRC[63]
DEST[2] <- SRC[95]
DEST[3] <- SRC[127]
IF DEST = r32
    THEN DEST[31:4] <- 0;
    ELSE DEST[63:4] <- 0;
FI

VMOVMSKPS (VEX.256 encoded version)
DEST[0] <- SRC[31]
DEST[1] <- SRC[63]
DEST[2] <- SRC[95]
DEST[3] <- SRC[127]
DEST[4] <- SRC[159]
DEST[5] <- SRC[191]
DEST[6] <- SRC[223]
DEST[7] <- SRC[255]
IF DEST = r32
    THEN DEST[31:8] <- 0;
    ELSE DEST[63:8] <- 0;
FI

Intel C/C++ Compiler Intrinsic Equivalent
int _mm_movemask_ps(__m128 a)
int _mm256_movemask_ps(__m256 a)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 7; additionally
#UD                      If VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVNTDQA
description:
MOVNTDQA-Load Double Quadword Non-Temporal Aligned Hint
 Opcode/                         Op /    64/32       CPUID           Description
 Instruction                     En      bit Mode    Feature Flag
                                         Support
 66 0F 38 2A /r                  RM      V/V         SSE4_1          Move double quadword from m128 to xmm1 using non-
 MOVNTDQA xmm1, m128                                                 temporal hint if WC memory type.
 VEX.128.66.0F38.WIG 2A /r       RM      V/V         AVX             Move double quadword from m128 to xmm using non-
 VMOVNTDQA xmm1, m128                                                temporal hint if WC memory type.
 VEX.256.66.0F38.WIG 2A /r       RM      V/V         AVX2            Move 256-bit data from m256 to ymm using non-temporal
 VMOVNTDQA ymm1, m256                                                hint if WC memory type.
 EVEX.128.66.0F38.W0 2A /r       FVM     V/V         AVX512VL        Move 128-bit data from m128 to xmm using non-temporal
 VMOVNTDQA xmm1, m128                                AVX512F         hint if WC memory type.
 EVEX.256.66.0F38.W0 2A /r       FVM     V/V         AVX512VL        Move 256-bit data from m256 to ymm using non-temporal
 VMOVNTDQA ymm1, m256                                AVX512F         hint if WC memory type.
 EVEX.512.66.0F38.W0 2A /r       FVM     V/V         AVX512F         Move 512-bit data from m512 to zmm using non-temporal
 VMOVNTDQA zmm1, m512                                                hint if WC memory type.



                                               Instruction Operand Encoding1
        Op/En                Operand 1                 Operand 2                   Operand 3               Operand 4
         RM              ModRM:reg (w)               ModRM:r/m (r)                    NA                      NA
         FVM             ModRM:reg (w)               ModRM:r/m (r)                    NA                      NA

Description
MOVNTDQA loads a double quadword from the source operand (second operand) to the destination operand (first
operand) using a non-temporal hint if the memory source is WC (write combining) memory type. For WC memory
type, the nontemporal hint may be implemented by loading a temporary internal buffer with the equivalent of an
aligned cache line without filling this data to the cache. Any memory-type aliased lines in the cache will be snooped
and flushed. Subsequent MOVNTDQA reads to unread portions of the WC cache line will receive data from the
temporary internal buffer if data is available. The temporary internal buffer may be flushed by the processor at any
time for any reason, for example:
. A load operation other than a MOVNTDQA which references memory already resident in a temporary internal
buffer.
. A non-WC reference to memory already resident in a temporary internal buffer.
. Interleaving of reads and writes to a single temporary internal buffer.
. Repeated (V)MOVNTDQA loads of a particular 16-byte item in a streaming line.
. Certain micro-architectural conditions including resource shortages, detection of
a mis-speculation condition, and various fault conditions
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when reading the
data from memory. Using this protocol, the processor
does not read the data into the cache hierarchy, nor does it fetch the corresponding cache line from memory into
the cache hierarchy. The memory type of the region being read can override the non-temporal hint, if the memory
address specified for the non-temporal read is not a WC memory region. Information on non-temporal reads and
writes can be found in "Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32
Architecture Software Developer's Manual, Volume 3A.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
a MFENCE instruction should be used in conjunction with MOVNTDQA instructions if multiple processors might use
different memory types for the referenced memory locations or to synchronize reads of a processor with writes by
other agents in the system. A processor's implementation of the streaming load hint does not override the effective
memory type, but the implementation of the hint is processor dependent. For example, a processor implementa-

1. ModRM.MOD = 011B required



tion may choose to ignore the hint and process the instruction as a normal MOVDQA for any memory type. Alter-
natively, another implementation may optimize cache reads generated by MOVNTDQA on WB memory type to
reduce cache evictions.
The 128-bit (V)MOVNTDQA addresses must be 16-byte aligned or the instruction will cause a #GP.
The 256-bit VMOVNTDQA addresses must be 32-byte aligned or the instruction will cause a #GP.
The 512-bit VMOVNTDQA addresses must be 64-byte aligned or the instruction will cause a #GP.

Operation
MOVNTDQA (128bit- Legacy SSE form)
DEST <-SRC
DEST[MAX_VL-1:128] (Unmodified)

VMOVNTDQA (VEX.128 and EVEX.128 encoded form)
DEST <- SRC
DEST[MAX_VL-1:128] <- 0

VMOVNTDQA (VEX.256 and EVEX.256 encoded forms)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVNTDQA (EVEX.512 encoded form)
DEST[511:0] <- SRC[511:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTDQA __m512i _mm512_stream_load_si512(void * p);
MOVNTDQA __m128i _mm_stream_load_si128 (__m128i *p);
VMOVNTDQA __m256i _mm_stream_load_si256 (__m256i *p);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD                    If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: MOVNTDQ
description:
MOVNTDQ-Store Packed Integers Using Non-Temporal Hint
 Opcode/                        Op /     64/32      CPUID            Description
 Instruction                    En       bit Mode   Feature Flag
                                         Support
 66 0F E7 /r                    MR       V/V        SSE2             Move packed integer values in xmm1 to m128 using non-
 MOVNTDQ m128, xmm1                                                  temporal hint.
 VEX.128.66.0F.WIG E7 /r        MR       V/V        AVX              Move packed integer values in xmm1 to m128 using non-
 VMOVNTDQ m128, xmm1                                                 temporal hint.
 VEX.256.66.0F.WIG E7 /r        MR       V/V        AVX              Move packed integer values in ymm1 to m256 using non-
 VMOVNTDQ m256, ymm1                                                 temporal hint.
 EVEX.128.66.0F.W0 E7 /r        FVM      V/V        AVX512VL         Move packed integer values in xmm1 to m128 using non-
 VMOVNTDQ m128, xmm1                                AVX512F          temporal hint.
 EVEX.256.66.0F.W0 E7 /r        FVM      V/V        AVX512VL         Move packed integer values in zmm1 to m256 using non-
 VMOVNTDQ m256, ymm1                                AVX512F          temporal hint.
 EVEX.512.66.0F.W0 E7 /r        FVM      V/V        AVX512F          Move packed integer values in zmm1 to m512 using non-
 VMOVNTDQ m512, zmm1                                                 temporal hint.



                                               Instruction Operand Encoding1
       Op/En                 Operand 1                 Operand 2                   Operand 3                  Operand 4
        MR                 ModRM:r/m (w)             ModRM:reg (r)                    NA                         NA
        FVM                ModRM:r/m (w)             ModRM:reg (r)                    NA                         NA

Description
Moves the packed integers in the source operand (second operand) to the destination operand (first operand) using
a non-temporal hint to prevent caching of the data during the write to memory. The source operand is an XMM
register, YMM register or ZMM register, which is assumed to contain integer data (packed bytes, words, double-
words, or quadwords). The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory
operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (512-bit
version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
"Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the IA-32 Intel Architecture Software Developer's
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with VMOVNTDQ instructions if multiple proces-
sors might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will
#UD.

Operation
VMOVNTDQ(EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] <- SRC[VL-1:0]
DEST[MAX_VL-1:VL] <- 0




1. ModRM.MOD = 011B required



MOVNTDQ (Legacy and VEX versions)
DEST <- SRC

Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTDQ void _mm512_stream_si512(void * p, __m512i a);
VMOVNTDQ void _mm256_stream_si256 (__m256i * p, __m256i a);
MOVNTDQ void _mm_stream_si128 (__m128i * p, __m128i a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD                     If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: MOVNTI
description:
MOVNTI-Store Doubleword Using Non-Temporal Hint
Opcode                    Instruction                    Op/    64-Bit   Compat/ Description
                                                         En     Mode     Leg Mode
0F C3 /r                  MOVNTI m32, r32                MR     Valid    Valid      Move doubleword from r32 to m32 using non-
                                                                                    temporal hint.
REX.W + 0F C3 /r          MOVNTI m64, r64                MR     Valid    N.E.       Move quadword from r64 to m64 using non-
                                                                                    temporal hint.



                                                 Instruction Operand Encoding
   Op/En              Operand 1                        Operand 2                 Operand 3                   Operand 4
    MR              ModRM:r/m (w)                     ModRM:reg (r)                 NA                          NA


Description
Moves the doubleword integer in the source operand (second operand) to the destination operand (first operand)
using a non-temporal hint to minimize cache pollution during the write to memory. The source operand is a
general-purpose register. The destination operand is a 32-bit memory location.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
"Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTI instructions if multiple processors
might use different memory types to read/write the destination memory locations.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.

Operation
DEST <- SRC;

Intel C/C++ Compiler Intrinsic Equivalent
MOVNTI:        void _mm_stream_si32 (int *p, int a)
MOVNTI:        void _mm_stream_si64(__int64 *p, __int64 a)

SIMD Floating-Point Exceptions
None.

Protected Mode Exceptions
#GP(0)                  For an illegal memory operand effective address in the CS, DS, ES, FS or GS segments.
#SS(0)                  For an illegal address in the SS segment.
#PF(fault-code)         For a page fault.
#UD                     If CPUID.01H:EDX.SSE2[bit 26] = 0.
                        If the LOCK prefix is used.





Real-Address Mode Exceptions
#GP                    If any part of the operand lies outside the effective address space from 0 to FFFFH.
#UD                    If CPUID.01H:EDX.SSE2[bit 26] = 0.
                       If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
Same exceptions as in real address mode.
#PF(fault-code)        For a page fault.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#PF(fault-code)        For a page fault.
#UD                    If CPUID.01H:EDX.SSE2[bit 26] = 0.
                       If the LOCK prefix is used.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.






platform: x86_64
mnem: MOVNTPD
description:
MOVNTPD-Store Packed Double-Precision Floating-Point Values Using Non-Temporal Hint
 Opcode/                         Op /      64/32       CPUID             Description
 Instruction                     En        bit Mode    Feature
                                           Support     Flag
 66 0F 2B /r                     MR        V/V         SSE2              Move packed double-precision values in xmm1 to m128 using
 MOVNTPD m128, xmm1                                                      non-temporal hint.
 VEX.128.66.0F.WIG 2B /r         MR        V/V         AVX               Move packed double-precision values in xmm1 to m128 using
 VMOVNTPD m128, xmm1                                                     non-temporal hint.
 VEX.256.66.0F.WIG 2B /r         MR        V/V         AVX               Move packed double-precision values in ymm1 to m256 using
 VMOVNTPD m256, ymm1                                                     non-temporal hint.
 EVEX.128.66.0F.W1 2B /r         FVM       V/V         AVX512VL          Move packed double-precision values in xmm1 to m128 using
 VMOVNTPD m128, xmm1                                   AVX512F           non-temporal hint.
 EVEX.256.66.0F.W1 2B /r         FVM       V/V         AVX512VL          Move packed double-precision values in ymm1 to m256 using
 VMOVNTPD m256, ymm1                                   AVX512F           non-temporal hint.
 EVEX.512.66.0F.W1 2B /r         FVM       V/V         AVX512F           Move packed double-precision values in zmm1 to m512 using
 VMOVNTPD m512, zmm1                                                     non-temporal hint.



                                                 Instruction Operand Encoding1
       Op/En                 Operand 1                    Operand 2                    Operand 3                    Operand 4
         MR                ModRM:r/m (w)                 ModRM:reg (r)                     NA                           NA
        FVM                ModRM:r/m (w)                 ModRM:reg (r)                     NA                           NA

Description
Moves the packed double-precision floating-point values in the source operand (second operand) to the destination
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The
source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed double-
precision, floating-pointing data. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The
memory operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte
(EVEX.512 encoded version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
"Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the IA-32 Intel Architecture Software Developer's
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPD instructions if multiple processors
might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, VEX.L must be 0; otherwise instructions will
#UD.

Operation
VMOVNTPD (EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] <- SRC[VL-1:0]
DEST[MAX_VL-1:VL] <- 0




1. ModRM.MOD = 011B required



MOVNTPD (Legacy and VEX versions)
DEST <- SRC

Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTPD void _mm512_stream_pd(double * p, __m512d a);
VMOVNTPD void _mm256_stream_pd (double * p, __m256d a);
MOVNTPD void _mm_stream_pd (double * p, __m128d a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE2;
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: MOVNTPS
description:
MOVNTPS-Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint
 Opcode/                         Op /   64/32         CPUID            Description
 Instruction                     En     bit Mode      Feature
                                        Support       Flag
 0F 2B /r                        MR     V/V           SSE              Move packed single-precision values xmm1 to mem using
 MOVNTPS m128, xmm1                                                    non-temporal hint.
 VEX.128.0F.WIG 2B /r            MR     V/V           AVX              Move packed single-precision values xmm1 to mem using
 VMOVNTPS m128, xmm1                                                   non-temporal hint.
 VEX.256.0F.WIG 2B /r            MR     V/V           AVX              Move packed single-precision values ymm1 to mem using
 VMOVNTPS m256, ymm1                                                   non-temporal hint.
 EVEX.128.0F.W0 2B /r            FVM    V/V           AVX512VL         Move packed single-precision values in xmm1 to m128
 VMOVNTPS m128, xmm1                                  AVX512F          using non-temporal hint.
 EVEX.256.0F.W0 2B /r            FVM    V/V           AVX512VL         Move packed single-precision values in ymm1 to m256
 VMOVNTPS m256, ymm1                                  AVX512F          using non-temporal hint.
 EVEX.512.0F.W0 2B /r            FVM    V/V           AVX512F          Move packed single-precision values in zmm1 to m512
 VMOVNTPS m512, zmm1                                                   using non-temporal hint.



                                           Instruction Operand Encoding1
       Op/En              Operand 1                   Operand 2                    Operand 3                     Operand 4
        MR              ModRM:r/m (w)               ModRM:reg (r)                      NA                            NA
        FVM             ModRM:r/m (w)               ModRM:reg (r)                      NA                            NA

Description
Moves the packed single-precision floating-point values in the source operand (second operand) to the destination
operand (first operand) using a non-temporal hint to prevent caching of the data during the write to memory. The
source operand is an XMM register, YMM register or ZMM register, which is assumed to contain packed single-preci-
sion, floating-pointing. The destination operand is a 128-bit, 256-bit or 512-bit memory location. The memory
operand must be aligned on a 16-byte (128-bit version), 32-byte (VEX.256 encoded version) or 64-byte (EVEX.512
encoded version) boundary otherwise a general-protection exception (#GP) will be generated.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
"Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the IA-32 Intel Architecture Software Developer's
Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTPS instructions if multiple processors
might use different memory types to read/write the destination memory locations.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.

Operation
VMOVNTPS (EVEX encoded versions)
VL = 128, 256, 512
DEST[VL-1:0] <- SRC[VL-1:0]
DEST[MAX_VL-1:VL] <- 0




1. ModRM.MOD = 011B required



MOVNTPS
DEST <- SRC

Intel C/C++ Compiler Intrinsic Equivalent
VMOVNTPS void _mm512_stream_ps(float * p, __m512d a);
MOVNTPS void _mm_stream_ps (float * p, __m128d a);
VMOVNTPS void _mm256_stream_ps (float * p, __m256 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type1.SSE; additionally
EVEX-encoded instruction, see Exceptions Type E1NF.
#UD                      If VEX.vvvv != 1111B or EVEX.vvvv != 1111B.






platform: x86_64
mnem: MOVNTQ
description:
MOVNTQ-Store of Quadword Using Non-Temporal Hint
Opcode                   Instruction               Op/   64-Bit   Compat/ Description
                                                   En    Mode     Leg Mode
0F E7 /r                 MOVNTQ m64, mm            MR    Valid    Valid        Move quadword from mm to m64 using non-
                                                                               temporal hint.



                                              Instruction Operand Encoding
   Op/En             Operand 1                   Operand 2                Operand 3                      Operand 4
    MR             ModRM:r/m (w)               ModRM:reg (r)                   NA                           NA


Description
Moves the quadword in the source operand (second operand) to the destination operand (first operand) using a
non-temporal hint to minimize cache pollution during the write to memory. The source operand is an MMX tech-
nology register, which is assumed to contain packed integer data (packed bytes, words, or doublewords). The
destination operand is a 64-bit memory location.
The non-temporal hint is implemented by using a write combining (WC) memory type protocol when writing the
data to memory. Using this protocol, the processor does not write the data into the cache hierarchy, nor does it
fetch the corresponding cache line from memory into the cache hierarchy. The memory type of the region being
written to can override the non-temporal hint, if the memory address specified for the non-temporal store is in an
uncacheable (UC) or write protected (WP) memory region. For more information on non-temporal stores, see
"Caching of Temporal vs. Non-Temporal Data" in Chapter 10 in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 1.
Because the WC protocol uses a weakly-ordered memory consistency model, a fencing operation implemented with
the SFENCE or MFENCE instruction should be used in conjunction with MOVNTQ instructions if multiple processors
might use different memory types to read/write the destination memory locations.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
DEST <- SRC;

Intel C/C++ Compiler Intrinsic Equivalent
MOVNTQ:         void _mm_stream_pi(__m64 * p, __m64 a)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Table 22-8, "Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception," in the Intel 64
and IA-32 Architectures Software Developer's Manual, Volume 3A.






platform: x86_64
mnem: MOVQ
description:
MOVQ-Move Quadword
Opcode/                               Op/ En     64/32-bit CPUID     Description
Instruction                                      Mode      Feature
                                                           Flag
0F 6F /r                              RM         V/V       MMX       Move quadword from mm/m64 to mm.
MOVQ mm, mm/m64
0F 7F /r                              MR         V/V       MMX       Move quadword from mm to mm/m64.
MOVQ mm/m64, mm
F3 0F 7E /r                           RM         V/V       SSE2      Move quadword from xmm2/mem64 to xmm1.
MOVQ xmm1, xmm2/m64
VEX.128.F3.0F.WIG 7E /r               RM         V/V       AVX       Move quadword from xmm2 to xmm1.
VMOVQ xmm1, xmm2/m64
EVEX.128.F3.0F.W1 7E /r               T1S-RM V/V           AVX512F   Move quadword from xmm2/m64 to xmm1.
VMOVQ xmm1, xmm2/m64
66 0F D6 /r                           MR         V/V       SSE2      Move quadword from xmm1 to xmm2/mem64.
MOVQ xmm2/m64, xmm1
VEX.128.66.0F.WIG D6 /r               MR         V/V       AVX       Move quadword from xmm2 register to xmm1/m64.
VMOVQ xmm1/m64, xmm2
EVEX.128.66.0F.W1 D6 /r               T1S-MR V/V           AVX512F   Move quadword from xmm2 register to xmm1/m64.
VMOVQ xmm1/m64, xmm2



                                           Instruction Operand Encoding
  Op/En              Operand 1                 Operand 2                Operand 3                 Operand 4
   RM            ModRM:reg (w)             ModRM:r/m (r)                   NA                        NA
   MR            ModRM:r/m (w)             ModRM:reg (r)                   NA                        NA
 T1S-RM          ModRM:reg (w)             ModRM:r/m (r)                   NA                        NA
 T1S-MR          ModRM:r/m (w)             ModRM:reg (r)                   NA                        NA


Description
Copies a quadword from the source operand (second operand) to the destination operand (first operand). The
source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations.
This instruction can be used to move a quadword between two MMX technology registers or between an MMX tech-
nology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM
register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.
When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM
register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.
In 64-bit mode and if not encoded using VEX/EVEX, use of the REX prefix in the form of REX.R permits this instruc-
tion to access additional registers (XMM8-XMM15).
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
If VMOVQ is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will cause an
#UD exception.





Operation
MOVQ instruction when operating on MMX technology registers and memory locations:
  DEST <- SRC;

MOVQ instruction when source and destination operands are XMM registers:
  DEST[63:0] <- SRC[63:0];
  DEST[127:64] <- 0000000000000000H;

MOVQ instruction when source operand is XMM register and destination
operand is memory location:
   DEST <- SRC[63:0];

MOVQ instruction when source operand is memory location and destination
operand is XMM register:
   DEST[63:0] <- SRC;
   DEST[127:64] <- 0000000000000000H;

VMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0

VMOVQ (VEX.128.66.0F D6) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0

VMOVQ (7E - EVEX encoded version) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[MAX_VL-1:64] <- 0

VMOVQ (D6 - EVEX encoded version) with XMM register source and destination:
DEST[63:0] <- SRC[63:0]
DEST[MAX_VL-1:64] <- 0

VMOVQ (7E) with memory source:
DEST[63:0] <- SRC[63:0]
DEST[VLMAX-1:64] <- 0

VMOVQ (7E - EVEX encoded version) with memory source:
DEST[63:0] <- SRC[63:0]
DEST[:MAX_VL-1:64] <- 0

VMOVQ (D6) with memory dest:
DEST[63:0] <- SRC2[63:0]

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
VMOVQ __m128i _mm_loadu_si64( void * s);
VMOVQ void _mm_storeu_si64( void * d, __m128i s);
MOVQ            m128i _mm_mov_epi64(__m128i a)





SIMD Floating-Point Exceptions
None

Other Exceptions
See Table 22-8, "Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception," in the Intel 64
and IA-32 Architectures Software Developer's Manual, Volume 3B.






platform: x86_64
mnem: MOVQ2DQ
description:
MOVQ2DQ-Move Quadword from MMX Technology to XMM Register
Opcode                  Instruction                  Op/   64-Bit    Compat/ Description
                                                     En    Mode      Leg Mode
F3 0F D6 /r             MOVQ2DQ xmm, mm              RM    Valid     Valid       Move quadword from mmx to low quadword
                                                                                 of xmm.



                                              Instruction Operand Encoding
   Op/En            Operand 1                   Operand 2                    Operand 3                   Operand 4
    RM            ModRM:reg (w)               ModRM:r/m (r)                     NA                          NA


Description
Moves the quadword from the source operand (second operand) to the low quadword of the destination operand
(first operand). The source operand is an MMX technology register and the destination operand is an XMM register.
This instruction causes a transition from x87 FPU to MMX technology operation (that is, the x87 FPU top-of-stack
pointer is set to 0 and the x87 FPU tag word is set to all 0s [valid]). If this instruction is executed while an x87 FPU
floating-point exception is pending, the exception is handled before the MOVQ2DQ instruction is executed.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional registers (XMM8-XMM15).

Operation
DEST[63:0] <- SRC[63:0];
DEST[127:64] <- 00000000000000000H;

Intel C/C++ Compiler Intrinsic Equivalent
MOVQ2DQ:        __128i _mm_movpi64_pi64 ( __m64 a)

SIMD Floating-Point Exceptions
None.

Protected Mode Exceptions
#NM                   If CR0.TS[bit 3] = 1.
#UD                   If CR0.EM[bit 2] = 1.
                      If CR4.OSFXSR[bit 9] = 0.
                      If CPUID.01H:EDX.SSE2[bit 26] = 0.
                      If the LOCK prefix is used.
#MF                   If there is a pending x87 FPU exception.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.




platform: x86_64
mnem: MOVS
description:
MOVS/MOVSB/MOVSW/MOVSD/MOVSQ - Move Data from String to String
  Opcode              Instruction                Op/     64-Bit   Compat/ Description
                                                   En      Mode     Leg Mode
    A4                  MOVS m8, m8                NP      Valid    Valid       For legacy mode, Move byte from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                byte from address (R|E)SI to (R|E)DI.
    A5                  MOVS m16, m16              NP      Valid    Valid       For legacy mode, move word from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                word at address (R|E)SI to (R|E)DI.
    A5                  MOVS m32, m32              NP      Valid    Valid       For legacy mode, move dword from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                dword from address (R|E)SI to (R|E)DI.
    REX.W + A5          MOVS m64, m64              NP      Valid    N.E.        Move qword from address (R|E)SI to (R|E)DI.
    A4                  MOVSB                      NP      Valid    Valid       For legacy mode, Move byte from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                byte from address (R|E)SI to (R|E)DI.
    A5                  MOVSW                      NP      Valid    Valid       For legacy mode, move word from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                word at address (R|E)SI to (R|E)DI.
    A5                  MOVSD                      NP      Valid    Valid       For legacy mode, move dword from address
                                                                                DS:(E)SI to ES:(E)DI. For 64-bit mode move
                                                                                dword from address (R|E)SI to (R|E)DI.
    REX.W + A5          MOVSQ                      NP      Valid    N.E.        Move qword from address (R|E)SI to (R|E)DI.



                                              Instruction Operand Encoding
     Op/En         Operand 1                   Operand 2                    Operand 3                     Operand 4
         NP            NA                         NA                           NA                             NA


Description
Moves the byte, word, or doubleword specified with the second operand (source operand) to the location specified
with the first operand (destination operand). Both the source and destination operands are located in memory. The
address of the source operand is read from the DS:ESI or the DS:SI registers (depending on the address-size attri-
bute of the instruction, 32 or 16, respectively). The address of the destination operand is read from the ES:EDI or
the ES:DI registers (again depending on the address-size attribute of the instruction). The DS segment may be
overridden with a segment override prefix, but the ES segment cannot be overridden.
At the assembly-code level, two forms of this instruction are allowed: the "explicit-operands" form and the "no-
operands" form. The explicit-operands form (specified with the MOVS mnemonic) allows the source and destination
operands to be specified explicitly. Here, the source and destination operands should be symbols that indicate the
size and location of the source value and the destination, respectively. This explicit-operands form is provided to
allow documentation; however, note that the documentation provided by this form can be misleading. That is, the
source and destination operand symbols must specify the correct type (size) of the operands (bytes, words, or
doublewords), but they do not have to specify the correct location. The locations of the source and destination
operands are always specified by the DS:(E)SI and ES:(E)DI registers, which must be loaded correctly before the
move string instruction is executed.
The no-operands form provides "short forms" of the byte, word, and doubleword versions of the MOVS instruc-
tions. Here also DS:(E)SI and ES:(E)DI are assumed to be the source and destination operands, respectively. The
size of the source and destination operands is selected with the mnemonic: MOVSB (byte move), MOVSW (word
move), or MOVSD (doubleword move).
After the move operation, the (E)SI and (E)DI registers are incremented or decremented automatically according
to the setting of the DF flag in the EFLAGS register. (If the DF flag is 0, the (E)SI and (E)DI register are incre-




mented; if the DF flag is 1, the (E)SI and (E)DI registers are decremented.) The registers are incremented or
decremented by 1 for byte operations, by 2 for word operations, or by 4 for doubleword operations.

                                                       NOTE
         To improve performance, more recent processors support modifications to the processor's
         operation during the string store operations initiated with MOVS and MOVSB. See Section 7.3.9.3
         in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 for additional
         information on fast-string operation.
The MOVS, MOVSB, MOVSW, and MOVSD instructions can be preceded by the REP prefix (see "REP/REPE/REPZ
/REPNE/REPNZ-Repeat String Operation Prefix" for a description of the REP prefix) for block moves of ECX bytes,
words, or doublewords.
In 64-bit mode, the instruction's default address size is 64 bits, 32-bit address size is supported using the prefix
67H. The 64-bit addresses are specified by RSI and RDI; 32-bit address are specified by ESI and EDI. Use of the
REX.W prefix promotes doubleword operation to 64 bits. See the summary chart at the beginning of this section for
encoding data and limits.

Operation
DEST <- SRC;

Non-64-bit Mode:

IF (Byte move)
    THEN IF DF = 0
         THEN
              (E)SI <- (E)SI + 1;
              (E)DI <- (E)DI + 1;
         ELSE
              (E)SI <- (E)SI - 1;
              (E)DI <- (E)DI - 1;
         FI;
    ELSE IF (Word move)
         THEN IF DF = 0
              (E)SI <- (E)SI + 2;
              (E)DI <- (E)DI + 2;
              FI;
         ELSE
              (E)SI <- (E)SI - 2;
              (E)DI <- (E)DI - 2;
         FI;
    ELSE IF (Doubleword move)
         THEN IF DF = 0
              (E)SI <- (E)SI + 4;
              (E)DI <- (E)DI + 4;
              FI;
         ELSE
              (E)SI <- (E)SI - 4;
              (E)DI <- (E)DI - 4;
         FI;
FI;
64-bit Mode:

IF (Byte move)
    THEN IF DF = 0
         THEN



                (R|E)SI <- (R|E)SI + 1;
                (R|E)DI <- (R|E)DI + 1;
          ELSE
                (R|E)SI <- (R|E)SI - 1;
                (R|E)DI <- (R|E)DI - 1;
          FI;
      ELSE IF (Word move)
          THEN IF DF = 0
                (R|E)SI <- (R|E)SI + 2;
                (R|E)DI <- (R|E)DI + 2;
                FI;
          ELSE
                (R|E)SI <- (R|E)SI - 2;
                (R|E)DI <- (R|E)DI - 2;
          FI;
      ELSE IF (Doubleword move)
          THEN IF DF = 0
                (R|E)SI <- (R|E)SI + 4;
                (R|E)DI <- (R|E)DI + 4;
                FI;
          ELSE
                (R|E)SI <- (R|E)SI - 4;
                (R|E)DI <- (R|E)DI - 4;
          FI;
      ELSE IF (Quadword move)
          THEN IF DF = 0
                (R|E)SI <- (R|E)SI + 8;
                (R|E)DI <- (R|E)DI + 8;
                FI;
          ELSE
                (R|E)SI <- (R|E)SI - 8;
                (R|E)DI <- (R|E)DI - 8;
          FI;
FI;

Flags Affected
None

Protected Mode Exceptions
#GP(0)                     If the destination is located in a non-writable segment.
                           If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                           If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                     If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made while the
                           current privilege level is 3.
#UD                        If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                        If a memory operand effective address is outside the SS segment limit.
#UD                        If the LOCK prefix is used.


Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: MOVSD
description:
MOVSD-Move or Merge Scalar Double-Precision Floating-Point Value
 Opcode/                                      Op / En   64/32         CPUID     Description
 Instruction                                            bit Mode      Feature
                                                        Support       Flag
 F2 0F 10 /r                                  RM        V/V           SSE2      Move scalar double-precision floating-point value
 MOVSD xmm1, xmm2                                                               from xmm2 to xmm1 register.
 F2 0F 10 /r                                  RM        V/V           SSE2      Load scalar double-precision floating-point value
 MOVSD xmm1, m64                                                                from m64 to xmm1 register.
 F2 0F 11 /r                                  MR        V/V           SSE2      Move scalar double-precision floating-point value
 MOVSD xmm1/m64, xmm2                                                           from xmm2 register to xmm1/m64.
 VEX.NDS.LIG.F2.0F.WIG 10 /r                  RVM       V/V           AVX       Merge scalar double-precision floating-point value
 VMOVSD xmm1, xmm2, xmm3                                                        from xmm2 and xmm3 to xmm1 register.
 VEX.LIG.F2.0F.WIG 10 /r                      XM        V/V           AVX       Load scalar double-precision floating-point value
 VMOVSD xmm1, m64                                                               from m64 to xmm1 register.
 VEX.NDS.LIG.F2.0F.WIG 11 /r                  MVR       V/V           AVX       Merge scalar double-precision floating-point value
 VMOVSD xmm1, xmm2, xmm3                                                        from xmm2 and xmm3 registers to xmm1.
 VEX.LIG.F2.0F.WIG 11 /r                      MR        V/V           AVX       Store scalar double-precision floating-point value
 VMOVSD m64, xmm1                                                               from xmm1 register to m64.
 EVEX.NDS.LIG.F2.0F.W1 10 /r                  RVM       V/V           AVX512F   Merge scalar double-precision floating-point value
 VMOVSD xmm1 {k1}{z}, xmm2, xmm3                                                from xmm2 and xmm3 registers to xmm1 under
                                                                                writemask k1.
 EVEX.LIG.F2.0F.W1 10 /r                      T1S-RM    V/V           AVX512F   Load scalar double-precision floating-point value
 VMOVSD xmm1 {k1}{z}, m64                                                       from m64 to xmm1 register under writemask k1.
 EVEX.NDS.LIG.F2.0F.W1 11 /r                  MVR       V/V           AVX512F   Merge scalar double-precision floating-point value
 VMOVSD xmm1 {k1}{z}, xmm2, xmm3                                                from xmm2 and xmm3 registers to xmm1 under
                                                                                writemask k1.
 EVEX.LIG.F2.0F.W1 11 /r                      T1S-MR    V/V           AVX512F   Store scalar double-precision floating-point value
 VMOVSD m64 {k1}, xmm1                                                          from xmm1 register to m64 under writemask k1.



                                                    Instruction Operand Encoding
       Op/En                  Operand 1                       Operand 2               Operand 3                   Operand 4
         RM                ModRM:reg (r, w)                ModRM:r/m (r)                  NA                          NA
        RVM                 ModRM:reg (w)                   VEX.vvvv (r)            ModRM:r/m (r)                     NA
         MR                 ModRM:r/m (w)                  ModRM:reg (r)                  NA                          NA
         XM                 ModRM:reg (w)                  ModRM:r/m (r)                  NA                          NA
        MVR                 ModRM:r/m (w)                      vvvv (r)             ModRM:reg (r)                     NA
      T1S-RM               ModRM:reg (r, w)                ModRM:r/m (r)                  NA                          NA
      T1S-MR                ModRM:r/m (w)                  ModRM:reg (r)                  NA                          NA





Description
Moves a scalar double-precision floating-point value from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be XMM registers or 64-bit memory locations.
This instruction can be used to move a double-precision floating-point value to and from the low quadword of an
XMM register and a 64-bit memory location, or to move a double-precision floating-point value between the low
quadwords of two XMM registers. The instruction cannot be used to transfer data between memory locations.
Legacy version: When the source and destination operands are XMM registers, bits MAX_VL:64 of the destination
operand remains unchanged. When the source operand is a memory location and destination operand is an XMM
registers, the quadword at bits 127:64 of the destination operand is cleared to all 0s, bits MAX_VL:128 of the desti-
nation operand remains unchanged.
VEX and EVEX encoded register-register syntax: Moves a scalar double-precision floating-point value from the
second source operand (the third operand) to the low quadword element of the destination operand (the first
operand). Bits 127:64 of the destination operand are copied from the first source operand (the second operand).
Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX and EVEX encoded memory store syntax: When the source operand is a memory location and destination
operand is an XMM registers, bits MAX_VL:64 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low quadword of the destination is updated according to the writemask.
Note: For VMOVSD (memory store and load forms), VEX.vvvv and EVEX.vvvv are reserved and must be 1111b,
otherwise instruction will #UD.

Operation
VMOVSD (EVEX.NDS.LIG.F2.0F 10 /r: VMOVSD xmm1, m64 with support for 32 registers)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC[63:0]
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[511:64] <- 0

VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD m64, xmm1 with support for 32 registers)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC[63:0]
    ELSE      *DEST[63:0] remains unchanged*   ; merging-masking
FI;

VMOVSD (EVEX.NDS.LIG.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- SRC2[63:0]
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





MOVSD (128-bit Legacy SSE version: MOVSD XMM1, XMM2)
DEST[63:0] <-SRC[63:0]
DEST[MAX_VL-1:64] (Unmodified)

VMOVSD (VEX.NDS.128.F2.0F 11 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] <-SRC2[63:0]
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, xmm2, xmm3)
DEST[63:0] <-SRC2[63:0]
DEST[127:64] <-SRC1[127:64]
DEST[MAX_VL-1:128] <-0

VMOVSD (VEX.NDS.128.F2.0F 10 /r: VMOVSD xmm1, m64)
DEST[63:0] <-SRC[63:0]
DEST[MAX_VL-1:64] <-0

MOVSD/VMOVSD (128-bit versions: MOVSD m64, xmm1 or VMOVSD m64, xmm1)
DEST[63:0] <-SRC[63:0]

MOVSD (128-bit Legacy SSE version: MOVSD XMM1, m64)
DEST[63:0] <-SRC[63:0]
DEST[127:64] <-0
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMOVSD __m128d _mm_mask_load_sd(__m128d s, __mmask8 k, double * p);
VMOVSD __m128d _mm_maskz_load_sd( __mmask8 k, double * p);
VMOVSD __m128d _mm_mask_move_sd(__m128d sh, __mmask8 k, __m128d sl, __m128d a);
VMOVSD __m128d _mm_maskz_move_sd( __mmask8 k, __m128d s, __m128d a);
VMOVSD void _mm_mask_store_sd(double * p, __mmask8 k, __m128d s);
MOVSD __m128d _mm_load_sd (double *p)
MOVSD void _mm_store_sd (double *p, __m128d a)
MOVSD __m128d _mm_move_sd ( __m128d a, __m128d b)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                      If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E10.






platform: x86_64
mnem: MOVSHDUP
description:
MOVSHDUP-Replicate Single FP Values
 Opcode/                           Op /        64/32        CPUID         Description
 Instruction                       En          bit Mode     Feature
                                               Support      Flag
 F3 0F 16 /r                       RM          V/V          SSE3          Move odd index single-precision floating-point values from
 MOVSHDUP xmm1, xmm2/m128                                                 xmm2/mem and duplicate each element into xmm1.
 VEX.128.F3.0F.WIG 16 /r           RM          V/V          AVX           Move odd index single-precision floating-point values from
 VMOVSHDUP xmm1, xmm2/m128                                                xmm2/mem and duplicate each element into xmm1.
 VEX.256.F3.0F.WIG 16 /r           RM          V/V          AVX           Move odd index single-precision floating-point values from
 VMOVSHDUP ymm1, ymm2/m256                                                ymm2/mem and duplicate each element into ymm1.
 EVEX.128.F3.0F.W0 16 /r           FVM         V/V          AVX512VL      Move odd index single-precision floating-point values from
 VMOVSHDUP xmm1 {k1}{z},                                    AVX512F       xmm2/m128 and duplicate each element into xmm1 under
 xmm2/m128                                                                writemask.
 EVEX.256.F3.0F.W0 16 /r           FVM         V/V          AVX512VL      Move odd index single-precision floating-point values from
 VMOVSHDUP ymm1 {k1}{z},                                    AVX512F       ymm2/m256 and duplicate each element into ymm1 under
 ymm2/m256                                                                writemask.
 EVEX.512.F3.0F.W0 16 /r           FVM         V/V          AVX512F       Move odd index single-precision floating-point values from
 VMOVSHDUP zmm1 {k1}{z},                                                  zmm2/m512 and duplicate each element into zmm1 under
 zmm2/m512                                                                writemask.



                                                 Instruction Operand Encoding
       Op/En               Operand 1                       Operand 2                    Operand 3                  Operand 4
         RM             ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA
        FVM             ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA

Description
Duplicates odd-indexed single-precision floating-point values from the source operand (the second operand) to
adjacent element pair in the destination operand (the first operand). See Figure 4-3. The source operand is an
XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the destination operand is an XMM, YMM
or ZMM register.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.




                     SRC      X7          X6         X5         X4        X3       X2        X1        X0




                     DEST     X7          X7         X5         X5        X3       X3        X1        X1


                                               Figure 4-3. MOVSHDUP Operation


Operation
VMOVSHDUP (EVEX encoded versions)




(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_SRC[31:0] <- SRC[63:32]
TMP_SRC[63:32] <- SRC[63:32]
TMP_SRC[95:64] <- SRC[127:96]
TMP_SRC[127:96] <- SRC[127:96]
IF VL >= 256
    TMP_SRC[159:128] <- SRC[191:160]
    TMP_SRC[191:160] <- SRC[191:160]
    TMP_SRC[223:192] <- SRC[255:224]
    TMP_SRC[255:224] <- SRC[255:224]
FI;
IF VL >= 512
    TMP_SRC[287:256] <- SRC[319:288]
    TMP_SRC[319:288] <- SRC[319:288]
    TMP_SRC[351:320] <- SRC[383:352]
    TMP_SRC[383:352] <- SRC[383:352]
    TMP_SRC[415:384] <- SRC[447:416]
    TMP_SRC[447:416] <- SRC[447:416]
    TMP_SRC[479:448] <- SRC[511:480]
    TMP_SRC[511:480] <- SRC[511:480]
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVSHDUP (VEX.256 encoded version)
DEST[31:0] <- SRC[63:32]
DEST[63:32] <- SRC[63:32]
DEST[95:64] <- SRC[127:96]
DEST[127:96] <- SRC[127:96]
DEST[159:128] <- SRC[191:160]
DEST[191:160] <- SRC[191:160]
DEST[223:192] <- SRC[255:224]
DEST[255:224] <- SRC[255:224]
DEST[MAX_VL-1:256] <- 0

VMOVSHDUP (VEX.128 encoded version)
DEST[31:0] <- SRC[63:32]
DEST[63:32] <- SRC[63:32]
DEST[95:64] <- SRC[127:96]
DEST[127:96] <- SRC[127:96]
DEST[MAX_VL-1:128] <- 0
MOVSHDUP (128-bit Legacy SSE version)
DEST[31:0] <-SRC[63:32]



DEST[63:32] <-SRC[63:32]
DEST[95:64] <-SRC[127:96]
DEST[127:96] <-SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMOVSHDUP __m512 _mm512_movehdup_ps( __m512 a);
VMOVSHDUP __m512 _mm512_mask_movehdup_ps(__m512 s, __mmask16 k, __m512 a);
VMOVSHDUP __m512 _mm512_maskz_movehdup_ps( __mmask16 k, __m512 a);
VMOVSHDUP __m256 _mm256_mask_movehdup_ps(__m256 s, __mmask8 k, __m256 a);
VMOVSHDUP __m256 _mm256_maskz_movehdup_ps( __mmask8 k, __m256 a);
VMOVSHDUP __m128 _mm_mask_movehdup_ps(__m128 s, __mmask8 k, __m128 a);
VMOVSHDUP __m128 _mm_maskz_movehdup_ps( __mmask8 k, __m128 a);
VMOVSHDUP __m256 _mm256_movehdup_ps (__m256 a);
VMOVSHDUP __m128 _mm_movehdup_ps (__m128 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
#UD                    If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVSLDUP
description:
MOVSLDUP-Replicate Single FP Values
 Opcode/                               Op /        64/32       CPUID          Description
 Instruction                           En          bit Mode    Feature
                                                   Support     Flag
 F3 0F 12 /r                           A           V/V         SSE3           Move even index single-precision floating-point values from
 MOVSLDUP xmm1, xmm2/m128                                                     xmm2/mem and duplicate each element into xmm1.
 VEX.128.F3.0F.WIG 12 /r               RM          V/V         AVX            Move even index single-precision floating-point values from
 VMOVSLDUP xmm1, xmm2/m128                                                    xmm2/mem and duplicate each element into xmm1.
 VEX.256.F3.0F.WIG 12 /r               RM          V/V         AVX            Move even index single-precision floating-point values from
 VMOVSLDUP ymm1, ymm2/m256                                                    ymm2/mem and duplicate each element into ymm1.
 EVEX.128.F3.0F.W0 12 /r               FVM         V/V         AVX512VL       Move even index single-precision floating-point values from
 VMOVSLDUP xmm1 {k1}{z},                                       AVX512F        xmm2/m128 and duplicate each element into xmm1 under
 xmm2/m128                                                                    writemask.
 EVEX.256.F3.0F.W0 12 /r               FVM         V/V         AVX512VL       Move even index single-precision floating-point values from
 VMOVSLDUP ymm1 {k1}{z},                                       AVX512F        ymm2/m256 and duplicate each element into ymm1 under
 ymm2/m256                                                                    writemask.
 EVEX.512.F3.0F.W0 12 /r               FVM         V/V         AVX512F        Move even index single-precision floating-point values from
 VMOVSLDUP zmm1 {k1}{z},                                                      zmm2/m512 and duplicate each element into zmm1 under
 zmm2/m512                                                                    writemask.



                                                     Instruction Operand Encoding
        Op/En                  Operand 1                       Operand 2                    Operand 3                  Operand 4
         RM                 ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA
        FVM                 ModRM:reg (w)                     ModRM:r/m (r)                    NA                          NA

Description
Duplicates even-indexed single-precision floating-point values from the source operand (the second operand). See
Figure 4-4. The source operand is an XMM, YMM or ZMM register or 128, 256 or 512-bit memory location and the
destination operand is an XMM, YMM or ZMM register.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
VEX.128 encoded version: Bits (MAX_VL-1:128) of the destination register are zeroed.
VEX.256 encoded version: Bits (MAX_VL-1:256) of the destination register are zeroed.
EVEX encoded version: The destination operand is updated at 32-bit granularity according to the writemask.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b otherwise instructions will #UD.




                         SRC      X7          X6         X5          X4       X3       X2        X1        X0




                         DEST     X6          X6         X4          X4       X2       X2        X0        X0


                                                   Figure 4-4. MOVSLDUP Operation





Operation
VMOVSLDUP (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
TMP_SRC[31:0] <- SRC[31:0]
TMP_SRC[63:32] <- SRC[31:0]
TMP_SRC[95:64] <- SRC[95:64]
TMP_SRC[127:96] <- SRC[95:64]
IF VL >= 256
    TMP_SRC[159:128] <- SRC[159:128]
    TMP_SRC[191:160] <- SRC[159:128]
    TMP_SRC[223:192] <- SRC[223:192]
    TMP_SRC[255:224] <- SRC[223:192]
FI;
IF VL >= 512
    TMP_SRC[287:256] <- SRC[287:256]
    TMP_SRC[319:288] <- SRC[287:256]
    TMP_SRC[351:320] <- SRC[351:320]
    TMP_SRC[383:352] <- SRC[351:320]
    TMP_SRC[415:384] <- SRC[415:384]
    TMP_SRC[447:416] <- SRC[415:384]
    TMP_SRC[479:448] <- SRC[479:448]
    TMP_SRC[511:480] <- SRC[479:448]
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVSLDUP (VEX.256 encoded version)
DEST[31:0] <- SRC[31:0]
DEST[63:32] <- SRC[31:0]
DEST[95:64] <- SRC[95:64]
DEST[127:96] <- SRC[95:64]
DEST[159:128] <- SRC[159:128]
DEST[191:160] <- SRC[159:128]
DEST[223:192] <- SRC[223:192]
DEST[255:224] <- SRC[223:192]
DEST[MAX_VL-1:256] <- 0

VMOVSLDUP (VEX.128 encoded version)
DEST[31:0] <- SRC[31:0]
DEST[63:32] <- SRC[31:0]
DEST[95:64] <- SRC[95:64]
DEST[127:96] <- SRC[95:64]
DEST[MAX_VL-1:128] <- 0



MOVSLDUP (128-bit Legacy SSE version)
DEST[31:0] <-SRC[31:0]
DEST[63:32] <-SRC[31:0]
DEST[95:64] <-SRC[95:64]
DEST[127:96] <-SRC[95:64]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMOVSLDUP __m512 _mm512_moveldup_ps( __m512 a);
VMOVSLDUP __m512 _mm512_mask_moveldup_ps(__m512 s, __mmask16 k, __m512 a);
VMOVSLDUP __m512 _mm512_maskz_moveldup_ps( __mmask16 k, __m512 a);
VMOVSLDUP __m256 _mm256_mask_moveldup_ps(__m256 s, __mmask8 k, __m256 a);
VMOVSLDUP __m256 _mm256_maskz_moveldup_ps( __mmask8 k, __m256 a);
VMOVSLDUP __m128 _mm_mask_moveldup_ps(__m128 s, __mmask8 k, __m128 a);
VMOVSLDUP __m128 _mm_maskz_moveldup_ps( __mmask8 k, __m128 a);
VMOVSLDUP __m256 _mm256_moveldup_ps (__m256 a);
VMOVSLDUP __m128 _mm_moveldup_ps (__m128 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4;
EVEX-encoded instruction, see Exceptions Type E4NF.nb.
#UD                     If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVSS
description:
MOVSS-Move or Merge Scalar Single-Precision Floating-Point Value
 Opcode/                                Op / En   64/32         CPUID       Description
 Instruction                                      bit Mode      Feature
                                                  Support       Flag
 F3 0F 10 /r                            RM        V/V           SSE         Merge scalar single-precision floating-point value
 MOVSS xmm1, xmm2                                                           from xmm2 to xmm1 register.
 F3 0F 10 /r                            RM        V/V           SSE         Load scalar single-precision floating-point value from
 MOVSS xmm1, m32                                                            m32 to xmm1 register.
 VEX.NDS.LIG.F3.0F.WIG 10 /r            RVM       V/V           AVX         Merge scalar single-precision floating-point value
 VMOVSS xmm1, xmm2, xmm3                                                    from xmm2 and xmm3 to xmm1 register
 VEX.LIG.F3.0F.WIG 10 /r                XM        V/V           AVX         Load scalar single-precision floating-point value from
 VMOVSS xmm1, m32                                                           m32 to xmm1 register.
 F3 0F 11 /r                            MR        V/V           SSE         Move scalar single-precision floating-point value
 MOVSS xmm2/m32, xmm1                                                       from xmm1 register to xmm2/m32.
 VEX.NDS.LIG.F3.0F.WIG 11 /r            MVR       V/V           AVX         Move scalar single-precision floating-point value
 VMOVSS xmm1, xmm2, xmm3                                                    from xmm2 and xmm3 to xmm1 register.
 VEX.LIG.F3.0F.WIG 11 /r                MR        V/V           AVX         Move scalar single-precision floating-point value
 VMOVSS m32, xmm1                                                           from xmm1 register to m32.
 EVEX.NDS.LIG.F3.0F.W0 10 /r            RVM       V/V           AVX512F     Move scalar single-precision floating-point value
 VMOVSS xmm1 {k1}{z}, xmm2, xmm3                                            from xmm2 and xmm3 to xmm1 register under
                                                                            writemask k1.
 EVEX.LIG.F3.0F.W0 10 /r                T1S-RM    V/V           AVX512F     Move scalar single-precision floating-point values
 VMOVSS xmm1 {k1}{z}, m32                                                   from m32 to xmm1 under writemask k1.
 EVEX.NDS.LIG.F3.0F.W0 11 /r            MVR       V/V           AVX512F     Move scalar single-precision floating-point value
 VMOVSS xmm1 {k1}{z}, xmm2, xmm3                                            from xmm2 and xmm3 to xmm1 register under
                                                                            writemask k1.
 EVEX.LIG.F3.0F.W0 11 /r                T1S-MR    V/V           AVX512F     Move scalar single-precision floating-point values
 VMOVSS m32 {k1}, xmm1                                                      from xmm1 to m32 under writemask k1.



                                              Instruction Operand Encoding
      Op/En             Operand 1                   Operand 2                     Operand 3                     Operand 4
       RM            ModRM:reg (r, w)             ModRM:r/m (r)                       NA                            NA
      RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                       NA
       MR            ModRM:r/m (w)                ModRM:reg (r)                       NA                            NA
       XM            ModRM:reg (w)                ModRM:r/m (r)                       NA                            NA
      MVR            ModRM:r/m (w)                   vvvv (r)                   ModRM:reg (r)                       NA
     T1S-RM          ModRM:reg (r, w)             ModRM:r/m (r)                       NA                            NA
     T1S-MR          ModRM:r/m (w)                ModRM:reg (r)                       NA                            NA





Description
Moves a scalar single-precision floating-point value from the source operand (second operand) to the destination
operand (first operand). The source and destination operands can be XMM registers or 32-bit memory locations.
This instruction can be used to move a single-precision floating-point value to and from the low doubleword of an
XMM register and a 32-bit memory location, or to move a single-precision floating-point value between the low
doublewords of two XMM registers. The instruction cannot be used to transfer data between memory locations.
Legacy version: When the source and destination operands are XMM registers, bits (MAX_VL-1:32) of the corre-
sponding destination register are unmodified. When the source operand is a memory location and destination
operand is an XMM registers, Bits (127:32) of the destination operand is cleared to all 0s, bits MAX_VL:128 of the
destination operand remains unchanged.
VEX and EVEX encoded register-register syntax: Moves a scalar single-precision floating-point value from the
second source operand (the third operand) to the low doubleword element of the destination operand (the first
operand). Bits 127:32 of the destination operand are copied from the first source operand (the second operand).
Bits (MAX_VL-1:128) of the corresponding destination register are zeroed.
VEX and EVEX encoded memory load syntax: When the source operand is a memory location and destination
operand is an XMM registers, bits MAX_VL:32 of the destination operand is cleared to all 0s.
EVEX encoded versions: The low doubleword of the destination is updated according to the writemask.
Note: For memory store form instruction "VMOVSS m32, xmm1", VEX.vvvv is reserved and must be 1111b other-
wise instruction will #UD. For memory store form instruction "VMOVSS mv {k1}, xmm1", EVEX.vvvv is reserved
and must be 1111b otherwise instruction will #UD.
Software should ensure VMOVSS is encoded with VEX.L=0. Encoding VMOVSS with VEX.L=1 may encounter
unpredictable behavior across different processor generations.

Operation
VMOVSS (EVEX.NDS.LIG.F3.0F.W0 11 /r when the source operand is memory and the destination is an XMM register)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC[31:0]
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[511:32] <- 0

VMOVSS (EVEX.NDS.LIG.F3.0F.W0 10 /r when the source operand is an XMM register and the destination is memory)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC[31:0]
    ELSE      *DEST[31:0] remains unchanged*   ; merging-masking
FI;





VMOVSS (EVEX.NDS.LIG.F3.0F.W0 10/11 /r where the source and destination are XMM registers)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- SRC2[31:0]
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

MOVSS (Legacy SSE version when the source and destination operands are both XMM registers)
DEST[31:0] <-SRC[31:0]
DEST[MAX_VL-1:32] (Unmodified)

VMOVSS (VEX.NDS.128.F3.0F 11 /r where the destination is an XMM register)
DEST[31:0] <-SRC2[31:0]
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

VMOVSS (VEX.NDS.128.F3.0F 10 /r where the source and destination are XMM registers)
DEST[31:0] <-SRC2[31:0]
DEST[127:32] <-SRC1[127:32]
DEST[MAX_VL-1:128] <-0

VMOVSS (VEX.NDS.128.F3.0F 10 /r when the source operand is memory and the destination is an XMM register)
DEST[31:0] <-SRC[31:0]
DEST[MAX_VL-1:32] <-0

MOVSS/VMOVSS (when the source operand is an XMM register and the destination is memory)
DEST[31:0] <-SRC[31:0]

MOVSS (Legacy SSE version when the source operand is memory and the destination is an XMM register)
DEST[31:0] <-SRC[31:0]
DEST[127:32] <-0
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VMOVSS __m128 _mm_mask_load_ss(__m128 s, __mmask8 k, float * p);
VMOVSS __m128 _mm_maskz_load_ss( __mmask8 k, float * p);
VMOVSS __m128 _mm_mask_move_ss(__m128 sh, __mmask8 k, __m128 sl, __m128 a);
VMOVSS __m128 _mm_maskz_move_ss( __mmask8 k, __m128 s, __m128 a);
VMOVSS void _mm_mask_store_ss(float * p, __mmask8 k, __m128 a);
MOVSS __m128 _mm_load_ss(float * p)
MOVSS void_mm_store_ss(float * p, __m128 a)
MOVSS __m128 _mm_move_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 5; additionally
#UD                      If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E10.






platform: x86_64
mnem: MOVSX
description:
MOVSX/MOVSXD-Move with Sign-Extension
Opcode                    Instruction               Op/     64-Bit    Compat/ Description
                                                    En      Mode      Leg Mode
0F BE /r                  MOVSX r16, r/m8           RM      Valid     Valid       Move byte to word with sign-extension.
0F BE /r                  MOVSX r32, r/m8           RM      Valid     Valid       Move byte to doubleword with sign-
                                                                                  extension.
REX + 0F BE /r            MOVSX r64, r/m8*          RM      Valid     N.E.        Move byte to quadword with sign-extension.
0F BF /r                  MOVSX r32, r/m16          RM      Valid     Valid       Move word to doubleword, with sign-
                                                                                  extension.
REX.W + 0F BF /r          MOVSX r64, r/m16          RM      Valid     N.E.        Move word to quadword with sign-extension.
REX.W** + 63 /r           MOVSXD r64, r/m32         RM      Valid     N.E.        Move doubleword to quadword with sign-
                                                                                  extension.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
** The use of MOVSXD without REX.W in 64-bit mode is discouraged, Regular MOV should be used instead of using MOVSXD without
   REX.W.



                                              Instruction Operand Encoding
   Op/En            Operand 1                   Operand 2                     Operand 3                    Operand 4
    RM             ModRM:reg (w)              ModRM:r/m (r)                      NA                           NA


Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and
sign extends the value to 16 or 32 bits (see Figure 7-6 in the Intel 64 and IA-32 Architectures Software Devel-
oper's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bits. See the summary chart at the
beginning of this section for encoding data and limits.

Operation
DEST <- SignExtend(SRC);

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                      If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.





Real-Address Mode Exceptions
#GP                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                   If a memory operand effective address is outside the SS segment limit.
#UD                   If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#UD                   If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                If the memory address is in a non-canonical form.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: MOVUPD
description:
MOVUPD-Move Unaligned Packed Double-Precision Floating-Point Values
 Opcode/                               Op / En   64/32      CPUID            Description
 Instruction                                     bit Mode   Feature
                                                 Support    Flag
 66 0F 10 /r                           RM        V/V        SSE2             Move unaligned packed double-precision floating-
 MOVUPD xmm1, xmm2/m128                                                      point from xmm2/mem to xmm1.
 66 0F 11 /r                           MR        V/V        SSE2             Move unaligned packed double-precision floating-
 MOVUPD xmm2/m128, xmm1                                                      point from xmm1 to xmm2/mem.
 VEX.128.66.0F.WIG 10 /r               RM        V/V        AVX              Move unaligned packed double-precision floating-
 VMOVUPD xmm1, xmm2/m128                                                     point from xmm2/mem to xmm1.
 VEX.128.66.0F.WIG 11 /r               MR        V/V        AVX              Move unaligned packed double-precision floating-
 VMOVUPD xmm2/m128, xmm1                                                     point from xmm1 to xmm2/mem.
 VEX.256.66.0F.WIG 10 /r               RM        V/V        AVX              Move unaligned packed double-precision floating-
 VMOVUPD ymm1, ymm2/m256                                                     point from ymm2/mem to ymm1.
 VEX.256.66.0F.WIG 11 /r               MR        V/V        AVX              Move unaligned packed double-precision floating-
 VMOVUPD ymm2/m256, ymm1                                                     point from ymm1 to ymm2/mem.
 EVEX.128.66.0F.W1 10 /r               FVM-RM    V/V        AVX512VL         Move unaligned packed double-precision floating-
 VMOVUPD xmm1 {k1}{z}, xmm2/m128                            AVX512F          point from xmm2/m128 to xmm1 using
                                                                             writemask k1.
 EVEX.128.66.0F.W1 11 /r               FVM-MR    V/V        AVX512VL         Move unaligned packed double-precision floating-
 VMOVUPD xmm2/m128 {k1}{z}, xmm1                            AVX512F          point from xmm1 to xmm2/m128 using
                                                                             writemask k1.
 EVEX.256.66.0F.W1 10 /r               FVM-RM    V/V        AVX512VL         Move unaligned packed double-precision floating-
 VMOVUPD ymm1 {k1}{z}, ymm2/m256                            AVX512F          point from ymm2/m256 to ymm1 using
                                                                             writemask k1.
 EVEX.256.66.0F.W1 11 /r               FVM-MR    V/V        AVX512VL         Move unaligned packed double-precision floating-
 VMOVUPD ymm2/m256 {k1}{z}, ymm1                            AVX512F          point from ymm1 to ymm2/m256 using
                                                                             writemask k1.
 EVEX.512.66.0F.W1 10 /r               FVM-RM    V/V        AVX512F          Move unaligned packed double-precision floating-
 VMOVUPD zmm1 {k1}{z}, zmm2/m512                                             point values from zmm2/m512 to zmm1 using
                                                                             writemask k1.
 EVEX.512.66.0F.W1 11 /r               FVM-MR    V/V        AVX512F          Move unaligned packed double-precision floating-
 VMOVUPD zmm2/m512 {k1}{z}, zmm1                                             point values from zmm1 to zmm2/m512 using
                                                                             writemask k1.



                                            Instruction Operand Encoding
       Op/En             Operand 1                 Operand 2                     Operand 3                   Operand 4
        RM             ModRM:reg (w)             ModRM:r/m (r)                      NA                           NA
        MR             ModRM:r/m (w)             ModRM:reg (r)                      NA                           NA
      FVM-RM           ModRM:reg (w)             ModRM:r/m (r)                      NA                           NA
      RVM-MR           ModRM:r/m (w)             ModRM:reg (r)                      NA                           NA

Description
Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a float64 memory
location, to store the contents of a ZMM register into a memory. The destination operand is updated according to
the writemask.





VEX.256 encoded version:
Moves 256 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. Bits (MAX_VL-1:256) of the destination register are zeroed.


128-bit versions:
Moves 128 bits of packed double-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned on a 16-byte
boundary without causing a general-protection exception (#GP) to be generated
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.

Operation
VMOVUPD (EVEX encoded versions, register-copy form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVUPD (EVEX encoded versions, store-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i]<- SRC[i+63:i]
         ELSE *DEST[i+63:i] remains unchanged*           ; merging-masking

   FI;
ENDFOR;





VMOVUPD (EVEX encoded versions, load-form)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- SRC[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE DEST[i+63:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVUPD (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVUPD (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]

VMOVUPD (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

MOVUPD (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)

(V)MOVUPD (128-bit store-form version)
DEST[127:0] <- SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVUPD __m512d _mm512_loadu_pd( void * s);
VMOVUPD __m512d _mm512_mask_loadu_pd(__m512d a, __mmask8 k, void * s);
VMOVUPD __m512d _mm512_maskz_loadu_pd( __mmask8 k, void * s);
VMOVUPD void _mm512_storeu_pd( void * d, __m512d a);
VMOVUPD void _mm512_mask_storeu_pd( void * d, __mmask8 k, __m512d a);
VMOVUPD __m256d _mm256_mask_loadu_pd(__m256d s, __mmask8 k, void * m);
VMOVUPD __m256d _mm256_maskz_loadu_pd( __mmask8 k, void * m);
VMOVUPD void _mm256_mask_storeu_pd( void * d, __mmask8 k, __m256d a);
VMOVUPD __m128d _mm_mask_loadu_pd(__m128d s, __mmask8 k, void * m);
VMOVUPD __m128d _mm_maskz_loadu_pd( __mmask8 k, void * m);
VMOVUPD void _mm_mask_storeu_pd( void * d, __mmask8 k, __m128d a);
MOVUPD __m256d _mm256_loadu_pd (double * p);
MOVUPD void _mm256_storeu_pd( double *p, __m256d a);
MOVUPD __m128d _mm_loadu_pd (double * p);
MOVUPD void _mm_storeu_pd( double *p, __m128d a);

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
Note treatment of #AC varies; additionally
#UD                     If VEX.vvvv != 1111B.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: MOVUPS
description:
MOVUPS-Move Unaligned Packed Single-Precision Floating-Point Values
 Opcode/                               Op / En    64/32          CPUID        Description
 Instruction                                      bit Mode       Feature
                                                  Support        Flag
 0F 10 /r                              RM         V/V            SSE          Move unaligned packed single-precision
 MOVUPS xmm1, xmm2/m128                                                       floating-point from xmm2/mem to xmm1.
 0F 11 /r                              MR         V/V            SSE          Move unaligned packed single-precision
 MOVUPS xmm2/m128, xmm1                                                       floating-point from xmm1 to xmm2/mem.
 VEX.128.0F.WIG 10 /r                  RM         V/V            AVX          Move unaligned packed single-precision
 VMOVUPS xmm1, xmm2/m128                                                      floating-point from xmm2/mem to xmm1.
 VEX.128.0F 11.WIG /r                  MR         V/V            AVX          Move unaligned packed single-precision
 VMOVUPS xmm2/m128, xmm1                                                      floating-point from xmm1 to xmm2/mem.
 VEX.256.0F 10.WIG /r                  RM         V/V            AVX          Move unaligned packed single-precision
 VMOVUPS ymm1, ymm2/m256                                                      floating-point from ymm2/mem to ymm1.
 VEX.256.0F 11.WIG /r                  MR         V/V            AVX          Move unaligned packed single-precision
 VMOVUPS ymm2/m256, ymm1                                                      floating-point from ymm1 to ymm2/mem.
 EVEX.128.0F.W0 10 /r                  FVM-RM     V/V            AVX512VL     Move unaligned packed single-precision
 VMOVUPS xmm1 {k1}{z}, xmm2/m128                                 AVX512F      floating-point values from xmm2/m128 to
                                                                              xmm1 using writemask k1.
 EVEX.256.0F.W0 10 /r                  FVM-RM     V/V            AVX512VL     Move unaligned packed single-precision
 VMOVUPS ymm1 {k1}{z}, ymm2/m256                                 AVX512F      floating-point values from ymm2/m256 to
                                                                              ymm1 using writemask k1.
 EVEX.512.0F.W0 10 /r                  FVM-RM     V/V            AVX512F      Move unaligned packed single-precision
 VMOVUPS zmm1 {k1}{z}, zmm2/m512                                              floating-point values from zmm2/m512 to
                                                                              zmm1 using writemask k1.
 EVEX.128.0F.W0 11 /r                  FVM-MR     V/V            AVX512VL     Move unaligned packed single-precision
 VMOVUPS xmm2/m128 {k1}{z}, xmm1                                 AVX512F      floating-point values from xmm1 to
                                                                              xmm2/m128 using writemask k1.
 EVEX.256.0F.W0 11 /r                  FVM-MR     V/V            AVX512VL     Move unaligned packed single-precision
 VMOVUPS ymm2/m256 {k1}{z}, ymm1                                 AVX512F      floating-point values from ymm1 to
                                                                              ymm2/m256 using writemask k1.
 EVEX.512.0F.W0 11 /r                  FVM-MR     V/V            AVX512F      Move unaligned packed single-precision
 VMOVUPS zmm2/m512 {k1}{z}, zmm1                                              floating-point values from zmm1 to
                                                                              zmm2/m512 using writemask k1.



                                         Instruction Operand Encoding
       Op/En             Operand 1                Operand 2                     Operand 3                   Operand 4
        RM             ModRM:reg (w)             ModRM:r/m (r)                     NA                           NA
        MR             ModRM:r/m (w)             ModRM:reg (r)                     NA                           NA
      FVM-RM           ModRM:reg (w)             ModRM:r/m (r)                     NA                           NA
      RVM-MR           ModRM:r/m (w)             ModRM:reg (r)                     NA                           NA

Description
Note: VEX.vvvv and EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
EVEX.512 encoded version:
Moves 512 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a ZMM register from a 512-bit float32
memory location, to store the contents of a ZMM register into memory. The destination operand is updated
according to the writemask.





VEX.256 and EVEX.256 encoded versions:
Moves 256 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load a YMM register from a 256-bit memory
location, to store the contents of a YMM register into a 256-bit memory location, or to move data between two YMM
registers. Bits (MAX_VL-1:256) of the destination register are zeroed.


128-bit versions:
Moves 128 bits of packed single-precision floating-point values from the source operand (second operand) to the
destination operand (first operand). This instruction can be used to load an XMM register from a 128-bit memory
location, to store the contents of an XMM register into a 128-bit memory location, or to move data between two
XMM registers.
128-bit Legacy SSE version: Bits (MAX_VL-1:128) of the corresponding destination register remain unchanged.
When the source or destination operand is a memory operand, the operand may be unaligned without causing a
general-protection exception (#GP) to be generated.
VEX.128 and EVEX.128 encoded versions: Bits (MAX_VL-1:128) of the destination register are zeroed.

Operation
VMOVUPS (EVEX encoded versions, register-copy form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVUPS (EVEX encoded versions, store-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i]<- SRC[i+31:i]
         ELSE *DEST[i+31:i] remains unchanged*           ; merging-masking
    FI;
ENDFOR;





VMOVUPS (EVEX encoded versions, load-form)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- SRC[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE DEST[i+31:i] <- 0          ; zeroing-masking
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VMOVUPS (VEX.256 encoded version, load - and register copy)
DEST[255:0] <- SRC[255:0]
DEST[MAX_VL-1:256] <- 0

VMOVUPS (VEX.256 encoded version, store-form)
DEST[255:0] <- SRC[255:0]

VMOVUPS (VEX.128 encoded version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] <- 0

MOVUPS (128-bit load- and register-copy- form Legacy SSE version)
DEST[127:0] <- SRC[127:0]
DEST[MAX_VL-1:128] (Unmodified)

(V)MOVUPS (128-bit store-form version)
DEST[127:0] <- SRC[127:0]

Intel C/C++ Compiler Intrinsic Equivalent
VMOVUPS __m512 _mm512_loadu_ps( void * s);
VMOVUPS __m512 _mm512_mask_loadu_ps(__m512 a, __mmask16 k, void * s);
VMOVUPS __m512 _mm512_maskz_loadu_ps( __mmask16 k, void * s);
VMOVUPS void _mm512_storeu_ps( void * d, __m512 a);
VMOVUPS void _mm512_mask_storeu_ps( void * d, __mmask8 k, __m512 a);
VMOVUPS __m256 _mm256_mask_loadu_ps(__m256 a, __mmask8 k, void * s);
VMOVUPS __m256 _mm256_maskz_loadu_ps( __mmask8 k, void * s);
VMOVUPS void _mm256_mask_storeu_ps( void * d, __mmask8 k, __m256 a);
VMOVUPS __m128 _mm_mask_loadu_ps(__m128 a, __mmask8 k, void * s);
VMOVUPS __m128 _mm_maskz_loadu_ps( __mmask8 k, void * s);
VMOVUPS void _mm_mask_storeu_ps( void * d, __mmask8 k, __m128 a);
MOVUPS __m256 _mm256_loadu_ps ( float * p);
MOVUPS void _mm256 _storeu_ps( float *p, __m256 a);
MOVUPS __m128 _mm_loadu_ps ( float * p);
MOVUPS void _mm_storeu_ps( float *p, __m128 a);

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
Note treatment of #AC varies;
EVEX-encoded instruction, see Exceptions Type E4.nb.
#UD                      If EVEX.vvvv != 1111B or VEX.vvvv != 1111B.






platform: x86_64
mnem: MOVZX
description:
MOVZX-Move with Zero-Extend
 Opcode                   Instruction                   Op/    64-Bit      Compat/ Description
                                                        En     Mode        Leg Mode
 0F B6 /r                 MOVZX r16, r/m8               RM     Valid       Valid        Move byte to word with zero-extension.
 0F B6 /r                 MOVZX r32, r/m8               RM     Valid       Valid        Move byte to doubleword, zero-extension.
 REX.W + 0F B6 /r         MOVZX r64, r/m8*              RM     Valid       N.E.         Move byte to quadword, zero-extension.
 0F B7 /r                 MOVZX r32, r/m16              RM     Valid       Valid        Move word to doubleword, zero-extension.
 REX.W + 0F B7 /r         MOVZX r64, r/m16              RM     Valid       N.E.         Move word to quadword, zero-extension.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if the REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En             Operand 1                     Operand 2                       Operand 3                     Operand 4
    RM              ModRM:reg (w)                ModRM:r/m (r)                        NA                             NA


Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and
zero extends the value. The size of the converted value depends on the operand-size attribute.
In 64-bit mode, the instruction's default operation size is 32 bits. Use of the REX.R prefix permits access to addi-
tional registers (R8-R15). Use of the REX.W prefix promotes operation to 64 bit operands. See the summary chart
at the beginning of this section for encoding data and limits.

Operation
DEST <- ZeroExtend(SRC);

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used.





Virtual-8086 Mode Exceptions
#GP(0)                If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made.
#UD                   If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                If the memory address is in a non-canonical form.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: MPSADBW
description:
MPSADBW - Compute Multiple Packed Sums of Absolute Difference
Opcode/                                          Op/      64/32-bit CPUID       Description
Instruction                                      En       Mode      Feature
                                                                    Flag
66 0F 3A 42 /r ib                                RMI      V/V       SSE4_1      Sums absolute 8-bit integer difference of
MPSADBW xmm1, xmm2/m128, imm8                                                   adjacent groups of 4 byte integers in xmm1
                                                                                and xmm2/m128 and writes the results in
                                                                                xmm1. Starting offsets within xmm1 and
                                                                                xmm2/m128 are determined by imm8.
VEX.NDS.128.66.0F3A.WIG 42 /r ib                 RVMI V/V           AVX         Sums absolute 8-bit integer difference of
VMPSADBW xmm1, xmm2, xmm3/m128, imm8                                            adjacent groups of 4 byte integers in xmm2
                                                                                and xmm3/m128 and writes the results in
                                                                                xmm1. Starting offsets within xmm2 and
                                                                                xmm3/m128 are determined by imm8.
VEX.NDS.256.66.0F3A.WIG 42 /r ib                 RVMI V/V           AVX2        Sums absolute 8-bit integer difference of
VMPSADBW ymm1, ymm2, ymm3/m256, imm8                                            adjacent groups of 4 byte integers in xmm2
                                                                                and ymm3/m128 and writes the results in
                                                                                ymm1. Starting offsets within ymm2 and
                                                                                xmm3/m128 are determined by imm8.



                                            Instruction Operand Encoding
   Op/En             Operand 1              Operand 2                     Operand 3                      Operand 4
    RMI         ModRM:reg (r, w)          ModRM:r/m (r)                      imm8                            NA
   RVMI             ModRM:reg (w)          VEX.vvvv (r)                ModRM:r/m (r)                        imm8


Description
(V)MPSADBW calculates packed word results of sum-absolute-difference (SAD) of unsigned bytes from two blocks
of 32-bit dword elements, using two select fields in the immediate byte to select the offsets of the two blocks within
the first source operand and the second operand. Packed SAD word results are calculated within each 128-bit lane.
Each SAD word result is calculated between a stationary block_2 (whose offset within the second source operand
is selected by a two bit select control, multiplied by 32 bits) and a sliding block_1 at consecutive byte-granular
position within the first source operand. The offset of the first 32-bit block of block_1 is selectable using a one bit
select control, multiplied by 32 bits.
128-bit Legacy SSE version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.
Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source operand
and destination operand are the same. The first source and destination operands are XMM registers. The second
source operand is either an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. Bits 7:3 of the immediate byte are ignored.
VEX.128 encoded version: Imm8[1:0]*32 specifies the bit offset of block_2 within the second source operand.
Imm[2]*32 specifies the initial bit offset of the block_1 within the first source operand. The first source and desti-
nation operands are XMM registers. The second source operand is either an XMM register or a 128-bit memory
location. Bits (127:128) of the corresponding YMM register are zeroed. Bits 7:3 of the immediate byte are ignored.
VEX.256 encoded version: The sum-absolute-difference (SAD) operation is repeated 8 times for MPSADW between
the same block_2 (fixed offset within the second source operand) and a variable block_1 (offset is shifted by 8 bits
for each SAD operation) in the first source operand. Each 16-bit result of eight SAD operations between block_2
and block_1 is written to the respective word in the lower 128 bits of the destination operand.
Additionally, VMPSADBW performs another eight SAD operations on block_4 of the second source operand and
block_3 of the first source operand. (Imm8[4:3]*32 + 128) specifies the bit offset of block_4 within the second
source operand. (Imm[5]*32+128) specifies the initial bit offset of the block_3 within the first source operand.
Each 16-bit result of eight SAD operations between block_4 and block_3 is written to the respective word in the
upper 128 bits of the destination operand.





The first source operand is a YMM register. The second source register can be a YMM register or a 256-bit memory
location. The destination operand is a YMM register. Bits 7:6 of the immediate byte are ignored.
Note: If VMPSADBW is encoded with VEX.L= 1, an attempt to execute the instruction encoded with VEX.L= 1 will
cause an #UD exception.




                                                                            Imm[4:3]*32+128
                             255              224               192                                128



                              Src2                                     Abs. Diff.     Imm[5]*32+128




                              Src1
                                                                                    Sum

                                   255                                                144         128


                            Destination



                                                                             Imm[1:0]*32
                               127             96                64                                   0



                                Src2                                    Abs. Diff.        Imm[2]*32




                                Src1
                                                                                     Sum

                                     127                                                  16          0



                             Destination




                                           Figure 4-5. 256-bit VMPSADBW Operation





Operation
VMPSADBW (VEX.256 encoded version)
BLK2_OFFSET <- imm8[1:0]*32
BLK1_OFFSET <- imm8[2]*32
SRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 <-SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]
SRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]

TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3





TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

BLK2_OFFSET <- imm8[4:3]*32 + 128
BLK1_OFFSET <- imm8[5]*32 + 128
SRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 <- SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]

SRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]

TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[143:128] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <-ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[159:144] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[175:160] <- TEMP0 + TEMP1 + TEMP2 + TEMP3



TEMP0 <-ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[191:176] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[207:192] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[223:208] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[239:224] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[255:240] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

VMPSADBW (VEX.128 encoded version)
BLK2_OFFSET <- imm8[1:0]*32
BLK1_OFFSET <- imm8[2]*32
SRC1_BYTE0 <- SRC1[BLK1_OFFSET+7:BLK1_OFFSET]
SRC1_BYTE1 <- SRC1[BLK1_OFFSET+15:BLK1_OFFSET+8]
SRC1_BYTE2 <- SRC1[BLK1_OFFSET+23:BLK1_OFFSET+16]
SRC1_BYTE3 <- SRC1[BLK1_OFFSET+31:BLK1_OFFSET+24]
SRC1_BYTE4 <- SRC1[BLK1_OFFSET+39:BLK1_OFFSET+32]
SRC1_BYTE5 <- SRC1[BLK1_OFFSET+47:BLK1_OFFSET+40]
SRC1_BYTE6 <- SRC1[BLK1_OFFSET+55:BLK1_OFFSET+48]
SRC1_BYTE7 <- SRC1[BLK1_OFFSET+63:BLK1_OFFSET+56]
SRC1_BYTE8 <- SRC1[BLK1_OFFSET+71:BLK1_OFFSET+64]
SRC1_BYTE9 <- SRC1[BLK1_OFFSET+79:BLK1_OFFSET+72]
SRC1_BYTE10 <- SRC1[BLK1_OFFSET+87:BLK1_OFFSET+80]

SRC2_BYTE0 <-SRC2[BLK2_OFFSET+7:BLK2_OFFSET]
SRC2_BYTE1 <- SRC2[BLK2_OFFSET+15:BLK2_OFFSET+8]
SRC2_BYTE2 <- SRC2[BLK2_OFFSET+23:BLK2_OFFSET+16]
SRC2_BYTE3 <- SRC2[BLK2_OFFSET+31:BLK2_OFFSET+24]





TEMP0 <- ABS(SRC1_BYTE0 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE1 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE2 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE3 - SRC2_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE1 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE2 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE3 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE4 - SRC2_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE2 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE3 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE4 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE5 - SRC2_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE3 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE4 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE5 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE6 - SRC2_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE4 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE5 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE6 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE7 - SRC2_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE5 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE6 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE7 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE8 - SRC2_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE6 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE7 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE8 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE9 - SRC2_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS(SRC1_BYTE7 - SRC2_BYTE0)
TEMP1 <- ABS(SRC1_BYTE8 - SRC2_BYTE1)
TEMP2 <- ABS(SRC1_BYTE9 - SRC2_BYTE2)
TEMP3 <- ABS(SRC1_BYTE10 - SRC2_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] <- 0





MPSADBW (128-bit Legacy SSE version)
SRC_OFFSET <- imm8[1:0]*32
DEST_OFFSET <- imm8[2]*32
DEST_BYTE0 <- DEST[DEST_OFFSET+7:DEST_OFFSET]
DEST_BYTE1 <- DEST[DEST_OFFSET+15:DEST_OFFSET+8]
DEST_BYTE2 <- DEST[DEST_OFFSET+23:DEST_OFFSET+16]
DEST_BYTE3 <- DEST[DEST_OFFSET+31:DEST_OFFSET+24]
DEST_BYTE4 <- DEST[DEST_OFFSET+39:DEST_OFFSET+32]
DEST_BYTE5 <- DEST[DEST_OFFSET+47:DEST_OFFSET+40]
DEST_BYTE6 <- DEST[DEST_OFFSET+55:DEST_OFFSET+48]
DEST_BYTE7 <- DEST[DEST_OFFSET+63:DEST_OFFSET+56]
DEST_BYTE8 <- DEST[DEST_OFFSET+71:DEST_OFFSET+64]
DEST_BYTE9 <- DEST[DEST_OFFSET+79:DEST_OFFSET+72]
DEST_BYTE10 <- DEST[DEST_OFFSET+87:DEST_OFFSET+80]

SRC_BYTE0 <- SRC[SRC_OFFSET+7:SRC_OFFSET]
SRC_BYTE1 <- SRC[SRC_OFFSET+15:SRC_OFFSET+8]
SRC_BYTE2 <- SRC[SRC_OFFSET+23:SRC_OFFSET+16]
SRC_BYTE3 <- SRC[SRC_OFFSET+31:SRC_OFFSET+24]

TEMP0 <- ABS( DEST_BYTE0 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE1 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE2 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE3 - SRC_BYTE3)
DEST[15:0] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE1 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE2 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE3 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE4 - SRC_BYTE3)
DEST[31:16] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE2 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE3 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE4 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE5 - SRC_BYTE3)
DEST[47:32] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE3 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE4 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE5 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE6 - SRC_BYTE3)
DEST[63:48] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE4 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE5 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE6 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE7 - SRC_BYTE3)
DEST[79:64] <- TEMP0 + TEMP1 + TEMP2 + TEMP3





TEMP0 <- ABS( DEST_BYTE5 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE6 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE7 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE8 - SRC_BYTE3)
DEST[95:80] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE6 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE7 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE8 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE9 - SRC_BYTE3)
DEST[111:96] <- TEMP0 + TEMP1 + TEMP2 + TEMP3

TEMP0 <- ABS( DEST_BYTE7 - SRC_BYTE0)
TEMP1 <- ABS( DEST_BYTE8 - SRC_BYTE1)
TEMP2 <- ABS( DEST_BYTE9 - SRC_BYTE2)
TEMP3 <- ABS( DEST_BYTE10 - SRC_BYTE3)
DEST[127:112] <- TEMP0 + TEMP1 + TEMP2 + TEMP3
DEST[VLMAX-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
(V)MPSADBW:      __m128i _mm_mpsadbw_epu8 (__m128i s1, __m128i s2, const int mask);
VMPSADBW:         __m256i _mm256_mpsadbw_epu8 (__m256i s1, __m256i s2, const int mask);

Flags Affected
None

Other Exceptions
See Exceptions Type 4; additionally
#UD                     If VEX.L = 1.






