# instructions

platform: x86
mnem: PMAXUD
description:
PMAXUD  -  Maximum of Packed Unsigned Dword Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 3F /r PMAXUD xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed unsigned dword integers
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 3F /r VPMAXUD| RVM  | V/V                   | AVX               | Compare packed unsigned dword integers
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | maximum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 3F /r VPMAXUD| RVM  | V/V                   | AVX2              | Compare packed unsigned dword integers
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m256 and store packed
|                                      |      |                       |                   | maximum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed unsigned dword integers in the destination operand (first operand)
and the source operand (second operand), and returns the maximum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[31:0] > SRC[31:0])
  THEN DEST[31:0] <- DEST[31:0];
  ELSE DEST[31:0] <- SRC[31:0]; FI;
IF (DEST[63:32] > SRC[63:32])
  THEN DEST[63:32] <- DEST[63:32];
  ELSE DEST[63:32] <- SRC[63:32]; FI;
IF (DEST[95:64] > SRC[95:64])
  THEN DEST[95:64] <- DEST[95:64];
  ELSE DEST[95:64] <- SRC[95:64]; FI;
IF (DEST[127:96] > SRC[127:96])
  THEN DEST[127:96] <- DEST[127:96];
  ELSE DEST[127:96] <- SRC[127:96]; FI;
VPMAXUD (VEX.128 encoded version)
  IF SRC1[31:0] > SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
  IF SRC1[127:95] > SRC2[127:95] THEN
     DEST[127:95] <- SRC1[127:95];
  ELSE
     DEST[127:95] <- SRC2[127:95]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXUD (VEX.256 encoded version)
  IF SRC1[31:0] > SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
  IF SRC1[255:224] > SRC2[255:224] THEN
     DEST[255:224] <- SRC1[255:224];
  ELSE
     DEST[255:224] <- SRC2[255:224]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMAXUD:| __m128i _mm_max_epu32 ( __m128i a, __m128i
|           | b);                                       
| VPMAXUD:  | __m256i _mm256_max_epu32 ( __m256i a,     
|           | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMAXUW
description:
PMAXUW  -  Maximum of Packed Word Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 38 3E /r PMAXUW xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed unsigned word integers  
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed 
|                                      |      |                       |                   | maximum values in xmm1.                
| VEX.NDS.128.66.0F38.WIG 3E/r VPMAXUW | RVM  | V/V                   | AVX               | Compare packed unsigned word integers  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm3/m128 and xmm2 and store maximum
|                                      |      |                       |                   | packed values in xmm1.                 
| VEX.NDS.256.66.0F38.WIG 3E /r VPMAXUW| RVM  | V/V                   | AVX2              | Compare packed unsigned word integers  
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm3/m256 and ymm2 and store maximum
|                                      |      |                       |                   | packed values in ymm1.                 

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed unsigned word integers in the destination operand (first operand)
and the source operand (second operand), and returns the maximum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed.

VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[15:0] > SRC[15:0])
  THEN DEST[15:0] <- DEST[15:0];
  ELSE DEST[15:0] <- SRC[15:0]; FI;
IF (DEST[31:16] > SRC[31:16])
  THEN DEST[31:16] <- DEST[31:16];
  ELSE DEST[31:16] <- SRC[31:16]; FI;
IF (DEST[47:32] > SRC[47:32])
  THEN DEST[47:32] <- DEST[47:32];
  ELSE DEST[47:32] <- SRC[47:32]; FI;
IF (DEST[63:48] > SRC[63:48])
  THEN DEST[63:48] <- DEST[63:48];
  ELSE DEST[63:48] <- SRC[63:48]; FI;
IF (DEST[79:64] > SRC[79:64])
  THEN DEST[79:64] <- DEST[79:64];
  ELSE DEST[79:64] <- SRC[79:64]; FI;
IF (DEST[95:80] > SRC[95:80])
  THEN DEST[95:80] <- DEST[95:80];
  ELSE DEST[95:80] <- SRC[95:80]; FI;
IF (DEST[111:96] > SRC[111:96])
  THEN DEST[111:96] <- DEST[111:96];
  ELSE DEST[111:96] <- SRC[111:96]; FI;
IF (DEST[127:112] > SRC[127:112])
  THEN DEST[127:112] <- DEST[127:112];
  ELSE DEST[127:112] <- SRC[127:112]; FI;
VPMAXUW (VEX.128 encoded version)
  IF SRC1[15:0] > SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF SRC1[127:112] >SRC2[127:112] THEN
     DEST[127:112] <- SRC1[127:112];
  ELSE
     DEST[127:112] <- SRC2[127:112]; FI;
DEST[VLMAX-1:128] <- 0
VPMAXUW (VEX.256 encoded version)
  IF SRC1[15:0] > SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 15th words in source and destination operands *)
  IF SRC1[255:240] >SRC2[255:240] THEN
     DEST[255:240] <- SRC1[255:240];
  ELSE
     DEST[255:240] <- SRC2[255:240]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMAXUW:| __m128i _mm_max_epu16 ( __m128i a, __m128i
|           | b);                                       
| VPMAXUW:  | __m256i _mm256_max_epu16 ( __m256i a,     
|           | __m256i b)                                

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMINSB
description:
PMINSB  -  Minimum of Packed Signed Byte Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 38 /r PMINSB xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed signed byte integers   
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 38 /r VPMINSB| RVM  | V/V                   | AVX               | Compare packed signed byte integers   
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 38 /r VPMINSB| RVM  | V/V                   | AVX2              | Compare packed signed byte integers   
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m256 and store packed
|                                      |      |                       |                   | minimum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed signed byte integers in the destination operand (first operand)
and the source operand (second operand), and returns the minimum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[7:0] < SRC[7:0])
  THEN DEST[7:0] <- DEST[7:0];
  ELSE DEST[7:0] <- SRC[7:0]; FI;
IF (DEST[15:8] < SRC[15:8])
  THEN DEST[15:8] <- DEST[15:8];
  ELSE DEST[15:8] <- SRC[15:8]; FI;
IF (DEST[23:16] < SRC[23:16])
  THEN DEST[23:16] <- DEST[23:16];
  ELSE DEST[23:16] <- SRC[23:16]; FI;
IF (DEST[31:24] < SRC[31:24])
  THEN DEST[31:24] <- DEST[31:24];
  ELSE DEST[31:24] <- SRC[31:24]; FI;
IF (DEST[39:32] < SRC[39:32])
  THEN DEST[39:32] <- DEST[39:32];
  ELSE DEST[39:32] <- SRC[39:32]; FI;
IF (DEST[47:40] < SRC[47:40])
  THEN DEST[47:40] <- DEST[47:40];
  ELSE DEST[47:40] <- SRC[47:40]; FI;
IF (DEST[55:48] < SRC[55:48])
  THEN DEST[55:48] <- DEST[55:48];
  ELSE DEST[55:48] <- SRC[55:48]; FI;
IF (DEST[63:56] < SRC[63:56])
  THEN DEST[63:56] <- DEST[63:56];
  ELSE DEST[63:56] <- SRC[63:56]; FI;
IF (DEST[71:64] < SRC[71:64])
  THEN DEST[71:64] <- DEST[71:64];
  ELSE DEST[71:64] <- SRC[71:64]; FI;
IF (DEST[79:72] < SRC[79:72])
  THEN DEST[79:72] <- DEST[79:72];
  ELSE DEST[79:72] <- SRC[79:72]; FI;
IF (DEST[87:80] < SRC[87:80])
  THEN DEST[87:80] <- DEST[87:80];
  ELSE DEST[87:80] <- SRC[87:80]; FI;
IF (DEST[95:88] < SRC[95:88])
  THEN DEST[95:88] <- DEST[95:88];
  ELSE DEST[95:88] <- SRC[95:88]; FI;
IF (DEST[103:96] < SRC[103:96])
  THEN DEST[103:96] <- DEST[103:96];
  ELSE DEST[103:96] <- SRC[103:96]; FI;
IF (DEST[111:104] < SRC[111:104])
  THEN DEST[111:104] <- DEST[111:104];
  ELSE DEST[111:104] <- SRC[111:104]; FI;
IF (DEST[119:112] < SRC[119:112])
  THEN DEST[119:112] <- DEST[119:112];
  ELSE DEST[119:112] <- SRC[119:112]; FI;
IF (DEST[127:120] < SRC[127:120])
  THEN DEST[127:120] <- DEST[127:120];
  ELSE DEST[127:120] <- SRC[127:120]; FI;
VPMINSB (VEX.128 encoded version)
  IF SRC1[7:0] < SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[7:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF SRC1[127:120] < SRC2[127:120] THEN
     DEST[127:120] <- SRC1[127:120];
  ELSE
     DEST[127:120] <- SRC2[127:120]; FI;
DEST[VLMAX-1:128] <- 0
VPMINSB (VEX.256 encoded version)
  IF SRC1[7:0] < SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[15:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
  IF SRC1[255:248] < SRC2[255:248] THEN
     DEST[255:248] <- SRC1[255:248];
  ELSE
     DEST[255:248] <- SRC2[255:248]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMINSB:| __m128i _mm_min_epi8 ( __m128i a, __m128i
|           | b);                                      
| VPMINSB:  | __m256i _mm256_min_epi8 ( __m256i a,     
|           | __m256i b);                              

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMINSD
description:
PMINSD  -  Minimum of Packed Dword Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 39 /r PMINSD xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed signed dword integers  
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 39 /r VPMINSD| RVM  | V/V                   | AVX               | Compare packed signed dword integers  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 39 /r VPMINSD| RVM  | V/V                   | AVX2              | Compare packed signed dword integers  
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m128 and store packed
|                                      |      |                       |                   | minimum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed signed dword integers in the destination operand (first operand)
and the source operand (second operand), and returns the minimum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[31:0] < SRC[31:0])
  THEN DEST[31:0] <- DEST[31:0];
  ELSE DEST[31:0] <- SRC[31:0]; FI;
IF (DEST[63:32] < SRC[63:32])
  THEN DEST[63:32] <- DEST[63:32];
  ELSE DEST[63:32] <- SRC[63:32]; FI;
IF (DEST[95:64] < SRC[95:64])
  THEN DEST[95:64] <- DEST[95:64];
  ELSE DEST[95:64] <- SRC[95:64]; FI;
IF (DEST[127:96] < SRC[127:96])
  THEN DEST[127:96] <- DEST[127:96];
  ELSE DEST[127:96] <- SRC[127:96]; FI;
VPMINSD (VEX.128 encoded version)
  IF SRC1[31:0] < SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
  IF SRC1[127:95] < SRC2[127:95] THEN
     DEST[127:95] <- SRC1[127:95];
  ELSE
     DEST[127:95] <- SRC2[127:95]; FI;
DEST[VLMAX-1:128] <- 0
VPMINSD (VEX.256 encoded version)
  IF SRC1[31:0] < SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
  IF SRC1[255:224] < SRC2[255:224] THEN
     DEST[255:224] <- SRC1[255:224];
  ELSE
     DEST[255:224] <- SRC2[255:224]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMINSD:| __m128i _mm_min_epi32 ( __m128i a, __m128i
|           | b);                                       
| VPMINSD:  | __m256i _mm256_min_epi32 (__m256i a,      
|           | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMINSW
description:
PMINSW - Minimum of Packed Signed Word Integers:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F EA /r1 PMINSW mm1, mm2/m64      | RM   | V/V                   | SSE               | Compare signed word integers in mm2/m64  
|                                    |      |                       |                   | and mm1 and return minimum values.       
| 66 0F EA /r PMINSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare signed word integers in xmm2/m128
|                                    |      |                       |                   | and xmm1 and return minimum values.      
| VEX.NDS.128.66.0F.WIG EA /r VPMINSW| RVM  | V/V                   | AVX               | Compare packed signed word integers      
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm3/m128 and xmm2 and return packed  
|                                    |      |                       |                   | minimum values in xmm1.                  
| VEX.NDS.256.66.0F.WIG EA /r VPMINSW| RVM  | V/V                   | AVX2              | Compare packed signed word integers      
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm3/m256 and ymm2 and return packed  
|                                    |      |                       |                   | minimum values in ymm1.                  
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD compare of the packed signed word integers in the destination
operand (first operand) and the source operand (second operand), and returns
the minimum value for each pair of word integers to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand can be an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMINSW (64-bit operands)
  IF DEST[15:0] < SRC[15:0] THEN
     DEST[15:0] <- DEST[15:0];
  ELSE
     DEST[15:0] <- SRC[15:0]; FI;
  (* Repeat operation for 2nd and 3rd words in source and destination operands *)
  IF DEST[63:48] < SRC[63:48] THEN
     DEST[63:48] <- DEST[63:48];
  ELSE
     DEST[63:48] <- SRC[63:48]; FI;
PMINSW (128-bit operands)
  IF DEST[15:0] < SRC[15:0] THEN
     DEST[15:0] <- DEST[15:0];
  ELSE
     DEST[15:0] <- SRC[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF DEST[127:112] < SRC/m64[127:112] THEN
     DEST[127:112] <- DEST[127:112];
  ELSE
     DEST[127:112] <- SRC[127:112]; FI;
VPMINSW (VEX.128 encoded version)
  IF SRC1[15:0] < SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF SRC1[127:112] < SRC2[127:112] THEN
     DEST[127:112] <- SRC1[127:112];
  ELSE
     DEST[127:112] <- SRC2[127:112]; FI;
DEST[VLMAX-1:128] <- 0
VPMINSW (VEX.256 encoded version)
  IF SRC1[15:0] < SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 15th words in source and destination operands *)
  IF SRC1[255:240] < SRC2[255:240] THEN
     DEST[255:240] <- SRC1[255:240];
  ELSE
     DEST[255:240] <- SRC2[255:240]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMINSW:   | __m64 _mm_min_pi16 (__m64 a, __m64 b)     
| (V)PMINSW:| __m128i _mm_min_epi16 ( __m128i a, __m128i
|           | b)                                        
| VPMINSW:  | __m256i _mm256_min_epi16 ( __m256i a,     
|           | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.                       
| #MF| (64-bit operations only) If there is
|    | a pending x87 FPU exception.        


platform: x86
mnem: PMINUB
description:
PMINUB - Minimum of Packed Unsigned Byte Integers:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F DA /r1 PMINUB mm1, mm2/m64      | RM   | V/V                   | SSE               | Compare unsigned byte integers in mm2/m64  
|                                    |      |                       |                   | and mm1 and returns minimum values.        
| 66 0F DA /r PMINUB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Compare unsigned byte integers in xmm2/m128
|                                    |      |                       |                   | and xmm1 and returns minimum values.       
| VEX.NDS.128.66.0F.WIG DA /r VPMINUB| RVM  | V/V                   | AVX               | Compare packed unsigned byte integers      
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm2 and xmm3/m128 and store packed     
|                                    |      |                       |                   | minimum values in xmm1.                    
| VEX.NDS.256.66.0F.WIG DA /r VPMINUB| RVM  | V/V                   | AVX2              | Compare packed unsigned byte integers      
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm2 and ymm3/m256 and store packed     
|                                    |      |                       |                   | minimum values in ymm1.                    
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD compare of the packed unsigned byte integers in the destination
operand (first operand) and the source operand (second operand), and returns
the minimum value for each pair of byte integers to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand can be an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand can be an YMM register or
a 256-bit memory location. The first source and destination operands are YMM
registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMINUB (for 64-bit operands)
  IF DEST[7:0] < SRC[17:0] THEN
     DEST[7:0] <- DEST[7:0];
  ELSE
     DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 7th bytes in source and destination operands *)
  IF DEST[63:56] < SRC[63:56] THEN
     DEST[63:56] <- DEST[63:56];
  ELSE
     DEST[63:56] <- SRC[63:56]; FI;
PMINUB (for 128-bit operands)
  IF DEST[7:0] < SRC[17:0] THEN
     DEST[7:0] <- DEST[7:0];
  ELSE
     DEST[7:0] <- SRC[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF DEST[127:120] < SRC[127:120] THEN
     DEST[127:120] <- DEST[127:120];
  ELSE
     DEST[127:120] <- SRC[127:120]; FI;
VPMINUB (VEX.128 encoded version)
VPMINUB instruction for 128-bit operands:
  IF SRC1[7:0] < SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[7:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 15th bytes in source and destination operands *)
  IF SRC1[127:120] < SRC2[127:120] THEN
     DEST[127:120] <- SRC1[127:120];
  ELSE
     DEST[127:120] <- SRC2[127:120]; FI;
DEST[VLMAX-1:128] <- 0
VPMINUB (VEX.256 encoded version)
VPMINUB instruction for 128-bit operands:
  IF SRC1[7:0] < SRC2[7:0] THEN
     DEST[7:0] <- SRC1[7:0];
  ELSE
     DEST[15:0] <- SRC2[7:0]; FI;
  (* Repeat operation for 2nd through 31st bytes in source and destination operands *)
  IF SRC1[255:248] < SRC2[255:248] THEN
     DEST[255:248] <- SRC1[255:248];
  ELSE
     DEST[255:248] <- SRC2[255:248]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMINUB:   | __m64 _m_min_pu8 (__m64 a, __m64 b)      
| (V)PMINUB:| __m128i _mm_min_epu8 ( __m128i a, __m128i
|           | b)                                       
| VPMINUB:  | __m256i _mm256_min_epu8 ( __m256i a,     
|           | __m256i b)                               

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMINUD
description:
PMINUD  -  Minimum of Packed Dword Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 3B /r PMINUD xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed unsigned dword integers
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.128.66.0F38.WIG 3B /r VPMINUD| RVM  | V/V                   | AVX               | Compare packed unsigned dword integers
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store packed
|                                      |      |                       |                   | minimum values in xmm1.               
| VEX.NDS.256.66.0F38.WIG 3B /r VPMINUD| RVM  | V/V                   | AVX2              | Compare packed unsigned dword integers
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m256 and store packed
|                                      |      |                       |                   | minimum values in ymm1.               

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed unsigned dword integers in the destination operand (first operand)
and the source operand (second operand), and returns the minimum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[31:0] < SRC[31:0])
  THEN DEST[31:0] <- DEST[31:0];
  ELSE DEST[31:0] <- SRC[31:0]; FI;
IF (DEST[63:32] < SRC[63:32])
  THEN DEST[63:32] <- DEST[63:32];
  ELSE DEST[63:32] <- SRC[63:32]; FI;
IF (DEST[95:64] < SRC[95:64])
  THEN DEST[95:64] <- DEST[95:64];
  ELSE DEST[95:64] <- SRC[95:64]; FI;
IF (DEST[127:96] < SRC[127:96])
  THEN DEST[127:96] <- DEST[127:96];
  ELSE DEST[127:96] <- SRC[127:96]; FI;
VPMINUD (VEX.128 encoded version)
VPMINUD instruction for 128-bit operands:
  IF SRC1[31:0] < SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 3rd dwords in source and destination operands *)
  IF SRC1[127:95] < SRC2[127:95] THEN
     DEST[127:95] <- SRC1[127:95];
  ELSE
     DEST[127:95] <- SRC2[127:95]; FI;
DEST[VLMAX-1:128] <- 0
VPMINUD (VEX.256 encoded version)
VPMINUD instruction for 128-bit operands:
  IF SRC1[31:0] < SRC2[31:0] THEN
     DEST[31:0] <- SRC1[31:0];
  ELSE
     DEST[31:0] <- SRC2[31:0]; FI;
  (* Repeat operation for 2nd through 7th dwords in source and destination operands *)
  IF SRC1[255:224] < SRC2[255:224] THEN
     DEST[255:224] <- SRC1[255:224];
  ELSE
     DEST[255:224] <- SRC2[255:224]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMINUD:| __m128i _mm_min_epu32 ( __m128i a, __m128i
|           | b);                                       
| VPMINUD:  | __m256i _mm256_min_epu32 ( __m256i a,     
|           | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMINUW
description:
PMINUW  -  Minimum of Packed Word Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 38 3A /r PMINUW xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Compare packed unsigned word integers  
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store packed 
|                                      |      |                       |                   | minimum values in xmm1.                
| VEX.NDS.128.66.0F38.WIG 3A/r VPMINUW | RVM  | V/V                   | AVX               | Compare packed unsigned word integers  
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm3/m128 and xmm2 and return packed
|                                      |      |                       |                   | minimum values in xmm1.                
| VEX.NDS.256.66.0F38.WIG 3A /r VPMINUW| RVM  | V/V                   | AVX2              | Compare packed unsigned word integers  
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm3/m256 and ymm2 and return packed
|                                      |      |                       |                   | minimum values in ymm1.                

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Compares packed unsigned word integers in the destination operand (first operand)
and the source operand (second operand), and returns the minimum for each packed
value in the destination operand. 128-bit Legacy SSE version: The first source
and destination operands are XMM registers. The second source operand is an
XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

IF (DEST[15:0] < SRC[15:0])
  THEN DEST[15:0] <- DEST[15:0];
  ELSE DEST[15:0] <- SRC[15:0]; FI;
IF (DEST[31:16] < SRC[31:16])
  THEN DEST[31:16] <- DEST[31:16];
  ELSE DEST[31:16] <- SRC[31:16]; FI;
IF (DEST[47:32] < SRC[47:32])
  THEN DEST[47:32] <- DEST[47:32];
  ELSE DEST[47:32] <- SRC[47:32]; FI;
IF (DEST[63:48] < SRC[63:48])
  THEN DEST[63:48] <- DEST[63:48];
  ELSE DEST[63:48] <- SRC[63:48]; FI;
IF (DEST[79:64] < SRC[79:64])
  THEN DEST[79:64] <- DEST[79:64];
  ELSE DEST[79:64] <- SRC[79:64]; FI;
IF (DEST[95:80] < SRC[95:80])
  THEN DEST[95:80] <- DEST[95:80];
  ELSE DEST[95:80] <- SRC[95:80]; FI;
IF (DEST[111:96] < SRC[111:96])
  THEN DEST[111:96] <- DEST[111:96];
  ELSE DEST[111:96] <- SRC[111:96]; FI;
IF (DEST[127:112] < SRC[127:112])
  THEN DEST[127:112] <- DEST[127:112];
  ELSE DEST[127:112] <- SRC[127:112]; FI;
VPMINUW (VEX.128 encoded version)
VPMINUW instruction for 128-bit operands:
  IF SRC1[15:0] < SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 7th words in source and destination operands *)
  IF SRC1[127:112] < SRC2[127:112] THEN
     DEST[127:112] <- SRC1[127:112];
  ELSE
     DEST[127:112] <- SRC2[127:112]; FI;
DEST[VLMAX-1:128] <- 0
VPMINUW (VEX.256 encoded version)
VPMINUW instruction for 128-bit operands:
  IF SRC1[15:0] < SRC2[15:0] THEN
     DEST[15:0] <- SRC1[15:0];
  ELSE
     DEST[15:0] <- SRC2[15:0]; FI;
  (* Repeat operation for 2nd through 15th words in source and destination operands *)
  IF SRC1[255:240] < SRC2[255:240] THEN
     DEST[255:240] <- SRC1[255:240];
  ELSE
     DEST[255:240] <- SRC2[255:240]; FI;

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMINUW:| __m128i _mm_min_epu16 ( __m128i a, __m128i
|           | b);                                       
| VPMINUW:  | __m256i _mm256_min_epu16 ( __m256i a,     
|           | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMOVMSKB
description:
PMOVMSKB - Move Byte Mask:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F D7 /r1 PMOVMSKB reg, mm            | RM   | V/V                   | SSE               | Move a byte mask of mm to reg. The upper
|                                       |      |                       |                   | bits of r32 or r64 are zeroed           
| 66 0F D7 /r PMOVMSKB reg, xmm         | RM   | V/V                   | SSE2              | Move a byte mask of xmm to reg. The     
|                                       |      |                       |                   | upper bits of r32 or r64 are zeroed     
| VEX.128.66.0F.WIG D7 /r VPMOVMSKB reg,| RM   | V/V                   | AVX               | Move a byte mask of xmm1 to reg. The    
| xmm1                                  |      |                       |                   | upper bits of r32 or r64 are filled     
|                                       |      |                       |                   | with zeros.                             
| VEX.256.66.0F.WIG D7 /r VPMOVMSKB reg,| RM   | V/V                   | AVX2              | Move a 32-bit mask of ymm1 to reg. The  
| ymm1                                  |      |                       |                   | upper bits of r64 are filled with zeros.
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Creates a mask made up of the most significant bit of each byte of the source
operand (second operand) and stores the result in the low byte or word of the
destination operand (first operand). The byte mask is 8 bits for 64-bit source
operand, 16 bits for 128-bit source operand and 32 bits for 256-bit source operand.
The destination operand is a general-purpose register.

In 64-bit mode, the instruction can access additional registers (XMM8-XMM15,
R8-R15) when used with a REX.R prefix. The default operand size is 64-bit in
64-bit mode. Legacy SSE version: The source operand is an MMX technology register.
128-bit Legacy SSE version: The source operand is an XMM register.

VEX.128 encoded version: The source operand is an XMM register. VEX.256 encoded
version: The source operand is a YMM register. Note: VEX.vvvv is reserved and
must be 1111b, VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMOVMSKB (with 64-bit source operand and r32)
  r32[0] <- SRC[7];
  r32[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 6 *)
  r32[7] <- SRC[63];
  r32[31:8] <- ZERO_FILL;
(V)PMOVMSKB (with 128-bit source operand and r32)
  r32[0] <- SRC[7];
  r32[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 14 *)
  r32[15] <- SRC[127];
  r32[31:16] <- ZERO_FILL;
VPMOVMSKB (with 256-bit source operand and r32)
r32[0] <- SRC[7];
r32[1] <- SRC[15];
(* Repeat operation for bytes 3rd through 31*)
r32[31] <- SRC[255];
PMOVMSKB (with 64-bit source operand and r64)
  r64[0] <- SRC[7];
  r64[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 6 *)
  r64[7] <- SRC[63];
  r64[63:8] <- ZERO_FILL;
(V)PMOVMSKB (with 128-bit source operand and r64)
  r64[0] <- SRC[7];
  r64[1] <- SRC[15];
  (* Repeat operation for bytes 2 through 14 *)
  r64[15] <- SRC[127];
  r64[63:16] <- ZERO_FILL;
VPMOVMSKB (with 256-bit source operand and r64)
r64[0] <- SRC[7];
r64[1] <- SRC[15];
(* Repeat operation for bytes 2 through 31*)
r64[31] <- SRC[255];
r64[63:32] <- ZERO_FILL;

Intel C/C++ Compiler Intrinsic Equivalent:
| PMOVMSKB:   | int _mm_movemask_pi8(__m64 a)        
| (V)PMOVMSKB:| int _mm_movemask_epi8 ( __m128i a)   
| VPMOVMSKB:  | int _mm256_movemask_epi8 ( __m256i a)

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 7; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PMOVSX
description:
PMOVSX  -  Packed Move with Sign Extend:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 66 0f 38 20 /r PMOVSXBW xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Sign extend 8 packed signed 8-bit integers 
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8        
|                                       |      |                       |                   | packed signed 16-bit integers in xmm1.     
| 66 0f 38 21 /r PMOVSXBD xmm1, xmm2/m32| RM   | V/V                   | SSE4_1            | Sign extend 4 packed signed 8-bit integers 
|                                       |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4        
|                                       |      |                       |                   | packed signed 32-bit integers in xmm1.     
| 66 0f 38 22 /r PMOVSXBQ xmm1, xmm2/m16| RM   | V/V                   | SSE4_1            | Sign extend 2 packed signed 8-bit integers 
|                                       |      |                       |                   | in the low 2 bytes of xmm2/m16 to 2        
|                                       |      |                       |                   | packed signed 64-bit integers in xmm1.     
| 66 0f 38 23 /r PMOVSXWD xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Sign extend 4 packed signed 16-bit integers
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4        
|                                       |      |                       |                   | packed signed 32-bit integers in xmm1.     
| 66 0f 38 24 /r PMOVSXWQ xmm1, xmm2/m32| RM   | V/V                   | SSE4_1            | Sign extend 2 packed signed 16-bit integers
|                                       |      |                       |                   | in the low 4 bytes of xmm2/m32 to 2        
|                                       |      |                       |                   | packed signed 64-bit integers in xmm1.     
| 66 0f 38 25 /r PMOVSXDQ xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Sign extend 2 packed signed 32-bit integers
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 2        
|                                       |      |                       |                   | packed signed 64-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 20 /r VPMOVSXBW   | RM   | V/V                   | AVX               | Sign extend 8 packed 8-bit integers        
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8        
|                                       |      |                       |                   | packed 16-bit integers in xmm1.            
| VEX.128.66.0F38.WIG 21 /r VPMOVSXBD   | RM   | V/V                   | AVX               | Sign extend 4 packed 8-bit integers        
| xmm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4        
|                                       |      |                       |                   | packed 32-bit integers in xmm1.            
| VEX.128.66.0F38.WIG 22 /r VPMOVSXBQ   | RM   | V/V                   | AVX               | Sign extend 2 packed 8-bit integers        
| xmm1, xmm2/m16                        |      |                       |                   | in the low 2 bytes of xmm2/m16 to 2        
|                                       |      |                       |                   | packed 64-bit integers in xmm1.            
| VEX.128.66.0F38.WIG 23 /r VPMOVSXWD   | RM   | V/V                   | AVX               | Sign extend 4 packed 16-bit integers       
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4        
|                                       |      |                       |                   | packed 32-bit integers in xmm1.            
| VEX.128.66.0F38.WIG 24 /r VPMOVSXWQ   | RM   | V/V                   | AVX               | Sign extend 2 packed 16-bit integers       
| xmm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 2        
|                                       |      |                       |                   | packed 64-bit integers in xmm1.            
| VEX.128.66.0F38.WIG 25 /r VPMOVSXDQ   | RM   | V/V                   | AVX               | Sign extend 2 packed 32-bit integers       
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 2        
|                                       |      |                       |                   | packed 64-bit integers in xmm1.            
| VEX.256.66.0F38.WIG 20 /r VPMOVSXBW   | RM   | V/V                   | AVX2              | Sign extend 16 packed 8-bit integers       
| ymm1, xmm2/m128                       |      |                       |                   | in xmm2/m128 to 16 packed 16-bit integers  
|                                       |      |                       |                   | in ymm1.                                   
| VEX.256.66.0F38.WIG 21 /r VPMOVSXBD   | RM   | V/V                   | AVX2              | Sign extend 8 packed 8-bit integers        
| ymm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8        
|                                       |      |                       |                   | packed 32-bit integers in ymm1.            
| VEX.256.66.0F38.WIG 22 /r VPMOVSXBQ   | RM   | V/V                   | AVX2              | Sign extend 4 packed 8-bit integers        
| ymm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4        
|                                       |      |                       |                   | packed 64-bit integers in ymm1.            
| VEX.256.66.0F38.WIG 23 /r VPMOVSXWD   | RM   | V/V                   | AVX2              | Sign extend 8 packed 16-bit integers       
| ymm1, xmm2/m128                       |      |                       |                   | in the low 16 bytes of xmm2/m128 to        
|                                       |      |                       |                   | 8 packed 32bit integers in ymm1.           
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| VEX.256.66.0F38.WIG 24 /r VPMOVSXWQ   | RM   | V/V                   | AVX2              | Sign extend 4 packed 16-bit integers       
| ymm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4        
|                                       |      |                       |                   | packed 64-bit integers in ymm1.            
| VEX.256.66.0F38.WIG 25 /r VPMOVSXDQ   | RM   | V/V                   | AVX2              | Sign extend 4 packed 32-bit integers       
| ymm1, xmm2/m128                       |      |                       |                   | in the low 16 bytes of xmm2/m128 to        
|                                       |      |                       |                   | 4 packed 64bit integers in ymm1.           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Sign-extend the low byte/word/dword values in each word/dword/qword element
of the source operand (second operand) to word/dword/qword integers and stored
as packed data in the destination operand (first operand). 128-bit Legacy SSE
version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM
register are zeroed. VEX.256 encoded version: The destination register is YMM
Register. Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise
the instruction will #UD.

Operation:

PMOVSXBW
  DEST[15:0] <- SignExtend(SRC[7:0]);
  DEST[31:16] <- SignExtend(SRC[15:8]);
  DEST[47:32] <- SignExtend(SRC[23:16]);
  DEST[63:48] <- SignExtend(SRC[31:24]);
  DEST[79:64] <- SignExtend(SRC[39:32]);
  DEST[95:80] <- SignExtend(SRC[47:40]);
  DEST[111:96] <- SignExtend(SRC[55:48]);
  DEST[127:112] <- SignExtend(SRC[63:56]);
PMOVSXBD
  DEST[31:0] <- SignExtend(SRC[7:0]);
  DEST[63:32] <- SignExtend(SRC[15:8]);
  DEST[95:64] <- SignExtend(SRC[23:16]);
  DEST[127:96] <- SignExtend(SRC[31:24]);
PMOVSXBQ
  DEST[63:0] <- SignExtend(SRC[7:0]);
  DEST[127:64] <- SignExtend(SRC[15:8]);
PMOVSXWD
  DEST[31:0] <- SignExtend(SRC[15:0]);
  DEST[63:32] <- SignExtend(SRC[31:16]);
  DEST[95:64] <- SignExtend(SRC[47:32]);
  DEST[127:96] <- SignExtend(SRC[63:48]);
PMOVSXWQ
  DEST[63:0] <- SignExtend(SRC[15:0]);
  DEST[127:64] <- SignExtend(SRC[31:16]);
PMOVSXDQ
  DEST[63:0] <- SignExtend(SRC[31:0]);
  DEST[127:64] <- SignExtend(SRC[63:32]);
VPMOVSXBW (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_WORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXBD (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXBQ (VEX.128 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXWD (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_DWORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXWQ (VEX.128 encoded version)
Packed_Sign_Extend_WORD_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXDQ (VEX.128 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVSXBW (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
VPMOVSXBD (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
VPMOVSXBQ (VEX.256 encoded version)
Packed_Sign_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Sign_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
VPMOVSXWD (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
VPMOVSXWQ (VEX.256 encoded version)
Packed_Sign_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Sign_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
VPMOVSXDQ (VEX.256 encoded version)
Packed_Sign_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Sign_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMOVSXBW:| __m128i _mm_ cvtepi8_epi16 ( __m128i   
|             | a);                                    
| VPMOVSXBW:  | __m256i _mm256_cvtepi8_epi16 ( __m128i 
|             | a);                                    
| (V)PMOVSXBD:| __m128i _mm_ cvtepi8_epi32 ( __m128i   
|             | a);                                    
| VPMOVSXBD:  | __m256i _mm256_cvtepi8_epi32 ( __m128i 
|             | a);                                    
| (V)PMOVSXBQ:| __m128i _mm_ cvtepi8_epi64 ( __m128i   
|             | a);                                    
| VPMOVSXBQ:  | __m256i _mm256_cvtepi8_epi64 ( __m128i 
|             | a);                                    
| (V)PMOVSXWD:| __m128i _mm_ cvtepi16_epi32 ( __m128i  
|             | a);                                    
| VPMOVSXWD:  | __m256i _mm256_cvtepi16_epi32 ( __m128i
|             | a);                                    
| (V)PMOVSXWQ:| __m128i _mm_ cvtepi16_epi64 ( __m128i  
|             | a);                                    
| VPMOVSXWQ:  | __m256i _mm256_cvtepi16_epi64 ( __m128i
|             | a);                                    
| (V)PMOVSXDQ:| __m128i _mm_ cvtepi32_epi64 ( __m128i  
|             | a);                                    
| VPMOVSXDQ:  | __m256i _mm256_cvtepi32_epi64 ( __m128i
|             | a);                                    

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PMOVZX
description:
PMOVZX  -  Packed Move with Zero Extend:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                         
| 66 0f 38 30 /r PMOVZXBW xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Zero extend 8 packed 8-bit integers 
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8 
|                                       |      |                       |                   | packed 16-bit integers in xmm1.     
| 66 0f 38 31 /r PMOVZXBD xmm1, xmm2/m32| RM   | V/V                   | SSE4_1            | Zero extend 4 packed 8-bit integers 
|                                       |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4 
|                                       |      |                       |                   | packed 32-bit integers in xmm1.     
| 66 0f 38 32 /r PMOVZXBQ xmm1, xmm2/m16| RM   | V/V                   | SSE4_1            | Zero extend 2 packed 8-bit integers 
|                                       |      |                       |                   | in the low 2 bytes of xmm2/m16 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| 66 0f 38 33 /r PMOVZXWD xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Zero extend 4 packed 16-bit integers
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4 
|                                       |      |                       |                   | packed 32-bit integers in xmm1.     
| 66 0f 38 34 /r PMOVZXWQ xmm1, xmm2/m32| RM   | V/V                   | SSE4_1            | Zero extend 2 packed 16-bit integers
|                                       |      |                       |                   | in the low 4 bytes of xmm2/m32 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| 66 0f 38 35 /r PMOVZXDQ xmm1, xmm2/m64| RM   | V/V                   | SSE4_1            | Zero extend 2 packed 32-bit integers
|                                       |      |                       |                   | in the low 8 bytes of xmm2/m64 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 30 /r VPMOVZXBW   | RM   | V/V                   | AVX               | Zero extend 8 packed 8-bit integers 
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8 
|                                       |      |                       |                   | packed 16-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 31 /r VPMOVZXBD   | RM   | V/V                   | AVX               | Zero extend 4 packed 8-bit integers 
| xmm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4 
|                                       |      |                       |                   | packed 32-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 32 /r VPMOVZXBQ   | RM   | V/V                   | AVX               | Zero extend 2 packed 8-bit integers 
| xmm1, xmm2/m16                        |      |                       |                   | in the low 2 bytes of xmm2/m16 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 33 /r VPMOVZXWD   | RM   | V/V                   | AVX               | Zero extend 4 packed 16-bit integers
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4 
|                                       |      |                       |                   | packed 32-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 34 /r VPMOVZXWQ   | RM   | V/V                   | AVX               | Zero extend 2 packed 16-bit integers
| xmm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| VEX.128.66.0F38.WIG 35 /r VPMOVZXDQ   | RM   | V/V                   | AVX               | Zero extend 2 packed 32-bit integers
| xmm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 2 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| VEX.256.66.0F38.WIG 30 /r VPMOVZXBW   | RM   | V/V                   | AVX2              | Zero extend 16 packed 8-bit integers
| ymm1, xmm2/m128                       |      |                       |                   | in the low 16 bytes of xmm2/m128 to 
|                                       |      |                       |                   | 16 packed 16-bit integers in ymm1.  
| VEX.256.66.0F38.WIG 31 /r VPMOVZXBD   | RM   | V/V                   | AVX2              | Zero extend 8 packed 8-bit integers 
| ymm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 8 
|                                       |      |                       |                   | packed 32-bit integers in ymm1.     
| VEX.256.66.0F38.WIG 32 /r VPMOVZXBQ   | RM   | V/V                   | AVX2              | Zero extend 4 packed 8-bit integers 
| ymm1, xmm2/m32                        |      |                       |                   | in the low 4 bytes of xmm2/m32 to 4 
|                                       |      |                       |                   | packed 64-bit integers in ymm1.     
| VEX.256.66.0F38.WIG 33 /r VPMOVZXWD   | RM   | V/V                   | AVX2              | Zero extend 8 packed 16-bit integers
| ymm1, xmm2/m128                       |      |                       |                   | in the low 16 bytes of xmm2/m128 to 
|                                       |      |                       |                   | 8 packed 32bit integers in ymm1.    
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                         
| VEX.256.66.0F38.WIG 34 /r VPMOVZXWQ   | RM   | V/V                   | AVX2              | Zero extend 4 packed 16-bit integers
| ymm1, xmm2/m64                        |      |                       |                   | in the low 8 bytes of xmm2/m64 to 4 
|                                       |      |                       |                   | packed 64-bit integers in xmm1.     
| VEX.256.66.0F38.WIG 35 /r VPMOVZXDQ   | RM   | V/V                   | AVX2              | Zero extend 4 packed 32-bit integers
| ymm1, xmm2/m128                       |      |                       |                   | in the low 16 bytes of xmm2/m128 to 
|                                       |      |                       |                   | 4 packed 64bit integers in ymm1.    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Zero-extend the low byte/word/dword values in each word/dword/qword element
of the source operand (second operand) to word/dword/qword integers and stored
as packed data in the destination operand (first operand). 128-bit Legacy SSE
version: Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM
register are zeroed. VEX.256 encoded version: The destination register is YMM
Register.

Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD.

Operation:

PMOVZXBW
  DEST[15:0] <- ZeroExtend(SRC[7:0]);
  DEST[31:16] <- ZeroExtend(SRC[15:8]);
  DEST[47:32] <- ZeroExtend(SRC[23:16]);
  DEST[63:48] <- ZeroExtend(SRC[31:24]);
  DEST[79:64] <- ZeroExtend(SRC[39:32]);
  DEST[95:80] <- ZeroExtend(SRC[47:40]);
  DEST[111:96] <- ZeroExtend(SRC[55:48]);
  DEST[127:112] <- ZeroExtend(SRC[63:56]);
PMOVZXBD
  DEST[31:0] <- ZeroExtend(SRC[7:0]);
  DEST[63:32] <- ZeroExtend(SRC[15:8]);
  DEST[95:64] <- ZeroExtend(SRC[23:16]);
  DEST[127:96] <- ZeroExtend(SRC[31:24]);
PMOVZXQB
  DEST[63:0] <- ZeroExtend(SRC[7:0]);
  DEST[127:64] <- ZeroExtend(SRC[15:8]);
PMOVZXWD
  DEST[31:0] <- ZeroExtend(SRC[15:0]);
  DEST[63:32] <- ZeroExtend(SRC[31:16]);
  DEST[95:64] <- ZeroExtend(SRC[47:32]);
  DEST[127:96] <- ZeroExtend(SRC[63:48]);
PMOVZXWQ
  DEST[63:0] <- ZeroExtend(SRC[15:0]);
  DEST[127:64] <- ZeroExtend(SRC[31:16]);
PMOVZXDQ
  DEST[63:0] <- ZeroExtend(SRC[31:0]);
  DEST[127:64] <- ZeroExtend(SRC[63:32]);
VPMOVZXBW (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_WORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXBD (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXBQ (VEX.128 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXWD (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_DWORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXWQ (VEX.128 encoded version)
Packed_Zero_Extend_WORD_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXDQ (VEX.128 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD()
DEST[VLMAX-1:128] <- 0
VPMOVZXBW (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_WORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_BYTE_to_WORD(DEST[255:128], SRC[127:64])
VPMOVZXBD (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_DWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_BYTE_to_DWORD(DEST[255:128], SRC[63:32])
VPMOVZXBQ (VEX.256 encoded version)
Packed_Zero_Extend_BYTE_to_QWORD(DEST[127:0], SRC[15:0])
Packed_Zero_Extend_BYTE_to_QWORD(DEST[255:128], SRC[31:16])
VPMOVZXWD (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_DWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_WORD_to_DWORD(DEST[255:128], SRC[127:64])
VPMOVZXWQ (VEX.256 encoded version)
Packed_Zero_Extend_WORD_to_QWORD(DEST[127:0], SRC[31:0])
Packed_Zero_Extend_WORD_to_QWORD(DEST[255:128], SRC[63:32])
VPMOVZXDQ (VEX.256 encoded version)
Packed_Zero_Extend_DWORD_to_QWORD(DEST[127:0], SRC[63:0])
Packed_Zero_Extend_DWORD_to_QWORD(DEST[255:128], SRC[127:64])

Flags Affected:
None


Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMOVZXBW:| __m128i _mm_ cvtepu8_epi16 ( __m128i   
|             | a);                                    
| VPMOVZXBW:  | __m256i _mm256_cvtepu8_epi16 ( __m128i 
|             | a);                                    
| (V)PMOVZXBD:| __m128i _mm_ cvtepu8_epi32 ( __m128i   
|             | a);                                    
| VPMOVZXBD:  | __m256i _mm256_cvtepu8_epi32 ( __m128i 
|             | a);                                    
| (V)PMOVZXBQ:| __m128i _mm_ cvtepu8_epi64 ( __m128i   
|             | a);                                    
| VPMOVZXBQ:  | __m256i _mm256_cvtepu8_epi64 ( __m128i 
|             | a);                                    
| (V)PMOVZXWD:| __m128i _mm_ cvtepu16_epi32 ( __m128i  
|             | a);                                    
| VPMOVZXWD:  | __m256i _mm256_cvtepu16_epi32 ( __m128i
|             | a);                                    
| (V)PMOVZXWQ:| __m128i _mm_ cvtepu16_epi64 ( __m128i  
|             | a);                                    
| VPMOVZXWQ:  | __m256i _mm256_cvtepu16_epi64 ( __m128i
|             | a);                                    
| (V)PMOVZXDQ:| __m128i _mm_ cvtepu32_epi64 ( __m128i  
|             | a);                                    
| VPMOVZXDQ:  | __m256i _mm256_cvtepu32_epi64 ( __m128i
|             | a);                                    

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PMULDQ
description:
PMULDQ  -  Multiply Packed Signed Dword Integers:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 66 0F 38 28 /r PMULDQ xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Multiply the packed signed dword integers 
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store the       
|                                      |      |                       |                   | quadword product in xmm1.                 
| VEX.NDS.128.66.0F38.WIG 28 /r VPMULDQ| RVM  | V/V                   | AVX               | Multiply packed signed doubleword integers
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 by packed signed doubleword       
|                                      |      |                       |                   | integers in xmm3/m128, and store the      
|                                      |      |                       |                   | quadword results in xmm1.                 
| VEX.NDS.256.66.0F38.WIG 28 /r VPMULDQ| RVM  | V/V                   | AVX2              | Multiply packed signed doubleword integers
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 by packed signed doubleword       
|                                      |      |                       |                   | integers in ymm3/m256, and store the      
|                                      |      |                       |                   | quadword results in ymm1.                 

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Multiplies the first source operand by the second source operand and stores
the result in the destination operand. For PMULDQ and VPMULDQ (VEX.128 encoded
version), the second source operand is two packed signed doubleword integers
stored in the first (low) and third doublewords of an XMM register or a 128-bit
memory location. The first source operand is two packed signed doubleword integers
stored in the first and third doublewords of an XMM register. The destination
contains two packed signed quadword integers stored in an XMM register. For
128-bit memory operands, 128 bits are fetched from memory, but only the first
and third doublewords are used in the computation. For VPMULDQ (VEX.256 encoded
version), the second source operand is four packed signed doubleword integers
stored in the first (low), third, fifth and seventh doublewords of an YMM register
or a 256-bit memory location. The first source operand is four packed signed
doubleword integers stored in the first, third, fifth and seventh doublewords
of an XMM register. The destination contains four packed signed quadword integers
stored in an YMM register. For 256-bit memory operands, 256 bits are fetched
from memory, but only the first, third, fifth and seventh doublewords are used
in the computation. When a quadword result is too large to be represented in
64 bits (overflow), the result is wrapped around and the low 64 bits are written
to the destination element (that is, the carry is ignored). 128-bit Legacy SSE
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.L must be 0, otherwise the instruction
will #UD. VEX.256 encoded version: The second source operand can be an YMM register
or a 256-bit memory location. The first source and destination operands are
YMM registers.

Operation:

PMULDQ (128-bit Legacy SSE version)
DEST[63:0] <- DEST[31:0] * SRC[31:0]
DEST[127:64] <- DEST[95:64] * SRC[95:64]
DEST[VLMAX-1:128] (Unmodified)
VPMULDQ (VEX.128 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64]
DEST[VLMAX-1:128] <- 0
VPMULDQ (VEX.256 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64]
DEST[191:128] <- SRC1[159:128] * SRC2[159:128]
DEST[255:192] <- SRC1[223:192] * SRC2[223:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMULDQ:| __m128i _mm_mul_epi32( __m128i a, __m128i
|           | b);                                      
| VPMULDQ:  | __m256i _mm256_mul_epi32( __m256i a,     
|           | __m256i b);                              

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PMULHRSW
description:
PMULHRSW  -  Packed Multiply High with Round and Scale:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F 38 0B /r1 PMULHRSW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Multiply 16-bit signed words, scale    
|                                        |      |                       |                   | and round signed doublewords, pack high
|                                        |      |                       |                   | 16 bits to mm1.                        
| 66 0F 38 0B /r PMULHRSW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Multiply 16-bit signed words, scale    
|                                        |      |                       |                   | and round signed doublewords, pack high
|                                        |      |                       |                   | 16 bits to xmm1.                       
| VEX.NDS.128.66.0F38.WIG 0B /r VPMULHRSW| RVM  | V/V                   | AVX               | Multiply 16-bit signed words, scale    
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | and round signed doublewords, pack high
|                                        |      |                       |                   | 16 bits to xmm1.                       
| VEX.NDS.256.66.0F38.WIG 0B /r VPMULHRSW| RVM  | V/V                   | AVX2              | Multiply 16-bit signed words, scale    
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and round signed doublewords, pack high
|                                        |      |                       |                   | 16 bits to ymm1.                       
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
PMULHRSW multiplies vertically each signed 16-bit integer from the destination
operand (first operand) with the corresponding signed 16-bit integer of the
source operand (second operand), producing intermediate, signed 32bit integers.
Each intermediate 32-bit integer is truncated to the 18 most significant bits.
Rounding is always performed by adding 1 to the least significant bit of the
18-bit intermediate result. The final result is obtained by selecting the 16
bits immediately to the right of the most significant bit of each 18-bit intermediate
result and packed to the destination operand.

When the source operand is a 128-bit memory operand, the operand must be aligned
on a 16-byte boundary or a general-protection exception (#GP) will be generated.

In 64-bit mode, use the REX prefix to access additional registers. Legacy SSE
version: Both operands can be MMX registers. The second source operand is an
MMX register or a 64bit memory location.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.L must be 0, otherwise the instruction will #UD. VEX.256 encoded version:
The second source operand can be an YMM register or a 256-bit memory location.
The first source and destination operands are YMM registers.

Operation:

PMULHRSW (with 64-bit operands)
  temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
  temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
  temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >> 14) + 1;
  temp3[31:0] = INT32 ((DEST[63:48] * SRc[63:48]) >> 14) + 1;
  DEST[15:0] = temp0[16:1];
  DEST[31:16] = temp1[16:1];
  DEST[47:32] = temp2[16:1];
  DEST[63:48] = temp3[16:1];
PMULHRSW (with 128-bit operand)
  temp0[31:0] = INT32 ((DEST[15:0] * SRC[15:0]) >>14) + 1;
  temp1[31:0] = INT32 ((DEST[31:16] * SRC[31:16]) >>14) + 1;
  temp2[31:0] = INT32 ((DEST[47:32] * SRC[47:32]) >>14) + 1;
  temp3[31:0] = INT32 ((DEST[63:48] * SRC[63:48]) >>14) + 1;
  temp4[31:0] = INT32 ((DEST[79:64] * SRC[79:64]) >>14) + 1;
  temp5[31:0] = INT32 ((DEST[95:80] * SRC[95:80]) >>14) + 1;
  temp6[31:0] = INT32 ((DEST[111:96] * SRC[111:96]) >>14) + 1;
  temp7[31:0] = INT32 ((DEST[127:112] * SRC[127:112) >>14) + 1;
  DEST[15:0] = temp0[16:1];
  DEST[31:16] = temp1[16:1];
  DEST[47:32] = temp2[16:1];
  DEST[63:48] = temp3[16:1];
  DEST[79:64] = temp4[16:1];
  DEST[95:80] = temp5[16:1];
  DEST[111:96] = temp6[16:1];
  DEST[127:112] = temp7[16:1];
VPMULHRSW (VEX.128 encoded version)
temp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
DEST[15:0] <- temp0[16:1]
DEST[31:16] <- temp1[16:1]
DEST[47:32] <- temp2[16:1]
DEST[63:48] <- temp3[16:1]
DEST[79:64] <- temp4[16:1]
DEST[95:80] <- temp5[16:1]
DEST[111:96] <- temp6[16:1]
DEST[127:112] <- temp7[16:1]
DEST[VLMAX-1:128] <- 0
VPMULHRSW (VEX.256 encoded version)
temp0[31:0] <- INT32 ((SRC1[15:0] * SRC2[15:0]) >>14) + 1
temp1[31:0] <- INT32 ((SRC1[31:16] * SRC2[31:16]) >>14) + 1
temp2[31:0] <- INT32 ((SRC1[47:32] * SRC2[47:32]) >>14) + 1
temp3[31:0] <- INT32 ((SRC1[63:48] * SRC2[63:48]) >>14) + 1
temp4[31:0] <- INT32 ((SRC1[79:64] * SRC2[79:64]) >>14) + 1
temp5[31:0] <- INT32 ((SRC1[95:80] * SRC2[95:80]) >>14) + 1
temp6[31:0] <- INT32 ((SRC1[111:96] * SRC2[111:96]) >>14) + 1
temp7[31:0] <- INT32 ((SRC1[127:112] * SRC2[127:112) >>14) + 1
temp8[31:0] <- INT32 ((SRC1[143:128] * SRC2[143:128]) >>14) + 1
temp9[31:0] <- INT32 ((SRC1[159:144] * SRC2[159:144]) >>14) + 1
temp10[31:0] <- INT32 ((SRC1[75:160] * SRC2[175:160]) >>14) + 1
temp11[31:0] <- INT32 ((SRC1[191:176] * SRC2[191:176]) >>14) + 1
temp12[31:0] <- INT32 ((SRC1[207:192] * SRC2[207:192]) >>14) + 1
temp13[31:0] <- INT32 ((SRC1[223:208] * SRC2[223:208]) >>14) + 1
temp14[31:0] <- INT32 ((SRC1[239:224] * SRC2[239:224]) >>14) + 1
temp15[31:0] <- INT32 ((SRC1[255:240] * SRC2[255:240) >>14) + 1

Intel C/C++ Compiler Intrinsic Equivalents:
| PMULHRSW:   | __m64 _mm_mulhrs_pi16 (__m64 a, __m64
|             | b)                                   
| (V)PMULHRSW:| __m128i _mm_mulhrs_epi16 (__m128i a, 
|             | __m128i b)                           
| VPMULHRSW:  | __m256i _mm256_mulhrs_epi16 (__m256i 
|             | a, __m256i b)                        

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMULHUW
description:
PMULHUW - Multiply Packed Unsigned Integers and Store High Result:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 0F E4 /r1 PMULHUW mm1, mm2/m64      | RM   | V/V                   | SSE               | Multiply the packed unsigned word integers
|                                     |      |                       |                   | in mm1 register and mm2/m64, and store    
|                                     |      |                       |                   | the high 16 bits of the results in mm1.   
| 66 0F E4 /r PMULHUW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Multiply the packed unsigned word integers
|                                     |      |                       |                   | in xmm1 and xmm2/m128, and store the      
|                                     |      |                       |                   | high 16 bits of the results in xmm1.      
| VEX.NDS.128.66.0F.WIG E4 /r VPMULHUW| RVM  | V/V                   | AVX               | Multiply the packed unsigned word integers
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm2 and xmm3/m128, and store the      
|                                     |      |                       |                   | high 16 bits of the results in xmm1.      
| VEX.NDS.256.66.0F.WIG E4 /r VPMULHUW| RVM  | V/V                   | AVX2              | Multiply the packed unsigned word integers
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm2 and ymm3/m256, and store the      
|                                     |      |                       |                   | high 16 bits of the results in ymm1.      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD unsigned multiply of the packed unsigned word integers in the
destination operand (first operand) and the source operand (second operand),
and stores the high 16 bits of each 32-bit intermediate results in the destination
operand. (Figure 4-8 shows this operation when using 64-bit operands.)

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand is an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.L must be 0, otherwise the instruction will #UD. VEX.256 encoded version:
The second source operand can be an YMM register or a 256-bit memory location.
The first source and destination operands are YMM registers.

| SRC | X3             | X2| X1             | X0             
| DEST| Y3 Z2 = X2 * Y2| Y2| Y1 Z1 = X1 * Y1| Y0 Z0 = X0 * Y0
DEST

| Z3[31:16]PMULHUW and PMULHW Instruction| Z2[31:16]| Z1[31:16]| Z0[31:16]Figure 4-8.
| Operation Using 64-bit Operands        |          |          |                     
Operation:

PMULHUW (with 64-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
PMULHUW (with 128-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  TEMP4[31:0] <-
  TEMP5[31:0] <-
  TEMP6[31:0] <-
  TEMP7[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
  DEST[79:64] <-
  DEST[95:80] <-
  DEST[111:96] <-
  DEST[127:112] <- TEMP7[31:16];
VPMULHUW (VEX.128 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[VLMAX-1:128] <- 0
PMULHUW (VEX.256 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0]
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[143:128] <- TEMP8[31:16]
DEST[159:144] <- TEMP9[31:16]
DEST[175:160] <- TEMP10[31:16]
DEST[191:176] <- TEMP11[31:16]
DEST[207:192] <- TEMP12[31:16]
DEST[223:208] <- TEMP13[31:16]
DEST[239:224] <- TEMP14[31:16]
DEST[255:240] <- TEMP15[31:16]

Intel C/C++ Compiler Intrinsic Equivalent:
| PMULHUW:   | __m64 _mm_mulhi_pu16(__m64 a, __m64 
|            | b)                                  
| (V)PMULHUW:| __m128i _mm_mulhi_epu16 ( __m128i a,
|            | __m128i b)                          
| VPMULHUW:  | __m256i _mm256_mulhi_epu16 ( __m256i
|            | a, __m256i b)                       

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMULHW
description:
PMULHW - Multiply Packed Signed Integers and Store High Result:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F E5 /r1 PMULHW mm, mm/m64        | RM   | V/V                   | MMX               | Multiply the packed signed word integers
|                                    |      |                       |                   | in mm1 register and mm2/m64, and store  
|                                    |      |                       |                   | the high 16 bits of the results in mm1. 
| 66 0F E5 /r PMULHW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Multiply the packed signed word integers
|                                    |      |                       |                   | in xmm1 and xmm2/m128, and store the    
|                                    |      |                       |                   | high 16 bits of the results in xmm1.    
| VEX.NDS.128.66.0F.WIG E5 /r VPMULHW| RVM  | V/V                   | AVX               | Multiply the packed signed word integers
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm2 and xmm3/m128, and store the    
|                                    |      |                       |                   | high 16 bits of the results in xmm1.    
| VEX.NDS.256.66.0F.WIG E5 /r VPMULHW| RVM  | V/V                   | AVX2              | Multiply the packed signed word integers
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm2 and ymm3/m256, and store the    
|                                    |      |                       |                   | high 16 bits of the results in ymm1.    
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD signed multiply of the packed signed word integers in the destination
operand (first operand) and the source operand (second operand), and stores
the high 16 bits of each intermediate 32-bit result in the destination operand.
(Figure 4-8 shows this operation when using 64-bit operands.)

n 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand is an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.L must be 0, otherwise the instruction will #UD. VEX.256 encoded version:
The second source operand can be an YMM register or a 256-bit memory location.
The first source and destination operands are YMM registers.

Operation:

PMULHW (with 64-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
PMULHW (with 128-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  TEMP4[31:0] <-
  TEMP5[31:0] <-
  TEMP6[31:0] <-
  TEMP7[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
  DEST[79:64] <-
  DEST[95:80] <-
  DEST[111:96] <-
  DEST[127:112] <- TEMP7[31:16];
VPMULHW (VEX.128 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[VLMAX-1:128] <- 0
PMULHW (VEX.256 encoded version)
TEMP0[31:0] <- SRC1[15:0] * SRC2[15:0] (*Signed Multiplication*)
TEMP1[31:0] <- SRC1[31:16] * SRC2[31:16]
TEMP2[31:0] <- SRC1[47:32] * SRC2[47:32]
TEMP3[31:0] <- SRC1[63:48] * SRC2[63:48]
TEMP4[31:0] <- SRC1[79:64] * SRC2[79:64]
TEMP5[31:0] <- SRC1[95:80] * SRC2[95:80]
TEMP6[31:0] <- SRC1[111:96] * SRC2[111:96]
TEMP7[31:0] <- SRC1[127:112] * SRC2[127:112]
TEMP8[31:0] <- SRC1[143:128] * SRC2[143:128]
TEMP9[31:0] <- SRC1[159:144] * SRC2[159:144]
TEMP10[31:0] <- SRC1[175:160] * SRC2[175:160]
TEMP11[31:0] <- SRC1[191:176] * SRC2[191:176]
TEMP12[31:0] <- SRC1[207:192] * SRC2[207:192]
TEMP13[31:0] <- SRC1[223:208] * SRC2[223:208]
TEMP14[31:0] <- SRC1[239:224] * SRC2[239:224]
TEMP15[31:0] <- SRC1[255:240] * SRC2[255:240]
DEST[15:0] <- TEMP0[31:16]
DEST[31:16] <- TEMP1[31:16]
DEST[47:32] <- TEMP2[31:16]
DEST[63:48] <- TEMP3[31:16]
DEST[79:64] <- TEMP4[31:16]
DEST[95:80] <- TEMP5[31:16]
DEST[111:96] <- TEMP6[31:16]
DEST[127:112] <- TEMP7[31:16]
DEST[143:128] <- TEMP8[31:16]
DEST[159:144] <- TEMP9[31:16]
DEST[175:160] <- TEMP10[31:16]
DEST[191:176] <- TEMP11[31:16]
DEST[207:192] <- TEMP12[31:16]
DEST[223:208] <- TEMP13[31:16]
DEST[239:224] <- TEMP14[31:16]
DEST[255:240] <- TEMP15[31:16]

Intel C/C++ Compiler Intrinsic Equivalent:
| PMULHW:   | __m64 _mm_mulhi_pi16 (__m64 m1, __m64
|           | m2)                                  
| (V)PMULHW:| __m128i _mm_mulhi_epi16 ( __m128i a, 
|           | __m128i b)                           
| VPMULHW:  | __m256i _mm256_mulhi_epi16 ( __m256i 
|           | a, __m256i b)                        

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMULLD
description:
PMULLD  -  Multiply Packed Signed Dword Integers and Store Low Result:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 66 0F 38 40 /r PMULLD xmm1, xmm2/m128| RM   | V/V                   | SSE4_1            | Multiply the packed dword signed integers
|                                      |      |                       |                   | in xmm1 and xmm2/m128 and store the      
|                                      |      |                       |                   | low 32 bits of each product in xmm1.     
| VEX.NDS.128.66.0F38.WIG 40 /r VPMULLD| RVM  | V/V                   | AVX               | Multiply the packed dword signed integers
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 and xmm3/m128 and store the      
|                                      |      |                       |                   | low 32 bits of each product in xmm1.     
| VEX.NDS.256.66.0F38.WIG 40 /r VPMULLD| RVM  | V/V                   | AVX2              | Multiply the packed dword signed integers
| ymm1, ymm2, ymm3/m256                |      |                       |                   | in ymm2 and ymm3/m256 and store the      
|                                      |      |                       |                   | low 32 bits of each product in ymm1.     

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs four signed multiplications from four pairs of signed dword integers
and stores the lower 32 bits of the four 64-bit products in the destination
operand (first operand). Each dword element in the destination operand is multiplied
with the corresponding dword element of the source operand (second operand)
to obtain a 64-bit intermediate product. 128-bit Legacy SSE version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The first
source and destination operands are XMM registers. The second source operand
is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The second source operand
can be an YMM register or a 256-bit memory location. The first source and destination
operands are YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

Temp0[63:0] <- DEST[31:0] * SRC[31:0];
Temp1[63:0] <- DEST[63:32] * SRC[63:32];
Temp2[63:0] <- DEST[95:64] * SRC[95:64];
Temp3[63:0] <- DEST[127:96] * SRC[127:96];
DEST[31:0] <- Temp0[31:0];
DEST[63:32] <- Temp1[31:0];
DEST[95:64] <- Temp2[31:0];
DEST[127:96] <- Temp3[31:0];
VPMULLD (VEX.128 encoded version)
Temp0[63:0] <- SRC1[31:0] * SRC2[31:0]
Temp1[63:0] <- SRC1[63:32] * SRC2[63:32]
Temp2[63:0] <- SRC1[95:64] * SRC2[95:64]
Temp3[63:0] <- SRC1[127:96] * SRC2[127:96]
DEST[31:0] <- Temp0[31:0]
DEST[63:32] <- Temp1[31:0]
DEST[95:64] <- Temp2[31:0]
DEST[127:96] <- Temp3[31:0]
DEST[VLMAX-1:128] <- 0
VPMULLD (VEX.256 encoded version)
Temp0[63:0] <- SRC1[31:0] * SRC2[31:0]
Temp1[63:0] <- SRC1[63:32] * SRC2[63:32]
Temp2[63:0] <- SRC1[95:64] * SRC2[95:64]
Temp3[63:0] <- SRC1[127:96] * SRC2[127:96]
Temp4[63:0] <- SRC1[159:128] * SRC2[159:128]
Temp5[63:0] <- SRC1[191:160] * SRC2[191:160]
Temp6[63:0] <- SRC1[223:192] * SRC2[223:192]
Temp7[63:0] <- SRC1[255:224] * SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PMULLUD:| __m128i _mm_mullo_epi32(__m128i a, __m128i
|            | b);                                       
| VPMULLD:   | __m256i _mm256_mullo_epi32(__m256i a,     
|            | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMULLW
description:
PMULLW - Multiply Packed Signed Integers and Store Low Result:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F D5 /r1 PMULLW mm, mm/m64        | RM   | V/V                   | MMX               | Multiply the packed signed word integers 
|                                    |      |                       |                   | in mm1 register and mm2/m64, and store   
|                                    |      |                       |                   | the low 16 bits of the results in mm1.   
| 66 0F D5 /r PMULLW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Multiply the packed signed word integers 
|                                    |      |                       |                   | in xmm1 and xmm2/m128, and store the     
|                                    |      |                       |                   | low 16 bits of the results in xmm1.      
| VEX.NDS.128.66.0F.WIG D5 /r VPMULLW| RVM  | V/V                   | AVX               | Multiply the packed dword signed integers
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm2 and xmm3/m128 and store the      
|                                    |      |                       |                   | low 32 bits of each product in xmm1.     
| VEX.NDS.256.66.0F.WIG D5 /r VPMULLW| RVM  | V/V                   | AVX2              | Multiply the packed signed word integers 
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm2 and ymm3/m256, and store the     
|                                    |      |                       |                   | low 16 bits of the results in ymm1.      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD signed multiply of the packed signed word integers in the destination
operand (first operand) and the source operand (second operand), and stores
the low 16 bits of each intermediate 32-bit result in the destination operand.
(Figure 4-8 shows this operation when using 64-bit operands.)

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand is an MMX technology register.

128-bit Legacy SSE version: The first source and destination operands are XMM
registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the corresponding YMM destination register remain
unchanged. VEX.128 encoded version: The first source and destination operands
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.L must be 0, otherwise the instruction will #UD. VEX.256 encoded version:
The second source operand can be an YMM register or a 256-bit memory location.
The first source and destination operands are YMM registers.

| SRC                                    | X3             | X2      | X1             | X0                 
| DEST                                   | Y3 Z2 = X2 * Y2| Y2      | Y1 Z1 = X1 * Y1| Y0 Z0 = X0 * Y0    
| DEST PMULLU Instruction Operation Using| Z3[15:0]       | Z2[15:0]| Z1[15:0]       | Z0[15:0]Figure 4-9.
| 64-bit Operands                        |                |         |                |                    
Operation:

PMULLW (with 64-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
PMULLW (with 128-bit operands)
  TEMP0[31:0] <-
  TEMP1[31:0] <-
  TEMP2[31:0] <-
  TEMP3[31:0] <-
  TEMP4[31:0] <-
  TEMP5[31:0] <-
  TEMP6[31:0] <-
  TEMP7[31:0] <-
  DEST[15:0] <-
  DEST[31:16] <-
  DEST[47:32] <-
  DEST[63:48] <-
  DEST[79:64] <-
  DEST[95:80] <-
  DEST[111:96] <-
  DEST[127:112] <- TEMP7[15:0];
VPMULLW (VEX.128 encoded version)
Temp0[31:0] <- SRC1[15:0] * SRC2[15:0]
Temp1[31:0] <- SRC1[31:16] * SRC2[31:16]
Temp2[31:0] <- SRC1[47:32] * SRC2[47:32]
Temp3[31:0] <- SRC1[63:48] * SRC2[63:48]
Temp4[31:0] <- SRC1[79:64] * SRC2[79:64]
Temp5[31:0] <- SRC1[95:80] * SRC2[95:80]
Temp6[31:0] <- SRC1[111:96] * SRC2[111:96]
Temp7[31:0] <- SRC1[127:112] * SRC2[127:112]
DEST[15:0] <- Temp0[15:0]
DEST[31:16] <- Temp1[15:0]
DEST[47:32] <- Temp2[15:0]
DEST[63:48] <- Temp3[15:0]
DEST[79:64] <- Temp4[15:0]
DEST[95:80] <- Temp5[15:0]
DEST[111:96] <- Temp6[15:0]
DEST[127:112] <- Temp7[15:0]
DEST[VLMAX-1:128] <- 0
VPMULLD (VEX.256 encoded version)
Temp0[63:0] <- SRC1[31:0] * SRC2[31:0]
Temp1[63:0] <- SRC1[63:32] * SRC2[63:32]
Temp2[63:0] <- SRC1[95:64] * SRC2[95:64]
Temp3[63:0] <- SRC1[127:96] * SRC2[127:96]
Temp4[63:0] <- SRC1[159:128] * SRC2[159:128]
Temp5[63:0] <- SRC1[191:160] * SRC2[191:160]
Temp6[63:0] <- SRC1[223:192] * SRC2[223:192]
Temp7[63:0] <- SRC1[255:224] * SRC2[255:224]
DEST[31:0] <- Temp0[31:0]
DEST[63:32] <- Temp1[31:0]
DEST[95:64] <- Temp2[31:0]
DEST[127:96] <- Temp3[31:0]
DEST[159:128] <- Temp4[31:0]
DEST[191:160] <- Temp5[31:0]
DEST[223:192] <- Temp6[31:0]
DEST[255:224] <- Temp7[31:0]

Intel C/C++ Compiler Intrinsic Equivalent:
| PMULLW:   | __m64 _mm_mullo_pi16(__m64 m1, __m64
|           | m2)                                 
| (V)PMULLW:| __m128i _mm_mullo_epi16 ( __m128i a,
|           | __m128i b)                          
| VPMULLW:  | __m256i _mm256_mullo_epi16 ( __m256i
|           | a, __m256i b);                      

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PMULUDQ
description:
PMULUDQ - Multiply Packed Unsigned Doubleword Integers:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F F4 /r1 PMULUDQ mm1, mm2/m64      | RM   | V/V                   | SSE2              | Multiply unsigned doubleword integer     
|                                     |      |                       |                   | in mm1 by unsigned doubleword integer    
|                                     |      |                       |                   | in mm2/m64, and store the quadword result
|                                     |      |                       |                   | in mm1.                                  
| 66 0F F4 /r PMULUDQ xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Multiply packed unsigned doubleword      
|                                     |      |                       |                   | integers in xmm1 by packed unsigned      
|                                     |      |                       |                   | doubleword integers in xmm2/m128, and    
|                                     |      |                       |                   | store the quadword results in xmm1.      
| VEX.NDS.128.66.0F.WIG F4 /r VPMULUDQ| RVM  | V/V                   | AVX               | Multiply packed unsigned doubleword      
| xmm1, xmm2, xmm3/m128               |      |                       |                   | integers in xmm2 by packed unsigned      
|                                     |      |                       |                   | doubleword integers in xmm3/m128, and    
|                                     |      |                       |                   | store the quadword results in xmm1.      
| VEX.NDS.256.66.0F.WIG F4 /r VPMULUDQ| RVM  | V/V                   | AVX2              | Multiply packed unsigned doubleword      
| ymm1, ymm2, ymm3/m256               |      |                       |                   | integers in ymm2 by packed unsigned      
|                                     |      |                       |                   | doubleword integers in ymm3/m256, and    
|                                     |      |                       |                   | store the quadword results in ymm1.      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Multiplies the first operand (destination operand) by the second operand (source
operand) and stores the result in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE version: The source operand can be an unsigned doubleword integer
stored in the low doubleword of an MMX technology register or a 64-bit memory
location. The destination operand can be an unsigned doubleword integer stored
in the low doubleword an MMX technology register. The result is an unsigned
quadword integer stored in the destination an MMX technology register. When
a quadword result is too large to be represented in 64 bits (overflow), the
result is wrapped around and the low 64 bits are written to the destination
element (that is, the carry is ignored).

For 64-bit memory operands, 64 bits are fetched from memory, but only the low
doubleword is used in the computation.

128-bit Legacy SSE version: The second source operand is two packed unsigned
doubleword integers stored in the first (low) and third doublewords of an XMM
register or a 128-bit memory location. For 128-bit memory operands, 128 bits
are fetched from memory, but only the first and third doublewords are used in
the computation.The first source operand is two packed unsigned doubleword integers
stored in the first and third doublewords of an XMM register. The destination
contains two packed unsigned quadword integers stored in an XMM register. Bits
(VLMAX1:128) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: The second source operand is two packed unsigned doubleword
integers stored in the first (low) and third doublewords of an XMM register
or a 128-bit memory location. For 128-bit memory operands, 128 bits are fetched
from memory, but only the first and third doublewords are used in the computation.The
first

source operand is two packed unsigned doubleword integers stored in the first
and third doublewords of an XMM register. The destination contains two packed
unsigned quadword integers stored in an XMM register. Bits (VLMAX1:128) of the
destination YMM register are zeroed. VEX.256 encoded version: The second source
operand is four packed unsigned doubleword integers stored in the first (low),
third, fifth and seventh doublewords of a YMM register or a 256-bit memory location.
For 256-bit memory operands, 256 bits are fetched from memory, but only the
first, third, fifth and seventh doublewords are used in the computation.The
first source operand is four packed unsigned doubleword integers stored in the
first, third, fifth and seventh doublewords of an YMM register. The destination
contains four packed unaligned quadword integers stored in an YMM register.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PMULUDQ (with 64-Bit operands)
  DEST[63:0] <- DEST[31:0] * SRC[31:0];
PMULUDQ (with 128-Bit operands)
  DEST[63:0] <- DEST[31:0] * SRC[31:0];
  DEST[127:64] <- DEST[95:64] * SRC[95:64];
VPMULUDQ (VEX.128 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64]
DEST[VLMAX-1:128] <- 0
VPMULUDQ (VEX.256 encoded version)
DEST[63:0] <- SRC1[31:0] * SRC2[31:0]
DEST[127:64] <- SRC1[95:64] * SRC2[95:64
DEST[191:128] <- SRC1[159:128] * SRC2[159:128]
DEST[255:192] <- SRC1[223:192] * SRC2[223:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| PMULUDQ:   | __m64 _mm_mul_su32 (__m64 a, __m64 b)     
| (V)PMULUDQ:| __m128i _mm_mul_epu32 ( __m128i a, __m128i
|            | b)                                        
| VPMULUDQ:  | __m256i _mm256_mul_epu32( __m256i a,      
|            | __m256i b);                               

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: POP
description:
POP - Pop a Value from the Stack:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                         
| 8F /0 | POP r/m16  | M    | Valid      | Valid          | Pop top of stack into m16; increment
|       |            |      |            |                | stack pointer.                      
| 8F /0 | POP r/m32  | M    | N.E.       | Valid          | Pop top of stack into m32; increment
|       |            |      |            |                | stack pointer.                      
| 8F /0 | POP r/m64  | M    | Valid      | N.E.           | Pop top of stack into m64; increment
|       |            |      |            |                | stack pointer. Cannot encode 32-bit 
|       |            |      |            |                | operand size.                       
| 58+ rw| POP r16    | O    | Valid      | Valid          | Pop top of stack into r16; increment
|       |            |      |            |                | stack pointer.                      
| 58+ rd| POP r32    | O    | N.E.       | Valid          | Pop top of stack into r32; increment
|       |            |      |            |                | stack pointer.                      
| 58+ rd| POP r64    | O    | Valid      | N.E.           | Pop top of stack into r64; increment
|       |            |      |            |                | stack pointer. Cannot encode 32-bit 
|       |            |      |            |                | operand size.                       
| 1F    | POP DS     | NP   | Invalid    | Valid          | Pop top of stack into DS; increment 
|       |            |      |            |                | stack pointer.                      
| 07    | POP ES     | NP   | Invalid    | Valid          | Pop top of stack into ES; increment 
|       |            |      |            |                | stack pointer.                      
| 17    | POP SS     | NP   | Invalid    | Valid          | Pop top of stack into SS; increment 
|       |            |      |            |                | stack pointer.                      
| 0F A1 | POP FS     | NP   | Valid      | Valid          | Pop top of stack into FS; increment 
|       |            |      |            |                | stack pointer by 16 bits.           
| 0F A1 | POP FS     | NP   | N.E.       | Valid          | Pop top of stack into FS; increment 
|       |            |      |            |                | stack pointer by 32 bits.           
| 0F A1 | POP FS     | NP   | Valid      | N.E.           | Pop top of stack into FS; increment 
|       |            |      |            |                | stack pointer by 64 bits.           
| 0F A9 | POP GS     | NP   | Valid      | Valid          | Pop top of stack into GS; increment 
|       |            |      |            |                | stack pointer by 16 bits.           
| 0F A9 | POP GS     | NP   | N.E.       | Valid          | Pop top of stack into GS; increment 
|       |            |      |            |                | stack pointer by 32 bits.           
| 0F A9 | POP GS     | NP   | Valid      | N.E.           | Pop top of stack into GS; increment 
|       |            |      |            |                | stack pointer by 64 bits.           

Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)  | NA       | NA       | NA       
| O    | opcode + rd (w)| NA       | NA       | NA       
| NP   | NA             | NA       | NA       | NA       

Description:
Loads the value from the top of the stack to the location specified with the
destination operand (or explicit opcode) and then increments the stack pointer.
The destination operand can be a general-purpose register, memory location,
or segment register.

Address and operand sizes are determined and used as follows:

 - Address size. The D flag in the current code-segment descriptor determines the
default address size; it may be overridden by an instruction prefix (67H). The
address size is used only when writing to a destination operand in memory.
 - Operand size. The D flag in the current code-segment descriptor determines the
default operand size; it may be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the amount by which the stack
pointer is incremented (2, 4 or 8).
 - Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment
descriptor determines the size of the stack pointer (16 or 32 bits); in 64-bit
mode, the size of the stack pointer is always 64 bits. The stack-address size
determines the width of the stack pointer when reading from the stack in memory
and when incrementing the stack pointer. (As stated above, the amount by which
the stack pointer is incremented is determined by the operand size.)

If the destination operand is one of the segment registers DS, ES, FS, GS, or
SS, the value loaded into the register must be a valid segment selector. In
protected mode, popping a segment selector into a segment register automatically
causes the descriptor information associated with that segment selector to be
loaded into the hidden (shadow) part of the segment register and causes the
selector and the descriptor information to be validated (see the “Operation”
section below).

A NULL value (0000-0003) may be popped into the DS, ES, FS, or GS register without
causing a general protection fault. However, any subsequent attempt to reference
a segment whose corresponding segment register is loaded with a NULL value causes
a general protection exception (#GP). In this situation, no memory reference
occurs and the saved value of the segment register is NULL.

The POP instruction cannot pop a value into the CS register. To load the CS
register from the stack, use the RET instruction.

If the ESP register is used as a base register for addressing a destination
operand in memory, the POP instruction computes the effective address of the
operand after it increments the ESP register. For the case of a 16-bit stack
where ESP wraps to 0H as a result of the POP instruction, the resulting location
of the memory write is processorfamily-specific.

The POP ESP instruction increments the stack pointer (ESP) before data at the
old top of stack is written into the destination.

A POP SS instruction inhibits all interrupts, including the NMI interrupt, until
after execution of the next instruction. This action allows sequential execution
of POP SS and MOV ESP, EBP instructions without the danger of having an invalid
stack during an interrupt1. However, use of the LSS instruction is the preferred
method of loading the SS and ESP registers.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). When in 64-bit mode, POPs using 32-bit operands are not
encodable and POPs to DS, ES, SS are not valid. See the summary chart at the
beginning of this section for encoding data and limits.

Operation:

IF StackAddrSize = 32
  THEN
     IF OperandSize = 32
       THEN
          DEST <- SS:ESP; (* Copy a doubleword *)
          ESP <- ESP + 4;
       ELSE (* OperandSize = 16*)
          DEST <- SS:ESP; (* Copy a word *)
1.
  may not be triggered. However, in a sequence of instructions that POP the SS register, only the first instruction in the sequence is
  guaranteed to delay an interrupt.
  In the following sequence, interrupts may be recognized before POP ESP executes:
  POP SS
  POP SS
  POP ESP
          ESP <- ESP + 2;
     FI;
  ELSE IF StackAddrSize = 64
     THEN
       IF OperandSize = 64
          THEN
             DEST <- SS:RSP; (* Copy quadword *)
             RSP <- RSP + 8;
          ELSE (* OperandSize = 16*)
             DEST <- SS:RSP; (* Copy a word *)
             RSP <- RSP + 2;
       FI;
     FI;
  ELSE StackAddrSize = 16
     THEN
       IF OperandSize = 16
          THEN
             DEST <- SS:SP; (* Copy a word *)
             SP <- SP + 2;
          ELSE (* OperandSize = 32 *)
             DEST <- SS:SP; (* Copy a doubleword *)
             SP <- SP + 4;
       FI;
FI;
Loading a segment register while in protected mode results in special actions, as described in the following listing.
These checks are performed on the segment selector and the segment descriptor it points to.
64-BIT_MODE
IF FS, or GS is loaded with non-NULL selector;
  THEN
     IF segment selector index is outside descriptor table limits
       OR segment is not a data or readable code segment
       OR ((segment is a data or nonconforming code segment)
          AND (both RPL and CPL > DPL))
             THEN #GP(selector);
       IF segment not marked present
          THEN #NP(selector);
     ELSE
       SegmentRegister <- segment selector;
       SegmentRegister <- segment descriptor;
     FI;
FI;
IF FS, or GS is loaded with a NULL selector;
     THEN
       SegmentRegister <- segment selector;
       SegmentRegister <- segment descriptor;
FI;
PREOTECTED MODE OR COMPATIBILITY MODE;
IF SS is loaded;
  THEN
     IF segment selector is NULL
       THEN #GP(0);
     FI;
     IF segment selector index is outside descriptor table limits
       or segment selector's RPL != CPL
       or segment is not a writable data segment
       or DPL != CPL
          THEN #GP(selector);
     FI;
     IF segment not marked present
       THEN #SS(selector);
       ELSE
          SS <- segment selector;
          SS <- segment descriptor;
     FI;
FI;
IF DS, ES, FS, or GS is loaded with non-NULL selector;
  THEN
     IF segment selector index is outside descriptor table limits
       or segment is not a data or readable code segment
       or ((segment is a data or nonconforming code segment)
       and (both RPL and CPL > DPL))
          THEN #GP(selector);
     FI;
     IF segment not marked present
       THEN #NP(selector);
       ELSE
          SegmentRegister <- segment selector;
          SegmentRegister <- segment descriptor;
     FI;
FI;
IF DS, ES, FS, or GS is loaded with a NULL selector
  THEN
     SegmentRegister <- segment selector;
     SegmentRegister <- segment descriptor;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)       | If attempt is made to load SS register        
|              | with NULL segment selector. If the destination
|              | operand is in a non-writable segment.         
|              | If a memory operand effective address         
|              | is outside the CS, DS, ES, FS, or GS          
|              | segment limit. If the DS, ES, FS, or          
|              | GS register is used to access memory          
|              | and it contains a NULL segment selector.      
| #GP(selector)| If segment selector index is outside          
|              | descriptor table limits. If the SS register   
|              | is being loaded and the segment selector's    
|              | RPL and the segment descriptor's DPL          
|              | are not equal to the CPL.                     
If the SS register is being loaded and the segment pointed to is a non-writable
data segment. If the DS, ES, FS, or GS register is being loaded and the segment
pointed to is not a data or readable code segment. If the DS, ES, FS, or GS
register is being loaded and the segment pointed to is a data or nonconforming
code segment, but both the RPL and the CPL are greater than the DPL.

| #SS(0)         | If the current top of stack is not within
|                | the stack segment. If a memory operand   
|                | effective address is outside the SS      
|                | segment limit.                           
| #SS(selector)  | If the SS register is being loaded and   
|                | the segment pointed to is marked not     
|                | present.                                 
| #NP            | If the DS, ES, FS, or GS register is     
|                | being loaded and the segment pointed     
|                | to is marked not present.                
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If an unaligned memory reference is      
|                | made while the current privilege level   
|                | is 3 and alignment checking is enabled.  
| #UD            | If the LOCK prefix is used.              

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address    
|                | is outside the CS, DS, ES, FS, or GS     
|                | segment limit.                           
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If an unaligned memory reference is      
|                | made while alignment checking is enabled.
| #UD            | If the LOCK prefix is used.              

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #SS(U)         | If the stack address is in a non-canonical 
|                | form.                                      
| #GP(selector)  | If the descriptor is outside the descriptor
|                | table limit. If the FS or GS register      
|                | is being loaded and the segment pointed    
|                | to is not a data or readable code segment. 
|                | If the FS or GS register is being loaded   
|                | and the segment pointed to is a data       
|                | or nonconforming code segment, but both    
|                | the RPL and the CPL are greater than       
|                | the DPL.                                   
| #AC(0)         | If an unaligned memory reference is        
|                | made while alignment checking is enabled.  
| #PF(fault-code)| If a page fault occurs.                    
| #NP            | If the FS or GS register is being loaded   
|                | and the segment pointed to is marked       
|                | not present.                               
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: POPA
description:
POPA/POPAD - Pop All General-Purpose Registers:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 61    | POPA       | NP   | Invalid    | Valid          | Pop DI, SI, BP, BX, DX, CX, and AX.  
| 61    | POPAD      | NP   | Invalid    | Valid          | Pop EDI, ESI, EBP, EBX, EDX, ECX, and
|       |            |      |            |                | EAX.                                 

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Pops doublewords (POPAD) or words (POPA) from the stack into the general-purpose
registers. The registers are loaded in the following order: EDI, ESI, EBP, EBX,
EDX, ECX, and EAX (if the operand-size attribute is 32) and DI, SI, BP, BX,
DX, CX, and AX (if the operand-size attribute is 16). (These instructions reverse
the operation of the PUSHA/PUSHAD instructions.) The value on the stack for
the ESP or SP register is ignored. Instead, the ESP or SP register is incremented
after each register is loaded.

The POPA (pop all) and POPAD (pop all double) mnemonics reference the same opcode.
The POPA instruction is intended for use when the operand-size attribute is
16 and the POPAD instruction for when the operand-size attribute is 32. Some
assemblers may force the operand size to 16 when POPA is used and to 32 when
POPAD is used (using the operand-size override prefix [66H] if necessary). Others
may treat these mnemonics as synonyms (POPA/POPAD) and use the current setting
of the operand-size attribute to determine the size of values to be popped from
the stack, regardless of the mnemonic used. (The D flag in the current code
segment's segment descriptor determines the operand-size attribute.)

This instruction executes as described in non-64-bit modes. It is not valid
in 64-bit mode.

Operation:

IF 64-Bit Mode
  THEN
     #UD;
ELSE
  IF OperandSize = 32 (* Instruction = POPAD *)
  THEN
     EDI <- Pop();
     ESI <- Pop();
     EBP <- Pop();
     Increment ESP by 4; (* Skip next 4 bytes of stack *)
     EBX <- Pop();
     EDX <- Pop();
     ECX <- Pop();
     EAX <- Pop();
  ELSE (* OperandSize = 16, instruction = POPA *)
     DI <- Pop();
     SI <- Pop();
     BP <- Pop();
     Increment ESP by 2; (* Skip next 2 bytes of stack *)
     BX <- Pop();
     DX <- Pop();
     CX <- Pop();
     AX <- Pop();
  FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #SS(0)         | If the starting or ending stack address
|                | is not within the stack segment.       
| #PF(fault-code)| If a page fault occurs.                
| #AC(0)         | If an unaligned memory reference is    
|                | made while the current privilege level 
|                | is 3 and alignment checking is enabled.
| #UD            | If the LOCK prefix is used.            

Real-Address Mode Exceptions:
| #SS| If the starting or ending stack address
|    | is not within the stack segment.       
| #UD| If the LOCK prefix is used.            

Virtual-8086 Mode Exceptions:
| #SS(0)         | If the starting or ending stack address  
|                | is not within the stack segment.         
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If an unaligned memory reference is      
|                | made while alignment checking is enabled.
| #UD            | If the LOCK prefix is used.              

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #UD| If in 64-bit mode.


platform: x86
mnem: POPCNT
description:
POPCNT  -  Return the Count of Number of Bits Set to 1:
| Opcode           | Instruction      | Op/En| 64-Bit Mode| Compat/Leg Mode| Description    
| F3               | POPCNT r16, r/m16| RM   | Valid      | Valid          | POPCNT on r/m16
| F3               | POPCNT r32, r/m32| RM   | Valid      | Valid          | POPCNT on r/m32
| F3 REX.W 0F B8 /r| POPCNT r64, r/m64| RM   | Valid      | N.E.           | POPCNT on r/m64

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
This instruction calculates of number of bits set to 1 in the second operand
(source) and returns the count in the first operand (a destination register).

Operation:

Count = 0;
For (i=0; i < OperandSize; i++)
{
     THEN Count++; FI;
}
DEST <- Count;

Flags Affected:
OF, SF, ZF, AF, CF, PF are all cleared. ZF is set if SRC = 0, otherwise ZF is
cleared


Intel C/C++ Compiler Intrinsic Equivalent:
| POPCNT:| int _mm_popcnt_u32(unsigned int a);    
| POPCNT:| int64_t _mm_popcnt_u64(unsigned __int64
|        | a);                                    

Protected Mode Exceptions:
| #GP(0)          | If a memory operand effective address    
|                 | is outside the CS, DS, ES, FS or GS      
|                 | segments.                                
| #SS(0)          | If a memory operand effective address    
|                 | is outside the SS segment limit.         
| #PF (fault-code)| For a page fault.                        
| #AC(0)          | If an unaligned memory reference is      
|                 | made while the current privilege level   
|                 | is 3 and alignment checking is enabled.  
| #UD             | If CPUID.01H:ECX.POPCNT [Bit 23] = 0.    
|                 | If LOCK prefix is used. Either the prefix
|                 | REP (F3h) or REPN (F2H) is used.         

Real-Address Mode Exceptions:
| #GP(0)| If any part of the operand lies outside  
|       | of the effective address space from      
|       | 0 to 0FFFFH.                             
| #SS(0)| If a memory operand effective address    
|       | is outside the SS segment limit.         
| #UD   | If CPUID.01H:ECX.POPCNT [Bit 23] = 0.    
|       | If LOCK prefix is used. Either the prefix
|       | REP (F3h) or REPN (F2H) is used.         

Virtual 8086 Mode Exceptions:
| #GP(0)          | If any part of the operand lies outside  
|                 | of the effective address space from      
|                 | 0 to 0FFFFH.                             
| #SS(0)          | If a memory operand effective address    
|                 | is outside the SS segment limit.         
| #PF (fault-code)| For a page fault.                        
| #AC(0)          | If an unaligned memory reference is      
|                 | made while alignment checking is enabled.
| #UD             | If CPUID.01H:ECX.POPCNT [Bit 23] = 0.    
|                 | If LOCK prefix is used. Either the prefix
|                 | REP (F3h) or REPN (F2H) is used.         

Compatibility Mode Exceptions:
Same exceptions as in Protected Mode.


64-Bit Mode Exceptions:
| #GP(0)          | If the memory address is in a non-canonical
|                 | form.                                      
| #SS(0)          | If a memory address referencing the        
|                 | SS segment is in a non-canonical form.     
| #PF (fault-code)| For a page fault.                          
| #AC(0)          | If alignment checking is enabled and       
|                 | an unaligned memory reference is made      
|                 | while the current privilege level is       
|                 | 3.                                         
| #UD             | If CPUID.01H:ECX.POPCNT [Bit 23] = 0.      
|                 | If LOCK prefix is used. Either the prefix  
|                 | REP (F3h) or REPN (F2H) is used.           


platform: x86
mnem: POPF
description:
POPF/POPFD/POPFQ - Pop Stack into EFLAGS Register:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 9D    | POPF       | NP   | Valid      | Valid          | Pop top of stack into lower 16 bits  
|       |            |      |            |                | of EFLAGS.                           
| 9D    | POPFD      | NP   | N.E.       | Valid          | Pop top of stack into EFLAGS.        
| 9D    | POPFQ      | NP   | Valid      | N.E.           | Pop top of stack and zero-extend into
|       |            |      |            |                | RFLAGS.                              

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Pops a doubleword (POPFD) from the top of the stack (if the current operand-size
attribute is 32) and stores the value in the EFLAGS register, or pops a word
from the top of the stack (if the operand-size attribute is 16) and stores it
in the lower 16 bits of the EFLAGS register (that is, the FLAGS register). These
instructions reverse the operation of the PUSHF/PUSHFD instructions.

The POPF (pop flags) and POPFD (pop flags double) mnemonics reference the same
opcode. The POPF instruction is intended for use when the operand-size attribute
is 16; the POPFD instruction is intended for use when the operand-size attribute
is 32. Some assemblers may force the operand size to 16 for POPF and to 32 for
POPFD. Others may treat the mnemonics as synonyms (POPF/POPFD) and use the setting
of the operand-size attribute to determine the size of values to pop from the
stack.

The effect of POPF/POPFD on the EFLAGS register changes, depending on the mode
of operation. When the processor is operating in protected mode at privilege
level 0 (or in real-address mode, the equivalent to privilege level 0), all
non-reserved flags in the EFLAGS register except RF1, VIP, VIF, and VM may be
modified. VIP, VIF and VM remain unaffected.

When operating in protected mode with a privilege level greater than 0, but
less than or equal to IOPL, all flags can be modified except the IOPL field
and VIP, VIF, and VM. Here, the IOPL flags are unaffected, the VIP and VIF flags
are cleared, and the VM flag is unaffected. The interrupt flag (IF) is altered
only when executing at a level at least as privileged as the IOPL. If a POPF/POPFD
instruction is executed with insufficient privilege, an exception does not occur
but privileged bits do not change.

When operating in virtual-8086 mode, the IOPL must be equal to 3 to use POPF/POPFD
instructions; VM, RF, IOPL, VIP, and VIF are unaffected. If the IOPL is less
than 3, POPF/POPFD causes a general-protection exception (#GP).

In 64-bit mode, use REX.W to pop the top of stack to RFLAGS. The mnemonic assigned
is POPFQ (note that the 32bit operand is not encodable). POPFQ pops 64 bits
from the stack, loads the lower 32 bits into RFLAGS, and zero extends the upper
bits of RFLAGS.

See Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for more information about the EFLAGS registers.

Operation:

IF VM = 0 (* Not in Virtual-8086 Mode *)
  THEN IF CPL = 0
     THEN
       IF OperandSize = 32;
          THEN
             EFLAGS <- Pop(); (* 32-bit pop *)
             (* All non-reserved flags except RF, VIP, VIF, and VM can be modified;
             VIP and VIF are cleared; RF, VM, and all reserved bits are unaffected. *)
          ELSE IF (Operandsize = 64)
1.
             RFLAGS = Pop(); (* 64-bit pop *)
             (* All non-reserved flags except RF, VIP, VIF, and VM can be modified; VIP
             and VIF are cleared; RF, VM, and all reserved bits are unaffected.*)
          ELSE (* OperandSize = 16 *)
             EFLAGS[15:0] <- Pop(); (* 16-bit pop *)
             (* All non-reserved flags can be modified. *)
       FI;
     ELSE (* CPL > 0 *)
       IF OperandSize = 32
          THEN
             IF CPL > IOPL
               THEN
                  EFLAGS <- Pop(); (* 32-bit pop *)
                  (* All non-reserved bits except IF, IOPL, RF, VIP, and
                  VIF can be modified; IF, IOPL, RF, VM, and all reserved
                  bits are unaffected; VIP and VIF are cleared. *)
               ELSE
                  EFLAGS <- Pop(); (* 32-bit pop *)
                  (* All non-reserved bits except IOPL, RF, VIP, and VIF can be
                  modified; IOPL, RF, VM, and all reserved bits are
                  unaffected; VIP and VIF are cleared. *)
             FI;
          ELSE IF (Operandsize = 64)
             IF CPL > IOPL
               THEN
                  RFLAGS <- Pop(); (* 64-bit pop *)
                  (* All non-reserved bits except IF, IOPL, RF, VIP, and
                  VIF can be modified; IF, IOPL, RF, VM, and all reserved
                  bits are unaffected; VIP and VIF are cleared. *)
               ELSE
                  RFLAGS <- Pop(); (* 64-bit pop *)
                  (* All non-reserved bits except IOPL, RF, VIP, and VIF can be
                  modified; IOPL, RF, VM, and all reserved bits are
                  unaffected; VIP and VIF are cleared. *)
             FI;
          ELSE (* OperandSize = 16 *)
             EFLAGS[15:0] <- Pop(); (* 16-bit pop *)
             (* All non-reserved bits except IOPL can be modified; IOPL and all
             reserved bits are unaffected. *)
       FI;
     FI;
  ELSE
     IF IOPL = 3
       THEN IF OperandSize = 32
          THEN
             EFLAGS <- Pop();
             (* All non-reserved bits except VM, RF, IOPL, VIP, and VIF can be
             modified; VM, RF, IOPL, VIP, VIF, and all reserved bits are unaffected. *)
          ELSE
             EFLAGS[15:0] <- Pop(); FI;
             (* All non-reserved bits except IOPL can be modified;
             IOPL and all reserved bits are unaffected. *)
     ELSE (* IOPL < 3 *)
       #GP(0);
     FI;
  FI;
FI;

Flags Affected:
All flags may be affected; see the Operation section for details.


Protected Mode Exceptions:
| #SS(0)         | If the top of stack is not within the  
|                | stack segment.                         
| #PF(fault-code)| If a page fault occurs.                
| #AC(0)         | If an unaligned memory reference is    
|                | made while the current privilege level 
|                | is 3 and alignment checking is enabled.
| #UD            | If the LOCK prefix is used.            

Real-Address Mode Exceptions:
| #SS| If the top of stack is not within the
|    | stack segment.                       
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If the I/O privilege level is less than        
|                | 3. If an attempt is made to execute            
|                | the POPF/POPFD instruction with an operand-size
|                | override prefix.                               
| #SS(0)         | If the top of stack is not within the          
|                | stack segment.                                 
| #PF(fault-code)| If a page fault occurs.                        
| #AC(0)         | If an unaligned memory reference is            
|                | made while alignment checking is enabled.      
| #UD            | If the LOCK prefix is used.                    

Compatibility Mode Exceptions:
Same as for protected mode exceptions.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #SS(0)         | If the stack address is in a non-canonical 
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: POR
description:
POR - Bitwise Logical OR:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                      
| 0F EB /r1 POR mm, mm/m64              | RM   | V/V                   | MMX               | Bitwise OR of mm/m64 and mm.     
| 66 0F EB /r POR xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Bitwise OR of xmm2/m128 and xmm1.
| VEX.NDS.128.66.0F.WIG EB /r VPOR xmm1,| RVM  | V/V                   | AVX               | Bitwise OR of xmm2/m128 and xmm3.
| xmm2, xmm3/m128                       |      |                       |                   |                                  
| VEX.NDS.256.66.0F.WIG EB /r VPOR ymm1,| RVM  | V/V                   | AVX2              | Bitwise OR of ymm2/m256 and ymm3.
| ymm2, ymm3/m256                       |      |                       |                   |                                  
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical OR operation on the source operand (second operand)
and the destination operand (first operand) and stores the result in the destination
operand. Each bit of the result is set to 1 if either or both of the corresponding
bits of the first and second operands are 1; otherwise, it is set to 0.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand is an MMX technology register.

128-bit Legacy SSE version: The second source operand is an XMM register or
a 128-bit memory location. The first source and destination operands can be
XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The second source operand is an XMM
register or a 128-bit memory location. The first source and destination operands
can be XMM registers. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.256 encoded version: The second source operand is an YMM register
or a 256-bit memory location. The first source and destination operands can
be YMM registers.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

POR (128-bit Legacy SSE version)
DEST <- DEST OR SRC
DEST[VLMAX-1:128] (Unmodified)
VPOR (VEX.128 encoded version)
DEST <- SRC1 OR SRC2
DEST[VLMAX-1:128] <- 0
VPOR (VEX.256 encoded version)
DEST <- SRC1 OR SRC2

Intel C/C++ Compiler Intrinsic Equivalent:
| POR:   | __m64 _mm_or_si64(__m64 m1, __m64 m2)   
| (V)POR:| __m128i _mm_or_si128(__m128i m1, __m128i
|        | m2)                                     
| VPOR:  | __m256i _mm256_or_si256 ( __m256i a,    
|        | __m256i b)                              

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PREFETCHh
description:
PREFETCHh - Prefetch Data Into Caches:
| Opcode  | Instruction   | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 0F 18 /1| PREFETCHT0 m8 | M    | Valid      | Valid          | Move data from m8 closer to the processor
|         |               |      |            |                | using T0 hint.                           
| 0F 18 /2| PREFETCHT1 m8 | M    | Valid      | Valid          | Move data from m8 closer to the processor
|         |               |      |            |                | using T1 hint.                           
| 0F 18 /3| PREFETCHT2 m8 | M    | Valid      | Valid          | Move data from m8 closer to the processor
|         |               |      |            |                | using T2 hint.                           
| 0F 18 /0| PREFETCHNTA m8| M    | Valid      | Valid          | Move data from m8 closer to the processor
|         |               |      |            |                | using NTA hint.                          

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Fetches the line of data from memory that contains the byte specified with the
source operand to a location in the cache hierarchy specified by a locality
hint:

 - T0 (temporal data) - prefetch data into all levels of the cache hierarchy.  - Pentium
III processor - 1st- or 2nd-level cache.  - Pentium 4 and Intel Xeon processors - 2nd-level
cache.
 - T1 (temporal data with respect to first level cache) - prefetch data into level
2 cache and higher.  - Pentium III processor - 2nd-level cache.  - Pentium 4 and Intel
Xeon processors - 2nd-level cache.
 - T2 (temporal data with respect to second level cache) - prefetch data into level
2 cache and higher.  - Pentium III processor - 2nd-level cache.  - Pentium 4 and Intel
Xeon processors - 2nd-level cache.
 - NTA (non-temporal data with respect to all cache levels) - prefetch data into
non-temporal cache structure and into a location close to the processor, minimizing
cache pollution.  - Pentium III processor - 1st-level cache  - Pentium 4 and Intel
Xeon processors - 2nd-level cache

The source operand is a byte memory location. (The locality hints are encoded
into the machine level instruction using bits 3 through 5 of the ModR/M byte.)

If the line selected is already present in the cache hierarchy at a level closer
to the processor, no data movement occurs. Prefetches from uncacheable or WC
memory are ignored.

The PREFETCHh instruction is merely a hint and does not affect program behavior.
If executed, this instruction moves data closer to the processor in anticipation
of future use.

The implementation of prefetch locality hints is implementation-dependent, and
can be overloaded or ignored by a processor implementation. The amount of data
prefetched is also processor implementation-dependent. It will, however, be
a minimum of 32 bytes.

It should be noted that processors are free to speculatively fetch and cache
data from system memory regions that are assigned a memory-type that permits
speculative reads (that is, the WB, WC, and WT memory types). A PREFETCHh instruction
is considered a hint to this speculative behavior. Because this speculative
fetching can occur at any time and is not tied to instruction execution, a PREFETCHh
instruction is not ordered with respect to the fence instructions (MFENCE, SFENCE,
and LFENCE) or locked memory references. A PREFETCHh instruction is also

unordered with respect to CLFLUSH instructions, other PREFETCHh instructions,
or any other general instruction. It is ordered with respect to serializing
instructions such as CPUID, WRMSR, OUT, and MOV CR.

This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FETCH (m8);

Intel C/C++ Compiler Intrinsic Equivalent:
void _mm_prefetch(char *p, int i)

The argument “*p” gives the address of the byte (and corresponding cache line)
to be prefetched. The value “i”gives a constant (_MM_HINT_T0, _MM_HINT_T1, _MM_HINT_T2,
or _MM_HINT_NTA) that specifies the type of prefetch operation to be performed.


Numeric Exceptions:
None.


Exceptions (All Operating Modes):
| #UD| If the LOCK prefix is used.


platform: x86
mnem: PREFETCHW
description:
PREFETCHW - Prefetch Data into Caches in Anticipation of a Write:
| Opcode/Instruction   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F 0D /1 PREFETCHW m8| A    | V/V                   | PRFCHW            | Move data from m8 closer to the processor
|                      |      |                       |                   | in anticipation of a write.              

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)| NA       | NA       | NA       

Description:
Fetches the cache line of data from memory that contains the byte specified
with the source operand to a location in the 1st or 2nd level cache and invalidates
all other cached instances of the line. The source operand is a byte memory
location. If the line selected is already present in the lowest level cache
and is already in an exclusively owned state, no data movement occurs. Prefetches
from non-writeback memory are ignored. The PREFETCHW instruction is merely a
hint and does not affect program behavior. If executed, this instruction moves
data closer to the processor and invalidates any other cached copy in anticipation
of the line being written to in the future. The characteristic of prefetch locality
hints is implementation-dependent, and can be overloaded or ignored by a processor
implementation. The amount of data prefetched is also processor implementation-dependent.
It will, however, be a minimum of 32 bytes. It should be noted that processors
are free to speculatively fetch and cache data with exclusive ownership from
system memory regions that permit such accesses (that is, the WB memory type).
A PREFETCHW instruction is considered a hint to this speculative behavior. Because
this speculative fetching can occur at any time and is not tied to instruction
execution, a PREFETCHW instruction is not ordered with respect to the fence
instructions (MFENCE, SFENCE, and LFENCE) or locked memory references. A PREFETCHW
instruction is also unordered with respect to CLFLUSH instructions, other PREFETCHW
instructions, or any other general instruction It is ordered with respect to
serializing instructions such as CPUID, WRMSR, OUT, and MOV CR. This instruction's
operation is the same in non-64-bit modes and 64-bit mode.

Operation:

FETCH_WITH_EXCLUSIVE_OWNERSHIP (m8);

Flags Affected:
All flags are affected


C/C++ Compiler Intrinsic Equivalent:
void _m_prefetchw( void * );


Protected Mode Exceptions:
| #UD| If the LOCK prefix is used.

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #UD| If the LOCK prefix is used.

Compatibility Mode Exceptions:
| #UD| If the LOCK prefix is used.

64-Bit Mode Exceptions:
| #UD| If the LOCK prefix is used.


platform: x86
mnem: PSADBW
description:
PSADBW - Compute Sum of Absolute Differences:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 0F F6 /r1 PSADBW mm1, mm2/m64      | RM   | V/V                   | SSE               | Computes the absolute differences of      
|                                    |      |                       |                   | the packed unsigned byte integers from    
|                                    |      |                       |                   | mm2 /m64 and mm1; differences are then    
|                                    |      |                       |                   | summed to produce an unsigned word integer
|                                    |      |                       |                   | result.                                   
| 66 0F F6 /r PSADBW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Computes the absolute differences of      
|                                    |      |                       |                   | the packed unsigned byte integers from    
|                                    |      |                       |                   | xmm2 /m128 and xmm1; the 8 low differences
|                                    |      |                       |                   | and 8 high differences are then summed    
|                                    |      |                       |                   | separately to produce two unsigned word   
|                                    |      |                       |                   | integer results.                          
| VEX.NDS.128.66.0F.WIG F6 /r VPSADBW| RVM  | V/V                   | AVX               | Computes the absolute differences of      
| xmm1, xmm2, xmm3/m128              |      |                       |                   | the packed unsigned byte integers from    
|                                    |      |                       |                   | xmm3 /m128 and xmm2; the 8 low differences
|                                    |      |                       |                   | and 8 high differences are then summed    
|                                    |      |                       |                   | separately to produce two unsigned word   
|                                    |      |                       |                   | integer results.                          
| VEX.NDS.256.66.0F.WIG F6 /r VPSADBW| RVM  | V/V                   | AVX2              | Computes the absolute differences of      
| ymm1, ymm2, ymm3/m256              |      |                       |                   | the packed unsigned byte integers from    
|                                    |      |                       |                   | ymm3 /m256 and ymm2; then each consecutive
|                                    |      |                       |                   | 8 differences are summed separately       
|                                    |      |                       |                   | to produce four unsigned word integer     
|                                    |      |                       |                   | results.                                  
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Computes the absolute value of the difference of 8 unsigned byte integers from
the source operand (second operand) and from the destination operand (first
operand). These 8 differences are then summed to produce an unsigned word integer
result that is stored in the destination operand. Figure 4-10 shows the operation
of the PSADBW instruction when using 64-bit operands.

When operating on 64-bit operands, the word integer result is stored in the
low word of the destination operand, and the remaining bytes in the destination
operand are cleared to all 0s.

When operating on 128-bit operands, two packed results are computed. Here, the
8 low-order bytes of the source and destination operands are operated on to
produce a word result that is stored in the low word of the destination operand,
and the 8 high-order bytes are operated on to produce a word result that is
stored in bits 64 through 79 of the destination operand. The remaining bytes
of the destination operand are cleared.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). Legacy SSE version: The source
operand can be an MMX technology register or a 64-bit memory location. The destination
operand is an MMX technology register.

128-bit Legacy SSE version: The first source operand and destination register
are XMM registers. The second source operand is an XMM register or a 128-bit
memory location. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged.

VEX.128 encoded version: The first source operand and destination register are
XMM registers. The second source operand is an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.256
encoded version: The first source operand and destination register are YMM registers.
The second source operand is an YMM register or a 256-bit memory location.

Note: VEX.L must be 0, otherwise the instruction will #UD.

| SRC Figure 4-10.| X7 Y7 ABS(X7:Y7) 00H| X6 Y6 ABS(X6:Y6) 00H PSADBW Instruction| X5 Y5 ABS(X5:Y5) 00H| X4 Y4 ABS(X4:Y4) 00H| X3 Y3 ABS(X3:Y3) 00H| X2 Y2 ABS(X2:Y2) 00H| X1 Y1 ABS(X1:Y1) SUM(TEMP7...TEMP0)| X0 Y0 ABS(X0:Y0) DEST
|                 |                     | Operation Using 64-bit Operands        |                     |                     |                     |                     |                                    |                      
Operation:

PSADBW (when using 64-bit operands)
  TEMP0 <- ABS(DEST[7:0] − SRC[7:0]);
  (* Repeat operation for bytes 2 through 6 *)
  TEMP7 <- ABS(DEST[63:56] − SRC[63:56]);
  DEST[15:0] <- SUM(TEMP0:TEMP7);
  DEST[63:16] <- 000000000000H;
PSADBW (when using 128-bit operands)
  TEMP0 <- ABS(DEST[7:0] − SRC[7:0]);
  (* Repeat operation for bytes 2 through 14 *)
  TEMP15 <- ABS(DEST[127:120] − SRC[127:120]);
  DEST[15:0] <- SUM(TEMP0:TEMP7);
  DEST[63:16] <- 000000000000H;
  DEST[79:64] <- SUM(TEMP8:TEMP15);
  DEST[127:80] <- 000000000000H;
  DEST[VLMAX-1:128] (Unmodified)
VPSADBW (VEX.128 encoded version)
TEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 14 *)
TEMP15 <- ABS(SRC1[127:120] - SRC2[127:120])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H
DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000
DEST[VLMAX-1:128] <- 0
VPSADBW (VEX.256 encoded version)
TEMP0 <- ABS(SRC1[7:0] - SRC2[7:0])
(* Repeat operation for bytes 2 through 30*)
TEMP31 <- ABS(SRC1[255:248] - SRC2[255:248])
DEST[15:0] <-SUM(TEMP0:TEMP7)
DEST[63:16] <- 000000000000H
DEST[79:64] <- SUM(TEMP8:TEMP15)
DEST[127:80] <- 00000000000H
DEST[143:128] <-SUM(TEMP16:TEMP23)
DEST[191:144] <- 000000000000H
DEST[207:192] <- SUM(TEMP24:TEMP31)
DEST[223:208] <- 00000000000H

Intel C/C++ Compiler Intrinsic Equivalent:
| PSADBW:   | __m64 _mm_sad_pu8(__m64 a,__m64 b)     
| (V)PSADBW:| __m128i _mm_sad_epu8(__m128i a, __m128i
|           | b)                                     
| VPSADBW:  | __m256i _mm256_sad_epu8( __m256i a,    
|           | __m256i b)                             

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSHUFB
description:
PSHUFB  -  Packed Shuffle Bytes:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F 38 00 /r1 PSHUFB mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Shuffle bytes in mm1 according to contents 
|                                      |      |                       |                   | of mm2/m64.                                
| 66 0F 38 00 /r PSHUFB xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Shuffle bytes in xmm1 according to contents
|                                      |      |                       |                   | of xmm2/m128.                              
| VEX.NDS.128.66.0F38.WIG 00 /r VPSHUFB| RVM  | V/V                   | AVX               | Shuffle bytes in xmm2 according to contents
| xmm1, xmm2, xmm3/m128                |      |                       |                   | of xmm3/m128.                              
| VEX.NDS.256.66.0F38.WIG 00 /r VPSHUFB| RVM  | V/V                   | AVX2              | Shuffle bytes in ymm2 according to contents
| ymm1, ymm2, ymm3/m256                |      |                       |                   | of ymm3/m256.                              
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
PSHUFB performs in-place shuffles of bytes in the destination operand (the first
operand) according to the shuffle control mask in the source operand (the second
operand). The instruction permutes the data in the destination operand, leaving
the shuffle mask unaffected. If the most significant bit (bit[7]) of each byte
of the shuffle control mask is set, then constant zero is written in the result
byte. Each byte in the shuffle control mask forms an index to permute the corresponding
byte in the destination operand. The value of each index is the least significant
4 bits (128-bit operation) or 3 bits (64-bit operation) of the shuffle control
byte. When the source operand is a 128-bit memory operand, the operand must
be aligned on a 16-byte boundary or a general-protection exception (#GP) will
be generated.

In 64-bit mode, use the REX prefix to access additional registers. Legacy SSE
version: Both operands can be MMX registers.

128-bit Legacy SSE version: The first source operand and the destination operand
are the same. Bits (VLMAX1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The destination operand is the first
operand, the first source operand is the second operand, the second source operand
is the third operand. Bits (VLMAX-1:128) of the destination YMM register are
zeroed. VEX.256 encoded version: Bits (255:128) of the destination YMM register
stores the 16-byte shuffle result of the upper 16 bytes of the first source
operand, using the upper 16-bytes of the second source operand as control mask.
The value of each index is for the high 128-bit lane is the least significant
4 bits of the respective shuffle control byte. The index value selects a source
data element within each 128-bit lane.

Note: VEX.L must be 0, otherwise the instruction will #UD.

Operation:

PSHUFB (with 64 bit operands)
  for i = 0 to 7 {
     if (SRC[(i * 8)+7] = 1 ) then
       DEST[(i*8)+7...(i*8)+0] <- 0;
     else
       index[2..0] <- SRC[(i*8)+2 .. (i*8)+0];
       DEST[(i*8)+7...(i*8)+0] <- DEST[(index*8+7)..(index*8+0)];
     endif;
  }
PSHUFB (with 128 bit operands)
  for i = 0 to 15 {
     if (SRC[(i * 8)+7] = 1 ) then
       DEST[(i*8)+7..(i*8)+0] <- 0;
     else
       index[3..0] <- SRC[(i*8)+3 .. (i*8)+0];
       DEST[(i*8)+7..(i*8)+0] <- DEST[(index*8+7)..(index*8+0)];
     endif
  }
DEST[VLMAX-1:128] <- 0
VPSHUFB (VEX.128 encoded version)
for i = 0 to 15 {
  if (SRC2[(i * 8)+7] = 1) then
     DEST[(i*8)+7..(i*8)+0] <- 0;
     else
     index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];
     DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];
  endif
}
DEST[VLMAX-1:128] <- 0
VPSHUFB (VEX.256 encoded version)
for i = 0 to 15 {
  if (SRC2[(i * 8)+7] == 1 ) then
     DEST[(i*8)+7..(i*8)+0] <- 0;
     else
     index[3..0] <- SRC2[(i*8)+3 .. (i*8)+0];
     DEST[(i*8)+7..(i*8)+0] <- SRC1[(index*8+7)..(index*8+0)];
  endif
  if (SRC2[128 + (i * 8)+7] == 1 ) then
     DEST[128 + (i*8)+7..(i*8)+0] <- 0;
     else
     index[3..0] <- SRC2[128 + (i*8)+3 .. (i*8)+0];
     DEST[128 + (i*8)+7..(i*8)+0] <- SRC1[128 + (index*8+7)..(index*8+0)];
  endif
}
                                 MM2
              07H
                                 MM1
              04H
                                 MM1
              04H
| Figure 4-11.| PSHUB with 64-Bit Operands

Intel C/C++ Compiler Intrinsic Equivalent:
| PSHUFB:   | __m64 _mm_shuffle_pi8 (__m64 a, __m64
|           | b)                                   
| (V)PSHUFB:| __m128i _mm_shuffle_epi8 (__m128i a, 
|           | __m128i b)                           
| VPSHUFB:  | __m256i _mm256_shuffle_epi8(__m256i  
|           | a, __m256i b)                        

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSHUFD
description:
PSHUFD - Shuffle Packed Doublewords:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 70 /r ib PSHUFD xmm1, xmm2/m128,  | RMI  | V/V                   | SSE2              | Shuffle the doublewords in xmm2/m128   
| imm8                                    |      |                       |                   | based on the encoding in imm8 and store
|                                         |      |                       |                   | the result in xmm1.                    
| VEX.128.66.0F.WIG 70 /r ib VPSHUFD xmm1,| RMI  | V/V                   | AVX               | Shuffle the doublewords in xmm2/m128   
| xmm2/m128, imm8                         |      |                       |                   | based on the encoding in imm8 and store
|                                         |      |                       |                   | the result in xmm1.                    
| VEX.256.66.0F.WIG 70 /r ib VPSHUFD ymm1,| RMI  | V/V                   | AVX2              | Shuffle the doublewords in ymm2/m256   
| ymm2/m256, imm8                         |      |                       |                   | based on the encoding in imm8 and store
|                                         |      |                       |                   | the result in ymm1.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Copies doublewords from source operand (second operand) and inserts them in
the destination operand (first operand) at the locations selected with the order
operand (third operand). Figure 4-12 shows the operation of the 256-bit VPSHUFD
instruction and the encoding of the order operand. Each 2-bit field in the order
operand selects the contents of one doubleword location within a 128-bit lane
and copy to the target element in the destination operand. For example, bits
0 and 1 of the order operand targets the first doubleword element in the low
and high 128-bit lane of the destination operand for 256-bit VPSHUFD. The encoded
value of bits 1:0 of the order operand (see the field encoding in Figure 4-12)
determines which doubleword element (from the respective 128-bit lane) of the
source operand will be copied to doubleword 0 of the destination operand. For
128-bit operation, only the low 128-bit lane are operative. The source operand
can be an XMM register or a 128-bit memory location. The destination operand
is an XMM register. The order operand is an 8-bit immediate. Note that this
instruction permits a doubleword in the source operand to be copied to more
than one doubleword location in the destination operand.

| SRC Encoding of Fields in Operand| X7 Y7 ORDER Figure 4-12.| X6 Y6 00B - X4 01B - X5 10B - X6 11B| X5 Y5 ORDER 256-bit VPSHUFD Instruction| X4 Y4 4 3| X3 Y3 0| X2 Y2 Encoding of Fields in ORDER Operand| X1 Y1 00B - X0 01B - X1 10B - X2 11B| X0 Y0
|                                  |                         | - X7                                | Operation                              |          |        |                                          | - X3                                |      
The source operand can be an XMM register or a 128-bit memory location. The
destination operand is an XMM register. The order operand is an 8-bit immediate.
Note that this instruction permits a doubleword in the source operand to be
copied to more than one doubleword location in the destination operand.

Legacy SSE instructions: In 64-bit mode using a REX prefix in the form of REX.R
permits this instruction to access additional registers (XMM8-XMM15). 128-bit
Legacy SSE version: Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: Bits (VLMAX-1:128) of the
destination YMM register are zeroed. VEX.256 encoded version: Bits (255:128)
of the destination stores the shuffled results of the upper 16 bytes of the
source operand using the immediate byte as the order operand.

Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise the
instruction will #UD.

Operation:

PSHUFD (128-bit Legacy SSE version)
DEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] (Unmodified)
VPSHUFD (VEX.128 encoded version)
DEST[31:0] <- (SRC >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC >> (ORDER[7:6] * 32))[31:0];
DEST[VLMAX-1:128] <- 0
VPSHUFD (VEX.256 encoded version)
DEST[31:0] <- (SRC[127:0] >> (ORDER[1:0] * 32))[31:0];
DEST[63:32] <- (SRC[127:0] >> (ORDER[3:2] * 32))[31:0];
DEST[95:64] <- (SRC[127:0] >> (ORDER[5:4] * 32))[31:0];
DEST[127:96] <- (SRC[127:0] >> (ORDER[7:6] * 32))[31:0];
DEST[159:128] <- (SRC[255:128] >> (ORDER[1:0] * 32))[31:0];
DEST[191:160] <- (SRC[255:128] >> (ORDER[3:2] * 32))[31:0];
DEST[223:192] <- (SRC[255:128] >> (ORDER[5:4] * 32))[31:0];
DEST[255:224] <- (SRC[255:128] >> (ORDER[7:6] * 32))[31:0];

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PSHUFD:| __m128i _mm_shuffle_epi32(__m128i a,
|           | int n)                              
| VPSHUFD:  | __m256i _mm256_shuffle_epi32(__m256i
|           | a, const int n)                     

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PSHUFHW
description:
PSHUFHW - Shuffle Packed High Words:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| F3 0F 70 /r ib PSHUFHW xmm1, xmm2/m128,| RMI  | V/V                   | SSE2              | Shuffle the high words in xmm2/m128    
| imm8                                   |      |                       |                   | based on the encoding in imm8 and store
|                                        |      |                       |                   | the result in xmm1.                    
| VEX.128.F3.0F.WIG 70 /r ib VPSHUFHW    | RMI  | V/V                   | AVX               | Shuffle the high words in xmm2/m128    
| xmm1, xmm2/m128, imm8                  |      |                       |                   | based on the encoding in imm8 and store
|                                        |      |                       |                   | the result in xmm1.                    
| VEX.256.F3.0F.WIG 70 /r ib VPSHUFHW    | RMI  | V/V                   | AVX2              | Shuffle the high words in ymm2/m256    
| ymm1, ymm2/m256, imm8                  |      |                       |                   | based on the encoding in imm8 and store
|                                        |      |                       |                   | the result in ymm1.                    

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Copies words from the high quadword of a 128-bit lane of the source operand
and inserts them in the high quadword of the destination operand at word locations
(of the respective lane) selected with the immediate operand. This 256-bit operation
is similar to the in-lane operation used by the 256-bit VPSHUFD instruction,
which is illustrated in Figure 4-12. For 128-bit operation, only the low 128-bit
lane is operative. Each 2-bit field in the immediate operand selects the contents
of one word location in the high quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3, 4) from
the high quadword of the source operand to be copied to the destination operand.
The low quadword of the source operand is copied to the low quadword of the
destination operand, for each 128-bit lane. Note that this instruction permits
a word in the high quadword of the source operand to be copied to more than
one word location in the high quadword of the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: The destination operand
is an XMM register. The source operand can be an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.vvvv
is reserved and must be 1111b, VEX.L must be 0, otherwise the instruction will
#UD. VEX.256 encoded version: The destination operand is an YMM register. The
source operand can be an YMM register or a 256-bit memory location. Note: In
VEX encoded versions VEX.vvvv is reserved and must be 1111b otherwise instructions
will #UD.

Operation:

PSHUFHW (128-bit Legacy SSE version)
DEST[63:0] <- SRC[63:0]
DEST[79:64] <- (SRC >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] (Unmodified)
VPSHUFHW (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[VLMAX-1:128] <- 0
VPSHUFHW (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0]
DEST[79:64] <- (SRC1 >> (imm[1:0] *16))[79:64]
DEST[95:80] <- (SRC1 >> (imm[3:2] * 16))[79:64]
DEST[111:96] <- (SRC1 >> (imm[5:4] * 16))[79:64]
DEST[127:112] <- (SRC1 >> (imm[7:6] * 16))[79:64]
DEST[191:128] <- SRC1[191:128]
DEST[207192] <- (SRC1 >> (imm[1:0] *16))[207:192]
DEST[223:208] <- (SRC1 >> (imm[3:2] * 16))[207:192]
DEST[239:224] <- (SRC1 >> (imm[5:4] * 16))[207:192]
DEST[255:240] <- (SRC1 >> (imm[7:6] * 16))[207:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PSHUFHW:| __m128i _mm_shufflehi_epi16(__m128i   
|            | a, int n)                             
| VPSHUFHW:  | __m256i _mm256_shufflehi_epi16(__m256i
|            | a, const int n)                       

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PSHUFLW
description:
PSHUFLW - Shuffle Packed Low Words:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| F2 0F 70 /r ib PSHUFLW xmm1, xmm2/m128,| RMI  | V/V                   | SSE2              | Shuffle the low words in xmm2/m128 based
| imm8                                   |      |                       |                   | on the encoding in imm8 and store the   
|                                        |      |                       |                   | result in xmm1.                         
| VEX.128.F2.0F.WIG 70 /r ib VPSHUFLW    | RMI  | V/V                   | AVX               | Shuffle the low words in xmm2/m128 based
| xmm1, xmm2/m128, imm8                  |      |                       |                   | on the encoding in imm8 and store the   
|                                        |      |                       |                   | result in xmm1.                         
| VEX.256.F2.0F.WIG 70 /r ib VPSHUFLW    | RMI  | V/V                   | AVX2              | Shuffle the low words in ymm2/m256 based
| ymm1, ymm2/m256, imm8                  |      |                       |                   | on the encoding in imm8 and store the   
|                                        |      |                       |                   | result in ymm1.                         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Copies words from the low quadword of a 128-bit lane of the source operand and
inserts them in the low quadword of the destination operand at word locations
(of the respective lane) selected with the immediate operand. The 256-bit operation
is similar to the in-lane operation used by the 256-bit VPSHUFD instruction,
which is illustrated in Figure 4-12. For 128-bit operation, only the low 128-bit
lane is operative. Each 2-bit field in the immediate operand selects the contents
of one word location in the low quadword of the destination operand. The binary
encodings of the immediate operand fields select words (0, 1, 2 or 3) from the
low quadword of the source operand to be copied to the destination operand.
The high quadword of the source operand is copied to the high quadword of the
destination operand, for each 128-bit lane. Note that this instruction permits
a word in the low quadword of the source operand to be copied to more than one
word location in the low quadword of the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
destination operand is an XMM register. The source operand can be an XMM register
or a 128-bit memory location. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: The destination operand
is an XMM register. The source operand can be an XMM register or a 128-bit memory
location. Bits (VLMAX-1:128) of the destination YMM register are zeroed. VEX.256
encoded version: The destination operand is an YMM register. The source operand
can be an YMM register or a 256-bit memory location.

Note: VEX.vvvv is reserved and must be 1111b, VEX.L must be 0, otherwise instructions
will #UD.

Operation:

PSHUFLW (128-bit Legacy SSE version)
DEST[15:0] <- (SRC >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)
VPSHUFLW (VEX.128 encoded version)
DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC[127:64]
DEST[VLMAX-1:128] <- 0
VPSHUFLW (VEX.256 encoded version)
DEST[15:0] <- (SRC1 >> (imm[1:0] *16))[15:0]
DEST[31:16] <- (SRC1 >> (imm[3:2] * 16))[15:0]
DEST[47:32] <- (SRC1 >> (imm[5:4] * 16))[15:0]
DEST[63:48] <- (SRC1 >> (imm[7:6] * 16))[15:0]
DEST[127:64] <- SRC1[127:64]
DEST[143:128] <- (SRC1 >> (imm[1:0] *16))[143:128]
DEST[159:144] <- (SRC1 >> (imm[3:2] * 16))[143:128]
DEST[175:160] <- (SRC1 >> (imm[5:4] * 16))[143:128]
DEST[191:176] <- (SRC1 >> (imm[7:6] * 16))[143:128]
DEST[255:192] <- SRC1[255:192]

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PSHUFLW:| __m128i _mm_shufflelo_epi16(__m128i   
|            | a, int n)                             
| VPSHUFLW:  | __m256i _mm256_shufflelo_epi16(__m256i
|            | a, const int n)                       

Flags Affected:
None.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1. If VEX.vvvv != 1111B.


platform: x86
mnem: PSHUFW
description:
PSHUFW - Shuffle Packed Words:
| Opcode/Instruction                   | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 0F 70 /r ib PSHUFW mm1, mm2/m64, imm8| RMI  | Valid      | Valid          | Shuffle the words in mm2/m64 based on    
|                                      |      |            |                | the encoding in imm8 and store the result
|                                      |      |            |                | in mm1.                                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RMI  | ModRM:reg (w)| ModRM:r/m (r)| imm8     | NA       

Description:
Copies words from the source operand (second operand) and inserts them in the
destination operand (first operand) at word locations selected with the order
operand (third operand). This operation is similar to the operation used by
the PSHUFD instruction, which is illustrated in Figure 4-12. For the PSHUFW
instruction, each 2-bit field in the order operand selects the contents of one
word location in the destination operand. The encodings of the order operand
fields select words from the source operand to be copied to the destination
operand.

The source operand can be an MMX technology register or a 64-bit memory location.
The destination operand is an MMX technology register. The order operand is
an 8-bit immediate. Note that this instruction permits a word in the source
operand to be copied to more than one word location in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Operation:

DEST[15:0] <- (SRC >> (ORDER[1:0] * 16))[15:0];
DEST[31:16] <- (SRC >> (ORDER[3:2] * 16))[15:0];
DEST[47:32] <- (SRC >> (ORDER[5:4] * 16))[15:0];
DEST[63:48] <- (SRC >> (ORDER[7:6] * 16))[15:0];

Intel C/C++ Compiler Intrinsic Equivalent:
| PSHUFW:| __m64 _mm_shuffle_pi16(__m64 a, int
|        | n)                                 

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Table 22-7, “Exception Conditions for SIMD/MMX Instructions with Memory
Reference,” in the Intel® 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A.


platform: x86
mnem: PSIGNB
description:
PSIGNB/PSIGNW/PSIGND  -  Packed SIGN:
| Opcode/Instruction                   | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                    
| 0F 38 08 /r1 PSIGNB mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Negate/zero/preserve packed byte integers      
|                                      |      |                       |                   | in mm1 depending on the corresponding          
|                                      |      |                       |                   | sign in mm2/m64.                               
| 66 0F 38 08 /r PSIGNB xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Negate/zero/preserve packed byte integers      
|                                      |      |                       |                   | in xmm1 depending on the corresponding         
|                                      |      |                       |                   | sign in xmm2/m128.                             
| 0F 38 09 /r1 PSIGNW mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Negate/zero/preserve packed word integers      
|                                      |      |                       |                   | in mm1 depending on the corresponding          
|                                      |      |                       |                   | sign in mm2/m128.                              
| 66 0F 38 09 /r PSIGNW xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Negate/zero/preserve packed word integers      
|                                      |      |                       |                   | in xmm1 depending on the corresponding         
|                                      |      |                       |                   | sign in xmm2/m128.                             
| 0F 38 0A /r1 PSIGND mm1, mm2/m64     | RM   | V/V                   | SSSE3             | Negate/zero/preserve packed doubleword         
|                                      |      |                       |                   | integers in mm1 depending on the corresponding 
|                                      |      |                       |                   | sign in mm2/m128.                              
| 66 0F 38 0A /r PSIGND xmm1, xmm2/m128| RM   | V/V                   | SSSE3             | Negate/zero/preserve packed doubleword         
|                                      |      |                       |                   | integers in xmm1 depending on the corresponding
|                                      |      |                       |                   | sign in xmm2/m128.                             
| VEX.NDS.128.66.0F38.WIG 08 /r VPSIGNB| RVM  | V/V                   | AVX               | Negate/zero/preserve packed byte integers      
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 depending on the corresponding         
|                                      |      |                       |                   | sign in xmm3/m128.                             
| VEX.NDS.128.66.0F38.WIG 09 /r VPSIGNW| RVM  | V/V                   | AVX               | Negate/zero/preserve packed word integers      
| xmm1, xmm2, xmm3/m128                |      |                       |                   | in xmm2 depending on the corresponding         
|                                      |      |                       |                   | sign in xmm3/m128.                             
| VEX.NDS.128.66.0F38.WIG 0A /r VPSIGND| RVM  | V/V                   | AVX               | Negate/zero/preserve packed doubleword         
| xmm1, xmm2, xmm3/m128                |      |                       |                   | integers in xmm2 depending on the corresponding
|                                      |      |                       |                   | sign in xmm3/m128.                             
| VEX.NDS.256.66.0F38.WIG 08 /r VPSIGNB| RVM  | V/V                   | AVX2              | Negate packed byte integers in ymm2            
| ymm1, ymm2, ymm3/m256                |      |                       |                   | if the corresponding sign in ymm3/m256         
|                                      |      |                       |                   | is less than zero.                             
| VEX.NDS.256.66.0F38.WIG 09 /r VPSIGNW| RVM  | V/V                   | AVX2              | Negate packed 16-bit integers in ymm2          
| ymm1, ymm2, ymm3/m256                |      |                       |                   | if the corresponding sign in ymm3/m256         
|                                      |      |                       |                   | is less than zero.                             
| VEX.NDS.256.66.0F38.WIG 0A /r VPSIGND| RVM  | V/V                   | AVX2              | Negate packed doubleword integers in           
| ymm1, ymm2, ymm3/m256                |      |                       |                   | ymm2 if the corresponding sign in ymm3/m256    
|                                      |      |                       |                   | is less than zero.                             
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
(V)PSIGNB/(V)PSIGNW/(V)PSIGND negates each data element of the destination operand
(the first operand) if the signed integer value of the corresponding data element
in the source operand (the second operand) is less than zero. If the signed
integer value of a data element in the source operand is positive, the corresponding
data element in the destination operand is unchanged. If a data element in the
source operand is zero, the corresponding data element in the destination operand
is set to zero.

(V)PSIGNB operates on signed bytes. (V)PSIGNW operates on 16-bit signed words.
(V)PSIGND operates on signed 32-bit integers. When the source operand is a 128bit
memory operand, the operand must be aligned on a 16-byte boundary or a general-protection
exception (#GP) will be generated.

Legacy SSE instructions: Both operands can be MMX registers. In 64-bit mode,
use the REX prefix to access additional registers. 128-bit Legacy SSE version:
The first source and destination operands are XMM registers. The second source
operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The first source and destination operands are XMM registers. The second
source operand is an XMM register or a 128-bit memory location. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.L must be 0, otherwise instructions
will #UD. VEX.256 encoded version: The first source and destination operands
are YMM registers. The second source operand is an YMM register or a 256-bit
memory location.

Operation:

PSIGNB (with 64 bit operands)
  IF (SRC[7:0] < 0 )
     DEST[7:0] <- Neg(DEST[7:0])
  ELSEIF (SRC[7:0] = 0 )
     DEST[7:0] <- 0
  ELSEIF (SRC[7:0] > 0 )
     DEST[7:0] <- DEST[7:0]
  Repeat operation for 2nd through 7th bytes
  IF (SRC[63:56] < 0 )
     DEST[63:56] <- Neg(DEST[63:56])
  ELSEIF (SRC[63:56] = 0 )
     DEST[63:56] <- 0
  ELSEIF (SRC[63:56] > 0 )
     DEST[63:56] <- DEST[63:56]
PSIGNB (with 128 bit operands)
  IF (SRC[7:0] < 0 )
     DEST[7:0] <- Neg(DEST[7:0])
  ELSEIF (SRC[7:0] = 0 )
     DEST[7:0] <- 0
  ELSEIF (SRC[7:0] > 0 )
     DEST[7:0] <- DEST[7:0]
  Repeat operation for 2nd through 15th bytes
  IF (SRC[127:120] < 0 )
     DEST[127:120] <- Neg(DEST[127:120])
  ELSEIF (SRC[127:120] = 0 )
     DEST[127:120] <- 0
  ELSEIF (SRC[127:120] > 0 )
     DEST[127:120] <- DEST[127:120]
VPSIGNB (VEX.128 encoded version)
DEST[127:0] <-BYTE_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSIGNB (VEX.256 encoded version)
DEST[255:0] <-BYTE_SIGN_256b(SRC1, SRC2)
PSIGNW (with 64 bit operands)
  IF (SRC[15:0] < 0 )
     DEST[15:0] <- Neg(DEST[15:0])
  ELSEIF (SRC[15:0] = 0 )
     DEST[15:0] <- 0
  ELSEIF (SRC[15:0] > 0 )
     DEST[15:0] <- DEST[15:0]
Repeat operation for 2nd through 3rd words
  IF (SRC[63:48] < 0 )
     DEST[63:48] <- Neg(DEST[63:48])
  ELSEIF (SRC[63:48] = 0 )
     DEST[63:48] <- 0
  ELSEIF (SRC[63:48] > 0 )
     DEST[63:48] <- DEST[63:48]
PSIGNW (with 128 bit operands)
  IF (SRC[15:0] < 0 )
     DEST[15:0] <- Neg(DEST[15:0])
  ELSEIF (SRC[15:0] = 0 )
     DEST[15:0] <- 0
  ELSEIF (SRC[15:0] > 0 )
     DEST[15:0] <- DEST[15:0]
  Repeat operation for 2nd through 7th words
  IF (SRC[127:112] < 0 )
     DEST[127:112] <- Neg(DEST[127:112])
  ELSEIF (SRC[127:112] = 0 )
     DEST[127:112] <- 0
  ELSEIF (SRC[127:112] > 0 )
     DEST[127:112] <- DEST[127:112]
VPSIGNW (VEX.128 encoded version)
DEST[127:0] <-WORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSIGNW (VEX.256 encoded version)
DEST[255:0] <-WORD_SIGN(SRC1, SRC2)
PSIGND (with 64 bit operands)
  IF (SRC[31:0] < 0 )
     DEST[31:0] <- Neg(DEST[31:0])
  ELSEIF (SRC[31:0] = 0 )
     DEST[31:0] <- 0
  ELSEIF (SRC[31:0] > 0 )
     DEST[31:0] <- DEST[31:0]
  IF (SRC[63:32] < 0 )
     DEST[63:32] <- Neg(DEST[63:32])
  ELSEIF (SRC[63:32] = 0 )
     DEST[63:32] <- 0
  ELSEIF (SRC[63:32] > 0 )
     DEST[63:32] <- DEST[63:32]
PSIGND (with 128 bit operands)
  IF (SRC[31:0] < 0 )
     DEST[31:0] <- Neg(DEST[31:0])
  ELSEIF (SRC[31:0] = 0 )
     DEST[31:0] <- 0
  ELSEIF (SRC[31:0] > 0 )
     DEST[31:0] <- DEST[31:0]
  Repeat operation for 2nd through 3rd double words
  IF (SRC[127:96] < 0 )
     DEST[127:96] <- Neg(DEST[127:96])
  ELSEIF (SRC[127:96] = 0 )
     DEST[127:96] <- 0
  ELSEIF (SRC[127:96] > 0 )
     DEST[127:96] <- DEST[127:96]
VPSIGND (VEX.128 encoded version)
DEST[127:0] <-DWORD_SIGN(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSIGND (VEX.256 encoded version)
DEST[255:0] <-DWORD_SIGN(SRC1, SRC2)

Intel C/C++ Compiler Intrinsic Equivalent:
| PSIGNB:   | __m64 _mm_sign_pi8 (__m64 a, __m64 b)     
| (V)PSIGNB:| __m128i _mm_sign_epi8 (__m128i a, __m128i 
|           | b)                                        
| VPSIGNB:  | __m256i _mm256_sign_epi8 (__m256i a,      
|           | __m256i b)                                
| PSIGNW:   | __m64 _mm_sign_pi16 (__m64 a, __m64       
|           | b)                                        
| (V)PSIGNW:| __m128i _mm_sign_epi16 (__m128i a, __m128i
|           | b)                                        
| VPSIGNW:  | __m256i _mm256_sign_epi16 (__m256i a,     
|           | __m256i b)                                
| PSIGND:   | __m64 _mm_sign_pi32 (__m64 a, __m64       
|           | b)                                        
| (V)PSIGND:| __m128i _mm_sign_epi32 (__m128i a, __m128i
|           | b)                                        
| VPSIGND:  | __m256i _mm256_sign_epi32 (__m256i a,     
|           | __m256i b)                                

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSLLDQ
description:
PSLLDQ - Shift Double Quadword Left Logical:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 66 0F 73 /7 ib PSLLDQ xmm1, imm8      | MI   | V/V                   | SSE2              | Shift xmm1 left by imm8 bytes while     
|                                       |      |                       |                   | shifting in 0s.                         
| VEX.NDD.128.66.0F.WIG 73 /7 ib VPSLLDQ| VMI  | V/V                   | AVX               | Shift xmm2 left by imm8 bytes while     
| xmm1, xmm2, imm8                      |      |                       |                   | shifting in 0s and store result in xmm1.
| VEX.NDD.256.66.0F.WIG 73 /7 ib VPSLLDQ| VMI  | V/V                   | AVX2              | Shift ymm2 left by imm8 bytes while     
| ymm1, ymm2, imm8                      |      |                       |                   | shifting in 0s and store result in ymm1.

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       
| VMI  | VEX.vvvv (w)    | ModRM:r/m (r)| imm8     | NA       

Description:
Shifts the destination operand (first operand) to the left by the number of
bytes specified in the count operand (second operand). The empty low-order bytes
are cleared (set to all 0s). If the value specified by the count operand is
greater than 15, the destination operand is set to all 0s. The count operand
is an 8-bit immediate. 128-bit Legacy SSE version: The source and destination
operands are the same. Bits (VLMAX-1:128) of the corresponding YMM destination
register remain unchanged. VEX.128 encoded version: The source and destination
operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed. VEX.256 encoded version: The source operand is a YMM register. The
destination operand is a YMM register. The count operand applies to both the
low and high 128-bit lanes.

Note: VEX.vvvv encodes the destination register, and VEX.B + ModRM.r/m encodes
the source register. VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSLLDQ(128-bit Legacy SSE version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- DEST << (TEMP * 8)
DEST[VLMAX-1:128] (Unmodified)
VPSLLDQ (VEX.128 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- SRC << (TEMP * 8)
DEST[VLMAX-1:128] <- 0
VPSLLDQ (VEX.256 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP  16; FI
DEST[127:0] <- SRC[127:0] << (TEMP * 8)
DEST[255:128] <- SRC[255:128] << (TEMP * 8)

Intel C/C++ Compiler Intrinsic Equivalent:
| (V)PSLLDQ:| __m128i _mm_slli_si128 ( __m128i a,
|           | int imm)                           
| VPSLLDQ:  | __m256i _mm256_slli_si256 ( __m256i
|           | a, const int imm)                  

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 7; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSLLW
description:
PSLLW/PSLLD/PSLLQ - Shift Packed Data Left Logical:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 0F F1 /r1 PSLLW mm, mm/m64              | RM   | V/V                   | MMX               | Shift words in mm left mm/m64 while         
|                                         |      |                       |                   | shifting in 0s.                             
| 66 0F F1 /r PSLLW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift words in xmm1 left by xmm2/m128       
|                                         |      |                       |                   | while shifting in 0s.                       
| 0F 71 /6 ib PSLLW mm1, imm8             | MI   | V/V                   | MMX               | Shift words in mm left by imm8 while        
|                                         |      |                       |                   | shifting in 0s.                             
| 66 0F 71 /6 ib PSLLW xmm1, imm8         | MI   | V/V                   | SSE2              | Shift words in xmm1 left by imm8 while      
|                                         |      |                       |                   | shifting in 0s.                             
| 0F F2 /r1 PSLLD mm, mm/m64              | RM   | V/V                   | MMX               | Shift doublewords in mm left by mm/m64      
|                                         |      |                       |                   | while shifting in 0s.                       
| 66 0F F2 /r PSLLD xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift doublewords in xmm1 left by xmm2/m128 
|                                         |      |                       |                   | while shifting in 0s.                       
| 0F 72 /6 ib1 PSLLD mm, imm8             | MI   | V/V                   | MMX               | Shift doublewords in mm left by imm8        
|                                         |      |                       |                   | while shifting in 0s.                       
| 66 0F 72 /6 ib PSLLD xmm1, imm8         | MI   | V/V                   | SSE2              | Shift doublewords in xmm1 left by imm8      
|                                         |      |                       |                   | while shifting in 0s.                       
| 0F F3 /r1 PSLLQ mm, mm/m64              | RM   | V/V                   | MMX               | Shift quadword in mm left by mm/m64         
|                                         |      |                       |                   | while shifting in 0s.                       
| 66 0F F3 /r PSLLQ xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift quadwords in xmm1 left by xmm2/m128   
|                                         |      |                       |                   | while shifting in 0s.                       
| 0F 73 /6 ib1 PSLLQ mm, imm8             | MI   | V/V                   | MMX               | Shift quadword in mm left by imm8 while     
|                                         |      |                       |                   | shifting in 0s.                             
| 66 0F 73 /6 ib PSLLQ xmm1, imm8         | MI   | V/V                   | SSE2              | Shift quadwords in xmm1 left by imm8        
|                                         |      |                       |                   | while shifting in 0s.                       
| VEX.NDS.128.66.0F.WIG F1 /r VPSLLW xmm1,| RVM  | V/V                   | AVX               | Shift words in xmm2 left by amount specified
| xmm2, xmm3/m128                         |      |                       |                   | in xmm3/m128 while shifting in 0s.          
| VEX.NDD.128.66.0F.WIG 71 /6 ib VPSLLW   | VMI  | V/V                   | AVX               | Shift words in xmm2 left by imm8 while      
| xmm1, xmm2, imm8                        |      |                       |                   | shifting in 0s.                             
| VEX.NDS.128.66.0F.WIG F2 /r VPSLLD xmm1,| RVM  | V/V                   | AVX               | Shift doublewords in xmm2 left by amount    
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting       
|                                         |      |                       |                   | in 0s.                                      
| VEX.NDD.128.66.0F.WIG 72 /6 ib VPSLLD   | VMI  | V/V                   | AVX               | Shift doublewords in xmm2 left by imm8      
| xmm1, xmm2, imm8                        |      |                       |                   | while shifting in 0s.                       
| VEX.NDS.128.66.0F.WIG F3 /r VPSLLQ xmm1,| RVM  | V/V                   | AVX               | Shift quadwords in xmm2 left by amount      
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting       
|                                         |      |                       |                   | in 0s.                                      
| VEX.NDD.128.66.0F.WIG 73 /6 ib VPSLLQ   | VMI  | V/V                   | AVX               | Shift quadwords in xmm2 left by imm8        
| xmm1, xmm2, imm8                        |      |                       |                   | while shifting in 0s.                       
| VEX.NDS.256.66.0F.WIG F1 /r VPSLLW ymm1,| RVM  | V/V                   | AVX2              | Shift words in ymm2 left by amount specified
| ymm2, xmm3/m128                         |      |                       |                   | in xmm3/m128 while shifting in 0s.          
| VEX.NDD.256.66.0F.WIG 71 /6 ib VPSLLW   | VMI  | V/V                   | AVX2              | Shift words in ymm2 left by imm8 while      
| ymm1, ymm2, imm8                        |      |                       |                   | shifting in 0s.                             
| VEX.NDS.256.66.0F.WIG F2 /r VPSLLD ymm1,| RVM  | V/V                   | AVX2              | Shift doublewords in ymm2 left by amount    
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting       
|                                         |      |                       |                   | in 0s.                                      
| VEX.NDD.256.66.0F.WIG 72 /6 ib VPSLLD   | VMI  | V/V                   | AVX2              | Shift doublewords in ymm2 left by imm8      
| ymm1, ymm2, imm8                        |      |                       |                   | while shifting in 0s.                       
| VEX.NDS.256.66.0F.WIG F3 /r VPSLLQ ymm1,| RVM  | V/V                   | AVX2              | Shift quadwords in ymm2 left by amount      
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting       
|                                         |      |                       |                   | in 0s.                                      
| VEX.NDD.256.66.0F.WIG 73 /6 ib VPSLLQ   | VMI  | V/V                   | AVX2              | Shift quadwords in ymm2 left by imm8        
| ymm1, ymm2, imm8                        |      |                       |                   | while shifting in 0s.                       
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       
| VMI  | VEX.vvvv (w)    | ModRM:r/m (r)| imm8         | NA       

Description:
Shifts the bits in the individual data elements (words, doublewords, or quadword)
in the destination operand (first operand) to the left by the number of bits
specified in the count operand (second operand). As the bits in the data elements
are shifted left, the empty low-order bits are cleared (set to 0). If the value
specified by the count operand is greater than 15 (for words), 31 (for doublewords),
or 63 (for a quadword), then the destination operand is set to all 0s. Figure
4-13 gives an example of shifting words in a 64-bit operand.

Pre-Shift

| X3 PSLLW, PSLLD, and PSLLQ Instruction| X2 X2 << COUNT| X1 X1 << COUNT| X0 DEST Shift Left with Zero Extension
| Operation Using 64-bit Operand        |               |               | X0 << COUNT DEST Figure 4-13.         
The (V)PSLLW instruction shifts each of the words in the destination operand
to the left by the number of bits specified in the count operand; the (V)PSLLD
instruction shifts each of the doublewords in the destination operand; and the
(V)PSLLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The destination operand is an MMX technology register;
the count operand can be either an MMX technology register or an 64-bit memory
location. 128-bit Legacy SSE version: The destination and first source operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. The count operand can be either an XMM register or a 128-bit
memory location or an 8-bit immediate. If the count operand is a memory address,
128 bits are loaded but the upper 64 bits are ignored.

VEX.128 encoded version: The destination and first source operands are XMM registers.
Bits (VLMAX-1:128) of the destination YMM register are zeroed. The count operand
can be either an XMM register or a 128-bit memory location or an 8-bit immediate.
If the count operand is a memory address, 128 bits are loaded but the upper
64 bits are ignored. VEX.256 encoded version: The destination and first source
operands are YMM registers. The count operand can be either an XMM register
or a 128-bit memory location or an 8-bit immediate.

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /6), VEX.vvvv
encodes the destination register, and VEX.B + ModRM.r/m encodes the source register.
VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSLLW (with 64-bit operand)
  IF (COUNT > 15)
  THEN
     DEST[64:0] <- 0000000000000000H;
  ELSE
     DEST[15:0] <- ZeroExtend(DEST[15:0] << COUNT);
     (* Repeat shift operation for 2nd and 3rd words *)
     DEST[63:48] <- ZeroExtend(DEST[63:48] << COUNT);
  FI;
PSLLD (with 64-bit operand)
  IF (COUNT > 31)
  THEN
     DEST[64:0] <- 0000000000000000H;
  ELSE
     DEST[31:0] <- ZeroExtend(DEST[31:0] << COUNT);
     DEST[63:32] <- ZeroExtend(DEST[63:32] << COUNT);
  FI;
PSLLQ (with 64-bit operand)
  IF (COUNT > 63)
  THEN
     DEST[64:0] <- 0000000000000000H;
  ELSE
     DEST <- ZeroExtend(DEST << COUNT);
  FI;
PSLLW (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 15)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H;
  ELSE
     DEST[15:0]
     (* Repeat shift operation for 2nd through 7th words *)
     DEST[127:112] <- ZeroExtend(DEST[127:112] << COUNT);
  FI;
PSLLD (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 31)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H;
  ELSE
     DEST[31:0]
     (* Repeat shift operation for 2nd and 3rd doublewords *)
     DEST[127:96] <- ZeroExtend(DEST[127:96] << COUNT);
  FI;
PSLLQ (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 63)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H;
  ELSE
     DEST[63:0]
     DEST[127:64] <- ZeroExtend(DEST[127:64] << COUNT);
  FI;
PSLLW (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSLLW (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSLLD (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSLLD (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSLLD (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSLLD (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSLLQ (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSLLQ (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSLLQ (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSLLQ (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_QWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSLLW (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSLLW (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSLLW (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSLLW (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSLLD (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSLLD (xmm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
VPSLLW (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORDS_256b(SRC1, SRC2)
VPSLLW (ymm, imm8)
DEST[255:0] <- LOGICAL_LEFT_SHIFT_WORD_256bS(SRC1, imm8)
VPSLLD (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, SRC2)
VPSLLD (ymm, imm8)
DEST[127:0] <- LOGICAL_LEFT_SHIFT_DWORDS_256b(SRC1, imm8)
VPSLLQ (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, SRC2)
VPSLLQ (ymm, imm8)
DEST[255:0] <- LOGICAL_LEFT_SHIFT_QWORDS_256b(SRC1, imm8)

Intel C/C++ Compiler Intrinsic Equivalents:
| PSLLW:   | __m64 _mm_slli_pi16 (__m64 m, int count) 
| PSLLW:   | __m64 _mm_sll_pi16(__m64 m, __m64 count) 
| (V)PSLLW:| __m128i _mm_slli_pi16(__m64 m, int count)
| (V)PSLLW:| __m128i _mm_slli_pi16(__m128i m, __m128i 
|          | count)                                   
| VPSLLW:  | __m256i _mm256_slli_epi16 (__m256i m,    
|          | int count)                               
| VPSLLW:  | __m256i _mm256_sll_epi16 (__m256i m,     
|          | __m128i count)                           
| PSLLD:   | count)                                   
| PSLLD:   | __m64 _mm_sll_pi32(__m64 m, __m64 count) 
| (V)PSLLD:| count)                                   
| (V)PSLLD:| __m128i _mm_sll_epi32(__m128i m, __m128i 
|          | count)                                   
| VPSLLD:  | __m256i _mm256_slli_epi32 (__m256i m,    
|          | int count)                               
| VPSLLD:  | __m256i _mm256_sll_epi32 (__m256i m,     
|          | __m128i count)                           
| PSLLQ:   | count)                                   
| PSLLQ:   | __m64 _mm_sll_si64(__m64 m, __m64 count) 
| (V)PSLLQ:| count)                                   
| (V)PSLLQ:| __m128i _mm_sll_epi64(__m128i m, __m128i 
|          | count)                                   
| VPSLLQ:  | __m256i _mm256_slli_epi64 (__m256i m,    
|          | int count)                               
| VPSLLQ:  | __m256i _mm256_sll_epi64 (__m256i m,     
|          | __m128i count)                           

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSRAW
description:
PSRAW/PSRAD - Shift Packed Data Right Arithmetic:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                              
| 0F E1 /r1 PSRAW mm, mm/m64              | RM   | V/V                   | MMX               | Shift words in mm right by mm/m64 while  
|                                         |      |                       |                   | shifting in sign bits.                   
| 66 0F E1 /r PSRAW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift words in xmm1 right by xmm2/m128   
|                                         |      |                       |                   | while shifting in sign bits.             
| 0F 71 /4 ib1 PSRAW mm, imm8             | MI   | V/V                   | MMX               | Shift words in mm right by imm8 while    
|                                         |      |                       |                   | shifting in sign bits                    
| 66 0F 71 /4 ib PSRAW xmm1, imm8         | MI   | V/V                   | SSE2              | Shift words in xmm1 right by imm8 while  
|                                         |      |                       |                   | shifting in sign bits                    
| 0F E2 /r1 PSRAD mm, mm/m64              | RM   | V/V                   | MMX               | Shift doublewords in mm right by mm/m64  
|                                         |      |                       |                   | while shifting in sign bits.             
| 66 0F E2 /r PSRAD xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift doubleword in xmm1 right by xmm2   
|                                         |      |                       |                   | /m128 while shifting in sign bits.       
| 0F 72 /4 ib1 PSRAD mm, imm8             | MI   | V/V                   | MMX               | Shift doublewords in mm right by imm8    
|                                         |      |                       |                   | while shifting in sign bits.             
| 66 0F 72 /4 ib PSRAD xmm1, imm8         | MI   | V/V                   | SSE2              | Shift doublewords in xmm1 right by imm8  
|                                         |      |                       |                   | while shifting in sign bits.             
| VEX.NDS.128.66.0F.WIG E1 /r VPSRAW xmm1,| RVM  | V/V                   | AVX               | Shift words in xmm2 right by amount      
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting    
|                                         |      |                       |                   | in sign bits.                            
| VEX.NDD.128.66.0F.WIG 71 /4 ib VPSRAW   | VMI  | V/V                   | AVX               | Shift words in xmm2 right by imm8 while  
| xmm1, xmm2, imm8                        |      |                       |                   | shifting in sign bits.                   
| VEX.NDS.128.66.0F.WIG E2 /r VPSRAD xmm1,| RVM  | V/V                   | AVX               | Shift doublewords in xmm2 right by amount
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting    
|                                         |      |                       |                   | in sign bits.                            
| VEX.NDD.128.66.0F.WIG 72 /4 ib VPSRAD   | VMI  | V/V                   | AVX               | Shift doublewords in xmm2 right by imm8  
| xmm1, xmm2, imm8                        |      |                       |                   | while shifting in sign bits.             
| VEX.NDS.256.66.0F.WIG E1 /r VPSRAW ymm1,| RVM  | V/V                   | AVX2              | Shift words in ymm2 right by amount      
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting    
|                                         |      |                       |                   | in sign bits.                            
| VEX.NDD.256.66.0F.WIG 71 /4 ib VPSRAW   | VMI  | V/V                   | AVX2              | Shift words in ymm2 right by imm8 while  
| ymm1, ymm2, imm8                        |      |                       |                   | shifting in sign bits.                   
| VEX.NDS.256.66.0F.WIG E2 /r VPSRAD ymm1,| RVM  | V/V                   | AVX2              | Shift doublewords in ymm2 right by amount
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting    
|                                         |      |                       |                   | in sign bits.                            
| VEX.NDD.256.66.0F.WIG 72 /4 ib VPSRAD   | VMI  | V/V                   | AVX2              | Shift doublewords in ymm2 right by imm8  
| ymm1, ymm2, imm8                        |      |                       |                   | while shifting in sign bits.             
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       
| VMI  | VEX.vvvv (w)    | ModRM:r/m (r)| imm8         | NA       

Description:
Shifts the bits in the individual data elements (words or doublewords) in the
destination operand (first operand) to the right by the number of bits specified
in the count operand (second operand). As the bits in the data elements are
shifted right, the empty high-order bits are filled with the initial value of
the sign bit of the data element. If the value specified by the count operand
is greater than 15 (for words) or 31 (for doublewords), each destination data
element is filled with the initial value of the sign bit of the element. (Figure
4-14 gives an example of shifting words in a 64-bit operand.)

Pre-Shift

| X3 PSRAW and PSRAD Instruction Operation| X2 X2 >> COUNT| X1 X1 >> COUNT| X0 DEST Shift Right with Sign Extension
| Using a 64-bit Operand                  |               |               | X0 >> COUNT DEST Figure 4-14.          
Note that only the first 64-bits of a 128-bit count operand are checked to compute
the count. If the second source operand is a memory address, 128 bits are loaded.

The (V)PSRAW instruction shifts each of the words in the destination operand
to the right by the number of bits specified in the count operand, and the (V)PSRAD
instruction shifts each of the doublewords in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The destination operand is an MMX technology register;
the count operand can be either an MMX technology register or an 64-bit memory
location. 128-bit Legacy SSE version: The destination and first source operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. The count operand can be either an XMM register or a 128-bit
memory location or an 8-bit immediate. If the count operand is a memory address,
128 bits are loaded but the upper 64 bits are ignored. VEX.128 encoded version:
The destination and first source operands are XMM registers. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. The count operand can be either
an XMM register or a 128-bit memory location or an 8-bit immediate. If the count
operand is a memory address, 128 bits are loaded but the upper 64 bits are ignored.
VEX.256 encoded version: The destination and first source operands are YMM registers.
The count operand can be either an XMM register or a 128-bit memory location
or an 8-bit immediate.

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /4), VEX.vvvv
encodes the destination register, and VEX.B + ModRM.r/m encodes the source register.
VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSRAW (with 64-bit operand)
  IF (COUNT > 15)
     THEN COUNT <- 16;
  FI;
  DEST[15:0] <- SignExtend(DEST[15:0] >> COUNT);
  (* Repeat shift operation for 2nd and 3rd words *)
  DEST[63:48] <- SignExtend(DEST[63:48] >> COUNT);
PSRAD (with 64-bit operand)
  IF (COUNT > 31)
     THEN COUNT <- 32;
  FI;
  DEST[31:0] <- SignExtend(DEST[31:0] >> COUNT);
  DEST[63:32] <- SignExtend(DEST[63:32] >> COUNT);
PSRAW (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 15)
     THEN COUNT <- 16;
  FI;
  DEST[15:0]
  (* Repeat shift operation for 2nd through 7th words *)
  DEST[127:112] <- SignExtend(DEST[127:112] >> COUNT);
PSRAD (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 31)
     THEN COUNT <- 32;
  FI;
  DEST[31:0]
  (* Repeat shift operation for 2nd and 3rd doublewords *)
  DEST[127:96] <- SignExtend(DEST[127:96] >>COUNT);
PSRAW (xmm, xmm, xmm/m128)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSRAW (xmm, imm8)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSRAW (xmm, xmm, xmm/m128)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSRAW (xmm, imm8)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSRAD (xmm, xmm, xmm/m128)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSRAD (xmm, imm8)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSRAD (xmm, xmm, xmm/m128)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSRAD (xmm, imm8)
DEST[127:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
VPSRAW (ymm, ymm, xmm/m128)
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
VPSRAW (ymm, imm8)
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
VPSRAD (ymm, ymm, xmm/m128)
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
VPSRAD (ymm, imm8)
DEST[255:0] <- ARITHMETIC_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)

Intel C/C++ Compiler Intrinsic Equivalents:
| PSRAW:   | __m64 _mm_srai_pi16 (__m64 m, int count) 
| PSRAW:   | __m64 _mm_sra_pi16 (__m64 m, __m64 count)
| (V)PSRAW:| count)                                   
| (V)PSRAW:| __m128i _mm_sra_epi16(__m128i m, __m128i 
|          | count)                                   
| VPSRAW:  | __m256i _mm256_srai_epi16 (__m256i m,    
|          | int count)                               
| VPSRAW:  | __m256i _mm256_sra_epi16 (__m256i m,     
|          | __m128i count)                           
| PSRAD:   | __m64 _mm_srai_pi32 (__m64 m, int count) 
| PSRAD:   | __m64 _mm_sra_pi32 (__m64 m, __m64 count)
| (V)PSRAD:| count)                                   
| (V)PSRAD:| __m128i _mm_sra_epi32 (__m128i m, __m128i
|          | count)                                   
| VPSRAD:  | __m256i _mm256_srai_epi32 (__m256i m,    
|          | int count)                               
| VPSRAD:  | __m256i _mm256_sra_epi32 (__m256i m,     
|          | __m128i count)                           

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSRLDQ
description:
PSRLDQ - Shift Double Quadword Right Logical:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 66 0F 73 /3 ib PSRLDQ xmm1, imm8      | MI   | V/V                   | SSE2              | Shift xmm1 right by imm8 while shifting
|                                       |      |                       |                   | in 0s.                                 
| VEX.NDD.128.66.0F.WIG 73 /3 ib VPSRLDQ| VMI  | V/V                   | AVX               | Shift xmm2 right by imm8 bytes while   
| xmm1, xmm2, imm8                      |      |                       |                   | shifting in 0s.                        
| VEX.NDD.256.66.0F.WIG 73 /3 ib VPSRLDQ| VMI  | V/V                   | AVX2              | Shift ymm1 right by imm8 bytes while   
| ymm1, ymm2, imm8                      |      |                       |                   | shifting in 0s.                        

Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3| Operand 4
| MI   | ModRM:r/m (r, w)| imm8         | NA       | NA       
| VMI  | VEX.vvvv (w)    | ModRM:r/m (r)| imm8     | NA       

Description:
Shifts the destination operand (first operand) to the right by the number of
bytes specified in the count operand (second operand). The empty high-order
bytes are cleared (set to all 0s). If the value specified by the count operand
is greater than 15, the destination operand is set to all 0s. The count operand
is an 8-bit immediate.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
source and destination operands are the same. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The source
and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination
YMM register are zeroed. VEX.256 encoded version: The source operand is a YMM
register. The destination operand is a YMM register. The count operand applies
to both the low and high 128-bit lanes.

Note: VEX.vvvv encodes the destination register, and VEX.B + ModRM.r/m encodes
the source register. VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSRLDQ(128-bit Legacy SSE version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- DEST >> (TEMP * 8)
DEST[VLMAX-1:128] (Unmodified)
VPSRLDQ (VEX.128 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- SRC >> (TEMP * 8)
DEST[VLMAX-1:128] <- 0
VPSRLDQ (VEX.256 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST[127:0] <- SRC[127:0] >> (TEMP * 8)
DEST[255:128] <- SRC[255:128] >> (TEMP * 8)

Intel C/C++ Compiler Intrinsic Equivalents:
| (V)PSRLDQ:| __m128i _mm_srli_si128 ( __m128i a,
|           | int imm)                           
| VPSRLDQ:  | __m256i _mm256_srli_si256 ( __m256i
|           | a, const int imm)                  

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 7; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSRLW
description:
PSRLW/PSRLD/PSRLQ - Shift Packed Data Right Logical:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F D1 /r1 PSRLW mm, mm/m64              | RM   | V/V                   | MMX               | Shift words in mm right by amount specified
|                                         |      |                       |                   | in mm/m64 while shifting in 0s.            
| 66 0F D1 /r PSRLW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift words in xmm1 right by amount        
|                                         |      |                       |                   | specified in xmm2/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| 0F 71 /2 ib1 PSRLW mm, imm8             | MI   | V/V                   | MMX               | Shift words in mm right by imm8 while      
|                                         |      |                       |                   | shifting in 0s.                            
| 66 0F 71 /2 ib PSRLW xmm1, imm8         | MI   | V/V                   | SSE2              | Shift words in xmm1 right by imm8 while    
|                                         |      |                       |                   | shifting in 0s.                            
| 0F D2 /r1 PSRLD mm, mm/m64              | RM   | V/V                   | MMX               | Shift doublewords in mm right by amount    
|                                         |      |                       |                   | specified in mm/m64 while shifting in      
|                                         |      |                       |                   | 0s.                                        
| 66 0F D2 /r PSRLD xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift doublewords in xmm1 right by amount  
|                                         |      |                       |                   | specified in xmm2 /m128 while shifting     
|                                         |      |                       |                   | in 0s.                                     
| 0F 72 /2 ib1 PSRLD mm, imm8             | MI   | V/V                   | MMX               | Shift doublewords in mm right by imm8      
|                                         |      |                       |                   | while shifting in 0s.                      
| 66 0F 72 /2 ib PSRLD xmm1, imm8         | MI   | V/V                   | SSE2              | Shift doublewords in xmm1 right by imm8    
|                                         |      |                       |                   | while shifting in 0s.                      
| 0F D3 /r1 PSRLQ mm, mm/m64              | RM   | V/V                   | MMX               | Shift mm right by amount specified in      
|                                         |      |                       |                   | mm/m64 while shifting in 0s.               
| 66 0F D3 /r PSRLQ xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Shift quadwords in xmm1 right by amount    
|                                         |      |                       |                   | specified in xmm2/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| 0F 73 /2 ib1 PSRLQ mm, imm8             | MI   | V/V                   | MMX               | Shift mm right by imm8 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| 66 0F 73 /2 ib PSRLQ xmm1, imm8         | MI   | V/V                   | SSE2              | Shift quadwords in xmm1 right by imm8      
|                                         |      |                       |                   | while shifting in 0s.                      
| VEX.NDS.128.66.0F.WIG D1 /r VPSRLW xmm1,| RVM  | V/V                   | AVX               | Shift words in xmm2 right by amount        
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.128.66.0F.WIG 71 /2 ib VPSRLW   | VMI  | V/V                   | AVX               | Shift words in xmm2 right by imm8 while    
| xmm1, xmm2, imm8                        |      |                       |                   | shifting in 0s.                            
| VEX.NDS.128.66.0F.WIG D2 /r VPSRLD xmm1,| RVM  | V/V                   | AVX               | Shift doublewords in xmm2 right by amount  
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.128.66.0F.WIG 72 /2 ib VPSRLD   | VMI  | V/V                   | AVX               | Shift doublewords in xmm2 right by imm8    
| xmm1, xmm2, imm8                        |      |                       |                   | while shifting in 0s.                      
| VEX.NDS.128.66.0F.WIG D3 /r VPSRLQ xmm1,| RVM  | V/V                   | AVX               | Shift quadwords in xmm2 right by amount    
| xmm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.128.66.0F.WIG 73 /2 ib VPSRLQ   | VMI  | V/V                   | AVX               | Shift quadwords in xmm2 right by imm8      
| xmm1, xmm2, imm8                        |      |                       |                   | while shifting in 0s.                      
| VEX.NDS.256.66.0F.WIG D1 /r VPSRLW ymm1,| RVM  | V/V                   | AVX2              | Shift words in ymm2 right by amount        
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.256.66.0F.WIG 71 /2 ib VPSRLW   | VMI  | V/V                   | AVX2              | Shift words in ymm2 right by imm8 while    
| ymm1, ymm2, imm8                        |      |                       |                   | shifting in 0s.                            
| VEX.NDS.256.66.0F.WIG D2 /r VPSRLD ymm1,| RVM  | V/V                   | AVX2              | Shift doublewords in ymm2 right by amount  
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.256.66.0F.WIG 72 /2 ib VPSRLD   | VMI  | V/V                   | AVX2              | Shift doublewords in ymm2 right by imm8    
| ymm1, ymm2, imm8                        |      |                       |                   | while shifting in 0s.                      
| VEX.NDS.256.66.0F.WIG D3 /r VPSRLQ ymm1,| RVM  | V/V                   | AVX2              | Shift quadwords in ymm2 right by amount    
| ymm2, xmm3/m128                         |      |                       |                   | specified in xmm3/m128 while shifting      
|                                         |      |                       |                   | in 0s.                                     
| VEX.NDD.256.66.0F.WIG 73 /2 ib VPSRLQ   | VMI  | V/V                   | AVX2              | Shift quadwords in ymm2 right by imm8      
| ymm1, ymm2, imm8                        |      |                       |                   | while shifting in 0s.                      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| MI   | ModRM:r/m (r, w)| imm8         | NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       
| VMI  | VEX.vvvv (w)    | ModRM:r/m (r)| imm8         | NA       

Description:
Shifts the bits in the individual data elements (words, doublewords, or quadword)
in the destination operand (first operand) to the right by the number of bits
specified in the count operand (second operand). As the bits in the data elements
are shifted right, the empty high-order bits are cleared (set to 0). If the
value specified by the count operand is greater than 15 (for words), 31 (for
doublewords), or 63 (for a quadword), then the destination operand is set to
all 0s. Figure 4-15 gives an example of shifting words in a 64-bit operand.

Note that only the first 64-bits of a 128-bit count operand are checked to compute
the count.

Pre-Shift

| X3 PSRLW, PSRLD, and PSRLQ Instruction| X2 X2 >> COUNT| X1 X1 >> COUNT| X0 DEST Shift Right with Zero Extension
| Operation Using 64-bit Operand        |               |               | X0 >> COUNT DEST Figure 4-15.          
The (V)PSRLW instruction shifts each of the words in the destination operand
to the right by the number of bits specified in the count operand; the (V)PSRLD
instruction shifts each of the doublewords in the destination operand; and the
PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The destination operand is an MMX technology register;
the count operand can be either an MMX technology register or an 64-bit memory
location. 128-bit Legacy SSE version: The destination operand is an XMM register;
the count operand can be either an XMM register or a 128-bit memory location,
or an 8-bit immediate. If the count operand is a memory address, 128 bits

are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding
YMM destination register remain unchanged. VEX.128 encoded version: The destination
operand is an XMM register; the count operand can be either an XMM register
or a 128-bit memory location, or an 8-bit immediate. If the count operand is
a memory address, 128 bits are loaded but the upper 64 bits are ignored. Bits
(VLMAX-1:128) of the destination YMM register are zeroed.

VEX.256 encoded version: The destination and first source operands are YMM registers.
The count operand can be either an YMM register or a 128-bit memory location
or an 8-bit immediate.

Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2), VEX.vvvv
encodes the destination register, and VEX.B + ModRM.r/m encodes the source register.
VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSRLW (with 64-bit operand)
  IF (COUNT > 15)
  THEN
     DEST[64:0] <- 0000000000000000H
  ELSE
     DEST[15:0] <- ZeroExtend(DEST[15:0] >> COUNT);
     (* Repeat shift operation for 2nd and 3rd words *)
     DEST[63:48] <- ZeroExtend(DEST[63:48] >> COUNT);
  FI;
PSRLD (with 64-bit operand)
  IF (COUNT > 31)
  THEN
     DEST[64:0] <- 0000000000000000H
  ELSE
     DEST[31:0] <- ZeroExtend(DEST[31:0] >> COUNT);
     DEST[63:32] <- ZeroExtend(DEST[63:32] >> COUNT);
  FI;
PSRLQ (with 64-bit operand)
  IF (COUNT > 63)
  THEN
     DEST[64:0] <- 0000000000000000H
  ELSE
     DEST <- ZeroExtend(DEST >> COUNT);
  FI;
PSRLW (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 15)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H
  ELSE
     DEST[15:0]
     (* Repeat shift operation for 2nd through 7th words *)
     DEST[127:112] <- ZeroExtend(DEST[127:112] >> COUNT);
  FI;
PSRLD (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 31)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H
  ELSE
     DEST[31:0]
     (* Repeat shift operation for 2nd and 3rd doublewords *)
     DEST[127:96] <- ZeroExtend(DEST[127:96] >> COUNT);
  FI;
PSRLQ (with 128-bit operand)
  COUNT <- COUNT_SOURCE[63:0];
  IF (COUNT > 15)
  THEN
     DEST[128:0] <- 00000000000000000000000000000000H
  ELSE
     DEST[63:0]
     DEST[127:64] <- ZeroExtend(DEST[127:64] >> COUNT);
  FI;
PSRLW (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSRLW (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSRLW (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSRLW (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSRLD (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSRLD (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSRLD (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSRLD (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
PSRLQ (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
PSRLQ (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)
DEST[VLMAX-1:128] (Unmodified)
VPSRLQ (xmm, xmm, xmm/m128)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPSRLQ (xmm, imm8)
DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)
DEST[VLMAX-1:128] <- 0
VPSRLW (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
VPSRLW (ymm, imm8)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
VPSRLD (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
VPSRLD (ymm, imm8)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
VPSRLQ (ymm, ymm, xmm/m128)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)
VPSRLQ (ymm, imm8)
DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)

Intel C/C++ Compiler Intrinsic Equivalents:
| PSRLW: PSRLW: (V)PSRLW: (V)PSRLW: VPSRLW:| __m64 _mm_srli_pi16(__m64 m, int __m64         | count)
| VPSRLW:                                  | _mm_srl_pi16 (__m64 m, __m64 count)            |       
|                                          | __m128i _mm_srli_epi16 (__m128i m, int         |       
|                                          | count) __m128i _mm_srl_epi16 (__m128i          |       
|                                          | m, __m128i count) __m256i _mm256_srli_epi16    |       
|                                          | (__m256i m, int count) __m256i _mm256_srl_epi16|       
|                                          | (__m256i m, __m128i count)                     |       
| PSRLD: PSRLD:                            | __m64 _mm_srli_pi32 (__m64 m, int __m64        | count)
|                                          | _mm_srl_pi32 (__m64 m, __m64 count)            |       
| (V)PSRLD: (V)PSRLD: VPSRLD: VPSRLD:      | __m128i _mm_srli_epi32 (__m128i m, int         | count)
|                                          | __m128i _mm_srl_epi32 (__m128i m, __m128i      |       
|                                          | count) __m256i _mm256_srli_epi32 (__m256i      |       
|                                          | m, int count) __m256i _mm256_srl_epi32         |       
|                                          | (__m256i m, __m128i count)                     |       
| PSRLQ: PSRLQ:                            | __m64 _mm_srli_si64 (__m64 m, int __m64        | count)
|                                          | _mm_srl_si64 (__m64 m, __m64 count)            |       
| (V)PSRLQ: (V)PSRLQ: VPSRLQ: VPSRLQ:      | __m128i _mm_srli_epi64 (__m128i m, int         | count)
|                                          | __m128i _mm_srl_epi64 (__m128i m, __m128i      |       
|                                          | count) __m256i _mm256_srli_epi64 (__m256i      |       
|                                          | m, int count) __m256i _mm256_srl_epi64         |       
|                                          | (__m256i m, __m128i count)                     |       

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4 and 7 for non-VEX-encoded instructions; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSUBB
description:
PSUBB/PSUBW/PSUBD - Subtract Packed Integers:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                               
| 0F F8 /r1 PSUBB mm, mm/m64              | RM   | V/V                   | MMX               | Subtract packed byte integers in mm/m64   
|                                         |      |                       |                   | from packed byte integers in mm.          
| 66 0F F8 /r PSUBB xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Subtract packed byte integers in xmm2/m128
|                                         |      |                       |                   | from packed byte integers in xmm1.        
| 0F F9 /r1 PSUBW mm, mm/m64              | RM   | V/V                   | MMX               | Subtract packed word integers in mm/m64   
|                                         |      |                       |                   | from packed word integers in mm.          
| 66 0F F9 /r PSUBW xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Subtract packed word integers in xmm2/m128
|                                         |      |                       |                   | from packed word integers in xmm1.        
| 0F FA /r1 PSUBD mm, mm/m64              | RM   | V/V                   | MMX               | Subtract packed doubleword integers       
|                                         |      |                       |                   | in mm/m64 from packed doubleword integers 
|                                         |      |                       |                   | in mm.                                    
| 66 0F FA /r PSUBD xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Subtract packed doubleword integers       
|                                         |      |                       |                   | in xmm2/mem128 from packed doubleword     
|                                         |      |                       |                   | integers in xmm1.                         
| VEX.NDS.128.66.0F.WIG F8 /r VPSUBB xmm1,| RVM  | V/V                   | AVX               | Subtract packed byte integers in xmm3/m128
| xmm2, xmm3/m128                         |      |                       |                   | from xmm2.                                
| VEX.NDS.128.66.0F.WIG F9 /r VPSUBW xmm1,| RVM  | V/V                   | AVX               | Subtract packed word integers in xmm3/m128
| xmm2, xmm3/m128                         |      |                       |                   | from xmm2.                                
| VEX.NDS.128.66.0F.WIG FA /r VPSUBD xmm1,| RVM  | V/V                   | AVX               | Subtract packed doubleword integers       
| xmm2, xmm3/m128                         |      |                       |                   | in xmm3/m128 from xmm2.                   
| VEX.NDS.256.66.0F.WIG F8 /r VPSUBB ymm1,| RVM  | V/V                   | AVX2              | Subtract packed byte integers in ymm3/m256
| ymm2, ymm3/m256                         |      |                       |                   | from ymm2.                                
| VEX.NDS.256.66.0F.WIG F9 /r VPSUBW ymm1,| RVM  | V/V                   | AVX2              | Subtract packed word integers in ymm3/m256
| ymm2, ymm3/m256                         |      |                       |                   | from ymm2.                                
| VEX.NDS.256.66.0F.WIG FA /r VPSUBD ymm1,| RVM  | V/V                   | AVX2              | Subtract packed doubleword integers       
| ymm2, ymm3/m256                         |      |                       |                   | in ymm3/m256 from ymm2.                   
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD subtract of the packed integers of the source operand (second
operand) from the packed integers of the destination operand (first operand),
and stores the packed integer results in the destination operand. See Figure
9-4 in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
1, for an illustration of a SIMD operation. Overflow is handled with wraparound,
as described in the following paragraphs.

The (V)PSUBB instruction subtracts packed byte integers. When an individual
result is too large or too small to be represented in a byte, the result is
wrapped around and the low 8 bits are written to the destination element.

The (V)PSUBW instruction subtracts packed word integers. When an individual
result is too large or too small to be represented in a word, the result is
wrapped around and the low 16 bits are written to the destination element.

The (V)PSUBD instruction subtracts packed doubleword integers. When an individual
result is too large or too small to be represented in a doubleword, the result
is wrapped around and the low 32 bits are written to the destination element.

Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either
unsigned or signed (two's complement notation) packed integers; however, it
does not set bits in the EFLAGS register to indicate overflow and/or a carry.
To prevent undetected overflow conditions, software must control the ranges
of values upon which it operates.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE version: When operating on 64-bit operands, the destination operand
must be an MMX technology register and the source operand can be either an MMX
technology register or a 64-bit memory location. 128-bit Legacy SSE version:
The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The second source operand is an XMM register or a 128-bit memory location.
The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The second
source operand is an YMM register or a 256-bit memory location. The first source
operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSUBB (with 64-bit operands)
  DEST[7:0] <- DEST[7:0] − SRC[7:0];
  (* Repeat subtract operation for 2nd through 7th byte *)
  DEST[63:56] <- DEST[63:56] − SRC[63:56];
PSUBB (with 128-bit operands)
  DEST[7:0] <- DEST[7:0] − SRC[7:0];
  (* Repeat subtract operation for 2nd through 14th byte *)
  DEST[127:120] <- DEST[111:120] − SRC[127:120];
VPSUBB (VEX.128 encoded version)
DEST[7:0] <- SRC1[7:0]-SRC2[7:0]
DEST[15:8] <- SRC1[15:8]-SRC2[15:8]
DEST[23:16] <- SRC1[23:16]-SRC2[23:16]
DEST[31:24] <- SRC1[31:24]-SRC2[31:24]
DEST[39:32] <- SRC1[39:32]-SRC2[39:32]
DEST[47:40] <- SRC1[47:40]-SRC2[47:40]
DEST[55:48] <- SRC1[55:48]-SRC2[55:48]
DEST[63:56] <- SRC1[63:56]-SRC2[63:56]
DEST[71:64] <- SRC1[71:64]-SRC2[71:64]
DEST[79:72] <- SRC1[79:72]-SRC2[79:72]
DEST[87:80] <- SRC1[87:80]-SRC2[87:80]
DEST[95:88] <- SRC1[95:88]-SRC2[95:88]
DEST[103:96] <- SRC1[103:96]-SRC2[103:96]
DEST[111:104] <- SRC1[111:104]-SRC2[111:104]
DEST[119:112] <- SRC1[119:112]-SRC2[119:112]
DEST[127:120] <- SRC1[127:120]-SRC2[127:120]
DEST[VLMAX-1:128] <- 00
VPSUBB (VEX.256 encoded version)
DEST[7:0] <- SRC1[7:0]-SRC2[7:0]
DEST[15:8] <- SRC1[15:8]-SRC2[15:8]
DEST[23:16] <- SRC1[23:16]-SRC2[23:16]
DEST[31:24] <- SRC1[31:24]-SRC2[31:24]
DEST[39:32] <- SRC1[39:32]-SRC2[39:32]
DEST[47:40] <- SRC1[47:40]-SRC2[47:40]
DEST[55:48] <- SRC1[55:48]-SRC2[55:48]
DEST[63:56] <- SRC1[63:56]-SRC2[63:56]
DEST[71:64] <- SRC1[71:64]-SRC2[71:64]
DEST[79:72] <- SRC1[79:72]-SRC2[79:72]
DEST[87:80] <- SRC1[87:80]-SRC2[87:80]
DEST[95:88] <- SRC1[95:88]-SRC2[95:88]
DEST[103:96] <- SRC1[103:96]-SRC2[103:96]
DEST[111:104] <- SRC1[111:104]-SRC2[111:104]
DEST[119:112] <- SRC1[119:112]-SRC2[119:112]
DEST[127:120] <- SRC1[127:120]-SRC2[127:120]
DEST[135:128] <- SRC1[135:128]-SRC2[135:128]
DEST[143:136] <- SRC1[143:136]-SRC2[143:136]
DEST[151:144] <- SRC1[151:144]-SRC2[151:144]
DEST[159:152] <- SRC1[159:152]-SRC2[159:152]
DEST[167:160] <- SRC1[167:160]-SRC2[167:160]
DEST[175:168] <- SRC1[175:168]-SRC2[175:168]
DEST[183:176] <- SRC1[183:176]-SRC2[183:176]
DEST[191:184] <- SRC1[191:184]-SRC2[191:184]
DEST[199:192] <- SRC1[199:192]-SRC2[199:192]
DEST[207:200] <- SRC1[207:200]-SRC2[207:200]
DEST[215:208] <- SRC1[215:208]-SRC2[215:208]
DEST[223:216] <- SRC1[223:216]-SRC2[223:216]
DEST[231:224] <- SRC1[231:224]-SRC2[231:224]
DEST[239:232] <- SRC1[239:232]-SRC2[239:232]
DEST[247:240] <- SRC1[247:240]-SRC2[247:240]
DEST[255:248] <- SRC1[255:248]-SRC2[255:248]
PSUBW (with 64-bit operands)
  DEST[15:0] <- DEST[15:0] − SRC[15:0];
  (* Repeat subtract operation for 2nd and 3rd word *)
  DEST[63:48] <- DEST[63:48] − SRC[63:48];
PSUBW (with 128-bit operands)
  DEST[15:0]
  (* Repeat subtract operation for 2nd through 7th word *)
  DEST[127:112] <- DEST[127:112] − SRC[127:112];
VPSUBW (VEX.128 encoded version)
DEST[15:0] <- SRC1[15:0]-SRC2[15:0]
DEST[31:16] <- SRC1[31:16]-SRC2[31:16]
DEST[47:32] <- SRC1[47:32]-SRC2[47:32]
DEST[63:48] <- SRC1[63:48]-SRC2[63:48]
DEST[79:64] <- SRC1[79:64]-SRC2[79:64]
DEST[95:80] <- SRC1[95:80]-SRC2[95:80]
DEST[111:96] <- SRC1[111:96]-SRC2[111:96]
DEST[127:112] <- SRC1[127:112]-SRC2[127:112]
DEST[VLMAX-1:128] <- 0
VPSUBW (VEX.256 encoded version)
DEST[15:0] <- SRC1[15:0]-SRC2[15:0]
DEST[31:16] <- SRC1[31:16]-SRC2[31:16]
DEST[47:32] <- SRC1[47:32]-SRC2[47:32]
DEST[63:48] <- SRC1[63:48]-SRC2[63:48]
DEST[79:64] <- SRC1[79:64]-SRC2[79:64]
DEST[95:80] <- SRC1[95:80]-SRC2[95:80]
DEST[111:96] <- SRC1[111:96]-SRC2[111:96]
DEST[127:112] <- SRC1[127:112]-SRC2[127:112]
DEST[143:128] <- SRC1[143:128]-SRC2[143:128]
DEST[159:144] <- SRC1[159:144]-SRC2[159:144]
DEST[175:160] <- SRC1[175:160]-SRC2[175:160]
DEST[191:176] <- SRC1[191:176]-SRC2[191:176]
DEST[207:192] <- SRC1207:192]-SRC2[207:192]
DEST[223:208] <- SRC1[223:208]-SRC2[223:208]
DEST[239:224] <- SRC1[239:224]-SRC2[239:224]
DEST[255:240] <- SRC1[255:240]-SRC2[255:240]
PSUBD (with 64-bit operands)
  DEST[31:0] <- DEST[31:0] − SRC[31:0];
  DEST[63:32] <- DEST[63:32] − SRC[63:32];
PSUBD (with 128-bit operands)
  DEST[31:0]
  (* Repeat subtract operation for 2nd and 3rd doubleword *)
  DEST[127:96] <- DEST[127:96] − SRC[127:96];
VPSUBD (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0]-SRC2[31:0]
DEST[63:32] <- SRC1[63:32]-SRC2[63:32]
DEST[95:64] <- SRC1[95:64]-SRC2[95:64]
DEST[127:96] <- SRC1[127:96]-SRC2[127:96]
DEST[VLMAX-1:128] <- 0
VPSUBD (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0]-SRC2[31:0]
DEST[63:32] <- SRC1[63:32]-SRC2[63:32]
DEST[95:64] <- SRC1[95:64]-SRC2[95:64]
DEST[127:96] <- SRC1[127:96]-SRC2[127:96]
DEST[159:128] <- SRC1[159:128]-SRC2[159:128]
DEST[191:160] <- SRC1[191:160]-SRC2[191:160]
DEST[223:192] <- SRC1[223:192]-SRC2[223:192]
DEST[255:224] <- SRC1[255:224]-SRC2[255:224]

Intel C/C++ Compiler Intrinsic Equivalents:
| PSUBB:   | __m64 _mm_sub_pi8(__m64 m1, __m64 m2)     
| (V)PSUBB:| __m128i _mm_sub_epi8 ( __m128i a, __m128i 
|          | b)                                        
| VPSUBB:  | __m256i _mm256_sub_epi8 ( __m256i a,      
|          | __m256i b)                                
| PSUBW:   | __m64 _mm_sub_pi16(__m64 m1, __m64 m2)    
| (V)PSUBW:| __m128i _mm_sub_epi16 ( __m128i a, __m128i
|          | b)                                        
| VPSUBW:  | __m256i _mm256_sub_epi16 ( __m256i a,     
|          | __m256i b)                                
| PSUBD:   | __m64 _mm_sub_pi32(__m64 m1, __m64 m2)    
| (V)PSUBD:| __m128i _mm_sub_epi32 ( __m128i a, __m128i
|          | b)                                        
| VPSUBD:  | __m256i _mm256_sub_epi32 ( __m256i a,     
|          | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSUBQ
description:
PSUBQ - Subtract Packed Quadword Integers:
| Opcode/Instruction                      | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| 0F FB /r1 PSUBQ mm1, mm2/m64            | RM   | V/V                   | SSE2              | Subtract quadword integer in mm1 from
|                                         |      |                       |                   | mm2 /m64.                            
| 66 0F FB /r PSUBQ xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Subtract packed quadword integers in 
|                                         |      |                       |                   | xmm1 from xmm2 /m128.                
| VEX.NDS.128.66.0F.WIG FB/r VPSUBQ xmm1, | RVM  | V/V                   | AVX               | Subtract packed quadword integers in 
| xmm2, xmm3/m128                         |      |                       |                   | xmm3/m128 from xmm2.                 
| VEX.NDS.256.66.0F.WIG FB /r VPSUBQ ymm1,| RVM  | V/V                   | AVX2              | Subtract packed quadword integers in 
| ymm2, ymm3/m256                         |      |                       |                   | ymm3/m256 from ymm2.                 
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Subtracts the second operand (source operand) from the first operand (destination
operand) and stores the result in the destination operand. When packed quadword
operands are used, a SIMD subtract is performed. When a quadword result is too
large to be represented in 64 bits (overflow), the result is wrapped around
and the low 64 bits are written to the destination element (that is, the carry
is ignored).

Note that the (V)PSUBQ instruction can operate on either unsigned or signed
(two's complement notation) integers; however, it does not set bits in the EFLAGS
register to indicate overflow and/or a carry. To prevent undetected overflow
conditions, software must control the ranges of the values upon which it operates.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE version: The source operand can be a quadword integer stored in an
MMX technology register or a 64bit memory location. 128-bit Legacy SSE version:
The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The second source operand is an XMM register or a 128-bit memory location.
The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The second
source operand is an YMM register or a 256-bit memory location. The first source
operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSUBQ (with 64-Bit operands)
  DEST[63:0] <- DEST[63:0] − SRC[63:0];
PSUBQ (with 128-Bit operands)
  DEST[63:0] <- DEST[63:0] − SRC[63:0];
  DEST[127:64] <- DEST[127:64] − SRC[127:64];
VPSUBQ (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0]-SRC2[63:0]
DEST[127:64] <- SRC1[127:64]-SRC2[127:64]
DEST[VLMAX-1:128] <- 0
VPSUBQ (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0]-SRC2[63:0]
DEST[127:64] <- SRC1[127:64]-SRC2[127:64]
DEST[191:128] <- SRC1[191:128]-SRC2[191:128]
DEST[255:192] <- SRC1[255:192]-SRC2[255:192]

Intel C/C++ Compiler Intrinsic Equivalents:
| PSUBQ:   | __m64 _mm_sub_si64(__m64 m1, __m64 m2)   
| (V)PSUBQ:| __m128i _mm_sub_epi64(__m128i m1, __m128i
|          | m2)                                      
| VPSUBQ:  | __m256i _mm256_sub_epi64(__m256i m1,     
|          | __m256i m2)                              

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSUBSB
description:
PSUBSB/PSUBSW - Subtract Packed Signed Integers with Signed Saturation:
| Opcode/Instruction                 | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                
| 0F E8 /r1 PSUBSB mm, mm/m64        | RM   | V/V                   | MMX               | Subtract signed packed bytes in mm/m64     
|                                    |      |                       |                   | from signed packed bytes in mm and saturate
|                                    |      |                       |                   | results.                                   
| 66 0F E8 /r PSUBSB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Subtract packed signed byte integers       
|                                    |      |                       |                   | in xmm2/m128 from packed signed byte       
|                                    |      |                       |                   | integers in xmm1 and saturate results.     
| 0F E9 /r1 PSUBSW mm, mm/m64        | RM   | V/V                   | MMX               | Subtract signed packed words in mm/m64     
|                                    |      |                       |                   | from signed packed words in mm and saturate
|                                    |      |                       |                   | results.                                   
| 66 0F E9 /r PSUBSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Subtract packed signed word integers       
|                                    |      |                       |                   | in xmm2/m128 from packed signed word       
|                                    |      |                       |                   | integers in xmm1 and saturate results.     
| VEX.NDS.128.66.0F.WIG E8 /r VPSUBSB| RVM  | V/V                   | AVX               | Subtract packed signed byte integers       
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm3/m128 from packed signed byte       
|                                    |      |                       |                   | integers in xmm2 and saturate results.     
| VEX.NDS.128.66.0F.WIG E9 /r VPSUBSW| RVM  | V/V                   | AVX               | Subtract packed signed word integers       
| xmm1, xmm2, xmm3/m128              |      |                       |                   | in xmm3/m128 from packed signed word       
|                                    |      |                       |                   | integers in xmm2 and saturate results.     
| VEX.NDS.256.66.0F.WIG E8 /r VPSUBSB| RVM  | V/V                   | AVX2              | Subtract packed signed byte integers       
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm3/m256 from packed signed byte       
|                                    |      |                       |                   | integers in ymm2 and saturate results.     
| VEX.NDS.256.66.0F.WIG E9 /r VPSUBSW| RVM  | V/V                   | AVX2              | Subtract packed signed word integers       
| ymm1, ymm2, ymm3/m256              |      |                       |                   | in ymm3/m256 from packed signed word       
|                                    |      |                       |                   | integers in ymm2 and saturate results.     
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD subtract of the packed signed integers of the source operand
(second operand) from the packed signed integers of the destination operand
(first operand), and stores the packed integer results in the destination operand.
See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled
with signed saturation, as described in the following paragraphs.

The (V)PSUBSB instruction subtracts packed signed byte integers. When an individual
byte result is beyond the range of a signed byte integer (that is, greater than
7FH or less than 80H), the saturated value of 7FH or 80H, respectively, is written
to the destination operand.

The (V)PSUBSW instruction subtracts packed signed word integers. When an individual
word result is beyond the range of a signed word integer (that is, greater than
7FFFH or less than 8000H), the saturated value of 7FFFH or 8000H, respectively,
is written to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE version: When operating on 64-bit operands, the destination operand
must be an MMX technology register and the source operand can be either an MMX
technology register or a 64-bit memory location. 128-bit Legacy SSE version:
The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The second source operand is an XMM register or a 128-bit memory location.
The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The second
source operand is an YMM register or a 256-bit memory location. The first source
operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSUBSB (with 64-bit operands)
  DEST[7:0] <- SaturateToSignedByte (DEST[7:0] − SRC (7:0]);
  (* Repeat subtract operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToSignedByte (DEST[63:56] − SRC[63:56] );
PSUBSB (with 128-bit operands)
  DEST[7:0] <- SaturateToSignedByte (DEST[7:0] − SRC[7:0]);
  (* Repeat subtract operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToSignedByte (DEST[127:120] − SRC[127:120]);
VPSUBSB (VEX.128 encoded version)
DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[VLMAX-1:128] <- 0
VPSUBSB (VEX.256 encoded version)
DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31th bytes *)
DEST[255:248] <- SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);
PSUBSW (with 64-bit operands)
  DEST[15:0] <- SaturateToSignedWord (DEST[15:0] − SRC[15:0] );
  (* Repeat subtract operation for 2nd and 7th words *)
  DEST[63:48] <- SaturateToSignedWord (DEST[63:48] − SRC[63:48] );
PSUBSW (with 128-bit operands)
  DEST[15:0]
  (* Repeat subtract operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToSignedWord (DEST[127:112] − SRC[127:112]);
VPSUBSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[VLMAX-1:128] <- 0
VPSUBSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] <- SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);

Intel C/C++ Compiler Intrinsic Equivalents:
| PSUBSB:   | __m64 _mm_subs_pi8(__m64 m1, __m64 m2)    
| (V)PSUBSB:| __m128i _mm_subs_epi8(__m128i m1, __m128i 
|           | m2)                                       
| VPSUBSB:  | __m256i _mm256_subs_epi8(__m256i m1,      
|           | __m256i m2)                               
| PSUBSW:   | __m64 _mm_subs_pi16(__m64 m1, __m64       
|           | m2)                                       
| (V)PSUBSW:| __m128i _mm_subs_epi16(__m128i m1, __m128i
|           | m2)                                       
| VPSUBSW:  | __m256i _mm256_subs_epi16(__m256i m1,     
|           | __m256i m2)                               

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PSUBUSB
description:
PSUBUSB/PSUBUSW - Subtract Packed Unsigned Integers with Unsigned Saturation:
| Opcode/Instruction                  | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                             
| 0F D8 /r1 PSUBUSB mm, mm/m64        | RM   | V/V                   | MMX               | Subtract unsigned packed bytes in mm/m64
|                                     |      |                       |                   | from unsigned packed bytes in mm and    
|                                     |      |                       |                   | saturate result.                        
| 66 0F D8 /r PSUBUSB xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Subtract packed unsigned byte integers  
|                                     |      |                       |                   | in xmm2/m128 from packed unsigned byte  
|                                     |      |                       |                   | integers in xmm1 and saturate result.   
| 0F D9 /r1 PSUBUSW mm, mm/m64        | RM   | V/V                   | MMX               | Subtract unsigned packed words in mm/m64
|                                     |      |                       |                   | from unsigned packed words in mm and    
|                                     |      |                       |                   | saturate result.                        
| 66 0F D9 /r PSUBUSW xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Subtract packed unsigned word integers  
|                                     |      |                       |                   | in xmm2/m128 from packed unsigned word  
|                                     |      |                       |                   | integers in xmm1 and saturate result.   
| VEX.NDS.128.66.0F.WIG D8 /r VPSUBUSB| RVM  | V/V                   | AVX               | Subtract packed unsigned byte integers  
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm3/m128 from packed unsigned byte  
|                                     |      |                       |                   | integers in xmm2 and saturate result.   
| VEX.NDS.128.66.0F.WIG D9 /r VPSUBUSW| RVM  | V/V                   | AVX               | Subtract packed unsigned word integers  
| xmm1, xmm2, xmm3/m128               |      |                       |                   | in xmm3/m128 from packed unsigned word  
|                                     |      |                       |                   | integers in xmm2 and saturate result.   
| VEX.NDS.256.66.0F.WIG D8 /r VPSUBUSB| RVM  | V/V                   | AVX2              | Subtract packed unsigned byte integers  
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm3/m256 from packed unsigned byte  
|                                     |      |                       |                   | integers in ymm2 and saturate result.   
| VEX.NDS.256.66.0F.WIG D9 /r VPSUBUSW| RVM  | V/V                   | AVX2              | Subtract packed unsigned word integers  
| ymm1, ymm2, ymm3/m256               |      |                       |                   | in ymm3/m256 from packed unsigned word  
|                                     |      |                       |                   | integers in ymm2 and saturate result.   
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a SIMD subtract of the packed unsigned integers of the source operand
(second operand) from the packed unsigned integers of the destination operand
(first operand), and stores the packed unsigned integer results in the destination
operand. See Figure 9-4 in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled
with unsigned saturation, as described in the following paragraphs.

These instructions can operate on either 64-bit or 128-bit operands.

The (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an
individual byte result is less than zero, the saturated value of 00H is written
to the destination operand.

The (V)PSUBUSW instruction subtracts packed unsigned word integers. When an
individual word result is less than zero, the saturated value of 0000H is written
to the destination operand.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE version: When operating on 64-bit operands, the destination operand
must be an MMX technology register and the source operand can be either an MMX
technology register or a 64-bit memory location. 128-bit Legacy SSE version:
The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: The second source operand is an XMM register or a 128-bit memory location.
The first source operand and destination operands are XMM registers. Bits (VLMAX-1:128)
of the destination YMM register are zeroed. VEX.256 encoded version: The second
source operand is an YMM register or a 256-bit memory location. The first source
operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PSUBUSB (with 64-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] − SRC (7:0] );
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToUnsignedByte (DEST[63:56] − SRC[63:56];
PSUBUSB (with 128-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] − SRC[7:0]);
  (* Repeat add operation for 2nd through 14th bytes *)
  DEST[127:120] <- SaturateToUnSignedByte (DEST[127:120] − SRC[127:120]);
VPSUBUSB (VEX.128 encoded version)
DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[VLMAX-1:128] <- 0
VPSUBUSB (VEX.256 encoded version)
DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31st bytes *)
DEST[255:148] <- SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);
PSUBUSW (with 64-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] − SRC[15:0] );
  (* Repeat add operation for 2nd and 3rd words *)
  DEST[63:48] <- SaturateToUnsignedWord (DEST[63:48] − SRC[63:48] );
PSUBUSW (with 128-bit operands)
  DEST[15:0]
  (* Repeat add operation for 2nd through 7th words *)
  DEST[127:112] <- SaturateToUnSignedWord (DEST[127:112] − SRC[127:112]);
VPSUBUSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[VLMAX-1:128] <- 0
VPSUBUSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);

Intel C/C++ Compiler Intrinsic Equivalents:
| PSUBUSB:                                           | __m64 _mm_subs_pu8(__m64 m1, __m64 m2)   
| (V)PSUBUSB:                                        | __m128i _mm_subs_epu8(__m128i m1, __m128i
|                                                    | m2)                                      
| VPSUBUSB:                                          | __m256i _mm256_subs_epu8(__m256i m1,     
|                                                    | __m256i m2)                              
| PSUBUSW: (V)PSUBUSW: __m128i _mm_subs_epu16(__m128i| __m64 _mm_subs_pu16(__m64 m1, __m64      
| m1, __m128i m2)                                    | m2)                                      
| VPSUBUSW:                                          | __m256i _mm256_subs_epu16(__m256i m1,    
|                                                    | __m256i m2)                              

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PTEST
description:
PTEST- Logical Compare:
| Opcode/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                           
| 66 0F 38 17 /r PTEST xmm1, xmm2/m128  | RM   | V/V                   | SSE4_1            | Set ZF if xmm2/m128 AND xmm1 result   
|                                       |      |                       |                   | is all 0s. Set CF if xmm2/m128 AND NOT
|                                       |      |                       |                   | xmm1 result is all 0s.                
| VEX.128.66.0F38.WIG 17 /r VPTEST xmm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on bitwise AND
| xmm2/m128                             |      |                       |                   | and ANDN of sources.                  
| VEX.256.66.0F38.WIG 17 /r VPTEST ymm1,| RM   | V/V                   | AVX               | Set ZF and CF depending on bitwise AND
| ymm2/m256                             |      |                       |                   | and ANDN of sources.                  

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (r)| ModRM:r/m (r)| NA       | NA       

Description:
PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise
AND of the first source operand (first operand) and the second source operand
(second operand). VPTEST sets the CF flag if all bits in the result are 0 of
the bitwise AND of the second source operand (second operand) and the logical
NOT of the destination operand. The first source register is specified by the
ModR/M reg field. 128-bit versions: The first source register is an XMM register.
The second source register can be an XMM register or a 128-bit memory location.
The destination register is not modified. VEX.256 encoded version: The first
source register is a YMM register. The second source register can be a YMM register
or a 256-bit memory location. The destination register is not modified. Note:
In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions
will #UD.

Operation:

(V)PTEST (128-bit version)
IF (SRC[127:0] BITWISE AND DEST[127:0] = 0)
  THEN ZF <- 1;
  ELSE ZF <- 0;
IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)
  THEN CF <- 1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;
VPTEST (VEX.256 encoded version)
IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF <- 1;
  ELSE ZF <- 0;
IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF <- 1;
  ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

Intel C/C++ Compiler Intrinsic Equivalent:
PTEST

int _mm_testz_si128 (__m128i s1, __m128i s2);

int _mm_testc_si128 (__m128i s1, __m128i s2);

int _mm_testnzc_si128 (__m128i s1, __m128i s2);

VPTEST

int _mm256_testz_si256 (__m256i s1, __m256i s2);

int _mm256_testc_si256 (__m256i s1, __m256i s2);

int _mm256_testnzc_si256 (__m256i s1, __m256i s2);

int _mm_testz_si128 (__m128i s1, __m128i s2);

int _mm_testc_si128 (__m128i s1, __m128i s2);

int _mm_testnzc_si128 (__m128i s1, __m128i s2);


Flags Affected:
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according
to the operation.


SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: PUNPCKHBW
description:
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ -  Unpack High Data:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                 
| 0F 68 /r1 PUNPCKHBW mm, mm/m64         | RM   | V/V                   | MMX               | Unpack and interleave high-order bytes      
|                                        |      |                       |                   | from mm and mm/m64 into mm.                 
| 66 0F 68 /r PUNPCKHBW xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Unpack and interleave high-order bytes      
|                                        |      |                       |                   | from xmm1 and xmm2/m128 into xmm1.          
| 0F 69 /r1 PUNPCKHWD mm, mm/m64         | RM   | V/V                   | MMX               | Unpack and interleave high-order words      
|                                        |      |                       |                   | from mm and mm/m64 into mm.                 
| 66 0F 69 /r PUNPCKHWD xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Unpack and interleave high-order words      
|                                        |      |                       |                   | from xmm1 and xmm2/m128 into xmm1.          
| 0F 6A /r1 PUNPCKHDQ mm, mm/m64         | RM   | V/V                   | MMX               | Unpack and interleave high-order doublewords
|                                        |      |                       |                   | from mm and mm/m64 into mm.                 
| 66 0F 6A /r PUNPCKHDQ xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Unpack and interleave high-order doublewords
|                                        |      |                       |                   | from xmm1 and xmm2/m128 into xmm1.          
| 66 0F 6D /r PUNPCKHQDQ xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Unpack and interleave high-order quadwords  
|                                        |      |                       |                   | from xmm1 and xmm2/m128 into xmm1.          
| VEX.NDS.128.66.0F.WIG 68/r VPUNPCKHBW  | RVM  | V/V                   | AVX               | Interleave high-order bytes from xmm2       
| xmm1,xmm2, xmm3/m128                   |      |                       |                   | and xmm3/m128 into xmm1.                    
| VEX.NDS.128.66.0F.WIG 69/r VPUNPCKHWD  | RVM  | V/V                   | AVX               | Interleave high-order words from xmm2       
| xmm1,xmm2, xmm3/m128                   |      |                       |                   | and xmm3/m128 into xmm1.                    
| VEX.NDS.128.66.0F.WIG 6A/r VPUNPCKHDQ  | RVM  | V/V                   | AVX               | Interleave high-order doublewords from      
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | xmm2 and xmm3/m128 into xmm1.               
| VEX.NDS.128.66.0F.WIG 6D/r VPUNPCKHQDQ | RVM  | V/V                   | AVX               | Interleave high-order quadword from         
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | xmm2 and xmm3/m128 into xmm1 register.      
| VEX.NDS.256.66.0F.WIG 68 /r VPUNPCKHBW | RVM  | V/V                   | AVX2              | Interleave high-order bytes from ymm2       
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and ymm3/m256 into ymm1 register.           
| VEX.NDS.256.66.0F.WIG 69 /r VPUNPCKHWD | RVM  | V/V                   | AVX2              | Interleave high-order words from ymm2       
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and ymm3/m256 into ymm1 register.           
| VEX.NDS.256.66.0F.WIG 6A /r VPUNPCKHDQ | RVM  | V/V                   | AVX2              | Interleave high-order doublewords from      
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | ymm2 and ymm3/m256 into ymm1 register.      
| VEX.NDS.256.66.0F.WIG 6D /r VPUNPCKHQDQ| RVM  | V/V                   | AVX2              | Interleave high-order quadword from         
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | ymm2 and ymm3/m256 into ymm1 register.      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Unpacks and interleaves the high-order data elements (bytes, words, doublewords,
or quadwords) of the destination operand (first operand) and source operand
(second operand) into the destination operand. Figure 4-16 shows the unpack
operation for bytes in 64-bit operands. The low-order data elements are ignored.

| SRC SRC| Y7 DEST Figure 4-16. 255 Y7| Y6 Y7 Y6 Figure 4-17.| Y5 X7 Y5| Y4 Y6 PUNPCKHBW Instruction Operation| Y3 X6 Y3| Y2 Y5 Y2 256-bit VPUNPCKHDQ Instruction| Y1 X5 Y1 DEST| Y0 X4 0 Y0 255 Y7| X7 255 X7 Y6| X6 X6 X6| X5 X5 Y3| X4 X4 X3| X3 X3 Y2| X2 X2 X2| X1 X1 0| X0 31 X0| DEST 0
|        |                            |                      |         | Using 64-bit Operands Y4             |         | Operation                              |              |                  |             |         |         |         |         |         |        |         |       
When the source data comes from a 64-bit memory operand, the full 64-bit operand
is accessed from memory, but the instruction uses only the high-order 32 bits.
When the source data comes from a 128-bit memory operand, an implementation
may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary
and normal segment checking will still be enforced.

The (V)PUNPCKHBW instruction interleaves the high-order bytes of the source
and destination operands, the (V)PUNPCKHWD instruction interleaves the high-order
words of the source and destination operands, the (V)PUNPCKHDQ instruction interleaves
the high-order doubleword (or doublewords) of the source and destination operands,
and the (V)PUNPCKHQDQ instruction interleaves the high-order quadwords of the
source and destination operands.

These instructions can be used to convert bytes to words, words to doublewords,
doublewords to quadwords, and quadwords to double quadwords, respectively, by
placing all 0s in the source operand. Here, if the source operand contains all
0s, the result (stored in the destination operand) contains zero extensions
of the high-order data elements from the original value in the destination operand.
For example, with the (V)PUNPCKHBW instruction the high-order bytes are zero
extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKHWD
instruction, the high-order words are zero extended (unpacked into unsigned
doubleword integers).

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE versions: The source operand can be an MMX technology register or
a 64-bit memory location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or
a 128-bit memory location. The first source operand and destination operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged.

VEX.128 encoded versions: The second source operand is an XMM register or a
128-bit memory location. The first source operand and destination operands are
XMM registers. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or a 256-bit
memory location. The first source operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PUNPCKHBW instruction with 64-bit operands:
  DEST[7:0] <- DEST[39:32];
  DEST[15:8] <- SRC[39:32];
  DEST[23:16] <- DEST[47:40];
  DEST[31:24] <- SRC[47:40];
  DEST[39:32] <- DEST[55:48];
  DEST[47:40] <- SRC[55:48];
  DEST[55:48] <- DEST[63:56];
  DEST[63:56] <- SRC[63:56];
PUNPCKHW instruction with 64-bit operands:
  DEST[15:0] <- DEST[47:32];
  DEST[31:16] <- SRC[47:32];
  DEST[47:32] <- DEST[63:48];
  DEST[63:48] <- SRC[63:48];
PUNPCKHDQ instruction with 64-bit operands:
  DEST[31:0] <- DEST[63:32];
  DEST[63:32] <- SRC[63:32];
PUNPCKHBW instruction with 128-bit operands:
  DEST[7:0]<- DEST[71:64];
  DEST[15:8]
  DEST[23:16] <- DEST[79:72];
  DEST[31:24] <- SRC[79:72];
  DEST[39:32] <- DEST[87:80];
  DEST[47:40] <- SRC[87:80];
  DEST[55:48] <- DEST[95:88];
  DEST[63:56] <- SRC[95:88];
  DEST[71:64] <- DEST[103:96];
  DEST[79:72] <- SRC[103:96];
  DEST[87:80] <- DEST[111:104];
  DEST[95:88] <- SRC[111:104];
  DEST[103:96]
  DEST[111:104] <- SRC[119:112];
  DEST[119:112] <- DEST[127:120];
  DEST[127:120] <- SRC[127:120];
PUNPCKHWD instruction with 128-bit operands:
  DEST[15:0]
  DEST[31:16] <- SRC[79:64];
  DEST[47:32] <- DEST[95:80];
  DEST[63:48] <- SRC[95:80];
  DEST[79:64] <- DEST[111:96];
  DEST[95:80] <- SRC[111:96];
  DEST[111:96]
  DEST[127:112] <- SRC[127:112];
PUNPCKHDQ instruction with 128-bit operands:
  DEST[31:0] <- DEST[95:64];
  DEST[63:32]
  DEST[95:64]
  DEST[127:96] <- SRC[127:96];
PUNPCKHQDQ instruction:
  DEST[63:0] <- DEST[127:64];
  DEST[127:64] <- SRC[127:64];
INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)
DEST[7:0] <- SRC1[71:64]
DEST[15:8] <- SRC2[71:64]
DEST[23:16] <- SRC1[79:72]
DEST[31:24] <- SRC2[79:72]
DEST[39:32] <- SRC1[87:80]
DEST[47:40] <- SRC2[87:80]
DEST[55:48] <- SRC1[95:88]
DEST[63:56] <-SRC2[95:88]
DEST[71:64] <- SRC1[103:96]
DEST[79:72] <- SRC2[103:96]
DEST[87:80] <- SRC1[111:104]
DEST[95:88] <- SRC2[111:104]
DEST[103:96] <- SRC1[119:112]
DEST[111:104] <- SRC2[119:112]
DEST[119:112] <- SRC1[127:120]
DEST[127:120] <- SRC2[127:120]
DEST[135:128] <- SRC1[199:192]
DEST[143:136] <- SRC2[199:192]
DEST[151:144] <- SRC1[207:200]
DEST[159:152] <- SRC2[207:200]
DEST[167:160] <- SRC1[215:208]
DEST[175:168] <- SRC2[215:208]
DEST[183:176] <- SRC1[223:216]
DEST[191:184] <-SRC2[223:216]
DEST[199:192] <- SRC1[231:224]
DEST[207:200] <- SRC2[231:224]
DEST[215:208] <- SRC1[239:232]
DEST[223:216] <- SRC2[239:232]
DEST[231:224] <- SRC1[247:240]
DEST[239:232] <- SRC2[247:240]
DEST[247:240] <- SRC1[255:248]
DEST[255:248] <- SRC2[255:248]
INTERLEAVE_HIGH_BYTES (SRC1, SRC2)
DEST[7:0] <- SRC1[71:64]
DEST[15:8] <- SRC2[71:64]
DEST[23:16] <- SRC1[79:72]
DEST[31:24] <- SRC2[79:72]
DEST[39:32] <- SRC1[87:80]
DEST[47:40] <- SRC2[87:80]
DEST[55:48] <- SRC1[95:88]
DEST[63:56] <-SRC2[95:88]
DEST[71:64] <- SRC1[103:96]
DEST[79:72] <- SRC2[103:96]
DEST[87:80] <- SRC1[111:104]
DEST[95:88] <- SRC2[111:104]
DEST[103:96] <- SRC1[119:112]
DEST[111:104] <- SRC2[119:112]
DEST[119:112] <- SRC1[127:120]
DEST[127:120] <- SRC2[127:120]
INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
DEST[15:0] <- SRC1[79:64]
DEST[31:16] <- SRC2[79:64]
DEST[47:32] <- SRC1[95:80]
DEST[63:48] <- SRC2[95:80]
DEST[79:64] <- SRC1[111:96]
DEST[95:80] <- SRC2[111:96]
DEST[111:96] <- SRC1[127:112]
DEST[127:112] <- SRC2[127:112]
DEST[143:128] <- SRC1[207:192]
DEST[159:144] <- SRC2[207:192]
DEST[175:160] <- SRC1[223:208]
DEST[191:176] <- SRC2[223:208]
DEST[207:192] <- SRC1[239:224]
DEST[223:208] <- SRC2[239:224]
DEST[239:224] <- SRC1[255:240]
DEST[255:240] <- SRC2[255:240]
INTERLEAVE_HIGH_WORDS (SRC1, SRC2)
DEST[15:0] <- SRC1[79:64]
DEST[31:16] <- SRC2[79:64]
DEST[47:32] <- SRC1[95:80]
DEST[63:48] <- SRC2[95:80]
DEST[79:64] <- SRC1[111:96]
DEST[95:80] <- SRC2[111:96]
DEST[111:96] <-SRC1[127:112]
DEST[127:112] <- SRC2[127:112]
INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
DEST[159:128] <- SRC1[223:192]
DEST[191:160] <- SRC2[223:192]
DEST[223:192] <- SRC1[255:224]
DEST[255:224] <- SRC2[255:224]
INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
DEST[191:128] <- SRC1[255:192]
DEST[255:192] <- SRC2[255:192]
INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
PUNPCKHBW (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_HIGH_BYTES(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
VPUNPCKHBW (VEX.128 encoded version)
DEST[127:0] <- INTERLEAVE_HIGH_BYTES(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKHBW (VEX.256 encoded version)
DEST[255:0] <- INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)
PUNPCKHWD (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_HIGH_WORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
VPUNPCKHWD (VEX.128 encoded version)
DEST[127:0] <- INTERLEAVE_HIGH_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKHWD (VEX.256 encoded version)
DEST[255:0] <- INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
PUNPCKHDQ (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_HIGH_DWORDS(DEST, SRC)
DEST[VLMAX-1:128] (Unmodified)
VPUNPCKHDQ (VEX.128 encoded version)
DEST[127:0] <- INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKHDQ (VEX.256 encoded version)
DEST[255:0] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
PUNPCKHQDQ (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_HIGH_QWORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHQDQ (VEX.128 encoded version)
DEST[127:0] <- INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[255:127] <- 0
VPUNPCKHQDQ (VEX.256 encoded version)
DEST[255:0] <- INTERLEAVE_HIGH_QWORDS_256(SRC1, SRC2)

Intel C/C++ Compiler Intrinsic Equivalents:
| PUNPCKHBW:    | __m64 _mm_unpackhi_pi8(__m64 m1, __m64       
|               | m2)                                          
| (V)PUNPCKHBW: | __m128i _mm_unpackhi_epi8(__m128i m1,        
|               | __m128i m2)                                  
| VPUNPCKHBW:   | __m256i _mm256_unpackhi_epi8(__m256i         
|               | m1, __m256i m2)                              
| PUNPCKHWD:    | __m64 _mm_unpackhi_pi16(__m64 m1,__m64       
|               | m2)                                          
| (V)PUNPCKHWD: | __m128i _mm_unpackhi_epi16(__m128i m1,__m128i
|               | m2)                                          
| VPUNPCKHWD:   | __m256i _mm256_unpackhi_epi16(__m256i        
|               | m1,__m256i m2)                               
| PUNPCKHDQ:    | __m64 _mm_unpackhi_pi32(__m64 m1, __m64      
|               | m2)                                          
| (V)PUNPCKHDQ: | __m128i _mm_unpackhi_epi32(__m128i m1,       
|               | __m128i m2)                                  
| VPUNPCKHDQ:   | __m256i _mm256_unpackhi_epi32(__m256i        
|               | m1, __m256i m2)                              
| (V)PUNPCKHQDQ:| __m128i _mm_unpackhi_epi64 ( __m128i         
|               | a, __m128i b)                                
| VPUNPCKHQDQ:  | __m256i _mm256_unpackhi_epi64 ( __m256i      
|               | a, __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PUNPCKLBW
description:
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ - Unpack Low Data:
| Opcode/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                            
| 0F 60 /r1 PUNPCKLBW mm, mm/m32         | RM   | V/V                   | MMX               | Interleave low-order bytes from mm and 
|                                        |      |                       |                   | mm/m32 into mm.                        
| 66 0F 60 /r PUNPCKLBW xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Interleave low-order bytes from xmm1   
|                                        |      |                       |                   | and xmm2/m128 into xmm1.               
| 0F 61 /r1 PUNPCKLWD mm, mm/m32         | RM   | V/V                   | MMX               | Interleave low-order words from mm and 
|                                        |      |                       |                   | mm/m32 into mm.                        
| 66 0F 61 /r PUNPCKLWD xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Interleave low-order words from xmm1   
|                                        |      |                       |                   | and xmm2/m128 into xmm1.               
| 0F 62 /r1 PUNPCKLDQ mm, mm/m32         | RM   | V/V                   | MMX               | Interleave low-order doublewords from  
|                                        |      |                       |                   | mm and mm/m32 into mm.                 
| 66 0F 62 /r PUNPCKLDQ xmm1, xmm2/m128  | RM   | V/V                   | SSE2              | Interleave low-order doublewords from  
|                                        |      |                       |                   | xmm1 and xmm2/m128 into xmm1.          
| 66 0F 6C /r PUNPCKLQDQ xmm1, xmm2/m128 | RM   | V/V                   | SSE2              | Interleave low-order quadword from xmm1
|                                        |      |                       |                   | and xmm2/m128 into xmm1 register.      
| VEX.NDS.128.66.0F.WIG 60/r VPUNPCKLBW  | RVM  | V/V                   | AVX               | Interleave low-order bytes from xmm2   
| xmm1,xmm2, xmm3/m128                   |      |                       |                   | and xmm3/m128 into xmm1.               
| VEX.NDS.128.66.0F.WIG 61/r VPUNPCKLWD  | RVM  | V/V                   | AVX               | Interleave low-order words from xmm2   
| xmm1,xmm2, xmm3/m128                   |      |                       |                   | and xmm3/m128 into xmm1.               
| VEX.NDS.128.66.0F.WIG 62/r VPUNPCKLDQ  | RVM  | V/V                   | AVX               | Interleave low-order doublewords from  
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | xmm2 and xmm3/m128 into xmm1.          
| VEX.NDS.128.66.0F.WIG 6C/r VPUNPCKLQDQ | RVM  | V/V                   | AVX               | Interleave low-order quadword from xmm2
| xmm1, xmm2, xmm3/m128                  |      |                       |                   | and xmm3/m128 into xmm1 register.      
| VEX.NDS.256.66.0F.WIG 60 /r VPUNPCKLBW | RVM  | V/V                   | AVX2              | Interleave low-order bytes from ymm2   
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and ymm3/m256 into ymm1 register.      
| VEX.NDS.256.66.0F.WIG 61 /r VPUNPCKLWD | RVM  | V/V                   | AVX2              | Interleave low-order words from ymm2   
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and ymm3/m256 into ymm1 register.      
| VEX.NDS.256.66.0F.WIG 62 /r VPUNPCKLDQ | RVM  | V/V                   | AVX2              | Interleave low-order doublewords from  
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | ymm2 and ymm3/m256 into ymm1 register. 
| VEX.NDS.256.66.0F.WIG 6C /r VPUNPCKLQDQ| RVM  | V/V                   | AVX2              | Interleave low-order quadword from ymm2
| ymm1, ymm2, ymm3/m256                  |      |                       |                   | and ymm3/m256 into ymm1 register.      
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Unpacks and interleaves the low-order data elements (bytes, words, doublewords,
and quadwords) of the destination operand (first operand) and source operand
(second operand) into the destination operand. (Figure 4-18 shows the unpack
operation for bytes in 64-bit operands.). The high-order data elements are ignored.

| SRC SRC| Y7 Figure 4-18. 255 Y7| Y6 Y6 Figure 4-19.| Y5 Y5| Y4 PUNPCKLBW Instruction Operation Using| Y3 Y3| Y2 Y2 256-bit VPUNPCKLDQ Instruction| Y1 DEST Y1 DEST| Y0 Y3 0 Y0 255 Y5| X7 Y2 255 X7 Y4| X6 X2 X6 X4| X5 Y1 X5 Y1| X4 X1 X4 X1| X3 Y0 X3 Y0| X2 X0 X2 X0| X1 X1 0| X0 31 X0| DEST 0
|        |                       |                   |      | 64-bit Operands Y4                      |      | Operation                           |                |                  |                |            |            |            |            |            |        |         |       
When the source data comes from a 128-bit memory operand, an implementation
may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary
and normal segment checking will still be enforced.

The (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and
destination operands, the (V)PUNPCKLWD instruction interleaves the low-order
words of the source and destination operands, the (V)PUNPCKLDQ instruction interleaves
the low-order doubleword (or doublewords) of the source and destination operands,
and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the
source and destination operands.

These instructions can be used to convert bytes to words, words to doublewords,
doublewords to quadwords, and quadwords to double quadwords, respectively, by
placing all 0s in the source operand. Here, if the source operand contains all
0s, the result (stored in the destination operand) contains zero extensions
of the high-order data elements from the original value in the destination operand.
For example, with the (V)PUNPCKLBW instruction the high-order bytes are zero
extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD
instruction, the high-order words are zero extended (unpacked into unsigned
doubleword integers).

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE versions: The source operand can be an MMX technology register or
a 32-bit memory location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or
a 128-bit memory location. The first source operand and destination operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded versions: The second source operand is an
XMM register or a 128-bit memory location. The first source operand and destination
operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.

VEX.256 encoded version: The second source operand is an YMM register or a 256-bit
memory location. The first source operand and destination operands are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PUNPCKLBW instruction with 64-bit operands:
  DEST[63:56] <- SRC[31:24];
  DEST[55:48] <- DEST[31:24];
  DEST[47:40] <- SRC[23:16];
  DEST[39:32] <- DEST[23:16];
  DEST[31:24] <- SRC[15:8];
  DEST[23:16] <- DEST[15:8];
  DEST[15:8] <- SRC[7:0];
  DEST[7:0] <- DEST[7:0];
PUNPCKLWD instruction with 64-bit operands:
  DEST[63:48] <- SRC[31:16];
  DEST[47:32] <- DEST[31:16];
  DEST[31:16] <- SRC[15:0];
  DEST[15:0] <- DEST[15:0];
PUNPCKLDQ instruction with 64-bit operands:
  DEST[63:32] <- SRC[31:0];
  DEST[31:0] <- DEST[31:0];
PUNPCKLBW instruction with 128-bit operands:
  DEST[7:0]<- DEST[7:0];
  DEST[15:8]
  DEST[23:16] <- DEST[15:8];
  DEST[31:24] <- SRC[15:8];
  DEST[39:32] <- DEST[23:16];
  DEST[47:40] <- SRC[23:16];
  DEST[55:48] <- DEST[31:24];
  DEST[63:56] <- SRC[31:24];
  DEST[71:64] <- DEST[39:32];
  DEST[79:72] <- SRC[39:32];
  DEST[87:80] <- DEST[47:40];
  DEST[95:88] <- SRC[47:40];
  DEST[103:96]
  DEST[111:104] <- SRC[55:48];
  DEST[119:112] <- DEST[63:56];
  DEST[127:120] <- SRC[63:56];
PUNPCKLWD instruction with 128-bit operands:
  DEST[15:0]
  DEST[31:16] <- SRC[15:0];
  DEST[47:32] <- DEST[31:16];
  DEST[63:48] <- SRC[31:16];
  DEST[79:64] <- DEST[47:32];
  DEST[95:80] <- SRC[47:32];
  DEST[111:96]
  DEST[127:112] <- SRC[63:48];
PUNPCKLDQ instruction with 128-bit operands:
  DEST[31:0] <- DEST[31:0];
  DEST[63:32]
  DEST[95:64]
  DEST[127:96] <- SRC[63:32];
PUNPCKLQDQ
  DEST[63:0] <- DEST[63:0];
  DEST[127:64] <- SRC[63:0];
INTERLEAVE_BYTES_256b (SRC1, SRC2)
DEST[7:0] <- SRC1[7:0]
DEST[15:8] <- SRC2[7:0]
DEST[23:16] <- SRC1[15:8]
DEST[31:24] <- SRC2[15:8]
DEST[39:32] <- SRC1[23:16]
DEST[47:40] <- SRC2[23:16]
DEST[55:48] <- SRC1[31:24]
DEST[63:56] <-SRC2[31:24]
DEST[71:64] <- SRC1[39:32]
DEST[79:72] <- SRC2[39:32]
DEST[87:80] <- SRC1[47:40]
DEST[95:88] <- SRC2[47:40]
DEST[103:96] <- SRC1[55:48]
DEST[111:104] <- SRC2[55:48]
DEST[119:112] <- SRC1[63:56]
DEST[127:120] <- SRC2[63:56]
DEST[135:128] <- SRC1[135:128]
DEST[143:136] <- SRC2[135:128]
DEST[151:144] <- SRC1[143:136]
DEST[159:152] <- SRC2[143:136]
DEST[167:160] <- SRC1[151:144]
DEST[175:168] <- SRC2[151:144]
DEST[183:176] <- SRC1[159:152]
DEST[191:184] <-SRC2[159:152]
DEST[199:192] <- SRC1[167:160]
DEST[207:200] <- SRC2[167:160]
DEST[215:208] <- SRC1[175:168]
DEST[223:216] <- SRC2[175:168]
DEST[231:224] <- SRC1[183:176]
DEST[239:232] <- SRC2[183:176]
DEST[247:240] <- SRC1[191:184]
DEST[255:248] <- SRC2[191:184]
INTERLEAVE_BYTES (SRC1, SRC2)
DEST[7:0] <- SRC1[7:0]
DEST[15:8] <- SRC2[7:0]
DEST[23:16] <- SRC2[15:8]
DEST[31:24] <- SRC2[15:8]
DEST[39:32] <- SRC1[23:16]
DEST[47:40] <- SRC2[23:16]
DEST[55:48] <- SRC1[31:24]
DEST[63:56] <-SRC2[31:24]
DEST[71:64] <- SRC1[39:32]
DEST[79:72] <- SRC2[39:32]
DEST[87:80] <- SRC1[47:40]
DEST[95:88] <- SRC2[47:40]
DEST[103:96] <- SRC1[55:48]
DEST[111:104] <- SRC2[55:48]
DEST[119:112] <- SRC1[63:56]
DEST[127:120] <- SRC2[63:56]
INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[15:0] <- SRC1[15:0]
DEST[31:16] <- SRC2[15:0]
DEST[47:32] <- SRC1[31:16]
DEST[63:48] <- SRC2[31:16]
DEST[79:64] <- SRC1[47:32]
DEST[95:80] <- SRC2[47:32]
DEST[111:96] <- SRC1[63:48]
DEST[127:112] <- SRC2[63:48]
DEST[143:128] <- SRC1[143:128]
DEST[159:144] <- SRC2[143:128]
DEST[175:160] <- SRC1[159:144]
DEST[191:176] <- SRC2[159:144]
DEST[207:192] <- SRC1[175:160]
DEST[223:208] <- SRC2[175:160]
DEST[239:224] <- SRC1[191:176]
DEST[255:240] <- SRC2[191:176]
INTERLEAVE_WORDS (SRC1, SRC2)
DEST[15:0] <- SRC1[15:0]
DEST[31:16] <- SRC2[15:0]
DEST[47:32] <- SRC1[31:16]
DEST[63:48] <- SRC2[31:16]
DEST[79:64] <- SRC1[47:32]
DEST[95:80] <- SRC2[47:32]
DEST[111:96] <- SRC1[63:48]
DEST[127:112] <- SRC2[63:48]
INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
DEST[159:128] <- SRC1[159:128]
DEST[191:160] <- SRC2[159:128]
DEST[223:192] <- SRC1[191:160]
DEST[255:224] <- SRC2[191:160]
INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[191:128] <- SRC1[191:128]
DEST[255:192] <- SRC2[191:128]
INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
PUNPCKLBW (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLBW (VEX.128 encoded instruction)
DEST[127:0] <- INTERLEAVE_BYTES(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKLBW (VEX.256 encoded instruction)
DEST[255:0] <- INTERLEAVE_BYTES_128b(SRC1, SRC2)
PUNPCKLWD (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLWD (VEX.128 encoded instruction)
DEST[127:0] <- INTERLEAVE_WORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKLWD (VEX.256 encoded instruction)
DEST[255:0] <- INTERLEAVE_WORDS(SRC1, SRC2)
PUNPCKLDQ (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_DWORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLDQ (VEX.128 encoded instruction)
DEST[127:0] <- INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKLDQ (VEX.256 encoded instruction)
DEST[255:0] <- INTERLEAVE_DWORDS(SRC1, SRC2)
PUNPCKLQDQ (128-bit Legacy SSE Version)
DEST[127:0] <- INTERLEAVE_QWORDS(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKLQDQ (VEX.128 encoded instruction)
DEST[127:0] <- INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[VLMAX-1:128] <- 0
VPUNPCKLQDQ (VEX.256 encoded instruction)
DEST[255:0] <- INTERLEAVE_QWORDS(SRC1, SRC2)

Intel C/C++ Compiler Intrinsic Equivalents:
| PUNPCKLBW:    | __m64 _mm_unpacklo_pi8 (__m64 m1, __m64 
|               | m2)                                     
| (V)PUNPCKLBW: | __m128i _mm_unpacklo_epi8 (__m128i m1,  
|               | __m128i m2)                             
| VPUNPCKLBW:   | __m256i _mm256_unpacklo_epi8 (__m256i   
|               | m1, __m256i m2)                         
| PUNPCKLWD:    | __m64 _mm_unpacklo_pi16 (__m64 m1, __m64
|               | m2)                                     
| (V)PUNPCKLWD: | __m128i _mm_unpacklo_epi16 (__m128i     
|               | m1, __m128i m2)                         
| VPUNPCKLWD:   | __m256i _mm256_unpacklo_epi16 (__m256i  
|               | m1, __m256i m2)                         
| PUNPCKLDQ:    | __m64 _mm_unpacklo_pi32 (__m64 m1, __m64
|               | m2)                                     
| (V)PUNPCKLDQ: | __m128i _mm_unpacklo_epi32 (__m128i     
|               | m1, __m128i m2)                         
| VPUNPCKLDQ:   | __m256i _mm256_unpacklo_epi32 (__m256i  
|               | m1, __m256i m2)                         
| (V)PUNPCKLQDQ:| __m128i _mm_unpacklo_epi64 (__m128i     
|               | m1, __m128i m2)                         
| VPUNPCKLQDQ:  | __m256i _mm256_unpacklo_epi64 (__m256i  
|               | m1, __m256i m2)                         

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: PUSH
description:
PUSH - Push Word, Doubleword or Quadword Onto the Stack:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description
| FF /6  | PUSH r/m16 | M    | Valid      | Valid          | Push r/m16.
| FF /6  | PUSH r/m32 | M    | N.E.       | Valid          | Push r/m32.
| FF /6  | PUSH r/m64 | M    | Valid      | N.E.           | Push r/m64.
| 50+rw  | PUSH r16   | O    | Valid      | Valid          | Push r16.  
| 50+rd  | PUSH r32   | O    | N.E.       | Valid          | Push r32.  
| 50+rd  | PUSH r64   | O    | Valid      | N.E.           | Push r64.  
| 6A ib  | PUSH imm8  | I    | Valid      | Valid          | Push imm8. 
| 68 iw  | PUSH imm16 | I    | Valid      | Valid          | Push imm16.
| 68 id  | PUSH imm32 | I    | Valid      | Valid          | Push imm32.
| 0E     | PUSH CS    | NP   | Invalid    | Valid          | Push CS.   
| 16     | PUSH SS    | NP   | Invalid    | Valid          | Push SS.   
| 1E     | PUSH DS    | NP   | Invalid    | Valid          | Push DS.   
| 06     | PUSH ES    | NP   | Invalid    | Valid          | Push ES.   
| 0F A0  | PUSH FS    | NP   | Valid      | Valid          | Push FS.   
| 0F A8  | PUSH GS    | NP   | Valid      | Valid          | Push GS.   
Notes: * See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1      | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (r)  | NA       | NA       | NA       
| O    | opcode + rd (r)| NA       | NA       | NA       
| I    | imm8/16/32     | NA       | NA       | NA       
| NP   | NA             | NA       | NA       | NA       

Description:
Decrements the stack pointer and then stores the source operand on the top of
the stack. Address and operand sizes are determined and used as follows:

 - Address size. The D flag in the current code-segment descriptor determines the
default address size; it may be overridden by an instruction prefix (67H). The
address size is used only when referencing a source operand in memory.
 - Operand size. The D flag in the current code-segment descriptor determines the
default operand size; it may be overridden by instruction prefixes (66H or REX.W).
The operand size (16, 32, or 64 bits) determines the amount by which the stack
pointer is decremented (2, 4 or 8). If the source operand is an immediate of
size less than the operand size, a sign-extended value is pushed on the stack.
If the source operand is a segment register (16 bits) and the operand size is
64-bits, a zeroextended value is pushed on the stack; if the operand size is
32-bits, either a zero-extended value is pushed on the stack or the segment
selector is written on the stack using a 16-bit move. For the last case, all
recent Core and Atom processors perform a 16-bit move, leaving the upper portion
of the stack location unmodified.
 - Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment
descriptor determines the size of the stack pointer (16 or 32 bits); in 64-bit
mode, the size of the stack pointer is always 64 bits. The stack-address size
determines the width of the stack pointer when writing to the stack in memory
and when decrementing the stack pointer. (As stated above, the amount by which
the stack pointer is decremented is determined by the operand size.) If the
operand size is less than the stack-address size, the PUSH instruction may result
in a misaligned stack pointer (a stack pointer that is not aligned on a doubleword
or quadword boundary).

The PUSH ESP instruction pushes the value of the ESP register as it existed
before the instruction was executed. If a PUSH instruction uses a memory operand
in which the ESP register is used for computing the operand address, the address
of the operand is computed before the ESP register is decremented.

If the ESP or SP register is 1 when the PUSH instruction is executed in real-address
mode, a stack-fault exception (#SS) is generated (because the limit of the stack
segment is violated). Its delivery encounters a second stackfault exception
(for the same reason), causing generation of a double-fault exception (#DF).
Delivery of the double-fault exception encounters a third stack-fault exception,
and the logical processor enters shutdown mode. See the discussion of the double-fault
exception in Chapter 6 of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


IA-32 Architecture Compatibility:
For IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes
the value of the ESP register as it existed before the instruction was executed.
(This is also true for Intel 64 architecture, real-address and virtual8086 modes
of IA-32 architecture.) For the Intel® 8086 processor, the PUSH SP instruction
pushes the new value of the SP register (that is the value after it has been
decremented by 2).

Operation:

(* See Description section for possible sign-extension or zero-extension of source operand and for *)
(* a case in which the size of the memory store may be smaller than the instruction's operand size *)
IF StackAddrSize = 64
  THEN
     IF OperandSize = 64
       THEN
          RSP <- RSP - 8;
          Memory[SS:RSP] <- SRC;
     ELSE IF OperandSize = 32
       THEN
          RSP <- RSP - 4;
          Memory[SS:RSP] <- SRC;
       ELSE (* OperandSize = 16 *)
          RSP <- RSP - 2;
          Memory[SS:RSP] <- SRC;
     FI;
ELSE IF StackAddrSize = 32
  THEN
     IF OperandSize = 64
       THEN
          ESP <- ESP - 8;
          Memory[SS:ESP] <- SRC;
     ELSE IF OperandSize = 32
       THEN
          ESP <- ESP - 4;
          Memory[SS:ESP] <- SRC;
       ELSE (* OperandSize = 16 *)
          ESP <- ESP - 2;
          Memory[SS:ESP] <- SRC;
     FI;
  ELSE (* StackAddrSize = 16 *)
     IF OperandSize = 32
       THEN
          SP <- SP - 4;
          Memory[SS:SP] <- SRC;
       ELSE (* OperandSize = 16 *)
          SP <- SP - 2;
          Memory[SS:SP] <- SRC;
     FI;
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)         | If a memory operand effective address   
|                | is outside the CS, DS, ES, FS, or GS    
|                | segment limit. If the DS, ES, FS, or    
|                | GS register is used to access memory    
|                | and it contains a NULL segment selector.
| #SS(0)         | If a memory operand effective address   
|                | is outside the SS segment limit.        
| #PF(fault-code)| If a page fault occurs.                 
| #AC(0)         | If alignment checking is enabled and    
|                | an unaligned memory reference is made   
|                | while the current privilege level is    
|                | 3.                                      
| #UD            | If the LOCK prefix is used.             

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address  
|    | is outside the CS, DS, ES, FS, or GS   
|    | segment limit.                         
| #SS| If a memory operand effective address  
|    | is outside the SS segment limit. If    
|    | the new value of the SP or ESP register
|    | is outside the stack segment limit.    
| #UD| If the LOCK prefix is used.            

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #SS(0)         | If the stack address is in a non-canonical 
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If alignment checking is enabled and       
|                | an unaligned memory reference is made      
|                | while the current privilege level is       
|                | 3.                                         
| #UD            | If the LOCK prefix is used. If the PUSH    
|                | is of CS, SS, DS, or ES.                   


platform: x86
mnem: PUSHA
description:
PUSHA/PUSHAD - Push All General-Purpose Registers:
| Opcode| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                           
| 60    | PUSHA      | NP   | Invalid    | Valid          | Push AX, CX, DX, BX, original SP, BP, 
|       |            |      |            |                | SI, and DI.                           
| 60    | PUSHAD     | NP   | Invalid    | Valid          | Push EAX, ECX, EDX, EBX, original ESP,
|       |            |      |            |                | EBP, ESI, and EDI.                    

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Pushes the contents of the general-purpose registers onto the stack. The registers
are stored on the stack in the following order: EAX, ECX, EDX, EBX, ESP (original
value), EBP, ESI, and EDI (if the current operand-size attribute is 32) and
AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute
is 16). These instructions perform the reverse operation of the POPA/POPAD instructions.
The value pushed for the ESP or SP register is its value before prior to pushing
the first register (see the “Operation” section below).

The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same
opcode. The PUSHA instruction is intended for use when the operand-size attribute
is 16 and the PUSHAD instruction for when the operandsize attribute is 32. Some
assemblers may force the operand size to 16 when PUSHA is used and to 32 when
PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD)
and use the current setting of the operand-size attribute to determine the size
of values to be pushed from the stack, regardless of the mnemonic used.

In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD
executes: an #SS exception is generated but not delivered (the stack error reported
prevents #SS delivery). Next, the processor generates a #DF exception and enters
a shutdown state as described in the #DF discussion in Chapter 6 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

This instruction executes as described in compatibility mode and legacy mode.
It is not valid in 64-bit mode.

Operation:

IF 64-bit Mode
  THEN #UD
FI;
IF OperandSize = 32 (* PUSHAD instruction *)
  THEN
     Temp <- (ESP);
     Push(EAX);
     Push(ECX);
     Push(EDX);
     Push(EBX);
     Push(Temp);
     Push(EBP);
     Push(ESI);
     Push(EDI);
  ELSE (* OperandSize = 16, PUSHA instruction *)
     Temp <- (SP);
     Push(AX);
     Push(CX);
     Push(DX);
     Push(BX);
     Push(Temp);
     Push(BP);
     Push(SI);
     Push(DI);
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #SS(0)         | If the starting or ending stack address
|                | is outside the stack segment limit.    
| #PF(fault-code)| If a page fault occurs.                
| #AC(0)         | If an unaligned memory reference is    
|                | made while the current privilege level 
|                | is 3 and alignment checking is enabled.
| #UD            | If the LOCK prefix is used.            

Real-Address Mode Exceptions:
| #GP| If the ESP or SP register contains 7,
|    | 9, 11, 13, or 15.                    
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If the ESP or SP register contains 7,    
|                | 9, 11, 13, or 15.                        
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If an unaligned memory reference is      
|                | made while alignment checking is enabled.
| #UD            | If the LOCK prefix is used.              

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #UD| If in 64-bit mode.


platform: x86
mnem: PUSHF
description:
PUSHF/PUSHFD - Push EFLAGS Register onto the Stack:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                  
| 9C     | PUSHF      | NP   | Valid      | Valid          | Push lower 16 bits of EFLAGS.
| 9C     | PUSHFD     | NP   | N.E.       | Valid          | Push EFLAGS.                 
| 9C     | PUSHFQ     | NP   | Valid      | N.E.           | Push RFLAGS.                 

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Decrements the stack pointer by 4 (if the current operand-size attribute is
32) and pushes the entire contents of the EFLAGS register onto the stack, or
decrements the stack pointer by 2 (if the operand-size attribute is 16) and
pushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register)
onto the stack. These instructions reverse the operation of the POPF/POPFD instructions.

When copying the entire EFLAGS register to the stack, the VM and RF flags (bits
16 and 17) are not copied; instead, the values for these flags are cleared in
the EFLAGS image stored on the stack. See Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer's Manual, Volume 1, for more information about
the EFLAGS register.

The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the
same opcode. The PUSHF instruction is intended for use when the operand-size
attribute is 16 and the PUSHFD instruction for when the operand-size attribute
is 32. Some assemblers may force the operand size to 16 when PUSHF is used and
to 32 when PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD)
and use the current setting of the operand-size attribute to determine the size
of values to be pushed from the stack, regardless of the mnemonic used.

In 64-bit mode, the instruction's default operation is to decrement the stack
pointer (RSP) by 8 and pushes RFLAGS on the stack. 16-bit operation is supported
using the operand size override prefix 66H. 32-bit operand size cannot be encoded
in this mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16
and 17) are not copied; instead, values for these flags are cleared in the RFLAGS
image stored on the stack.

When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3,
the PUSHF/PUSHFD instruction causes a general protection exception (#GP).

In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruction
executes: an #SS exception is generated but not delivered (the stack error reported
prevents #SS delivery). Next, the processor generates a #DF exception and enters
a shutdown state as described in the #DF discussion in Chapter 6 of the Intel®
64 and IA-32 Architectures Software Developer's Manual, Volume 3A.

Operation:

IF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3)))
(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)
  THEN
     IF OperandSize = 32
       THEN
          push (EFLAGS AND 00FCFFFFH);
          (* VM and RF EFLAG bits are cleared in image stored on the stack *)
       ELSE
          push (EFLAGS); (* Lower 16 bits only *)
     FI;
  ELSE IF 64-bit MODE (* In 64-bit Mode *)
     IF OperandSize = 64
       THEN
          push (RFLAGS AND 00000000_00FCFFFFH);
          (* VM and RF RFLAG bits are cleared in image stored on the stack; *)
       ELSE
          push (EFLAGS); (* Lower 16 bits only *)
     FI;
  ELSE (* In Virtual-8086 Mode with IOPL less than 3 *)
     #GP(0); (* Trap to virtual-8086 monitor *)
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #SS(0)         | If the new value of the ESP register   
|                | is outside the stack segment boundary. 
| #PF(fault-code)| If a page fault occurs.                
| #AC(0)         | If an unaligned memory reference is    
|                | made while the current privilege level 
|                | is 3 and alignment checking is enabled.
| #UD            | If the LOCK prefix is used.            

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)         | If the I/O privilege level is less than  
|                | 3.                                       
| #PF(fault-code)| If a page fault occurs.                  
| #AC(0)         | If an unaligned memory reference is      
|                | made while alignment checking is enabled.
| #UD            | If the LOCK prefix is used.              

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)         | If the memory address is in a non-canonical
|                | form.                                      
| #SS(0)         | If the stack address is in a non-canonical 
|                | form.                                      
| #PF(fault-code)| If a page fault occurs.                    
| #AC(0)         | If an unaligned memory reference is        
|                | made while the current privilege level     
|                | is 3 and alignment checking is enabled.    
| #UD            | If the LOCK prefix is used.                


platform: x86
mnem: PXOR
description:
PXOR - Logical Exclusive OR:
| Opcode*/Instruction                    | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                       
| 0F EF /r1 PXOR mm, mm/m64              | RM   | V/V                   | MMX               | Bitwise XOR of mm/m64 and mm.     
| 66 0F EF /r PXOR xmm1, xmm2/m128       | RM   | V/V                   | SSE2              | Bitwise XOR of xmm2/m128 and xmm1.
| VEX.NDS.128.66.0F.WIG EF /r VPXOR xmm1,| RVM  | V/V                   | AVX               | Bitwise XOR of xmm3/m128 and xmm2.
| xmm2, xmm3/m128                        |      |                       |                   |                                   
| VEX.NDS.256.66.0F.WIG EF /r VPXOR ymm1,| RVM  | V/V                   | AVX2              | Bitwise XOR of ymm3/m256 and ymm2.
| ymm2, ymm3/m256                        |      |                       |                   |                                   
Notes: 1. See note in Section 2.4, “Instruction Exception Specification” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A
and Section 22.25.3, “Exception Conditions of Legacy SIMD Instructions Operating
on MMX Registers” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A.


Instruction Operand Encoding:
| Op/En| Operand 1       | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (r, w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)   | VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Performs a bitwise logical exclusive-OR (XOR) operation on the source operand
(second operand) and the destination operand (first operand) and stores the
result in the destination operand. Each bit of the result is 1 if the corresponding
bits of the two operands are different; each bit is 0 if the corresponding bits
of the operands are the same.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15).

Legacy SSE instructions: The source operand can be an MMX technology register
or a 64-bit memory location. The destination operand is an MMX technology register.
128-bit Legacy SSE version: The second source operand is an XMM register or
a 128-bit memory location. The first source operand and destination operands
are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged. VEX.128 encoded version: The second source operand is an XMM
register or a 128-bit memory location. The first source operand and destination
operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed. VEX.256 encoded version: The second source operand is an YMM register
or a 256-bit memory location. The first source operand and destination operands
are YMM registers.

Note: VEX.L must be 0, otherwise instructions will #UD.

Operation:

PXOR (128-bit Legacy SSE version)
DEST <- DEST XOR SRC
DEST[VLMAX-1:128] (Unmodified)
VPXOR (VEX.128 encoded version)
DEST <- SRC1 XOR SRC2
DEST[VLMAX-1:128] <- 0
VPXOR (VEX.256 encoded version)
DEST <- SRC1 XOR SRC2

Intel C/C++ Compiler Intrinsic Equivalent:
| PXOR:   | __m64 _mm_xor_si64 (__m64 m1, __m64       
|         | m2)                                       
| (V)PXOR:| __m128i _mm_xor_si128 ( __m128i a, __m128i
|         | b)                                        
| VPXOR:  | __m256i _mm256_xor_si256 ( __m256i a,     
|         | __m256i b)                                

Flags Affected:
None.


Numeric Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.L = 1.


platform: x86
mnem: RCL
description:
RCL/RCR/ROL/ROR- - Rotate:
| Opcode**        | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| D0 /2           | RCL r/m8, 1    | M1   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) left once.      
| REX + D0 /2     | RCL r/m8*, 1   | M1   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) left once.      
| D2 /2           | RCL r/m8, CL   | MC   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) left CL times.  
| REX + D2 /2     | RCL r/m8*, CL  | MC   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) left CL times.  
| C0 /2 ib        | RCL r/m8, imm8 | MI   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) left imm8 times.
| REX + C0 /2 ib  | RCL r/m8*, imm8| MI   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) left imm8 times.
| D1 /2           | RCL r/m16, 1   | M1   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) left once.    
| D3 /2           | RCL r/m16, CL  | MC   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) left CL times.
| C1 /2 ib        | RCL r/m16, imm8| MI   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) left imm8     
|                 |                |      |            |                | times.                                   
| D1 /2           | RCL r/m32, 1   | M1   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) left once.    
| REX.W + D1 /2   | RCL r/m64, 1   | M1   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) left once.    
|                 |                |      |            |                | Uses a 6 bit count.                      
| D3 /2           | RCL r/m32, CL  | MC   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) left CL times.
| REX.W + D3 /2   | RCL r/m64, CL  | MC   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) left CL times.
|                 |                |      |            |                | Uses a 6 bit count.                      
| C1 /2 ib        | RCL r/m32, imm8| MI   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) left imm8     
|                 |                |      |            |                | times.                                   
| REX.W + C1 /2 ib| RCL r/m64, imm8| MI   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) left imm8     
|                 |                |      |            |                | times. Uses a 6 bit count.               
| D0 /3           | RCR r/m8, 1    | M1   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) right once.     
| REX + D0 /3     | RCR r/m8*, 1   | M1   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) right once.     
| D2 /3           | RCR r/m8, CL   | MC   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) right CL times. 
| REX + D2 /3     | RCR r/m8*, CL  | MC   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) right CL times. 
| C0 /3 ib        | RCR r/m8, imm8 | MI   | Valid      | Valid          | Rotate 9 bits (CF, r/m8) right imm8      
|                 |                |      |            |                | times.                                   
| REX + C0 /3 ib  | RCR r/m8*, imm8| MI   | Valid      | N.E.           | Rotate 9 bits (CF, r/m8) right imm8      
|                 |                |      |            |                | times.                                   
| D1 /3           | RCR r/m16, 1   | M1   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) right once.   
| D3 /3           | RCR r/m16, CL  | MC   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) right CL      
|                 |                |      |            |                | times.                                   
| C1 /3 ib        | RCR r/m16, imm8| MI   | Valid      | Valid          | Rotate 17 bits (CF, r/m16) right imm8    
|                 |                |      |            |                | times.                                   
| D1 /3           | RCR r/m32, 1   | M1   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) right once.   
|                 |                |      |            |                | Uses a 6 bit count.                      
| REX.W + D1 /3   | RCR r/m64, 1   | M1   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) right once.   
|                 |                |      |            |                | Uses a 6 bit count.                      
| D3 /3           | RCR r/m32, CL  | MC   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) right CL      
|                 |                |      |            |                | times.                                   
| REX.W + D3 /3   | RCR r/m64, CL  | MC   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) right CL      
|                 |                |      |            |                | times. Uses a 6 bit count.               
| C1 /3 ib        | RCR r/m32, imm8| MI   | Valid      | Valid          | Rotate 33 bits (CF, r/m32) right imm8    
|                 |                |      |            |                | times.                                   
| REX.W + C1 /3 ib| RCR r/m64, imm8| MI   | Valid      | N.E.           | Rotate 65 bits (CF, r/m64) right imm8    
|                 |                |      |            |                | times. Uses a 6 bit count.               
| D0 /0           | ROL r/m8, 1    | M1   | Valid      | Valid          | Rotate 8 bits r/m8 left once.            
| REX + D0 /0     | ROL r/m8*, 1   | M1   | Valid      | N.E.           | Rotate 8 bits r/m8 left once             
| D2 /0           | ROL r/m8, CL   | MC   | Valid      | Valid          | Rotate 8 bits r/m8 left CL times.        
| REX + D2 /0     | ROL r/m8*, CL  | MC   | Valid      | N.E.           | Rotate 8 bits r/m8 left CL times.        
| C0 /0 ib        | ROL r/m8, imm8 | MI   | Valid      | Valid          | Rotate 8 bits r/m8 left imm8 times.      
| Opcode**        | Instruction    | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| REX + C0 /0 ib  | ROL r/m8*, imm8| MI   | Valid      | N.E.           | Rotate 8 bits r/m8 left imm8 times.      
| D1 /0           | ROL r/m16, 1   | M1   | Valid      | Valid          | Rotate 16 bits r/m16 left once.          
| D3 /0           | ROL r/m16, CL  | MC   | Valid      | Valid          | Rotate 16 bits r/m16 left CL times.      
| C1 /0 ib        | ROL r/m16, imm8| MI   | Valid      | Valid          | Rotate 16 bits r/m16 left imm8 times.    
| D1 /0           | ROL r/m32, 1   | M1   | Valid      | Valid          | Rotate 32 bits r/m32 left once.          
| REX.W + D1 /0   | ROL r/m64, 1   | M1   | Valid      | N.E.           | Rotate 64 bits r/m64 left once. Uses     
|                 |                |      |            |                | a 6 bit count.                           
| D3 /0           | ROL r/m32, CL  | MC   | Valid      | Valid          | Rotate 32 bits r/m32 left CL times.      
| REX.W + D3 /0   | ROL r/m64, CL  | MC   | Valid      | N.E.           | Rotate 64 bits r/m64 left CL times.      
|                 |                |      |            |                | Uses a 6 bit count.                      
| C1 /0 ib        | ROL r/m32, imm8| MI   | Valid      | Valid          | Rotate 32 bits r/m32 left imm8 times.    
| REX.W + C1 /0 ib| ROL r/m64, imm8| MI   | Valid      | N.E.           | Rotate 64 bits r/m64 left imm8 times.    
|                 |                |      |            |                | Uses a 6 bit count.                      
| D0 /1           | ROR r/m8, 1    | M1   | Valid      | Valid          | Rotate 8 bits r/m8 right once.           
| REX + D0 /1     | ROR r/m8*, 1   | M1   | Valid      | N.E.           | Rotate 8 bits r/m8 right once.           
| D2 /1           | ROR r/m8, CL   | MC   | Valid      | Valid          | Rotate 8 bits r/m8 right CL times.       
| REX + D2 /1     | ROR r/m8*, CL  | MC   | Valid      | N.E.           | Rotate 8 bits r/m8 right CL times.       
| C0 /1 ib        | ROR r/m8, imm8 | MI   | Valid      | Valid          | Rotate 8 bits r/m16 right imm8 times.    
| REX + C0 /1 ib  | ROR r/m8*, imm8| MI   | Valid      | N.E.           | Rotate 8 bits r/m16 right imm8 times.    
| D1 /1           | ROR r/m16, 1   | M1   | Valid      | Valid          | Rotate 16 bits r/m16 right once.         
| D3 /1           | ROR r/m16, CL  | MC   | Valid      | Valid          | Rotate 16 bits r/m16 right CL times.     
| C1 /1 ib        | ROR r/m16, imm8| MI   | Valid      | Valid          | Rotate 16 bits r/m16 right imm8 times.   
| D1 /1           | ROR r/m32, 1   | M1   | Valid      | Valid          | Rotate 32 bits r/m32 right once.         
| REX.W + D1 /1   | ROR r/m64, 1   | M1   | Valid      | N.E.           | Rotate 64 bits r/m64 right once. Uses    
|                 |                |      |            |                | a 6 bit count.                           
| D3 /1           | ROR r/m32, CL  | MC   | Valid      | Valid          | Rotate 32 bits r/m32 right CL times.     
| REX.W + D3 /1   | ROR r/m64, CL  | MC   | Valid      | N.E.           | Rotate 64 bits r/m64 right CL times.     
|                 |                |      |            |                | Uses a 6 bit count.                      
| C1 /1 ib        | ROR r/m32, imm8| MI   | Valid      | Valid          | Rotate 32 bits r/m32 right imm8 times.   
| REX.W + C1 /1 ib| ROR r/m64, imm8| MI   | Valid      | N.E.           | Rotate 64 bits r/m64 right imm8 times.   
|                 |                |      |            |                | Uses a 6 bit count.                      
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH. ** See IA-32 Architecture
Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M1   | ModRM:r/m (w)| 1        | NA       | NA       
| MC   | ModRM:r/m (w)| CL       | NA       | NA       
| MI   | ModRM:r/m (w)| imm8     | NA       | NA       

Description:
Shifts (rotates) the bits of the first operand (destination operand) the number
of bit positions specified in the second operand (count operand) and stores
the result in the destination operand. The destination operand can be a register
or a memory location; the count operand is an unsigned integer that can be an
immediate or a value in the CL register. In legacy and compatibility mode, the
processor restricts the count to a number between 0 and 31 by masking all the
bits in the count operand except the 5 least-significant bits.

The rotate left (ROL) and rotate through carry left (RCL) instructions shift
all the bits toward more-significant bit positions, except for the most-significant
bit, which is rotated to the least-significant bit location. The rotate right
(ROR) and rotate through carry right (RCR) instructions shift all the bits toward
less significant bit positions, except for the least-significant bit, which
is rotated to the most-significant bit location.

The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction
shifts the CF flag into the least-significant bit and shifts the most-significant
bit into the CF flag. The RCR instruction shifts the CF flag into the most-significant
bit and shifts the least-significant bit into the CF flag. For the ROL and ROR
instructions, the original value of the CF flag is not a part of the result,
but the CF flag receives a copy of the bit that was shifted from one end to
the other.

The OF flag is defined only for the 1-bit rotates; it is undefined in all other
cases (except RCL and RCR instructions only: a zero-bit rotate does nothing,
that is affects no flags). For left rotates, the OF flag is set to the exclusive
OR of the CF bit (after the rotate) and the most-significant bit of the result.
For right rotates, the OF flag is set to the exclusive OR of the two most-significant
bits of the result.

In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional
registers (R8-R15). Use of REX.W promotes the first operand to 64 bits and causes
the count operand to become a 6-bit counter.


IA-32 Architecture Compatibility:
The 8086 does not mask the rotation count. However, all other IA-32 processors
(starting with the Intel 286 processor) do mask the rotation count to 5 bits,
resulting in a maximum count of 31. This masking is done in all operating modes
(including the virtual-8086 mode) to reduce the maximum execution time of the
instructions.

Operation:

(* RCL and RCR instructions *)
SIZE <- OperandSize;
CASE (determine count) OF
  SIZE <- 8:
  SIZE <- 16:
  SIZE <- 32:
  SIZE <- 64:
ESAC;
(* RCL instruction operation *)
WHILE (tempCOUNT != 0)
  DO
     tempCF <- MSB(DEST);
     DEST <- (DEST * 2) + CF;
     CF <- tempCF;
     tempCOUNT <- tempCOUNT - 1;
  OD;
ELIHW;
IF COUNT = 1
  THEN OF <- MSB(DEST) XOR CF;
  ELSE OF is undefined;
FI;
(* RCR instruction operation *)
IF COUNT = 1
  THEN OF <- MSB(DEST) XOR CF;
  ELSE OF is undefined;
FI;
WHILE (tempCOUNT != 0)
  DO
     tempCF <- LSB(SRC);
     DEST <- (DEST / 2) + (CF * 2SIZE);
     CF <- tempCF;
     tempCOUNT <- tempCOUNT - 1;
  OD;
(* ROL and ROR instructions *)
IF OperandSize = 64
  THEN COUNTMASK = 3FH;
  ELSE COUNTMASK = 1FH;
FI;
(* ROL instruction operation *)
tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE
WHILE (tempCOUNT != 0)
  DO
     tempCF <- MSB(DEST);
     DEST <- (DEST * 2) + tempCF;
     tempCOUNT <- tempCOUNT - 1;
  OD;
ELIHW;
CF <- LSB(DEST);
IF (COUNT & COUNTMASK) = 1
  THEN OF <- MSB(DEST) XOR CF;
  ELSE OF is undefined;
FI;
(* ROR instruction operation *)
tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE
WHILE (tempCOUNT != 0)
  DO
     tempCF <- LSB(SRC);
     DEST <- (DEST / 2) + (tempCF * 2SIZE);
     tempCOUNT <- tempCOUNT - 1;
  OD;
ELIHW;
CF <- MSB(DEST);
IF (COUNT & COUNTMASK) = 1
  THEN OF <- MSB(DEST) XOR MSB − 1(DEST);
  ELSE OF is undefined;
FI;

Flags Affected:
The CF flag contains the value of the bit shifted into it. The OF flag is affected
only for single-bit rotates (see “Description” above); it is undefined for multi-bit
rotates. The SF, ZF, AF, and PF flags are not affected.


Protected Mode Exceptions:
| #GP(0)         | If the source operand is located in       
|                | a non-writable segment. If a memory       
|                | operand effective address is outside      
|                | the CS, DS, ES, FS, or GS segment limit.  
|                | If the DS, ES, FS, or GS register contains
|                | a NULL segment selector.                  
| #SS(0)         | If a memory operand effective address     
|                | is outside the SS segment limit.          
| #PF(fault-code)| If a page fault occurs.                   
| #AC(0)         | If alignment checking is enabled and      
|                | an unaligned memory reference is made     
|                | while the current privilege level is      
|                | 3.                                        
| #UD            | If the LOCK prefix is used.               

Real-Address Mode Exceptions:
| #GP| If a memory operand effective address
|    | is outside the CS, DS, ES, FS, or GS 
|    | segment limit.                       
| #SS| If a memory operand effective address
|    | is outside the SS segment limit.     
| #UD| If the LOCK prefix is used.          

Virtual-8086 Mode Exceptions:
| #GP(0)         | If a memory operand effective address 
|                | is outside the CS, DS, ES, FS, or GS  
|                | segment limit.                        
| #SS(0)         | If a memory operand effective address 
|                | is outside the SS segment limit.      
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made.
| #UD            | If the LOCK prefix is used.           

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #SS(0)         | If a memory address referencing the   
|                | SS segment is in a non-canonical form.
| #GP(0)         | If the source operand is located in   
|                | a nonwritable segment. If the memory  
|                | address is in a non-canonical form.   
| #PF(fault-code)| If a page fault occurs.               
| #AC(0)         | If alignment checking is enabled and  
|                | an unaligned memory reference is made 
|                | while the current privilege level is  
|                | 3.                                    
| #UD            | If the LOCK prefix is used.           


platform: x86
mnem: RCPPS
description:
RCPPS - Compute Reciprocals of Packed Single-Precision Floating-Point Values:
| Opcode*/Instruction                        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                  
| 0F 53 /r RCPPS xmm1, xmm2/m128             | RM   | V/V                   | SSE               | Computes the approximate reciprocals         
|                                            |      |                       |                   | of the packed single-precision floating-point
|                                            |      |                       |                   | values in xmm2/m128 and stores the results   
|                                            |      |                       |                   | in xmm1.                                     
| VEX.128.0F.WIG 53 /r VRCPPS xmm1, xmm2/m128| RM   | V/V                   | AVX               | Computes the approximate reciprocals         
|                                            |      |                       |                   | of packed single-precision values in         
|                                            |      |                       |                   | xmm2/mem and stores the results in xmm1.     
| VEX.256.0F.WIG 53 /r VRCPPS ymm1, ymm2/m256| RM   | V/V                   | AVX               | Computes the approximate reciprocals         
|                                            |      |                       |                   | of packed single-precision values in         
|                                            |      |                       |                   | ymm2/mem and stores the results in ymm1.     

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3| Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA       | NA       

Description:
Performs a SIMD computation of the approximate reciprocals of the four packed
single-precision floating-point values in the source operand (second operand)
stores the packed single-precision floating-point results in the destination
operand. The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Figure 10-5 in the Intel® 64
and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration
of a SIMD single-precision floating-point operation.

The relative error for this approximation is:

|Relative Error| ≤ 1.5 * 2−12

The RCPPS instruction is not affected by the rounding control bits in the MXCSR
register. When a source value is a 0.0, an ∞ of the sign of the source value
is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results are always flushed to 0.0, with the sign of the operand. (Input
values greater than or equal to |1.11111111110100000000000B*2125| are guaranteed
to not produce tiny results; input values less than or equal to |1.00000000000110000000001B*2126|
are guaranteed to produce tiny results, which are in turn flushed to 0.0; and
input values in between this range may or may not produce tiny results, depending
on the implementation.) When a source value is an SNaN or QNaN, the SNaN is
converted to a QNaN or the source QNaN is returned.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
second source can be an XMM register or an 128-bit memory location. The destination
is not distinct from the first source XMM register and the upper bits (VLMAX-1:128)
of the corresponding YMM register destination are unmodified. VEX.128 encoded
version: the first source operand is an XMM register or 128-bit memory location.
The destination operand is an XMM register. The upper bits (VLMAX-1:128) of
the corresponding YMM register destination are zeroed. VEX.256 encoded version:
The first source operand is a YMM register. The second source operand can be
a YMM register or a 256-bit memory location. The destination operand is a YMM
register. Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b,
otherwise instructions will #UD.

Operation:

RCPPS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] (Unmodified)
VRCPPS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] <- 0
VRCPPS (VEX.256 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[159:128] <- APPROXIMATE(1/SRC[159:128])
DEST[191:160] <- APPROXIMATE(1/SRC[191:160])
DEST[223:192] <- APPROXIMATE(1/SRC[223:192])
DEST[255:224] <- APPROXIMATE(1/SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalent:
| RCCPS:| __m128 _mm_rcp_ps(__m128 a)     
| RCPPS:| __m256 _mm256_rcp_ps (__m256 a);

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 4; additionally

| #UD| If VEX.vvvv != 1111B.


platform: x86
mnem: RCPSS
description:
RCPSS - Compute Reciprocal of Scalar Single-Precision Floating-Point Values:
| Opcode*/Instruction                     | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                                  
| F3 0F 53 /r RCPSS xmm1, xmm2/m32        | RM   | V/V                   | SSE               | Computes the approximate reciprocal          
|                                         |      |                       |                   | of the scalar single-precision floating-point
|                                         |      |                       |                   | value in xmm2/m32 and stores the result      
|                                         |      |                       |                   | in xmm1.                                     
| VEX.NDS.LIG.F3.0F.WIG 53 /r VRCPSS xmm1,| RVM  | V/V                   | AVX               | Computes the approximate reciprocal          
| xmm2, xmm3/m32                          |      |                       |                   | of the scalar single-precision floating-point
|                                         |      |                       |                   | value in xmm3/m32 and stores the result      
|                                         |      |                       |                   | in xmm1. Also, upper single precision        
|                                         |      |                       |                   | floating-point values (bits[127:32])         
|                                         |      |                       |                   | from xmm2 are copied to xmm1[127:32].        

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2    | Operand 3    | Operand 4
| RM   | ModRM:reg (w)| ModRM:r/m (r)| NA           | NA       
| RVM  | ModRM:reg (w)| VEX.vvvv (r) | ModRM:r/m (r)| NA       

Description:
Computes of an approximate reciprocal of the low single-precision floating-point
value in the source operand (second operand) and stores the single-precision
floating-point result in the destination operand. The source operand can be
an XMM register or a 32-bit memory location. The destination operand is an XMM
register. The three high-order doublewords of the destination operand remain
unchanged. See Figure 10-6 in the Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for an illustration of a scalar single-precision
floatingpoint operation.

The relative error for this approximation is:

|Relative Error| ≤ 1.5 * 2−12

The RCPSS instruction is not affected by the rounding control bits in the MXCSR
register. When a source value is a 0.0, an ∞ of the sign of the source value
is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results are always flushed to 0.0, with the sign of the operand. (Input
values greater than or equal to |1.11111111110100000000000B*2125| are guaranteed
to not produce tiny results; input values less than or equal to |1.00000000000110000000001B*2126|
are guaranteed to produce tiny results, which are in turn flushed to 0.0; and
input values in between this range may or may not produce tiny results, depending
on the implementation.) When a source value is an SNaN or QNaN, the SNaN is
converted to a QNaN or the source QNaN is returned.

In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction
to access additional registers (XMM8-XMM15). 128-bit Legacy SSE version: The
first source operand and the destination operand are the same. Bits (VLMAX1:32)
of the corresponding YMM destination register remain unchanged. VEX.128 encoded
version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation:

RCPSS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[VLMAX-1:32] (Unmodified)
VRCPSS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC2[31:0])
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent:
| RCPSS:| __m128 _mm_rcp_ss(__m128 a)

SIMD Floating-Point Exceptions:
None.


Other Exceptions:
See Exceptions Type 5.


platform: x86
mnem: RDFSBASE
description:
RDFSBASE/RDGSBASE - Read FS/GS Segment Base:
| Opcode/Instruction              | Op/En| 64/32bit Mode| CPUID Feature Flag| Description                         
| F3 0F AE /0 RDFSBASE r32        | M    | V/I          | FSGSBASE          | Load the 32-bit destination register
|                                 |      |              |                   | with the FS base address.           
| REX.W + F3 0F AE /0 RDFSBASE r64| M    | V/I          | FSGSBASE          | Load the 64-bit destination register
|                                 |      |              |                   | with the FS base address.           
| F3 0F AE /1 RDGSBASE r32        | M    | V/I          | FSGSBASE          | Load the 32-bit destination register
|                                 |      |              |                   | with the GS base address.           
| REX.W + F3 0F AE /1 RDGSBASE r64| M    | V/I          | FSGSBASE          | Load the 64-bit destination register
|                                 |      |              |                   | with the GS base address.           

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Loads the general-purpose register indicated by the modR/M:r/m field with the
FS or GS segment base address.

The destination operand may be either a 32-bit or a 64-bit general-purpose register.
The REX.W prefix indicates the operand size is 64 bits. If no REX.W prefix is
used, the operand size is 32 bits; the upper 32 bits of the source base address
(for FS or GS) are ignored and upper 32 bits of the destination register are
cleared. This instruction is supported only in 64-bit mode.

Operation:

DEST <- FS/GS segment base address;

Flags Affected:
None


C/C++ Compiler Intrinsic Equivalent:
| RDFSBASE:| unsigned int _readfsbase_u32(void ); 
| RDFSBASE:| unsigned __int64 _readfsbase_u64(void
|          | );                                   
| RDGSBASE:| unsigned int _readgsbase_u32(void ); 
| RDGSBASE:| unsigned __int64 _readgsbase_u64(void
|          | );                                   

Protected Mode Exceptions:
| #UD| The RDFSBASE and RDGSBASE instructions
|    | are not recognized in protected mode. 

Real-Address Mode Exceptions:
| #UD| The RDFSBASE and RDGSBASE instructions  
|    | are not recognized in real-address mode.

Virtual-8086 Mode Exceptions:
| #UD| The RDFSBASE and RDGSBASE instructions  
|    | are not recognized in virtual-8086 mode.

Compatibility Mode Exceptions:
| #UD| The RDFSBASE and RDGSBASE instructions
|    | are not recognized in compatibility   
|    | mode.                                 

64-Bit Mode Exceptions:
| #UD| If the LOCK prefix is used. If CR4.FSGSBASE[bit
|    | 16] = 0. If CPUID.07H.0H:EBX.FSGSBASE[bit      
|    | 0] = 0.                                        


platform: x86
mnem: RDMSR
description:
RDMSR - Read from Model Specific Register:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                            
| 0F 32  | RDMSR      | NP   | Valid      | Valid          | Read MSR specified by ECX into EDX:EAX.
Notes: * See IA-32 Architecture Compatibility section below.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Reads the contents of a 64-bit model specific register (MSR) specified in the
ECX register into registers EDX:EAX. (On processors that support the Intel 64
architecture, the high-order 32 bits of RCX are ignored.) The EDX register is
loaded with the high-order 32 bits of the MSR and the EAX register is loaded
with the low-order 32 bits. (On processors that support the Intel 64 architecture,
the high-order 32 bits of each of RAX and RDX are cleared.) If fewer than 64
bits are implemented in the MSR being read, the values returned to EDX:EAX in
unimplemented bit locations are undefined.

This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) will be generated. Specifying
a reserved or unimplemented MSR address in ECX will also cause a general protection
exception.

The MSRs control functions for testability, execution tracing, performance-monitoring,
and machine check errors. Chapter 35, “Model-Specific Registers (MSRs),” in
the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3C,
lists all the MSRs that can be read with this instruction and their addresses.
Note that each processor family has its own set of MSRs.

The CPUID instruction should be used to determine whether MSRs are supported
(CPUID.01H:EDX[5] = 1) before using this instruction.


IA-32 Architecture Compatibility:
The MSRs and the ability to read them with the RDMSR instruction were introduced
into the IA-32 Architecture with the Pentium processor. Execution of this instruction
by an IA-32 processor earlier than the Pentium processor results in an invalid
opcode exception #UD.

See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25
of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3C, for more information about the behavior of this instruction in VMX non-root
operation.

Operation:

EDX:EAX <- MSR[ECX];

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not      
|       | 0. If the value in ECX specifies a reserved
|       | or unimplemented MSR address.              
| #UD   | If the LOCK prefix is used.                

Real-Address Mode Exceptions:
| #GP| If the value in ECX specifies a reserved
|    | or unimplemented MSR address.           
| #UD| If the LOCK prefix is used.             

Virtual-8086 Mode Exceptions:
| #GP(0)| The RDMSR instruction is not recognized
|       | in virtual-8086 mode.                  

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: RDPMC
description:
RDPMC - Read Performance-Monitoring Counters:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                        
| 0F 33  | RDPMC      | NP   | Valid      | Valid          | Read performance-monitoring counter
|        |            |      |            |                | specified by ECX into EDX:EAX.     

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
The EAX register is loaded with the low-order 32 bits. The EDX register is loaded
with the supported high-order bits of the counter. The number of high-order
bits loaded into EDX is implementation specific on processors that do no support
architectural performance monitoring. The width of fixed-function and general-purpose
performance counters on processors supporting architectural performance monitoring
are reported by CPUID 0AH leaf. See below for the treatment of the EDX register
for “fast” reads.

The ECX register selects one of two type of performance counters, specifies
the index relative to the base of each counter type, and selects “fast” read
mode if supported. The two counter types are :

 - General-purpose or special-purpose performance counters: The number of general-purpose
counters is model specific if the processor does not support architectural performance
monitoring, see Chapter 30 of Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B. Special-purpose counters are available only in selected processor
members, see Section 30.13, 30.14 of Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 3B. This counter type is selected if ECX[30] is clear.
 - Fixed-function performance counter. The number fixed-function performance counters
is enumerated by CPUID 0AH leaf. See Chapter 30 of Intel® 64 and IA-32 Architectures
Software Developer's Manual, Volume 3B. This counter type is selected if ECX[30]
is set.

ECX[29:0] specifies the index. The width of general-purpose performance counters
are 40-bits for processors that do not support architectural performance monitoring
counters.The width of special-purpose performance counters are implementation
specific. The width of fixed-function performance counters and general-purpose
performance counters on processor supporting architectural performance monitoring
are reported by CPUID 0AH leaf.

Table 4-12 lists valid indices of the general-purpose and special-purpose performance
counters according to the derived DisplayFamily_DisplayModel values of CPUID
encoding for each processor family (see CPUID instruction in Chapter 3, “Instruction
Set Reference, A-M” in the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 2A).


Table 4-12. Valid General and Special Purpose Performance Counter Index Range for RDPMC:
| Processor Family                            | DisplayFamily_DisplayModel/Other Signatures| Valid PMC Index Range| General-purpose Counters
| P6                                          | 06H_01H, 06H_03H, 06H_05H, 06H_06H,        | 0, 1                 | 0, 1                    
|                                             | 06H_07H, 06H_08H, 06H_0AH, 06H_0BH         |                      |                         
| Pentium® 4, Intel® Xeon processors          | 0FH_00H, 0FH_01H, 0FH_02H                  | ≥ 0 and ≤ 17         | ≥ 0 and ≤ 17            
| Pentium 4, Intel Xeon processors            | (0FH_03H, 0FH_04H, 0FH_06H) and (L3        | ≥ 0 and ≤ 17         | ≥ 0 and ≤ 17            
|                                             | is absent)                                 |                      |                         
| Pentium M processors                        | 06H_09H, 06H_0DH                           | 0, 1                 | 0, 1                    
| 64-bit Intel Xeon processors with L3        | 0FH_03H, 0FH_04H) and (L3 is present)      | ≥ 0 and ≤ 25         | ≥ 0 and ≤ 17            
| Intel® Core™ Solo and Intel® Core™ Duo      | 06H_0EH Valid General and Special Purpose  | 0, 1                 | 0, 1                    
| processors, Dual-core Intel® Xeon® processor| Performance Counter Index Range for        |                      |                         
| LV Table 4-12.                              | RDPMC (Contd.)                             |                      |                         
| Processor Family                            | DisplayFamily_DisplayModel/Other Signatures| Valid PMC Index Range| General-purpose Counters
| Intel® Core™2 Duo processor, Intel Xeon     | 06H_0FH                                    | 0, 1                 | 0, 1                    
| processor                                   |                                            |                      |                         
3000, 5100, 5300, 7300 Series - general-purpose PMC

| Intel Xeon processors 7100 series with       | (0FH_06H) and (L3 is present)     | ≥ 0 and ≤ 25| ≥ 0 and ≤ 17
| L3                                           |                                   |             |             
| Intel® Core™2 Duo processor family,          | 06H_17H                           | 0, 1        | 0, 1        
| Intel Xeon processor family - general-purpose|                                   |             |             
| PMC                                          |                                   |             |             
| Intel Xeon processors 7400 series            | (06H_1DH)                         | ≥ 0 and ≤ 9 | 0, 1        
| Intel® Atom™ processor family                | 06H_1CH                           | 0, 1        | 0, 1        
| Intel® Core™i7 processor, Intel Xeon         | 06H_1AH, 06H_1EH, 06H_1FH, 06H_2EH| 0-3         | 0, 1, 2, 3  
| processors 5500 series                       |                                   |             |             
The Pentium 4 and Intel Xeon processors also support “fast” (32-bit) and “slow”
(40-bit) reads on the first 18 performance counters. Selected this option using
ECX[31]. If bit 31 is set, RDPMC reads only the low 32 bits of the selected
performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result
is returned in EAX and EDX is set to 0. A 32-bit read executes faster on Pentium
4 processors and Intel Xeon processors than a full 40-bit read.

On 64-bit Intel Xeon processors with L3, performance counters with indices 18-25
are 32-bit counters. EDX is cleared after executing RDPMC for these counters.
On Intel Xeon processor 7100 series with L3, performance counters with indices
18-25 are also 32-bit counters.

In Intel Core 2 processor family, Intel Xeon processor 3000, 5100, 5300 and
7400 series, the fixed-function performance counters are 40-bits wide; they
can be accessed by RDMPC with ECX between from 4000_0000H and 4000_0002H.

On Intel Xeon processor 7400 series, there are eight 32-bit special-purpose
counters addressable with indices 2-9, ECX[30]=0.

When in protected or virtual 8086 mode, the performance-monitoring counters
enabled (PCE) flag in register CR4 restricts the use of the RDPMC instruction
as follows. When the PCE flag is set, the RDPMC instruction can be executed
at any privilege level; when the flag is clear, the instruction can only be
executed at privilege level 0. (When in real-address mode, the RDPMC instruction
is always enabled.)

The performance-monitoring counters can also be read with the RDMSR instruction,
when executing at privilege level 0.

The performance-monitoring counters are event counters that can be programmed
to count events such as the number of instructions decoded, number of interrupts
received, or number of cache loads. Chapter 19, “Performance Monitoring Events,”
in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3B, lists the events that can be counted for various processors in the Intel
64 and IA-32 architecture families.

The RDPMC instruction is not a serializing instruction; that is, it does not
imply that all the events caused by the preceding instructions have been completed
or that events caused by subsequent instructions have not begun. If an exact
event count is desired, software must insert a serializing instruction (such
as the CPUID instruction) before and/or after the RDPMC instruction.

In the Pentium 4 and Intel Xeon processors, performing back-to-back fast reads
are not guaranteed to be monotonic. To guarantee monotonicity on back-to-back
reads, a serializing instruction must be placed between the two RDPMC instructions.

The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086
mode; however, the full contents of the ECX register are used to select the
counter, and the event count is stored in the full EAX and EDX registers. The
RDPMC instruction was introduced into the IA-32 Architecture in the Pentium
Pro processor and the Pentium processor with MMX technology. The earlier Pentium
processors have performance-monitoring counters, but they must be read with
the RDMSR instruction.

Operation:

(* Intel Core i7 processor family and Intel Xeon processor 3400, 5500 series*)
Most significant counter bit (MSCB) = 47
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
  THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
     EAX <- IA32_FIXED_CTR(ECX)[30:0];
     EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];
  ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
     EAX <- PMC(ECX[30:0])[31:0];
     EDX <- PMC(ECX[30:0])[MSCB:32];
  ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
     #GP(0);
FI;
(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300, 7400 series*)
Most significant counter bit (MSCB) = 39
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
  THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
     EAX <- IA32_FIXED_CTR(ECX)[30:0];
     EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];
  ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
     EAX <- PMC(ECX[30:0])[31:0];
     EDX <- PMC(ECX[30:0])[MSCB:32];
  ELSE IF (ECX[30] = 0 and ECX[29:0] in valid special-purpose counter range)
     EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
  ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
     #GP(0);
FI;
(* P6 family processors and Pentium processor with MMX technology *)
IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
  THEN
     EAX <- PMC(ECX)[31:0];
     EDX <- PMC(ECX)[39:32];
  ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
     #GP(0);
FI;
(* Processors with CPUID family 15 *)
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
  THEN IF (ECX[30:0] = 0:17)
     THEN IF ECX[31] = 0
       THEN
          EAX <- PMC(ECX[30:0])[31:0]; (* 40-bit read *)
          EDX <- PMC(ECX[30:0])[39:32];
     ELSE (* ECX[31] = 1*)
       THEN
          EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
          EDX <- 0;
     FI;
  ELSE IF (*64-bit Intel Xeon processor with L3 *)
     THEN IF (ECX[30:0] = 18:25 )
       EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
       EDX <- 0;
     FI;
  ELSE IF (*Intel Xeon processor 7100 series with L3 *)
     THEN IF (ECX[30:0] = 18:25 )
       EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
       EDX <- 0;
     FI;
  ELSE (* Invalid PMC index in ECX[30:0], see Table 4-15. *)
     GP(0);
  FI;
ELSE
  #GP(0);
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the current privilege level is not       
|       | 0 and the PCE flag in the CR4 register      
|       | is clear. If an invalid performance         
|       | counter index is specified (see Table       
|       | 4-12). (Pentium 4 and Intel Xeon processors)
|       | If the value in ECX[30:0] is not within     
|       | the valid range.                            
| #UD   | If the LOCK prefix is used.                 

Real-Address Mode Exceptions:
| #GP| If an invalid performance counter index
|    | is specified (see Table 4-12). (Pentium
|    | 4 and Intel Xeon processors) If the    
|    | value in ECX[30:0] is not within the   
|    | valid range.                           
| #UD| If the LOCK prefix is used.            

Virtual-8086 Mode Exceptions:
| #GP(0)| If the PCE flag in the CR4 register         
|       | is clear. If an invalid performance         
|       | counter index is specified (see Table       
|       | 4-12). (Pentium 4 and Intel Xeon processors)
|       | If the value in ECX[30:0] is not within     
|       | the valid range.                            
| #UD   | If the LOCK prefix is used.                 

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
| #GP(0)| If the current privilege level is not  
|       | 0 and the PCE flag in the CR4 register 
|       | is clear. If an invalid performance    
|       | counter index is specified in ECX[30:0]
|       | (see Table 4-12).                      
| #UD   | If the LOCK prefix is used.            


platform: x86
mnem: RDRAND
description:
RDRAND - Read Random Number:
| Opcode*/Instruction        | Op/En| 64/32 bit Mode Support| CPUID Feature Flag| Description                          
| 0F C7 /6 RDRAND r16        | M    | V/V                   | RDRAND            | Read a 16-bit random number and store
|                            |      |                       |                   | in the destination register.         
| 0F C7 /6 RDRAND r32        | M    | V/V                   | RDRAND            | Read a 32-bit random number and store
|                            |      |                       |                   | in the destination register.         
| REX.W + 0F C7 /6 RDRAND r64| M    | V/I                   | RDRAND            | Read a 64-bit random number and store
|                            |      |                       |                   | in the destination register.         

Instruction Operand Encoding:
| Op/En| Operand 1    | Operand 2| Operand 3| Operand 4
| M    | ModRM:r/m (w)| NA       | NA       | NA       

Description:
Loads a hardware generated random value and store it in the destination register.
The size of the random value is determined by the destination register size
and operating mode. The Carry Flag indicates whether a random value is available
at the time the instruction is executed. CF=1 indicates that the data in the
destination is valid. Otherwise CF=0 and the data in the destination operand
will be returned as zeros for the specified width. All other flags are forced
to 0 in either situation. Software must check the state of CF=1 for determining
if a valid random value has been returned, otherwise it is expected to loop
and retry execution of RDRAND (see Intel® 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, Section 7.3.17, “Random Number Generator Instruction”).
This instruction is available at all privilege levels. In 64-bit mode, the instruction's
default operation size is 32 bits. Using a REX prefix in the form of REX.B permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W
promotes operation to 64 bit operands. See the summary chart at the beginning
of this section for encoding data and limits.

Operation:

IF HW_RND_GEN.ready = 1
  THEN
     CASE of
       osize is 64: DEST[63:0] <- HW_RND_GEN.data;
       osize is 32: DEST[31:0] <- HW_RND_GEN.data;
       osize is 16: DEST[15:0] <- HW_RND_GEN.data;
     ESAC
     CF <- 1;
  ELSE
     CASE of
       osize is 64: DEST[63:0] <- 0;
       osize is 32: DEST[31:0] <- 0;
       osize is 16: DEST[15:0] <- 0;
     ESAC
     CF <- 0;
FI
OF, SF, ZF, AF, PF <- 0;

Flags Affected:
The CF flag is set according to the result (see the “Operation” section above).
The OF, SF, ZF, AF, and PF flags are set to 0.


Intel C/C++ Compiler Intrinsic Equivalent:
| RDRAND:| int _rdrand16_step( unsigned short * 
|        | );                                   
| RDRAND:| int _rdrand32_step( unsigned int * );
| RDRAND:| int _rdrand64_step( unsigned __int64 
|        | *);                                  

Protected Mode Exceptions:
| #UD| If the LOCK prefix is used. If the F2H            
|    | or F3H prefix is used. If CPUID.01H:ECX.RDRAND[bit
|    | 30] = 0.                                          

Real-Address Mode Exceptions:
Same exceptions as in protected mode.


Virtual-8086 Mode Exceptions:
Same exceptions as in protected mode.


Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: RDTSC
description:
RDTSC - Read Time-Stamp Counter:
| Opcode*| Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                          
| 0F 31  | RDTSC      | NP   | Valid      | Valid          | Read time-stamp counter into EDX:EAX.

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Loads the current value of the processor's time-stamp counter (a 64-bit MSR)
into the EDX:EAX registers. The EDX register is loaded with the high-order 32
bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On
processors that support the Intel 64 architecture, the high-order 32 bits of
each of RAX and RDX are cleared.)

The processor monotonically increments the time-stamp counter MSR every clock
cycle and resets it to 0 whenever the processor is reset. See “Time Stamp Counter”
in Chapter 17 of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B, for specific details of the time stamp counter behavior.

When in protected or virtual 8086 mode, the time stamp disable (TSD) flag in
register CR4 restricts the use of the RDTSC instruction as follows. When the
TSD flag is clear, the RDTSC instruction can be executed at any privilege level;
when the flag is set, the instruction can only be executed at privilege level
0. (When in real-address mode, the RDTSC instruction is always enabled.)

The time-stamp counter can also be read with the RDMSR instruction, when executing
at privilege level 0.

The RDTSC instruction is not a serializing instruction. It does not necessarily
wait until all previous instructions have been executed before reading the counter.
Similarly, subsequent instructions may begin execution before the read operation
is performed. If software requires RDTSC to be executed only after all previous
instructions have completed locally, it can either use RDTSCP (if the processor
supports that instruction) or execute the sequence LFENCE;RDTSC.

This instruction was introduced by the Pentium processor.

See “Changes to Instruction Behavior in VMX Non-Root Operation” in Chapter 25
of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume
3C, for more information about the behavior of this instruction in VMX non-root
operation.

Operation:

IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
  THEN EDX:EAX <- TimeStampCounter;
  ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
     #GP(0);
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the TSD flag in register CR4 is set
|       | and the CPL is greater than 0.        
| #UD   | If the LOCK prefix is used.           

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used.

Virtual-8086 Mode Exceptions:
| #GP(0)| If the TSD flag in register CR4 is set.
| #UD   | If the LOCK prefix is used.            

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: RDTSCP
description:
RDTSCP - Read Time-Stamp Counter and Processor ID:
| Opcode* | Instruction| Op/En| 64-Bit Mode| Compat/Leg Mode| Description                              
| 0F 01 F9| RDTSCP     | NP   | Valid      | Valid          | Read 64-bit time-stamp counter and 32-bit
|         |            |      |            |                | IA32_TSC_AUX value into EDX:EAX and      
|         |            |      |            |                | ECX.                                     

Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Loads the current value of the processor's time-stamp counter (a 64-bit MSR)
into the EDX:EAX registers and also loads the IA32_TSC_AUX MSR (address C000_0103H)
into the ECX register. The EDX register is loaded with the high-order 32 bits
of the IA32_TSC MSR; the EAX register is loaded with the low-order 32 bits of
the IA32_TSC MSR; and the ECX register is loaded with the low-order 32-bits
of IA32_TSC_AUX MSR. On processors that support the Intel 64 architecture, the
high-order 32 bits of each of RAX, RDX, and RCX are cleared.

The processor monotonically increments the time-stamp counter MSR every clock
cycle and resets it to 0 whenever the processor is reset. See “Time Stamp Counter”
in Chapter 17 of the Intel® 64 and IA-32 Architectures Software Developer's
Manual, Volume 3B, for specific details of the time stamp counter behavior.

When in protected or virtual 8086 mode, the time stamp disable (TSD) flag in
register CR4 restricts the use of the RDTSCP instruction as follows. When the
TSD flag is clear, the RDTSCP instruction can be executed at any privilege level;
when the flag is set, the instruction can only be executed at privilege level
0. (When in real-address mode, the RDTSCP instruction is always enabled.)

The RDTSCP instruction waits until all previous instructions have been executed
before reading the counter.

| However, The presence of the RDTSCP       | subsequent instructions may begin execution
| instruction is indicated by CPUID leaf    | before the read operation is performed.    
| 80000001H, EDX bit 27. If the bit is      |                                            
| set to 1 then RDTSCP is present on the    |                                            
| processor. See “Changes to Instruction    |                                            
| Behavior in VMX Non-Root Operation”       |                                            
| in Chapter 25 of the Intel® 64 and IA-32  |                                            
| Architectures Software Developer's Manual,|                                            
| Volume 3C, for more information about     |                                            
| the behavior of this instruction in       |                                            
| VMX non-root operation.                   |                                            
Operation:

IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
  THEN
     EDX:EAX <- TimeStampCounter;
     ECX <- IA32_TSC_AUX[31:0];
  ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
     #GP(0);
FI;

Flags Affected:
None.


Protected Mode Exceptions:
| #GP(0)| If the TSD flag in register CR4 is set                       
|       | and the CPL is greater than 0.                               
| #UD   | If the LOCK prefix is used. If CPUID.80000001H:EDX.RDTSCP[bit
|       | 27] = 0.                                                     

Real-Address Mode Exceptions:
| #UD| If the LOCK prefix is used. If CPUID.80000001H:EDX.RDTSCP[bit
|    | 27] = 0.                                                     

Virtual-8086 Mode Exceptions:
| #GP(0)| If the TSD flag in register CR4 is set.                      
| #UD   | If the LOCK prefix is used. If CPUID.80000001H:EDX.RDTSCP[bit
|       | 27] = 0.                                                     

Compatibility Mode Exceptions:
Same exceptions as in protected mode.


64-Bit Mode Exceptions:
Same exceptions as in protected mode.


platform: x86
mnem: REP
description:
REP/REPE/REPZ/REPNE/REPNZ - Repeat String Operation Prefix:
| Opcode     | Instruction        | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                  
| F3 6C      | REP INS m8, DX     | NP   | Valid      | Valid          | Input (E)CX bytes from port DX into          
|            |                    |      |            |                | ES:[(E)DI].                                  
| F3 6C      | REP INS m8, DX     | NP   | Valid      | N.E.           | Input RCX bytes from port DX into [RDI].     
| F3 6D      | REP INS m16, DX    | NP   | Valid      | Valid          | Input (E)CX words from port DX into          
|            |                    |      |            |                | ES:[(E)DI.]                                  
| F3 6D      | REP INS m32, DX    | NP   | Valid      | Valid          | Input (E)CX doublewords from port DX         
|            |                    |      |            |                | into ES:[(E)DI].                             
| F3 6D      | REP INS r/m32, DX  | NP   | Valid      | N.E.           | Input RCX default size from port DX          
|            |                    |      |            |                | into [RDI].                                  
| F3 A4      | REP MOVS m8, m8    | NP   | Valid      | Valid          | Move (E)CX bytes from DS:[(E)SI] to          
|            |                    |      |            |                | ES:[(E)DI].                                  
| F3 REX.W A4| REP MOVS m8, m8    | NP   | Valid      | N.E.           | Move RCX bytes from [RSI] to [RDI].          
| F3 A5      | REP MOVS m16, m16  | NP   | Valid      | Valid          | Move (E)CX words from DS:[(E)SI] to          
|            |                    |      |            |                | ES:[(E)DI].                                  
| F3 A5      | REP MOVS m32, m32  | NP   | Valid      | Valid          | Move (E)CX doublewords from DS:[(E)SI]       
|            |                    |      |            |                | to ES:[(E)DI].                               
| F3 REX.W A5| REP MOVS m64, m64  | NP   | Valid      | N.E.           | Move RCX quadwords from [RSI] to [RDI].      
| F3 6E      | REP OUTS DX, r/m8  | NP   | Valid      | Valid          | Output (E)CX bytes from DS:[(E)SI] to        
|            |                    |      |            |                | port DX.                                     
| F3 REX.W 6E| REP OUTS DX, r/m8* | NP   | Valid      | N.E.           | Output RCX bytes from [RSI] to port          
|            |                    |      |            |                | DX.                                          
| F3 6F      | REP OUTS DX, r/m16 | NP   | Valid      | Valid          | Output (E)CX words from DS:[(E)SI] to        
|            |                    |      |            |                | port DX.                                     
| F3 6F      | REP OUTS DX, r/m32 | NP   | Valid      | Valid          | Output (E)CX doublewords from DS:[(E)SI]     
|            |                    |      |            |                | to port DX.                                  
| F3 REX.W 6F| REP OUTS DX, r/m32 | NP   | Valid      | N.E.           | Output RCX default size from [RSI] to        
|            |                    |      |            |                | port DX.                                     
| F3 AC      | REP LODS AL        | NP   | Valid      | Valid          | Load (E)CX bytes from DS:[(E)SI] to          
|            |                    |      |            |                | AL.                                          
| F3 REX.W AC| REP LODS AL        | NP   | Valid      | N.E.           | Load RCX bytes from [RSI] to AL.             
| F3 AD      | REP LODS AX        | NP   | Valid      | Valid          | Load (E)CX words from DS:[(E)SI] to          
|            |                    |      |            |                | AX.                                          
| F3 AD      | REP LODS EAX       | NP   | Valid      | Valid          | Load (E)CX doublewords from DS:[(E)SI]       
|            |                    |      |            |                | to EAX.                                      
| F3 REX.W AD| REP LODS RAX       | NP   | Valid      | N.E.           | Load RCX quadwords from [RSI] to RAX.        
| F3 AA      | REP STOS m8        | NP   | Valid      | Valid          | Fill (E)CX bytes at ES:[(E)DI] with          
|            |                    |      |            |                | AL.                                          
| F3 REX.W AA| REP STOS m8        | NP   | Valid      | N.E.           | Fill RCX bytes at [RDI] with AL.             
| F3 AB      | REP STOS m16       | NP   | Valid      | Valid          | Fill (E)CX words at ES:[(E)DI] with          
|            |                    |      |            |                | AX.                                          
| F3 AB      | REP STOS m32       | NP   | Valid      | Valid          | Fill (E)CX doublewords at ES:[(E)DI]         
|            |                    |      |            |                | with EAX.                                    
| F3 REX.W AB| REP STOS m64       | NP   | Valid      | N.E.           | Fill RCX quadwords at [RDI] with RAX.        
| F3 A6      | REPE CMPS m8, m8   | NP   | Valid      | Valid          | Find nonmatching bytes in ES:[(E)DI]         
|            |                    |      |            |                | and DS:[(E)SI].                              
| F3 REX.W A6| REPE CMPS m8, m8   | NP   | Valid      | N.E.           | Find non-matching bytes in [RDI] and         
|            |                    |      |            |                | [RSI].                                       
| F3 A7      | REPE CMPS m16, m16 | NP   | Valid      | Valid          | Find nonmatching words in ES:[(E)DI]         
|            |                    |      |            |                | and DS:[(E)SI].                              
| F3 A7      | REPE CMPS m32, m32 | NP   | Valid      | Valid          | Find nonmatching doublewords in ES:[(E)DI]and
|            |                    |      |            |                | DS:[(E)SI].                                  
| F3 REX.W A7| REPE CMPS m64, m64 | NP   | Valid      | N.E.           | Find non-matching quadwords in [RDI]         
|            |                    |      |            |                | and [RSI].                                   
| F3 AE      | REPE SCAS m8       | NP   | Valid      | Valid          | Find non-AL byte starting at ES:[(E)DI].     
| F3 REX.W AE| REPE SCAS m8       | NP   | Valid      | N.E.           | Find non-AL byte starting at [RDI].          
| F3 AF      | REPE SCAS m16      | NP   | Valid      | Valid          | Find non-AX word starting at ES:[(E)DI].     
| F3 AF      | REPE SCAS m32      | NP   | Valid      | Valid          | Find non-EAX doubleword starting at          
|            |                    |      |            |                | ES:[(E)DI].                                  
| Opcode     | Instruction        | Op/En| 64-Bit Mode| Compat/Leg Mode| Description                                  
| F3 REX.W AF| REPE SCAS m64      | NP   | Valid      | N.E.           | Find non-RAX quadword starting at [RDI].     
| F2 A6      | REPNE CMPS m8, m8  | NP   | Valid      | Valid          | Find matching bytes in ES:[(E)DI] and        
|            |                    |      |            |                | DS:[(E)SI].                                  
| F2 REX.W A6| REPNE CMPS m8, m8  | NP   | Valid      | N.E.           | Find matching bytes in [RDI] and [RSI].      
| F2 A7      | REPNE CMPS m16, m16| NP   | Valid      | Valid          | Find matching words in ES:[(E)DI] and        
|            |                    |      |            |                | DS:[(E)SI].                                  
| F2 A7      | REPNE CMPS m32, m32| NP   | Valid      | Valid          | Find matching doublewords in ES:[(E)DI]      
|            |                    |      |            |                | and DS:[(E)SI].                              
| F2 REX.W A7| REPNE CMPS m64, m64| NP   | Valid      | N.E.           | Find matching doublewords in [RDI] and       
|            |                    |      |            |                | [RSI].                                       
| F2 AE      | REPNE SCAS m8      | NP   | Valid      | Valid          | Find AL, starting at ES:[(E)DI].             
| F2 REX.W AE| REPNE SCAS m8      | NP   | Valid      | N.E.           | Find AL, starting at [RDI].                  
| F2 AF      | REPNE SCAS m16     | NP   | Valid      | Valid          | Find AX, starting at ES:[(E)DI].             
| F2 AF      | REPNE SCAS m32     | NP   | Valid      | Valid          | Find EAX, starting at ES:[(E)DI].            
| F2 REX.W AF| REPNE SCAS m64     | NP   | Valid      | N.E.           | Find RAX, starting at [RDI].                 
Notes: * In 64-bit mode, r/m8 can not be encoded to access the following byte
registers if a REX prefix is used: AH, BH, CH, DH.


Instruction Operand Encoding:
| Op/En| Operand 1| Operand 2| Operand 3| Operand 4
| NP   | NA       | NA       | NA       | NA       

Description:
Repeats a string instruction the number of times specified in the count register
or until the indicated condition of the ZF flag is no longer met. The REP (repeat),
REPE (repeat while equal), REPNE (repeat while not equal), REPZ (repeat while
zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be
added to one of the string instructions. The REP prefix can be added to the
INS, OUTS, MOVS, LODS, and STOS instructions, and the REPE, REPNE, REPZ, and
REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and
REPNZ prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.)
The behavior of the REP prefix is undefined when used with non-string instructions.

The REP prefixes apply only to one string instruction at a time. To repeat a
block of instructions, use the LOOP instruction or another looping construct.
All of these repeat prefixes cause the associated instruction to be repeated
until the count in register is decremented to 0. See Table 4-13.


Table 4-13. Repeat Prefixes:
| Repeat Prefix| Termination Condition 1*| Termination Condition 2
| REP          | RCX or (E)CX = 0        | None                   
| REPE/REPZ    | RCX or (E)CX = 0        | ZF = 0                 
| REPNE/REPNZ  | RCX or (E)CX = 0        | ZF = 1                 
Notes: * Count register is CX, ECX or RCX by default, depending on attributes
of the operating modes.

The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag
after each iteration and terminate the repeat loop if the ZF flag is not in
the specified state. When both termination conditions are tested, the cause
of a repeat termination can be determined either by testing the count register
with a JECXZ instruction or by testing the ZF flag (with a JZ, JNZ, or JNE instruction).

When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require
initialization because both the CMPS and SCAS instructions affect the ZF flag
according to the results of the comparisons they make.

A repeating string operation can be suspended by an exception or interrupt.
When this happens, the state of the registers is preserved to allow the string
operation to be resumed upon a return from the exception or interrupt handler.
The source and destination registers point to the next string elements to be
operated on, the EIP register points to the string instruction, and the ECX
register has the value it held following the last successful iteration of the
instruction. This mechanism allows long string operations to proceed without
affecting the interrupt response time of the system.

When a fault occurs during the execution of a CMPS or SCAS instruction that
is prefixed with REPE or REPNE, the EFLAGS value is restored to the state prior
to the execution of the instruction. Since the SCAS and CMPS instructions do
not use EFLAGS as an input, the processor can resume the instruction after the
page fault handler.

Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can
handle the rate at which these instructions execute. Note that a REP STOS instruction
is the fastest way to initialize a large block of memory.

In 64-bit mode, the operand size of the count register is associated with the
address size attribute. Thus the default count register is RCX; REX.W has no
effect on the address size and the count register. In 64-bit mode, if 67H is
used to override address size attribute, the count register is ECX and any implicit
source/destination operand will use the corresponding 32-bit index register.
See the summary chart at the beginning of this section for encoding data and
limits.

Operation:

IF AddressSize = 16
 THEN
   Use CX for CountReg;
   Implicit Source/Dest operand for memory use of SI/DI;
 ELSE IF AddressSize = 64
   THEN Use RCX for CountReg;
   Implicit Source/Dest operand for memory use of RSI/RDI;
 ELSE
   Use ECX for CountReg;
   Implicit Source/Dest operand for memory use of ESI/EDI;
FI;
WHILE CountReg != 0
  DO
     Service pending interrupts (if any);
     Execute associated string instruction;
     CountReg <- (CountReg - 1);
     IF CountReg = 0
       THEN exit WHILE loop; FI;
     IF (Repeat prefix is REPZ or REPE) and (ZF = 0)
     or (Repeat prefix is REPNZ or REPNE) and (ZF = 1)
       THEN exit WHILE loop; FI;
  OD;

Flags Affected:
None; however, the CMPS and SCAS instructions do set the status flags in the
EFLAGS register.


Exceptions (All Operating Modes):
Exceptions may be generated by an instruction associated with the prefix.


64-Bit Mode Exceptions:
| #GP(0)| If the memory address is in a non-canonical
|       | form.                                      


