# instructions

platform: ARM
mnem: VLD3
description:
        Load single 3-element structure to one lane of three registers loads one 3-element structure from memory into       (F8.1.92)
        corresponding elements of three registers. Elements of the registers that are not loaded are unchanged. For details
        of the addressing mode see Advanced SIMD addressing mode on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7           4 3         0
            1 1 1 1 0 1 0 0 1 D 1 0                   Rn           Vd      !=11 1 0 index_align         Rm
                                                                           size


        Offset variant

        Applies when Rm = 1111.

        VLD3{<c>}{<q>}.<size> <list>, [<Rn>]


        Post-indexed variant

        Applies when Rm = 1101.

        VLD3{<c>}{<q>}.<size> <list>, [<Rn>]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>


        Decode for all variants of this encoding

         if size == '11' then SEE VLD3 (single 3-element structure to all lanes);
         case size of
               when '00'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
               when '01'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
               when '10'
                   if index_align<1:0> != '00' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
         d = UInt(D:Vd);     d2 = d + inc;   d3 = d2 + inc;   n = UInt(Rn);   m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d3 > 31 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7           4 3         0
            1 1 1 1 1 0 0 1 1 D 1 0                   Rn           Vd      !=11 1 0 index_align         Rm
                                                                           size
Offset variant

Applies when Rm = 1111.

VLD3{<c>}{<q>}.<size> <list>, [<Rn>]


Post-indexed variant

Applies when Rm = 1101.

VLD3{<c>}{<q>}.<size> <list>, [<Rn>]!


Post-indexed variant

Applies when Rm != 11x1.

VLD3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>


Decode for all variants of this encoding

 if size == '11' then SEE VLD3 (single 3-element structure to all lanes);
 case size of
     when '00'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
     when '01'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 2;   index = UInt(index_align<3:2>);
         inc = if index_align<1> == '0' then 1 else 2;
     when '10'
         if index_align<1:0> != '00' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         inc = if index_align<2> == '0' then 1 else 2;
 d = UInt(D:Vd);  d2 = d + inc;    d3 = d2 + inc;    n = UInt(Rn);     m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 || d3 > 31 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD3 (single 3-element structure to
one lane) on page J1-5386.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VLD3 instruction must be
               unconditional. ARM strongly recommends that a T32 VLD3 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

               {<Dd[x]>, <Dd+1[x]>, <Dd+2[x]>}
                           Single-spaced registers, see Table F8-3 on page F8-3464.

               {<Dd[x]>, <Dd+2[x]>, <Dd+4[x]>}
                           Double-spaced registers, see Table F8-3 on page F8-3464.

               This is not available if <size> == 8.
        <Rn>              Contains the base address for the access.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                                                 Table F8-3 Encoding of index and register spacing

                                            <size> == 8               <size> == 16            <size> == 32

                         Index              index_align[3:1] = x      index_align[3:2] = x    index_align[3] = x

                         Single-spacing     index_align[0] = 0        index_align[1:0] = '00' index_align[2:0] = '000'

                         Double-spacing     -                         index_align[1:0] = '10' index_align[2:0] = '100'



        Alignment

        Standard alignment rules apply, see Alignment support on page B2-75.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();    CheckAdvSIMDEnabled();
               address = R[n];
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + 3*ebytes;
               Elem[D[d], index] = MemU[address,ebytes];
               Elem[D[d2],index] = MemU[address+ebytes,ebytes];
               Elem[D[d3],index] = MemU[address+2*ebytes,ebytes];


platform: ARM
mnem: VLD4
description:
Load single 4-element structure to one lane of four registers loads one 4-element structure from memory into       (F8.1.95)
corresponding elements of four registers. Elements of the registers that are not loaded are unchanged. For details of
the addressing mode see Advanced SIMD addressing mode on page F5-2605.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7               4 3         0
   1 1 1 1 0 1 0 0 1 D 1 0                    Rn           Vd       !=11 1 1 index_align          Rm
                                                                    size


Offset variant

Applies when Rm = 1111.

VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then SEE VLD4 (single 4-element structure to all lanes);
 case size of
      when '00'
           ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
           alignment = if index_align<0> == '0' then 1 else 4;
      when '01'
           ebytes = 2;   index = UInt(index_align<3:2>);
           inc = if index_align<1> == '0' then 1 else 2;
           alignment = if index_align<0> == '0' then 1 else 8;
      when '10'
           if index_align<1:0> == '11' then UNDEFINED;
           ebytes = 4;   index = UInt(index_align<3>);
           inc = if index_align<2> == '0' then 1 else 2;
           alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>);
 d = UInt(D:Vd);    d2 = d + inc;    d3 = d2 + inc;   d4 = d3 + inc;      n = UInt(Rn);    m = UInt(Rm);
 wback = (m != 15);     register_index = (m != 15 && m != 13);
 if n == 15 || d4 > 31 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7               4 3         0
   1 1 1 1 1 0 0 1 1 D 1 0                    Rn           Vd       !=11 1 1 index_align          Rm
                                                                    size
        Offset variant

        Applies when Rm = 1111.

        VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VLD4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then SEE VLD4 (single 4-element structure to all lanes);
         case size of
               when '00'
                   ebytes = 1;   index = UInt(index_align<3:1>);      inc = 1;
                   alignment = if index_align<0> == '0' then 1 else 4;
               when '01'
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 8;
               when '10'
                   if index_align<1:0> == '11' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
                   alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>);
         d = UInt(D:Vd);     d2 = d + inc;    d3 = d2 + inc;    d4 = d3 + inc; n = UInt(Rn);   m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d4 > 31 then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLD4 (single 4-element structure to
        one lane) on page J1-5387.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VLD4 instruction must be
                          unconditional. ARM strongly recommends that a T32 VLD4 instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            The data size. It must be one of:

                          8          Encoded as size = 0b00.

                          16         Encoded as size = 0b01.

                          32         Encoded as size = 0b10.

        <list>            The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

                          {<Dd[x]>, <Dd+1[x]>, <Dd+2[x]>, <Dd+3[x]>}
                                     Single-spaced registers, see Table F8-4 on page F8-3473.

                          {<Dd[x]>, <Dd+2[x]>, <Dd+4[x]>, <Dd+6[x]>}
                                     Double-spaced registers, see Table F8-4 on page F8-3473.
               Not available if <size> == 8.

<Rn>          The base address for the access.

<align>       The alignment. It can be:

              32            4-byte alignment, available only if <size> is 8.

              64            8-byte alignment, available only if <size> is 16 or 32.

              128           16-byte alignment, available only if <size> is 32.

              omitted       Standard alignment, see Unaligned data access on page E2-2427.

               : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
              see Advanced SIMD addressing mode on page F5-2605.

<Rm>          Contains an address offset applied after the access.

For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                         Table F8-4 Encoding of index, alignment, and register spacing

                                       <size> == 8              <size> == 16               <size> == 32

                  Index                index_align[3:1] = x     index_align[3:2] = x       index_align[3] = x

                  Single-spacing       -                        index_align[1] = 0         index_align[2] = 0

                  Double-spacing       -                        index_align[1] = 1         index_align[2] = 1

                  <align> omitted      index_align[0] = 0       index_align[0] = 0         index_align[1:0] = '00'

                  <align> == 32        index_align[0] = 1       -                          -

                  <align> == 64        -                        index_align[0] = 1         index_align[1:0] = '01'

                  <align> == 128       -                        -                          index_align[1:0] = '10'



Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDEnabled();
    address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
    if wback then
        if register_index then
             R[n] = R[n] + R[m];
        else
             R[n] = R[n] + 4*ebytes;
    Elem[D[d], index] = MemU[address,ebytes];
    Elem[D[d2],index] = MemU[address+ebytes,ebytes];
    Elem[D[d3],index] = MemU[address+2*ebytes,ebytes];
    Elem[D[d4],index] = MemU[address+3*ebytes,ebytes];


platform: ARM
mnem: VLDM
description:
        Load Multiple SIMD&FP registers loads multiple registers from consecutive locations in the Advanced SIMD and       (F8.1.98)
        floating-point register file using an address from a general-purpose register.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        This instruction is used by the aliases FLDMDBX, FLDMIAX, and VPOP. See the Alias conditions on
        page F8-3482 table for details of when each alias is preferred.


        A1


           31        28 27 26 25 24 23 22 21 20 19         16 15       12 11 10 9 8 7                       0
              !=1111     1 1 0 P U D W 1               Rn          Vd      1 0 1 1              imm8
               cond


        Decrement Before variant

        Applies when P = 1 && U = 0 && W = 1.

        VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <dreglist>


        Increment After variant

        Applies when P = 0 && U = 1.

        VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
        VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>


        Decode for all variants of this encoding

         if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
         if P == '1' && W == '0' then SEE VLDR;
         if P == U && W == '1' then UNDEFINED;
         // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
         single_regs = FALSE;      add = (U == '1');    wback = (W == '1');
         d = UInt(D:Vd);     n = UInt(Rn);    imm32 = ZeroExtend(imm8:'00', 32);
         regs = UInt(imm8) DIV 2;      // If UInt(imm8) is odd, see "FLDMX".
         if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
         if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
         if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;


        A2


           31        28 27 26 25 24 23 22 21 20 19         16 15       12 11 10 9 8 7                       0
              !=1111     1 1 0 P U D W 1               Rn          Vd      1 0 1 0              imm8
               cond


        Decrement Before variant

        Applies when P = 1 && U = 0 && W = 1.

        VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <sreglist>


        Increment After variant

        Applies when P = 0 && U = 1.

        VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
        VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
Decode for all variants of this encoding

 if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
 if P == '1' && W == '0' then SEE VLDR;
 if P == U && W == '1' then UNDEFINED;
 // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
 single_regs = TRUE;  add = (U == '1');  wback = (W == '1');     d = UInt(Vd:D);    n = UInt(Rn);
 imm32 = ZeroExtend(imm8:'00', 32);  regs = UInt(imm8);
 if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
 if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7                        0
  1 1 1 0 1 1 0 P U D W 1                Rn          Vd         1 0 1 1               imm8




Decrement Before variant

Applies when P = 1 && U = 0 && W = 1.

VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <dreglist>


Increment After variant

Applies when P = 0 && U = 1.

VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <dreglist>


Decode for all variants of this encoding

 if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
 if P == '1' && W == '0' then SEE VLDR;
 if P == U && W == '1' then UNDEFINED;
 // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
 single_regs = FALSE;  add = (U == '1');  wback = (W == '1');
 d = UInt(D:Vd);  n = UInt(Rn);  imm32 = ZeroExtend(imm8:'00', 32);
 regs = UInt(imm8) DIV 2;  // If UInt(imm8) is odd, see "FLDMX".
 if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
 if regs == 0 || regs > 16 || (d+regs) > 32 then UNPREDICTABLE;
 if imm8<0> == '1' && (d+regs) > 16 then UNPREDICTABLE;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7                        0
  1 1 1 0 1 1 0 P U D W 1                Rn          Vd         1 0 1 0               imm8




Decrement Before variant

Applies when P = 1 && U = 0 && W = 1.

VLDMDB{<c>}{<q>}{.<size>} <Rn>!, <sreglist>


Increment After variant

Applies when P = 0 && U = 1.

VLDM{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
VLDMIA{<c>}{<q>}{.<size>} <Rn>{!}, <sreglist>
        Decode for all variants of this encoding

         if P == '0' && U == '0' && W == '0' then SEE "Related encodings";
         if P == '1' && W == '0' then SEE VLDR;
         if P == U && W == '1' then UNDEFINED;
         // Remaining combinations are PUW = 010 (IA without !), 011 (IA with !), 101 (DB with !)
         single_regs = TRUE;       add = (U == '1');     wback = (W == '1');      d = UInt(Vd:D);     n = UInt(Rn);
         imm32 = ZeroExtend(imm8:'00', 32);          regs = UInt(imm8);
         if n == 15 && (wback || CurrentInstrSet() != InstrSet_A32) then UNPREDICTABLE;
         if regs == 0 || (d+regs) > 32 then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VLDM on page J1-5388.

        Related encodings: 64-bit transfers accessing the SIMD and floating-point register file on page F5-2607.


        Alias conditions


                               Alias                     is preferred when

                               FLDMDBX                   P == '1' && U == '0' && imm8<0> == '1'

                               FLDMIAX                   P == '0' && U == '1' && imm8<0> == '1'

                               VPOP                      P == '0' && U == '1' && W == '1' && Rn == '1101'



        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers
                          being transferred.

        <Rn>              For encoding A1 and A2: is the general-purpose base register, encoded in the "Rn" field. If
                          writeback is not specified, the PC can be used.

                          For encoding T1 and T2: is the general-purpose base register, encoded in the "Rn" field.

        !                 Specifies base register writeback. Encoded in the "W" field as 1 if present, otherwise 0.

        <sreglist>        Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must
                          contain at least one register.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The
                          list must contain at least one register, and must not contain more than 16 registers.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();        CheckVFPEnabled(TRUE);
               address = if add then R[n] else R[n]-imm32;
               if wback then R[n] = if add then R[n]+imm32 else R[n]-imm32;
               for r = 0 to regs-1
                   if single_regs then
                        S[d+r] = MemA[address,4];       address = address+4;
                   else
   word1 = MemA[address,4];  word2 = MemA[address+4,4];      address = address+8;
   // Combine the word-aligned words in the correct order for current endianness.
   D[d+r] = if BigEndian() then word1:word2 else word2:word1;


platform: ARM
mnem: VLDR
description:
        Load SIMD&FP register loads a single register from the Advanced SIMD and floating-point register file, using an       (F8.1.99)
        address from a general-purpose register, with an optional offset.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7                       0
              !=1111     1 1 0 1 U D 0 1             Rn           Vd       1 0 1 1             imm8
               cond


        Literal variant

        Applies when Rn = 1111.

        VLDR{<c>}{<q>}{.64} <Dd>, <label>
        VLDR{<c>}{<q>}{.64} <Dd>, [PC, #{+/-}<imm>]


        Offset variant

        Applies when Rn != 1111.

        VLDR{<c>}{<q>}{.64} <Dd>, [<Rn> {, #{+/-}<imm>}]


        Decode for all variants of this encoding

         single_reg = FALSE;     add = (U == '1');   imm32 = ZeroExtend(imm8:'00', 32);
         d = UInt(D:Vd);     n = UInt(Rn);


        A2


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7                       0
              !=1111     1 1 0 1 U D 0 1             Rn           Vd       1 0 1 0             imm8
               cond


        Literal variant

        Applies when Rn = 1111.

        VLDR{<c>}{<q>}{.32} <Sd>, <label>
        VLDR{<c>}{<q>}{.32} <Sd>, [PC, #{+/-}<imm>]


        Offset variant

        Applies when Rn != 1111.

        VLDR{<c>}{<q>}{.32} <Sd>, [<Rn> {, #{+/-}<imm>}]


        Decode for all variants of this encoding

         single_reg = TRUE;     add = (U == '1');   imm32 = ZeroExtend(imm8:'00', 32);
         d = UInt(Vd:D);     n = UInt(Rn);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15        12 11 10 9 8 7                         0
  1 1 1 0 1 1 0 1 U D 0 1                  Rn           Vd        1 0 1 1                imm8




Literal variant

Applies when Rn = 1111.

VLDR{<c>}{<q>}{.64} <Dd>, <label>
VLDR{<c>}{<q>}{.64} <Dd>, [PC, #{+/-}<imm>]


Offset variant

Applies when Rn != 1111.

VLDR{<c>}{<q>}{.64} <Dd>, [<Rn> {, #{+/-}<imm>}]


Decode for all variants of this encoding

 single_reg = FALSE;  add = (U == '1');    imm32 = ZeroExtend(imm8:'00', 32);
 d = UInt(D:Vd);  n = UInt(Rn);


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15        12 11 10 9 8 7                         0
  1 1 1 0 1 1 0 1 U D 0 1                  Rn           Vd        1 0 1 0                imm8




Literal variant

Applies when Rn = 1111.

VLDR{<c>}{<q>}{.32} <Sd>, <label>
VLDR{<c>}{<q>}{.32} <Sd>, [PC, #{+/-}<imm>]


Offset variant

Applies when Rn != 1111.

VLDR{<c>}{<q>}{.32} <Sd>, [<Rn> {, #{+/-}<imm>}]


Decode for all variants of this encoding

 single_reg = TRUE;  add = (U == '1');    imm32 = ZeroExtend(imm8:'00', 32);
 d = UInt(Vd:D);  n = UInt(Rn);


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

.64           Optional data size specifiers.

<Dd>          The destination register for a doubleword load.

.32           Optional data size specifiers.

<Sd>          The destination register for a singleword load.
        <label>           The label of the literal data item to be loaded. The assembler calculates the required value of the
                          offset from the Align(PC, 4) value of the instruction to this label. Permitted values are multiples of
                          4 in the range -1020 to 1020. If the offset is zero or positive, imm32 is equal to the offset and add ==
                          TRUE. If the offset is negative, imm32 is equal to minus the offset and add == FALSE.

        <Rn>              Is the general-purpose base register, encoded in the "Rn" field.

        +/-               Specifies the offset is added to or subtracted from the base register, defaulting to + if omitted and
                          encoded in the "U" field. It can have the following values:

                          -            when U = 0

                          +            when U = 1

        <imm>             The immediate offset used for forming the address. For the immediate forms of the syntax, <imm>
                          can be omitted, in which case the #0 form of the instruction is assembled. Permitted values are
                          multiples of 4 in the range 0 to 1020.

        For the literal forms of the instruction, the base register is encoded as 0b1111 to indicate that the PC is the base
        register.

        The alternative syntax permits the addition or subtraction of the offset and the immediate offset to be specified
        separately, including permitting a subtraction of 0 that cannot be specified using the normal syntax. For more
        information, see Use of labels in UAL instruction syntax on page F1-2469.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckVFPEnabled(TRUE);
               base = if n == 15 then Align(PC,4) else R[n];
               address = if add then (base + imm32) else (base - imm32);
               if single_reg then
                   S[d] = MemA[address,4];
               else
                   word1 = MemA[address,4];       word2 = MemA[address+4,4];
                   // Combine the word-aligned words in the correct order for current endianness.
                   D[d] = if BigEndian() then word1:word2 else word2:word1;


platform: ARM
mnem: VMAX
description:
Vector Maximum compares corresponding elements in two vectors, and copies the larger of each pair into the       (F8.1.100)
corresponding element in the destination vector.

The operand vector elements are 32-bit floating-point numbers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 0 0 D 0 0                    Vn           Vd       1 1 1 1 N Q M 0              Vm
                                   op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMAX{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VMAX{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 maximum = (op == '0');      esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 0 1 1 1 1 0 D 0 0                    Vn           Vd       1 1 1 1 N Q M 0              Vm
                                   op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMAX{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VMAX{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>
        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         maximum = (op == '0');      esize = 32;    elements = 2;
         d = UInt(D:Vd);      n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VMAX or VMIN instruction must be
                          unconditional. ARM strongly recommends that a T32 VMAX or VMIN instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Floating-point maximum and minimum

        .       max(+0.0, -0.0) = +0.0

        .       If any input is a NaN, the corresponding result element is the default NaN.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[D[n+r],e,esize];      op2 = Elem[D[m+r],e,esize];
                        if maximum then
                             Elem[D[d+r],e,esize] = FPMax(op1, op2, StandardFPSCRValue());
                        else
                             Elem[D[d+r],e,esize] = FPMin(op1, op2, StandardFPSCRValue());


platform: ARM
mnem: VMAXNM
description:
This instruction determines the floating-point maximum number.       (F8.1.102)

It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one
operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMAX.

This instruction is not conditional.


A1


   31 30 29 28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 1 0 D 0 0                   Vn          Vd         1 1 1 1 N Q M 1               Vm
                                  op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMAXNM{<q>}.F32 <Dd>, <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VMAXNM{<q>}.F32 <Qd>, <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 maximum = (op == '0');
 advsimd = TRUE; esize = 32; elements = 2;
 d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


A2


   31 30 29 28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 1 1 1 0 1 D 0 0                   Vn          Vd         1 0 1 sz N 0 M 0              Vm
                                                                                     op


Single-precision scalar variant

Applies when sz = 0.

VMAXNM{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VMAXNM{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 advsimd = FALSE;
 maximum = (op == '0'); dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
 if InITBlock() then UNPREDICTABLE;
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3              0 15          12 11 10 9 8 7 6 5 4 3          0
            1 1 1 1 1 1 1 1 0 D 0 0                  Vn         Vd         1 1 1 1 N Q M 1       Vm
                                         op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMAXNM{<q>}.F32 <Dd>, <Dn>, <Dm>// Not permitted in IT block


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMAXNM{<q>}.F32 <Qd>, <Qn>, <Qm>// Not permitted in IT block


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         maximum = (op == '0');
         advsimd = TRUE; esize = 32; elements = 2;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3              0 15          12 11 10 9 8 7 6 5 4 3          0
            1 1 1 1 1 1 1 0 1 D 0 0                  Vn         Vd         1 0 1 sz N 0 M 0      Vm
                                                                                     op


        Single-precision scalar variant

        Applies when sz = 0.

        VMAXNM{<q>}.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


        Double-precision scalar variant

        Applies when sz = 1.

        VMAXNM{<q>}.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


        Decode for all variants of this encoding

         advsimd = FALSE;
         maximum = (op == '0'); dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
         if InITBlock() then UNPREDICTABLE;


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors.
Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations();   CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
 if advsimd then              // Advanced SIMD instruction
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[D[n+r], e, esize]; op2 = Elem[D[m+r], e, esize];
            if maximum then
                 Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, StandardFPSCRValue());
            else
                 Elem[D[d+r], e, esize] = FPMinNum(op1, op2, StandardFPSCRValue());
 else                         // VFP instruction
    if dp_operation then
        if maximum then
            D[d] = FPMaxNum(D[n], D[m], FPSCR);
        else
            D[d] = FPMinNum(D[n], D[m], FPSCR);
    else
        if maximum then
            S[d] = FPMaxNum(S[n], S[m], FPSCR);
        else
            S[d] = FPMinNum(S[n], S[m], FPSCR);


platform: ARM
mnem: VMIN
description:
        Vector Minimum compares corresponding elements in two vectors, and copies the smaller of each pair into the       (F8.1.103)
        corresponding element in the destination vector.

        The operand vector elements are 32-bit floating-point numbers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 0 0 D 1 0                   Vn           Vd      1 1 1 1 N Q M 0             Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMIN{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMIN{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         maximum = (op == '0');      esize = 32;  elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 0 1 1 1 1 0 D 1 0                   Vn           Vd      1 1 1 1 N Q M 0             Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMIN{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMIN{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 maximum = (op == '0');   esize = 32;    elements = 2;
 d = UInt(D:Vd);   n = UInt(N:Vn);    m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VMAX or VMIN instruction must be
               unconditional. ARM strongly recommends that a T32 VMAX or VMIN instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<Qd>           Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>           Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>           Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
               <Qm>*2.

<Dd>           Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>           Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>           Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Floating-point minimum

.     min(+0.0, -0.0) = -0.0

.     If any input is a NaN, the corresponding result element is the default NaN.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
              op1 = Elem[D[n+r],e,esize];     op2 = Elem[D[m+r],e,esize];
              if maximum then
                  Elem[D[d+r],e,esize] = FPMax(op1, op2, StandardFPSCRValue());
              else
                  Elem[D[d+r],e,esize] = FPMin(op1, op2, StandardFPSCRValue());


platform: ARM
mnem: VMINNM
description:
        This instruction determines the floating point minimum number.       (F8.1.105)

        It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one
        operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMIN.

        This instruction is not conditional.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 1 0 D 1 0                  Vn          Vd        1 1 1 1 N Q M 1                Vm
                                          op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMINNM{<q>}.F32 <Dd>, <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMINNM{<q>}.F32 <Qd>, <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         maximum = (op == '0');
         advsimd = TRUE; esize = 32; elements = 2;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        A2


           31 30 29 28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 1 1 1 0 1 D 0 0                  Vn          Vd        1 0 1 sz N 1 M 0               Vm
                                                                                          op


        Single-precision scalar variant

        Applies when sz = 0.

        VMINNM{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VMINNM{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         advsimd = FALSE;
         maximum = (op == '0'); dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
         if InITBlock() then UNPREDICTABLE;
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15          12 11 10 9 8 7 6 5 4 3                0
  1 1 1 1 1 1 1 1 0 D 1 0                Vn           Vd         1 1 1 1 N Q M 1             Vm
                               op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMINNM{<q>}.F32 <Dd>, <Dn>, <Dm>// Not permitted in IT block


128-bit SIMD vector variant

Applies when Q = 1.

VMINNM{<q>}.F32 <Qd>, <Qn>, <Qm>// Not permitted in IT block


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 maximum = (op == '0');
 advsimd = TRUE; esize = 32; elements = 2;
 d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15          12 11 10 9 8 7 6 5 4 3                0
  1 1 1 1 1 1 1 0 1 D 0 0                Vn           Vd         1 0 1 sz N 1 M 0            Vm
                                                                                 op


Single-precision scalar variant

Applies when sz = 0.

VMINNM{<q>}.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


Double-precision scalar variant

Applies when sz = 1.

VMINNM{<q>}.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


Decode for all variants of this encoding

 advsimd = FALSE;
 maximum = (op == '0'); dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.
        Assembler symbols

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         EncodingSpecificOperations();       CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
         if advsimd then                  // Advanced SIMD instruction
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = Elem[D[n+r], e, esize]; op2 = Elem[D[m+r], e, esize];
                        if maximum then
                             Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, StandardFPSCRValue());
                        else
                             Elem[D[d+r], e, esize] = FPMinNum(op1, op2, StandardFPSCRValue());
         else                             // VFP instruction
               if dp_operation then
                   if maximum then
                        D[d] = FPMaxNum(D[n], D[m], FPSCR);
                   else
                        D[d] = FPMinNum(D[n], D[m], FPSCR);
               else
                   if maximum then
                        S[d] = FPMaxNum(S[n], S[m], FPSCR);
                   else
                        S[d] = FPMinNum(S[n], S[m], FPSCR);


platform: ARM
mnem: VMLA
description:
Vector Multiply Accumulate multiplies corresponding elements in two vectors, and accumulates the results into the       (F8.1.106)
elements of the destination vector.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 0 0 D 0 0                    Vn          Vd        1 1 0 1 N Q M 1              Vm
                                   op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMLA{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>// Encoding T1/A1, encoded as Q = 0, sz = 0


128-bit SIMD vector variant

Applies when Q = 1.

VMLA{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>// Encoding T1/A1, encoded as Q = 1, sz = 0


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE;    add = (op == '0');    esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                 0
     !=1111    1 1 1 0 0 D 0 0                Vn          Vd        1 0 1 sz N 0 M 0             Vm
      cond                                                                           op


Single-precision scalar variant

Applies when sz = 0.

VMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;    dp_operation = (sz == '1');    add = (op == '0');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11 10 9 8 7 6 5 4 3              0
            1 1 1 0 1 1 1 1 0 D 0 0                  Vn           Vd       1 1 0 1 N Q M 1           Vm
                                          op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMLA{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>// Encoding T1/A1, encoded as Q = 0, sz = 0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMLA{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>// Encoding T1/A1, encoded as Q = 1, sz = 0


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE;     add = (op == '0');   esize = 32;   elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15        12 11 10 9 8 7 6 5 4 3              0
            1 1 1 0 1 1 1 0 0 D 0 0                  Vn           Vd       1 0 1 sz N 0 M 0          Vm




        Single-precision scalar variant

        Applies when sz = 0.

        VMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE;     dp_operation = (sz == '1');   add = (op == '0');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        Assembler symbols

        <c>               For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
                          Advanced SIMD VMLA or VMLS instruction must be unconditional. ARM strongly recommends that a
                          T32 Advanced SIMD VMLA or VMLS instruction is unconditional, see Conditional execution on
                          page F2-2507.

                          For encoding T2: see Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.
<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sn>          Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

<Sm>          Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();     CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
    if advsimd then   // Advanced SIMD instruction
        for r = 0 to regs-1
            for e = 0 to elements-1
                 product = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize], StandardFPSCRValue());
                 addend = if add then product else FPNeg(product);
                 Elem[D[d+r],e,esize] = FPAdd(Elem[D[d+r],e,esize], addend, StandardFPSCRValue());
    else              // VFP instruction
        if dp_operation then
            addend64 = if add then FPMul(D[n], D[m], FPSCR) else FPNeg(FPMul(D[n], D[m], FPSCR));
            D[d] = FPAdd(D[d], addend64, FPSCR);
        else
            addend32 = if add then FPMul(S[n], S[m], FPSCR) else FPNeg(FPMul(S[n], S[m], FPSCR));
            S[d] = FPAdd(S[d], addend32, FPSCR);


platform: ARM
mnem: VMLAL
description:
        Vector Multiply Accumulate Long multiplies corresponding elements in two vectors, and add the products to the       (F8.1.109)
        corresponding element of the destination vector. The destination vector element is twice as long as the elements that
        are multiplied.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19             16 15       12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 U 1 D !=11                    Vn            Vd       1 0 0 0 N 0 M 0              Vm
                                              size                                   op


        A1 variant

        VMLAL{<c>}{<q>}.<type><size> <Qd>, <Dn>, <Dm>// Encoding T2/A2


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vd<0> == '1' then UNDEFINED;
         add = (op == '0');      long_destination = TRUE;      unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);     regs = 1;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15       12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 U 1 1 1 1 1 D !=11                    Vn            Vd       1 0 0 0 N 0 M 0              Vm
                                              size                                   op


        T1 variant

        VMLAL{<c>}{<q>}.<type><size> <Qd>, <Dn>, <Dm>// Encoding T2/A2


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vd<0> == '1' then UNDEFINED;
         add = (op == '0');      long_destination = TRUE;      unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);     regs = 1;


        Notes for all encodings

        Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 Advanced SIMD VMLA, VMLAL, VMLS,
                          or VMLSL instruction must be unconditional. ARM strongly recommends that a T32 Advanced SIMD
                          VMLA, VMLAL, VMLS, or VMLSL instruction is unconditional, see Conditional execution on page F2-2507.
<q>           See Standard assembler syntax fields on page F2-2506.

<type>        The data type for the elements of the operands. It must be one of:

              S           Optional in encoding T1/A1. Encoded as U = 0 in encoding T2/A2.

              U           Optional in encoding T1/A1. Encoded as U = 1 in encoding T2/A2.

              I           Available only in encoding T1/A1.

<size>        The data size for the elements of the operands. It must be one of:

              8           Encoded as size = 0b00.

              16          Encoded as size = 0b01.

              32          Encoded as size = 0b10.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();     CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            product = Int(Elem[Din[n+r],e,esize],unsigned) * Int(Elem[Din[m+r],e,esize],unsigned);
            addend = if add then product else -product;
            if long_destination then
                 Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + addend;
            else
                 Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + addend;


platform: ARM
mnem: VMLS
description:
        Vector Multiply Subtract multiplies corresponding elements in two vectors, subtracts the products from       (F8.1.111)
        corresponding elements of the destination vector, and places the results in the destination vector.

                  Note
        ARM recommends that software does not use the VMLS instruction in the Round towards Plus Infinity and Round
        towards Minus Infinity rounding modes, because the rounding of the product and of the sum can change the result
        of the instruction in opposite directions, defeating the purpose of these rounding modes.


        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3              0
            1 1 1 1 0 0 1 0 0 D 1 0                   Vn           Vd       1 1 0 1 N Q M 1             Vm
                                           op sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMLS{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>// Encoding T1/A1, encoded as Q = 0, sz = 0


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMLS{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>// Encoding T1/A1, encoded as Q = 1, sz = 0


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE;     add = (op == '0');    esize = 32;   elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        A2


           31        28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3              0
              !=1111     1 1 1 0 0 D 0 0              Vn           Vd       1 0 1 sz N 1 M 0            Vm
               cond                                                                        op


        Single-precision scalar variant

        Applies when sz = 0.

        VMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;  dp_operation = (sz == '1');  add = (op == '0');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 0 1 1 1 1 0 D 1 0                Vn          Vd         1 1 0 1 N Q M 1             Vm
                               op sz


64-bit SIMD vector variant

Applies when Q = 0.

VMLS{<c>}{<q>}.F32 <Dd>, <Dn>, <Dm>// Encoding T1/A1, encoded as Q = 0, sz = 0


128-bit SIMD vector variant

Applies when Q = 1.

VMLS{<c>}{<q>}.F32 <Qd>, <Qn>, <Qm>// Encoding T1/A1, encoded as Q = 1, sz = 0


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE;  add = (op == '0');  esize = 32;  elements = 2;
 d = UInt(D:Vd);  n = UInt(N:Vn);  m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 0 1 1 1 0 0 D 0 0                Vn          Vd         1 0 1 sz N 1 M 0            Vm




Single-precision scalar variant

Applies when sz = 0.

VMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;  dp_operation = (sz == '1');  add = (op == '0');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        Assembler symbols

        <c>               For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
                          Advanced SIMD VMLA or VMLS instruction must be unconditional. ARM strongly recommends that a
                          T32 Advanced SIMD VMLA or VMLS instruction is unconditional, see Conditional execution on
                          page F2-2507.

                          For encoding T2: see Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
               if advsimd then    // Advanced SIMD instruction
                   for r = 0 to regs-1
                        for e = 0 to elements-1
                             product = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize], StandardFPSCRValue());
                             addend = if add then product else FPNeg(product);
                             Elem[D[d+r],e,esize] = FPAdd(Elem[D[d+r],e,esize], addend, StandardFPSCRValue());
               else               // VFP instruction
                   if dp_operation then
                        addend64 = if add then FPMul(D[n], D[m], FPSCR) else FPNeg(FPMul(D[n], D[m], FPSCR));
                        D[d] = FPAdd(D[d], addend64, FPSCR);
                   else
                        addend32 = if add then FPMul(S[n], S[m], FPSCR) else FPNeg(FPMul(S[n], S[m], FPSCR));
                        S[d] = FPAdd(S[d], addend32, FPSCR);


platform: ARM
mnem: VMLSL
description:
Vector Multiply Subtract Long multiplies corresponding elements in two vectors, and subtract the products from       (F8.1.114)
the corresponding elements of the destination vector. The destination vector element is twice as long as the elements
that are multiplied.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 U 1 D !=11                   Vn            Vd       1 0 1 0 N 0 M 0              Vm
                                    size                                    op


A1 variant

VMLSL{<c>}{<q>}.<type><size> <Qd>, <Dn>, <Dm>// Encoding T2/A2


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 add = (op == '0');     long_destination = TRUE;     unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);     regs = 1;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15       12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 U 1 1 1 1 1 D !=11                   Vn            Vd       1 0 1 0 N 0 M 0              Vm
                                    size                                    op


T1 variant

VMLSL{<c>}{<q>}.<type><size> <Qd>, <Dn>, <Dm>// Encoding T2/A2


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 add = (op == '0');     long_destination = TRUE;     unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);     regs = 1;


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 Advanced SIMD VMLA, VMLAL, VMLS,
                or VMLSL instruction must be unconditional. ARM strongly recommends that a T32 Advanced SIMD
                VMLA, VMLAL, VMLS, or VMLSL instruction is unconditional, see Conditional execution on page F2-2507.
        <q>               See Standard assembler syntax fields on page F2-2506.

        <type>            The data type for the elements of the operands. It must be one of:

                          S           Optional in encoding T1/A1. Encoded as U = 0 in encoding T2/A2.

                          U           Optional in encoding T1/A1. Encoded as U = 1 in encoding T2/A2.

                          I           Available only in encoding T1/A1.

        <size>            The data size for the elements of the operands. It must be one of:

                          8           Encoded as size = 0b00.

                          16          Encoded as size = 0b01.

                          32          Encoded as size = 0b10.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        product = Int(Elem[Din[n+r],e,esize],unsigned) * Int(Elem[Din[m+r],e,esize],unsigned);
                        addend = if add then product else -product;
                        if long_destination then
                             Elem[Q[d>>1],e,2*esize] = Elem[Qin[d>>1],e,2*esize] + addend;
                        else
                             Elem[D[d+r],e,esize] = Elem[Din[d+r],e,esize] + addend;


platform: ARM
mnem: VMOV
description:
Copy two general-purpose registers to or from a SIMD&FP register copies two words from two general-purpose       (F8.1.116)
registers into a doubleword register in the Advanced SIMD and floating-point register file, or from a doubleword
register in the Advanced SIMD and floating-point register file to two general-purpose registers.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31         28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                0
     !=1111      1 1 0 0 0 1 0 op            Rt2          Rt       1 0 1 1 0 0 M 1              Vm
      cond


Encoding

Applies when op = 1.

VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm>


Encoding

Applies when op = 0.

VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2>


Decode for all variants of this encoding

 to_arm_registers = (op == '1');      t = UInt(Rt);   t2 = UInt(Rt2);     m = UInt(M:Vm);
 if t == 15 || t2 == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
 if to_arm_registers && t == t2 then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 0 1 1 0 0 0 1 0 op                   Rt2          Rt       1 0 1 1 0 0 M 1              Vm




Encoding

Applies when op = 1.

VMOV{<c>}{<q>} <Rt>, <Rt2>, <Dm>


Encoding

Applies when op = 0.

VMOV{<c>}{<q>} <Dm>, <Rt>, <Rt2>


Decode for all variants of this encoding

 to_arm_registers = (op == '1');      t = UInt(Rt);   t2 = UInt(Rt2);     m = UInt(M:Vm);
 if t == 15 || t2 == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13
 if to_arm_registers && t == t2 then UNPREDICTABLE;
        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMOV (between two general-purpose
        registers and a doubleword floating-point register) on page J1-5390.


        Assembler symbols

        <Dm>              Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "M:Vm" field.

        <Rt2>             Is the first general-purpose register that <Dm>[63:32] will be transferred to or from, encoded in the
                          "Rt" field.

        <Rt>              Is the first general-purpose register that <Dm>[31:0] will be transferred to or from, encoded in the "Rt"
                          field.

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckVFPEnabled(TRUE);
               if to_arm_registers then
                   R[t] = D[m]<31:0>;
                   R[t2] = D[m]<63:32>;
               else
                   D[m]<31:0> = R[t];
                   D[m]<63:32> = R[t2];


platform: ARM
mnem: VMOVL
description:
        Vector Move Long takes each element in a doubleword vector, sign or zero-extends them to twice their original       (F8.1.124)
        length, and places the results in a quadword vector.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21      19 18 17 16 15        12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 U 1 D              !=000   0 0 0         Vd      1 0 1 0 0 0 M 1             Vm
                                            imm3H


        A1 variant

        VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm>


        Decode for this encoding

         if imm3 == '000' then SEE "Related encodings";
         if imm3 != '001' && imm3 != '010' && imm3 != '100' then SEE VSHLL;
         if Vd<0> == '1' then UNDEFINED;
         esize = 8 * UInt(imm3);
         unsigned = (U == '1');      elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5            3 2 1 0 15           12 11 10 9 8 7 6 5 4 3               0
            1 1 1 U 1 1 1 1 1 D              !=000   0 0 0         Vd      1 0 1 0 0 0 M 1             Vm
                                            imm3H


        T1 variant

        VMOVL{<c>}{<q>}.<dt> <Qd>, <Dm>


        Decode for this encoding

         if imm3 == '000' then SEE "Related encodings";
         if imm3 != '001' && imm3 != '010' && imm3 != '100' then SEE VSHLL;
         if Vd<0> == '1' then UNDEFINED;
         esize = 8 * UInt(imm3);
         unsigned = (U == '1');      elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VMOVL instruction must be
                          unconditional. ARM strongly recommends that a T32 VMOVL instruction is unconditional, see
                          Conditional execution on page F2-2507.
<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          The data type for the elements of the operand. It must be one of:

              S8          Encoded as U = 0, imm3 = 0b001.

              S16         Encoded as U = 0, imm3 = 0b010.

              S32         Encoded as U = 0, imm3 = 0b100.

              U8          Encoded as U = 1, imm3 = 0b001.

              U16         Encoded as U = 1, imm3 = 0b010.

              U32         Encoded as U = 1, imm3 = 0b100.



<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Int(Elem[Din[m],e,esize], unsigned);
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;


platform: ARM
mnem: VMOVN
description:
        Vector Move and Narrow copies the least significant half of each element of a quadword vector into the       (F8.1.125)
        corresponding elements of a doubleword vector.

        The operand vector elements can be any one of 16-bit, 32-bit, or 64-bit integers. There is no distinction between
        signed and unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.

        This instruction is used by the aliases VRSHRN (zero) and VSHRN (zero). See the Alias conditions on
        page F8-3543 table for details of when each alias is preferred.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                       Vd      0 0 1 0 0 0 M 0              Vm




        A1 variant

        VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>


        Decode for this encoding

         if size == '11' then UNDEFINED;
         if Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                       Vd      0 0 1 0 0 0 M 0              Vm




        T1 variant

        VMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>


        Decode for this encoding

         if size == '11' then UNDEFINED;
         if Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);
Alias conditions


                    Alias                    is preferred when

                    VRSHRN (zero)            Never

                    VSHRN (zero)             Never



Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VMOVN instruction must be
              unconditional. ARM strongly recommends that a T32 VMOVN instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operand, encoded in the "size" field. It can have the following
              values:

              I16          when size = 00

              I32          when size = 01

              I64          when size = 10

              It is RESERVED when size = 11.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        Elem[D[d],e,esize] = Elem[Qin[m>>1],e,2*esize]<esize-1:0>;


platform: ARM
mnem: VMRS
description:
        Move SIMD&FP Special register to general-purpose register moves the value of an Advanced SIMD and       (F8.1.126)
        floating-point System register to a general-purpose register. When the specified System register is the FPSCR, a
        form of the instruction transfers the FPSCR.{N, Z, C, V} condition flags to the The Application Program Status
        Register, APSR on page E1-2382.{N, Z, C, V} condition flags.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        When these settings permit the execution of floating-point and Advanced SIMD instructions, if the specified
        floating-point System register is not the FPSCR, the instruction is UNDEFINED if executed in User mode.

        In an implementation that includes EL2, when HCR.TID0 is set to 1, any VMRS access to FPSID from a Non-secure
        EL1 mode that would be permitted if HCR.TID0 was set to 0 generates a Hyp Trap exception. For more information,
        see ID group 0, Primary device identification registers on page G1-3917.

        For simplicity, the VMRS pseudocode does not show the possible trap to Hyp mode.


        A1


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3 2 1 0
              !=1111     1 1 1 0 1 1 1 1             reg          Rt       1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0)
               cond


        A1 variant

        VMRS{<c>}{<q>} <Rt>, <spec_reg>


        Decode for this encoding

         t = UInt(Rt);
         if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;
         if t == 15 && reg != '0001' then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
            1 1 1 0 1 1 1 0 1 1 1 1                  reg          Rt       1 0 1 0 0 (0) (0) 1 (0) (0) (0) (0)




        T1 variant

        VMRS{<c>}{<q>} <Rt>, <spec_reg>


        Decode for this encoding

         t = UInt(Rt);
         if !(reg IN {'000x', '0101', '011x', '1000'}) then UNPREDICTABLE;
         if t == 15 && reg != '0001' then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMRS on page J1-5390.
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Rt>          Is the general-purpose destination register, encoded in the "Rt" field. Is one of:

              R0-R14      General-purpose register.

              APSR_nzcv   If <spec_reg> is FPSCR, encoded as 0b1111. This instruction transfers the FPSCR.{N, Z,
                          C, V} condition flags to the APSR.{N, Z, C, V} condition flags.

<spec_reg>    Is the source Advanced SIMD and floating-point System register, encoded in the "reg" field. It can
              have the following values:

              FPSID       when reg = 0000

              FPSCR       when reg = 0001

              MVFR2       when reg = 0101

              MVFR1       when reg = 0110

              MVFR0       when reg = 0111

              FPEXC       when reg = 1000

              It is RESERVED when:

              .      reg = 001x.

              .      reg = 0100.

              .      reg = 1001.

              .      reg = 101x.

              .      reg = 11xx.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    if reg == '0001' then                    // FPSCR
        CheckVFPEnabled(TRUE);
        if t == 15 then
            PSTATE.<N,Z,C,V> = FPSR.<N,Z,C,V>;
        else
            R[t] = FPSCR;
    elsif PSTATE.EL == EL0 then
        UNDEFINED;                           // Non-FPSCR registers accessible only at PL1 or above
    else
        CheckVFPEnabled(FALSE);              // Non-FPSCR registers are not affected by FPEXC.EN
        case reg of
            // Pseudocode does not consider possible HCR.TIDn Hyp Traps of Non-secure register reads
            when '0000'   R[t] = FPSID;
            when '0101'   R[t] = MVFR2;
            when '0110'   R[t] = MVFR1;
            when '0111'   R[t] = MVFR0;
            when '1000'   R[t] = FPEXC;
            otherwise     Unreachable();     // Dealt with above or in encoding-specific pseudocode


platform: ARM
mnem: VMSR
description:
        Move general-purpose register to SIMD&FP Special register moves the value of a general-purpose register to a       (F8.1.127)
        floating-point System register.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        When these settings permit the execution of floating-point and Advanced SIMD instructions:

        .       If the specified floating-point System register is not the FPSCR, the instruction is UNDEFINED if executed in
                User mode.

        .       If the specified floating-point System register is the FPEXC and the instruction is executed in a mode other
                than User mode the instruction is ignored.


        A1


           31        28 27 26 25 24 23 22 21 20 19          16 15         12 11 10 9 8 7 6 5 4 3 2 1 0
              !=1111     1 1 1 0 1 1 1 0              reg            Rt      1 0 1 0 (0) (0) (0) 1 (0) (0) (0) (0)
               cond


        A1 variant

        VMSR{<c>}{<q>} <spec_reg>, <Rt>


        Decode for this encoding

         t = UInt(Rt);
         if reg != '000x' && reg != '1000' then UNPREDICTABLE;
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15         12 11 10 9 8 7 6 5 4 3 2 1 0
            1 1 1 0 1 1 1 0 1 1 1 0                   reg            Rt      1 0 1 0 0 (0) (0) 1 (0) (0) (0) (0)




        T1 variant

        VMSR{<c>}{<q>} <spec_reg>, <Rt>


        Decode for this encoding

         t = UInt(Rt);
         if reg != '000x' && reg != '1000' then UNPREDICTABLE;
         if t == 15 then UNPREDICTABLE; // ARMv8-A removes UNPREDICTABLE for R13


        Notes for all encodings

        For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
        Architectural Constraints on UNPREDICTABLE behaviors, and particularly VMSR on page J1-5390.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.
<spec_reg>    Is the destination Advanced SIMD and floating-point System register, encoded in the "reg" field. It
              can have the following values:

              FPSID       when reg = 0000

              FPSCR       when reg = 0001

              FPEXC       when reg = 1000

              It is RESERVED when:

              .      reg = 001x.

              .      reg = 01xx.

              .      reg = 1001.

              .      reg = 101x.

              .      reg = 11xx.

<Rt>          Is the general-purpose source register, encoded in the "Rt" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();
    if reg == '0001' then                   // FPSCR
        CheckVFPEnabled(TRUE);
        FPSCR = R[t];
    elsif PSTATE.EL == EL0 then
        UNDEFINED;                          // Non-FPSCR registers accessible only at PL1 or above
    else
        CheckVFPEnabled(FALSE);             // Non-FPSCR registers are not affected by FPEXC.EN
        case reg of
            when '0000'                     // VMSR access to FPSID is ignored
            when '1000'    FPEXC = R[t];
            otherwise      Unreachable();   // Dealt with above or in encoding-specific pseudocode


platform: ARM
mnem: VMUL
description:
        Vector Multiply multiplies corresponding elements in two vectors, and places the results in the destination vector.       (F8.1.128)

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 1 0 D 0 0                   Vn          Vd       1 1 0 1 N Q M 1            Vm
                                              sz


        64-bit SIMD vector variant

        Applies when Q = 0.

        VMUL{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMUL{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         advsimd = TRUE;     esize = 32;  elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        A2


           31        28 27 26 25 24 23 22 21 20 19        16 15        12 11 10 9 8 7 6 5 4 3                0
              !=1111     1 1 1 0 0 D 1 0              Vn          Vd       1 0 1 sz N 0 M 0           Vm
               cond


        Single-precision scalar variant

        Applies when sz = 0.

        VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE;     dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3              0 15        12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 1 1 1 1 1 0 D 0 sz                Vn          Vd         1 1 0 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when sz = 0 && Q = 0.

VMUL{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VMUL{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 advsimd = TRUE;  esize = 32;  elements = 2;
 d = UInt(D:Vd);  n = UInt(N:Vn);   m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3              0 15        12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 0 1 1 1 0 0 D 1 0                 Vn          Vd         1 0 1 sz N 0 M 0             Vm




Single-precision scalar variant

Applies when sz = 0.

VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;  dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


Assembler symbols

<c>           For encoding A1, A2 and T1: see Standard assembler syntax fields on page F2-2506. An A32
              Advanced SIMD VMUL instruction must be unconditional. ARM strongly recommends that a T32
              Advanced SIMD VMUL instruction is unconditional, see Conditional execution on page F2-2507.

              For encoding T2: see Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.
        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
               if advsimd then    // Advanced SIMD instruction
                   for r = 0 to regs-1
                        for e = 0 to elements-1
                             Elem[D[d+r],e,esize] = FPMul(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
        StandardFPSCRValue());
               else               // VFP instruction
                   if dp_operation then
                        D[d] = FPMul(D[n], D[m], FPSCR);
                   else
                        S[d] = FPMul(S[n], S[m], FPSCR);


platform: ARM
mnem: VMULL
description:
        Vector Multiply Long multiplies corresponding elements in two vectors. The destination vector elements are twice       (F8.1.131)
        as long as the elements that are multiplied.

        For information about multiplying polynomials see Polynomial arithmetic over {0, 1} on page A1-45.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 U 1 D !=11                  Vn           Vd      1 1 op 0 N 0 M 0            Vm
                                           size


        A1 variant

        VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         unsigned = (U == '1'); polynomial = (op == '1'); long_destination = TRUE;
         esize = 8 << UInt(size); elements = 64 DIV esize;
         if polynomial then
               if U == '1' || size == '01' then UNDEFINED;
               if size == '10' then      // .p64
                   if !HaveCryptoExt() then UNDEFINED;
                   if InITBlock() then UNPREDICTABLE;
                   esize = 64; elements = 1;
         if Vd<0> == '1' then UNDEFINED;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = 1;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 U 1 1 1 1 1 D !=11                  Vn           Vd      1 1 op 0 N 0 M 0            Vm
                                           size


        T1 variant

        VMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         unsigned = (U == '1'); polynomial = (op == '1'); long_destination = TRUE;
         esize = 8 << UInt(size); elements = 64 DIV esize;
         if polynomial then
               if U == '1' || size == '01' then UNDEFINED;
               if size == '10' then      // .p64
                   if !HaveCryptoExt() then UNDEFINED;
                   if InITBlock() then UNPREDICTABLE;
                   esize = 64; elements = 1;
         if Vd<0> == '1' then UNDEFINED;
         d = UInt(D:Vd); n = UInt(N:Vn); m = UInt(M:Vm); regs = 1;
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 Advanced SIMD VMUL or VMULL
               instruction must be unconditional. ARM strongly recommends that a T32 Advanced SIMD VMUL or
               VMULL instruction is unconditional, see Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<dt>           Is the data type for the elements of the operands, encoded in the "op:U:size" field. It can have the
               following values:

               S8           when op = 0, U = 0, size = 00

               S16          when op = 0, U = 0, size = 01

               S32          when op = 0, U = 0, size = 10

               U8           when op = 0, U = 1, size = 00

               U16          when op = 0, U = 1, size = 01

               U32          when op = 0, U = 1, size = 10

               P8           when op = 1, U = 0, size = 00

               P64          when op = 1, U = 0, size = 10

               It is RESERVED when:

               .      op = 0, U = 0, size = 11.

               .      op = 0, U = 1, size = 11.

               .      op = 1, U = 0, size = 01.

               .      op = 1, U = 0, size = 11.

               .      op = 1, U = 1, size = xx.

<Qd>           Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dn>           Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>           Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();      CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
              op1 = Elem[Din[n+r],e,esize];     op1val = Int(op1, unsigned);
              op2 = Elem[Din[m+r],e,esize];     op2val = Int(op2, unsigned);
              if polynomial then
                  product = PolynomialMult(op1,op2);
              else
                  product = (op1val*op2val)<2*esize-1:0>;
              if long_destination then
                  Elem[Q[d>>1],e,2*esize] = product;
              else
                  Elem[D[d+r],e,esize] = product<esize-1:0>;


platform: ARM
mnem: VMVN
description:
        Vector Bitwise NOT (immediate) places the bitwise inverse of an immediate integer constant into every element of       (F8.1.133)
        the destination register.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18       16 15       12 11       8 7 6 5 4 3              0
            1 1 1 1 0 0 1 i 1 D 0 0 0                 imm3         Vd        cmode    0 Q 1 1         imm4




        64-bit SIMD vector variant

        Applies when Q = 0.

        VMVN{<c>}{<q>}.<dt> <Dd>, #<imm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMVN{<c>}{<q>}.<dt> <Qd>, #<imm>


        Decode for all variants of this encoding

         if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings";
         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4);
         d = UInt(D:Vd);     regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2                0 15       12 11       8 7 6 5 4 3              0
            1 1 1 i 1 1 1 1 1 D 0 0 0                 imm3         Vd        cmode    0 Q 1 1         imm4




        64-bit SIMD vector variant

        Applies when Q = 0.

        VMVN{<c>}{<q>}.<dt> <Dd>, #<imm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VMVN{<c>}{<q>}.<dt> <Qd>, #<imm>


        Decode for all variants of this encoding

         if (cmode<0> == '1' && cmode<3:2> != '11') || cmode<3:1> == '111' then SEE "Related encodings";
         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         imm64 = AdvSIMDExpandImm('1', cmode, i:imm3:imm4);
         d = UInt(D:Vd);     regs = if Q == '0' then 1 else 2;
Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VMVN instruction must be
              unconditional. ARM strongly recommends that a T32 VMVN instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          The data type. It must be either I16 or I32.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<imm>         Is a constant of the type specified by <dt> that is replicated to fill the destination register. For details
              of the range of constants available and the encoding of <dt> and <imm>, see One register and a
              modified immediate value on page F5-2596.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();    CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         D[d+r] = NOT(imm64);


platform: ARM
mnem: VNEG
description:
        Vector Negate negates each element in a vector, and places the results in a second vector. The floating-point version       (F8.1.135)
        only inverts the sign bit.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 1                      Vd       0 F 1 1 1 Q M 0               Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VNEG{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VNEG{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' || (F == '1' && size != '10') then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         advsimd = TRUE;     floating_point = (F == '1');
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


        A2


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15         12 11 10 9 8 7 6 5 4 3                  0
              !=1111     1 1 1 0 1 D 1 1 0 0 0 1                  Vd       1 0 1 sz 0 1 M 0              Vm
               cond


        Single-precision scalar variant

        Applies when sz = 0.

        VNEG{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VNEG{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         advsimd = FALSE;     dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                 12 11 10 9 8 7 6 5 4 3                 0
  1 1 1 1 1 1 1 1 1 D 1 1 size 0 1                    Vd        0 F 1 1 1 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VNEG{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VNEG{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' || (F == '1' && size != '10') then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 advsimd = TRUE;  floating_point = (F == '1');
 esize = 8 << UInt(size);  elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                 12 11 10 9 8 7 6 5 4 3                 0
  1 1 1 0 1 1 1 0 1 D 1 1 0 0 0 1                     Vd        1 0 1 sz 0 1 M 0             Vm




Single-precision scalar variant

Applies when sz = 0.

VNEG{<c>}{<q>}.F32 <Sd>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNEG{<c>}{<q>}.F64 <Dd>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 advsimd = FALSE;  dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 Advanced SIMD VNEG instruction
              must be unconditional. ARM strongly recommends that a T32 Advanced SIMD VNEG instruction is
              unconditional, see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.
        <dt>              Is the data type for the elements of the vectors, encoded in the "F:size" field. It can have the
                          following values:

                          S8           when F = 0, size = 00

                          S16          when F = 0, size = 01

                          S32          when F = 0, size = 10

                          F32          when F = 1, size = 10

                          It is RESERVED when:

                          .      F = 0, size = 11.

                          .      F = 1, size = 0x.

                          .      F = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sm>              Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
               if advsimd then    // Advanced SIMD instruction
                   for r = 0 to regs-1
                        for e = 0 to elements-1
                             if floating_point then
                                 Elem[D[d+r],e,esize] = FPNeg(Elem[D[m+r],e,esize]);
                             else
                                 result = -SInt(Elem[D[m+r],e,esize]);
                                 Elem[D[d+r],e,esize] = result<esize-1:0>;
               else               // VFP instruction
                   if dp_operation then
                        D[d] = FPNeg(D[m]);
                   else
                        S[d] = FPNeg(S[m]);


platform: ARM
mnem: VNMLA
description:
Vector Negate Multiply Accumulate multiplies together two floating-point register values, adds the negation of the       (F8.1.136)
floating-point value in the destination register to the negation of the product, and writes the result back to the
destination register.

         Note
ARM recommends that software does not use the VNMLA instruction in the Round towards Plus Infinity and Round
towards Minus Infinity rounding modes, because the rounding of the product and of the sum can change the result
of the instruction in opposite directions, defeating the purpose of these rounding modes.


Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31        28 27 26 25 24 23 22 21 20 19           16 15        12 11 10 9 8 7 6 5 4 3                  0
     !=1111     1 1 1 0 0 D 0 1               Vn           Vd        1 0 1 sz N 1 M 0              Vm
      cond                                                                            op


Single-precision scalar variant

Applies when sz = 0.

VNMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 0 1 1 1 0 0 D 0 1                    Vn           Vd        1 0 1 sz N 1 M 0              Vm
                                                                                      op


Single-precision scalar variant

Applies when sz = 0.

VNMLA{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMLA{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>
        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL};

         if ConditionPassed() then
               EncodingSpecificOperations();     CheckVFPEnabled(TRUE);
               if dp_operation then
                   product64 = FPMul(D[n], D[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR);
                        when VFPNegMul_VNMLS    D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR);
                        when VFPNegMul_VNMUL    D[d] = FPNeg(product64);
               else
                   product32 = FPMul(S[n], S[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR);
                        when VFPNegMul_VNMLS    S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR);
                        when VFPNegMul_VNMUL    S[d] = FPNeg(product32);


platform: ARM
mnem: VNMLS
description:
Vector Negate Multiply Subtract multiplies together two floating-point register values, adds the negation of the       (F8.1.137)
floating-point value in the destination register to the product, and writes the result back to the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31       28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                  0
     !=1111    1 1 1 0 0 D 0 1                Vn            Vd       1 0 1 sz N 0 M 0              Vm
      cond                                                                            op


Single-precision scalar variant

Applies when sz = 0.

VNMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 0 1 1 1 0 0 D 0 1                    Vn            Vd       1 0 1 sz N 0 M 0              Vm
                                                                                      op


Single-precision scalar variant

Applies when sz = 0.

VNMLS{<c>}{<q>}.F32 <Sd>, <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMLS{<c>}{<q>}.F64 <Dd>, <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 type = if op == '1' then VFPNegMul_VNMLA else VFPNegMul_VNMLS;
 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL};

         if ConditionPassed() then
               EncodingSpecificOperations();     CheckVFPEnabled(TRUE);
               if dp_operation then
                   product64 = FPMul(D[n], D[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR);
                        when VFPNegMul_VNMLS    D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR);
                        when VFPNegMul_VNMUL    D[d] = FPNeg(product64);
               else
                   product32 = FPMul(S[n], S[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR);
                        when VFPNegMul_VNMLS    S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR);
                        when VFPNegMul_VNMUL    S[d] = FPNeg(product32);


platform: ARM
mnem: VNMUL
description:
Vector Negate Multiply multiplies together two floating-point register values, and writes the negation of the result       (F8.1.138)
to the destination register.

Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                0
     !=1111     1 1 1 0 0 D 1 0              Vn           Vd       1 0 1 sz N 1 M 0             Vm
      cond


Single-precision scalar variant

Applies when sz = 0.

VNMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 type = VFPNegMul_VNMUL;
 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15         12 11 10 9 8 7 6 5 4 3                0
   1 1 1 0 1 1 1 0 0 D 1 0                   Vn           Vd       1 0 1 sz N 1 M 0             Vm




Single-precision scalar variant

Applies when sz = 0.

VNMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm>


Double-precision scalar variant

Applies when sz = 1.

VNMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm>


Decode for all variants of this encoding

 if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
 type = VFPNegMul_VNMUL;
 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         enumeration VFPNegMul {VFPNegMul_VNMLA, VFPNegMul_VNMLS, VFPNegMul_VNMUL};

         if ConditionPassed() then
               EncodingSpecificOperations();     CheckVFPEnabled(TRUE);
               if dp_operation then
                   product64 = FPMul(D[n], D[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    D[d] = FPAdd(FPNeg(D[d]), FPNeg(product64), FPSCR);
                        when VFPNegMul_VNMLS    D[d] = FPAdd(FPNeg(D[d]), product64, FPSCR);
                        when VFPNegMul_VNMUL    D[d] = FPNeg(product64);
               else
                   product32 = FPMul(S[n], S[m], FPSCR);
                   case type of
                        when VFPNegMul_VNMLA    S[d] = FPAdd(FPNeg(S[d]), FPNeg(product32), FPSCR);
                        when VFPNegMul_VNMLS    S[d] = FPAdd(FPNeg(S[d]), product32, FPSCR);
                        when VFPNegMul_VNMUL    S[d] = FPNeg(product32);


platform: ARM
mnem: VORN
description:
Vector Bitwise OR NOT (immediate) performs a bitwise OR between a register value and the complement of an       (F8.1.139)
immediate value, and returns the result into the destination vector

This instruction is an alias of the VORR (immediate) instruction. This means that:

.      The encodings in this description are named to match the encodings of VORR (immediate).

.      The description of VORR (immediate) gives the operational pseudocode for this instruction.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18       16 15        12 11           8 7 6 5 4 3            0
   1 1 1 1 0 0 1 i 1 D 0 0 0                  imm3        Vd          cmode       0 Q 0 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VORN{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.<dt> <Dd>, #~<imm>

and is never the preferred disassembly.

128-bit SIMD vector variant

Applies when Q = 1.

VORN{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.<dt> <Qd>, #~<imm>

and is never the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2                0 15        12 11           8 7 6 5 4 3            0
   1 1 1 i 1 1 1 1 1 D 0 0 0                  imm3        Vd          cmode       0 Q 0 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VORN{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>

is equivalent to

VORR{<c>}{<q>}.<dt> <Dd>, #~<imm>

and is never the preferred disassembly.

128-bit SIMD vector variant

Applies when Q = 1.

VORN{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>
        is equivalent to

        VORR{<c>}{<q>}.<dt> <Qd>, #~<imm>

        and is never the preferred disassembly.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VORR instruction must be
                          unconditional. ARM strongly recommends that a T32 VORR instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              The data type used for <imm>. It can be either I16 or I32. I8, I64, and F32 are also permitted, but the
                          resulting syntax is a pseudo-instruction.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <imm>             Is a constant of the type specified by <dt> that is replicated to fill the destination register. For details
                          of the range of constants available and the encoding of <dt> and <imm>, see One register and a
                          modified immediate value on page F5-2596.


        Operation for all encodings

        The description of VORR (immediate) gives the operational pseudocode for this instruction.


platform: ARM
mnem: VORR
description:
Vector Bitwise OR (immediate) performs a bitwise OR between a register value and an immediate value, and       (F8.1.141)
returns the result into the destination vector.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.

This instruction is used by the alias VORN (immediate). See the Alias conditions on page F8-3578 table for details
of when each alias is preferred.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18        16 15       12 11            8 7 6 5 4 3            0
   1 1 1 1 0 0 1 i 1 D 0 0 0                   imm3        Vd          cmode       0 Q 0 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VORR{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>


128-bit SIMD vector variant

Applies when Q = 1.

VORR{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>


Decode for all variants of this encoding

 if cmode<0> == '0' || cmode<3:2> == '11' then SEE VMOV (immediate);
 if Q == '1' && Vd<0> == '1' then UNDEFINED;
 imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4);
 d = UInt(D:Vd);     regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2                 0 15       12 11            8 7 6 5 4 3            0
   1 1 1 i 1 1 1 1 1 D 0 0 0                   imm3        Vd          cmode       0 Q 0 1       imm4




64-bit SIMD vector variant

Applies when Q = 0.

VORR{<c>}{<q>}.<dt> {<Dd>,} <Dd>, #<imm>


128-bit SIMD vector variant

Applies when Q = 1.

VORR{<c>}{<q>}.<dt> {<Qd>,} <Qd>, #<imm>
        Decode for all variants of this encoding

         if cmode<0> == '0' || cmode<3:2> == '11' then SEE VMOV (immediate);
         if Q == '1' && Vd<0> == '1' then UNDEFINED;
         imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4);
         d = UInt(D:Vd);      regs = if Q == '0' then 1 else 2;


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Alias conditions


                               Alias                     is preferred when

                               VORN (immediate)          Never



        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VORR instruction must be
                          unconditional. ARM strongly recommends that a T32 VORR instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              The data type used for <imm>. It can be either I16 or I32. I8, I64, and F32 are also permitted, but the
                          resulting syntax is a pseudo-instruction.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <imm>             Is a constant of the type specified by <dt> that is replicated to fill the destination register. For details
                          of the range of constants available and the encoding of <dt> and <imm>, see One register and a
                          modified immediate value on page F5-2596.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   D[d+r] = D[d+r] OR imm64;


platform: ARM
mnem: VPADAL
description:
Vector Pairwise Add and Accumulate Long adds adjacent pairs of elements of a vector, and accumulates the results       (F8.1.143)
into the elements of the destination vector.

The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The
result elements are twice the length of the operand elements.

The following figure shows an example of the operation of VPADAL doubleword operation for data type S16.

                                                                                 Dm




                                                                                            +             +




                                                                                 Dd

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                        Vd       0 1 1 0 op Q M 0             Vm




64-bit SIMD vector variant

Applies when Q = 0.

VPADAL{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VPADAL{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 unsigned = (op == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                        Vd       0 1 1 0 op Q M 0             Vm
        64-bit SIMD vector variant

        Applies when Q = 0.

        VPADAL{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VPADAL{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         unsigned = (op == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VPADAL instruction must be
                          unconditional. ARM strongly recommends that a T32 VPADAL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the vectors, encoded in the "op:size" field. It can have the
                          following values:

                          S8           when op = 0, size = 00

                          S16          when op = 0, size = 01

                          S32          when op = 0, size = 10

                          U8           when op = 1, size = 00

                          U16          when op = 1, size = 01

                          U32          when op = 1, size = 10

                          It is RESERVED when:

                          .      op = 0, size = 11.

                          .      op = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               h = elements DIV 2;

               for r = 0 to regs-1
                   for e = 0 to h-1
                        op1 = Elem[D[m+r],2*e,esize];      op2 = Elem[D[m+r],2*e+1,esize];
                        result = Int(op1, unsigned) + Int(op2, unsigned);
                        Elem[D[d+r],e,2*esize] = Elem[D[d+r],e,2*esize] + result;


platform: ARM
mnem: VPADD
description:
Vector Pairwise Add (floating-point) adds adjacent pairs of elements of two vectors, and places the results in the       (F8.1.144)
destination vector.

The operands and result are doubleword vectors.

The operand and result elements are 32-bit floating-point numbers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 0 D 0 sz                   Vn           Vd        1 1 0 1 N Q M 0              Vm




A1 variant

VPADD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 esize = 32;    elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 1 1 1 1 0 D 0 sz                   Vn           Vd        1 1 0 1 N Q M 0              Vm




T1 variant

VPADD{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 esize = 32;    elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VPADD instruction must be
                unconditional. ARM strongly recommends that a T32 VPADD instruction is unconditional, see
                Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();   CheckAdvSIMDEnabled();
               bits(64) dest;
               h = elements DIV 2;

               for e = 0 to h-1
                   Elem[dest,e,esize]   = FPAdd(Elem[D[n],2*e,esize], Elem[D[n],2*e+1,esize],
        StandardFPSCRValue());
                   Elem[dest,e+h,esize] = FPAdd(Elem[D[m],2*e,esize], Elem[D[m],2*e+1,esize],
        StandardFPSCRValue());

               D[d] = dest;


platform: ARM
mnem: VPADDL
description:
Vector Pairwise Add Long adds adjacent pairs of elements of two vectors, and places the results in the destination       (F8.1.146)
vector.

The vectors can be doubleword or quadword. The operand elements can be 8-bit, 16-bit, or 32-bit integers. The
result elements are twice the length of the operand elements.

The following figure shows an example of the operation of VPADDL doubleword operation for data type S16.

                                                                                  Dm




                                                                                             +             +




                                                                                  Dd

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                        Vd       0 0 1 0 op Q M 0             Vm




64-bit SIMD vector variant

Applies when Q = 0.

VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 unsigned = (op == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                 0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                        Vd       0 0 1 0 op Q M 0             Vm
        64-bit SIMD vector variant

        Applies when Q = 0.

        VPADDL{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VPADDL{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         unsigned = (op == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VPADDL instruction must be
                          unconditional. ARM strongly recommends that a T32 VPADDL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the vectors, encoded in the "op:size" field. It can have the
                          following values:

                          S8           when op = 0, size = 00

                          S16          when op = 0, size = 01

                          S32          when op = 0, size = 10

                          U8           when op = 1, size = 00

                          U16          when op = 1, size = 01

                          U32          when op = 1, size = 10

                          It is RESERVED when:

                          .      op = 0, size = 11.

                          .      op = 1, size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               h = elements DIV 2;

               for r = 0 to regs-1
                   for e = 0 to h-1
                        op1 = Elem[D[m+r],2*e,esize];      op2 = Elem[D[m+r],2*e+1,esize];
                        result = Int(op1, unsigned) + Int(op2, unsigned);
                        Elem[D[d+r],e,2*esize] = result<2*esize-1:0>;


platform: ARM
mnem: VPMAX
description:
Vector Pairwise Maximum compares adjacent pairs of elements in two doubleword vectors, and copies the larger       (F8.1.147)
of each pair into the corresponding element in the destination doubleword vector.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 0 D 0 0                    Vn           Vd        1 1 1 1 N 0 M 0              Vm
                                   op sz                                              Q


A1 variant

VPMAX{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 maximum = (op == '0');      esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 1 1 1 1 0 D 0 0                    Vn           Vd        1 1 1 1 N 0 M 0              Vm
                                   op sz                                              Q


T1 variant

VPMAX{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 maximum = (op == '0');      esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VPMAX or VPMIN instruction must be
                unconditional. ARM strongly recommends that a T32 VPMAX or VPMIN instruction is unconditional,
                see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();   CheckAdvSIMDEnabled();
               bits(64) dest;
               h = elements DIV 2;

               for e = 0 to h-1
                   op1 = Elem[D[n],2*e,esize];   op2 = Elem[D[n],2*e+1,esize];
                   Elem[dest,e,esize] = if maximum then FPMax(op1,op2,StandardFPSCRValue()) else
        FPMin(op1,op2,StandardFPSCRValue());
                   op1 = Elem[D[m],2*e,esize];   op2 = Elem[D[m],2*e+1,esize];
                   Elem[dest,e+h,esize] = if maximum then FPMax(op1,op2,StandardFPSCRValue()) else
        FPMin(op1,op2,StandardFPSCRValue());

               D[d] = dest;


platform: ARM
mnem: VPMIN
description:
Vector Pairwise Minimum compares adjacent pairs of elements in two doubleword vectors, and copies the smaller       (F8.1.149)
of each pair into the corresponding element in the destination doubleword vector.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19           16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 0 D 1 0                    Vn           Vd        1 1 1 1 N 0 M 0              Vm
                                   op sz                                              Q


A1 variant

VPMIN{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 maximum = (op == '0');      esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 1 1 1 1 0 D 1 0                    Vn           Vd        1 1 1 1 N 0 M 0              Vm
                                   op sz                                              Q


T1 variant

VPMIN{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


Decode for this encoding

 if sz == '1' || Q == '1' then UNDEFINED;
 maximum = (op == '0');      esize = 32;  elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VPMAX or VPMIN instruction must be
                unconditional. ARM strongly recommends that a T32 VPMAX or VPMIN instruction is unconditional,
                see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();   CheckAdvSIMDEnabled();
               bits(64) dest;
               h = elements DIV 2;

               for e = 0 to h-1
                   op1 = Elem[D[n],2*e,esize];   op2 = Elem[D[n],2*e+1,esize];
                   Elem[dest,e,esize] = if maximum then FPMax(op1,op2,StandardFPSCRValue()) else
        FPMin(op1,op2,StandardFPSCRValue());
                   op1 = Elem[D[m],2*e,esize];   op2 = Elem[D[m],2*e+1,esize];
                   Elem[dest,e+h,esize] = if maximum then FPMax(op1,op2,StandardFPSCRValue()) else
        FPMin(op1,op2,StandardFPSCRValue());

               D[d] = dest;


platform: ARM
mnem: VPOP
description:
Pop SIMD&FP registers from Stack loads multiple consecutive Advanced SIMD and floating-point register file       (F8.1.151)
registers from the stack

This instruction is an alias of the VLDM, VLDMDB, VLDMIA instruction. This means that:

.      The encodings in this description are named to match the encodings of VLDM, VLDMDB, VLDMIA.

.      The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


A1


  31        28 27 26 25 24 23 22 21 20 19         16 15      12 11 10 9 8 7                          0
     !=1111     1 1 0 0 1 D 1 1 1 1 0 1                   Vd       1 0 1 1                imm8
      cond                P U       W        Rn


Increment After variant

VPOP{<c>}{<q>}{.<size>} <dreglist>

is equivalent to

VLDM{<c>}{<q>}{.<size>} SP!, <dreglist>

and is always the preferred disassembly.


A2


  31        28 27 26 25 24 23 22 21 20 19         16 15      12 11 10 9 8 7                          0
     !=1111     1 1 0 0 1 D 1 1 1 1 0 1                   Vd       1 0 1 0                imm8
      cond                P U       W        Rn


Increment After variant

VPOP{<c>}{<q>}{.<size>} <sreglist>

is equivalent to

VLDM{<c>}{<q>}{.<size>} SP!, <sreglist>

and is always the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                 0 15       12 11 10 9 8 7                          0
   1 1 1 0 1 1 0 0 1 D 1 1 1 1 0 1                        Vd       1 0 1 1                imm8
                          P U       W        Rn


Increment After variant

VPOP{<c>}{<q>}{.<size>} <dreglist>

is equivalent to

VLDM{<c>}{<q>}{.<size>} SP!, <dreglist>

and is always the preferred disassembly.
        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15         12 11 10 9 8 7                              0
            1 1 1 0 1 1 0 0 1 D 1 1 1 1 0 1                            Vd       1 0 1 0                 imm8
                                    P U       W         Rn


        Increment After variant

        VPOP{<c>}{<q>}{.<size>} <sreglist>

        is equivalent to

        VLDM{<c>}{<q>}{.<size>} SP!, <sreglist>

        and is always the preferred disassembly.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers
                          being transferred.

        <sreglist>        Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must
                          contain at least one register.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The
                          list must contain at least one register, and must not contain more than 16 registers.


        Operation for all encodings

        The description of VLDM, VLDMDB, VLDMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: VPUSH
description:
Push SIMD&FP registers to Stack stores multiple consecutive registers from the Advanced SIMD and       (F8.1.152)
floating-point register file to the stack

This instruction is an alias of the VSTM, VSTMDB, VSTMIA instruction. This means that:

.      The encodings in this description are named to match the encodings of VSTM, VSTMDB, VSTMIA.

.      The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


A1


  31       28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7                          0
     !=1111     1 1 0 1 0 D 1 0 1 1 0 1                    Vd       1 0 1 1                imm8
      cond                 P U       W        Rn


Decrement Before variant

VPUSH{<c>}{<q>}{.<size>} <dreglist>

is equivalent to

VSTMDB{<c>}{<q>}{.<size>} SP!, <dreglist>

and is always the preferred disassembly.


A2


  31       28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7                          0
     !=1111     1 1 0 1 0 D 1 0 1 1 0 1                    Vd       1 0 1 0                imm8
      cond                 P U       W        Rn


Decrement Before variant

VPUSH{<c>}{<q>}{.<size>} <sreglist>

is equivalent to

VSTMDB{<c>}{<q>}{.<size>} SP!, <sreglist>

and is always the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7                          0
   1 1 1 0 1 1 0 1 0 D 1 0 1 1 0 1                         Vd       1 0 1 1                imm8
                           P U       W        Rn


Decrement Before variant

VPUSH{<c>}{<q>}{.<size>} <dreglist>

is equivalent to

VSTMDB{<c>}{<q>}{.<size>} SP!, <dreglist>

and is always the preferred disassembly.
        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15         12 11 10 9 8 7                              0
            1 1 1 0 1 1 0 1 0 D 1 0 1 1 0 1                            Vd       1 0 1 0                 imm8
                                    P U       W         Rn


        Decrement Before variant

        VPUSH{<c>}{<q>}{.<size>} <sreglist>

        is equivalent to

        VSTMDB{<c>}{<q>}{.<size>} SP!, <sreglist>

        and is always the preferred disassembly.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            An optional data size specifier. If present, it must be equal to the size in bits, 32 or 64, of the registers
                          being transferred.

        <sreglist>        Is the list of consecutively numbered 32-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "Vd:D", and "imm8" is set to the number of registers in the list. The list must
                          contain at least one register.

        <dreglist>        Is the list of consecutively numbered 64-bit SIMD&FP registers to be transferred. The first register
                          in the list is encoded in "D:Vd", and "imm8" is set to twice the number of registers in the list. The
                          list must contain at least one register, and must not contain more than 16 registers.


        Operation for all encodings

        The description of VSTM, VSTMDB, VSTMIA gives the operational pseudocode for this instruction.


platform: ARM
mnem: VQABS
description:
Vector Saturating Absolute takes the absolute value of each element in a vector, and places the results in the       (F8.1.153)
destination vector.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                        Vd        0 1 1 1 0 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQABS{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQABS{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                        Vd        0 1 1 1 0 Q M 0              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQABS{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQABS{<c>}{<q>}.<dt> <Qd>, <Qm>
        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQABS instruction must be
                          unconditional. ARM strongly recommends that a T32 VQABS instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the vectors, encoded in the "size" field. It can have the following
                          values:

                          S8           when size = 00

                          S16          when size = 01

                          S32          when size = 10

                          It is RESERVED when size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        result = Abs(SInt(Elem[D[m+r],e,esize]));
                        (Elem[D[d+r],e,esize], sat) = SignedSatQ(result, esize);
                        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQADD
description:
Vector Saturating Add adds the values of corresponding elements of two vectors, and places the results in the       (F8.1.154)
destination vector.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15      12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 0 D size                   Vn           Vd        0 0 0 0 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQADD{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQADD{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 U 1 1 1 1 0 D size                   Vn           Vd        0 0 0 0 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQADD{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQADD{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm>
        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQADD instruction must be
                          unconditional. ARM strongly recommends that a T32 VQADD instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the vectors, encoded in the "U:size" field. It can have the
                          following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          S64          when U = 0, size = 11

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

                          U64          when U = 1, size = 11

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        sum = Int(Elem[D[n+r],e,esize], unsigned) + Int(Elem[D[m+r],e,esize], unsigned);
                        (Elem[D[d+r],e,esize], sat) = SatQ(sum, esize, unsigned);
                        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQDMLAL
description:
Vector Saturating Doubling Multiply Accumulate Long multiplies corresponding elements in two doubleword       (F8.1.155)
vectors, doubles the products, and accumulates the results into the elements of a quadword vector.

The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD
scalars on page F5-2586.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15      12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 0 1 D !=11                   Vn           Vd        1 0 0 1 N 0 M 0              Vm
                                    size                                    op


A1 variant

VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 add = (op == '0');
 scalar_form = FALSE;     d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);
 esize = 8 << UInt(size);     elements = 64 DIV esize;


A2


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15      12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 0 1 D !=11                   Vn           Vd        0 0 1 1 N 1 M 0              Vm
                                    size                                op


A2 variant

VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>]


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 add = (op == '0');
 scalar_form = TRUE;     d = UInt(D:Vd);    n = UInt(N:Vn);
 if size == '01' then esize = 16;      elements = 4;    m = UInt(Vm<2:0>);      index = UInt(M:Vm<3>);
 if size == '10' then esize = 32;      elements = 2;    m = UInt(Vm);      index = UInt(M);
        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 1 1 D !=11                    Vn           Vd      1 0 0 1 N 0 M 0                 Vm
                                              size                                    op


        T1 variant

        VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         add = (op == '0');
         scalar_form = FALSE;      d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);
         esize = 8 << UInt(size);       elements = 64 DIV esize;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 1 1 D !=11                    Vn           Vd      0 0 1 1 N 1 M 0                 Vm
                                              size                             op


        T2 variant

        VQDMLAL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>]


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         add = (op == '0');
         scalar_form = TRUE;      d = UInt(D:Vd);     n = UInt(N:Vn);
         if size == '01' then esize = 16;        elements = 4;   m = UInt(Vm<2:0>);   index = UInt(M:Vm<3>);
         if size == '10' then esize = 32;        elements = 2;   m = UInt(Vm);   index = UInt(M);


        Notes for all encodings

        Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQDMLAL or VQDMLSL instruction must
                          be unconditional. ARM strongly recommends that a T32 VQDMLAL or VQDMLSL instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "size" field. It can have the
                          following values:

                          S16          when size = 01

                          S32          when size = 10

                          It is RESERVED when:

                          .      size = 00.

                          .      size = 11.

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          For encoding A1 and T1: is the 64-bit name of the second SIMD&FP source register, encoded in
              the "M:Vm" field.

              For encoding A2 and T2: is the 64-bit name of the second SIMD&FP source register, encoded in
              the "Vm<2:0>" field when <dt> is S16, otherwise the "Vm" field.

<index>       Is the element index in the range 0 to 3, encoded in the "M:Vm<3>" field when <dt> is S16,
              otherwise in range 0 to 1, encoded in the "M" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckAdvSIMDEnabled();
    if scalar_form then op2 = SInt(Elem[Din[m],index,esize]);
    for e = 0 to elements-1
        if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]);
        op1 = SInt(Elem[Din[n],e,esize]);
        // The following only saturates if both op1 and op2 equal -(2^(esize-1))
        (product, sat1) = SignedSatQ(2*op1*op2, 2*esize);
        if add then
            result = SInt(Elem[Qin[d>>1],e,2*esize]) + SInt(product);
        else
            result = SInt(Elem[Qin[d>>1],e,2*esize]) - SInt(product);
        (Elem[Q[d>>1],e,2*esize], sat2) = SignedSatQ(result, 2*esize);
        if sat1 || sat2 then FPSR.QC = '1';


platform: ARM
mnem: VQDMLSL
description:
        Vector Saturating Doubling Multiply Subtract Long multiplies corresponding elements in two doubleword vectors,       (F8.1.156)
        subtracts double the products from corresponding elements of a quadword vector, and places the results in the same
        quadword vector.

        The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD
        scalars on page F5-2586.

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 1 D !=11                  Vn           Vd      1 0 1 1 N 0 M 0             Vm
                                            size                                 op


        A1 variant

        VQDMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         add = (op == '0');
         scalar_form = FALSE;     d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);
         esize = 8 << UInt(size);     elements = 64 DIV esize;


        A2


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 1 D !=11                  Vn           Vd      0 1 1 1 N 1 M 0             Vm
                                            size                              op


        A2 variant

        VQDMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>]


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         add = (op == '0');
         scalar_form = TRUE;     d = UInt(D:Vd);    n = UInt(N:Vn);
         if size == '01' then esize = 16;      elements = 4;    m = UInt(Vm<2:0>);   index = UInt(M:Vm<3>);
         if size == '10' then esize = 32;      elements = 2;    m = UInt(Vm);   index = UInt(M);
T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15        12 11 10 9 8 7 6 5 4 3                   0
  1 1 1 0 1 1 1 1 1 D !=11                  Vn           Vd       1 0 1 1 N 0 M 0                Vm
                                  size                                       op


T1 variant

VQDMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 add = (op == '0');
 scalar_form = FALSE;  d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);
 esize = 8 << UInt(size);   elements = 64 DIV esize;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                0 15        12 11 10 9 8 7 6 5 4 3                   0
  1 1 1 0 1 1 1 1 1 D !=11                  Vn           Vd       0 1 1 1 N 1 M 0                Vm
                                  size                               op


T2 variant

VQDMLSL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>[<index>]


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 add = (op == '0');
 scalar_form = TRUE;  d = UInt(D:Vd);     n = UInt(N:Vn);
 if size == '01' then esize = 16;    elements = 4;   m = UInt(Vm<2:0>);      index = UInt(M:Vm<3>);
 if size == '10' then esize = 32;    elements = 2;   m = UInt(Vm);      index = UInt(M);


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQDMLAL or VQDMLSL instruction must
              be unconditional. ARM strongly recommends that a T32 VQDMLAL or VQDMLSL instruction is
              unconditional, see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              S16          when size = 01

              S32          when size = 10

              It is RESERVED when:

              .      size = 00.

              .      size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.
        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              For encoding A1 and T1: is the 64-bit name of the second SIMD&FP source register, encoded in
                          the "M:Vm" field.

                          For encoding A2 and T2: is the 64-bit name of the second SIMD&FP source register, encoded in
                          the "Vm<2:0>" field when <dt> is S16, otherwise the "Vm" field.

        <index>           Is the element index in the range 0 to 3, encoded in the "M:Vm<3>" field when <dt> is S16,
                          otherwise in range 0 to 1, encoded in the "M" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();     CheckAdvSIMDEnabled();
               if scalar_form then op2 = SInt(Elem[Din[m],index,esize]);
               for e = 0 to elements-1
                   if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]);
                   op1 = SInt(Elem[Din[n],e,esize]);
                   // The following only saturates if both op1 and op2 equal -(2^(esize-1))
                   (product, sat1) = SignedSatQ(2*op1*op2, 2*esize);
                   if add then
                        result = SInt(Elem[Qin[d>>1],e,2*esize]) + SInt(product);
                   else
                        result = SInt(Elem[Qin[d>>1],e,2*esize]) - SInt(product);
                   (Elem[Q[d>>1],e,2*esize], sat2) = SignedSatQ(result, 2*esize);
                   if sat1 || sat2 then FPSR.QC = '1';


platform: ARM
mnem: VQDMULH
description:
Vector Saturating Doubling Multiply Returning High Half multiplies corresponding elements in two vectors,       (F8.1.157)
doubles the results, and places the most significant half of the final results in the destination vector. The results are
truncated, for rounded results see VQRDMULH.

The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD
scalars on page F5-2586.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 0 0 D size                   Vn           Vd        1 0 1 1 N Q M 0                Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size == '00' || size == '11' then UNDEFINED;
 scalar_form = FALSE;     esize = 8 << UInt(size);     elements = 64 DIV esize;
 d = UInt(D:Vd);    n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


A2


  31 30 29 28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 Q 1 D !=11                   Vn           Vd        1 1 0 0 N 1 M 0                Vm
                                    size


64-bit SIMD vector variant

Applies when Q = 0.

VQDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]>


128-bit SIMD vector variant

Applies when Q = 1.

VQDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]>
        Decode for all variants of this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
         scalar_form = TRUE;     d = UInt(D:Vd);  n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;
         if size == '01' then esize = 16;     elements = 4;   m = UInt(Vm<2:0>);    index = UInt(M:Vm<3>);
         if size == '10' then esize = 32;     elements = 2;   m = UInt(Vm);    index = UInt(M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3               0 15         12 11 10 9 8 7 6 5 4 3              0
            1 1 1 0 1 1 1 1 0 D size                 Vn         Vd         1 0 1 1 N Q M 0           Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size == '00' || size == '11' then UNDEFINED;
         scalar_form = FALSE;     esize = 8 << UInt(size);   elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3               0 15         12 11 10 9 8 7 6 5 4 3              0
            1 1 1 Q 1 1 1 1 1 D !=11                 Vn         Vd         1 1 0 0 N 1 M 0           Vm
                                          size


        64-bit SIMD vector variant

        Applies when Q = 0.

        VQDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]>


        Decode for all variants of this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
         scalar_form = TRUE;     d = UInt(D:Vd);  n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;
         if size == '01' then esize = 16;     elements = 4;   m = UInt(Vm<2:0>);    index = UInt(M:Vm<3>);
         if size == '10' then esize = 32;     elements = 2;   m = UInt(Vm);    index = UInt(M);
Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQDMULH instruction must be
              unconditional. ARM strongly recommends that a T32 VQDMULH instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              S16          when size = 01

              S32          when size = 10

              It is RESERVED when:

              .      size = 00.

              .      size = 11.

<Qd>          For encoding A1 and T1: is the 128-bit name of the SIMD&FP destination register, encoded in the
              "D:Vd" field, as <Qd>*2.

              For encoding A2 and T2: is the 128-bit name of the SIMD&FP destination register, encoded in the
              "D:Vd" field as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm[x]>       The scalar for either a quadword or a doubleword scalar operation. If <dt> is S16, Dm is restricted to
              D0-D7. If <dt> is S32, Dm is restricted to D0-D15.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     if scalar_form then op2 = SInt(Elem[D[m],index,esize]);
     for r = 0 to regs-1
         for e = 0 to elements-1
             if !scalar_form then op2 = SInt(Elem[D[m+r],e,esize]);
             op1 = SInt(Elem[D[n+r],e,esize]);
             // The following only saturates if both op1 and op2 equal -(2^(esize-1))
             (result, sat) = SignedSatQ((2*op1*op2) >> esize, esize);
             Elem[D[d+r],e,esize] = result;
             if sat then FPSR.QC = '1';


platform: ARM
mnem: VQDMULL
description:
        Vector Saturating Doubling Multiply Long multiplies corresponding elements in two doubleword vectors, doubles       (F8.1.158)
        the products, and places the results in a quadword vector.

        The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD
        scalars on page F5-2586.

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 1 D !=11                  Vn           Vd      1 1 0 1 N 0 M 0             Vm
                                            size


        A1 variant

        VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         scalar_form = FALSE;     d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);
         esize = 8 << UInt(size);     elements = 64 DIV esize;


        A2


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 1 D !=11                  Vn           Vd      1 0 1 1 N 1 M 0             Vm
                                            size


        A2 variant

        VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]>// Encoding T2/A2


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if size == '00' || Vd<0> == '1' then UNDEFINED;
         scalar_form = TRUE;     d = UInt(D:Vd);    n = UInt(N:Vn);
         if size == '01' then esize = 16;      elements = 4;    m = UInt(Vm<2:0>);   index = UInt(M:Vm<3>);
         if size == '10' then esize = 32;      elements = 2;    m = UInt(Vm);   index = UInt(M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 0 1 1 1 1 1 D !=11                  Vn           Vd      1 1 0 1 N 0 M 0             Vm
                                            size
T1 variant

VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm>


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 scalar_form = FALSE;  d = UInt(D:Vd);     n = UInt(N:Vn);       m = UInt(M:Vm);
 esize = 8 << UInt(size);   elements = 64 DIV esize;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15          12 11 10 9 8 7 6 5 4 3                     0
  1 1 1 0 1 1 1 1 1 D !=11                   Vn             Vd        1 0 1 1 N 1 M 0                Vm
                                  size


T2 variant

VQDMULL{<c>}{<q>}.<dt> <Qd>, <Dn>, <Dm[x]>// Encoding T2/A2


Decode for this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' || Vd<0> == '1' then UNDEFINED;
 scalar_form = TRUE;  d = UInt(D:Vd);     n = UInt(N:Vn);
 if size == '01' then esize = 16;     elements = 4;    m = UInt(Vm<2:0>);        index = UInt(M:Vm<3>);
 if size == '10' then esize = 32;     elements = 2;    m = UInt(Vm);       index = UInt(M);


Notes for all encodings

Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQDMULL instruction must be
              unconditional. ARM strongly recommends that a T32 VQDMULL instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              S16          when size = 01

              S32          when size = 10

              It is RESERVED when:

              .      size = 00.

              .      size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm[x]>       The scalar for a scalar operation. If <dt> is S16, Dm is restricted to D0-D7. If <dt> is S32, Dm is restricted
              to D0-D15.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.
        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();   CheckAdvSIMDEnabled();
               if scalar_form then op2 = SInt(Elem[Din[m],index,esize]);
               for e = 0 to elements-1
                   if !scalar_form then op2 = SInt(Elem[Din[m],e,esize]);
                   op1 = SInt(Elem[Din[n],e,esize]);
                   // The following only saturates if both op1 and op2 equal -(2^(esize-1))
                   (product, sat) = SignedSatQ(2*op1*op2, 2*esize);
                   Elem[Q[d>>1],e,2*esize] = product;
                   if sat then FPSR.QC = '1';


platform: ARM
mnem: VQMOVN
description:
Vector Saturating Move and Narrow copies each element of the operand vector to the corresponding element of the       (F8.1.159)
destination vector.

The operand is a quadword vector. The elements can be any one of:

.      16-bit, 32-bit, or 64-bit signed integers.

.      16-bit, 32-bit, or 64-bit unsigned integers.

The result is a doubleword vector. The elements are half the length of the operand vector elements. If the operand
is unsigned, the results are unsigned. If the operand is signed, the results can be signed or unsigned.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.

This instruction is used by the aliases VQRSHRN (zero), VQRSHRUN (zero), VQSHRN (zero), and VQSHRUN
(zero). See the Alias conditions on page F8-3618 table for details of when each alias is preferred.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                         Vd       0 0 1 0        op   M 0      Vm




Signed result variant

Applies when op = 1x.

VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>


Unsigned result variant

Applies when op = 01.

VQMOVUN{<c>}{<q>}.<dt> <Dd>, <Qm>


Decode for all variants of this encoding

 if op == '00' then SEE VMOVN;
 if size == '11' || Vm<0> == '1' then UNDEFINED;
 src_unsigned = (op == '11');       dest_unsigned = (op<0> == '1');
 esize = 8 << UInt(size);      elements = 64 DIV esize;
 d = UInt(D:Vd);     m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                       12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                         Vd       0 0 1 0        op   M 0      Vm




Signed result variant

Applies when op = 1x.
        VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>


        Unsigned result variant

        Applies when op = 01.

        VQMOVUN{<c>}{<q>}.<dt> <Dd>, <Qm>


        Decode for all variants of this encoding

         if op == '00' then SEE VMOVN;
         if size == '11' || Vm<0> == '1' then UNDEFINED;
         src_unsigned = (op == '11');        dest_unsigned = (op<0> == '1');
         esize = 8 << UInt(size);        elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);


        Alias conditions


                                Alias                    is preferred when

                                VQRSHRN (zero)           Never

                                VQRSHRUN (zero)          Never

                                VQSHRN (zero)            Never

                                VQSHRUN (zero)           Never



        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQMOVN or VQMOVUN instruction must
                          be unconditional. ARM strongly recommends that a T32 VQMOVN or VQMOVUN instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              For the signed result variant: is the data type for the elements of the operand, encoded in the
                          "op:size" field. It can have the following values:

                          S16          when op = 10, size = 00

                          S32          when op = 10, size = 01

                          S64          when op = 10, size = 10

                          U8           when op = 11, size = 00

                          U32          when op = 11, size = 01

                          U64          when op = 11, size = 10

                          It is RESERVED when:

                          .      op = 0x, size = xx.

                          .      op = 10, size = 11.

                          .      op = 11, size = 11.

                          For the unsigned result variant: is the data type for the elements of the operand, encoded in the "size"
                          field. It can have the following values:

                          S16          when size = 00

                          S32          when size = 01

                          S64          when size = 10

                          It is RESERVED when size = 11.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.
<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        operand = Int(Elem[Qin[m>>1],e,2*esize], src_unsigned);
        (Elem[D[d],e,esize], sat) = SatQ(operand, esize, dest_unsigned);
        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQNEG
description:
        Vector Saturating Negate negates each element in a vector, and places the results in the destination vector.       (F8.1.160)

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 1 1 1 1 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQNEG{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQNEG{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 1 1 1 1 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQNEG{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQNEG{<c>}{<q>}.<dt> <Qd>, <Qm>
Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQNEG instruction must be
              unconditional. ARM strongly recommends that a T32 VQNEG instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the vectors, encoded in the "size" field. It can have the following
              values:

              S8           when size = 00

              S16          when size = 01

              S32          when size = 10

              It is RESERVED when size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             result = -SInt(Elem[D[m+r],e,esize]);
             (Elem[D[d+r],e,esize], sat) = SignedSatQ(result, esize);
             if sat then FPSR.QC = '1';


platform: ARM
mnem: VQRDMULH
description:
        Vector Saturating Rounding Doubling Multiply Returning High Half multiplies corresponding elements in two       (F8.1.161)
        vectors, doubles the results, and places the most significant half of the final results in the destination vector. The
        results are rounded. For truncated results see VQDMULH.

        The second operand can be a scalar instead of a vector. For more information about scalars see Advanced SIMD
        scalars on page F5-2586.

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 0 0 1 1 0 D size                  Vn           Vd       1 0 1 1 N Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQRDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQRDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size == '00' || size == '11' then UNDEFINED;
         scalar_form = FALSE;     esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        A2


           31 30 29 28 27 26 25 24 23 22 21 20 19           16 15      12 11 10 9 8 7 6 5 4 3                     0
            1 1 1 1 0 0 1 Q 1 D !=11                  Vn           Vd       1 1 0 1 N 1 M 0                 Vm
                                            size


        64-bit SIMD vector variant

        Applies when Q = 0.

        VQRDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQRDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]>
Decode for all variants of this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
 scalar_form = TRUE;  d = UInt(D:Vd);  n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;
 if size == '01' then esize = 16;  elements = 4;   m = UInt(Vm<2:0>);     index = UInt(M:Vm<3>);
 if size == '10' then esize = 32;  elements = 2;   m = UInt(Vm);     index = UInt(M);


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 1 1 1 1 1 0 D size               Vn          Vd         1 0 1 1 N Q M 0             Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQRDMULH{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VQRDMULH{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size == '00' || size == '11' then UNDEFINED;
 scalar_form = FALSE;  esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  n = UInt(N:Vn);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


T2


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 Q 1 1 1 1 1 D !=11               Vn          Vd         1 1 0 1 N 1 M 0             Vm
                               size


64-bit SIMD vector variant

Applies when Q = 0.

VQRDMULH{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm[x]>


128-bit SIMD vector variant

Applies when Q = 1.

VQRDMULH{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Dm[x]>


Decode for all variants of this encoding

 if size == '11' then SEE "Related encodings";
 if size == '00' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1') then UNDEFINED;
 scalar_form = TRUE;  d = UInt(D:Vd);  n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;
 if size == '01' then esize = 16;  elements = 4;   m = UInt(Vm<2:0>);     index = UInt(M:Vm<3>);
 if size == '10' then esize = 32;  elements = 2;   m = UInt(Vm);     index = UInt(M);
        Notes for all encodings

        Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQRDMULH instruction must be
                          unconditional. ARM strongly recommends that a T32 VQRDMULH instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the operands, encoded in the "size" field. It can have the
                          following values:

                          S16          when size = 01

                          S32          when size = 10

                          It is RESERVED when:

                          .      size = 00.

                          .      size = 11.

        <Qd>              For encoding A1 and T1: is the 128-bit name of the SIMD&FP destination register, encoded in the
                          "D:Vd" field, as <Qd>*2.

                          For encoding A2 and T2: is the 128-bit name of the SIMD&FP destination register, encoded in the
                          "D:Vd" field as <Qd>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm[x]>           The scalar for either a quadword or a doubleword scalar operation. If <dt> is S16, Dm is restricted to
                          D0-D7. If <dt> is S32, Dm is restricted to D0-D15.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               round_const = 1 << (esize-1);
               if scalar_form then op2 = SInt(Elem[D[m],index,esize]);
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        op1 = SInt(Elem[D[n+r],e,esize]);
                        if !scalar_form then op2 = SInt(Elem[D[m+r],e,esize]);
                        (result, sat) = SignedSatQ((2*op1*op2 + round_const) >> esize, esize);
                        Elem[D[d+r],e,esize] = result;
                        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQRSHL
description:
Vector Saturating Rounding Shift Left takes each element in a vector, shifts them by a value from the least       (F8.1.162)
significant byte of the corresponding element of a second vector, and places the results in the destination vector. If
the shift value is positive, the operation is a left shift. Otherwise, it is a right shift.

For truncated results see VQSHL (register).

The first operand and result elements are the same data type, and can be any one of:

.      8-bit, 16-bit, 32-bit, or 64-bit signed integers.

.      8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

The second operand is a signed integer of the same size.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19              16 15        12 11 10 9 8 7 6 5 4 3                0
   1 1 1 1 0 0 1 U 0 D size                     Vn            Vd       0 1 0 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>


128-bit SIMD vector variant

Applies when Q = 1.

VQRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);      elements = 64 DIV esize;
 d = UInt(D:Vd);     m = UInt(M:Vm);     n = UInt(N:Vn);      regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3                     0 15         12 11 10 9 8 7 6 5 4 3                0
   1 1 1 U 1 1 1 1 0 D size                     Vn            Vd       0 1 0 1 N Q M 1              Vm




64-bit SIMD vector variant

Applies when Q = 0.

VQRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>
        128-bit SIMD vector variant

        Applies when Q = 1.

        VQRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED;
         unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);    n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQRSHL instruction must be
                          unconditional. ARM strongly recommends that a T32 VQRSHL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <dt>              Is the data type for the elements of the vectors, encoded in the "U:size" field. It can have the
                          following values:

                          S8           when U = 0, size = 00

                          S16          when U = 0, size = 01

                          S32          when U = 0, size = 10

                          S64          when U = 0, size = 11

                          U8           when U = 1, size = 00

                          U16          when U = 1, size = 01

                          U32          when U = 1, size = 10

                          U64          when U = 1, size = 11

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

        <Qm>              Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
                          <Qm>*2.

        <Qn>              Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        shift = SInt(Elem[D[n+r],e,esize]<7:0>);
                        round_const = 1 << (-1-shift); // 0 for left shift, 2^(n-1) for right shift
                        operand = Int(Elem[D[m+r],e,esize], unsigned);
                        (result, sat) = SatQ((operand + round_const) << shift, esize, unsigned);
                        Elem[D[d+r],e,esize] = result;
                        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQRSHRN
description:
Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right shifts       (F8.1.163)
them by an immediate value, and places the signed rounded results in a doubleword vector

This instruction is an alias of the VQMOVN, VQMOVUN instruction. This means that:

.      The encodings in this description are named to match the encodings of VQMOVN, VQMOVUN.

.      The description of VQMOVN, VQMOVUN gives the operational pseudocode for this instruction.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd       0 0 1 0 1 x M 0              Vm
                                                                                   op


Signed result variant

VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0

is equivalent to

VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

and is never the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd       0 0 1 0 1 x M 0              Vm
                                                                                   op


Signed result variant

VQRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0

is equivalent to

VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

and is never the preferred disassembly.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VQMOVN or VQMOVUN instruction must
                be unconditional. ARM strongly recommends that a T32 VQMOVN or VQMOVUN instruction is
                unconditional, see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<dt>            Is the data type for the elements of the operand, encoded in the "op:size" field. It can have the
                following values:

                S16          when op = 10, size = 00

                S32          when op = 10, size = 01

                S64          when op = 10, size = 10

                U8           when op = 11, size = 00

                U32          when op = 11, size = 01
                          U64         when op = 11, size = 10

                          It is RESERVED when:

                          .      op = 0x, size = xx.

                          .      op = 10, size = 11.

                          .      op = 11, size = 11.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.


        Operation for all encodings

        The description of VQMOVN, VQMOVUN gives the operational pseudocode for this instruction.


platform: ARM
mnem: VQRSHRUN
description:
Vector Saturating Rounding Shift Right, Narrow takes each element in a quadword vector of integers, right shifts       (F8.1.164)
them by an immediate value, and places the rounded results in a doubleword vector.

For truncated results, see VQSHL (register).

The operand elements must all be the same size, and can be any one of:

.      16-bit, 32-bit, or 64-bit signed integers.

.      16-bit, 32-bit, or 64-bit unsigned integers.

The result elements are half the width of the operand elements. If the operand elements are signed, the results can
be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21                  16 15      12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 1 D                    imm6             Vd        1 0 0 op 0 1 M 1             Vm




Signed result variant

Applies when !(imm6 == 000xxx) && op = 1.

VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


Unsigned result variant

Applies when U = 1 && !(imm6 == 000xxx) && op = 0.

VQRSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


Decode for all variants of this encoding

 if imm6 == '000xxx' then SEE "Related encodings";
 if U == '0' && op == '0' then SEE VRSHRN;
 if Vm<0> == '1' then UNDEFINED;
 case imm6 of
      when "001xxx"    esize = 8;    elements = 8;   shift_amount = 16 - UInt(imm6);
      when "01xxxx"    esize = 16;    elements = 4;   shift_amount = 32 - UInt(imm6);
      when "1xxxxx"    esize = 32;    elements = 2;   shift_amount = 64 - UInt(imm6);
 src_unsigned = (U == '1' && op == '1');       dest_unsigned = (U == '1');
 d = UInt(D:Vd);     m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5                       0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 U 1 1 1 1 1 D                    imm6             Vd        1 0 0 op 0 1 M 1             Vm
        Signed result variant

        Applies when !(imm6 == 000xxx) && op = 1.

        VQRSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


        Unsigned result variant

        Applies when U = 1 && !(imm6 == 000xxx) && op = 0.

        VQRSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


        Decode for all variants of this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if U == '0' && op == '0' then SEE VRSHRN;
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "01xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
         src_unsigned = (U == '1' && op == '1');         dest_unsigned = (U == '1');
         d = UInt(D:Vd);      m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQRSHRN or VQRSHRUN instruction
                          must be unconditional. ARM strongly recommends that a T32 VQRSHRN or VQRSHRUN instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <type>            For the signed result variant: is the data type for the elements of the vectors, encoded in the "U"
                          field. It can have the following values:

                          S            when U = 0

                          U            when U = 1

                          For the unsigned result variant: is the data type for the elements of the vectors, encoded in the "U"
                          field. It can have the following values:

                          S            when U = 1

        <size>            Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field. It can have the
                          following values:

                          16           when imm6<5:3> = 001

                          32           when imm6<5:3> = 01x

                          64           when imm6<5:3> = 1xx

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <imm>             Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               round_const = 1 << (shift_amount - 1);
   for e = 0 to elements-1
       operand = Int(Elem[Qin[m>>1],e,2*esize], src_unsigned);
       (result, sat) = SatQ((operand + round_const) >> shift_amount, esize, dest_unsigned);
       Elem[D[d],e,esize] = result;
       if sat then FPSR.QC = '1';


platform: ARM
mnem: VQSHL
description:
        Vector Saturating Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate       (F8.1.166)
        value, and places the results in a second vector.

        The operand elements must all be the same size, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        The result elements are the same size as the operand elements. If the operand elements are signed, the results can
        be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 U 1 D                     imm6            Vd      0 1 1 op L Q M 1               Vm




        VQSHL, double, signed-result variant

        Applies when !(imm6 == 000xxx && L == 0) && op = 1 && Q = 0.

        VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        VQSHL, quad, signed-result variant

        Applies when !(imm6 == 000xxx && L == 0) && op = 1 && Q = 1.

        VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        VQSHLU, double, unsigned-result variant

        Applies when U = 1 && !(imm6 == 000xxx && L == 0) && op = 0 && Q = 0.

        VQSHLU{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        VQSHLU, quad, unsigned-result variant

        Applies when U = 1 && !(imm6 == 000xxx && L == 0) && op = 0 && Q = 1.

        VQSHLU{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if U == '0' && op == '0' then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;    elements = 8;    shift_amount = UInt(imm6) - 8;
               when "001xxxx"    esize = 16;     elements = 4;   shift_amount = UInt(imm6) - 16;
               when "01xxxxx"    esize = 32;     elements = 2;   shift_amount = UInt(imm6) - 32;
     when "1xxxxxx"  esize = 64;    elements = 1;    shift_amount = UInt(imm6);
 src_unsigned = (U == '1' && op == '1');    dest_unsigned = (U == '1');
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5                    0 15         12 11 10 9 8 7 6 5 4 3                  0
  1 1 1 U 1 1 1 1 1 D                   imm6             Vd       0 1 1 op L Q M 1              Vm




VQSHL, double, signed-result variant

Applies when !(imm6 == 000xxx && L == 0) && op = 1 && Q = 0.

VQSHL{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


VQSHL, quad, signed-result variant

Applies when !(imm6 == 000xxx && L == 0) && op = 1 && Q = 1.

VQSHL{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


VQSHLU, double, unsigned-result variant

Applies when U = 1 && !(imm6 == 000xxx && L == 0) && op = 0 && Q = 0.

VQSHLU{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


VQSHLU, quad, unsigned-result variant

Applies when U = 1 && !(imm6 == 000xxx && L == 0) && op = 0 && Q = 1.

VQSHLU{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if U == '0' && op == '0' then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;    elements = 8;    shift_amount = UInt(imm6) - 8;
     when "001xxxx"  esize = 16;    elements = 4;    shift_amount = UInt(imm6) - 16;
     when "01xxxxx"  esize = 32;    elements = 2;    shift_amount = UInt(imm6) - 32;
     when "1xxxxxx"  esize = 64;    elements = 1;    shift_amount = UInt(imm6);
 src_unsigned = (U == '1' && op == '1');    dest_unsigned = (U == '1');
 d = UInt(D:Vd);  m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQSHL or VQSHLU instruction must be
              unconditional. ARM strongly recommends that a T32 VQSHL or VQSHLU instruction is unconditional,
              see Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<type>        Is the data type for the elements of the vectors, encoded in the "U" field. It can have the following
              values:

              S            when U = 0
                          U            when U = 1

        <size>            Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
                          following values:

                          8            when L = 0, imm6<5:3> = 001

                          16           when L = 0, imm6<5:3> = 01x

                          32           when L = 0, imm6<5:3> = 1xx

                          64           when L = 1, imm6<5:3> = xxx

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

        <imm>             Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        operand = Int(Elem[D[m+r],e,esize], src_unsigned);
                        (result, sat) = SatQ(operand << shift_amount, esize, dest_unsigned);
                        Elem[D[d+r],e,esize] = result;
                        if sat then FPSR.QC = '1';


platform: ARM
mnem: VQSHRN
description:
Vector Saturating Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an       (F8.1.168)
immediate value, and places the signed truncated results in a doubleword vector

This instruction is an alias of the VQMOVN, VQMOVUN instruction. This means that:

.      The encodings in this description are named to match the encodings of VQMOVN, VQMOVUN.

.      The description of VQMOVN, VQMOVUN gives the operational pseudocode for this instruction.


A1


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15           12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd       0 0 1 0 1 x M 0              Vm
                                                                                   op


Signed result variant

VQSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0

is equivalent to

VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

and is never the preferred disassembly.


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3                   0
   1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd       0 0 1 0 1 x M 0              Vm
                                                                                   op


Signed result variant

VQSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0

is equivalent to

VQMOVN{<c>}{<q>}.<dt> <Dd>, <Qm>

and is never the preferred disassembly.


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VQMOVN or VQMOVUN instruction must
                be unconditional. ARM strongly recommends that a T32 VQMOVN or VQMOVUN instruction is
                unconditional, see Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<dt>            Is the data type for the elements of the operand, encoded in the "op:size" field. It can have the
                following values:

                S16          when op = 10, size = 00

                S32          when op = 10, size = 01

                S64          when op = 10, size = 10

                U8           when op = 11, size = 00

                U32          when op = 11, size = 01
                          U64         when op = 11, size = 10

                          It is RESERVED when:

                          .      op = 0x, size = xx.

                          .      op = 10, size = 11.

                          .      op = 11, size = 11.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.


        Operation for all encodings

        The description of VQMOVN, VQMOVUN gives the operational pseudocode for this instruction.


platform: ARM
mnem: VQSHRUN
description:
Vector Saturating Shift Right, Narrow takes each element in a quadword vector of integers, right shifts them by an       (F8.1.169)
immediate value, and places the truncated results in a doubleword vector.

For rounded results, see VQRSHRN, VQRSHRUN.

The operand elements must all be the same size, and can be any one of:

.      16-bit, 32-bit, or 64-bit signed integers.

.      16-bit, 32-bit, or 64-bit unsigned integers.

The result elements are half the width of the operand elements. If the operand elements are signed, the results can
be either signed or unsigned. If the operand elements are unsigned, the result elements must also be unsigned.

If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
occurs. For details see Pseudocode description of saturation on page E1-2375.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21                  16 15      12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 1 D                    imm6             Vd        1 0 0 op 0 0 M 1             Vm




Signed result variant

Applies when !(imm6 == 000xxx) && op = 1.

VQSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


Unsigned result variant

Applies when U = 1 && !(imm6 == 000xxx) && op = 0.

VQSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


Decode for all variants of this encoding

 if imm6 == '000xxx' then SEE "Related encodings";
 if U == '0' && op == '0' then SEE VSHRN;
 if Vm<0> == '1' then UNDEFINED;
 case imm6 of
      when "001xxx"    esize = 8;    elements = 8;   shift_amount = 16 - UInt(imm6);
      when "01xxxx"    esize = 16;    elements = 4;   shift_amount = 32 - UInt(imm6);
      when "1xxxxx"    esize = 32;    elements = 2;   shift_amount = 64 - UInt(imm6);
 src_unsigned = (U == '1' && op == '1');       dest_unsigned = (U == '1');
 d = UInt(D:Vd);    m = UInt(M:Vm);


T1


  15 14 13 12 11 10 9 8 7 6 5                       0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 U 1 1 1 1 1 D                    imm6             Vd        1 0 0 op 0 0 M 1             Vm
        Signed result variant

        Applies when !(imm6 == 000xxx) && op = 1.

        VQSHRN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


        Unsigned result variant

        Applies when U = 1 && !(imm6 == 000xxx) && op = 0.

        VQSHRUN{<c>}{<q>}.<type><size> <Dd>, <Qm>, #<imm>


        Decode for all variants of this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if U == '0' && op == '0' then SEE VSHRN;
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "01xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
         src_unsigned = (U == '1' && op == '1');         dest_unsigned = (U == '1');
         d = UInt(D:Vd);      m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VQSHRN or VQSHRUN instruction must
                          be unconditional. ARM strongly recommends that a T32 VQSHRN or VQSHRUN instruction is
                          unconditional, see Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <type>            For the signed result variant: is the data type for the elements of the vectors, encoded in the "U"
                          field. It can have the following values:

                          S            when U = 0

                          U            when U = 1

                          For the unsigned result variant: is the data type for the elements of the vectors, encoded in the "U"
                          field. It can have the following values:

                          S            when U = 1

        <size>            Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field. It can have the
                          following values:

                          16           when imm6<5:3> = 001

                          32           when imm6<5:3> = 01x

                          64           when imm6<5:3> = 1xx

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <imm>             Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for e = 0 to elements-1
   operand = Int(Elem[Qin[m>>1],e,2*esize], src_unsigned);
   (result, sat) = SatQ(operand >> shift_amount, esize, dest_unsigned);
   Elem[D[d],e,esize] = result;
   if sat then FPSR.QC = '1';


platform: ARM
mnem: VQSUB
description:
        Vector Saturating Subtract subtracts the elements of the second operand vector from the corresponding elements of       (F8.1.171)
        the first operand vector, and places the results in the destination vector. Signed and unsigned operations are distinct.

        The operand and result elements must all be the same type, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation
        occurs. For details see Pseudocode description of saturation on page E1-2375.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19            16 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 U 0 D size                     Vn          Vd       0 0 1 0 N Q M 1             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQSUB{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VQSUB{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                    0 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 U 1 1 1 1 0 D size                     Vn          Vd       0 0 1 0 N Q M 1             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VQSUB{<c>}{<q>}.<dt> {<Dd>,} <Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.
VQSUB{<c>}{<q>}.<dt> {<Qd>,} <Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VQSUB instruction must be
              unconditional. ARM strongly recommends that a T32 VQSUB instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the vectors, encoded in the "U:size" field. It can have the
              following values:

              S8           when U = 0, size = 00

              S16          when U = 0, size = 01

              S32          when U = 0, size = 10

              S64          when U = 0, size = 11

              U8           when U = 1, size = 00

              U16          when U = 1, size = 01

              U32          when U = 1, size = 10

              U64          when U = 1, size = 11

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             diff = Int(Elem[D[n+r],e,esize], unsigned) - Int(Elem[D[m+r],e,esize], unsigned);
             (Elem[D[d+r],e,esize], sat) = SatQ(diff, esize, unsigned);
             if sat then FPSR.QC = '1';


platform: ARM
mnem: VRADDHN
description:
        Vector Rounding Add and Narrow, returning High Half adds corresponding elements in two quadword vectors, and       (F8.1.172)
        places the most significant half of each result in a doubleword vector. The results are rounded. For truncated results,
        see VADDHN.

        The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned
        integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19            16 15      12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D !=11                   Vn          Vd       0 1 0 0 N 0 M 0               Vm
                                            size


        A1 variant

        VRADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15       12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 1 D !=11                   Vn          Vd       0 1 0 0 N 0 M 0               Vm
                                            size


        T1 variant

        VRADDHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VRADDHN instruction must be
                          unconditional. ARM strongly recommends that a T32 VRADDHN instruction is unconditional, see
                          Conditional execution on page F2-2507.
<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              I16          when size = 00

              I32          when size = 01

              I64          when size = 10

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the D:"Vd" field.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDEnabled();
    round_const = 1 << (esize-1);
    for e = 0 to elements-1
        result = Elem[Qin[n>>1],e,2*esize] + Elem[Qin[m>>1],e,2*esize] + round_const;
        Elem[D[d],e,esize] = result<2*esize-1:esize>;


platform: ARM
mnem: VRECPE
description:
        Vector Reciprocal Estimate finds an approximate reciprocal of each element in the operand vector, and places the       (F8.1.173)
        results in the destination vector.

        The operand and result elements are the same type, and can be 32-bit floating-point numbers, or 32-bit unsigned
        integers.

        For details of the operation performed by this instruction see Floating-point reciprocal square root estimate and
        step on page E1-2408.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                       Vd      0 1 0 F 0 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRECPE{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRECPE{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         floating_point = (F == '1');     esize = 32;   elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                 0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                       Vd      0 1 0 F 0 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRECPE{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRECPE{<c>}{<q>}.<dt> <Qd>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 floating_point = (F == '1');      esize = 32;   elements = 2;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VRECPE instruction must be
                unconditional. ARM strongly recommends that a T32 VRECPE instruction is unconditional, see
                Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<dt>            Is the data type for the elements of the vectors, encoded in the "F:size" field. It can have the
                following values:

                S32          when F = 0, size = 10

                F32          when F = 1, size = 10

                It is RESERVED when:

                .      F = 0, size = 0x.

                .      F = 0, size = 11.

                .      F = 1, size = 0x.

                .      F = 1, size = 11.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>            Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>            Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Newton-Raphson iteration

For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the
reciprocal of a number, see Floating-point reciprocal estimate and step on page E1-2405.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();       CheckAdvSIMDEnabled();
     for r = 0 to regs-1
          for e = 0 to elements-1
               if floating_point then
                   Elem[D[d+r],e,32] = FPRecipEstimate(Elem[D[m+r],e,32], StandardFPSCRValue());
               else
                   Elem[D[d+r],e,32] = UnsignedRecipEstimate(Elem[D[m+r],e,32]);


platform: ARM
mnem: VRECPS
description:
        Vector Reciprocal Step multiplies the elements of one vector by the corresponding elements of another vector,       (F8.1.174)
        subtracts each of the products from 2.0, and places the results into the elements of the destination vector.

        The operand and result elements are 32-bit floating-point numbers.

        For details of the operation performed by this instruction see Floating-point reciprocal estimate and step on
        page E1-2405.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 0 0 D 0 sz                  Vn           Vd      1 1 1 1 N Q M 1                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRECPS{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRECPS{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 0 1 1 1 1 0 D 0 sz                  Vn           Vd      1 1 1 1 N Q M 1                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRECPS{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRECPS{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 esize = 32;    elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VRECPS instruction must be
                unconditional. ARM strongly recommends that a T32 VRECPS instruction is unconditional, see
                Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>            Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>            Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Newton-Raphson iteration

For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the
reciprocal of a number, see Floating-point reciprocal estimate and step on page E1-2405.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();      CheckAdvSIMDEnabled();
     for r = 0 to regs-1
          for e = 0 to elements-1
               Elem[D[d+r],e,32] = FPRecipStep(Elem[D[n+r],e,32], Elem[D[m+r],e,32]);


platform: ARM
mnem: VREV16
description:
        Vector Reverse in halfwords reverses the order of 8-bit elements in each halfword of the vector, and places the result       (F8.1.175)
        in the corresponding destination vector.

        There is no distinction between data types, other than size.

        The following figure shows an example of the operation of VREV16 doubleword operation.

                                                                                       VREV16.8, doubleword
                                                                                       Dm




                                                                                       Dd

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 1 0 Q M 0               Vm
                                                                                     op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VREV16{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VREV16{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if UInt(op)+UInt(size) >= 3 then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
         reverse_mask = (groupsize-1)<esize-1:0>;        // EORing mask used for index calculations
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 1 0 Q M 0               Vm
                                                                                     op
64-bit SIMD vector variant

Applies when Q = 0.

VREV16{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VREV16{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if UInt(op)+UInt(size) >= 3 then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
 reverse_mask = (groupsize-1)<esize-1:0>;        // EORing mask used for index calculations
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VREV instruction must be
              unconditional. ARM strongly recommends that a T32 VREV instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operand, encoded in the "size" field. It can have the following
              values:

              8            when size = 00

              It is RESERVED when:

              .      size = 01.

              .      size = 1x.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     bits(64) dest;

     for r = 0 to regs-1
         for e = 0 to elements-1
             // Calculate destination element index by bitwise EOR on source element index:
             e_bits = e<esize-1:0>;      d_bits = e_bits EOR reverse_mask;      d = UInt(d_bits);
             Elem[dest,d,esize] = Elem[D[m+r],e,esize];
         D[d+r] = dest;


platform: ARM
mnem: VREV32
description:
        Vector Reverse in words reverses the order of 8-bit or 16-bit elements in each word of the vector, and places the       (F8.1.176)
        result in the corresponding destination vector.

        There is no distinction between data types, other than size.

        The following figure shows an example of the operation of VREV32 doubleword operations.

             VREV32.8, doubleword                       VREV32.16, doubleword
             Dm                                         Dm




              Dd                                        Dd

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 0 1 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VREV32{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VREV32{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if UInt(op)+UInt(size) >= 3 then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
         reverse_mask = (groupsize-1)<esize-1:0>;        // EORing mask used for index calculations
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 0 1 Q M 0             Vm
64-bit SIMD vector variant

Applies when Q = 0.

VREV32{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VREV32{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if UInt(op)+UInt(size) >= 3 then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
 reverse_mask = (groupsize-1)<esize-1:0>;        // EORing mask used for index calculations
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VREV instruction must be
              unconditional. ARM strongly recommends that a T32 VREV instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operand, encoded in the "size" field. It can have the following
              values:

              8            when size = 00

              16           when size = 01

              It is RESERVED when size = 1x.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     bits(64) dest;

     for r = 0 to regs-1
         for e = 0 to elements-1
             // Calculate destination element index by bitwise EOR on source element index:
             e_bits = e<esize-1:0>;      d_bits = e_bits EOR reverse_mask;      d = UInt(d_bits);
             Elem[dest,d,esize] = Elem[D[m+r],e,esize];
         D[d+r] = dest;


platform: ARM
mnem: VREV64
description:
        Vector Reverse in doublewords reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the       (F8.1.177)
        vector, and places the result in the corresponding destination vector.

        There is no distinction between data types, other than size.

        The following figure shows an example of the operation of VREV64 doubleword operations.

             VREV64.8, doubleword                       VREV64.32, quadword
             Dm                                         Qm




              Dd                                        Qm

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 0 0 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VREV64{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VREV64{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if UInt(op)+UInt(size) >= 3 then UNDEFINED;
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         esize = 8 << UInt(size);      elements = 64 DIV esize;
         groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
         reverse_mask = (groupsize-1)<esize-1:0>;         // EORing mask used for index calculations
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 1 1 1 1 1 D 1 1 size 0 0                       Vd      0 0 0 0 0 Q M 0             Vm
64-bit SIMD vector variant

Applies when Q = 0.

VREV64{<c>}{<q>}.<dt> <Dd>, <Dm>


128-bit SIMD vector variant

Applies when Q = 1.

VREV64{<c>}{<q>}.<dt> <Qd>, <Qm>


Decode for all variants of this encoding

 if UInt(op)+UInt(size) >= 3 then UNDEFINED;
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 groupsize = (1 << (3-UInt(op)-UInt(size))); // elements per reversing group: 2, 4 or 8
 reverse_mask = (groupsize-1)<esize-1:0>;        // EORing mask used for index calculations
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VREV instruction must be
              unconditional. ARM strongly recommends that a T32 VREV instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operand, encoded in the "size" field. It can have the following
              values:

              8            when size = 00

              16           when size = 01

              32           when size = 10

              It is RESERVED when size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     bits(64) dest;

     for r = 0 to regs-1
         for e = 0 to elements-1
             // Calculate destination element index by bitwise EOR on source element index:
             e_bits = e<esize-1:0>;      d_bits = e_bits EOR reverse_mask;      d = UInt(d_bits);
             Elem[dest,d,esize] = Elem[D[m+r],e,esize];
         D[d+r] = dest;


platform: ARM
mnem: VRHADD
description:
        Vector Rounding Halving Add adds corresponding elements in two vectors of integers, shifts each result right one       (F8.1.178)
        bit, and places the final results in the destination vector.

        The operand and result elements are all the same type, and can be any one of:

        .       8-bit, 16-bit, or 32-bit signed integers.

        .       8-bit, 16-bit, or 32-bit unsigned integers.

        The results of the halving operations are rounded. For truncated results, see VHADD.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19            16 15       12 11 10 9 8 7 6 5 4 3             0
            1 1 1 1 0 0 1 U 0 D size                    Vn          Vd      0 0 0 1 N Q M 0            Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size == '11' then UNDEFINED;
         unsigned = (U == '1');
         esize = 8 << UInt(size);        elements = 64 DIV esize;
         d = UInt(D:Vd);      n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                   0 15        12 11 10 9 8 7 6 5 4 3             0
            1 1 1 U 1 1 1 1 0 D size                    Vn          Vd      0 0 0 1 N Q M 0            Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRHADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.
VRHADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size == '11' then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  n = UInt(N:Vn);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VRHADD instruction must be
              unconditional. ARM strongly recommends that a T32 VRHADD instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "U:size" field. It can have the
              following values:

              S8           when U = 0, size = 00

              S16          when U = 0, size = 01

              S32          when U = 0, size = 10

              U8           when U = 1, size = 00

              U16          when U = 1, size = 01

              U32          when U = 1, size = 10

              It is RESERVED when:

              .      U = 0, size = 11.

              .      U = 1, size = 11.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             op1 = Int(Elem[D[n+r],e,esize], unsigned);
             op2 = Int(Elem[D[m+r],e,esize], unsigned);
             result = op1 + op2 + 1;
             Elem[D[d+r],e,esize] = result<esize:1>;


platform: ARM
mnem: VRINTA
description:
        Vector Round floating-point to integer towards Nearest with Ties to Away rounds a vector of floating-point values       (F8.1.179)
        to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode. A
        zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a
        NaN is propagated as for normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9       7 6 5 4 3              0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                       Vd        0 1 0 1 0 Q M 0                Vm
                                                                                      op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTA{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTA{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9       7 6 5 4 3              0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                       Vd        0 1 0 1 0 Q M 0                Vm
                                                                                      op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTA{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTA{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

Related encodings: Two registers, miscellaneous on page F5-2594.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRINTM
description:
        Vector Round floating-point to integer towards -Infinity rounds a vector of floating-point values to integral       (F8.1.181)
        floating-point values of the same size, using the Round towards -Infinity rounding mode. A zero input gives a zero
        result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as
        for normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9       7 6 5 4 3             0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd        0 1 1 0 1 Q M 0             Vm
                                                                                       op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTM{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTM{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9       7 6 5 4 3             0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd        0 1 1 0 1 Q M 0             Vm
                                                                                       op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTM{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTM{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

Related encodings: Two registers, miscellaneous on page F5-2594.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRINTN
description:
        Vector Round floating-point to integer to Nearest rounds a vector of floating-point values to integral floating-point       (F8.1.183)
        values of the same size using the Round to Nearest rounding mode. A zero input gives a zero result with the same
        sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15             12 11 10 9      7 6 5 4 3            0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd        0 1 0 0 0 Q M 0             Vm
                                                                                     op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTN{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTN{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));        exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                       12 11 10 9      7 6 5 4 3            0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd        0 1 0 0 0 Q M 0             Vm
                                                                                     op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTN{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTN{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));        exact = FALSE;
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

Related encodings: Two registers, miscellaneous on page F5-2594.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRINTP
description:
        Vector Round floating-point to integer towards +Infinity rounds a vector of floating-point values to integral       (F8.1.185)
        floating-point values of the same size using the Round towards +Infinity rounding mode. A zero input gives a zero
        result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as
        for normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9       7 6 5 4 3             0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd        0 1 1 1 1 Q M 0             Vm
                                                                                       op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTP{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTP{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9       7 6 5 4 3             0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd        0 1 1 1 1 Q M 0             Vm
                                                                                       op


        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTP{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTP{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if op<2> != op<0> then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         // Rounding encoded differently from other VCVT and VRINT instructions
         rounding = FPDecodeRM(op<2>:NOT(op<1>));       exact = FALSE;
 esize = 32;  elements = 2;
 d = UInt(D:Vd);  m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
 if InITBlock() then UNPREDICTABLE;


Notes for all encodings

Related encodings: Two registers, miscellaneous on page F5-2594.


Assembler symbols

<q>           See Standard assembler syntax fields on page F2-2506.

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRINTR
description:
        Round floating-point to integer rounds a floating-point value to an integral floating-point value of the same size       (F8.1.187)
        using the rounding mode specified in the FPSCR. A zero input gives a zero result with the same sign, an infinite
        input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.


        A1


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15         12 11 10 9 8 7 6 5 4 3                  0
              !=1111     1 1 1 0 1 D 1 1 0 1 1 0                  Vd       1 0 1 sz 0 1 M 0             Vm
               cond                                                                    op


        Single-precision scalar variant

        Applies when sz = 0.

        VRINTR{<c>}{<q>}.F32.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VRINTR{<c>}{<q>}.F64.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
         dp_operation = (sz == '1');      exact = FALSE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                  0
            1 1 1 0 1 1 1 0 1 D 1 1 0 1 1 0                       Vd       1 0 1 sz 0 1 M 0             Vm
                                                                                       op


        Single-precision scalar variant

        Applies when sz = 0.

        VRINTR{<c>}{<q>}.F32.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VRINTR{<c>}{<q>}.F64.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         rounding = if op == '1' then FPRounding_ZERO else FPRoundingMode(FPSCR);
         dp_operation = (sz == '1');      exact = FALSE;
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506.

        <q>               See Standard assembler syntax fields on page F2-2506.
<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>          Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
    if dp_operation then
        D[d] = FPRoundInt(D[m], FPSCR, rounding, exact);
    else
        S[d] = FPRoundInt(S[m], FPSCR, rounding, exact);


platform: ARM
mnem: VRINTX
description:
        Vector round floating-point to integer inexact rounds a vector of floating-point values to integral floating-point       (F8.1.188)
        values of the same size, using the Round to Nearest rounding mode, and raises the Inexact exception when the result
        value is not numerically equal to the input value. A zero input gives a zero result with the same sign, an infinite input
        gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd      0 1 0 0 1 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTX{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTX{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPRounding_TIEEVEN;      exact = TRUE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                        Vd      0 1 0 0 1 Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTX{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTX{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPRounding_TIEEVEN;      exact = TRUE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<q>            See Standard assembler syntax fields on page F2-2506.

<Qd>           Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>           Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>           Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>           Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRINTZ
description:
        Vector round floating-point to integer towards Zero rounds a vector of floating-point values to integral       (F8.1.190)
        floating-point values of the same size, using the Round towards Zero rounding mode. A zero input gives a zero result
        with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for
        normal arithmetic.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                       Vd        0 1 0 1 1 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTZ{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTZ{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPRounding_ZERO;     exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                      12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                       Vd        0 1 0 1 1 Q M 0             Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRINTZ{<q>}.F32.F32 <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRINTZ{<q>}.F32.F32 <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         rounding = FPRounding_ZERO;     exact = FALSE;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;
         if InITBlock() then UNPREDICTABLE;
Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<q>            See Standard assembler syntax fields on page F2-2506.

<Qd>           Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>           Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>           Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>           Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 EncodingSpecificOperations(); CheckAdvSIMDEnabled();
 for r = 0 to regs-1
     for e = 0 to elements-1
         op1 = Elem[D[m+r],e,esize];
         result = FPRoundInt(op1, StandardFPSCRValue(), rounding, exact);
         Elem[D[d+r],e,esize] = result;


platform: ARM
mnem: VRSHL
description:
        Vector Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of       (F8.1.192)
        the corresponding element of a second vector, and places the results in the destination vector. If the shift value is
        positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift,
        see VSHL.

        The first operand and result elements are the same data type, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        The second operand is always a signed integer of the same size.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19              16 15         12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 1 0 0 1 U 0 D size                      Vn            Vd       0 1 0 1 N Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED;
         unsigned = (U == '1');
         esize = 8 << UInt(size);       elements = 64 DIV esize;
         d = UInt(D:Vd);      m = UInt(M:Vm);     n = UInt(N:Vn);      regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                      0 15         12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 U 1 1 1 1 0 D size                      Vn            Vd       0 1 0 1 N Q M 0                 Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>


        128-bit SIMD vector variant

        Applies when Q = 1.
VRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>


Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1' || Vn<0> == '1') then UNDEFINED;
 unsigned = (U == '1');
 esize = 8 << UInt(size);   elements = 64 DIV esize;
 d = UInt(D:Vd);  m = UInt(M:Vm);    n = UInt(N:Vn);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VRSHL instruction must be
              unconditional. ARM strongly recommends that a T32 VRSHL instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the vectors, encoded in the "U:size" field. It can have the
              following values:

              S8           when U = 0, size = 00

              S16          when U = 0, size = 01

              S32          when U = 0, size = 10

              S64          when U = 0, size = 11

              U8           when U = 1, size = 00

              U16          when U = 1, size = 01

              U32          when U = 1, size = 10

              U64          when U = 1, size = 11

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

<Dn>          Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             shift = SInt(Elem[D[n+r],e,esize]<7:0>);
             round_const = 1 << (-shift-1); // 0 for left shift, 2^(n-1) for right shift
             result = (Int(Elem[D[m+r],e,esize], unsigned) + round_const) << shift;
             Elem[D[d+r],e,esize] = result<esize-1:0>;


platform: ARM
mnem: VRSHR
description:
        Vector Rounding Shift Right takes each element in a vector, right shifts them by an immediate value, and places the       (F8.1.193)
        rounded results in the destination vector. For truncated results, see VSHR.

        The operand and result elements must be the same size, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3              0
            1 1 1 1 0 0 1 U 1 D                     imm6            Vd      0 0 1 0 L Q M 1            Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "001xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "01xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
               when "1xxxxxx"    esize = 64;     elements = 1;   shift_amount = 64 - UInt(imm6);
         unsigned = (U == '1');       d = UInt(D:Vd);    m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15       12 11 10 9 8 7 6 5 4 3              0
            1 1 1 U 1 1 1 1 1 D                     imm6            Vd      0 0 1 0 L Q M 1            Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VRSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.
VRSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = 16 - UInt(imm6);
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = 32 - UInt(imm6);
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = 64 - UInt(imm6);
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = 64 - UInt(imm6);
 unsigned = (U == '1');   d = UInt(D:Vd);    m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VRSHR instruction must be
              unconditional. ARM strongly recommends that a T32 VRSHR instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<type>        Is the data type for the elements of the vectors, encoded in the "U" field. It can have the following
              values:

              S            when U = 0

              U            when U = 1

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     round_const = 1 << (shift_amount - 1);
     for r = 0 to regs-1
         for e = 0 to elements-1
             result = (Int(Elem[D[m+r],e,esize], unsigned) + round_const) >> shift_amount;
             Elem[D[d+r],e,esize] = result<esize-1:0>;


platform: ARM
mnem: VRSHRN
description:
        Vector Rounding Shift Right and Narrow takes each element in a vector, right shifts them by an immediate value,       (F8.1.195)
        and places the rounded results in the destination vector. For truncated results, see VSHRN.

        The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned
        integers. The destination elements are half the size of the source elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                16 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 0 1 D                  imm6              Vd       1 0 0 0 0 1 M 1              Vm




        A1 variant

        Applies when imm6 != 000xxx.

        VRSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>


        Decode for this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"   esize = 8;  elements = 8;    shift_amount = 16 - UInt(imm6);
               when "01xxxx"   esize = 16;   elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"   esize = 32;   elements = 2;   shift_amount = 64 - UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5                      0 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 0 1 1 1 1 1 D                  imm6              Vd       1 0 0 0 0 1 M 1              Vm




        T1 variant

        Applies when imm6 != 000xxx.

        VRSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>


        Decode for this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"   esize = 8;  elements = 8;    shift_amount = 16 - UInt(imm6);
               when "01xxxx"   esize = 16;   elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"   esize = 32;   elements = 2;   shift_amount = 64 - UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);
Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VRSHRN instruction must be
              unconditional. ARM strongly recommends that a T32 VRSHRN instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<size>        Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field. It can have the
              following values:

              16          when imm6<5:3> = 001

              32          when imm6<5:3> = 01x

              64          when imm6<5:3> = 1xx

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<imm>         Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     round_const = 1 << (shift_amount-1);
     for e = 0 to elements-1
         result = LSR(Elem[Qin[m>>1],e,2*esize] + round_const, shift_amount);
         Elem[D[d],e,esize] = result<esize-1:0>;


platform: ARM
mnem: VRSQRTE
description:
        Vector Reciprocal Square Root Estimate finds an approximate reciprocal square root of each element in a vector,       (F8.1.197)
        and places the results in a second vector.

        The operand and result elements are the same type, and can be 32-bit floating-point numbers, or 32-bit unsigned
        integers.

        For details of the operation performed by this instruction see Floating-point reciprocal estimate and step on
        page E1-2405.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15          12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 1 1 D 1 1 size 1 1                       Vd      0 1 0 F 1 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSQRTE{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRSQRTE{<c>}{<q>}.<dt> <Qd>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if size != '10' then UNDEFINED;
         floating_point = (F == '1');     esize = 32;   elements = 2;
         d = UInt(D:Vd);     m = UInt(M:Vm);   regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 1                       Vd      0 1 0 F 1 Q M 0              Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSQRTE{<c>}{<q>}.<dt> <Dd>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRSQRTE{<c>}{<q>}.<dt> <Qd>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if size != '10' then UNDEFINED;
 floating_point = (F == '1');      esize = 32;   elements = 2;
 d = UInt(D:Vd);    m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VRSQRTE instruction must be
                unconditional. ARM strongly recommends that a T32 VRSQRTE instruction is unconditional, see
                Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<dt>            Is the data type for the elements of the vectors, encoded in the "F:size" field. It can have the
                following values:

                S32          when F = 0, size = 10

                F32          when F = 1, size = 10

                It is RESERVED when:

                .      F = 0, size = 0x.

                .      F = 0, size = 11.

                .      F = 1, size = 0x.

                .      F = 1, size = 11.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>            Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>            Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Newton-Raphson iteration

For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the
reciprocal of the square root of a number, see Floating-point reciprocal estimate and step on page E1-2405.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();       CheckAdvSIMDEnabled();
     for r = 0 to regs-1
          for e = 0 to elements-1
               if floating_point then
                   Elem[D[d+r],e,32] = FPRSqrtEstimate(Elem[D[m+r],e,32], StandardFPSCRValue());
               else
                   Elem[D[d+r],e,32] = UnsignedRSqrtEstimate(Elem[D[m+r],e,32]);


platform: ARM
mnem: VRSQRTS
description:
        Vector Reciprocal Square Root Step multiplies the elements of one vector by the corresponding elements of another       (F8.1.198)
        vector, subtracts each of the products from 3.0, divides these results by 2.0, and places the results into the elements
        of the destination vector.

        The operand and result elements are 32-bit floating-point numbers.

        For details of the operation performed by this instruction see Floating-point reciprocal estimate and step on
        page E1-2405.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 1 0 0 1 0 0 D 1 sz                  Vn           Vd       1 1 1 1 N Q M 1                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSQRTS{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRSQRTS{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>


        Decode for all variants of this encoding

         if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
         if sz == '1' then UNDEFINED;
         esize = 32;     elements = 2;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 1 0 D 1 sz                  Vn           Vd       1 1 1 1 N Q M 1                Vm




        64-bit SIMD vector variant

        Applies when Q = 0.

        VRSQRTS{<c>}{<q>}.F32 {<Dd>, }<Dn>, <Dm>


        128-bit SIMD vector variant

        Applies when Q = 1.

        VRSQRTS{<c>}{<q>}.F32 {<Qd>, }<Qn>, <Qm>
Decode for all variants of this encoding

 if Q == '1' && (Vd<0> == '1' || Vn<0> == '1' || Vm<0> == '1') then UNDEFINED;
 if sz == '1' then UNDEFINED;
 esize = 32;    elements = 2;
 d = UInt(D:Vd);    n = UInt(N:Vn);   m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


Assembler symbols

<c>             See Standard assembler syntax fields on page F2-2506. An A32 VRSQRTS instruction must be
                unconditional. ARM strongly recommends that a T32 VRSQRTS instruction is unconditional, see
                Conditional execution on page F2-2507.

<q>             See Standard assembler syntax fields on page F2-2506.

<Qd>            Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field, as <Qd>*2.

<Qn>            Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>            Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>            Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dn>            Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

<Dm>            Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.


Newton-Raphson iteration

For details of the operation performed and how it can be used in a Newton-Raphson iteration to calculate the
reciprocal of the square root of a number, see Floating-point reciprocal estimate and step on page E1-2405.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();      CheckAdvSIMDEnabled();
     for r = 0 to regs-1
          for e = 0 to elements-1
               Elem[D[d+r],e,32] = FPRSqrtStep(Elem[D[n+r],e,32], Elem[D[m+r],e,32]);


platform: ARM
mnem: VRSRA
description:
        Vector Rounding Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate       (F8.1.199)
        value, and accumulates the rounded results into the destination vector. For truncated results, see VSRA.

        The operand and result elements must all be the same type, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3              0
            1 1 1 1 0 0 1 U 1 D                     imm6            Vd      0 0 1 1 L Q M 1              Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VRSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VRSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "001xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "01xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
               when "1xxxxxx"    esize = 64;     elements = 1;   shift_amount = 64 - UInt(imm6);
         unsigned = (U == '1');       d = UInt(D:Vd);    m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15       12 11 10 9 8 7 6 5 4 3              0
            1 1 1 U 1 1 1 1 1 D                     imm6            Vd      0 0 1 1 L Q M 1              Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VRSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.
VRSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = 16 - UInt(imm6);
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = 32 - UInt(imm6);
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = 64 - UInt(imm6);
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = 64 - UInt(imm6);
 unsigned = (U == '1');   d = UInt(D:Vd);    m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VRSRA instruction must be
              unconditional. ARM strongly recommends that a T32 VRSRA instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<type>        Is the data type for the elements of the vectors, encoded in the "U" field. It can have the following
              values:

              S            when U = 0

              U            when U = 1

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     round_const = 1 << (shift_amount - 1);
     for r = 0 to regs-1
         for e = 0 to elements-1
             result = (Int(Elem[D[m+r],e,esize], unsigned) + round_const) >> shift_amount;
             Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;


platform: ARM
mnem: VRSUBHN
description:
        Vector Rounding Subtract and Narrow, returning High Half subtracts the elements of one quadword vector from the       (F8.1.200)
        corresponding elements of another quadword vector, takes the most significant half of each result, and places the
        final results in a doubleword vector. The results are rounded. For truncated results, see VSUBHN.

        The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned
        integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 1 1 D !=11                  Vn           Vd      0 1 1 0 N 0 M 0               Vm
                                           size


        A1 variant

        VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 1 1 1 1 1 D !=11                  Vn           Vd      0 1 1 0 N 0 M 0               Vm
                                           size


        T1 variant

        VRSUBHN{<c>}{<q>}.<dt> <Dd>, <Qn>, <Qm>


        Decode for this encoding

         if size == '11' then SEE "Related encodings";
         if Vn<0> == '1' || Vm<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;
         d = UInt(D:Vd);     n = UInt(N:Vn);   m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: Advanced SIMD data-processing instructions on page F5-2587.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VRSUBHN instruction must be
                          unconditional. ARM strongly recommends that a T32 VRSUBHN instruction is unconditional, see
                          Conditional execution on page F2-2507.
<q>           See Standard assembler syntax fields on page F2-2506.

<dt>          Is the data type for the elements of the operands, encoded in the "size" field. It can have the
              following values:

              I16          when size = 00

              I32          when size = 01

              I64          when size = 10

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the D:"Vd" field.

<Qn>          Is the 128-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field as <Qn>*2.

<Qm>          Is the 128-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field as
              <Qm>*2.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();      CheckAdvSIMDEnabled();
    round_const = 1 << (esize-1);
    for e = 0 to elements-1
        result = Elem[Qin[n>>1],e,2*esize] - Elem[Qin[m>>1],e,2*esize] + round_const;
        Elem[D[d],e,esize] = result<2*esize-1:esize>;


platform: ARM
mnem: VSELEQ
description:
        Floating-point conditional select allows the destination register to take the value in either one or the other source       (F8.1.201)
        register according to the condition codes in the The Application Program Status Register, APSR on page E1-2382.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19         16 15        12 11 10 9 8 7 6 5 4 3                    0
            1 1 1 1 1 1 1 0 0 D             cc        Vn          Vd        1 0 1 sz N 0 M 0              Vm




        VSELEQ, doubleprec variant

        Applies when cc = 00 && sz = 1.

        VSELEQ.F64 <Dd>, <Dn>, <Dm>// Cannot be conditional


        VSELEQ, singleprec variant

        Applies when cc = 00 && sz = 0.

        VSELEQ.F32 <Sd>, <Sn>, <Sm>// Cannot be conditional


        VSELGE, doubleprec variant

        Applies when cc = 10 && sz = 1.

        VSELGE.F64 <Dd>, <Dn>, <Dm>// Cannot be conditional


        VSELGE, singleprec variant

        Applies when cc = 10 && sz = 0.

        VSELGE.F32 <Sd>, <Sn>, <Sm>// Cannot be conditional


        VSELGT, doubleprec variant

        Applies when cc = 11 && sz = 1.

        VSELGT.F64 <Dd>, <Dn>, <Dm>// Cannot be conditional


        VSELGT, singleprec variant

        Applies when cc = 11 && sz = 0.

        VSELGT.F32 <Sd>, <Sn>, <Sm>// Cannot be conditional


        VSELVS, doubleprec variant

        Applies when cc = 01 && sz = 1.

        VSELVS.F64 <Dd>, <Dn>, <Dm>// Cannot be conditional


        VSELVS, singleprec variant

        Applies when cc = 01 && sz = 0.

        VSELVS.F32 <Sd>, <Sn>, <Sm>// Cannot be conditional


        Decode for all variants of this encoding

         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
 m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
 cond = cc:(cc<1> EOR cc<0>):'0';
 if InITBlock() then UNPREDICTABLE;


T1


  15 14 13 12 11 10 9 8 7 6 5 4 3             0 15         12 11 10 9 8 7 6 5 4 3                0
  1 1 1 1 1 1 1 0 0 D           cc       Vn          Vd         1 0 1 sz N 0 M 0            Vm




VSELEQ, doubleprec variant

Applies when cc = 00 && sz = 1.

VSELEQ.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


VSELEQ, singleprec variant

Applies when cc = 00 && sz = 0.

VSELEQ.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


VSELGE, doubleprec variant

Applies when cc = 10 && sz = 1.

VSELGE.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


VSELGE, singleprec variant

Applies when cc = 10 && sz = 0.

VSELGE.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


VSELGT, doubleprec variant

Applies when cc = 11 && sz = 1.

VSELGT.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


VSELGT, singleprec variant

Applies when cc = 11 && sz = 0.

VSELGT.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


VSELVS, doubleprec variant

Applies when cc = 01 && sz = 1.

VSELVS.F64 <Dd>, <Dn>, <Dm>// Not permitted in IT block


VSELVS, singleprec variant

Applies when cc = 01 && sz = 0.

VSELVS.F32 <Sd>, <Sn>, <Sm>// Not permitted in IT block


Decode for all variants of this encoding

 dp_operation = (sz == '1');
 d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
 n = if dp_operation then UInt(N:Vn) else UInt(Vn:N);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
         cond = cc:(cc<1> EOR cc<0>):'0';
         if InITBlock() then UNPREDICTABLE;


        Assembler symbols

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dn>              Is the 64-bit name of the first SIMD&FP source register, encoded in the "N:Vn" field.

        <Dm>              Is the 64-bit name of the second SIMD&FP source register, encoded in the "M:Vm" field.

        <Sd>              Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

        <Sn>              Is the 32-bit name of the first SIMD&FP source register, encoded in the "Vn:N" field.

        <Sm>              Is the 32-bit name of the second SIMD&FP source register, encoded in the "Vm:M" field.


        Operation for all encodings

         EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
         if dp_operation then
               D[d] = if ConditionHolds(cond) then D[n] else D[m];
         else
               S[d] = if ConditionHolds(cond) then S[n] else S[m];


platform: ARM
mnem: VSHL
description:
Vector Shift Left (immediate) takes each element in a vector of integers, left shifts them by an immediate value, and       (F8.1.202)
places the results in the destination vector.

Bits shifted out of the left of each element are lost.

The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit integers. There is no distinction
between signed and unsigned integers.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 0 1 D                    imm6             Vd        0 1 0 1 L Q M 1              Vm




64-bit SIMD vector variant

Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

VSHL{<c>}{<q>}.I<size> {<Dd>,} <Dm>, #<imm>


128-bit SIMD vector variant

Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

VSHL{<c>}{<q>}.I<size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if L:imm6 == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
      when "0001xxx"    esize = 8;    elements = 8;   shift_amount = UInt(imm6) - 8;
      when "001xxxx"    esize = 16;    elements = 4;    shift_amount = UInt(imm6) - 16;
      when "01xxxxx"    esize = 32;    elements = 2;    shift_amount = UInt(imm6) - 32;
      when "1xxxxxx"    esize = 64;    elements = 1;    shift_amount = UInt(imm6);
 d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


T1


  15 14 13 12 11 10 9 8 7 6 5                        0 15       12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 0 1 1 1 1 1 D                    imm6             Vd        0 1 0 1 L Q M 1              Vm




64-bit SIMD vector variant

Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

VSHL{<c>}{<q>}.I<size> {<Dd>,} <Dm>, #<imm>


128-bit SIMD vector variant

Applies when !(imm6 == 000xxx && L == 0) && Q = 1.
        VSHL{<c>}{<q>}.I<size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if L:imm6 == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;     elements = 8;   shift_amount = UInt(imm6) - 8;
               when "001xxxx"    esize = 16;     elements = 4;    shift_amount = UInt(imm6) - 16;
               when "01xxxxx"    esize = 32;     elements = 2;    shift_amount = UInt(imm6) - 32;
               when "1xxxxxx"    esize = 64;     elements = 1;    shift_amount = UInt(imm6);
         d = UInt(D:Vd);      m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VSHL instruction must be
                          unconditional. ARM strongly recommends that a T32 VSHL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <size>            Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
                          following values:

                          8            when L = 0, imm6<5:3> = 001

                          16           when L = 0, imm6<5:3> = 01x

                          32           when L = 0, imm6<5:3> = 1xx

                          64           when L = 1, imm6<5:3> = xxx

        <Qd>              Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

        <Qm>              Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

        <Dd>              Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

        <Dm>              Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

        <imm>             Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               for r = 0 to regs-1
                   for e = 0 to elements-1
                        Elem[D[d+r],e,esize] = LSL(Elem[D[m+r],e,esize], shift_amount);


platform: ARM
mnem: VSHLL
description:
Vector Shift Left Long takes each element in a doubleword vector, left shifts them by an immediate value, and       (F8.1.204)
places the results in a quadword vector.

The operand elements can be:

.      8-bit, 16-bit, or 32-bit signed integers.

.      8-bit, 16-bit, or 32-bit unsigned integers.

.      8-bit, 16-bit, or 32-bit untyped integers, maximum shift only.

The result elements are twice the length of the operand elements.

Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
as a floating-point instruction encoding, see Conditional execution on page F2-2507.


A1


  31 30 29 28 27 26 25 24 23 22 21                 16 15        12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 U 1 D                     imm6            Vd         1 0 1 0 0 0 M 1              Vm




A1 variant

Applies when imm6 != 000xxx.

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>


Decode for this encoding

 if imm6 == '000xxx' then SEE "Related encodings";
 if Vd<0> == '1' then UNDEFINED;
 case imm6 of
      when "001xxx"    esize = 8;    elements = 8;   shift_amount = UInt(imm6) - 8;
      when "01xxxx"    esize = 16;    elements = 4;   shift_amount = UInt(imm6) - 16;
      when "1xxxxx"    esize = 32;    elements = 2;   shift_amount = UInt(imm6) - 32;
 if shift_amount == 0 then SEE VMOVL;
 unsigned = (U == '1');      d = UInt(D:Vd);    m = UInt(M:Vm);


A2


  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15            12 11 10 9 8 7 6 5 4 3                  0
   1 1 1 1 0 0 1 1 1 D 1 1 size 1 0                        Vd         0 0 1 1 0 0 M 0              Vm




A2 variant

VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>


Decode for this encoding

 if size == '11' || Vd<0> == '1' then UNDEFINED;
 esize = 8 << UInt(size);       elements = 64 DIV esize;   shift_amount = esize;
 unsigned = FALSE;     // Or TRUE without change of functionality
 d = UInt(D:Vd);     m = UInt(M:Vm);
        T1


           15 14 13 12 11 10 9 8 7 6 5                      0 15        12 11 10 9 8 7 6 5 4 3             0
            1 1 1 U 1 1 1 1 1 D                   imm6             Vd       1 0 1 0 0 0 M 1           Vm




        T1 variant

        Applies when imm6 != 000xxx.

        VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>


        Decode for this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if Vd<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"   esize = 8;    elements = 8;   shift_amount = UInt(imm6) - 8;
               when "01xxxx"   esize = 16;    elements = 4;   shift_amount = UInt(imm6) - 16;
               when "1xxxxx"   esize = 32;    elements = 2;   shift_amount = UInt(imm6) - 32;
         if shift_amount == 0 then SEE VMOVL;
         unsigned = (U == '1');     d = UInt(D:Vd);    m = UInt(M:Vm);


        T2


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                     12 11 10 9 8 7 6 5 4 3             0
            1 1 1 1 1 1 1 1 1 D 1 1 size 1 0                       Vd       0 0 1 1 0 0 M 0           Vm




        T2 variant

        VSHLL{<c>}{<q>}.<type><size> <Qd>, <Dm>, #<imm>


        Decode for this encoding

         if size == '11' || Vd<0> == '1' then UNDEFINED;
         esize = 8 << UInt(size);     elements = 64 DIV esize;     shift_amount = esize;
         unsigned = FALSE;     // Or TRUE without change of functionality
         d = UInt(D:Vd);     m = UInt(M:Vm);


        Notes for all encodings

        Related encodings: One register and a modified immediate value on page F5-2596.


        Assembler symbols

        <c>               See Standard assembler syntax fields on page F2-2506. An A32 VSHLL instruction must be
                          unconditional. ARM strongly recommends that a T32 VSHLL instruction is unconditional, see
                          Conditional execution on page F2-2507.

        <q>               See Standard assembler syntax fields on page F2-2506.

        <type>            The data type for the elements of the operand. It must be one of:

                          S          Signed. In encoding T1/A1, encoded as U = 0.

                          U          Unsigned. In encoding T1/A1, encoded as U = 1.

                          I          Untyped integer, Available only in encoding T2/A2.
<size>        The data size for the elements of the operand. The following table shows the permitted values and
              their encodings:


                                          <size>      Encoding T1/A1                       Encoding T2/A2

                                          8           Encoded as imm6<5:3> = 0b001         Encoded as size = 0b00

                                          16          Encoded as imm6<5:4> = 0b01          Encoded as size = 0b01

                                          32          Encoded as imm6<5> = 1               Encoded as size = 0b10


<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         The immediate value. <imm> must lie in the range 1 to <size>, and:

              .      If <size> == <imm>, the encoding is T2/A2.

              .      Otherwise, the encoding is T1/A1, and:

                     --      If <size> == 8, <imm> is encoded in imm6<2:0>.

                     --      If <size> == 16, <imm> is encoded in imm6<3:0>.

                     --      If <size> == 32, <imm> is encoded in imm6<4:0>.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();     CheckAdvSIMDEnabled();
    for e = 0 to elements-1
        result = Int(Elem[Din[m],e,esize], unsigned) << shift_amount;
        Elem[Q[d>>1],e,2*esize] = result<2*esize-1:0>;


platform: ARM
mnem: VSHR
description:
        Vector Shift Right takes each element in a vector, right shifts them by an immediate value, and places the truncated       (F8.1.205)
        results in the destination vector. For rounded results, see VRSHR.

        The operand and result elements must be the same size, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 U 1 D                     imm6            Vd      0 0 0 0 L Q M 1             Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "001xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "01xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
               when "1xxxxxx"    esize = 64;     elements = 1;   shift_amount = 64 - UInt(imm6);
         unsigned = (U == '1');       d = UInt(D:Vd);    m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15       12 11 10 9 8 7 6 5 4 3               0
            1 1 1 U 1 1 1 1 1 D                     imm6            Vd      0 0 0 0 L Q M 1             Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.
VSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = 16 - UInt(imm6);
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = 32 - UInt(imm6);
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = 64 - UInt(imm6);
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = 64 - UInt(imm6);
 unsigned = (U == '1');   d = UInt(D:Vd);    m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VSHR instruction must be
              unconditional. ARM strongly recommends that a T32 VSHR instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<type>        Is the data type for the elements of the vectors, encoded in the "U" field. It can have the following
              values:

              S            when U = 0

              U            when U = 1

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
             Elem[D[d+r],e,esize] = result<esize-1:0>;


platform: ARM
mnem: VSHRN
description:
        Vector Shift Right Narrow takes each element in a vector, right shifts them by an immediate value, and places the       (F8.1.207)
        truncated results in the destination vector. For rounded results, see VRSHRN.

        The operand elements can be 16-bit, 32-bit, or 64-bit integers. There is no distinction between signed and unsigned
        integers. The destination elements are half the size of the source elements.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                16 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 1 0 0 1 0 1 D                  imm6              Vd       1 0 0 0 0 0 M 1              Vm




        A1 variant

        Applies when imm6 != 000xxx.

        VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>


        Decode for this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"   esize = 8;   elements = 8;   shift_amount = 16 - UInt(imm6);
               when "01xxxx"   esize = 16;   elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"   esize = 32;   elements = 2;   shift_amount = 64 - UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);


        T1


           15 14 13 12 11 10 9 8 7 6 5                      0 15        12 11 10 9 8 7 6 5 4 3                0
            1 1 1 0 1 1 1 1 1 D                  imm6              Vd       1 0 0 0 0 0 M 1              Vm




        T1 variant

        Applies when imm6 != 000xxx.

        VSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm>


        Decode for this encoding

         if imm6 == '000xxx' then SEE "Related encodings";
         if Vm<0> == '1' then UNDEFINED;
         case imm6 of
               when "001xxx"   esize = 8;   elements = 8;   shift_amount = 16 - UInt(imm6);
               when "01xxxx"   esize = 16;   elements = 4;   shift_amount = 32 - UInt(imm6);
               when "1xxxxx"   esize = 32;   elements = 2;   shift_amount = 64 - UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);
Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VSHRN instruction must be
              unconditional. ARM strongly recommends that a T32 VSHRN instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<size>        Is the data size for the elements of the vectors, encoded in the "imm6<5:3>" field. It can have the
              following values:

              16          when imm6<5:3> = 001

              32          when imm6<5:3> = 01x

              64          when imm6<5:3> = 1xx

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<imm>         Is an immediate value, in the range 1 to <size>/2, encoded in the "imm6" field as <size>/2 - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for e = 0 to elements-1
         result = LSR(Elem[Qin[m>>1],e,2*esize], shift_amount);
         Elem[D[d],e,esize] = result<esize-1:0>;


platform: ARM
mnem: VSLI
description:
        Vector Shift Left and Insert takes each element in the operand vector, left shifts them by an immediate value, and       (F8.1.209)
        inserts the results in the destination vector. Bits shifted out of the left of each element are lost.

        The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between
        data types.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15         12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 1 1 D                    imm6              Vd        0 1 0 1 L Q M 1               Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSLI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSLI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;   elements = 8;     shift_amount = UInt(imm6) - 8;
               when "001xxxx"    esize = 16;   elements = 4;     shift_amount = UInt(imm6) - 16;
               when "01xxxxx"    esize = 32;   elements = 2;     shift_amount = UInt(imm6) - 32;
               when "1xxxxxx"    esize = 64;   elements = 1;     shift_amount = UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15         12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 1 1 1 1 1 D                    imm6              Vd        0 1 0 1 L Q M 1               Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSLI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSLI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm>
Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = UInt(imm6) - 8;
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = UInt(imm6) - 16;
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = UInt(imm6) - 32;
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = UInt(imm6);
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VSLI instruction must be
              unconditional. ARM strongly recommends that a T32 VSLI instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 0 to <size>-1, encoded in the "imm6" field.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     mask = LSL(Ones(esize), shift_amount);
     for r = 0 to regs-1
         for e = 0 to elements-1
             shifted_op = LSL(Elem[D[m+r],e,esize], shift_amount);
             Elem[D[d+r],e,esize] = (Elem[D[d+r],e,esize] AND NOT(mask)) OR shifted_op;


platform: ARM
mnem: VSQRT
description:
        Square Root calculates the square root of the value in a floating-point register and writes the result to another       (F8.1.210)
        floating-point register.

        Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in
        which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp
        mode. For more information see Enabling Advanced SIMD and floating-point support on page G1-3896.


        A1


           31        28 27 26 25 24 23 22 21 20 19 18 17 16 15         12 11 10 9 8 7 6 5 4 3                   0
              !=1111     1 1 1 0 1 D 1 1 0 0 0 1                  Vd       1 0 1 sz 1 1 M 0              Vm
               cond


        Single-precision scalar variant

        Applies when sz = 0.

        VSQRT{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VSQRT{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15                    12 11 10 9 8 7 6 5 4 3                   0
            1 1 1 0 1 1 1 0 1 D 1 1 0 0 0 1                       Vd       1 0 1 sz 1 1 M 0              Vm




        Single-precision scalar variant

        Applies when sz = 0.

        VSQRT{<c>}{<q>}.F32 <Sd>, <Sm>


        Double-precision scalar variant

        Applies when sz = 1.

        VSQRT{<c>}{<q>}.F64 <Dd>, <Dm>


        Decode for all variants of this encoding

         if FPSCR.Len != '000' || FPSCR.Stride != '00' then UNDEFINED;
         dp_operation = (sz == '1');
         d = if dp_operation then UInt(D:Vd) else UInt(Vd:D);
         m = if dp_operation then UInt(M:Vm) else UInt(Vm:M);
Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506.

<q>           See Standard assembler syntax fields on page F2-2506.

<Sd>          Is the 32-bit name of the SIMD&FP destination register, encoded in the "Vd:D" field.

<Sm>          Is the 32-bit name of the SIMD&FP source register, encoded in the "Vm:M" field.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.


Operation for all encodings

 if ConditionPassed() then
    EncodingSpecificOperations();    CheckVFPEnabled(TRUE);
    if dp_operation then
        D[d] = FPSqrt(D[m], StandardFPSCRValue());
    else
        S[d] = FPSqrt(S[m], StandardFPSCRValue());


platform: ARM
mnem: VSRA
description:
        Vector Shift Right and Accumulate takes each element in a vector, right shifts them by an immediate value, and       (F8.1.211)
        accumulates the truncated results into the destination vector. For rounded results, see VRSRA.

        The operand and result elements must all be the same type, and can be any one of:

        .       8-bit, 16-bit, 32-bit, or 64-bit signed integers.

        .       8-bit, 16-bit, 32-bit, or 64-bit unsigned integers.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15       12 11 10 9 8 7 6 5 4 3             0
            1 1 1 1 0 0 1 U 1 D                     imm6            Vd      0 0 0 1 L Q M 1            Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;    elements = 8;    shift_amount = 16 - UInt(imm6);
               when "001xxxx"    esize = 16;     elements = 4;   shift_amount = 32 - UInt(imm6);
               when "01xxxxx"    esize = 32;     elements = 2;   shift_amount = 64 - UInt(imm6);
               when "1xxxxxx"    esize = 64;     elements = 1;   shift_amount = 64 - UInt(imm6);
         unsigned = (U == '1');       d = UInt(D:Vd);    m = UInt(M:Vm);  regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15       12 11 10 9 8 7 6 5 4 3             0
            1 1 1 U 1 1 1 1 1 D                     imm6            Vd      0 0 0 1 L Q M 1            Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSRA{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.
VSRA{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>


Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = 16 - UInt(imm6);
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = 32 - UInt(imm6);
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = 64 - UInt(imm6);
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = 64 - UInt(imm6);
 unsigned = (U == '1');   d = UInt(D:Vd);    m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VSRA instruction must be
              unconditional. ARM strongly recommends that a T32 VSRA instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<type>        Is the data type for the elements of the vectors, encoded in the "U" field. It can have the following
              values:

              S            when U = 0

              U            when U = 1

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     for r = 0 to regs-1
         for e = 0 to elements-1
             result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
             Elem[D[d+r],e,esize] = Elem[D[d+r],e,esize] + result;


platform: ARM
mnem: VSRI
description:
        Vector Shift Right and Insert takes each element in the operand vector, right shifts them by an immediate value, and       (F8.1.212)
        inserts the results in the destination vector. Bits shifted out of the right of each element are lost.

        The elements must all be the same size, and can be 8-bit, 16-bit, 32-bit, or 64-bit. There is no distinction between
        data types.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21                  16 15         12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 0 0 1 1 1 D                    imm6              Vd        0 1 0 0 L Q M 1               Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSRI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSRI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm>


        Decode for all variants of this encoding

         if (L:imm6) == '0000xxx' then SEE "Related encodings";
         if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
         case L:imm6 of
               when "0001xxx"    esize = 8;   elements = 8;     shift_amount = 16 - UInt(imm6);
               when "001xxxx"    esize = 16;   elements = 4;     shift_amount = 32 - UInt(imm6);
               when "01xxxxx"    esize = 32;   elements = 2;     shift_amount = 64 - UInt(imm6);
               when "1xxxxxx"    esize = 64;   elements = 1;     shift_amount = 64 - UInt(imm6);
         d = UInt(D:Vd);     m = UInt(M:Vm);    regs = if Q == '0' then 1 else 2;


        T1


           15 14 13 12 11 10 9 8 7 6 5                        0 15         12 11 10 9 8 7 6 5 4 3               0
            1 1 1 1 1 1 1 1 1 D                    imm6              Vd        0 1 0 0 L Q M 1               Vm




        64-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 0.

        VSRI{<c>}{<q>}.<size> {<Dd>,} <Dm>, #<imm>


        128-bit SIMD vector variant

        Applies when !(imm6 == 000xxx && L == 0) && Q = 1.

        VSRI{<c>}{<q>}.<size> {<Qd>,} <Qm>, #<imm>
Decode for all variants of this encoding

 if (L:imm6) == '0000xxx' then SEE "Related encodings";
 if Q == '1' && (Vd<0> == '1' || Vm<0> == '1') then UNDEFINED;
 case L:imm6 of
     when "0001xxx"  esize = 8;     elements = 8;   shift_amount = 16 - UInt(imm6);
     when "001xxxx"  esize = 16;     elements = 4;    shift_amount = 32 - UInt(imm6);
     when "01xxxxx"  esize = 32;     elements = 2;    shift_amount = 64 - UInt(imm6);
     when "1xxxxxx"  esize = 64;     elements = 1;    shift_amount = 64 - UInt(imm6);
 d = UInt(D:Vd);  m = UInt(M:Vm);     regs = if Q == '0' then 1 else 2;


Notes for all encodings

Related encodings: One register and a modified immediate value on page F5-2596.


Assembler symbols

<c>           See Standard assembler syntax fields on page F2-2506. An A32 VSRI instruction must be
              unconditional. ARM strongly recommends that a T32 VSRI instruction is unconditional, see
              Conditional execution on page F2-2507.

<q>           See Standard assembler syntax fields on page F2-2506.

<size>        Is the data size for the elements of the vectors, encoded in the "L:imm6<5:3>" field. It can have the
              following values:

              8            when L = 0, imm6<5:3> = 001

              16           when L = 0, imm6<5:3> = 01x

              32           when L = 0, imm6<5:3> = 1xx

              64           when L = 1, imm6<5:3> = xxx

<Qd>          Is the 128-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field as <Qd>*2.

<Qm>          Is the 128-bit name of the SIMD&FP source register, encoded in the "M:Vm" field as <Qm>*2.

<Dd>          Is the 64-bit name of the SIMD&FP destination register, encoded in the "D:Vd" field.

<Dm>          Is the 64-bit name of the SIMD&FP source register, encoded in the "M:Vm" field.

<imm>         Is an immediate value, in the range 1 to <size>, encoded in the "imm6" field as <size> - <imm>.


Operation for all encodings

 if ConditionPassed() then
     EncodingSpecificOperations();     CheckAdvSIMDEnabled();
     mask = LSR(Ones(esize), shift_amount);
     for r = 0 to regs-1
         for e = 0 to elements-1
             shifted_op = LSR(Elem[D[m+r],e,esize], shift_amount);
             Elem[D[d+r],e,esize] = (Elem[D[d+r],e,esize] AND NOT(mask)) OR shifted_op;


platform: ARM
mnem: VST1
description:
        Store single element from one lane of one register stores one element to memory from one element of a register. For       (F8.1.213)
        details of the addressing mode see Advanced SIMD addressing mode on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7          4 3         0
            1 1 1 1 0 1 0 0 1 D 0 0                   Rn           Vd      !=11 0 0 index_align        Rm
                                                                           size


        Offset variant

        Applies when Rm = 1111.

        VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         case size of
               when '00'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 1;   index = UInt(index_align<3:1>);     alignment = 1;
               when '01'
                   if index_align<1> != '0' then UNDEFINED;
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   alignment = if index_align<0> == '0' then 1 else 2;
               when '10'
                   if index_align<2> != '0' then UNDEFINED;
                   if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   alignment = if index_align<1:0> == '00' then 1 else 4;
         d = UInt(D:Vd);     n = UInt(Rn);   m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7          4 3         0
            1 1 1 1 1 0 0 1 1 D 0 0                   Rn           Vd      !=11 0 0 index_align        Rm
                                                                           size
Offset variant

Applies when Rm = 1111.

VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 case size of
     when '00'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 1;   index = UInt(index_align<3:1>);     alignment = 1;
     when '01'
         if index_align<1> != '0' then UNDEFINED;
         ebytes = 2;   index = UInt(index_align<3:2>);
         alignment = if index_align<0> == '0' then 1 else 2;
     when '10'
         if index_align<2> != '0' then UNDEFINED;
         if index_align<1:0> != '00' && index_align<1:0> != '11' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         alignment = if index_align<1:0> == '00' then 1 else 4;
 d = UInt(D:Vd);  n = UInt(Rn);    m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VST1 instruction must be
               unconditional. ARM strongly recommends that a T32 VST1 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The register containing the element to store. It must be {<Dd[x]>}. The register <Dd> is encoded in
               D:Vd.

<Rn>           Contains the base address for the access.

<align>        The alignment. It can be one of:

               16          2-byte alignment, available only if <size> is 16.
                          32           4-byte alignment, available only if <size> is 32.

                          omitted      Standard alignment, see Unaligned data access on page E2-2427.

                          : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
                          see Advanced SIMD addressing mode on page F5-2605.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

        Table F8-5 shows the encoding of index and alignment for different <size> values.

                                                                          Table F8-5 Encoding of index and alignment

                                              <size> == 8              <size> == 16                 <size> == 32

                         Index                index_align[3:1] = x     index_align[3:2] = x         index_align[3] = x

                         <align> omitted      index_align[0] = 0       index_align[1:0] = '00'      index_align[2:0] = '000'

                         <align> == 16        -                        index_align[1:0] = '01'      -

                         <align> == 32        -                        -                            index_align[2:0] = '011'



        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();      CheckAdvSIMDEnabled();
               address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + ebytes;
               MemU[address,ebytes] = Elem[D[d],index];


platform: ARM
mnem: VST2
description:
        Store single 2-element structure from one lane of two registers stores one 2-element structure to memory from       (F8.1.215)
        corresponding elements of two registers. For details of the addressing mode see Advanced SIMD addressing mode
        on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7           4 3         0
            1 1 1 1 0 1 0 0 1 D 0 0                   Rn           Vd      !=11 0 1 index_align         Rm
                                                                           size


        Offset variant

        Applies when Rm = 1111.

        VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         case size of
               when '00'
                   ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
                   alignment = if index_align<0> == '0' then 1 else 2;
               when '01'
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 4;
               when '10'
                   if index_align<1> != '0' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 8;
         d = UInt(D:Vd);     d2 = d + inc;   n = UInt(Rn);   m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d2 > 31 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7           4 3         0
            1 1 1 1 1 0 0 1 1 D 0 0                   Rn           Vd      !=11 0 1 index_align         Rm
                                                                           size
Offset variant

Applies when Rm = 1111.

VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VST2{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 case size of
     when '00'
         ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
         alignment = if index_align<0> == '0' then 1 else 2;
     when '01'
         ebytes = 2;   index = UInt(index_align<3:2>);
         inc = if index_align<1> == '0' then 1 else 2;
         alignment = if index_align<0> == '0' then 1 else 4;
     when '10'
         if index_align<1> != '0' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         inc = if index_align<2> == '0' then 1 else 2;
         alignment = if index_align<0> == '0' then 1 else 8;
 d = UInt(D:Vd);  d2 = d + inc;    n = UInt(Rn);   m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 || d2 > 31 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST2 (single 2-element structure from
one lane) on page J1-5391.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VST2 instruction must be
               unconditional. ARM strongly recommends that a T32 VST2 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

               {<Dd[x]>, <Dd+1[x]>}
                           Single-spaced registers, see Table F8-6 on page F8-3740.

               {<Dd[x]>, <Dd+2[x]>}
                           Double-spaced registers, see Table F8-6 on page F8-3740.
                          This is not available if <size> == 8.

        <Rn>              Contains the base address for the access.

        <align>           The alignment. It can be one of:

                          16           2-byte alignment, available only if <size> is 8.

                          32           4-byte alignment, available only if <size> is 16.

                          64           8-byte alignment, available only if <size> is 32.

                          omitted      Standard alignment, see Unaligned data access on page E2-2427.

                          : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
                          see Advanced SIMD addressing mode on page F5-2605.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                                    Table F8-6 Encoding of index, alignment, and register spacing

                                                  <size> == 8              <size> == 16              <size> == 32

                             Index                index_align[3:1] = x     index_align[3:2] = x      index_align[3] = x

                             Single-spacing       -                        index_align[1] = 0        index_align[2] = 0

                             Double-spacing       -                        index_align[1] = 1        index_align[2] = 1

                             <align> omitted      index_align[0] = 0       index_align[0] = 0        index_align[1:0] = '00'

                             <align> == 16        index_align[0] = 1       -                         -

                             <align> == 32        -                        index_align[0] = 1        -

                             <align> == 64        -                        -                         index_align[1:0] = '01'



        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + 2*ebytes;
               MemU[address,          ebytes] = Elem[D[d], index];
               MemU[address+ebytes,ebytes] = Elem[D[d2],index];


platform: ARM
mnem: VST3
description:
        Store single 3-element structure from one lane of three registers stores one 3-element structure to memory from       (F8.1.217)
        corresponding elements of three registers. For details of the addressing mode see Advanced SIMD addressing mode
        on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15        12 11 10 9 8 7           4 3         0
            1 1 1 1 0 1 0 0 1 D 0 0                   Rn           Vd       !=11 1 0 index_align        Rm
                                                                            size


        Offset variant

        Applies when Rm = 1111.

        VST3{<c>}{<q>}.<size> <list>, [<Rn>]


        Post-indexed variant

        Applies when Rm = 1101.

        VST3{<c>}{<q>}.<size> <list>, [<Rn>]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         case size of
               when '00'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 1;   index = UInt(index_align<3:1>);      inc = 1;
               when '01'
                   if index_align<0> != '0' then UNDEFINED;
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
               when '10'
                   if index_align<1:0> != '00' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
         d = UInt(D:Vd);     d2 = d + inc;   d3 = d2 + inc;   n = UInt(Rn);    m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d3 > 31 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15        12 11 10 9 8 7           4 3         0
            1 1 1 1 1 0 0 1 1 D 0 0                   Rn           Vd       !=11 1 0 index_align        Rm
                                                                            size
Offset variant

Applies when Rm = 1111.

VST3{<c>}{<q>}.<size> <list>, [<Rn>]


Post-indexed variant

Applies when Rm = 1101.

VST3{<c>}{<q>}.<size> <list>, [<Rn>]!


Post-indexed variant

Applies when Rm != 11x1.

VST3{<c>}{<q>}.<size> <list>, [<Rn>], <Rm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 case size of
     when '00'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
     when '01'
         if index_align<0> != '0' then UNDEFINED;
         ebytes = 2;   index = UInt(index_align<3:2>);
         inc = if index_align<1> == '0' then 1 else 2;
     when '10'
         if index_align<1:0> != '00' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         inc = if index_align<2> == '0' then 1 else 2;
 d = UInt(D:Vd);  d2 = d + inc;    d3 = d2 + inc;    n = UInt(Rn);     m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 || d3 > 31 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST3 (single 3-element structure from
one lane) on page J1-5392.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VST3 instruction must be
               unconditional. ARM strongly recommends that a T32 VST3 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

               {<Dd[x]>, <Dd+1[x]>, <Dd+2[x]>}
                           Single-spaced registers, see Table F8-7 on page F8-3746.

               {<Dd[x]>, <Dd+2[x]>, <Dd+4[x]>}
                           Double-spaced registers, see Table F8-7 on page F8-3746.

               This is not available if <size> == 8.
        <Rn>              Contains the base address for the access.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                                                 Table F8-7 Encoding of index and register spacing

                                            <size> == 8               <size> == 16            <size> == 32

                         Index              index_align[3:1] = x      index_align[3:2] = x    index_align[3] = x

                         Single-spacing     index_align[0] = 0        index_align[1:0] = '00' index_align[2:0] = '000'

                         Double-spacing     -                         index_align[1:0] = '10' index_align[2:0] = '100'



        Alignment

        Standard alignment rules apply, see Alignment support on page B2-75.


        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();    CheckAdvSIMDEnabled();
               address = R[n];
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + 3*ebytes;
               MemU[address,           ebytes] = Elem[D[d], index];
               MemU[address+ebytes,    ebytes] = Elem[D[d2],index];
               MemU[address+2*ebytes,ebytes] = Elem[D[d3],index];


platform: ARM
mnem: VST4
description:
        Store single 4-element structure from one lane of four registers stores one 4-element structure to memory from       (F8.1.219)
        corresponding elements of four registers. For details of the addressing mode see Advanced SIMD addressing mode
        on page F5-2605.

        Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the
        instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. For
        more information see Enabling Advanced SIMD and floating-point support on page G1-3896.

        ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available
        as a floating-point instruction encoding, see Conditional execution on page F2-2507.


        A1


           31 30 29 28 27 26 25 24 23 22 21 20 19          16 15       12 11 10 9 8 7            4 3         0
            1 1 1 1 0 1 0 0 1 D 0 0                   Rn           Vd      !=11 1 1 index_align         Rm
                                                                           size


        Offset variant

        Applies when Rm = 1111.

        VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


        Post-indexed variant

        Applies when Rm = 1101.

        VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


        Post-indexed variant

        Applies when Rm != 11x1.

        VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


        Decode for all variants of this encoding

         if size == '11' then UNDEFINED;
         case size of
               when '00'
                   ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
                   alignment = if index_align<0> == '0' then 1 else 4;
               when '01'
                   ebytes = 2;   index = UInt(index_align<3:2>);
                   inc = if index_align<1> == '0' then 1 else 2;
                   alignment = if index_align<0> == '0' then 1 else 8;
               when '10'
                   if index_align<1:0> == '11' then UNDEFINED;
                   ebytes = 4;   index = UInt(index_align<3>);
                   inc = if index_align<2> == '0' then 1 else 2;
                   alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>);
         d = UInt(D:Vd);     d2 = d + inc;   d3 = d2 + inc;   d4 = d3 + inc;    n = UInt(Rn);  m = UInt(Rm);
         wback = (m != 15);     register_index = (m != 15 && m != 13);
         if n == 15 || d4 > 31 then UNPREDICTABLE;


        T1


           15 14 13 12 11 10 9 8 7 6 5 4 3                  0 15       12 11 10 9 8 7            4 3         0
            1 1 1 1 1 0 0 1 1 D 0 0                   Rn           Vd      !=11 1 1 index_align         Rm
                                                                           size
Offset variant

Applies when Rm = 1111.

VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]


Post-indexed variant

Applies when Rm = 1101.

VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]!


Post-indexed variant

Applies when Rm != 11x1.

VST4{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm>


Decode for all variants of this encoding

 if size == '11' then UNDEFINED;
 case size of
     when '00'
         ebytes = 1;   index = UInt(index_align<3:1>);     inc = 1;
         alignment = if index_align<0> == '0' then 1 else 4;
     when '01'
         ebytes = 2;   index = UInt(index_align<3:2>);
         inc = if index_align<1> == '0' then 1 else 2;
         alignment = if index_align<0> == '0' then 1 else 8;
     when '10'
         if index_align<1:0> == '11' then UNDEFINED;
         ebytes = 4;   index = UInt(index_align<3>);
         inc = if index_align<2> == '0' then 1 else 2;
         alignment = if index_align<1:0> == '00' then 1 else 4 << UInt(index_align<1:0>);
 d = UInt(D:Vd);  d2 = d + inc;    d3 = d2 + inc;    d4 = d3 + inc;      n = UInt(Rn);    m = UInt(Rm);
 wback = (m != 15);   register_index = (m != 15 && m != 13);
 if n == 15 || d4 > 31 then UNPREDICTABLE;


Notes for all encodings

For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Appendix J1
Architectural Constraints on UNPREDICTABLE behaviors, and particularly VST4 (single 4-element structure from
one lane) on page J1-5393.


Assembler symbols

<c>            See Standard assembler syntax fields on page F2-2506. An A32 VST4 instruction must be
               unconditional. ARM strongly recommends that a T32 VST4 instruction is unconditional, see
               Conditional execution on page F2-2507.

<q>            See Standard assembler syntax fields on page F2-2506.

<size>         The data size. It must be one of:

               8           Encoded as size = 0b00.

               16          Encoded as size = 0b01.

               32          Encoded as size = 0b10.

<list>         The registers containing the structure. Encoded with D:Vd = <Dd>. It must be one of:

               {<Dd[x]>, <Dd+1[x]>, <Dd+2[x]>, <Dd+3[x]>}
                           Single-spaced registers, see Table F8-8 on page F8-3752.

               {<Dd[x]>, <Dd+2[x]>, <Dd+4[x]>, <Dd+6[x]>}
                           Double-spaced registers, see Table F8-8 on page F8-3752.
                          This is not available if <size> == 8.

        <Rn>              The base address for the access.

        <align>           The alignment. It can be:

                          32           4-byte alignment, available only if <size> is 8.

                          64           8-byte alignment, available only if <size> is 16 or 32.

                          128          16-byte alignment, available only if <size> is 32.

                          omitted      Standard alignment, see Unaligned data access on page E2-2427.

                          : is the preferred separator before the <align> value, but the alignment can be specified as @<align>,
                          see Advanced SIMD addressing mode on page F5-2605.

        <Rm>              Contains an address offset applied after the access.

        For more information about <Rn>, !, and <Rm>, see Advanced SIMD addressing mode on page F5-2605.

                                                    Table F8-8 Encoding of index, alignment, and register spacing

                                                  <size> == 8              <size> == 16              <size> == 32

                             Index                index_align[3:1] = x     index_align[3:2] = x      index_align[3] = x

                             Single-spacing       -                        index_align[1] = 0        index_align[2] = 0

                             Double-spacing       -                        index_align[1] = 1        index_align[2] = 1

                             <align> omitted      index_align[0] = 0       index_align[0] = 0        index_align[1:0] = '00'

                             <align> == 32        index_align[0] = 1       -                         -

                             <align> == 64        -                        index_align[0] = 1        index_align[1:0] = '01'

                             <align> == 128       -                        -                         index_align[1:0] = '10'



        Operation for all encodings

         if ConditionPassed() then
               EncodingSpecificOperations();       CheckAdvSIMDEnabled();
               address = R[n];     if (address MOD alignment) != 0 then GenerateAlignmentException();
               if wback then
                   if register_index then
                        R[n] = R[n] + R[m];
                   else
                        R[n] = R[n] + 4*ebytes;
               MemU[address,            ebytes] = Elem[D[d], index];
               MemU[address+ebytes,     ebytes] = Elem[D[d2],index];
               MemU[address+2*ebytes,ebytes] = Elem[D[d3],index];
               MemU[address+3*ebytes,ebytes] = Elem[D[d4],index];


