# instructions

platform: x86_64
mnem: VPSLLVW
description:
VPSLLVW/VPSLLVD/VPSLLVQ-Variable Bit Shift Left Logical
 Opcode/                                  Op /     64/32        CPUID      Description
 Instruction                              En       bit Mode     Feature
                                                   Support      Flag
 VEX.NDS.128.66.0F38.W0 47 /r             RVM      V/V          AVX2       Shift doublewords in xmm2 left by amount specified in
 VPSLLVD xmm1, xmm2, xmm3/m128                                             the corresponding element of xmm3/m128 while
                                                                           shifting in 0s.
 VEX.NDS.128.66.0F38.W1 47 /r             RVM      V/V          AVX2       Shift quadwords in xmm2 left by amount specified in
 VPSLLVQ xmm1, xmm2, xmm3/m128                                             the corresponding element of xmm3/m128 while
                                                                           shifting in 0s.
 VEX.NDS.256.66.0F38.W0 47 /r             RVM      V/V          AVX2       Shift doublewords in ymm2 left by amount specified in
 VPSLLVD ymm1, ymm2, ymm3/m256                                             the corresponding element of ymm3/m256 while
                                                                           shifting in 0s.
 VEX.NDS.256.66.0F38.W1 47 /r             RVM      V/V          AVX2       Shift quadwords in ymm2 left by amount specified in
 VPSLLVQ ymm1, ymm2, ymm3/m256                                             the corresponding element of ymm3/m256 while
                                                                           shifting in 0s.
 EVEX.NDS.128.66.0F38.W1 12 /r            FVM      V/V          AVX512VL   Shift words in xmm2 left by amount specified in the
 VPSLLVW xmm1 {k1}{z}, xmm2,                                    AVX512BW   corresponding element of xmm3/m128 while shifting
 xmm3/m128                                                                 in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W1 12 /r            FVM      V/V          AVX512VL   Shift words in ymm2 left by amount specified in the
 VPSLLVW ymm1 {k1}{z}, ymm2,                                    AVX512BW   corresponding element of ymm3/m256 while shifting
 ymm3/m256                                                                 in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W1 12 /r            FVM      V/V          AVX512BW   Shift words in zmm2 left by amount specified in the
 VPSLLVW zmm1 {k1}{z}, zmm2,                                               corresponding element of zmm3/m512 while shifting
 zmm3/m512                                                                 in 0s using writemask k1.
 EVEX.NDS.128.66.0F38.W0 47 /r            FV       V/V          AVX512VL   Shift doublewords in xmm2 left by amount specified in
 VPSLLVD xmm1 {k1}{z}, xmm2,                                    AVX512F    the corresponding element of xmm3/m128/m32bcst
 xmm3/m128/m32bcst                                                         while shifting in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W0 47 /r            FV       V/V          AVX512VL   Shift doublewords in ymm2 left by amount specified in
 VPSLLVD ymm1 {k1}{z}, ymm2,                                    AVX512F    the corresponding element of ymm3/m256/m32bcst
 ymm3/m256/m32bcst                                                         while shifting in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W0 47 /r            FV       V/V          AVX512F    Shift doublewords in zmm2 left by amount specified in
 VPSLLVD zmm1 {k1}{z}, zmm2,                                               the corresponding element of zmm3/m512/m32bcst
 zmm3/m512/m32bcst                                                         while shifting in 0s using writemask k1.
 EVEX.NDS.128.66.0F38.W1 47 /r            FV       V/V          AVX512VL   Shift quadwords in xmm2 left by amount specified in
 VPSLLVQ xmm1 {k1}{z}, xmm2,                                    AVX512F    the corresponding element of xmm3/m128/m64bcst
 xmm3/m128/m64bcst                                                         while shifting in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W1 47 /r            FV       V/V          AVX512VL   Shift quadwords in ymm2 left by amount specified in
 VPSLLVQ ymm1 {k1}{z}, ymm2,                                    AVX512F    the corresponding element of ymm3/m256/m64bcst
 ymm3/m256/m64bcst                                                         while shifting in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W1 47 /r            FV       V/V          AVX512F    Shift quadwords in zmm2 left by amount specified in
 VPSLLVQ zmm1 {k1}{z}, zmm2,                                               the corresponding element of zmm3/m512/m64bcst
 zmm3/m512/m64bcst                                                         while shifting in 0s using writemask k1.



                                                  Instruction Operand Encoding
        Op/En                 Operand 1                    Operand 2               Operand 3                  Operand 4
         RVM                ModRM:reg (w)                 VEX.vvvv (r)           ModRM:r/m (r)                    NA
         FVM                ModRM:reg (w)                 EVEX.vvvv (r)          ModRM:r/m (r)                    NA
          FV                ModRM:reg (w)                 EVEX.vvvv (r)          ModRM:r/m (r)                    NA





Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
left by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted left, the empty low-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSLLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSLLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.

Operation
VPSLLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- ZeroExtend(SRC1[i+15:i] << SRC2[i+15:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSLLVD (VEX.128 version)
COUNT_0 <-SRC2[31 : 0]
    (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <-SRC2[100 : 96];
IF COUNT_0 < 32 THEN
DEST[31:0] <-ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] <-0;
    (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
DEST[127:96] <-ZeroExtend(SRC1[127:96] << COUNT_3);
ELSE
DEST[127:96] <-0;
DEST[MAX_VL-1:128] <-0;

VPSLLVD (VEX.256 version)
COUNT_0 <-SRC2[31 : 0];
    (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 <-SRC2[228 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] <-ZeroExtend(SRC1[31:0] << COUNT_0);
ELSE
DEST[31:0] <-0;
    (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
DEST[255:224] <-ZeroExtend(SRC1[255:224] << COUNT_7);
ELSE
DEST[255:224] <-0;
DEST[MAX_VL-1:256] <- 0;

VPSLLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] << SRC2[31:0])
                    ELSE DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] << SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSLLVQ (VEX.128 version)
COUNT_0 <-SRC2[63 : 0];
COUNT_1 <-SRC2[127 : 64];
IF COUNT_0 < 64THEN
DEST[63:0] <-ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] <-0;
IF COUNT_1 < 64 THEN
DEST[127:64] <-ZeroExtend(SRC1[127:64] << COUNT_1);
ELSE
DEST[127:96] <-0;
DEST[MAX_VL-1:128] <-0;

VPSLLVQ (VEX.256 version)
COUNT_0 <-SRC2[63 : 0];
    (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <-SRC2[197 : 192];
IF COUNT_0 < 64THEN
DEST[63:0] <-ZeroExtend(SRC1[63:0] << COUNT_0);
ELSE
DEST[63:0] <-0;
    (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
DEST[255:192] <-ZeroExtend(SRC1[255:192] << COUNT_3);
ELSE
DEST[255:192] <-0;
DEST[MAX_VL-1:256] <- 0;

VPSLLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] << SRC2[63:0])
                    ELSE DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] << SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





Intel C/C++ Compiler Intrinsic Equivalent
VPSLLVW __m512i _mm512_sllv_epi16(__m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_mask_sllv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m512i _mm512_maskz_sllv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSLLVW __m256i _mm256_mask_sllv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m256i _mm256_maskz_sllv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSLLVW __m128i _mm_mask_sllv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVW __m128i _mm_maskz_sllv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m512i _mm512_sllv_epi32(__m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_mask_sllv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m512i _mm512_maskz_sllv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVQ __m512i _mm512_sllv_epi64(__m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_mask_sllv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSLLVQ __m512i _mm512_maskz_sllv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSLLVD __m256i _mm256_mask_sllv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m256i _mm256_maskz_sllv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSLLVD __m128i _mm_mask_sllv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m128i _mm_maskz_sllv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSLLVD __m256i _mm256_sllv_epi32 (__m256i m, __m256i count)
VPSLLVQ __m256i _mm256_sllv_epi64 (__m256i m, __m256i count)

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded VPSLLVD/VPSLLVQ, see Exceptions Type E4.
EVEX-encoded VPSLLVW, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPSRAVW
description:
VPSRAVW/VPSRAVD/VPSRAVQ-Variable Bit Shift Right Arithmetic
 Opcode/                              Op/    64/32         CPUID          Description
 Instruction                          En     bit Mode      Feature
                                             Support       Flag
 VEX.NDS.128.66.0F38.W0 46 /r         RVM    V/V           AVX2           Shift doublewords in xmm2 right by amount specified
 VPSRAVD xmm1, xmm2, xmm3/m128                                            in the corresponding element of xmm3/m128 while
                                                                          shifting in sign bits.
 VEX.NDS.256.66.0F38.W0 46 /r         RVM    V/V           AVX2           Shift doublewords in ymm2 right by amount specified
 VPSRAVD ymm1, ymm2, ymm3/m256                                            in the corresponding element of ymm3/m256 while
                                                                          shifting in sign bits.
 EVEX.NDS.128.66.0F38.W1 11 /r        FVM    V/V           AVX512VL       Shift words in xmm2 right by amount specified in the
 VPSRAVW xmm1 {k1}{z}, xmm2,                               AVX512BW       corresponding element of xmm3/m128 while shifting
 xmm3/m128                                                                in sign bits using writemask k1.
 EVEX.NDS.256.66.0F38.W1 11 /r        FVM    V/V           AVX512VL       Shift words in ymm2 right by amount specified in the
 VPSRAVW ymm1 {k1}{z}, ymm2,                               AVX512BW       corresponding element of ymm3/m256 while shifting
 ymm3/m256                                                                in sign bits using writemask k1.
 EVEX.NDS.512.66.0F38.W1 11 /r        FVM    V/V           AVX512BW       Shift words in zmm2 right by amount specified in the
 VPSRAVW zmm1 {k1}{z}, zmm2,                                              corresponding element of zmm3/m512 while shifting
 zmm3/m512                                                                in sign bits using writemask k1.
 EVEX.NDS.128.66.0F38.W0 46 /r        FV     V/V           AVX512VL       Shift doublewords in xmm2 right by amount specified
 VPSRAVD xmm1 {k1}{z}, xmm2,                               AVX512F        in the corresponding element of
 xmm3/m128/m32bcst                                                        xmm3/m128/m32bcst while shifting in sign bits
                                                                          using writemask k1.
 EVEX.NDS.256.66.0F38.W0 46 /r        FV     V/V           AVX512VL       Shift doublewords in ymm2 right by amount specified
 VPSRAVD ymm1 {k1}{z}, ymm2,                               AVX512F        in the corresponding element of
 ymm3/m256/m32bcst                                                        ymm3/m256/m32bcst while shifting in sign bits
                                                                          using writemask k1.
 EVEX.NDS.512.66.0F38.W0 46 /r        FV     V/V           AVX512F        Shift doublewords in zmm2 right by amount specified
 VPSRAVD zmm1 {k1}{z}, zmm2,                                              in the corresponding element of
 zmm3/m512/m32bcst                                                        zmm3/m512/m32bcst while shifting in sign bits using
                                                                          writemask k1.
 EVEX.NDS.128.66.0F38.W1 46 /r        FV     V/V           AVX512VL       Shift quadwords in xmm2 right by amount specified
 VPSRAVQ xmm1 {k1}{z}, xmm2,                               AVX512F        in the corresponding element of
 xmm3/m128/m64bcst                                                        xmm3/m128/m64bcst while shifting in sign bits
                                                                          using writemask k1.
 EVEX.NDS.256.66.0F38.W1 46 /r        FV     V/V           AVX512VL       Shift quadwords in ymm2 right by amount specified
 VPSRAVQ ymm1 {k1}{z}, ymm2,                               AVX512F        in the corresponding element of
 ymm3/m256/m64bcst                                                        ymm3/m256/m64bcst while shifting in sign bits
                                                                          using writemask k1.

 EVEX.NDS.512.66.0F38.W1 46 /r        FV     V/V           AVX512F        Shift quadwords in zmm2 right by amount specified in
 VPSRAVQ zmm1 {k1}{z}, zmm2,                                              the corresponding element of zmm3/m512/m64bcst
 zmm3/m512/m64bcst                                                        while shifting in sign bits using writemask k1.



                                            Instruction Operand Encoding
      Op/En             Operand 1                  Operand 2                    Operand 3                   Operand 4
       RVM            ModRM:reg (w)                VEX.vvvv (r)               ModRM:r/m (r)                     NA
       FVM            ModRM:reg (w)             EVEX.vvvv (r)                 ModRM:r/m (r)                     NA
        FV            ModRM:reg (w)             EVEX.vvvv (r)                 ModRM:r/m (r)                     NA





Description
Shifts the bits in the individual data elements (word/doublewords/quadword) in the first source operand (the
second operand) to the right by the number of bits specified in the count value of respective data elements in the
second source operand (the third operand). As the bits in the data elements are shifted right, the empty high-order
bits are set to the MSB (sign extension).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for words),
31 (for doublewords), or 63 (for a quadword), then the destination data element are filled with the corresponding
sign bit of the source element.
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 16 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding destination register are
zeroed.
EVEX.512/256/128 encoded VPSRAVD/W: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a
512/256/128-bit vector broadcasted from a 32/64-bit memory location. The destination is conditionally updated
with writemask k1.
EVEX.512/256/128 encoded VPSRAVQ: The destination and first source operands are ZMM/YMM/XMM registers.
The count operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination
is conditionally updated with writemask k1.

Operation
VPSRAVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN
             COUNT <- SRC2[i+3:i]
             IF COUNT < 16
                  THEN     DEST[i+15:i] <- SignExtend(SRC1[i+15:i] >> COUNT)
                  ELSE
                       FOR k<- 0 TO 15
                           DEST[i+k] <- SRC1[i+15]
                       ENDFOR;
             FI
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSRAVD (VEX.128 version)
COUNT_0 <- SRC2[31 : 0]
   (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <- SRC2[100 : 96];
DEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);
   (* Repeat shift operation for 2nd through 4th dwords *)
DEST[127:96] <- SignExtend(SRC1[127:96] >> COUNT_3);
DEST[MAX_VL-1:128] <- 0;

VPSRAVD (VEX.256 version)
COUNT_0 <- SRC2[31 : 0];
   (* Repeat Each COUNT_i for the 2nd through 8th dwords of SRC2*)
COUNT_7 <- SRC2[228 : 224];
DEST[31:0] <- SignExtend(SRC1[31:0] >> COUNT_0);
   (* Repeat shift operation for 2nd through 7th dwords *)
DEST[255:224] <- SignExtend(SRC1[255:224] >> COUNT_7);
DEST[MAX_VL-1:256] <- 0;

VPSRAVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         COUNT <- SRC2[4:0]
                         IF COUNT < 32
                              THEN     DEST[i+31:i] <- SignExtend(SRC1[i+31:i] >> COUNT)
                              ELSE
                                   FOR k<- 0 TO 31
                                       DEST[i+k] <- SRC1[i+31]
                                   ENDFOR;
                         FI
                    ELSE
                         COUNT <- SRC2[i+4:i]
                         IF COUNT < 32
                              THEN     DEST[i+31:i] <- SignExtend(SRC1[i+31:i] >> COUNT)
                              ELSE
                                   FOR k<- 0 TO 31
                                       DEST[i+k] <- SRC1[i+31]
                                   ENDFOR;
                         FI
               FI;
    ELSE
         IF *merging-masking*                   ; merging-masking
               THEN *DEST[31:0] remains unchanged*
               ELSE                             ; zeroing-masking
                    DEST[31:0] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSRAVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN
                         COUNT <- SRC2[5:0]
                         IF COUNT < 64
                              THEN      DEST[i+63:i] <- SignExtend(SRC1[i+63:i] >> COUNT)
                              ELSE
                                   FOR k<- 0 TO 63
                                        DEST[i+k] <- SRC1[i+63]
                                   ENDFOR;
                         FI
                    ELSE
                         COUNT <- SRC2[i+5:i]
                         IF COUNT < 64
                              THEN      DEST[i+63:i] <- SignExtend(SRC1[i+63:i] >> COUNT)
                              ELSE
                                   FOR k<- 0 TO 63
                                        DEST[i+k] <- SRC1[i+63]
                                   ENDFOR;
                         FI
               FI;
    ELSE
         IF *merging-masking*                    ; merging-masking
               THEN *DEST[63:0] remains unchanged*
               ELSE                              ; zeroing-masking
                    DEST[63:0] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





Intel C/C++ Compiler Intrinsic Equivalent
VPSRAVD __m512i _mm512_srav_epi32(__m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_mask_srav_epi32(__m512i s, __mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m512i _mm512_maskz_srav_epi32(__mmask16 m, __m512i a, __m512i cnt);
VPSRAVD __m256i _mm256_srav_epi32(__m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_mask_srav_epi32(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m256i _mm256_maskz_srav_epi32(__mmask8 m, __m256i a, __m256i cnt);
VPSRAVD __m128i _mm_srav_epi32(__m128i a, __m128i cnt);
VPSRAVD __m128i _mm_mask_srav_epi32(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m512i _mm512_srav_epi64(__m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_mask_srav_epi64(__m512i s, __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m512i _mm512_maskz_srav_epi64( __mmask8 m, __m512i a, __m512i cnt);
VPSRAVQ __m256i _mm256_srav_epi64(__m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_mask_srav_epi64(__m256i s, __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m256i _mm256_maskz_srav_epi64( __mmask8 m, __m256i a, __m256i cnt);
VPSRAVQ __m128i _mm_srav_epi64(__m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_mask_srav_epi64(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVQ __m128i _mm_maskz_srav_epi64( __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m512i _mm512_srav_epi16(__m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_mask_srav_epi16(__m512i s, __mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m512i _mm512_maskz_srav_epi16(__mmask32 m, __m512i a, __m512i cnt);
VPSRAVW __m256i _mm256_srav_epi16(__m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_mask_srav_epi16(__m256i s, __mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m256i _mm256_maskz_srav_epi16(__mmask16 m, __m256i a, __m256i cnt);
VPSRAVW __m128i _mm_srav_epi16(__m128i a, __m128i cnt);
VPSRAVW __m128i _mm_mask_srav_epi16(__m128i s, __mmask8 m, __m128i a, __m128i cnt);
VPSRAVW __m128i _mm_maskz_srav_epi32(__mmask8 m, __m128i a, __m128i cnt);
VPSRAVD __m256i _mm256_srav_epi32 (__m256i m, __m256i count)

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: VPSRLVW
description:
VPSRLVW/VPSRLVD/VPSRLVQ-Variable Bit Shift Right Logical
 Opcode/                                   Op /    64/32         CPUID      Description
 Instruction                               En      bit Mode      Feature
                                                   Support       Flag
 VEX.NDS.128.66.0F38.W0 45 /r              RVM     V/V           AVX2       Shift doublewords in xmm2 right by amount specified
 VPSRLVD xmm1, xmm2, xmm3/m128                                              in the corresponding element of xmm3/m128 while
                                                                            shifting in 0s.
 VEX.NDS.128.66.0F38.W1 45 /r              RVM     V/V           AVX2       Shift quadwords in xmm2 right by amount specified in
 VPSRLVQ xmm1, xmm2, xmm3/m128                                              the corresponding element of xmm3/m128 while
                                                                            shifting in 0s.
 VEX.NDS.256.66.0F38.W0 45 /r              RVM     V/V           AVX2       Shift doublewords in ymm2 right by amount specified
 VPSRLVD ymm1, ymm2, ymm3/m256                                              in the corresponding element of ymm3/m256 while
                                                                            shifting in 0s.
 VEX.NDS.256.66.0F38.W1 45 /r              RVM     V/V           AVX2       Shift quadwords in ymm2 right by amount specified in
 VPSRLVQ ymm1, ymm2, ymm3/m256                                              the corresponding element of ymm3/m256 while
                                                                            shifting in 0s.
 EVEX.NDS.128.66.0F38.W1 10 /r             FVM     V/V           AVX512VL   Shift words in xmm2 right by amount specified in the
 VPSRLVW xmm1 {k1}{z}, xmm2,                                     AVX512BW   corresponding element of xmm3/m128 while shifting
 xmm3/m128                                                                  in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W1 10 /r             FVM     V/V           AVX512VL   Shift words in ymm2 right by amount specified in the
 VPSRLVW ymm1 {k1}{z}, ymm2,                                     AVX512BW   corresponding element of ymm3/m256 while shifting
 ymm3/m256                                                                  in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W1 10 /r             FVM     V/V           AVX512BW   Shift words in zmm2 right by amount specified in the
 VPSRLVW zmm1 {k1}{z}, zmm2,                                                corresponding element of zmm3/m512 while shifting
 zmm3/m512                                                                  in 0s using writemask k1.
 EVEX.NDS.128.66.0F38.W0 45 /r             FV      V/V           AVX512VL   Shift doublewords in xmm2 right by amount specified
 VPSRLVD xmm1 {k1}{z}, xmm2,                                     AVX512F    in the corresponding element of xmm3/m128/m32bcst
 xmm3/m128/m32bcst                                                          while shifting in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W0 45 /r             FV      V/V           AVX512VL   Shift doublewords in ymm2 right by amount specified
 VPSRLVD ymm1 {k1}{z}, ymm2,                                     AVX512F    in the corresponding element of ymm3/m256/m32bcst
 ymm3/m256/m32bcst                                                          while shifting in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W0 45 /r             FV      V/V           AVX512F    Shift doublewords in zmm2 right by amount specified
 VPSRLVD zmm1 {k1}{z}, zmm2,                                                in the corresponding element of zmm3/m512/m32bcst
 zmm3/m512/m32bcst                                                          while shifting in 0s using writemask k1.
 EVEX.NDS.128.66.0F38.W1 45 /r             FV      V/V           AVX512VL   Shift quadwords in xmm2 right by amount specified in
 VPSRLVQ xmm1 {k1}{z}, xmm2,                                     AVX512F    the corresponding element of xmm3/m128/m64bcst
 xmm3/m128/m64bcst                                                          while shifting in 0s using writemask k1.
 EVEX.NDS.256.66.0F38.W1 45 /r             FV      V/V           AVX512VL   Shift quadwords in ymm2 right by amount specified in
 VPSRLVQ ymm1 {k1}{z}, ymm2,                                     AVX512F    the corresponding element of ymm3/m256/m64bcst
 ymm3/m256/m64bcst                                                          while shifting in 0s using writemask k1.
 EVEX.NDS.512.66.0F38.W1 45 /r             FV      V/V           AVX512F    Shift quadwords in zmm2 right by amount specified in
 VPSRLVQ zmm1 {k1}{z}, zmm2,                                                the corresponding element of zmm3/m512/m64bcst
 zmm3/m512/m64bcst                                                          while shifting in 0s using writemask k1.



                                                  Instruction Operand Encoding
       Op/En                 Operand 1                     Operand 2               Operand 3                  Operand 4
        RVM               ModRM:reg (w)                    VEX.vvvv (r)          ModRM:r/m (r)                    NA
        FVM               ModRM:reg (w)                  EVEX.vvvv (r)           ModRM:r/m (r)                    NA
         FV               ModRM:reg (w)                  EVEX.vvvv (r)           ModRM:r/m (r)                    NA





Description
Shifts the bits in the individual data elements (words, doublewords or quadword) in the first source operand to the
right by the count value of respective data elements in the second source operand. As the bits in the data elements
are shifted right, the empty high-order bits are cleared (set to 0).
The count values are specified individually in each data element of the second source operand. If the unsigned
integer value specified in the respective data element of the second source operand is greater than 15 (for word),
31 (for doublewords), or 63 (for a quadword), then the destination data element are written with 0.
VEX.128 encoded version: The destination and first source operands are XMM registers. The count operand can be
either an XMM register or a 128-bit memory location. Bits (MAX_VL-1:128) of the corresponding destination
register are zeroed.
VEX.256 encoded version: The destination and first source operands are YMM registers. The count operand can be
either an YMM register or a 256-bit memory. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded VPSRLVD/Q: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512-bit vector broad-
casted from a 32/64-bit memory location. The destination is conditionally updated with writemask k1.
EVEX encoded VPSRLVW: The destination and first source operands are ZMM/YMM/XMM registers. The count
operand can be either a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is condition-
ally updated with writemask k1.

Operation
VPSRLVW (EVEX encoded version)
(KL, VL) = (8, 128), (16, 256), (32, 512)

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- ZeroExtend(SRC1[i+15:i] >> SRC2[i+15:i])
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE                           ; zeroing-masking
                       DEST[i+15:i] <- 0
             FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSRLVD (VEX.128 version)
COUNT_0 <-SRC2[31 : 0]
    (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <-SRC2[127 : 96];
IF COUNT_0 < 32 THEN
    DEST[31:0] <-ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
    DEST[31:0] <-0;
    (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 32 THEN
    DEST[127:96] <-ZeroExtend(SRC1[127:96] >> COUNT_3);
ELSE
    DEST[127:96] <-0;
DEST[MAX_VL-1:128] <-0;

VPSRLVD (VEX.256 version)
COUNT_0 <-SRC2[31 : 0];
    (* Repeat Each COUNT_i for the 2nd through 7th dwords of SRC2*)
COUNT_7 <-SRC2[255 : 224];
IF COUNT_0 < 32 THEN
DEST[31:0] <-ZeroExtend(SRC1[31:0] >> COUNT_0);
ELSE
DEST[31:0] <-0;
    (* Repeat shift operation for 2nd through 7th dwords *)
IF COUNT_7 < 32 THEN
    DEST[255:224] <-ZeroExtend(SRC1[255:224] >> COUNT_7);
ELSE
    DEST[255:224] <-0;
DEST[MAX_VL-1:256] <-0;

VPSRLVD (EVEX encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] >> SRC2[31:0])
                    ELSE DEST[i+31:i] <- ZeroExtend(SRC1[i+31:i] >> SRC2[i+31:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





VPSRLVQ (VEX.128 version)
COUNT_0 <-SRC2[63 : 0];
COUNT_1 <-SRC2[127 : 64];
IF COUNT_0 < 64 THEN
    DEST[63:0] <-ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
    DEST[63:0] <-0;
IF COUNT_1 < 64 THEN
    DEST[127:64] <-ZeroExtend(SRC1[127:64] >> COUNT_1);
ELSE
    DEST[127:64] <-0;
DEST[MAX_VL-1:128] <-0;

VPSRLVQ (VEX.256 version)
COUNT_0 <-SRC2[63 : 0];
    (* Repeat Each COUNT_i for the 2nd through 4th dwords of SRC2*)
COUNT_3 <-SRC2[255 : 192];
IF COUNT_0 < 64 THEN
DEST[63:0] <-ZeroExtend(SRC1[63:0] >> COUNT_0);
ELSE
DEST[63:0] <-0;
    (* Repeat shift operation for 2nd through 4th dwords *)
IF COUNT_3 < 64 THEN
    DEST[255:192] <-ZeroExtend(SRC1[255:192] >> COUNT_3);
ELSE
    DEST[255:192] <-0;
DEST[MAX_VL-1:256] <-0;

VPSRLVQ (EVEX encoded version)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] >> SRC2[63:0])
                    ELSE DEST[i+63:i] <- ZeroExtend(SRC1[i+63:i] >> SRC2[i+63:i])
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;





Intel C/C++ Compiler Intrinsic Equivalent
VPSRLVW __m512i _mm512_srlv_epi16(__m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_mask_srlv_epi16(__m512i s, __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m512i _mm512_maskz_srlv_epi16( __mmask32 k, __m512i a, __m512i cnt);
VPSRLVW __m256i _mm256_mask_srlv_epi16(__m256i s, __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m256i _mm256_maskz_srlv_epi16( __mmask16 k, __m256i a, __m256i cnt);
VPSRLVW __m128i _mm_mask_srlv_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m128i _mm_maskz_srlv_epi16( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVW __m256i _mm256_srlv_epi32 (__m256i m, __m256i count)
VPSRLVD __m512i _mm512_srlv_epi32(__m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_mask_srlv_epi32(__m512i s, __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m512i _mm512_maskz_srlv_epi32( __mmask16 k, __m512i a, __m512i cnt);
VPSRLVD __m256i _mm256_mask_srlv_epi32(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m256i _mm256_maskz_srlv_epi32( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVD __m128i _mm_mask_srlv_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVD __m128i _mm_maskz_srlv_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m512i _mm512_srlv_epi64(__m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_mask_srlv_epi64(__m512i s, __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m512i _mm512_maskz_srlv_epi64( __mmask8 k, __m512i a, __m512i cnt);
VPSRLVQ __m256i _mm256_mask_srlv_epi64(__m256i s, __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m256i _mm256_maskz_srlv_epi64( __mmask8 k, __m256i a, __m256i cnt);
VPSRLVQ __m128i _mm_mask_srlv_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_maskz_srlv_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLVQ __m256i _mm256_srlv_epi64 (__m256i m, __m256i count)
VPSRLVD __m128i _mm_srlv_epi32( __m128i a, __m128i cnt);
VPSRLVQ __m128i _mm_srlv_epi64( __m128i a, __m128i cnt);

SIMD Floating-Point Exceptions
None

Other Exceptions
VEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded VPSRLVD/Q, see Exceptions Type E4.
EVEX-encoded VPSRLVW, see Exceptions Type E4.nb.






platform: x86_64
mnem: VPTERNLOGD
description:
VPTERNLOGD/VPTERNLOGQ-Bitwise Ternary Logic
 Opcode/                                 Op /   64/32       CPUID      Description
 Instruction                             En     bit Mode    Feature
                                                Support     Flag
 EVEX.DDS.128.66.0F3A.W0 25 /r ib        FV     V/V         AVX512VL   Bitwise ternary logic taking xmm1, xmm2 and
 VPTERNLOGD xmm1 {k1}{z}, xmm2,                             AVX512F    xmm3/m128/m32bcst as source operands and writing
 xmm3/m128/m32bcst, imm8                                               the result to xmm1 under writemask k1 with dword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.
 EVEX.DDS.256.66.0F3A.W0 25 /r ib        FV     V/V         AVX512VL   Bitwise ternary logic taking ymm1, ymm2 and
 VPTERNLOGD ymm1 {k1}{z}, ymm2,                             AVX512F    ymm3/m256/m32bcst as source operands and writing
 ymm3/m256/m32bcst, imm8                                               the result to ymm1 under writemask k1 with dword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.
 EVEX.DDS.512.66.0F3A.W0 25 /r ib        FV     V/V         AVX512F    Bitwise ternary logic taking zmm1, zmm2 and
 VPTERNLOGD zmm1 {k1}{z}, zmm2,                                        zmm3/m512/m32bcst as source operands and writing
 zmm3/m512/m32bcst, imm8                                               the result to zmm1 under writemask k1 with dword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.
 EVEX.DDS.128.66.0F3A.W1 25 /r ib        FV     V/V         AVX512VL   Bitwise ternary logic taking xmm1, xmm2 and
 VPTERNLOGQ xmm1 {k1}{z}, xmm2,                             AVX512F    xmm3/m128/m64bcst as source operands and writing
 xmm3/m128/m64bcst, imm8                                               the result to xmm1 under writemask k1 with qword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.
 EVEX.DDS.256.66.0F3A.W1 25 /r ib        FV     V/V         AVX512VL   Bitwise ternary logic taking ymm1, ymm2 and
 VPTERNLOGQ ymm1 {k1}{z}, ymm2,                             AVX512F    ymm3/m256/m64bcst as source operands and writing
 ymm3/m256/m64bcst, imm8                                               the result to ymm1 under writemask k1 with qword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.
 EVEX.DDS.512.66.0F3A.W1 25 /r ib        FV     V/V         AVX512F    Bitwise ternary logic taking zmm1, zmm2 and
 VPTERNLOGQ zmm1 {k1}{z}, zmm2,                                        zmm3/m512/m64bcst as source operands and writing
 zmm3/m512/m64bcst, imm8                                               the result to zmm1 under writemask k1 with qword
                                                                       granularity. The immediate value determines the specific
                                                                       binary function being implemented.



                                                Instruction Operand Encoding
       Op/En             Operand 1                     Operand 2                Operand 3                    Operand 4
        FV            ModRM:reg (r, w)                EVEX.vvvv (r)            ModRM:r/m (r)                   Imm8

Description
VPTERNLOGD/Q takes three bit vectors of 512-bit length (in the first, second and third operand) as input data to
form a set of 512 indices, each index is comprised of one bit from each input vector. The imm8 byte specifies a
boolean logic table producing a binary value for each 3-bit index value. The final 512-bit boolean result is written
to the destination operand (the first operand) using the writemask k1 with the granularity of doubleword element
or quadword element into the destination.
The destination operand is a ZMM (EVEX.512)/YMM (EVEX.256)/XMM (EVEX.128) register. The first source operand
is a ZMM/YMM/XMM register. The second source operand can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location The destination
operand is a ZMM register conditionally updated with writemask k1.





Table 5-11 shows two examples of Boolean functions specified by immediate values 0xE2 and 0xE4, with the look
up result listed in the fourth column following the three columns containing all possible values of the 3-bit index.

               Table 5-11. Examples of VPTERNLOGD/Q Imm8 Boolean Function and Input Index Values
  VPTERNLOGD reg1, reg2, src3, 0xE2                Bit Result with   VPTERNLOGD reg1, reg2, src3, 0xE4              Bit Result with
                                                   Imm8=0xE2                                                        Imm8=0xE4
  Bit(reg1)       Bit(reg2)        Bit(src3)                         Bit(reg1)        Bit(reg2)       Bit(src3)
  0               0                0               0                 0                0               0             0
  0               0                1               1                 0                0               1             0
  0               1                0               0                 0                1               0             1
  0               1                1               0                 0                1               1             0
  1               0                0               0                 1                0               0             0
  1               0                1               1                 1                0               1             1
  1               1                0               1                 1                1               0             1
  1               1                1               1                 1                1               1             1

Specifying different values in imm8 will allow any arbitrary three-input Boolean functions to be implemented in
software using VPTERNLOGD/Q. Table 5-1 and Table 5-2 provide a mapping of all 256 possible imm8 values to
various Boolean expressions.

Operation
VPTERNLOGD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               FOR k <- 0 TO 31
                   IF (EVEX.b = 1) AND (SRC2 *is memory*)
                         THEN DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
                         ELSE DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
                   FI;
                             ; table lookup of immediate bellow;
    ELSE
         IF *merging-masking*                    ; merging-masking
               THEN *DEST[31+i:i] remains unchanged*
               ELSE                              ; zeroing-masking
                   DEST[31+i:i] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





VPTERNLOGQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               FOR k <- 0 TO 63
                    IF (EVEX.b = 1) AND (SRC2 *is memory*)
                         THEN DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ k ]]
                         ELSE DEST[j][k] <- imm[(DEST[i+k] << 2) + (SRC1[ i+k ] << 1) + SRC2[ i+k ]]
                    FI;                 ; table lookup of immediate bellow;
         ELSE
               IF *merging-masking*                    ; merging-masking
                    THEN *DEST[63+i:i] remains unchanged*
                    ELSE                               ; zeroing-masking
                         DEST[63+i:i] <- 0
               FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPTERNLOGD __m512i _mm512_ternarylogic_epi32(__m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_mask_ternarylogic_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m512i _mm512_maskz_ternarylogic_epi32(__mmask m, __m512i a, __m512i b, int imm);
VPTERNLOGD __m256i _mm256_ternarylogic_epi32(__m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_mask_ternarylogic_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m256i _mm256_maskz_ternarylogic_epi32( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGD __m128i _mm_ternarylogic_epi32(__m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_mask_ternarylogic_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGD __m128i _mm_maskz_ternarylogic_epi32( __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m512i _mm512_ternarylogic_epi64(__m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_mask_ternarylogic_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m512i _mm512_maskz_ternarylogic_epi64( __mmask8 m, __m512i a, __m512i b, int imm);
VPTERNLOGQ __m256i _mm256_ternarylogic_epi64(__m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_mask_ternarylogic_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m256i _mm256_maskz_ternarylogic_epi64( __mmask8 m, __m256i a, __m256i b, int imm);
VPTERNLOGQ __m128i _mm_ternarylogic_epi64(__m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_mask_ternarylogic_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b, int imm);
VPTERNLOGQ __m128i _mm_maskz_ternarylogic_epi64( __mmask8 m, __m128i a, __m128i b, int imm);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VPTESTMB
description:
VPTESTMB/VPTESTMW/VPTESTMD/VPTESTMQ-Logical AND and Set Mask
 Opcode/                         Op/    64/32        CPUID         Description
 Instruction                     En     bit Mode     Feature
                                        Support      Flag
 EVEX.NDS.128.66.0F38.W0 26 /r   FVM    V/V          AVX512VL      Bitwise AND of packed byte integers in xmm2 and
 VPTESTMB k2 {k1}, xmm2,                             AVX512BW      xmm3/m128 and set mask k2 to reflect the zero/non-zero
 xmm3/m128                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.256.66.0F38.W0 26 /r   FVM    V/V          AVX512VL      Bitwise AND of packed byte integers in ymm2 and
 VPTESTMB k2 {k1}, ymm2,                             AVX512BW      ymm3/m256 and set mask k2 to reflect the zero/non-zero
 ymm3/m256                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.512.66.0F38.W0 26 /r   FVM    V/V          AVX512BW      Bitwise AND of packed byte integers in zmm2 and
 VPTESTMB k2 {k1}, zmm2,                                           zmm3/m512 and set mask k2 to reflect the zero/non-zero
 zmm3/m512                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.128.66.0F38.W1 26 /r   FVM    V/V          AVX512VL      Bitwise AND of packed word integers in xmm2 and
 VPTESTMW k2 {k1}, xmm2,                             AVX512BW      xmm3/m128 and set mask k2 to reflect the zero/non-zero
 xmm3/m128                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.256.66.0F38.W1 26 /r   FVM    V/V          AVX512VL      Bitwise AND of packed word integers in ymm2 and
 VPTESTMW k2 {k1}, ymm2,                             AVX512BW      ymm3/m256 and set mask k2 to reflect the zero/non-zero
 ymm3/m256                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.512.66.0F38.W1 26 /r   FVM    V/V          AVX512BW      Bitwise AND of packed word integers in zmm2 and
 VPTESTMW k2 {k1}, zmm2,                                           zmm3/m512 and set mask k2 to reflect the zero/non-zero
 zmm3/m512                                                         status of each element of the result, under writemask k1.
 EVEX.NDS.128.66.0F38.W0 27 /r   FV     V/V          AVX512VL      Bitwise AND of packed doubleword integers in xmm2 and
 VPTESTMD k2 {k1}, xmm2,                             AVX512F       xmm3/m128/m32bcst and set mask k2 to reflect the
 xmm3/m128/m32bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.
 EVEX.NDS.256.66.0F38.W0 27 /r   FV     V/V          AVX512VL      Bitwise AND of packed doubleword integers in ymm2 and
 VPTESTMD k2 {k1}, ymm2,                             AVX512F       ymm3/m256/m32bcst and set mask k2 to reflect the
 ymm3/m256/m32bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.
 EVEX.NDS.512.66.0F38.W0 27 /r   FV     V/V          AVX512F       Bitwise AND of packed doubleword integers in zmm2 and
 VPTESTMD k2 {k1}, zmm2,                                           zmm3/m512/m32bcst and set mask k2 to reflect the
 zmm3/m512/m32bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.
 EVEX.NDS.128.66.0F38.W1 27 /r   FV     V/V          AVX512VL      Bitwise AND of packed quadword integers in xmm2 and
 VPTESTMQ k2 {k1}, xmm2,                             AVX512F       xmm3/m128/m64bcst and set mask k2 to reflect the
 xmm3/m128/m64bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.
 EVEX.NDS.256.66.0F38.W1 27 /r   FV     V/V          AVX512VL      Bitwise AND of packed quadword integers in ymm2 and
 VPTESTMQ k2 {k1}, ymm2,                             AVX512F       ymm3/m256/m64bcst and set mask k2 to reflect the
 ymm3/m256/m64bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.
 EVEX.NDS.512.66.0F38.W1 27 /r   FV     V/V          AVX512F       Bitwise AND of packed quadword integers in zmm2 and
 VPTESTMQ k2 {k1}, zmm2,                                           zmm3/m512/m64bcst and set mask k2 to reflect the
 zmm3/m512/m64bcst                                                 zero/non-zero status of each element of the result, under
                                                                   writemask k1.



                                              Instruction Operand Encoding
     Op/En               Operand 1                  Operand 2                    Operand 3                 Operand 4
      FVM              ModRM:reg (w)               EVEX.vvvv (r)             ModRM:r/m (r)                     NA
       FV              ModRM:reg (w)               EVEX.vvvv (r)             ModRM:r/m (r)                     NA





Description
Performs a bitwise logical AND operation on the first source operand (the second operand) and second source
operand (the third operand) and stores the result in the destination operand (the first operand) under the
writemask. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and second
src operands is non-zero; otherwise it is set to 0.
VPTESTMD/VPTESTMQ: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a mask register updated under the writemask.
VPTESTMB/VPTESTMW: The first source operand is a ZMM/YMM/XMM register. The second source operand can be a
ZMM/YMM/XMM register or a 512/256/128-bit memory location. The destination operand is a mask register
updated under the writemask.

Operation
VPTESTMB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN      DEST[j] <- (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] != 0)? 1 : 0;
         ELSE      DEST[j] = 0                ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPTESTMW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN      DEST[j] <- (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] != 0)? 1 : 0;
         ELSE      DEST[j] = 0                ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPTESTMD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[31:0] != 0)? 1 : 0;
                    ELSE DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] != 0)? 1 : 0;
               FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0





VPTESTMQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;
                    ELSE DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;
               FI;
         ELSE       DEST[j] <- 0                ; zeroing-masking only
    FI;
ENDFOR
DEST[MAX_KL-1:KL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPTESTMB __mmask64 _mm512_test_epi8_mask( __m512i a, __m512i b);
VPTESTMB __mmask64 _mm512_mask_test_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_test_epi16_mask( __m512i a, __m512i b);
VPTESTMW __mmask32 _mm512_mask_test_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_test_epi32_mask( __m512i a, __m512i b);
VPTESTMD __mmask16 _mm512_mask_test_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_test_epi64_mask(__m512i a, __m512i b);
VPTESTMQ __mmask8 _mm512_mask_test_epi64_mask(__mmask8, __m512i a, __m512i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
VPTESTMD/Q: See Exceptions Type E4.
VPTESTMB/W: See Exceptions Type E4.nb.






platform: x86_64
mnem: VPTESTNMB
description:
VPTESTNMB/VPTESTNMW/VPTESTNMD/VPTESTNMQ-Logical NAND and Set
 Opcode/                         Op/   64/32      CPUID      Description
 Instruction                     En    bit Mode
                                       Support
 EVEX.NDS.128.F3.0F38.W0 26 /r   FVM   V/V        AVX512VL   Bitwise NAND of packed byte integers in xmm2 and
 VPTESTNMB k2 {k1}, xmm2,                         AVX512BW   xmm3/m128 and set mask k2 to reflect the zero/non-zero
 xmm3/m128                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.256.F3.0F38.W0 26 /r   FVM   V/V        AVX512VL   Bitwise NAND of packed byte integers in ymm2 and
 VPTESTNMB k2 {k1}, ymm2,                         AVX512BW   ymm3/m256 and set mask k2 to reflect the zero/non-zero
 ymm3/m256                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.512.F3.0F38.W0 26 /r   FVM   V/V        AVX512F    Bitwise NAND of packed byte integers in zmm2 and
 VPTESTNMB k2 {k1}, zmm2,                         AVX512BW   zmm3/m512 and set mask k2 to reflect the zero/non-zero
 zmm3/m512                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.128.F3.0F38.W1 26 /r   FVM   V/V        AVX512VL   Bitwise NAND of packed word integers in xmm2 and
 VPTESTNMW k2 {k1}, xmm2,                         AVX512BW   xmm3/m128 and set mask k2 to reflect the zero/non-zero
 xmm3/m128                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.256.F3.0F38.W1 26 /r   FVM   V/V        AVX512VL   Bitwise NAND of packed word integers in ymm2 and
 VPTESTNMW k2 {k1}, ymm2,                         AVX512BW   ymm3/m256 and set mask k2 to reflect the zero/non-zero
 ymm3/m256                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.512.F3.0F38.W1 26 /r   FVM   V/V        AVX512F    Bitwise NAND of packed word integers in zmm2 and
 VPTESTNMW k2 {k1}, zmm2,                         AVX512BW   zmm3/m512 and set mask k2 to reflect the zero/non-zero
 zmm3/m512                                                   status of each element of the result, under writemask k1.

 EVEX.NDS.128.F3.0F38.W0 27 /r   FV    V/V        AVX512VL   Bitwise NAND of packed doubleword integers in xmm2 and
 VPTESTNMD k2 {k1}, xmm2,                         AVX512F    xmm3/m128/m32bcst and set mask k2 to reflect the
 xmm3/m128/m32bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.
 EVEX.NDS.256.F3.0F38.W0 27 /r   FV    V/V        AVX512VL   Bitwise NAND of packed doubleword integers in ymm2 and
 VPTESTNMD k2 {k1}, ymm2,                         AVX512F    ymm3/m256/m32bcst and set mask k2 to reflect the
 ymm3/m256/m32bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.
 EVEX.NDS.512.F3.0F38.W0 27 /r   FV    V/V        AVX512F    Bitwise NAND of packed doubleword integers in zmm2 and
 VPTESTNMD k2 {k1}, zmm2,                                    zmm3/m512/m32bcst and set mask k2 to reflect the
 zmm3/m512/m32bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.
 EVEX.NDS.128.F3.0F38.W1 27 /r   FV    V/V        AVX512VL   Bitwise NAND of packed quadword integers in xmm2 and
 VPTESTNMQ k2 {k1}, xmm2,                         AVX512F    xmm3/m128/m64bcst and set mask k2 to reflect the
 xmm3/m128/m64bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.
 EVEX.NDS.256.F3.0F38.W1 27 /r   FV    V/V        AVX512VL   Bitwise NAND of packed quadword integers in ymm2 and
 VPTESTNMQ k2 {k1}, ymm2,                         AVX512F    ymm3/m256/m64bcst and set mask k2 to reflect the
 ymm3/m256/m64bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.
 EVEX.NDS.512.F3.0F38.W1 27 /r   FV    V/V        AVX512F    Bitwise NAND of packed quadword integers in zmm2 and
 VPTESTNMQ k2 {k1}, zmm2,                                    zmm3/m512/m64bcst and set mask k2 to reflect the
 zmm3/m512/m64bcst                                           zero/non-zero status of each element of the result, under
                                                             writemask k1.





                                                  Instruction Operand Encoding
     Op/En               Operand 1                     Operand 2                Operand 3                  Operand 4
     FVM               ModRM:reg (w)                 EVEX.vvvv (r)             ModRM:r/m (r)                   NA
      FV               ModRM:reg (w)                 EVEX.vvvv (r)             ModRM:r/m (r)                   NA

Description
Performs a bitwise logical NAND operation on the byte/word/doubleword/quadword element of the first source
operand (the second operand) with the corresponding element of the second source operand (the third operand)
and stores the logical comparison result into each bit of the destination operand (the first operand) according to the
writemask k1. Each bit of the result is set to 1 if the bitwise AND of the corresponding elements of the first and
second src operands is zero; otherwise it is set to 0.
EVEX encoded VPTESTNMD/Q: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location, or a 512/256/128-bit vector broadcasted
from a 32/64-bit memory location. The destination is updated according to the writemask.
EVEX encoded VPTESTNMB/W: The first source operand is a ZMM/YMM/XMM registers. The second source operand
can be a ZMM/YMM/XMM register, a 512/256/128-bit memory location. The destination is updated according to the
writemask.

Operation
VPTESTNMB
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i <- j*8
    IF MaskBit(j) OR *no writemask*
         THEN
              DEST[j] <- (SRC1[i+7:i] BITWISE AND SRC2[i+7:i] == 0)? 1 : 0
         ELSE DEST[j] <- 0; zeroing masking only
    FI
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPTESTNMW
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j*16
    IF MaskBit(j) OR *no writemask*
         THEN
               DEST[j] <- (SRC1[i+15:i] BITWISE AND SRC2[i+15:i] == 0)? 1 : 0
         ELSE DEST[j] <- 0; zeroing masking only
    FI
ENDFOR
DEST[MAX_KL-1:KL] <- 0





VPTESTNMD
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j*32
    IF MaskBit(j) OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- (SRC1[i+31:i] BITWISE AND SRC2[31:0] == 0)? 1 : 0
                    ELSE DEST[j] <- (SRC1[i+31:i] BITWISE AND SRC2[i+31:i] == 0)? 1 : 0
               FI
         ELSE DEST[j] <- 0; zeroing masking only
    FI
ENDFOR
DEST[MAX_KL-1:KL] <- 0

VPTESTNMQ
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j*64
    IF MaskBit(j) OR *no writemask*
         THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[63:0] != 0)? 1 : 0;
                    ELSE DEST[j] <- (SRC1[i+63:i] BITWISE AND SRC2[i+63:i] != 0)? 1 : 0;
               FI;
         ELSE DEST[j] <- 0; zeroing masking only
    FI
ENDFOR
DEST[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VPTESTNMB __mmask64 _mm512_testn_epi8_mask( __m512i a, __m512i b);
VPTESTNMB __mmask64 _mm512_mask_testn_epi8_mask(__mmask64, __m512i a, __m512i b);
VPTESTNMB __mmask32 _mm256_testn_epi8_mask(__m256i a, __m256i b);
VPTESTNMB __mmask32 _mm256_mask_testn_epi8_mask(__mmask32, __m256i a, __m256i b);
VPTESTNMB __mmask16 _mm_testn_epi8_mask(__m128i a, __m128i b);
VPTESTNMB __mmask16 _mm_mask_testn_epi8_mask(__mmask16, __m128i a, __m128i b);
VPTESTNMW __mmask32 _mm512_testn_epi16_mask( __m512i a, __m512i b);
VPTESTNMW __mmask32 _mm512_mask_testn_epi16_mask(__mmask32, __m512i a, __m512i b);
VPTESTNMW __mmask16 _mm256_testn_epi16_mask(__m256i a, __m256i b);
VPTESTNMW __mmask16 _mm256_mask_testn_epi16_mask(__mmask16, __m256i a, __m256i b);
VPTESTNMW __mmask8 _mm_testn_epi16_mask(__m128i a, __m128i b);
VPTESTNMW __mmask8 _mm_mask_testn_epi16_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMD __mmask16 _mm512_testn_epi32_mask( __m512i a, __m512i b);
VPTESTNMD __mmask16 _mm512_mask_testn_epi32_mask(__mmask16, __m512i a, __m512i b);
VPTESTNMD __mmask8 _mm256_testn_epi32_mask(__m256i a, __m256i b);
VPTESTNMD __mmask8 _mm256_mask_testn_epi32_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMD __mmask8 _mm_testn_epi32_mask(__m128i a, __m128i b);
VPTESTNMD __mmask8 _mm_mask_testn_epi32_mask(__mmask8, __m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm512_testn_epi64_mask(__m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm512_mask_testn_epi64_mask(__mmask8, __m512i a, __m512i b);
VPTESTNMQ __mmask8 _mm256_testn_epi64_mask(__m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm256_mask_testn_epi64_mask(__mmask8, __m256i a, __m256i b);
VPTESTNMQ __mmask8 _mm_testn_epi64_mask(__m128i a, __m128i b);
VPTESTNMQ __mmask8 _mm_mask_testn_epi64_mask(__mmask8, __m128i a, __m128i b);

SIMD Floating-Point Exceptions
None

Other Exceptions
VPTESTNMD/VPTESTNMQ: See Exceptions Type E4.
VPTESTNMB/VPTESTNMW: See Exceptions Type E4.nb.






platform: x86_64
mnem: VRANGEPD
description:
VRANGEPD-Range Restriction Calculation For Packed Pairs of Float64 Values
    Opcode/                             Op /        64/32                CPUID             Description
    Instruction                         En          bit Mode             Feature
                                                    Support              Flag
    EVEX.NDS.128.66.0F3A.W1 50 /r ib    FV          V/V                  AVX512VL          Calculate two RANGE operation output value from 2 pairs
    VRANGEPD xmm1 {k1}{z}, xmm2,                                         AVX512DQ          of double-precision floating-point values in xmm2 and
    xmm3/m128/m64bcst, imm8                                                                xmm3/m128/m32bcst, store the results to xmm1 under
                                                                                           the writemask k1. Imm8 specifies the comparison and sign
                                                                                           of the range operation.
    EVEX.NDS.256.66.0F3A.W1 50 /r ib    FV          V/V                  AVX512VL          Calculate four RANGE operation output value from 4pairs
    VRANGEPD ymm1 {k1}{z}, ymm2,                                         AVX512DQ          of double-precision floating-point values in ymm2 and
    ymm3/m256/m64bcst, imm8                                                                ymm3/m256/m32bcst, store the results to ymm1 under
                                                                                           the writemask k1. Imm8 specifies the comparison and sign
                                                                                           of the range operation.
    EVEX.NDS.512.66.0F3A.W1 50 /r ib    FV          V/V                  AVX512DQ          Calculate eight RANGE operation output value from 8
    VRANGEPD zmm1 {k1}{z}, zmm2,                                                           pairs of double-precision floating-point values in zmm2
    zmm3/m512/m64bcst{sae}, imm8                                                           and zmm3/m512/m32bcst, store the results to zmm1
                                                                                           under the writemask k1. Imm8 specifies the comparison
                                                                                           and sign of the range operation.



                                                        Instruction Operand Encoding
           Op/En               Operand 1                                  Operand 2                               Operand 3                          Operand 4
            FV               ModRM:reg (w)                               EVEX.vvvv (r)                          ModRM:r/m (r)                            Imm8

Description
This instruction calculates 2/4/8 range operation outputs from two sets of packed input double-precision FP values
in the first source operand (the second operand) and the second source operand (the third operand). The range
outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
.     Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
      absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
      combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
.     Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
      value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.



                       7          6                 5                4              3                       2         1                 0

           imm8                    Must Be Zero                                         Sign Control (SC)            Compare Operation Select



                                                                                                                Imm8[1:0] = 00b : Select Min value
                                   Imm8[3:2] = 00b : Select sign(SRC1)                                          Imm8[1:0] = 01b : Select Max value
                                   Imm8[3:2] = 01b : Select sign(Compare_Result)                                Imm8[1:0] = 10b : Select Min-Abs value
                                   Imm8[3:2] = 10b : Set sign to 0                                              Imm8[1:0] = 11b : Select Max-Abs value
                                   Imm8[3:2] = 11b : Set sign to 1


                                   Figure 5-27. Imm8 Controls for VRANGEPD/SD/PS/SS





When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control
(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-12.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-
tude-0, opposite-signed input cases are listed in Table 5-13.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-14.

      Table 5-12. Signaling of Comparison Operation of One or More NaN Input Values and Effect of Imm8[3:2]
  Src1            Src2           Result                  IE Signaling Due to Comparison          Imm8[3:2] Effect to Range Output
  sNaN1           sNaN2          Quiet(sNaN1)            Yes                                     Ignored
  sNaN1           qNaN2          Quiet(sNaN1)            Yes                                     Ignored
  sNaN1           Norm2          Quiet(sNaN1)            Yes                                     Ignored
  qNaN1           sNaN2          Quiet(sNaN2)            Yes                                     Ignored
  qNaN1           qNaN2          qNaN1                   No                                      Applicable
  qNaN1           Norm2          Norm2                   No                                      Applicable
  Norm1           sNaN2          Quiet(sNaN2)            Yes                                     Ignored
  Norm1           qNaN2          Norm1                   No                                      Applicable



         Table 5-13. Comparison Result for Opposite-Signed Zero Cases for MIN, MIN_ABS and MAX, MAX_ABS
                           MIN and MIN_ABS                                                     MAX and MAX_ABS
 Src1                 Src2                  Result                      Src1              Src2                 Result
 +0                   -0                    -0                          +0                -0                   +0
 -0                   +0                    -0                          -0                +0                   +0



  Table 5-14. Comparison Result of Equal-Magnitude Input Cases for MIN_ABS and MAX_ABS, (|a| = |b|, a>0, b<0)
                    MIN_ABS (|a| = |b|, a>0, b<0)                                    MAX_ABS (|a| = |b|, a>0, b<0)
 Src1                 Src2                  Result                      Src1              Src2                 Result
 a                    b                     b                           a                 b                    a
 b                    a                     b                           b                 a                    a





Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
   // Check if SNAN and report IE, see also Table 5-12
   IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
   IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);

    Src1.exp <- SRC1[62:52];
    Src1.fraction <- SRC1[51:0];
    IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
          IF DAZ THEN Src1.fraction <- 0;
          ELSE IF (SRC2 <> QNAN) Set DE; FI;
    FI;

    Src2.exp <- SRC2[62:52];
    Src2.fraction <- SRC2[51:0];
    IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
          IF DAZ THEN Src2.fraction <- 0;
          ELSE IF (SRC1 <> QNAN) Set DE; FI;
    FI;

    IF (SRC2 = QNAN) THEN{TMP[63:0] <- SRC1[63:0]}
    ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] <- SRC2[63:0]}
    ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] <- from Table 5-13
    ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] <- from Table 5-14
    ELSE
        Case(CmpOpCtl[1:0])
        00: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
        01: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
        10: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
        11: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
        ESAC;
    FI;

    Case(SignSelCtl[1:0])
    00: dest <- (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
    01: dest <- TMP[63:0];// Preserve sign of compare result
    10: dest <- (0 << 63) OR (TMP[62:0]);// Zero out sign bit
    11: dest <- (1 << 63) OR (TMP[62:0]);// Set the sign bit
    ESAC;
    RETURN dest[63:0];
}

CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];





VRANGEPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- RangeDP (SRC1[i+63:i], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
                    ELSE DEST[i+63:i] <- RangeDP (SRC1[i+63:i], SRC2[i+63:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+63:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+63:i] = 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

The following example describes a common usage of this instruction for checking that the input operand is
bounded between +-1023.

VRANGEPD zmm_dst, zmm_src, zmm_1023, 02h;

Where:
          zmm_dst is the destination operand.
          zmm_src is the input operand to compare against +-1023 (this is SRC1).
          zmm_1023 is the reference operand, contains the value of 1023 (and this is SRC2).
          IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of SRC1.sign.

In case |zmm_src| < 1023 (i.e. SRC1 is smaller than 1023 in magnitude), then its value will be written into
zmm_dst. Otherwise, the value stored in zmm_dst will get the value of 1023 (received on zmm_1023, which is
SRC2).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| >= 1023, the selected sign of SRC1 is kept.
Thus, if zmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023 while if zmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.





Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPD __m512d _mm512_range_pd ( __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_range_round_pd ( __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_mask_range_pd (__m512 ds, __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_mask_range_round_pd (__m512d s, __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m512d _mm512_maskz_range_pd ( __mmask8 k, __m512d a, __m512d b, int imm);
VRANGEPD __m512d _mm512_maskz_range_round_pd ( __mmask8 k, __m512d a, __m512d b, int imm, int sae);
VRANGEPD __m256d _mm256_range_pd ( __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_mask_range_pd (__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m256d _mm256_maskz_range_pd ( __mmask8 k, __m256d a, __m256d b, int imm);
VRANGEPD __m128d _mm_range_pd ( __m128 a, __m128d b, int imm);
VRANGEPD __m128d _mm_mask_range_pd (__m128 s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGEPD __m128d _mm_maskz_range_pd ( __mmask8 k, __m128d a, __m128d b, int imm);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VRANGEPS
description:
 VRANGEPS-Range Restriction Calculation For Packed Pairs of Float32 Values
    Opcode/                               Op /    64/32         CPUID          Description
    Instruction                           En      bit Mode      Feature
                                                  Support       Flag
    EVEX.NDS.128.66.0F3A.W0 50 /r ib      FV      V/V           AVX512VL       Calculate four RANGE operation output value from 4 pairs
    VRANGEPS xmm1 {k1}{z}, xmm2,                                AVX512DQ       of single-precision floating-point values in xmm2 and
    xmm3/m128/m32bcst, imm8                                                    xmm3/m128/m32bcst, store the results to xmm1 under
                                                                               the writemask k1. Imm8 specifies the comparison and sign
                                                                               of the range operation.
    EVEX.NDS.256.66.0F3A.W0 50 /r ib      FV      V/V           AVX512VL       Calculate eight RANGE operation output value from 8 pairs
    VRANGEPS ymm1 {k1}{z}, ymm2,                                AVX512DQ       of single-precision floating-point values in ymm2 and
    ymm3/m256/m32bcst, imm8                                                    ymm3/m256/m32bcst, store the results to ymm1 under
                                                                               the writemask k1. Imm8 specifies the comparison and sign
                                                                               of the range operation.
    EVEX.NDS.512.66.0F3A.W0 50 /r ib      FV      V/V           AVX512DQ       Calculate 16 RANGE operation output value from 16 pairs
    VRANGEPS zmm1 {k1}{z}, zmm2,                                               of single-precision floating-point values in zmm2 and
    zmm3/m512/m32bcst{sae}, imm8                                               zmm3/m512/m32bcst, store the results to zmm1 under
                                                                               the writemask k1. Imm8 specifies the comparison and sign
                                                                               of the range operation.



                                                    Instruction Operand Encoding
            Op/En                   Operand 1                      Operand 2                     Operand 3               Operand 4
             FV                  ModRM:reg (w)                    EVEX.vvvv (r)                ModRM:r/m (r)               Imm8

Description
This instruction calculates 4/8/16 range operation outputs from two sets of packed input single-precision FP values
in the first source operand (the second operand) and the second source operand (the third operand). The range
outputs are written to the destination operand (the first operand) under the writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
.     Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
      absolute value of the input value pair. Each comparison of two input values produces an intermediate result
      that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
.     Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
      value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control
(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-12.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-
tude-0, opposite-signed input cases are listed in Table 5-13.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-14.





Operation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
   // Check if SNAN and report IE, see also Table 5-12
   IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
   IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);

    Src1.exp <- SRC1[30:23];
    Src1.fraction <- SRC1[22:0];
    IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
          IF DAZ THEN Src1.fraction <- 0;
          ELSE IF (SRC2 <> QNAN) Set DE; FI;
    FI;
    Src2.exp <- SRC2[30:23];
    Src2.fraction <- SRC2[22:0];
    IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
          IF DAZ THEN Src2.fraction <- 0;
          ELSE IF (SRC1 <> QNAN) Set DE; FI;
    FI;

    IF (SRC2 = QNAN) THEN{TMP[31:0] <- SRC1[31:0]}
    ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] <- SRC2[31:0]}
    ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] <- from Table 5-13
    ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] <- from Table 5-14
    ELSE
         Case(CmpOpCtl[1:0])
         00: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
         01: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
         10: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
         11: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
         ESAC;
    FI;
    Case(SignSelCtl[1:0])
    00: dest <- (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
    01: dest <- TMP[31:0];// Preserve sign of compare result
    10: dest <- (0 << 31) OR (TMP[30:0]);// Zero out sign bit
    11: dest <- (1 << 31) OR (TMP[30:0]);// Set the sign bit
    ESAC;
    RETURN dest[31:0];
}

CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];





VRANGEPS
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- RangeSP (SRC1[i+31:i], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
                    ELSE DEST[i+31:i] <- RangeSP (SRC1[i+31:i], SRC2[i+31:i], DAZ, CmpOpCtl[1:0], SignSelCtl[1:0]);
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+31:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+31:i] = 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

The following example describes a common usage of this instruction for checking that the input operand is
bounded between +-150.

VRANGEPS zmm_dst, zmm_src, zmm_150, 02h;

Where:
zmm_dst is the destination operand.
zmm_src is the input operand to compare against +-150.
zmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.

In case |zmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in zmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from zmm_src. So, even
in the case of |zmm_src| >= 150, the selected sign of SRC1 is kept.
Thus, if zmm_src < -150, the result of VRANGEPS will be the minimal value of -150 while if zmm_src > +150,
the result of VRANGE will be the maximal value of +150.





Intel C/C++ Compiler Intrinsic Equivalent
VRANGEPS __m512 _mm512_range_ps ( __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_range_round_ps ( __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_mask_range_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_mask_range_round_ps (__m512 s, __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m512 _mm512_maskz_range_ps ( __mmask16 k, __m512 a, __m512 b, int imm);
VRANGEPS __m512 _mm512_maskz_range_round_ps ( __mmask16 k, __m512 a, __m512 b, int imm, int sae);
VRANGEPS __m256 _mm256_range_ps ( __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_mask_range_ps (__m256 s, __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m256 _mm256_maskz_range_ps ( __mmask8 k, __m256 a, __m256 b, int imm);
VRANGEPS __m128 _mm_range_ps ( __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_mask_range_ps (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGEPS __m128 _mm_maskz_range_ps ( __mmask8 k, __m128 a, __m128 b, int imm);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VRANGESD
description:
VRANGESD-Range Restriction Calculation From a pair of Scalar Float64 Values
    Opcode/                             Op /    64/32        CPUID            Description
    Instruction                         En      bit Mode     Feature
                                                Support      Flag
    EVEX.NDS.LIG.66.0F3A.W1 51 /r       T1S     V/V          AVX512DQ         Calculate a RANGE operation output value from 2 double-
    VRANGESD xmm1 {k1}{z},                                                    precision floating-point values in xmm2 and xmm3/m64,
    xmm2, xmm3/m64{sae}, imm8                                                 store the output to xmm1 under writemask. Imm8 specifies
                                                                              the comparison and sign of the range operation.



                                                     Instruction Operand Encoding
          Op/En                   Operand 1                     Operand 2                    Operand 3                 Operand 4
           T1S                 ModRM:reg (w)                  EVEX.vvvv (r)                 ModRM:r/m (r)                Imm8

Description
This instruction calculates a range operation output from two input double-precision FP values in the low qword
element of the first source operand (the second operand) and second source operand (the third operand). The
range output is written to the low qword element of the destination operand (the first operand) under the
writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
.     Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
      absolute value of the input value pair. Each comparison of two input values produces an intermediate result
      that combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
.     Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
      value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
Bits 128:63 of the destination operand are copied from the respective element of the first source operand.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control
(Imm8[3:2] has no effect to the range operation output, this is indicated also in Table 5-12.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-
tude-0, opposite-signed input cases are listed in Table 5-13.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-14.





Operation
RangeDP(SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
   // Check if SNAN and report IE, see also Table 5-12
   IF (SRC1 = SNAN) THEN RETURN (QNAN(SRC1), set IE);
   IF (SRC2 = SNAN) THEN RETURN (QNAN(SRC2), set IE);

    Src1.exp <- SRC1[62:52];
    Src1.fraction <- SRC1[51:0];
    IF ((Src1.exp = 0 ) and (Src1.fraction != 0)) THEN// Src1 is a denormal number
          IF DAZ THEN Src1.fraction <- 0;
          ELSE IF (SRC2 <> QNAN) Set DE; FI;
    FI;

    Src2.exp <- SRC2[62:52];
    Src2.fraction <- SRC2[51:0];
    IF ((Src2.exp = 0) and (Src2.fraction !=0 )) THEN// Src2 is a denormal number
          IF DAZ THEN Src2.fraction <- 0;
          ELSE IF (SRC1 <> QNAN) Set DE; FI;
    FI;

    IF (SRC2 = QNAN) THEN{TMP[63:0] <- SRC1[63:0]}
    ELSE IF(SRC1 = QNAN) THEN{TMP[63:0] <- SRC2[63:0]}
    ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[63:0] <- from Table 5-13
    ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[63:0] <- from Table 5-14
    ELSE
        Case(CmpOpCtl[1:0])
        00: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC1[63:0] : SRC2[63:0];
        01: TMP[63:0] <- (SRC1[63:0] <= SRC2[63:0]) ? SRC2[63:0] : SRC1[63:0];
        10: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC1[63:0] : SRC2[63:0];
        11: TMP[63:0] <- (ABS(SRC1[63:0]) <= ABS(SRC2[63:0])) ? SRC2[63:0] : SRC1[63:0];
        ESAC;
    FI;

    Case(SignSelCtl[1:0])
    00: dest <- (SRC1[63] << 63) OR (TMP[62:0]);// Preserve Src1 sign bit
    01: dest <- TMP[63:0];// Preserve sign of compare result
    10: dest <- (0 << 63) OR (TMP[62:0]);// Zero out sign bit
    11: dest <- (1 << 63) OR (TMP[62:0]);// Set the sign bit
    ESAC;
    RETURN dest[63:0];
}

CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];





VRANGESD
IF k1[0] OR *no writemask*
         THEN DEST[63:0] <- RangeDP (SRC1[63:0], SRC2[63:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[63:0] = 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

The following example describes a common usage of this instruction for checking that the input operand is
bounded between +-1023.

VRANGESD xmm_dst, xmm_src, xmm_1023, 02h;

Where:
xmm_dst is the destination operand.
xmm_src is the input operand to compare against +-1023.
xmm_1023 is the reference operand, contains the value of 1023.
IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.

In case |xmm_src| < 1023, then its value will be written into xmm_dst. Otherwise, the value stored in xmm_dst
will get the value of 1023 (received on xmm_1023).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from xmm_src. So, even
in the case of |xmm_src| >= 1023, the selected sign of SRC1 is kept.
Thus, if xmm_src < -1023, the result of VRANGEPD will be the minimal value of -1023while if xmm_src > +1023,
the result of VRANGE will be the maximal value of +1023.



Intel C/C++ Compiler Intrinsic Equivalent
VRANGESD __m128d _mm_range_sd ( __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_range_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRANGESD __m128d _mm_mask_range_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_mask_range_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);
VRANGESD __m128d _mm_maskz_range_sd ( __mmask8 k, __m128d a, __m128d b, int imm);
VRANGESD __m128d _mm_maskz_range_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VRANGESS
description:
VRANGESS-Range Restriction Calculation From a Pair of Scalar Float32 Values
    Opcode/                         Op /    64/32      CPUID        Description
    Instruction                     En      bit Mode   Feature
                                            Support    Flag
    EVEX.NDS.LIG.66.0F3A.W0 51 /r   T1S     V/V        AVX512DQ     Calculate a RANGE operation output value from 2 single-
    VRANGESS xmm1 {k1}{z},                                          precision floating-point values in xmm2 and xmm3/m32,
    xmm2, xmm3/m32{sae}, imm8                                       store the output to xmm1 under writemask. Imm8 specifies
                                                                    the comparison and sign of the range operation.



                                                Instruction Operand Encoding
          Op/En               Operand 1                   Operand 2                       Operand 3                  Operand 4
           T1S              ModRM:reg (w)                EVEX.vvvv (r)                   ModRM:r/m (r)                   NA

Description
This instruction calculates a range operation output from two input single-precision FP values in the low dword
element of the first source operand (the second operand) and second source operand (the third operand). The
range output is written to the low dword element of the destination operand (the first operand) under the
writemask k1.
Bits7:4 of imm8 byte must be zero. The range operation output is performed in two parts, each configured by a
two-bit control field within imm8[3:0]:
.     Imm8[1:0] specifies the initial comparison operation to be one of max, min, max absolute value or min
      absolute value of the input value pair. Each comparison of two input values produces an intermediate result that
      combines with the sign selection control (Imm8[3:2]) to determine the final range operation output.
.     Imm8[3:2] specifies the sign of the range operation output to be one of the following: from the first input
      value, from the comparison result, set or clear.
The encodings of Imm8[1:0] and Imm8[3:2] are shown in Figure 5-27.
Bits 128:31 of the destination operand are copied from the respective elements of the first source operand.
When one or more of the input value is a NAN, the comparison operation may signal invalid exception (IE). Details
with one of more input value is NAN is listed in Table 5-12. If the comparison raises an IE, the sign select control
(Imm8[3:2]) has no effect to the range operation output, this is indicated also in Table 5-12.
When both input values are zeros of opposite signs, the comparison operation of MIN/MAX in the range compare
operation is slightly different from the conceptually similar FP MIN/MAX operation that are found in the instructions
VMAXPD/VMINPD. The details of MIN/MAX/MIN_ABS/MAX_ABS operation for VRANGEPD/PS/SD/SS for magni-
tude-0, opposite-signed input cases are listed in Table 5-13.
Additionally, non-zero, equal-magnitude with opposite-sign input values perform MIN_ABS or MAX_ABS compar-
ison operation with result listed in Table 5-14.





Operation
RangeSP(SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0])
{
   // Check if SNAN and report IE, see also Table 5-12
   IF (SRC1=SNAN) THEN RETURN (QNAN(SRC1), set IE);
   IF (SRC2=SNAN) THEN RETURN (QNAN(SRC2), set IE);

    Src1.exp <- SRC1[30:23];
    Src1.fraction <- SRC1[22:0];
    IF ((Src1.exp = 0 ) and (Src1.fraction != 0 )) THEN// Src1 is a denormal number
          IF DAZ THEN Src1.fraction <- 0;
          ELSE IF (SRC2 <> QNAN) Set DE; FI;
    FI;
    Src2.exp <- SRC2[30:23];
    Src2.fraction <- SRC2[22:0];
    IF ((Src2.exp = 0 ) and (Src2.fraction != 0 )) THEN// Src2 is a denormal number
          IF DAZ THEN Src2.fraction <- 0;
          ELSE IF (SRC1 <> QNAN) Set DE; FI;
    FI;

    IF (SRC2 = QNAN) THEN{TMP[31:0] <- SRC1[31:0]}
    ELSE IF(SRC1 = QNAN) THEN{TMP[31:0] <- SRC2[31:0]}
    ELSE IF (Both SRC1, SRC2 are magnitude-0 and opposite-signed) TMP[31:0] <- from Table 5-13
    ELSE IF (Both SRC1, SRC2 are magnitude-equal and opposite-signed and CmpOpCtl[1:0] > 01) TMP[31:0] <- from Table 5-14
    ELSE
         Case(CmpOpCtl[1:0])
         00: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC1[31:0] : SRC2[31:0];
         01: TMP[31:0] <- (SRC1[31:0] <= SRC2[31:0]) ? SRC2[31:0] : SRC1[31:0];
         10: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC1[31:0] : SRC2[31:0];
         11: TMP[31:0] <- (ABS(SRC1[31:0]) <= ABS(SRC2[31:0])) ? SRC2[31:0] : SRC1[31:0];
         ESAC;
    FI;
    Case(SignSelCtl[1:0])
    00: dest <- (SRC1[31] << 31) OR (TMP[30:0]);// Preserve Src1 sign bit
    01: dest <- TMP[31:0];// Preserve sign of compare result
    10: dest <- (0 << 31) OR (TMP[30:0]);// Zero out sign bit
    11: dest <- (1 << 31) OR (TMP[30:0]);// Set the sign bit
    ESAC;
    RETURN dest[31:0];
}

CmpOpCtl[1:0]= imm8[1:0];
SignSelCtl[1:0]=imm8[3:2];





VRANGESS
IF k1[0] OR *no writemask*
         THEN DEST[31:0] <- RangeSP (SRC1[31:0], SRC2[31:0], CmpOpCtl[1:0], SignSelCtl[1:0]);
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[31:0] = 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

The following example describes a common usage of this instruction for checking that the input operand is bound-
ed between +-150.

VRANGESS zmm_dst, zmm_src, zmm_150, 02h;

Where:
xmm_dst is the destination operand.
xmm_src is the input operand to compare against +-150.
xmm_150 is the reference operand, contains the value of 150.
IMM=02(imm8[1:0]='10) selects the Min Absolute value operation with selection of src1.sign.

In case |xmm_src| < 150, then its value will be written into zmm_dst. Otherwise, the value stored in xmm_dst
will get the value of 150 (received on zmm_150).
However, the sign control (imm8[3:2]='00) instructs to select the sign of SRC1 received from xmm_src. So, even
in the case of |xmm_src| >= 150, the selected sign of SRC1 is kept.
Thus, if xmm_src < -150, the result of VRANGESS will be the minimal value of -150 while if xmm_src > +150,
the result of VRANGE will be the maximal value of +150.



Intel C/C++ Compiler Intrinsic Equivalent
VRANGESS __m128 _mm_range_ss ( __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_range_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRANGESS __m128 _mm_mask_range_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_mask_range_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);
VRANGESS __m128 _mm_maskz_range_ss ( __mmask8 k, __m128 a, __m128 b, int imm);
VRANGESS __m128 _mm_maskz_range_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);

SIMD Floating-Point Exceptions

Invalid, Denormal

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VRCP14PD
description:
VRCP14PD-Compute Approximate Reciprocals of Packed Float64 Values
 Opcode/                                 Op /   64/32       CPUID          Description
 Instruction                             En     bit Mode    Feature
                                                Support     Flag
 EVEX.128.66.0F38.W1 4C /r               FV     V/V         AVX512VL       Computes the approximate reciprocals of the packed double-
 VRCP14PD xmm1 {k1}{z},                                     AVX512F        precision floating-point values in xmm2/m128/m64bcst and
 xmm2/m128/m64bcst                                                         stores the results in xmm1. Under writemask.
 EVEX.256.66.0F38.W1 4C /r               FV     V/V         AVX512VL       Computes the approximate reciprocals of the packed double-
 VRCP14PD ymm1 {k1}{z},                                     AVX512F        precision floating-point values in ymm2/m256/m64bcst and
 ymm2/m256/m64bcst                                                         stores the results in ymm1. Under writemask.
 EVEX.512.66.0F38.W1 4C /r               FV     V/V         AVX512F        Computes the approximate reciprocals of the packed double-
 VRCP14PD zmm1 {k1}{z},                                                    precision floating-point values in zmm2/m512/m64bcst and
 zmm2/m512/m64bcst                                                         stores the results in zmm1. Under writemask.



                                                      Instruction Operand Encoding
          Op/En                Operand 1                     Operand 2                   Operand 3                    Operand 4
              FV             ModRM:reg (w)                 ModRM:r/m (r)                     NA                          NA

Description
This instruction performs a SIMD computation of the approximate reciprocals of eight/four/two packed double-
precision floating-point values in the source operand (the second operand) and stores the packed double-precision
floating-point results in the destination operand. The maximum relative error for this approximation is less than 2-
14
   .
The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 64-
bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.
The VRCP14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

                                          Table 5-15. VRCP14PD/VRCP14SD Special Cases
 Input value                       Result value               Comments
 0 <= X <= 2-1024                    INF                        Very small denormal
      -1024 <=
 -2             X <= -0             -INF                       Very small denormal
         1022
 X>2                               Underflow                  Up to 18 bits of fractions are returned*
 X < -21022                        -Underflow                 Up to 18 bits of fractions are returned*
         -n                        2n
 X=2
 X = -2-n                          -2n

* in this case the mantissa is shifted right by one or two bits


A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.





Operation
VRCP14PD ((EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask* THEN
             IF (EVEX.b = 1) AND (SRC *is memory*)
                  THEN DEST[i+63:i] <- APPROXIMATE(1.0/SRC[63:0]);
                  ELSE DEST[i+63:i] <- APPROXIMATE(1.0/SRC[i+63:i]);
             FI;
   ELSE
        IF *merging-masking*                 ; merging-masking
             THEN *DEST[i+63:i] remains unchanged*
             ELSE                            ; zeroing-masking
                  DEST[i+63:i] <- 0
        FI;
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VRCP14PD __m512d _mm512_rcp14_pd( __m512d a);
VRCP14PD __m512d _mm512_mask_rcp14_pd(__m512d s, __mmask8 k, __m512d a);
VRCP14PD __m512d _mm512_maskz_rcp14_pd( __mmask8 k, __m512d a);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VRCP14SD
description:
VRCP14SD-Compute Approximate Reciprocal of Scalar Float64 Value
 Opcode/                              Op     64/32        CPUID         Description
 Instruction                          / En   bit Mode     Feature
                                             Support      Flag
 EVEX.NDS.LIG.66.0F38.W1 4D /r        T1S    V/V          AVX512F       Computes the approximate reciprocal of the scalar double-
 VRCP14SD xmm1 {k1}{z}, xmm2,                                           precision floating-point value in xmm3/m64 and stores the
 xmm3/m64                                                               result in xmm1 using writemask k1. Also, upper double-precision
                                                                        floating-point value (bits[127:64]) from xmm2 is copied to
                                                                        xmm1[127:64].



                                                  Instruction Operand Encoding
       Op/En                 Operand 1                   Operand 2                     Operand 3                   Operand 4
        T1S                ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                    NA

Description
This instruction performs a SIMD computation of the approximate reciprocal of the low double-precision floating-
point value in the second source operand (the third operand) stores the result in the low quadword element of the
destination operand (the first operand) according to the writemask k1. Bits (127:64) of the XMM register destina-
tion are copied from corresponding bits in the first source operand (the second operand). The maximum relative
error for this approximation is less than 2-14. The source operand can be an XMM register or a 64-bit memory loca-
tion. The destination operand is an XMM register.
The VRCP14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned. See Table 5-15 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP14SD (EVEX version)
IF k1[0] OR *no writemask*
         THEN DEST[63:0] <- APPROXIMATE(1.0/SRC2[63:0]);
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SD __m128d _mm_rcp14_sd( __m128d a, __m128d b);
VRCP14SD __m128d _mm_mask_rcp14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VRCP14SD __m128d _mm_maskz_rcp14_sd( __mmask8 k, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E5.






platform: x86_64
mnem: VRCP14PS
description:
VRCP14PS-Compute Approximate Reciprocals of Packed Float32 Values
 Opcode/                                 Op /   64/32        CPUID          Description
 Instruction                             En     bit Mode     Feature
                                                Support      Flag
 EVEX.128.66.0F38.W0 4C /r               FV     V/V          AVX512VL       Computes the approximate reciprocals of the packed single-
 VRCP14PS xmm1 {k1}{z},                                      AVX512F        precision floating-point values in xmm2/m128/m32bcst and
 xmm2/m128/m32bcst                                                          stores the results in xmm1. Under writemask.
 EVEX.256.66.0F38.W0 4C /r               FV     V/V          AVX512VL       Computes the approximate reciprocals of the packed single-
 VRCP14PS ymm1 {k1}{z},                                      AVX512F        precision floating-point values in ymm2/m256/m32bcst and
 ymm2/m256/m32bcst                                                          stores the results in ymm1. Under writemask.
 EVEX.512.66.0F38.W0 4C /r               FV     V/V          AVX512F        Computes the approximate reciprocals of the packed single-
 VRCP14PS zmm1 {k1}{z},                                                     precision floating-point values in zmm2/m512/m32bcst and
 zmm2/m512/m32bcst                                                          stores the results in zmm1. Under writemask.



                                                      Instruction Operand Encoding
       Op/En                 Operand 1                      Operand 2                     Operand 3                   Operand 4
         FV                ModRM:reg (w)                   ModRM:r/m (r)                     NA                           NA

Description
This instruction performs a SIMD computation of the approximate reciprocals of the packed single-precision
floating-point values in the source operand (the second operand) and stores the packed single-precision floating-
point results in the destination operand (the first operand). The maximum relative error for this approximation is
less than 2-14.
The source operand can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-
bit memory location. The destination operand is a ZMM register conditionally updated according to the writemask.
The VRCP14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.

                                          Table 5-16. VRCP14PS/VRCP14SS Special Cases
  Input value                      Result value                Comments
  0 <= X <= 2-128                    INF                         Very small denormal
    -128 <=
  -2         X <= -0                -INF                        Very small denormal
       126
  X>2                              Underflow                   Up to 18 bits of fractions are returned*
  X < -2126                        -Underflow                  Up to 18 bits of fractions are returned*
        -n                         2n
  X=2
  X = -2-n                         -2n

* in this case the mantissa is shifted right by one or two bits


A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.





Operation
VRCP14PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+31:i] <- APPROXIMATE(1.0/SRC[31:0]);
                    ELSE DEST[i+31:i] <- APPROXIMATE(1.0/SRC[i+31:i]);
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+31:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+31:i] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VRCP14PS __m512 _mm512_rcp14_ps( __m512 a);
VRCP14PS __m512 _mm512_mask_rcp14_ps(__m512 s, __mmask16 k, __m512 a);
VRCP14PS __m512 _mm512_maskz_rcp14_ps( __mmask16 k, __m512 a);
VRCP14PS __m256 _mm256_rcp14_ps( __m256 a);
VRCP14PS __m256 _mm512_mask_rcp14_ps(__m256 s, __mmask8 k, __m256 a);
VRCP14PS __m256 _mm512_maskz_rcp14_ps( __mmask8 k, __m256 a);
VRCP14PS __m128 _mm_rcp14_ps( __m128 a);
VRCP14PS __m128 _mm_mask_rcp14_ps(__m128 s, __mmask8 k, __m128 a);
VRCP14PS __m128 _mm_maskz_rcp14_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VRCP14SS
description:
VRCP14SS-Compute Approximate Reciprocal of Scalar Float32 Value
 Opcode/                                 Op /   64/32        CPUID      Description
 Instruction                             En     bit Mode     Feature
                                                Support      Flag
 EVEX.NDS.LIG.66.0F38.W0 4D /r           T1S    V/V          AVX512F    Computes the approximate reciprocal of the scalar single-
 VRCP14SS xmm1 {k1}{z}, xmm2,                                           precision floating-point value in xmm3/m32 and stores the
 xmm3/m32                                                               results in xmm1 using writemask k1. Also, upper double-
                                                                        precision floating-point value (bits[127:32]) from xmm2 is
                                                                        copied to xmm1[127:32].



                                                  Instruction Operand Encoding
       Op/En                 Operand 1                     Operand 2                  Operand 3                  Operand 4
        T1S                ModRM:reg (w)                EVEX.vvvv (r)             ModRM:r/m (r)                     NA

Description
This instruction performs a SIMD computation of the approximate reciprocal of the low single-precision floating-
point value in the second source operand (the third operand) and stores the result in the low quadword element of
the destination operand (the first operand) according to the writemask k1. Bits (127:32) of the XMM register desti-
nation are copied from corresponding bits in the first source operand (the second operand). The maximum relative
error for this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory loca-
tion. The destination operand is an XMM register.
The VRCP14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source value
is a 0.0, an inf with the sign of the source value is returned. A denormal source value will be treated as zero only in
case of DAZ bit set in MXCSR. Otherwise it is treated correctly (i.e. not as a 0.0). Underflow results are flushed to
zero only in case of FTZ bit set in MXCSR. Otherwise it will be treated correctly (i.e. correct underflow result is
written) with the sign of the operand. When a source value is a SNaN or QNaN, the SNaN is converted to a QNaN
or the source QNaN is returned. See Table 5-16 for special-case input values.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRCP14xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP14SS (EVEX version)
IF k1[0] OR *no writemask*
         THEN DEST[31:0] <- APPROXIMATE(1.0/SRC2[31:0]);
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VRCP14SS __m128 _mm_rcp14_ss( __m128 a, __m128 b);
VRCP14SS __m128 _mm_mask_rcp14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VRCP14SS __m128 _mm_maskz_rcp14_ss( __mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E5.






platform: x86_64
mnem: VRCP28PD
description:
VRCP28PD-Approximation to the Reciprocal of Packed Double-Precision Floating-Point Values
with Less Than 2^-28 Relative Error
 Opcode/                            Op /    64/32         CPUID           Description
 Instruction                        En      bit Mode      Feature
                                            Support       Flag
 EVEX.512.66.0F38.W1 CA /r          FV      V/V           AVX512ER        Computes the approximate reciprocals ( < 2^-28 relative error)
 VRCP28PD zmm1 {k1}{z},                                                   of the packed double-precision floating-point values in
 zmm2/m512/m64bcst {sae}                                                  zmm2/m512/m64bcst and stores the results in zmm1. Under
                                                                          writemask.



                                                     Instruction Operand Encoding
      Op/En                  Operand 1                      Operand 2                     Operand 3                       Operand 4
        FV                ModRM:reg (w)                   ModRM:r/m (r)                       NA                                NA

Description
Computes the reciprocal approximation of the float64 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP28PD (EVEX encoded versions)
(KL, VL) = (8, 512)

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask* THEN
             IF (EVEX.b = 1) AND (SRC *is memory*)
                  THEN DEST[i+63:i] <- RCP_28_DP(1.0/SRC[63:0]);
                  ELSE DEST[i+63:i] <- RCP_28_DP(1.0/SRC[i+63:i]);
             FI;
   ELSE
        IF *merging-masking*                 ; merging-masking
             THEN *DEST[i+63:i] remains unchanged*
             ELSE                            ; zeroing-masking
                  DEST[i+63:i] <- 0
        FI;
   FI;
ENDFOR;





                                                  Table 5-17. VRCP28PD Special Cases
          Input value                    Result value              Comments
          NAN                            QNAN(input)               If (SRC = SNaN) then #I
          0<=X<          2-1022           INF                       Positive input denormal or zero; #Z
               -1022
          -2           < X <= -0          -INF                      Negative input denormal or zero; #Z
          X>    21022                    +0.0f
                   1022
          X < -2                         -0.0f
          X = +inf                         +0.0f
          X = -inf                         -0.0f
          X=    2-n                      2n                        Exact result (unless input/output is a denormal)
                   -n                         n
          X = -2                         -2                        Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PD __m512d _mm512_rcp28_round_pd ( __m512d a, int sae);
VRCP28PD __m512d _mm512_mask_rcp28_round_pd(__m512d a, __mmask8 m, __m512d b, int sae);
VRCP28PD __m512d _mm512_maskz_rcp28_round_pd( __mmask8 m, __m512d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E2.






platform: x86_64
mnem: VRCP28SD
description:
VRCP28SD-Approximation to the Reciprocal of Scalar Double-Precision Floating-Point Value
with Less Than 2^-28 Relative Error
 Opcode/                                   Op /    64/32         CPUID           Description
 Instruction                               En      bit Mode      Feature
                                                   Support       Flag
 EVEX.NDS.LIG.66.0F38.W1 CB /r             T1S     V/V           AVX512ER        Computes the approximate reciprocal ( < 2^-28 relative
 VRCP28SD xmm1 {k1}{z}, xmm2,                                                    error) of the scalar double-precision floating-point value
 xmm3/m64 {sae}                                                                  in xmm3/m64 and stores the results in xmm1. Under
                                                                                 writemask. Also, upper double-precision floating-point
                                                                                 value (bits[127:64]) from xmm2 is copied to
                                                                                 xmm1[127:64].



                                                     Instruction Operand Encoding
      Op/En                 Operand 1                      Operand 2                       Operand 3                       Operand 4
       T1S               ModRM:reg (w)                     EVEX.vvvv                     ModRM:r/m (r)                         NA

Description
Computes the reciprocal approximation of the low float64 value in the second source operand (the third operand)
and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with
less than 2^-28 of maximum relative error. The result is written into the low float64 element of the destination
operand according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the
first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result
is flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory
location. The destination operand is a XMM register, conditionally updated using writemask k1.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP28SD ((EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
              DEST[63: 0] <- RCP_28_DP(1.0/SRC2[63: 0]);
ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[63: 0] remains unchanged*
              ELSE                          ; zeroing-masking
                  DEST[63: 0] <- 0
         FI;
FI;
ENDFOR;
DEST[127:64] <- SRC1[127: 64]
DEST[MAX_VL-1:128] <- 0





                                                     Table 5-18. VRCP28SD Special Cases
          Input value                       Result value               Comments
          NAN                               QNAN(input)                If (SRC = SNaN) then #I
          0<=X<          2-1022              INF                        Positive input denormal or zero; #Z
               -1022
          -2           < X <= -0             -INF                       Negative input denormal or zero; #Z
          X>    21022                       +0.0f
                   1022
          X < -2                            -0.0f
          X = +inf                            +0.0f
          X = -inf                            -0.0f
          X=    2-n                         2n                         Exact result (unless input/output is a denormal)
                   -n                            n
          X = -2                            -2                         Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent
VRCP28SD __m128d _mm_rcp28_round_sd ( __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_mask_rcp28_round_sd(__m128d s, __mmask8 m, __m128d a, __m128d b, int sae);
VRCP28SD __m128d _mm_maskz_rcp28_round_sd(__mmask8 m, __m128d a, __m128d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E3.






platform: x86_64
mnem: VRCP28PS
description:
VRCP28PS-Approximation to the Reciprocal of Packed Single-Precision Floating-Point Values
with Less Than 2^-28 Relative Error
 Opcode/                               Op /    64/32         CPUID           Description
 Instruction                           En      bit Mode      Feature
                                               Support       Flag
 EVEX.512.66.0F38.W0 CA /r             FV      V/V           AVX512ER        Computes the approximate reciprocals ( < 2^-28 relative
 VRCP28PS zmm1 {k1}{z},                                                      error) of the packed single-precision floating-point values in
 zmm2/m512/m32bcst {sae}                                                     zmm2/m512/m32bcst and stores the results in zmm1. Under
                                                                             writemask.



                                                     Instruction Operand Encoding
     Op/En                 Operand 1                        Operand 2                       Operand 3                      Operand 4
       FV                ModRM:reg (w)                    ModRM:r/m (r)                         NA                              NA

Description
Computes the reciprocal approximation of the float32 values in the source operand (the second operand) and store
the results to the destination operand (the first operand) using the writemask k1. The approximate reciprocal is
evaluated with less than 2^-28 of maximum relative error prior to final rounding. The final results are rounded to
< 2^-23 relative error before written to the destination.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results
are flushed to zeros and do not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP28PS (EVEX encoded versions)
(KL, VL) = (16, 512)

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask* THEN
             IF (EVEX.b = 1) AND (SRC *is memory*)
                  THEN DEST[i+31:i] <- RCP_28_SP(1.0/SRC[31:0]);
                  ELSE DEST[i+31:i] <- RCP_28_SP(1.0/SRC[i+31:i]);
             FI;
   ELSE
        IF *merging-masking*                 ; merging-masking
             THEN *DEST[i+31:i] remains unchanged*
             ELSE                            ; zeroing-masking
                  DEST[i+31:i] <- 0
        FI;
   FI;
ENDFOR;





                                                     Table 5-19. VRCP28PS Special Cases
          Input value                       Result value               Comments
          NAN                               QNAN(input)                If (SRC = SNaN) then #I
          0<=X<             2-126            INF                        Positive input denormal or zero; #Z
               -126
          -2          < X <= -0              -INF                       Negative input denormal or zero; #Z
          X>    2126                        +0.0f
                      126
          X < -2                            -0.0f
          X = +inf                            +0.0f
          X = -inf                            -0.0f
          X=    2-n                         2n                         Exact result (unless input/output is a denormal)
                      -n                         n
          X = -2                            -2                         Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent
VRCP28PS _mm512_rcp28_round_ps ( __m512 a, int sae);
VRCP28PS __m512 _mm512_mask_rcp28_round_ps(__m512 s, __mmask16 m, __m512 a, int sae);
VRCP28PS __m512 _mm512_maskz_rcp28_round_ps( __mmask16 m, __m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E2.






platform: x86_64
mnem: VRCP28SS
description:
VRCP28SS-Approximation to the Reciprocal of Scalar Single-Precision Floating-Point Value
with Less Than 2^-28 Relative Error
 Opcode/                                Op /    64/32         CPUID            Description
 Instruction                            En      bit Mode      Feature
                                                Support       Flag
 EVEX.NDS.LIG.66.0F38.W0 CB /r          T1S     V/V           AVX512ER         Computes the approximate reciprocal ( < 2^-28 relative
 VRCP28SS xmm1 {k1}{z},                                                        error) of the scalar single-precision floating-point value in
 xmm2, xmm3/m32 {sae}                                                          xmm3/m32 and stores the results in xmm1. Under
                                                                               writemask. Also, upper 3 single-precision floating-point
                                                                               values (bits[127:32]) from xmm2 is copied to
                                                                               xmm1[127:32].



                                                      Instruction Operand Encoding
      Op/En                  Operand 1                       Operand 2                       Operand 3                         Operand 4
       T1S                 ModRM:reg (w)                     EVEX.vvvv                     ModRM:r/m (r)                          NA

Description
Computes the reciprocal approximation of the low float32 value in the second source operand (the third operand)
and store the result to the destination operand (the first operand). The approximate reciprocal is evaluated with
less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 relative
error before written into the low float32 element of the destination according to writemask k1. Bits 127:32 of the
destination is copied from the corresponding bits of the first source operand (the second operand).
A denormal input value is treated as zero and does not signal #DE, irrespective of MXCSR.DAZ. A denormal result
is flushed to zero and does not signal #UE, irrespective of MXCSR.FZ.
If any source element is NaN, the quietized NaN source value is returned for that element. If any source element is
+-inf, +-0.0 is returned for that element. Also, if any source element is +-0.0, +-inf is returned for that element.
The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory
location. The destination operand is a XMM register, conditionally updated using writemask k1.
A numerically exact implementation of VRCP28xx can be found at https://software.intel.com/en-us/articles/refer-
ence-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRCP28SS ((EVEX encoded versions)
IF k1[0] OR *no writemask* THEN
              DEST[31: 0] <- RCP_28_SP(1.0/SRC2[31: 0]);
ELSE
         IF *merging-masking*               ; merging-masking
              THEN *DEST[31: 0] remains unchanged*
              ELSE                          ; zeroing-masking
                  DEST[31: 0] <- 0
         FI;
FI;
ENDFOR;
DEST[127:32] <- SRC1[127: 32]
DEST[MAX_VL-1:128] <- 0





                                                        Table 5-20. VRCP28SS Special Cases
          Input value                          Result value               Comments
          NAN                                  QNAN(input)                If (SRC = SNaN) then #I
          0<=X<             2-126               INF                        Positive input denormal or zero; #Z
               -126
          -2          < X <= -0                 -INF                       Negative input denormal or zero; #Z
          X>    2126                           +0.0f
                      126
          X < -2                               -0.0f
          X = +inf                               +0.0f
          X = -inf                               -0.0f
          X=    2-n                            2n                         Exact result (unless input/output is a denormal)
                      -n                            n
          X = -2                               -2                         Exact result (unless input/output is a denormal)

Intel C/C++ Compiler Intrinsic Equivalent

VRCP28SS __m128 _mm_rcp28_round_ss ( __m128 a, __m128 b, int sae);
VRCP28SS __m128 _mm_mask_rcp28_round_ss(__m128 s, __mmask8 m, __m128 a, __m128 b, int sae);
VRCP28SS __m128 _mm_maskz_rcp28_round_ss(__mmask8 m, __m128 a, __m128 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E3.






platform: x86_64
mnem: VREDUCEPD
description:
VREDUCEPD-Perform Reduction Transformation on Packed Float64 Values
 Opcode/                                           Op /         64/32            CPUID               Description
 Instruction                                       En           bit Mode         Feature
                                                                Support          Flag
 EVEX.128.66.0F3A.W1 56 /r ib                      FV           V/V              AVX512VL            Perform reduction transformation on packed double-precision
 VREDUCEPD xmm1 {k1}{z},                                                         AVX512DQ            floating point values in xmm2/m128/m32bcst by subtracting
 xmm2/m128/m64bcst, imm8                                                                             a number of fraction bits specified by the imm8 field. Stores
                                                                                                     the result in xmm1 register under writemask k1.
 EVEX.256.66.0F3A.W1 56 /r ib                      FV           V/V              AVX512VL            Perform reduction transformation on packed double-precision
 VREDUCEPD ymm1 {k1}{z},                                                         AVX512DQ            floating point values in ymm2/m256/m32bcst by subtracting
 ymm2/m256/m64bcst, imm8                                                                             a number of fraction bits specified by the imm8 field. Stores
                                                                                                     the result in ymm1 register under writemask k1.
 EVEX.512.66.0F3A.W1 56 /r ib                      FV           V/V              AVX512DQ            Perform reduction transformation on double-precision floating
 VREDUCEPD zmm1 {k1}{z},                                                                             point values in zmm2/m512/m32bcst by subtracting a
 zmm2/m512/m64bcst{sae},                                                                             number of fraction bits specified by the imm8 field. Stores the
 imm8                                                                                                result in zmm1 register under writemask k1.



                                                                      Instruction Operand Encoding
           Op/En                              Operand 1                                Operand 2                              Operand 3                           Operand 4
             FV                           ModRM:reg (w)                              ModRM:r/m (r)                                  Imm8                                NA

Description
Perform reduction transformation of the packed binary encoded double-precision FP values in the source operand
(the second operand) and store the reduced results in binary FP format to the destination operand (the first
operand) under the writemask k1.
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-
mation can be expressed as:
dest = src - (ROUND(2M*src))*2-M;
where "Round()" treats "src", "2M", and their product as binary FP numbers with normalized significand and bi-
ased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where 'man2' is the normalized significand and 'p' is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC != RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.



                        7                 6                 5                4                 3              2                1                0

    imm8                                   Fixed point length                                SPE             RS               Round Control Override



                                                                  Suppress Precision Exception: Imm8[3]                                        Imm8[1:0] = 00b : Round nearest even
                                                                  Imm8[3] = 0b : Use MXCSR exception mask   Round Select: Imm8[2]
           Imm8[7:4] : Number of fixed points to subtract                                                                                      Imm8[1:0] = 01b : Round down
                                                                  Imm8[3] = 1b : Suppress                   Imm8[2] = 0b : Use Imm8[1:0]
                                                                                                                                               Imm8[1:0] = 10b : Round up
                                                                                                            Imm8[2] = 1b : Use MXCSR
                                                                                                                                               Imm8[1:0] = 11b : Truncate



                                                 Figure 5-28. Imm8 Controls for VREDUCEPD/SD/PS/SS




Handling of special case of input values are listed in Table 5-21.

                                     Table 5-21. VREDUCEPD/SD/PS/SS Special Cases
                                               Round Mode                           Returned value
  |Src1| <   2-M-1                             RNE                                  Src1
                                               RPI, Src1 > 0                        Round (Src1-2-M) *
                                               RPI, Src1 <= 0                        Src1
                                               RNI, Src1 >= 0                        Src1
  |Src1| <   2-M                               RNI, Src1 < 0                        Round (Src1+2-M) *
                                               NOT RNI                              +0.0
  Src1 = +-0, or
  Dest = +-0 (Src1!=INF)                        RNI                                  -0.0
  Src1 = +-INF                                  any                                  +0.0
  Src1= +-NAN                                   n/a                                  QNaN(Src1)

   * Round control = (imm8.MS1)? MXCSR.RC: imm8.RC

Operation
ReduceArgumentDP(SRC[63:0], imm8[7:0])
{
   // Check for NaN
   IF (SRC [63:0] = NAN) THEN
        RETURN (Convert SRC[63:0] to QNaN); FI;
   M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
   RC <- imm8[1:0];// Round Control for ROUND() operation
   RC source <- imm[2];
   SPE <- 0;// Suppress Precision Exception
   TMP[63:0] <- 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
   TMP[63:0] <- SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls
   RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}

VREDUCEPD
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC *is memory*)
                    THEN DEST[i+63:i] <- ReduceArgumentDP(SRC[63:0], imm8[7:0]);
                    ELSE DEST[i+63:i] <- ReduceArgumentDP(SRC[i+63:i], imm8[7:0]);
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+63:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+63:i] = 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VREDUCEPD __m512d _mm512_mask_reduce_pd( __m512d a, int imm, int sae)
VREDUCEPD __m512d _mm512_mask_reduce_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae)
VREDUCEPD __m512d _mm512_maskz_reduce_pd(__mmask8 k, __m512d a, int imm, int sae)
VREDUCEPD __m256d _mm256_mask_reduce_pd( __m256d a, int imm)
VREDUCEPD __m256d _mm256_mask_reduce_pd(__m256d s, __mmask8 k, __m256d a, int imm)
VREDUCEPD __m256d _mm256_maskz_reduce_pd(__mmask8 k, __m256d a, int imm)
VREDUCEPD __m128d _mm_mask_reduce_pd( __m128d a, int imm)
VREDUCEPD __m128d _mm_mask_reduce_pd(__m128d s, __mmask8 k, __m128d a, int imm)
VREDUCEPD __m128d _mm_maskz_reduce_pd(__mmask8 k, __m128d a, int imm)

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E2, additionally
#UD                     If EVEX.vvvv != 1111B.






platform: x86_64
mnem: VREDUCESD
description:
VREDUCESD-Perform a Reduction Transformation on a Scalar Float64 Value
 Opcode/                         Op /   64/32 bit    CPUID       Description
 Instruction                     En     Mode         Feature
                                        Support      Flag
 EVEX.NDS.LIG.66.0F3A.W1 57      T1S    V/V          AVX512D     Perform a reduction transformation on a scalar double-precision
 VREDUCESD xmm1 {k1}{z},                             Q           floating point value in xmm3/m64 by subtracting a number of
 xmm2, xmm3/m64{sae},                                            fraction bits specified by the imm8 field. Also, upper double
 imm8/r                                                          precision floating-point value (bits[127:64]) from xmm2 are
                                                                 copied to xmm1[127:64]. Stores the result in xmm1 register.



                                               Instruction Operand Encoding
         Op/En                 Operand 1                    Operand 2                     Operand 3               Operand 4
            T1S              ModRM:reg (w)                EVEX.vvvv (r)                 ModRM:r/m (r)                 NA

Description
Perform a reduction transformation of the binary encoded double-precision FP value in the low qword element of
the second source operand (the third operand) and store the reduced result in binary FP format to the low qword
element of the destination operand (the first operand) under the writemask k1. Bits 127:64 of the destination
operand are copied from respective qword elements of the first source operand (the second operand).
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-
mation can be expressed as:
dest = src - (ROUND(2M*src))*2-M;
where "Round()" treats "src", "2M", and their product as binary FP numbers with normalized significand and bi-
ased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where 'man2' is the normalized significand and 'p' is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC != RNE: 0<=|Reduced Result|<2p-M
This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
The operation is write masked.
Handling of special case of input values are listed in Table 5-21.

Operation
ReduceArgumentDP(SRC[63:0], imm8[7:0])
{
   // Check for NaN
   IF (SRC [63:0] = NAN) THEN
        RETURN (Convert SRC[63:0] to QNaN); FI;
   M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
   RC <- imm8[1:0];// Round Control for ROUND() operation
   RC source <- imm[2];
   SPE <- 0;// Suppress Precision Exception
   TMP[63:0] <- 2-M *{ROUND(2M*SRC[63:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
   TMP[63:0] <- SRC[63:0] - TMP[63:0]; // subtraction under the same RC,SPE controls
   RETURN TMP[63:0]; // binary encoded FP with biased exponent and normalized significand
}





VREDUCESD
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- ReduceArgumentDP(SRC2[63:0], imm8[7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] = 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0



Intel C/C++ Compiler Intrinsic Equivalent
VREDUCESD __m128d _mm_mask_reduce_sd( __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_mask_reduce_sd(__m128d s, __mmask16 k, __m128d a, __m128d b, int imm, int sae)
VREDUCESD __m128d _mm_maskz_reduce_sd(__mmask16 k, __m128d a, __m128d b, int imm, int sae)

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VREDUCEPS
description:
VREDUCEPS-Perform Reduction Transformation on Packed Float32 Values
 Opcode/                         Op /   64/32       CPUID            Description
 Instruction                     En     bit Mode    Feature
                                        Support     Flag
 EVEX.128.66.0F3A.W0 56 /r ib    FV     V/V         AVX512VL         Perform reduction transformation on packed single-precision
 VREDUCEPS xmm1 {k1}{z},                            AVX512DQ         floating point values in xmm2/m128/m32bcst by subtracting
 xmm2/m128/m32bcst, imm8                                             a number of fraction bits specified by the imm8 field. Stores
                                                                     the result in xmm1 register under writemask k1.
 EVEX.256.66.0F3A.W0 56 /r ib    FV     V/V         AVX512VL         Perform reduction transformation on packed single-precision
 VREDUCEPS ymm1 {k1}{z},                            AVX512DQ         floating point values in ymm2/m256/m32bcst by subtracting
 ymm2/m256/m32bcst, imm8                                             a number of fraction bits specified by the imm8 field. Stores
                                                                     the result in ymm1 register under writemask k1.
 EVEX.512.66.0F3A.W0 56 /r ib    FV     V/V         AVX512DQ         Perform reduction transformation on packed single-precision
 VREDUCEPS zmm1 {k1}{z},                                             floating point values in zmm2/m512/m32bcst by subtracting
 zmm2/m512/m32bcst{sae},                                             a number of fraction bits specified by the imm8 field. Stores
 imm8                                                                the result in zmm1 register under writemask k1.



                                              Instruction Operand Encoding
     Op/En              Operand 1                   Operand 2                      Operand 3                    Operand 4
       FV             ModRM:reg (w)                ModRM:r/m (r)                     Imm8                           NA

Description
Perform reduction transformation of the packed binary encoded single-precision FP values in the source operand
(the second operand) and store the reduced results in binary FP format to the destination operand (the first
operand) under the writemask k1.
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-
mation can be expressed as:
dest = src - (ROUND(2M*src))*2-M;
where "Round()" treats "src", "2M", and their product as binary FP numbers with normalized significand and bi-
ased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where 'man2' is the normalized significand and 'p' is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC != RNE: 0<=|Reduced Result|<2p-M


This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
Handling of special case of input values are listed in Table 5-21.





Operation
ReduceArgumentSP(SRC[31:0], imm8[7:0])
{
   // Check for NaN
   IF (SRC [31:0] = NAN) THEN
        RETURN (Convert SRC[31:0] to QNaN); FI
   M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
   RC <- imm8[1:0];// Round Control for ROUND() operation
   RC source <- imm[2];
   SPE <- 0;// Suppress Precision Exception
   TMP[31:0] <- 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
   TMP[31:0] <- SRC[31:0] - TMP[31:0]; // subtraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand
}

VREDUCEPS
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC *is memory*)
                    THEN DEST[i+31:i] <- ReduceArgumentSP(SRC[31:0], imm8[7:0]);
                    ELSE DEST[i+31:i] <- ReduceArgumentSP(SRC[i+31:i], imm8[7:0]);
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+31:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+31:i] = 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VREDUCEPS __m512 _mm512_mask_reduce_ps( __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_mask_reduce_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m512 _mm512_maskz_reduce_ps(__mmask16 k, __m512 a, int imm, int sae)
VREDUCEPS __m256 _mm256_mask_reduce_ps( __m256 a, int imm)
VREDUCEPS __m256 _mm256_mask_reduce_ps(__m256 s, __mmask8 k, __m256 a, int imm)
VREDUCEPS __m256 _mm256_maskz_reduce_ps(__mmask8 k, __m256 a, int imm)
VREDUCEPS __m128 _mm_mask_reduce_ps( __m128 a, int imm)
VREDUCEPS __m128 _mm_mask_reduce_ps(__m128 s, __mmask8 k, __m128 a, int imm)
VREDUCEPS __m128 _mm_maskz_reduce_ps(__mmask8 k, __m128 a, int imm)

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E2, additionally
#UD                     If EVEX.vvvv != 1111B.





platform: x86_64
mnem: VREDUCESS
description:
VREDUCESS-Perform a Reduction Transformation on a Scalar Float32 Value
 Opcode/                        Op /    64/32      CPUID          Description
 Instruction                    En      bit Mode   Feature
                                        Support    Flag
 EVEX.NDS.LIG.66.0F3A.W0 57     T1S     V/V        AVX512DQ       Perform a reduction transformation on a scalar single-precision
 /r /ib                                                           floating point value in xmm3/m32 by subtracting a number of
 VREDUCESS xmm1 {k1}{z},                                          fraction bits specified by the imm8 field. Also, upper single
 xmm2, xmm3/m32{sae},                                             precision floating-point values (bits[127:32]) from xmm2 are
 imm8                                                             copied to xmm1[127:32]. Stores the result in xmm1 register.



                                               Instruction Operand Encoding
        Op/En                  Operand 1                   Operand 2                   Operand 3                  Operand 4
         T1S                ModRM:reg (w)                 EVEX.vvvv (r)              ModRM:r/m (r)                    NA

Description
Perform a reduction transformation of the binary encoded single-precision FP value in the low dword element of the
second source operand (the third operand) and store the reduced result in binary FP format to the low dword
element of the destination operand (the first operand) under the writemask k1. Bits 127:32 of the destination
operand are copied from respective dword elements of the first source operand (the second operand).
The reduction transformation subtracts the integer part and the leading M fractional bits from the binary FP source
value, where M is a unsigned integer specified by imm8[7:4], see Figure 5-28. Specifically, the reduction transfor-
mation can be expressed as:
dest = src - (ROUND(2M*src))*2-M;
where "Round()" treats "src", "2M", and their product as binary FP numbers with normalized significand and bi-
ased exponents.
The magnitude of the reduced result can be expressed by considering src= 2p*man2,
where 'man2' is the normalized significand and 'p' is the unbiased exponent
Then if RC = RNE: 0<=|Reduced Result|<=2p-M-1
Then if RC != RNE: 0<=|Reduced Result|<2p-M


This instruction might end up with a precision exception set. However, in case of SPE set (i.e. Suppress Precision
Exception, which is imm8[3]=1), no precision exception is reported.
Handling of special case of input values are listed in Table 5-21.

Operation
ReduceArgumentSP(SRC[31:0], imm8[7:0])
{
   // Check for NaN
   IF (SRC [31:0] = NAN) THEN
        RETURN (Convert SRC[31:0] to QNaN); FI
   M <- imm8[7:4]; // Number of fraction bits of the normalized significand to be subtracted
   RC <- imm8[1:0];// Round Control for ROUND() operation
   RC source <- imm[2];
   SPE <- 0;// Suppress Precision Exception
   TMP[31:0] <- 2-M *{ROUND(2M*SRC[31:0], SPE, RC_source, RC)}; // ROUND() treats SRC and 2M as standard binary FP values
   TMP[31:0] <- SRC[31:0] - TMP[31:0]; // subtraction under the same RC,SPE controls
RETURN TMP[31:0]; // binary encoded FP with biased exponent and normalized significand
}





VREDUCESS
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- ReduceArgumentSP(SRC2[31:0], imm8[7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] = 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0



Intel C/C++ Compiler Intrinsic Equivalent
VREDUCESS __m128 _mm_mask_reduce_ss( __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_mask_reduce_ss(__m128 s, __mmask16 k, __m128 a, __m128 b, int imm, int sae)
VREDUCESS __m128 _mm_maskz_reduce_ss(__mmask16 k, __m128 a, __m128 b, int imm, int sae)

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VRNDSCALEPD
description:
VRNDSCALEPD-Round Packed Float64 Values To Include A Given Number Of Fraction Bits
 Opcode/                           Op /   64/32        CPUID         Description
 Instruction                       En     bit Mode     Feature
                                          Support      Flag
 EVEX.128.66.0F3A.W1 09 /r ib      FV     V/V          AVX512VL      Rounds packed double-precision floating point values in
 VRNDSCALEPD xmm1 {k1}{z},                             AVX512F       xmm2/m128/m64bcst to a number of fraction bits
 xmm2/m128/m64bcst, imm8                                             specified by the imm8 field. Stores the result in xmm1
                                                                     register. Under writemask.
 EVEX.256.66.0F3A.W1 09 /r ib      FV     V/V          AVX512VL      Rounds packed double-precision floating point values in
 VRNDSCALEPD ymm1 {k1}{z},                             AVX512F       ymm2/m256/m64bcst to a number of fraction bits
 ymm2/m256/m64bcst, imm8                                             specified by the imm8 field. Stores the result in ymm1
                                                                     register. Under writemask.
 EVEX.512.66.0F3A.W1 09 /r ib      FV     V/V          AVX512F       Rounds packed double-precision floating-point values in
 VRNDSCALEPD zmm1 {k1}{z},                                           zmm2/m512/m64bcst to a number of fraction bits
 zmm2/m512/m64bcst{sae}, imm8                                        specified by the imm8 field. Stores the result in zmm1
                                                                     register using writemask k1.



                                            Instruction Operand Encoding
       Op/En              Operand 1                   Operand 2                    Operand 3                  Operand 4
        FV              ModRM:reg (w)                ModRM:r/m (r)                   Imm8                         NA

Description
Round the double-precision floating-point values in the source operand by the rounding mode specified in the
immediate operand (see Figure 5-29) and places the result in the destination operand.
The destination operand (the first operand) is a ZMM/YMM/XMM register conditionally updated according to the
writemask. The source operand (the second operand) can be a ZMM/YMM/XMM register, a 512/256/128-bit
memory location, or a 512/256/128-bit vector broadcasted from a 64-bit memory location.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the "Immediate Control Description" figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.
The formula of the operation on each data element for VRNDSCALEPD is
    ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
    round_ctrl = imm[3:0];
    M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).





VRNDSCALEPD is a more general form of the VEX-encoded VROUNDPD instruction. In VROUNDPD, the formula of
the operation on each element is
    ROUND(x) = Round_to_INT(x, round_ctrl),
    round_ctrl = imm[3:0];


Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.



                        7                 6                 5              4                 3              2                1                0

    imm8                                  Fixed point length                               SPE             RS               Round Control Override



                                                                Suppress Precision Exception: Imm8[3]                                        Imm8[1:0] = 00b : Round nearest even
                                                                Imm8[3] = 0b : Use MXCSR exception mask   Round Select: Imm8[2]
           Imm8[7:4] : Number of fixed points to preserve                                                                                    Imm8[1:0] = 01b : Round down
                                                                Imm8[3] = 1b : Suppress                   Imm8[2] = 0b : Use Imm8[1:0]
                                                                                                                                             Imm8[1:0] = 10b : Round up
                                                                                                          Imm8[2] = 1b : Use MXCSR
                                                                                                                                             Imm8[1:0] = 11b : Truncate



                                              Figure 5-29. Imm8 Controls for VRNDSCALEPD/SD/PS/SS


Handling of special case of input values are listed in Table 5-22.

                                                   Table 5-22. VRNDSCALEPD/SD/PS/SS Special Cases
                                                                                   Returned value
Src1=+-inf                                                                          Src1
Src1=+-NAN                                                                          Src1 converted to QNAN
Src1=+-0                                                                            Src1





Operation
RoundToIntegerDP(SRC[63:0], imm8[7:0]) {
   if (imm8[2] = 1)
         rounding_direction <- MXCSR:RC          ; get round control from MXCSR
   else
         rounding_direction <- imm8[1:0]         ; get round control from imm8[1:0]
   FI
   M <- imm8[7:4]           ; get the scaling factor

    case (rounding_direction)
    00: TMP[63:0] <- round_to_nearest_even_integer(2M*SRC[63:0])
    01: TMP[63:0] <- round_to_equal_or_smaller_integer(2M*SRC[63:0])
    10: TMP[63:0] <- round_to_equal_or_larger_integer(2M*SRC[63:0])
    11: TMP[63:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])
    ESAC

    Dest[63:0] <- 2-M* TMP[63:0]             ; scale down back to 2-M

    if (imm8[3] = 0) Then ; check SPE
          if (SRC[63:0] != Dest[63:0]) Then       ; check precision lost
                set_precision()             ; set #PE
          FI;
    FI;
    return(Dest[63:0])
}





VRNDSCALEPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF *src is a memory operand*
    THEN TMP_SRC <- BROADCAST64(SRC, VL, k1)
    ELSE TMP_SRC <- SRC
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- RoundToIntegerDP((TMP_SRC[i+63:i], imm8[7:0])
   ELSE
        IF *merging-masking*                ; merging-masking
             THEN *DEST[i+63:i] remains unchanged*
             ELSE                           ; zeroing-masking
                  DEST[i+63:i] <- 0
        FI;
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0



Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALEPD __m512d _mm512_roundscale_pd( __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_roundscale_round_pd( __m512d a, int imm, int sae);
VRNDSCALEPD __m512d _mm512_mask_roundscale_pd(__m512d s, __mmask8 k, __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_mask_roundscale_round_pd(__m512d s, __mmask8 k, __m512d a, int imm, int sae);
VRNDSCALEPD __m512d _mm512_maskz_roundscale_pd( __mmask8 k, __m512d a, int imm);
VRNDSCALEPD __m512d _mm512_maskz_roundscale_round_pd( __mmask8 k, __m512d a, int imm, int sae);
VRNDSCALEPD __m256d _mm256_roundscale_pd( __m256d a, int imm);
VRNDSCALEPD __m256d _mm256_mask_roundscale_pd(__m256d s, __mmask8 k, __m256d a, int imm);
VRNDSCALEPD __m256d _mm256_maskz_roundscale_pd( __mmask8 k, __m256d a, int imm);
VRNDSCALEPD __m128d _mm_roundscale_pd( __m128d a, int imm);
VRNDSCALEPD __m128d _mm_mask_roundscale_pd(__m128d s, __mmask8 k, __m128d a, int imm);
VRNDSCALEPD __m128d _mm_maskz_roundscale_pd( __mmask8 k, __m128d a, int imm);

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VRNDSCALESD
description:
VRNDSCALESD-Round Scalar Float64 Value To Include A Given Number Of Fraction Bits
 Opcode/                                Op /   64/32       CPUID        Description
 Instruction                            En     bit Mode    Feature
                                               Support     Flag
 EVEX.NDS.LIG.66.0F3A.W1 0B /r ib       T1S    V/V         AVX512F      Rounds scalar double-precision floating-point value in
 VRNDSCALESD xmm1 {k1}{z}, xmm2,                                        xmm3/m64 to a number of fraction bits specified by the
 xmm3/m64{sae}, imm8                                                    imm8 field. Stores the result in xmm1 register.



                                               Instruction Operand Encoding
       Op/En              Operand 1                  Operand 2                     Operand 3                    Operand 4
        T1S             ModRM:reg (w)               EVEX.vvvv (r)                ModRM:r/m (r)                    Imm8

Description
Rounds a double-precision floating-point value in the low quadword (see Figure 5-29) element the second source
operand (the third operand) by the rounding mode specified in the immediate operand and places the result in the
corresponding element of the destination operand (the third operand) according to the writemask. The quadword
element at bits 127:64 of the destination is copied from the first source operand (the second operand).
The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or
memory location. Bits MAX_VL-1:128 of the destination register are cleared.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a double-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the "Immediate Control Description" figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.


The formula of the operation for VRNDSCALESD is
    ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
    round_ctrl = imm[3:0];
    M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALESD is a more general form of the VEX-encoded VROUNDSD instruction. In VROUNDSD, the formula of
the operation is
    ROUND(x) = Round_to_INT(x, round_ctrl),
    round_ctrl = imm[3:0];


EVEX encoded version: The source operand is a XMM register or a 64-bit memory location. The destination operand
is a XMM register.
Handling of special case of input values are listed in Table 5-22.





Operation
RoundToIntegerDP(SRC[63:0], imm8[7:0]) {
   if (imm8[2] = 1)
         rounding_direction <- MXCSR:RC          ; get round control from MXCSR
   else
         rounding_direction <- imm8[1:0]         ; get round control from imm8[1:0]
   FI
   M <- imm8[7:4]           ; get the scaling factor

    case (rounding_direction)
    00: TMP[63:0] <- round_to_nearest_even_integer(2M*SRC[63:0])
    01: TMP[63:0] <- round_to_equal_or_smaller_integer(2M*SRC[63:0])
    10: TMP[63:0] <- round_to_equal_or_larger_integer(2M*SRC[63:0])
    11: TMP[63:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[63:0])
    ESAC

    Dest[63:0] <- 2-M* TMP[63:0]             ; scale down back to 2-M

    if (imm8[3] = 0) Then ; check SPE
          if (SRC[63:0] != Dest[63:0]) Then       ; check precision lost
                set_precision()             ; set #PE
          FI;
    FI;
    return(Dest[63:0])
}

VRNDSCALESD (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- RoundToIntegerDP(SRC2[63:0], Zero_upper_imm[7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALESD __m128d _mm_roundscale_sd ( __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_roundscale_round_sd ( __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_mask_roundscale_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_mask_roundscale_round_sd (__m128d s, __mmask8 k, __m128d a, __m128d b, int imm, int sae);
VRNDSCALESD __m128d _mm_maskz_roundscale_sd ( __mmask8 k, __m128d a, __m128d b, int imm);
VRNDSCALESD __m128d _mm_maskz_roundscale_round_sd ( __mmask8 k, __m128d a, __m128d b, int imm, int sae);

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E3.




platform: x86_64
mnem: VRNDSCALEPS
description:
VRNDSCALEPS-Round Packed Float32 Values To Include A Given Number Of Fraction Bits
 Opcode/                               Op /   64/32         CPUID          Description
 Instruction                           En     bit Mode      Feature
                                              Support       Flag
 EVEX.128.66.0F3A.W0 08 /r ib          FV     V/V           AVX512VL       Rounds packed single-precision floating point values in
 VRNDSCALEPS xmm1 {k1}{z},                                  AVX512F        xmm2/m128/m32bcst to a number of fraction bits
 xmm2/m128/m32bcst, imm8                                                   specified by the imm8 field. Stores the result in xmm1
                                                                           register. Under writemask.
 EVEX.256.66.0F3A.W0 08 /r ib          FV     V/V           AVX512VL       Rounds packed single-precision floating point values in
 VRNDSCALEPS ymm1 {k1}{z},                                  AVX512F        ymm2/m256/m32bcst to a number of fraction bits
 ymm2/m256/m32bcst, imm8                                                   specified by the imm8 field. Stores the result in ymm1
                                                                           register. Under writemask.
 EVEX.512.66.0F3A.W0 08 /r ib          FV     V/V           AVX512F        Rounds packed single-precision floating-point values in
 VRNDSCALEPS zmm1 {k1}{z},                                                 zmm2/m512/m32bcst to a number of fraction bits
 zmm2/m512/m32bcst{sae}, imm8                                              specified by the imm8 field. Stores the result in zmm1
                                                                           register using writemask.



                                              Instruction Operand Encoding
      Op/En              Operand 1                     Operand 2                      Operand 3                    Operand 4
        FV             ModRM:reg (w)                 ModRM:r/m (r)                       Imm8                         NA

Description
Round the single-precision floating-point values in the source operand by the rounding mode specified in the imme-
diate operand (see Figure 5-29) and places the result in the destination operand.
The destination operand (the first operand) is a ZMM register conditionally updated according to the writemask.
The source operand (the second operand) can be a ZMM register, a 512-bit memory location, or a 512-bit vector
broadcasted from a 32-bit memory location.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the "Immediate Control Description" figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control table below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.


The formula of the operation on each data element for VRNDSCALEPS is
    ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
    round_ctrl = imm[3:0];
    M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALEPS is a more general form of the VEX-encoded VROUNDPS instruction. In VROUNDPS, the formula of
the operation on each element is
    ROUND(x) = Round_to_INT(x, round_ctrl),
    round_ctrl = imm[3:0];




Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
Handling of special case of input values are listed in Table 5-22.



Operation
RoundToIntegerSP(SRC[31:0], imm8[7:0]) {
   if (imm8[2] = 1)
         rounding_direction <- MXCSR:RC          ; get round control from MXCSR
   else
         rounding_direction <- imm8[1:0]         ; get round control from imm8[1:0]
   FI
   M <- imm8[7:4]           ; get the scaling factor

    case (rounding_direction)
    00: TMP[31:0] <- round_to_nearest_even_integer(2M*SRC[31:0])
    01: TMP[31:0] <- round_to_equal_or_smaller_integer(2M*SRC[31:0])
    10: TMP[31:0] <- round_to_equal_or_larger_integer(2M*SRC[31:0])
    11: TMP[31:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])
    ESAC;

    Dest[31:0] <- 2-M* TMP[31:0]               ; scale down back to 2-M
    if (imm8[3] = 0) Then         ; check SPE
          if (SRC[31:0] != Dest[31:0]) Then         ; check precision lost
                set_precision()         ; set #PE
          FI;
    FI;
    return(Dest[31:0])
}

VRNDSCALEPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF *src is a memory operand*
    THEN TMP_SRC <- BROADCAST32(SRC, VL, k1)
    ELSE TMP_SRC <- SRC
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- RoundToIntegerSP(TMP_SRC[i+31:i]), imm8[7:0])
   ELSE
        IF *merging-masking*                ; merging-masking
             THEN *DEST[i+31:i] remains unchanged*
             ELSE                           ; zeroing-masking
                  DEST[i+31:i] <- 0
        FI;
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALEPS __m512 _mm512_roundscale_ps( __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_roundscale_round_ps( __m512 a, int imm, int sae);
VRNDSCALEPS __m512 _mm512_mask_roundscale_ps(__m512 s, __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_mask_roundscale_round_ps(__m512 s, __mmask16 k, __m512 a, int imm, int sae);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_ps( __mmask16 k, __m512 a, int imm);
VRNDSCALEPS __m512 _mm512_maskz_roundscale_round_ps( __mmask16 k, __m512 a, int imm, int sae);
VRNDSCALEPS __m256 _mm256_roundscale_ps( __m256 a, int imm);
VRNDSCALEPS __m256 _mm256_mask_roundscale_ps(__m256 s, __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m256 _mm256_maskz_roundscale_ps( __mmask8 k, __m256 a, int imm);
VRNDSCALEPS __m128 _mm_roundscale_ps( __m256 a, int imm);
VRNDSCALEPS __m128 _mm_mask_roundscale_ps(__m128 s, __mmask8 k, __m128 a, int imm);
VRNDSCALEPS __m128 _mm_maskz_roundscale_ps( __mmask8 k, __m128 a, int imm);

SIMD Floating-Point Exceptions

Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VRNDSCALESS
description:
VRNDSCALESS-Round Scalar Float32 Value To Include A Given Number Of Fraction Bits
 Opcode/                                    Op /    64/32        CPUID         Description
 Instruction                                En      bit Mode     Feature
                                                    Support      Flag
 EVEX.NDS.LIG.66.0F3A.W0 0A /r ib           T1S     V/V          AVX512F       Rounds scalar single-precision floating-point value in
 VRNDSCALESS xmm1 {k1}{z}, xmm2,                                               xmm3/m32 to a number of fraction bits specified by the
 xmm3/m32{sae}, imm8                                                           imm8 field. Stores the result in xmm1 register under
                                                                               writemask.



                                                   Instruction Operand Encoding
      Op/En                Operand 1                      Operand 2                    Operand 3                   Operand 4
       T1S               ModRM:reg (w)                  EVEX.vvvv (r)                ModRM:r/m (r)                     NA

Description
Rounds the single-precision floating-point value in the low doubleword element of the second source operand (the
third operand) by the rounding mode specified in the immediate operand (see Figure 5-29) and places the result in
the corresponding element of the destination operand (the first operand) according to the writemask. The double-
word elements at bits 127:32 of the destination are copied from the first source operand (the second operand).
The destination and first source operands are XMM registers, the 2nd source operand can be an XMM register or
memory location. Bits MAX_VL-1:128 of the destination register are cleared.
The rounding process rounds the input to an integral value, plus number bits of fraction that are specified by
imm8[7:4] (to be included in the result) and returns the result as a single-precision floating-point value.
It should be noticed that no overflow is induced while executing this instruction (although the source is scaled by
the imm8[7:4] value).
The immediate operand also specifies control fields for the rounding operation, three bit fields are defined and
shown in the "Immediate Control Description" figure below. Bit 3 of the immediate byte controls the processor
behavior for a precision exception, bit 2 selects the source of rounding mode control. Bits 1:0 specify a non-sticky
rounding-mode value (Immediate control tables below lists the encoded values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
The sign of the result of this instruction is preserved, including the sign of zero.


The formula of the operation for VRNDSCALESS is
    ROUND(x) = 2-M*Round_to_INT(x*2M, round_ctrl),
    round_ctrl = imm[3:0];
    M=imm[7:4];
The operation of x*2M is computed as if the exponent range is unlimited (i.e. no overflow ever occurs).
VRNDSCALESS is a more general form of the VEX-encoded VROUNDSS instruction. In VROUNDSS, the formula of
the operation on each element is
    ROUND(x) = Round_to_INT(x, round_ctrl),
    round_ctrl = imm[3:0];


EVEX encoded version: The source operand is a XMM register or a 32-bit memory location. The destination operand
is a XMM register.
Handling of special case of input values are listed in Table 5-22.





Operation
RoundToIntegerSP(SRC[31:0], imm8[7:0]) {
   if (imm8[2] = 1)
         rounding_direction <- MXCSR:RC          ; get round control from MXCSR
   else
         rounding_direction <- imm8[1:0]         ; get round control from imm8[1:0]
   FI
   M <- imm8[7:4]           ; get the scaling factor

    case (rounding_direction)
    00: TMP[31:0] <- round_to_nearest_even_integer(2M*SRC[31:0])
    01: TMP[31:0] <- round_to_equal_or_smaller_integer(2M*SRC[31:0])
    10: TMP[31:0] <- round_to_equal_or_larger_integer(2M*SRC[31:0])
    11: TMP[31:0] <- round_to_nearest_smallest_magnitude_integer(2M*SRC[31:0])
    ESAC;

    Dest[31:0] <- 2-M* TMP[31:0]               ; scale down back to 2-M
    if (imm8[3] = 0) Then         ; check SPE
          if (SRC[31:0] != Dest[31:0]) Then         ; check precision lost
                set_precision()         ; set #PE
          FI;
    FI;
    return(Dest[31:0])
}

VRNDSCALESS (EVEX encoded version)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- RoundToIntegerSP(SRC2[31:0], Zero_upper_imm[7:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VRNDSCALESS __m128 _mm_roundscale_ss ( __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_roundscale_round_ss ( __m128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_mask_roundscale_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_mask_roundscale_round_ss (__m128 s, __mmask8 k, __m128 a, __m128 b, int imm, int sae);
VRNDSCALESS __m128 _mm_maskz_roundscale_ss ( __mmask8 k, __m128 a, __m128 b, int imm);
VRNDSCALESS __m128 _mm_maskz_roundscale_round_ss ( __mmask8 k, __m128 a, __m128 b, int imm, int sae);

SIMD Floating-Point Exceptions
Invalid, Precision
If SPE is enabled, precision exception is not reported (regardless of MXCSR exception mask).

Other Exceptions
See Exceptions Type E3.





platform: x86_64
mnem: VRSQRT14PD
description:
VRSQRT14PD-Compute Approximate Reciprocals of Square Roots of Packed Float64 Values
 Opcode/                                Op /   64/32       CPUID          Description
 Instruction                            En     bit Mode    Feature
                                               Support     Flag
 EVEX.128.66.0F38.W1 4E /r              FV     V/V         AVX512VL       Computes the approximate reciprocal square roots of the
 VRSQRT14PD xmm1 {k1}{z},                                  AVX512F        packed double-precision floating-point values in
 xmm2/m128/m64bcst                                                        xmm2/m128/m64bcst and stores the results in xmm1.
                                                                          Under writemask.
 EVEX.256.66.0F38.W1 4E /r              FV     V/V         AVX512VL       Computes the approximate reciprocal square roots of the
 VRSQRT14PD ymm1 {k1}{z},                                  AVX512F        packed double-precision floating-point values in
 ymm2/m256/m64bcst                                                        ymm2/m256/m64bcst and stores the results in ymm1.
                                                                          Under writemask.
 EVEX.512.66.0F38.W1 4E /r              FV     V/V         AVX512F        Computes the approximate reciprocal square roots of the
 VRSQRT14PD zmm1 {k1}{z},                                                 packed double-precision floating-point values in
 zmm2/m512/m64bcst                                                        zmm2/m512/m64bcst and stores the results in zmm1
                                                                          under writemask.



                                                  Instruction Operand Encoding
      Op/En                 Operand 1                     Operand 2                     Operand 3                Operand 4
        FV                ModRM:reg (w)                ModRM:r/m (r)                       NA                       NA

Description
This instruction performs a SIMD computation of the approximate reciprocals of the square roots of the eight
packed double-precision floating-point values in the source operand (the second operand) and stores the packed
double-precision floating-point results in the destination operand (the first operand) according to the writemask.
The maximum relative error for this approximation is less than 2-14.
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location, or a 512-bit
vector broadcasted from a 64-bit memory location. The destination operand is a ZMM register, conditionally
updated using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 64-bit memory location. The destination operand is a YMM register, conditionally updated using
writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 64-bit memory location. The destination operand is a XMM register, conditionally updated using
writemask k1.
The VRSQRT14PD instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.





Operation
VRSQRT14PD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+63:i] <- APPROXIMATE(1.0/ SQRT(SRC[63:0]));
                    ELSE DEST[i+63:i] <- APPROXIMATE(1.0/ SQRT(SRC[i+63:i]));
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+63:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+63:i] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

                                            Table 5-23. VRSQRT14PD Special Cases
                         Input value         Result value         Comments
                         Any denormal        Normal               Cannot generate overflow
                               -2n               n
                         X=2                 2
                         X<0                 QNaN_Indefinite      Including -INF
                         X = -0              -INF
                         X = +0              +INF
                         X = +INF            +0

Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14PD __m512d _mm512_rsqrt14_pd( __m512d a);
VRSQRT14PD __m512d _mm512_mask_rsqrt14_pd(__m512d s, __mmask8 k, __m512d a);
VRSQRT14PD __m512d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m512d a);
VRSQRT14PD __m256d _mm256_rsqrt14_pd( __m256d a);
VRSQRT14PD __m256d _mm512_mask_rsqrt14_pd(__m256d s, __mmask8 k, __m256d a);
VRSQRT14PD __m256d _mm512_maskz_rsqrt14_pd( __mmask8 k, __m256d a);
VRSQRT14PD __m128d _mm_rsqrt14_pd( __m128d a);
VRSQRT14PD __m128d _mm_mask_rsqrt14_pd(__m128d s, __mmask8 k, __m128d a);
VRSQRT14PD __m128d _mm_maskz_rsqrt14_pd( __mmask8 k, __m128d a);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E4.






platform: x86_64
mnem: VRSQRT14SD
description:
VRSQRT14SD-Compute Approximate Reciprocal of Square Root of Scalar Float64 Value
 Opcode/                                Op /   64/32         CPUID        Description
 Instruction                            En     bit Mode      Feature
                                               Support       Flag
 EVEX.NDS.LIG.66.0F38.W1 4F /r          T1S    V/V           AVX512F      Computes the approximate reciprocal square root of the
 VRSQRT14SD xmm1 {k1}{z},                                                 scalar double-precision floating-point value in xmm3/m64
 xmm2, xmm3/m64                                                           and stores the result in the low quadword element of xmm1
                                                                          using writemask k1. Bits[127:64] of xmm2 is copied to
                                                                          xmm1[127:64].



                                                  Instruction Operand Encoding
       Op/En                 Operand 1                     Operand 2                     Operand 3                   Operand 4
        T1S                ModRM:reg (w)                  EVEX.vvvv (r)                 ModRM:r/m (r)                   NA

Description
Computes the approximate reciprocal of the square roots of the scalar double-precision floating-point value in the
low quadword element of the source operand (the second operand) and stores the result in the low quadword
element of the destination operand (the first operand) according to the writemask. The maximum relative error for
this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The
destination operand is an XMM register.
Bits (127:64) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
The VRSQRT14SD instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT14SD (EVEX version)
IF k1[0] or *no writemask*
    THEN      DEST[63:0] <- APPROXIMATE(1.0/ SQRT(SRC2[63:0]))
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[63:0] <- 0
         FI;
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0





                                            Table 5-24. VRSQRT14SD Special Cases
                         Input value         Result value      Comments
                         Any denormal        Normal            Cannot generate overflow
                         X=   2-2n           2   n

                         X<0                 QNaN_Indefinite   Including -INF
                         X = -0              -INF
                         X = +0              +INF
                         X = +INF            +0

Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SD __m128d _mm_rsqrt14_sd( __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_mask_rsqrt14_sd(__m128d s, __mmask8 k, __m128d a, __m128d b);
VRSQRT14SD __m128d _mm_maskz_rsqrt14_sd( __mmask8d m, __m128d a, __m128d b);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E5.






platform: x86_64
mnem: VRSQRT14PS
description:
VRSQRT14PS-Compute Approximate Reciprocals of Square Roots of Packed Float32 Values
 Opcode/                             Op /    64/32        CPUID         Description
 Instruction                         En      bit Mode     Feature
                                             Support      Flag
 EVEX.128.66.0F38.W0 4E /r           FV      V/V          AVX512VL      Computes the approximate reciprocal square roots of the
 VRSQRT14PS xmm1 {k1}{z},                                 AVX512F       packed single-precision floating-point values in
 xmm2/m128/m32bcst                                                      xmm2/m128/m32bcst and stores the results in xmm1.
                                                                        Under writemask.
 EVEX.256.66.0F38.W0 4E /r           FV      V/V          AVX512VL      Computes the approximate reciprocal square roots of the
 VRSQRT14PS ymm1 {k1}{z},                                 AVX512F       packed single-precision floating-point values in
 ymm2/m256/m32bcst                                                      ymm2/m256/m32bcst and stores the results in ymm1.
                                                                        Under writemask.
 EVEX.512.66.0F38.W0 4E /r           FV      V/V          AVX512F       Computes the approximate reciprocal square roots of the
 VRSQRT14PS zmm1 {k1}{z},                                               packed single-precision floating-point values in
 zmm2/m512/m32bcst                                                      zmm2/m512/m32bcst and stores the results in zmm1. Under
                                                                        writemask.



                                                   Instruction Operand Encoding
       Op/En                 Operand 1                    Operand 2                   Operand 3                Operand 4
         FV                ModRM:reg (w)                ModRM:r/m (r)                    NA                       NA

Description
This instruction performs a SIMD computation of the approximate reciprocals of the square roots of 16 packed
single-precision floating-point values in the source operand (the second operand) and stores the packed single-
precision floating-point results in the destination operand (the first operand) according to the writemask. The
maximum relative error for this approximation is less than 2-14.
EVEX.512 encoded version: The source operand can be a ZMM register, a 512-bit memory location or a 512-bit
vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally
updated using writemask k1.
EVEX.256 encoded version: The source operand is a YMM register, a 256-bit memory location, or a 256-bit vector
broadcasted from a 32-bit memory location. The destination operand is a YMM register, conditionally updated using
writemask k1.
EVEX.128 encoded version: The source operand is a XMM register, a 128-bit memory location, or a 128-bit vector
broadcasted from a 32-bit memory location. The destination operand is a XMM register, conditionally updated using
writemask k1.
The VRSQRT14PS instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an inf with the sign of the source value is returned. When the source operand is an +inf then +ZERO
value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR. Otherwise it is treated
correctly and performs the approximation with the specified masked response. When a source value is a negative
value (other than 0.0) a floating-point QNaN_indefinite is returned. When a source value is an SNaN or QNaN, the
SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
Note: EVEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.





Operation
VRSQRT14PS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+31:i] <- APPROXIMATE(1.0/ SQRT(SRC[31:0]));
                    ELSE DEST[i+31:i] <- APPROXIMATE(1.0/ SQRT(SRC[i+31:i]));
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+31:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+31:i] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0



                                            Table 5-25. VRSQRT14PS Special Cases
                         Input value         Result value         Comments
                         Any denormal        Normal               Cannot generate overflow
                               -2n               n
                         X=2                 2
                         X<0                 QNaN_Indefinite      Including -INF
                         X = -0              -INF
                         X = +0              +INF
                         X = +INF            +0

Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14PS __m512 _mm512_rsqrt14_ps( __m512 a);
VRSQRT14PS __m512 _mm512_mask_rsqrt14_ps(__m512 s, __mmask16 k, __m512 a);
VRSQRT14PS __m512 _mm512_maskz_rsqrt14_ps( __mmask16 k, __m512 a);
VRSQRT14PS __m256 _mm256_rsqrt14_ps( __m256 a);
VRSQRT14PS __m256 _mm256_mask_rsqrt14_ps(__m256 s, __mmask8 k, __m256 a);
VRSQRT14PS __m256 _mm256_maskz_rsqrt14_ps( __mmask8 k, __m256 a);
VRSQRT14PS __m128 _mm_rsqrt14_ps( __m128 a);
VRSQRT14PS __m128 _mm_mask_rsqrt14_ps(__m128 s, __mmask8 k, __m128 a);
VRSQRT14PS __m128 _mm_maskz_rsqrt14_ps( __mmask8 k, __m128 a);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: VRSQRT14SS
description:
VRSQRT14SS-Compute Approximate Reciprocal of Square Root of Scalar Float32 Value
 Opcode/                                Op /   64/32        CPUID         Description
 Instruction                            En     bit Mode     Feature
                                               Support      Flag
 EVEX.NDS.LIG.66.0F38.W0 4F /r          T1S    V/V          AVX512F       Computes the approximate reciprocal square root of the
 VRSQRT14SS xmm1 {k1}{z},                                                 scalar single-precision floating-point value in xmm3/m32
 xmm2, xmm3/m32                                                           and stores the result in the low doubleword element of
                                                                          xmm1 using writemask k1. Bits[127:32] of xmm2 is copied
                                                                          to xmm1[127:32].



                                                  Instruction Operand Encoding
       Op/En                Operand 1                     Operand 2                     Operand 3                Operand 4
        T1S               ModRM:reg (w)                   VEX.vvvv                  ModRM:r/m (r)                    NA

Description
Computes of the approximate reciprocal of the square root of the scalar single-precision floating-point value in the
low doubleword element of the source operand (the second operand) and stores the result in the low doubleword
element of the destination operand (the first operand) according to the writemask. The maximum relative error for
this approximation is less than 2-14. The source operand can be an XMM register or a 32-bit memory location. The
destination operand is an XMM register.
Bits (127:32) of the XMM register destination are copied from corresponding bits in the first source operand. Bits
(MAX_VL-1:128) of the destination register are zeroed.
The VRSQRT14SS instruction is not affected by the rounding control bits in the MXCSR register. When a source
value is a 0.0, an inf with the sign of the source value is returned. When the source operand is an inf, zero with the
sign of the source value is returned. A denormal source value is treated as zero only if DAZ bit is set in MXCSR.
Otherwise it is treated correctly and performs the approximation with the specified masked response. When a
source value is a negative value (other than 0.0) a floating-point indefinite is returned. When a source value is an
SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
MXCSR exception flags are not affected by this instruction and floating-point exceptions are not reported.
A numerically exact implementation of VRSQRT14xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT14SS (EVEX version)
IF k1[0] or *no writemask*
    THEN      DEST[31:0] <- APPROXIMATE(1.0/ SQRT(SRC2[31:0]))
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  THEN DEST[31:0] <- 0
         FI;
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0





                                            Table 5-26. VRSQRT14SS Special Cases
                         Input value         Result value      Comments
                         Any denormal        Normal            Cannot generate overflow
                         X=   2-2n           2   n

                         X<0                 QNaN_Indefinite   Including -INF
                         X = -0              -INF
                         X = +0              +INF
                         X = +INF            +0

Intel C/C++ Compiler Intrinsic Equivalent
VRSQRT14SS __m128 _mm_rsqrt14_ss( __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_mask_rsqrt14_ss(__m128 s, __mmask8 k, __m128 a, __m128 b);
VRSQRT14SS __m128 _mm_maskz_rsqrt14_ss( __mmask8 k, __m128 a, __m128 b);

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type E5.






platform: x86_64
mnem: VRSQRT28PD
description:
VRSQRT28PD-Approximation to the Reciprocal Square Root of Packed Double-Precision
Floating-Point Values with Less Than 2^-28 Relative Error
 Opcode/                            Op /    64/32         CPUID          Description
 Instruction                        En      bit Mode      Feature
                                            Support       Flag
 EVEX.512.66.0F38.W1 CC /r          FV      V/V           AVX512ER       Computes approximations to the Reciprocal square root (<2^-
 VRSQRT28PD zmm1 {k1}{z},                                                28 relative error) of the packed double-precision floating-point
 zmm2/m512/m64bcst {sae}                                                 values from zmm2/m512/m64bcst and stores result in
                                                                         zmm1with writemask k1.



                                                    Instruction Operand Encoding
    Op/En               Operand 1                       Operand 2                      Operand 3                        Operand 4
     FV               ModRM:reg (w)                    ModRM:r/m (r)                       NA                                  NA

Description
Computes the reciprocal square root of the float64 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error.
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -inf and set the DivByZero flag.
The source operand is a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 64-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT28PD (EVEX encoded versions)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC *is memory*)
                    THEN DEST[i+63:i] <- (1.0/ SQRT(SRC[63:0]));
                    ELSE DEST[i+63:i] <- (1.0/ SQRT(SRC[i+63:i]));
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[i+63:i] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[i+63:i] <- 0
         FI;
    FI;
ENDFOR;





                                              Table 5-27. VRSQRT28PD Special Cases
                Input value                      Result value                Comments
                NAN                              QNAN(input)                 If (SRC = SNaN) then #I
                X=   2-2n                        2n

                X<0                              QNaN_Indefinite             Including -INF
                X = -0 or negative denormal      -INF                        #Z
                X = +0 or positive denormal      +INF                        #Z
                X = +INF                         +0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PD __m512d _mm512_rsqrt28_round_pd(__m512d a, int sae);
VRSQRT28PD __m512d _mm512_mask_rsqrt28_round_pd(__m512d s, __mmask8 m,__m512d a, int sae);
VRSQRT28PD __m512d _mm512_maskz_rsqrt28_round_pd(__mmask8 m,__m512d a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E2.






platform: x86_64
mnem: VRSQRT28SD
description:
VRSQRT28SD-Approximation to the Reciprocal Square Root of Scalar Double-Precision
Floating-Point Value with Less Than 2^-28 Relative Error
 Opcode/                                 Op /    64/32         CPUID           Description
 Instruction                             En      bit Mode      Feature
                                                 Support       Flag
 EVEX.NDS.LIG.66.0F38.W1 CD /r           T1S     V/V           AVX512ER        Computes approximate reciprocal square root (<2^-28
 VRSQRT28SD xmm1 {k1}{z},                                                      relative error) of the scalar double-precision floating-point
 xmm2, xmm3/m64 {sae}                                                          value from xmm3/m64 and stores result in xmm1with
                                                                               writemask k1. Also, upper double-precision floating-point
                                                                               value (bits[127:64]) from xmm2 is copied to
                                                                               xmm1[127:64].



                                                    Instruction Operand Encoding
    Op/En                Operand 1                      Operand 2                       Operand 3                       Operand 4
     T1S               ModRM:reg (w)                   EVEX.vvvv (r)                  ModRM:r/m (r)                           NA

Description
Computes the reciprocal square root of the low float64 value in the second source operand (the third operand) and
store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated
with less than 2^-28 of maximum relative error. The result is written into the low float64 element of xmm1
according to the writemask k1. Bits 127:64 of the destination is copied from the corresponding bits of the first source operand
(the second operand).
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -inf and set the DivByZero flag.
The first source operand is an XMM register. The second source operand is an XMM register or a 64-bit memory
location. The destination operand is a XMM register.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT28SD (EVEX encoded versions)
   IF k1[0] OR *no writemask* THEN
             DEST[63: 0] <- (1.0/ SQRT(SRC[63: 0]));
   ELSE
        IF *merging-masking*               ; merging-masking
             THEN *DEST[63: 0] remains unchanged*
             ELSE                          ; zeroing-masking
                 DEST[63: 0] <- 0
        FI;
   FI;
ENDFOR;
DEST[127:64] <- SRC1[127: 64]
DEST[MAX_VL-1:128] <- 0





                                              Table 5-28. VRSQRT28SD Special Cases
                Input value                       Result value                 Comments
                NAN                               QNAN(input)                  If (SRC = SNaN) then #I
                X=   2-2n                         2n

                X<0                               QNaN_Indefinite              Including -INF
                X = -0 or negative denormal       -INF                         #Z
                X = +0 or positive denormal       +INF                         #Z
                X = +INF                          +0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SD __m128d _mm_rsqrt28_round_sd(__m128d a, __m128b b, int sae);
VRSQRT28SD __m128d _mm_mask_rsqrt28_round_pd(__m128d s, __mmask8 m,__m128d a, __m128d b, int sae);
VRSQRT28SD __m128d _mm_maskz_rsqrt28_round_pd( __mmask8 m,__m128d a, __m128d b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E3.






platform: x86_64
mnem: VRSQRT28PS
description:
VRSQRT28PS-Approximation to the Reciprocal Square Root of Packed Single-Precision
Floating-Point Values with Less Than 2^-28 Relative Error
 Opcode/                               Op /    64/32        CPUID           Description
 Instruction                           En      bit Mode     Feature
                                               Support      Flag
 EVEX.512.66.0F38.W0 CC /r             FV      V/V          AVX512ER        Computes approximations to the Reciprocal square root
 VRSQRT28PS zmm1 {k1}{z},                                                   (<2^-28 relative error) of the packed single-precision
 zmm2/m512/m32bcst {sae}                                                    floating-point values from zmm2/m512/m32bcst and stores
                                                                            result in zmm1with writemask k1.



                                                    Instruction Operand Encoding
     Op/En               Operand 1                      Operand 2                       Operand 3                       Operand 4
      FV               ModRM:reg (w)                  ModRM:r/m (r)                         NA                                 NA

Description
Computes the reciprocal square root of the float32 values in the source operand (the second operand) and store
the results to the destination operand (the first operand). The approximate reciprocal is evaluated with less than
2^-28 of maximum relative error prior to final rounding. The final results is rounded to < 2^-23 relative error
before written to the destination.
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -inf and set the DivByZero flag.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit
memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT28PS (EVEX encoded versions)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
              IF (EVEX.b = 1) AND (SRC *is memory*)
                   THEN DEST[i+31:i] <- (1.0/ SQRT(SRC[31:0]));
                   ELSE DEST[i+31:i] <- (1.0/ SQRT(SRC[i+31:i]));
              FI;
    ELSE
         IF *merging-masking*                 ; merging-masking
              THEN *DEST[i+31:i] remains unchanged*
              ELSE                            ; zeroing-masking
                   DEST[i+31:i] <- 0
         FI;
    FI;
ENDFOR;





                                              Table 5-29. VRSQRT28PS Special Cases
                Input value                      Result value                 Comments
                NAN                              QNAN(input)                  If (SRC = SNaN) then #I
                X=   2-2n                        2 n

                X<0                              QNaN_Indefinite              Including -INF
                X = -0 or negative denormal      -INF                         #Z
                X = +0 or positive denormal      +INF                         #Z
                X = +INF                         +0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28PS __m512 _mm512_rsqrt28_round_ps(__m512 a, int sae);
VRSQRT28PS __m512 _mm512_mask_rsqrt28_round_ps(__m512 s, __mmask16 m,__m512 a, int sae);
VRSQRT28PS __m512 _mm512_maskz_rsqrt28_round_ps(__mmask16 m,__m512 a, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E2.






platform: x86_64
mnem: VRSQRT28SS
description:
VRSQRT28SS-Approximation to the Reciprocal Square Root of Scalar Single-Precision Floating-
Point Value with Less Than 2^-28 Relative Error
 Opcode/                                Op /     64/32         CPUID           Description
 Instruction                            En       bit Mode      Feature
                                                 Support       Flag
 EVEX.NDS.LIG.66.0F38.W0 CD /r          T1S      V/V           AVX512ER        Computes approximate reciprocal square root (<2^-28
 VRSQRT28SS xmm1 {k1}{z},                                                      relative error) of the scalar single-precision floating-point
 xmm2, xmm3/m32 {sae}                                                          value from xmm3/m32 and stores result in xmm1with
                                                                               writemask k1. Also, upper 3 single-precision floating-point
                                                                               value (bits[127:32]) from xmm2 is copied to
                                                                               xmm1[127:32].



                                                      Instruction Operand Encoding
     Op/En                Operand 1                       Operand 2                        Operand 3                        Operand 4
      T1S               ModRM:reg (w)                   EVEX.vvvv (r)                    ModRM:r/m (r)                             NA

Description
Computes the reciprocal square root of the low float32 value in the second source operand (the third operand) and
store the result to the destination operand (the first operand). The approximate reciprocal square root is evaluated
with less than 2^-28 of maximum relative error prior to final rounding. The final result is rounded to < 2^-23 rela-
tive error before written to the low float32 element of the destination according to the writemask k1. Bits 127:32 of
the destination is copied from the corresponding bits of the first source operand (the second operand).
If any source element is NaN, the quietized NaN source value is returned for that element. Negative (non-zero)
source numbers, as well as -inf, return the canonical NaN and set the Invalid Flag (#I).
A value of -0 must return -inf and set the DivByZero flags (#Z). Negative numbers should return NaN and set the
Invalid flag (#I). Note however that the instruction flush input denormals to zero of the same sign, so negative
denormals return -inf and set the DivByZero flag.
The first source operand is an XMM register. The second source operand is an XMM register or a 32-bit memory
location. The destination operand is a XMM register.
A numerically exact implementation of VRSQRT28xx can be found at https://software.intel.com/en-us/arti-
cles/reference-implementations-for-IA-approximation-instructions-vrcp14-vrsqrt14-vrcp28-vrsqrt28-vexp2.

Operation
VRSQRT28SS (EVEX encoded versions)
   IF k1[0] OR *no writemask* THEN
             DEST[31: 0] <- (1.0/ SQRT(SRC[31: 0]));
   ELSE
        IF *merging-masking*               ; merging-masking
             THEN *DEST[31: 0] remains unchanged*
             ELSE                          ; zeroing-masking
                 DEST[31: 0] <- 0
        FI;
   FI;
ENDFOR;
DEST[127:32] <- SRC1[127: 32]
DEST[MAX_VL-1:128] <- 0





                                             Table 5-30. VRSQRT28SS Special Cases
                Input value                      Result value                  Comments
                NAN                              QNAN(input)                   If (SRC = SNaN) then #I
                X=   2-2n                        2 n

                X<0                              QNaN_Indefinite               Including -INF
                X = -0 or negative denormal      -INF                          #Z
                X = +0 or positive denormal      +INF                          #Z
                X = +INF                         +0

Intel C/C++ Compiler Intrinsic Equivalent

VRSQRT28SS __m128 _mm_rsqrt28_round_ss(__m128 a, __m128 b, int sae);
VRSQRT28SS __m128 _mm512_mask_rsqrt28_round_ss(__m128 s, __mmask8 m,__m128 a,__m128 b, int sae);
VRSQRT28SS __m128 _mm512_maskz_rsqrt28_round_ss(__mmask8 m,__m128 a,__m128 b, int sae);

SIMD Floating-Point Exceptions

Invalid (if SNaN input), Divide-by-zero

Other Exceptions

See Exceptions Type E3.






platform: x86_64
mnem: VSCALEFPD
description:
VSCALEFPD-Scale Packed Float64 Values With Float64 Values
 Opcode/                                  Op /     64/32        CPUID          Description
 Instruction                              En       bit Mode     Feature
                                                   Support      Flag
 EVEX.NDS.128.66.0F38.W1 2C /r            FV       V/V          AVX512VL       Scale the packed double-precision floating-point values in
 VSCALEFPD xmm1 {k1}{z}, xmm2,                                  AVX512F        xmm2 using values from xmm3/m128/m64bcst. Under
 xmm3/m128/m64bcst                                                             writemask k1.
 EVEX.NDS.256.66.0F38.W1 2C /r            FV       V/V          AVX512VL       Scale the packed double-precision floating-point values in
 VSCALEFPD ymm1 {k1}{z}, ymm2,                                  AVX512F        ymm2 using values from ymm3/m256/m64bcst. Under
 ymm3/m256/m64bcst                                                             writemask k1.
 EVEX.NDS.512.66.0F38.W1 2C /r            FV       V/V          AVX512F        Scale the packed double-precision floating-point values in
 VSCALEFPD zmm1 {k1}{z}, zmm2,                                                 zmm2 using values from zmm3/m512/m64bcst. Under
 zmm3/m512/m64bcst{er}                                                         writemask k1.



                                                   Instruction Operand Encoding
       Op/En                 Operand 1                      Operand 2                   Operand 3                     Operand 4
         FV               ModRM:reg (w)                  EVEX.vvvv (r)                ModRM:r/m (r)                       NA

Description
Performs a floating-point scale of the packed double-precision floating-point values in the first source operand by
multiplying it by 2 power of the double-precision floating-point values in second source operand.
The equation of this operation is given by:
zmm1 := zmm2*2floor(zmm3).
Floor(zmm3) means maximum integer value <= zmm3.
If the result cannot be represented in double precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
The first source operand is a ZMM/YMM/XMM register. The second source operand is a ZMM/YMM/XMM register, a
512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a 64-bit memory location. The
destination operand is a ZMM/YMM/XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-31 and Table 5-32.


                                        Table 5-31. \VSCALEFPD/SD/PS/SS Special Cases

                                                                 Src2                                        Set IE
                           +-NaN             +Inf                  -Inf                 0/Denorm/Norm
  Src1    +-QNaN            QNaN(Src1)       +INF                  +0                   QNaN(Src1)            IF either source is SNAN
          +-SNaN            QNaN(Src1)       QNaN(Src1)            QNaN(Src1)           QNaN(Src1)            YES
          +-Inf             QNaN(Src2)       Src1                  QNaN_Indefinite      Src1                  IF Src2 is SNAN or -INF
          +-0               QNaN(Src2)       QNaN_Indefinite       Src1                 Src1                  IF Src2 is SNAN or +INF
          Denorm/Norm      QNaN(Src2)       +-INF (Src1 sign)       +-0 (Src1 sign)       Compute Result        IF Src2 is SNAN





                                     Table 5-32. Additional VSCALEFPD/SD Special Cases
 Special Case                        Returned value                                                      Faults
 |result| <   2-1074                +-0 or +-Min-Denormal (Src1 sign)                                      Underflow
                1024
 |result| >= 2                       +-INF (Src1 sign) or +-Max-normal (Src1 sign)                          Overflow

Operation
SCALE(SRC1, SRC2)
{
TMP_SRC2 <- SRC2
TMP_SRC1 <- SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
    /* SRC2 is a 64 bits floating-point value */
     DEST[63:0] <- TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))
}
VSCALEFPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- SCALE(SRC1[i+63:i], SRC2[63:0]);
                    ELSE DEST[i+63:i] <- SCALE(SRC1[i+63:i], SRC2[i+63:i]);
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFPD __m512d _mm512_scalef_round_pd(__m512d a, __m512d b, int);
VSCALEFPD __m512d _mm512_mask_scalef_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int);
VSCALEFPD __m512d _mm512_maskz_scalef_round_pd(__mmask8 k, __m512d a, __m512d b, int);
VSCALEFPD __m256d _mm256_scalef_round_pd(__m256d a, __m256d b, int);
VSCALEFPD __m256d _mm256_mask_scalef_round_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int);
VSCALEFPD __m256d _mm256_maskz_scalef_round_pd(__mmask8 k, __m256d a, __m256d b, int);
VSCALEFPD __m128d _mm_scalef_round_pd(__m128d a, __m128d b, int);
VSCALEFPD __m128d _mm_mask_scalef_round_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSCALEFPD __m128d _mm_maskz_scalef_round_pd(__mmask8 k, __m128d a, __m128d b, int);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.

Other Exceptions
See Exceptions Type E2.






platform: x86_64
mnem: VSCALEFSD
description:
VSCALEFSD-Scale Scalar Float64 Values With Float64 Values
 Opcode/                             Op /   64/32        CPUID     Description
 Instruction                         En     bit Mode     Feature
                                            Support      Flag
 EVEX.NDS.LIG.66.0F38.W1 2D /r       T1S    V/V          AVX512F   Scale the scalar double-precision floating-point values in
 VSCALEFSD xmm1 {k1}{z}, xmm2,                                     xmm2 using the value from xmm3/m64. Under writemask
 xmm3/m64{er}                                                      k1.



                                              Instruction Operand Encoding
      Op/En              Operand 1                     Operand 2                 Operand 3                   Operand 4
       T1S             ModRM:reg (w)               EVEX.vvvv (r)              ModRM:r/m (r)                      NA

Description
Performs a floating-point scale of the packed double-precision floating-point value in the first source operand by
multiplying it by 2 power of the double-precision floating-point value in second source operand.
The equation of this operation is given by:
xmm1 := xmm2*2floor(xmm3).
Floor(xmm3) means maximum integer value <= xmm3.
If the result cannot be represented in double precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register
or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-31 and Table 5-32.

Operation
SCALE(SRC1, SRC2)
{
    ; Check for denormal operands
TMP_SRC2 <- SRC2
TMP_SRC1 <- SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
    /* SRC2 is a 64 bits floating-point value */
    DEST[63:0] <- TMP_SRC1[63:0] * POW(2, Floor(TMP_SRC2[63:0]))
}





VSCALEFSD (EVEX encoded version)
IF (EVEX.b= 1) and SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] OR *no writemask*
    THEN DEST[63:0] <- SCALE(SRC1[63:0], SRC2[63:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[63:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[63:0] <- 0
         FI
FI;
DEST[127:64] <- SRC1[127:64]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFSD __m128d _mm_scalef_round_sd(__m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_mask_scalef_round_sd(__m128d s, __mmask8 k, __m128d a, __m128d b, int);
VSCALEFSD __m128d _mm_maskz_scalef_round_sd(__mmask8 k, __m128d a, __m128d b, int);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VSCALEFPS
description:
VSCALEFPS-Scale Packed Float32 Values With Float32 Values
 Opcode/                               Op /   64/32       CPUID         Description
 Instruction                           En     bit Mode    Feature
                                              Support     Flag
 EVEX.NDS.128.66.0F38.W0 2C /r         FV     V/V         AVX512VL      Scale the packed single-precision floating-point values in
 VSCALEFPS xmm1 {k1}{z}, xmm2,                            AVX512F       xmm2 using values from xmm3/m128/m32bcst. Under
 xmm3/m128/m32bcst                                                      writemask k1.
 EVEX.NDS.256.66.0F38.W0 2C /r         FV     V/V         AVX512VL      Scale the packed single-precision values in ymm2 using
 VSCALEFPS ymm1 {k1}{z}, ymm2,                            AVX512F       floating point values from ymm3/m256/m32bcst. Under
 ymm3/m256/m32bcst                                                      writemask k1.
 EVEX.NDS.512.66.0F38.W0 2C /r         FV     V/V         AVX512F       Scale the packed single-precision floating-point values in
 VSCALEFPS zmm1 {k1}{z}, zmm2,                                          zmm2 using floating-point values from
 zmm3/m512/m32bcst{er}                                                  zmm3/m512/m32bcst. Under writemask k1.



                                              Instruction Operand Encoding
       Op/En            Operand 1                    Operand 2                   Operand 3                      Operand 4
         FV            ModRM:reg (w)                EVEX.vvvv (r)              ModRM:r/m (r)                       NA

Description
Performs a floating-point scale of the packed single-precision floating-point values in the first source operand by
multiplying it by 2 power of the float32 values in second source operand.
The equation of this operation is given by:
zmm1 := zmm2*2floor(zmm3).
Floor(zmm3) means maximum integer value <= zmm3.


If the result cannot be represented in single precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand is a ZMM
register, a 512-bit memory location or a 512-bit vector broadcasted from a 32-bit memory location. The destination
operand is a ZMM register conditionally updated with writemask k1.
EVEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM
register, a 256-bit memory location, or a 256-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a YMM register, conditionally updated using writemask k1.
EVEX.128 encoded version: The first source operand is an XMM register. The second source operand is a XMM
register, a 128-bit memory location, or a 128-bit vector broadcasted from a 32-bit memory location. The destina-
tion operand is a XMM register, conditionally updated using writemask k1.
Handling of special-case input values are listed in Table 5-31 and Table 5-33.

                                 Table 5-33. Additional VSCALEFPS/SS Special Cases
 Special Case                    Returned value                                                        Faults
                -149
 |result| < 2                    +-0 or +-Min-Denormal (Src1 sign)                                       Underflow
 |result| >=   2128               +-INF (Src1 sign) or +-Max-normal (Src1 sign)                           Overflow





Operation
SCALE(SRC1, SRC2)
{             ; Check for denormal operands
TMP_SRC2 <- SRC2
TMP_SRC1 <- SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
    /* SRC2 is a 32 bits floating-point value */
    DEST[31:0] <- TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))
}

VSCALEFPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF (VL = 512) AND (EVEX.b = 1) AND (SRC2 *is register*)
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SCALE(SRC1[i+31:i], SRC2[31:0]);
                    ELSE DEST[i+31:i] <- SCALE(SRC1[i+31:i], SRC2[i+31:i]);
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE                           ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0;

Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFPS __m512 _mm512_scalef_round_ps(__m512 a, __m512 b, int);
VSCALEFPS __m512 _mm512_mask_scalef_round_ps(__m512 s, __mmask16 k, __m512 a, __m512 b, int);
VSCALEFPS __m512 _mm512_maskz_scalef_round_ps(__mmask16 k, __m512 a, __m512 b, int);
VSCALEFPS __m256 _mm256_scalef_round_ps(__m256 a, __m256 b, int);
VSCALEFPS __m256 _mm256_mask_scalef_round_ps(__m256 s, __mmask8 k, __m256 a, __m256 b, int);
VSCALEFPS __m256 _mm256_maskz_scalef_round_ps(__mmask8 k, __m256 a, __m256 b, int);
VSCALEFPS __m128 _mm_scalef_round_ps(__m128 a, __m128 b, int);
VSCALEFPS __m128 _mm_mask_scalef_round_ps(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSCALEFPS __m128 _mm_maskz_scalef_round_ps(__mmask8 k, __m128 a, __m128 b, int);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.

Other Exceptions
See Exceptions Type E2.




platform: x86_64
mnem: VSCALEFSS
description:
VSCALEFSS-Scale Scalar Float32 Value With Float32 Value
 Opcode/                            Op /   64/32        CPUID     Description
 Instruction                        En     bit Mode     Feature
                                           Support      Flag
 EVEX.NDS.LIG.66.0F38.W0 2D /r      T1S    V/V          AVX512F   Scale the scalar single-precision floating-point value in
 VSCALEFSS xmm1 {k1}{z}, xmm2,                                    xmm2 using floating-point value from xmm3/m32. Under
 xmm3/m32{er}                                                     writemask k1.



                                              Instruction Operand Encoding
      Op/En             Operand 1                     Operand 2                 Operand 3                  Operand 4
       T1S            ModRM:reg (w)               EVEX.vvvv (r)             ModRM:r/m (r)                      NA

Description
Performs a floating-point scale of the scalar single-precision floating-point value in the first source operand by
multiplying it by 2 power of the float32 value in second source operand.
The equation of this operation is given by:
xmm1 := xmm2*2floor(xmm3).
Floor(xmm3) means maximum integer value <= xmm3.


If the result cannot be represented in single precision, then the proper overflow response (for positive scaling
operand), or the proper underflow response (for negative scaling operand) is issued. The overflow and underflow
responses are dependent on the rounding mode (for IEEE-compliant rounding), as well as on other settings in
MXCSR (exception mask bits, FTZ bit), and on the SAE bit.
EVEX encoded version: The first source operand is an XMM register. The second source operand is an XMM register
or a memory location. The destination operand is an XMM register conditionally updated with writemask k1.
Handling of special-case input values are listed in Table 5-31 and Table 5-33.





Operation
SCALE(SRC1, SRC2)
{
              ; Check for denormal operands
TMP_SRC2 <- SRC2
TMP_SRC1 <- SRC1
IF (SRC2 is denormal AND MXCSR.DAZ) THEN TMP_SRC2=0
IF (SRC1 is denormal AND MXCSR.DAZ) THEN TMP_SRC1=0
    /* SRC2 is a 32 bits floating-point value */
    DEST[31:0] <- TMP_SRC1[31:0] * POW(2, Floor(TMP_SRC2[31:0]))
}

VSCALEFSS (EVEX encoded version)
IF (EVEX.b= 1) and SRC2 *is a register*
    THEN
         SET_RM(EVEX.RC);
    ELSE
         SET_RM(MXCSR.RM);
FI;
IF k1[0] OR *no writemask*
    THEN DEST[31:0] <- SCALE(SRC1[31:0], SRC2[31:0])
    ELSE
         IF *merging-masking*              ; merging-masking
              THEN *DEST[31:0] remains unchanged*
              ELSE                         ; zeroing-masking
                  DEST[31:0] <- 0
         FI
FI;
DEST[127:32] <- SRC1[127:32]
DEST[MAX_VL-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VSCALEFSS __m128 _mm_scalef_round_ss(__m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_mask_scalef_round_ss(__m128 s, __mmask8 k, __m128 a, __m128 b, int);
VSCALEFSS __m128 _mm_maskz_scalef_round_ss(__mmask8 k, __m128 a, __m128 b, int);

SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal (for Src1).
Denormal is not reported for Src2.

Other Exceptions
See Exceptions Type E3.






platform: x86_64
mnem: VSCATTERDPS
description:
VSCATTERDPS/VSCATTERDPD/VSCATTERQPS/VSCATTERQPD-Scatter Packed Single, Packed
Double with Signed Dword and Qword Indices
    Opcode/                               Op/E     64/32       CPUID         Description
    Instruction                           n        bit Mode    Feature
                                                   Support     Flag
    EVEX.128.66.0F38.W0 A2 /vsib          T1S      V/V         AVX512VL      Using signed dword indices, scatter single-precision
    VSCATTERDPS vm32x {k1}, xmm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.256.66.0F38.W0 A2 /vsib          T1S      V/V         AVX512VL      Using signed dword indices, scatter single-precision
    VSCATTERDPS vm32y {k1}, ymm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.512.66.0F38.W0 A2 /vsib          T1S      V/V         AVX512F       Using signed dword indices, scatter single-precision
    VSCATTERDPS vm32z {k1}, zmm1                                             floating-point values to memory using writemask k1.
    EVEX.128.66.0F38.W1 A2 /vsib          T1S      V/V         AVX512VL      Using signed dword indices, scatter double-precision
    VSCATTERDPD vm32x {k1}, xmm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.256.66.0F38.W1 A2 /vsib          T1S      V/V         AVX512VL      Using signed dword indices, scatter double-precision
    VSCATTERDPD vm32x {k1}, ymm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.512.66.0F38.W1 A2 /vsib          T1S      V/V         AVX512F       Using signed dword indices, scatter double-precision
    VSCATTERDPD vm32y {k1}, zmm1                                             floating-point values to memory using writemask k1.
    EVEX.128.66.0F38.W0 A3 /vsib          T1S      V/V         AVX512VL      Using signed qword indices, scatter single-precision
    VSCATTERQPS vm64x {k1}, xmm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.256.66.0F38.W0 A3 /vsib          T1S      V/V         AVX512VL      Using signed qword indices, scatter single-precision
    VSCATTERQPS vm64y {k1}, xmm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.512.66.0F38.W0 A3 /vsib          T1S      V/V         AVX512F       Using signed qword indices, scatter single-precision
    VSCATTERQPS vm64z {k1}, ymm1                                             floating-point values to memory using writemask k1.
    EVEX.128.66.0F38.W1 A3 /vsib          T1S      V/V         AVX512VL      Using signed qword indices, scatter double-precision
    VSCATTERQPD vm64x {k1}, xmm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.256.66.0F38.W1 A3 /vsib          T1S      V/V         AVX512VL      Using signed qword indices, scatter double-precision
    VSCATTERQPD vm64y {k1}, ymm1                               AVX512F       floating-point values to memory using writemask k1.
    EVEX.512.66.0F38.W1 A3 /vsib          T1S      V/V         AVX512F       Using signed qword indices, scatter double-precision
    VSCATTERQPD vm64z {k1}, zmm1                                             floating-point values to memory using writemask k1.



                                                 Instruction Operand Encoding
        Op/En               Operand 1                    Operand 2                 Operand 3                    Operand 4
                      BaseReg (R): VSIB:base,
         T1S                                          ModRM:reg (r)                    NA                           NA
                     VectorReg(R): VSIB:index

Description
Stores up to 16 elements (or 8 elements) in doubleword/quadword vector zmm1 to the memory locations pointed
by base address BASE_ADDR and index vector VINDEX, with scale SCALE. The elements are specified via the VSIB
(i.e., the index register is a vector register, holding packed indices). Elements will only be stored if their corre-
sponding mask bit is one. The entire mask register will be set to zero by this instruction unless it triggers an excep-
tion.
This instruction can be suspended by an exception if at least one element is already scattered (i.e., if the exception
is triggered by an element other than the rightmost one with its mask bit set). When this happens, the destination
register and the mask register (k1) are partially updated. If any traps or interrupts are pending from already scat-
tered elements, they will be delivered in lieu of the exception; in this case, EFLAG.RF is set to one so an instruction
breakpoint is not re-triggered when the instruction is continued.
Note that:
.     Only writes to overlapping vector indices are guaranteed to be ordered with respect to each other (from LSB to
      MSB of the source registers). Note that this also include partially overlapping vector indices. Writes that are not
      overlapped may happen in any order. Memory ordering with other instructions follows the Intel-64 memory
      ordering model. Note that this does not account for non-overlapping indices that map into the same physical
      address locations.



.   If two or more destination indices completely overlap, the "earlier" write(s) may be skipped.
.   Faults are delivered in a right-to-left manner. That is, if a fault is triggered by an element and delivered, all
    elements closer to the LSB of the destination zmm will be completed (and non-faulting). Individual elements
    closer to the MSB may or may not be completed. If a given element triggers multiple faults, they are delivered
    in the conventional order.
.   Elements may be scattered in any order, but faults must be delivered in a right-to left order; thus, elements to
    the left of a faulting one may be gathered before the fault is delivered. A given implementation of this
    instruction is repeatable - given the same input values and architectural state, the same set of elements to the
    left of the faulting one will be gathered.
.   This instruction does not perform AC checks, and so will never deliver an AC fault.
.   Not valid with 16-bit effective addresses. Will deliver a #UD fault.
.   If this instruction overwrites itself and then takes a fault, only a subset of elements may be completed before
    the fault is delivered (as described above). If the fault handler completes and attempts to re-execute this
    instruction, the new instruction will be executed, and the scatter will not complete.
Note that the presence of VSIB byte is enforced in this instruction. Hence, the instruction will #UD fault if
ModRM.rm is different than 100b.
This instruction has special disp8*N and alignment rules. N is considered to be the size of a single vector element.
The scaled index may require more bits to represent than the address bits used by the processor (e.g., in 32-bit
mode, if the scale is greater than one). In this case, the most significant bits beyond the number of address bits
are ignored.
The instruction will #UD fault if the k0 mask register is specified





Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a ZMM register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement





VSCATTERDPS (EVEX encoded versions)
(KL, VL)= (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR +SignExtend(VINDEX[i+31:i]) * SCALE + DISP] <-
              SRC[i+31:i]
              k1[j] <- 0
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VSCATTERDPD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR +SignExtend(VINDEX[k+31:k]) * SCALE + DISP] <-
              SRC[i+63:i]
              k1[j] <- 0
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VSCATTERQPS (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    k <- j * 64
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR + (VINDEX[k+63:k]) * SCALE + DISP] <-
              SRC[i+31:i]
              k1[j] <- 0
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0

VSCATTERQPD (EVEX encoded versions)
(KL, VL)= (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN MEM[BASE_ADDR + (VINDEX[i+63:i]) * SCALE + DISP] <-
              SRC[i+63:i]
              k1[j] <- 0
    FI;
ENDFOR
k1[MAX_KL-1:KL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERDPD void _mm512_i32scatter_pd(void * base, __m256i vdx, __m512d a, int scale);
VSCATTERDPD void _mm512_mask_i32scatter_pd(void * base, __mmask8 k, __m256i vdx, __m512d a, int scale);
VSCATTERDPS void _mm512_i32scatter_ps(void * base, __m512i vdx, __m512 a, int scale);
VSCATTERDPS void _mm512_mask_i32scatter_ps(void * base, __mmask16 k, __m512i vdx, __m512 a, int scale);
VSCATTERQPD void _mm512_i64scatter_pd(void * base, __m512i vdx, __m512d a, int scale);
VSCATTERQPD void _mm512_mask_i64scatter_pd(void * base, __mmask8 k, __m512i vdx, __m512d a, int scale);
VSCATTERQPS void _mm512_i64scatter_ps(void * base, __m512i vdx, __m256 a, int scale);
VSCATTERQPS void _mm512_mask_i64scatter_ps(void * base, __mmask8 k, __m512i vdx, __m256 a, int scale);
VSCATTERDPD void _mm256_i32scatter_pd(void * base, __m128i vdx, __m256d a, int scale);
VSCATTERDPD void _mm256_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m256d a, int scale);
VSCATTERDPS void _mm256_i32scatter_ps(void * base, __m256i vdx, __m256 a, int scale);
VSCATTERDPS void _mm256_mask_i32scatter_ps(void * base, __mmask8 k, __m256i vdx, __m256 a, int scale);
VSCATTERQPD void _mm256_i64scatter_pd(void * base, __m256i vdx, __m256d a, int scale);
VSCATTERQPD void _mm256_mask_i64scatter_pd(void * base, __mmask8 k, __m256i vdx, __m256d a, int scale);
VSCATTERQPS void _mm256_i64scatter_ps(void * base, __m256i vdx, __m128 a, int scale);
VSCATTERQPS void _mm256_mask_i64scatter_ps(void * base, __mmask8 k, __m256i vdx, __m128 a, int scale);
VSCATTERDPD void _mm_i32scatter_pd(void * base, __m128i vdx, __m128d a, int scale);
VSCATTERDPD void _mm_mask_i32scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERDPS void _mm_i32scatter_ps(void * base, __m128i vdx, __m128 a, int scale);
VSCATTERDPS void _mm_mask_i32scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);
VSCATTERQPD void _mm_i64scatter_pd(void * base, __m128i vdx, __m128d a, int scale);
VSCATTERQPD void _mm_mask_i64scatter_pd(void * base, __mmask8 k, __m128i vdx, __m128d a, int scale);
VSCATTERQPS void _mm_i64scatter_ps(void * base, __m128i vdx, __m128 a, int scale);
VSCATTERQPS void _mm_mask_i64scatter_ps(void * base, __mmask8 k, __m128i vdx, __m128 a, int scale);

SIMD Floating-Point Exceptions
Invalid, Overflow, Underflow, Precision, Denormal

Other Exceptions
See Exceptions Type E12.






platform: x86_64
mnem: VSCATTERPF0DPS
description:
VSCATTERPF0DPS/VSCATTERPF0QPS/VSCATTERPF0DPD/VSCATTERPF0QPD-Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T0 Hint with Intent
to Write
 Opcode/                                  Op/     64/32        CPUID          Description
 Instruction                              En      bit Mode     Feature
                                                  Support      Flag
 EVEX.512.66.0F38.W0 C6 /5 /vsib          T1S     V/V          AVX512PF       Using signed dword indices, prefetch sparse byte
 VSCATTERPF0DPS vm32z {k1}                                                    memory locations containing single-precision data using
                                                                              writemask k1 and T0 hint with intent to write.
 EVEX.512.66.0F38.W0 C7 /5 /vsib          T1S     V/V          AVX512PF       Using signed qword indices, prefetch sparse byte
 VSCATTERPF0QPS vm64z {k1}                                                    memory locations containing single-precision data using
                                                                              writemask k1 and T0 hint with intent to write.
 EVEX.512.66.0F38.W1 C6 /5 /vsib          T1S     V/V          AVX512PF       Using signed dword indices, prefetch sparse byte
 VSCATTERPF0DPD vm32y {k1}                                                    memory locations containing double-precision data
                                                                              using writemask k1 and T0 hint with intent to write.
 EVEX.512.66.0F38.W1 C7 /5 /vsib          T1S     V/V          AVX512PF       Using signed qword indices, prefetch sparse byte
 VSCATTERPF0QPD vm64z {k1}                                                    memory locations containing double-precision data
                                                                              using writemask k1 and T0 hint with intent to write.



                                                  Instruction Operand Encoding
      Op/En                 Operand 1                     Operand 2                    Operand 3                    Operand 4
       T1S            BaseReg (R): VSIB:base,                 NA                            NA                          NA
                     VectorReg(R): VSIB:index

Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T0):
. T0 (temporal data)-prefetch data into the first level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request
for exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.



VSCATTERPF0DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=0, RFO = 1)
    FI;
ENDFOR

VSCATTERPF0DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=0, RFO = 1)
    FI;
ENDFOR

VSCATTERPF0QPS (EVEX encoded version)
(KL, VL) = (8, 256)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=0, RFO = 1)
    FI;
ENDFOR

VSCATTERPF0QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=0, RFO = 1)
    FI;
ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERPF0DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF0DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF0DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF0QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_prefetch_i64scatter_ps(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF0QPS void _mm512_mask_prefetch_i64scatter_ps(void * base, __mmask8 m, __m512i vdx, int scale, int hint);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12NP.





platform: x86_64
mnem: VSCATTERPF1DPS
description:
VSCATTERPF1DPS/VSCATTERPF1QPS/VSCATTERPF1DPD/VSCATTERPF1QPD-Sparse Prefetch
Packed SP/DP Data Values with Signed Dword, Signed Qword Indices Using T1 Hint with Intent
to Write
 Opcode/                                 Op/     64/32        CPUID         Description
 Instruction                             En      bit Mode     Feature
                                                 Support      Flag
 EVEX.512.66.0F38.W0 C6 /6 /vsib         T1S     V/V          AVX512PF      Using signed dword indices, prefetch sparse byte memory
 VSCATTERPF1DPS vm32z {k1}                                                  locations containing single-precision data using writemask
                                                                            k1 and T1 hint with intent to write.
 EVEX.512.66.0F38.W0 C7 /6 /vsib         T1S     V/V          AVX512PF      Using signed qword indices, prefetch sparse byte memory
 VSCATTERPF1QPS vm64z {k1}                                                  locations containing single-precision data using writemask
                                                                            k1 and T1 hint with intent to write.
 EVEX.512.66.0F38.W1 C6 /6 /vsib         T1S     V/V          AVX512PF      Using signed dword indices, prefetch sparse byte memory
 VSCATTERPF1DPD vm32y {k1}                                                  locations containing double-precision data using
                                                                            writemask k1 and T1 hint with intent to write.
 EVEX.512.66.0F38.W1 C7 /6 /vsib         T1S     V/V          AVX512PF      Using signed qword indices, prefetch sparse byte memory
 VSCATTERPF1QPD vm64z {k1}                                                  locations containing double-precision data using
                                                                            writemask k1 and T1 hint with intent to write.



                                                  Instruction Operand Encoding
     Op/En                 Operand 1                     Operand 2                    Operand 3                     Operand 4
      T1S           BaseReg (R): VSIB:base,                 NA                            NA                            NA
                   VectorReg(R): VSIB:index

Description
The instruction conditionally prefetches up to sixteen 32-bit or eight 64-bit integer byte data elements. The
elements are specified via the VSIB (i.e., the index register is an zmm, holding packed indices). Elements will only
be prefetched if their corresponding mask bit is one.
cache lines will be brought into exclusive state (RFO) specified by a locality hint (T1):
. T1 (temporal data)-prefetch data into the second level cache.
[PS data] For dword indices, the instruction will prefetch sixteen memory locations. For qword indices, the instruc-
tion will prefetch eight values.
[PD data] For dword and qword indices, the instruction will prefetch eight memory locations.
Note that:
(1) The prefetches may happen in any order (or not at all). The instruction is a hint.
(2) The mask is left unchanged.
(3) Not valid with 16-bit effective addresses. Will deliver a #UD fault.
(4) No FP nor memory faults may be produced by this instruction.
(5) Prefetches do not handle cache line splits
(6) A #UD is signaled if the memory operand is encoded without the SIB byte.

Operation
BASE_ADDR stands for the memory operand base address (a GPR); may not exist
VINDEX stands for the memory operand vector of indices (a vector register)
SCALE stands for the memory operand scalar (1, 2, 4 or 8)
DISP is the optional 1, 2 or 4 byte displacement
PREFETCH(mem, Level, State) Prefetches a byte memory location pointed by 'mem' into the cache level specified by 'Level'; a request
for exclusive/ownership is done if 'State' is 1. Note that the memory location ignore cache line splits. This operation is considered a
hint for the processor and may be skipped depending on implementation.



VSCATTERPF1DPS (EVEX encoded version)
(KL, VL) = (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+31:i]) * SCALE + DISP], Level=1, RFO = 1)
    FI;
ENDFOR

VSCATTERPF1DPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 32
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+31:k]) * SCALE + DISP], Level=1, RFO = 1)
    FI;
ENDFOR

VSCATTERPF1QPS (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[i+63:i]) * SCALE + DISP], Level=1, RFO = 1)
    FI;
ENDFOR

VSCATTERPF1QPD (EVEX encoded version)
(KL, VL) = (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    k <- j * 64
    IF k1[j]
         Prefetch( [BASE_ADDR + SignExtend(VINDEX[k+63:k]) * SCALE + DISP], Level=1, RFO = 1)
    FI;
ENDFOR

Intel C/C++ Compiler Intrinsic Equivalent
VSCATTERPF1DPD void _mm512_prefetch_i32scatter_pd(void *base, __m256i vdx, int scale, int hint);
VSCATTERPF1DPD void _mm512_mask_prefetch_i32scatter_pd(void *base, __mmask8 m, __m256i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm512_prefetch_i32scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF1DPS void _mm512_mask_prefetch_i32scatter_ps(void *base, __mmask16 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512_prefetch_i64scatter_pd(void * base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPD void _mm512_mask_prefetch_i64scatter_pd(void * base, __mmask8 m, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_prefetch_i64scatter_ps(void *base, __m512i vdx, int scale, int hint);
VSCATTERPF1QPS void _mm512_mask_prefetch_i64scatter_ps(void *base, __mmask8 m, __m512i vdx, int scale, int hint);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E12NP.





platform: x86_64
mnem: VSHUFF32x4
description:
VSHUFF32x4/VSHUFF64x2/VSHUFI32x4/VSHUFI64x2-Shuffle Packed Values at 128-bit
Granularity
 Opcode/                                   Op /    64/32       CPUID        Description
 Instruction                               En      bit Mode    Feature
                                                   Support     Flag
 EVEX.NDS.256.66.0F3A.W0 23 /r ib          FV      V/V         AVX512VL     Shuffle 128-bit packed single-precision floating-point
 VSHUFF32X4 ymm1{k1}{z}, ymm2,                                 AVX512F      values selected by imm8 from ymm2 and
 ymm3/m256/m32bcst, imm8                                                    ymm3/m256/m32bcst and place results in ymm1
                                                                            subject to writemask k1.
 EVEX.NDS.512.66.0F3A.W0 23 /r ib          FV      V/V         AVX512F      Shuffle 128-bit packed single-precision floating-point
 VSHUFF32x4 zmm1{k1}{z}, zmm2,                                              values selected by imm8 from zmm2 and
 zmm3/m512/m32bcst, imm8                                                    zmm3/m512/m32bcst and place results in zmm1
                                                                            subject to writemask k1.
 EVEX.NDS.256.66.0F3A.W1 23 /r ib          FV      V/V         AVX512VL     Shuffle 128-bit packed double-precision floating-point
 VSHUFF64X2 ymm1{k1}{z}, ymm2,                                 AVX512F      values selected by imm8 from ymm2 and
 ymm3/m256/m64bcst, imm8                                                    ymm3/m256/m64bcst and place results in ymm1
                                                                            subject to writemask k1.
 EVEX.NDS.512.66.0F3A.W1 23 /r ib          FV      V/V         AVX512F      Shuffle 128-bit packed double-precision floating-point
 VSHUFF64x2 zmm1{k1}{z}, zmm2,                                              values selected by imm8 from zmm2 and
 zmm3/m512/m64bcst, imm8                                                    zmm3/m512/m64bcst and place results in zmm1
                                                                            subject to writemask k1.
 EVEX.NDS.256.66.0F3A.W0 43 /r ib          FV      V/V         AVX512VL     Shuffle 128-bit packed double-word values selected by
 VSHUFI32X4 ymm1{k1}{z}, ymm2,                                 AVX512F      imm8 from ymm2 and ymm3/m256/m32bcst and place
 ymm3/m256/m32bcst, imm8                                                    results in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F3A.W0 43 /r ib          FV      V/V         AVX512F      Shuffle 128-bit packed double-word values selected by
 VSHUFI32x4 zmm1{k1}{z}, zmm2,                                              imm8 from zmm2 and zmm3/m512/m32bcst and place
 zmm3/m512/m32bcst, imm8                                                    results in zmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F3A.W1 43 /r ib          FV      V/V         AVX512VL     Shuffle 128-bit packed quad-word values selected by
 VSHUFI64X2 ymm1{k1}{z}, ymm2,                                 AVX512F      imm8 from ymm2 and ymm3/m256/m64bcst and place
 ymm3/m256/m64bcst, imm8                                                    results in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F3A.W1 43 /r ib          FV      V/V         AVX512F      Shuffle 128-bit packed quad-word values selected by
 VSHUFI64x2 zmm1{k1}{z}, zmm2,                                              imm8 from zmm2 and zmm3/m512/m64bcst and place
 zmm3/m512/m64bcst, imm8                                                    results in zmm1 subject to writemask k1.



                                                  Instruction Operand Encoding
       Op/En                 Operand 1                    Operand 2                 Operand 3                  Operand 4
         FV                ModRM:reg (w)                 EVEX.vvvv (r)            ModRM:r/m (r)                    NA

Description
256-bit Version: Moves one of the two 128-bit packed single-precision floating-point values from the first source
operand (second operand) into the low 128-bit of the destination operand (first operand); moves one of the two
packed 128-bit floating-point values from the second source operand (third operand) into the high 128-bit of the
destination operand. The selector operand (third operand) determines which values are moved to the destination
operand.
512-bit Version: Moves two of the four 128-bit packed single-precision floating-point values from the first source
operand (second operand) into the low 256-bit of each double qword of the destination operand (first operand);
moves two of the four packed 128-bit floating-point values from the second source operand (third operand) into
the high 256-bit of the destination operand. The selector operand (third operand) determines which values are
moved to the destination operand.
The first source operand is a vector register. The second source operand can be a ZMM register, a 512-bit memory
location or a 512-bit vector broadcasted from a 32/64-bit memory location. The destination operand is a vector
register.
The writemask updates the destination operand with the granularity of 32/64-bit data elements.



Operation
Select2(SRC, control) {
CASE (control[0]) OF
   0: TMP <- SRC[127:0];
   1: TMP <- SRC[255:128];
ESAC;
RETURN TMP
}

Select4(SRC, control) {
CASE (control[1:0]) OF
   0: TMP <- SRC[127:0];
   1: TMP <- SRC[255:128];
   2: TMP <- SRC[383:256];
   3: TMP <- SRC[511:384];
ESAC;
RETURN TMP
}

VSHUFF32x4 (EVEX versions)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask*
         THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        THEN DEST[i+31:i] <- 0
               FI;
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VSHUFF64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSHUFI32x4 (EVEX 512-bit version)
(KL, VL) = (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 32



   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       THEN DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSHUFI64x2 (EVEX 512-bit version)
(KL, VL) = (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 256
    TMP_DEST[127:0] <- Select2(SRC1[255:0], imm8[0]);
    TMP_DEST[255:128] <- Select2(SRC2[255:0], imm8[1]);
FI;
IF VL = 512
    TMP_DEST[127:0] <- Select4(SRC1[511:0], imm8[1:0]);
    TMP_DEST[255:128] <- Select4(SRC1[511:0], imm8[3:2]);
    TMP_DEST[383:256] <- Select4(TMP_SRC2[511:0], imm8[5:4]);
    TMP_DEST[511:384] <- Select4(TMP_SRC2[511:0], imm8[7:6]);
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         THEN DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
VSHUFI32x4 __m512i _mm512_shuffle_i32x4(__m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_mask_shuffle_i32x4(__m512i s, __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m512i _mm512_maskz_shuffle_i32x4( __mmask16 k, __m512i a, __m512i b, int imm);
VSHUFI32x4 __m256i _mm256_shuffle_i32x4(__m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_mask_shuffle_i32x4(__m256i s, __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFI32x4 __m256i _mm256_maskz_shuffle_i32x4( __mmask8 k, __m256i a, __m256i b, int imm);
VSHUFF32x4 __m512 _mm512_shuffle_f32x4(__m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_mask_shuffle_f32x4(__m512 s, __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFF32x4 __m512 _mm512_maskz_shuffle_f32x4( __mmask16 k, __m512 a, __m512 b, int imm);
VSHUFI64x2 __m512i _mm512_shuffle_i64x2(__m512i a, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_mask_shuffle_i64x2(__m512i s, __mmask8 k, __m512i b, __m512i b, int imm);
VSHUFI64x2 __m512i _mm512_maskz_shuffle_i64x2( __mmask8 k, __m512i a, __m512i b, int imm);
VSHUFF64x2 __m512d _mm512_shuffle_f64x2(__m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_mask_shuffle_f64x2(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFF64x2 __m512d _mm512_maskz_shuffle_f64x2( __mmask8 k, __m512d a, __m512d b, int imm);

SIMD Floating-Point Exceptions
None

Other Exceptions
See Exceptions Type E4NF.
#UD                    If EVEX.L'L = 0 for VSHUFF32x4/VSHUFF64x2.






platform: x86_64
mnem: VTESTPD
description:
VTESTPD/VTESTPS-Packed Bit Test
 Opcode/                                       Op/   64/32 bit    CPUID     Description
 Instruction                                   En    Mode         Feature
                                                     Support      Flag
 VEX.128.66.0F38.W0 0E /r                      RM    V/V          AVX       Set ZF and CF depending on sign bit AND and
 VTESTPS xmm1, xmm2/m128                                                    ANDN of packed single-precision floating-point
                                                                            sources.
 VEX.256.66.0F38.W0 0E /r                      RM    V/V          AVX       Set ZF and CF depending on sign bit AND and
 VTESTPS ymm1, ymm2/m256                                                    ANDN of packed single-precision floating-point
                                                                            sources.
 VEX.128.66.0F38.W0 0F /r                      RM    V/V          AVX       Set ZF and CF depending on sign bit AND and
 VTESTPD xmm1, xmm2/m128                                                    ANDN of packed double-precision floating-point
                                                                            sources.
 VEX.256.66.0F38.W0 0F /r                      RM    V/V          AVX       Set ZF and CF depending on sign bit AND and
 VTESTPD ymm1, ymm2/m256                                                    ANDN of packed double-precision floating-point
                                                                            sources.



                                            Instruction Operand Encoding
  Op/En            Operand 1                   Operand 2                    Operand 3                    Operand 4
    RM            ModRM:reg (r)              ModRM:r/m (r)                     NA                           NA


Description
VTESTPS performs a bitwise comparison of all the sign bits of the packed single-precision elements in the first
source operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with
the dest sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND of the source sign bits with the
inverted dest sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with
VEX.W=1 will cause #UD.
VTESTPD performs a bitwise comparison of all the sign bits of the double-precision elements in the first source
operation and corresponding sign bits in the second source operand. If the AND of the source sign bits with the dest
sign bits produces all zeros, the ZF is set else the ZF is clear. If the AND the source sign bits with the inverted dest
sign bits produces all zeros the CF is set else the CF is clear. An attempt to execute VTESTPS with VEX.W=1 will
cause #UD.
The first source register is specified by the ModR/M reg field.
128-bit version: The first source register is an XMM register. The second source register can be an XMM register or
a 128-bit memory location. The destination register is not modified.
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM
register or a 256-bit memory location. The destination register is not modified.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





Operation
VTESTPS (128-bit version)
TEMP[127:0] <- SRC[127:0] AND DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;

TEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127] = 0)
    THEN CF <-1;
    ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

VTESTPS (VEX.256 encoded version)
TEMP[255:0] <- SRC[255:0] AND DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;

TEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[31] = TEMP[63] = TEMP[95] = TEMP[127]= TEMP[160] =TEMP[191] = TEMP[224] = TEMP[255] = 0)
    THEN CF <-1;
    ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

VTESTPD (128-bit version)
TEMP[127:0] <- SRC[127:0] AND DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
     THEN ZF <-1;
     ELSE ZF <- 0;

TEMP[127:0] <- SRC[127:0] AND NOT DEST[127:0]
IF ( TEMP[63] = TEMP[127] = 0)
     THEN CF <-1;
     ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

VTESTPD (VEX.256 encoded version)
TEMP[255:0] <- SRC[255:0] AND DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
    THEN ZF <-1;
    ELSE ZF <- 0;

TEMP[255:0] <- SRC[255:0] AND NOT DEST[255:0]
IF (TEMP[63] = TEMP[127] = TEMP[191] = TEMP[255] = 0)
    THEN CF <-1;
    ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;





Intel C/C++ Compiler Intrinsic Equivalent

VTESTPS
   int _mm256_testz_ps (__m256 s1, __m256 s2);
   int _mm256_testc_ps (__m256 s1, __m256 s2);
   int _mm256_testnzc_ps (__m256 s1, __m128 s2);
   int _mm_testz_ps (__m128 s1, __m128 s2);
   int _mm_testc_ps (__m128 s1, __m128 s2);
   int _mm_testnzc_ps (__m128 s1, __m128 s2);



VTESTPD
   int _mm256_testz_pd (__m256d s1, __m256d s2);
   int _mm256_testc_pd (__m256d s1, __m256d s2);
   int _mm256_testnzc_pd (__m256d s1, __m256d s2);
   int _mm_testz_pd (__m128d s1, __m128d s2);
   int _mm_testc_pd (__m128d s1, __m128d s2);
   int _mm_testnzc_pd (__m128d s1, __m128d s2);

Flags Affected
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                  If VEX.vvvv != 1111B.
                     If VEX.W = 1 for VTESTPS or VTESTPD.






platform: x86_64
mnem: VZEROALL
description:
VZEROALL-Zero All YMM Registers
 Opcode/                                       Op/     64/32 bit   CPUID      Description
 Instruction                                   En      Mode        Feature
                                                       Support     Flag
 VEX.256.0F.WIG 77                             NP      V/V         AVX        Zero all YMM registers.
 VZEROALL



                                          Instruction Operand Encoding
   Op/En             Operand 1             Operand 2                     Operand 3                      Operand 4
     NP                 NA                    NA                             NA                            NA


Description
The instruction zeros contents of all XMM or YMM registers.
Note: VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD. In Compatibility and legacy 32-
bit mode only the lower 8 registers are modified.

Operation
VZEROALL (VEX.256 encoded version)
IF (64-bit mode)
    YMM0[VLMAX-1:0] <- 0
    YMM1[VLMAX-1:0] <- 0
    YMM2[VLMAX-1:0] <- 0
    YMM3[VLMAX-1:0] <- 0
    YMM4[VLMAX-1:0] <- 0
    YMM5[VLMAX-1:0] <- 0
    YMM6[VLMAX-1:0] <- 0
    YMM7[VLMAX-1:0] <- 0
    YMM8[VLMAX-1:0] <- 0
    YMM9[VLMAX-1:0] <- 0
    YMM10[VLMAX-1:0] <- 0
    YMM11[VLMAX-1:0] <- 0
    YMM12[VLMAX-1:0] <- 0
    YMM13[VLMAX-1:0] <- 0
    YMM14[VLMAX-1:0] <- 0
    YMM15[VLMAX-1:0] <- 0
ELSE
    YMM0[VLMAX-1:0] <- 0
    YMM1[VLMAX-1:0] <- 0
    YMM2[VLMAX-1:0] <- 0
    YMM3[VLMAX-1:0] <- 0
    YMM4[VLMAX-1:0] <- 0
    YMM5[VLMAX-1:0] <- 0
    YMM6[VLMAX-1:0] <- 0
    YMM7[VLMAX-1:0] <- 0
    YMM8-15: Unmodified
FI





Intel C/C++ Compiler Intrinsic Equivalent
VZEROALL:        _mm256_zeroall()

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 8.






platform: x86_64
mnem: VZEROUPPER
description:
VZEROUPPER-Zero Upper Bits of YMM Registers
Opcode/                                            Op/     64/32 bit   CPUID     Description
Instruction                                        En      Mode        Feature
                                                           Support     Flag
VEX.128.0F.WIG 77                                  NP    V/V           AVX       Zero upper 128 bits of all YMM registers.
VZEROUPPER



                                              Instruction Operand Encoding
   Op/En              Operand 1                Operand 2                     Operand 3                     Operand 4
     NP                  NA                       NA                             NA                           NA


Description
The instruction zeros the bits in position 128 and higher of all YMM registers. The lower 128-bits of the registers
(the corresponding XMM registers) are unmodified.
This instruction is recommended when transitioning between AVX and legacy SSE code - it will eliminate perfor-
mance penalties caused by false dependencies.
Note: VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD. In Compatibility and legacy 32-bit
mode only the lower 8 registers are modified.

Operation
VZEROUPPER
IF (64-bit mode)
    YMM0[VLMAX-1:128] <- 0
    YMM1[VLMAX-1:128] <- 0
    YMM2[VLMAX-1:128] <- 0
    YMM3[VLMAX-1:128] <- 0
    YMM4[VLMAX-1:128] <- 0
    YMM5[VLMAX-1:128] <- 0
    YMM6[VLMAX-1:128] <- 0
    YMM7[VLMAX-1:128] <- 0
    YMM8[VLMAX-1:128] <- 0
    YMM9[VLMAX-1:128] <- 0
    YMM10[VLMAX-1:128] <- 0
    YMM11[VLMAX-1:128] <- 0
    YMM12[VLMAX-1:128] <- 0
    YMM13[VLMAX-1:128] <- 0
    YMM14[VLMAX-1:128] <- 0
    YMM15[VLMAX-1:128] <- 0
ELSE
    YMM0[VLMAX-1:128] <- 0
    YMM1[VLMAX-1:128] <- 0
    YMM2[VLMAX-1:128] <- 0
    YMM3[VLMAX-1:128] <- 0
    YMM4[VLMAX-1:128] <- 0
    YMM5[VLMAX-1:128] <- 0
    YMM6[VLMAX-1:128] <- 0
    YMM7[VLMAX-1:128] <- 0
    YMM8-15: unmodified
FI





Intel C/C++ Compiler Intrinsic Equivalent
VZEROUPPER:      _mm256_zeroupper()

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 8.






platform: x86_64
mnem: WAIT
description:
WAIT/FWAIT-Wait
 Opcode                Instruction                 Op/    64-Bit   Compat/ Description
                                                   En     Mode     Leg Mode
 9B                    WAIT                        NP     Valid    Valid       Check pending unmasked floating-point
                                                                               exceptions.
 9B                    FWAIT                       NP     Valid    Valid       Check pending unmasked floating-point
                                                                               exceptions.



                                            Instruction Operand Encoding
   Op/En           Operand 1                  Operand 2                    Operand 3                   Operand 4
      NP              NA                           NA                         NA                           NA


Description
Causes the processor to check for and handle pending, unmasked, floating-point exceptions before proceeding.
(FWAIT is an alternate mnemonic for WAIT.)
This instruction is useful for synchronizing exceptions in critical sections of code. Coding a WAIT instruction after a
floating-point instruction ensures that any unmasked floating-point exceptions the instruction may raise are
handled before the processor can modify the instruction's results. See the section titled "Floating-Point Exception
Synchronization" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1,
for more information on using the WAIT/FWAIT instruction.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

Operation
CheckForPendingUnmaskedFloatingPointExceptions;

FPU Flags Affected
The C0, C1, C2, and C3 flags are undefined.

Floating-Point Exceptions
None.

Protected Mode Exceptions
#NM                  If CR0.MP[bit 1] = 1 and CR0.TS[bit 3] = 1.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: WBINVD
description:
WBINVD-Write Back and Invalidate Cache
 Opcode                    Instruction                Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 0F 09                    WBINVD                      NP    Valid    Valid       Write back and flush Internal caches; initiate
                                                                                 writing-back and flushing of external caches.



                                               Instruction Operand Encoding
    Op/En              Operand 1                  Operand 2                  Operand 3                     Operand 4
      NP                   NA                         NA                        NA                             NA


Description
Writes back all modified cache lines in the processor's internal cache to main memory and invalidates (flushes) the
internal caches. The instruction then issues a special-function bus cycle that directs external caches to also write
back modified data and another bus cycle to indicate that the external caches should be invalidated.
After executing this instruction, the processor does not wait for the external caches to complete their write-back
and flushing operations before proceeding with instruction execution. It is the responsibility of hardware to respond
to the cache write-back and flush signals. The amount of time or cycles for WBINVD to complete will vary due to
size and other factors of different cache hierarchies. As a consequence, the use of the WBINVD instruction can have
an impact on logical processor interrupt/event response time. Additional information of WBINVD behavior in a
cache hierarchy with hierarchical sharing topology can be found in Chapter 2 of the Intel 64 and IA-32 Architec-
tures Software Developer's Manual, Volume 3A.
The WBINVD instruction is a privileged instruction. When the processor is running in protected mode, the CPL of a
program or procedure must be 0 to execute this instruction. This instruction is also a serializing instruction (see
"Serializing Instructions" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 3A).
In situations where cache coherency with main memory is not a concern, software can use the INVD instruction.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.

IA-32 Architecture Compatibility
The WBINVD instruction is implementation dependent, and its function may be implemented differently on future
Intel 64 and IA-32 processors. The instruction is not supported on IA-32 processors earlier than the Intel486
processor.

Operation
WriteBack(InternalCaches);
Flush(InternalCaches);
SignalWriteBack(ExternalCaches);
SignalFlush(ExternalCaches);
Continue; (* Continue execution *)

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the current privilege level is not 0.
#UD                     If the LOCK prefix is used.





Real-Address Mode Exceptions
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  WBINVD cannot be executed at the virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: WRFSBASE
description:
WRFSBASE/WRGSBASE-Write FS/GS Segment Base
Opcode/                                          Op/     64/32-   CPUID Fea- Description
Instruction                                      En      bit      ture Flag
                                                         Mode
F3 0F AE /2                                      M       V/I      FSGSBASE   Load the FS base address with the 32-bit value in
WRFSBASE r32                                                                 the source register.
F3 REX.W 0F AE /2                                M       V/I      FSGSBASE   Load the FS base address with the 64-bit value in
WRFSBASE r64                                                                 the source register.
F3 0F AE /3                                      M       V/I      FSGSBASE   Load the GS base address with the 32-bit value in
WRGSBASE r32                                                                 the source register.
F3 REX.W 0F AE /3                                M       V/I      FSGSBASE   Load the GS base address with the 64-bit value in
WRGSBASE r64                                                                 the source register.



                                                 Instruction Operand Encoding
   Op/En             Operand 1                       Operand 2                Operand 3                      Operand 4
     M              ModRM:r/m (r)                       NA                       NA                             NA


Description
Loads the FS or GS segment base address with the general-purpose register indicated by the modR/M:r/m field.
The source operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the
operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source
register are ignored and upper 32 bits of the base address (for FS or GS) are cleared.
This instruction is supported only in 64-bit mode.

Operation
FS/GS segment base address <- SRC;

Flags Affected
None

C/C++ Compiler Intrinsic Equivalent
WRFSBASE:        void _writefsbase_u32( unsigned int );
WRFSBASE:           _writefsbase_u64( unsigned __int64 );
WRGSBASE:           void _writegsbase_u32( unsigned int );
WRGSBASE:           _writegsbase_u64( unsigned __int64 );

Protected Mode Exceptions
#UD                    The WRFSBASE and WRGSBASE instructions are not recognized in protected mode.

Real-Address Mode Exceptions
#UD                    The WRFSBASE and WRGSBASE instructions are not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                    The WRFSBASE and WRGSBASE instructions are not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
#UD                    The WRFSBASE and WRGSBASE instructions are not recognized in compatibility mode.



64-Bit Mode Exceptions
#UD                   If the LOCK prefix is used.
                      If CR4.FSGSBASE[bit 16] = 0.
                      If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0
#GP(0)                If the source register contains a non-canonical address.






platform: x86_64
mnem: WRMSR
description:
WRMSR-Write to Model Specific Register
 Opcode                Instruction              Op/      64-Bit   Compat/ Description
                                                En       Mode     Leg Mode
 0F 30                 WRMSR                    NP       Valid    Valid       Write the value in EDX:EAX to MSR specified
                                                                              by ECX.



                                           Instruction Operand Encoding
   Op/En           Operand 1                 Operand 2                    Operand 3                   Operand 4
    NP                NA                        NA                           NA                           NA


Description
Writes the contents of registers EDX:EAX into the 64-bit model specific register (MSR) specified in the ECX register.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The contents of
the EDX register are copied to high-order 32 bits of the selected MSR and the contents of the EAX register are
copied to low-order 32 bits of the MSR. (On processors that support the Intel 64 architecture, the high-order 32
bits of each of RAX and RDX are ignored.) Undefined or reserved bits in an MSR should be set to values previously
read.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) is generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a
general protection exception. The processor will also generate a general protection exception if software attempts
to write to bits in a reserved MSR.
When the WRMSR instruction is used to write to an MTRR, the TLBs are invalidated. This includes global entries (see
"Translation Lookaside Buffers (TLBs)" in Chapter 3 of the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3A).
MSRs control functions for testability, execution tracing, performance-monitoring and machine check errors.
Chapter 35, "Model-Specific Registers (MSRs)", in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3C, lists all MSRs that can be written with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The WRMSR instruction is a serializing instruction (see "Serializing Instructions" in Chapter 8 of the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A). Note that WRMSR to the IA32_TSC_DEADLINE
MSR (MSR index 6E0H) and the X2APIC MSRs (MSR indices 802H to 83FH) are not serializing.
The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before
using this instruction.

IA-32 Architecture Compatibility
The MSRs and the ability to read them with the WRMSR instruction were introduced into the IA-32 architecture with
the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor
results in an invalid opcode exception #UD.

Operation
MSR[ECX] <- EDX:EAX;

Flags Affected
None.





Protected Mode Exceptions
#GP(0)                   If the current privilege level is not 0.
                         If the value in ECX specifies a reserved or unimplemented MSR address.
                         If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
                         If the source register contains a non-canonical address and ECX specifies one of the following
                         MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,
                         IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                      If the value in ECX specifies a reserved or unimplemented MSR address.
                         If the value in EDX:EAX sets bits that are reserved in the MSR specified by ECX.
                         If the source register contains a non-canonical address and ECX specifies one of the following
                         MSRs: IA32_DS_AREA, IA32_FS_BASE, IA32_GS_BASE, IA32_KERNEL_GS_BASE,
                         IA32_LSTAR, IA32_SYSENTER_EIP, IA32_SYSENTER_ESP.
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   The WRMSR instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: WRPKRU
description:
WRPKRU-Write Data to User Page Key Register
Opcode*                Instruction          Op/     64/32bit   CPUID     Description
                                            En      Mode       Feature
                                                    Support    Flag
0F 01 EF               WRPKRU               NP      V/V        OSPKE     Writes EAX into PKRU.



                                            Instruction Operand Encoding
  Op/En            Operand 1                 Operand 2                    Operand 3                     Operand 4
    NP                 NA                         NA                         NA                             NA


Description
Writes the value of EAX into PKRU. ECX and EDX must be 0 when WRPKRU is executed; otherwise, a general-
protection exception (#GP) occurs.
WRPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX, RDX and RAX are ignored.

Operation

IF (ECX = 0 AND EDX = 0)
    THEN PKRU <- EAX;
    ELSE #GP(0);
FI;

Flags Affected
None.

C/C++ Compiler Intrinsic Equivalent
WRPKRU:           void _wrpkru(uint32_t);

Protected Mode Exceptions
#GP(0)                If ECX   != 0.
                      If EDX   != 0.
#UD                   If the LOCK prefix is used.
                      If CR4.PKE = 0.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.





platform: x86_64
mnem: XACQUIRE
description:
XACQUIRE/XRELEASE - Hardware Lock Elision Prefix Hints
    Opcode/Instruction                   64/32bit        CPUID     Description
                                         Mode            Feature
                                         Support         Flag
    F2                                   V/V             HLE1      A hint used with an "XACQUIRE-enabled" instruction to start lock
    XACQUIRE                                                       elision on the instruction memory operand address.
    F3                                   V/V             HLE       A hint used with an "XRELEASE-enabled" instruction to end lock
    XRELEASE                                                       elision on the instruction memory operand address.
NOTES:
1. Software is not required to check the HLE feature flag to use XACQUIRE or XRELEASE, as they are treated as regular prefix if HLE
   feature flag reports 0.



Description
The XACQUIRE prefix is a hint to start lock elision on the memory address specified by the instruction and the
XRELEASE prefix is a hint to end lock elision on the memory address specified by the instruction.
The XACQUIRE prefix hint can only be used with the following instructions (these instructions are also referred to
as XACQUIRE-enabled when used with the XACQUIRE prefix):
.     Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination
      operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,
      OR, SBB, SUB, XOR, XADD, and XCHG.
.     The XCHG instruction either with or without the presence of the LOCK prefix.
The XRELEASE prefix hint can only be used with the following instructions (also referred to as XRELEASE-enabled
when used with the XRELEASE prefix):
.     Instructions with an explicit LOCK prefix (F0H) prepended to forms of the instruction where the destination
      operand is a memory operand: ADD, ADC, AND, BTC, BTR, BTS, CMPXCHG, CMPXCHG8B, DEC, INC, NEG, NOT,
      OR, SBB, SUB, XOR, XADD, and XCHG.
.     The XCHG instruction either with or without the presence of the LOCK prefix.
.     The "MOV mem, reg" (Opcode 88H/89H) and "MOV mem, imm" (Opcode C6H/C7H) instructions. In these
      cases, the XRELEASE is recognized without the presence of the LOCK prefix.
The lock variables must satisfy the guidelines described in Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, Section 16.3.3, for elision to be successful, otherwise an HLE abort may be signaled.
If an encoded byte sequence that meets XACQUIRE/XRELEASE requirements includes both prefixes, then the HLE
semantic is determined by the prefix byte that is placed closest to the instruction opcode. For example, an F3F2C6
will not be treated as a XRELEASE-enabled instruction since the F2H (XACQUIRE) is closest to the instruction
opcode C6. Similarly, an F2F3F0 prefixed instruction will be treated as a XRELEASE-enabled instruction since F3H
(XRELEASE) is closest to the instruction opcode.





Intel 64 and IA-32 Compatibility
The effect of the XACQUIRE/XRELEASE prefix hint is the same in non-64-bit modes and in 64-bit mode.
For instructions that do not support the XACQUIRE hint, the presence of the F2H prefix behaves the same way as
prior hardware, according to
.   REPNE/REPNZ semantics for string instructions,
.   Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
.   Cause #UD if prepending the VEX prefix.
.   Undefined for non-string instructions or other situations.
For instructions that do not support the XRELEASE hint, the presence of the F3H prefix behaves the same way as in
prior hardware, according to
.   REP/REPE/REPZ semantics for string instructions,
.   Serve as SIMD prefix for legacy SIMD instructions operating on XMM register
.   Cause #UD if prepending the VEX prefix.
.   Undefined for non-string instructions or other situations.

Operation
XACQUIRE
IF XACQUIRE-enabled instruction
    THEN
        IF (HLE_NEST_COUNT < MAX_HLE_NEST_COUNT) THEN
             HLE_NEST_COUNT++
             IF (HLE_NEST_COUNT = 1) THEN
                   HLE_ACTIVE <- 1
                   IF 64-bit mode
                        THEN
                             restartRIP <- instruction pointer of the XACQUIRE-enabled instruction
                        ELSE
                             restartEIP <- instruction pointer of the XACQUIRE-enabled instruction
                   FI;
                   Enter HLE Execution (* record register state, start tracking memory state *)
             FI; (* HLE_NEST_COUNT = 1*)
             IF ElisionBufferAvailable
                   THEN
                        Allocate elision buffer
                        Record address and data for forwarding and commit checking
                        Perform elision
                   ELSE
                        Perform lock acquire operation transactionally but without elision
             FI;
        ELSE (* HLE_NEST_COUNT = MAX_HLE_NEST_COUNT *)
                   GOTO HLE_ABORT_PROCESSING
        FI;
    ELSE
        Treat instruction as non-XACQUIRE F2H prefixed legacy instruction
FI;





XRELEASE

IF XRELEASE-enabled instruction
    THEN
        IF (HLE_NEST_COUNT > 0)
              THEN
                  HLE_NEST_COUNT--
                  IF lock address matches in elision buffer THEN
                        IF lock satisfies address and value requirements THEN
                              Deallocate elision buffer
                        ELSE
                              GOTO HLE_ABORT_PROCESSING
                        FI;
                  FI;
                  IF (HLE_NEST_COUNT = 0)
                        THEN
                              IF NoAllocatedElisionBuffer
                                   THEN
                                        Try to commit transactional execution
                                        IF fail to commit transactional execution
                                              THEN
                                                    GOTO HLE_ABORT_PROCESSING;
                                              ELSE (* commit success *)
                                                    HLE_ACTIVE <- 0
                                        FI;
                                   ELSE
                                        GOTO HLE_ABORT_PROCESSING
                              FI;
                  FI;
        FI; (* HLE_NEST_COUNT > 0 *)
    ELSE
        Treat instruction as non-XRELEASE F3H prefixed legacy instruction
FI;

(* For any HLE abort condition encountered during HLE execution *)
HLE_ABORT_PROCESSING:
    HLE_ACTIVE <- 0
    HLE_NEST_COUNT <- 0
    Restore architectural register state
    Discard memory updates performed in transaction
    Free any allocated lock elision buffers
    IF 64-bit mode
         THEN
              RIP <- restartRIP
         ELSE
              EIP <- restartEIP
    FI;
    Execute and retire instruction at RIP (or EIP) and ignore any HLE hint
END





SIMD Floating-Point Exceptions
None

Other Exceptions
#GP(0)              If the use of prefix causes instruction length to exceed 15 bytes.






platform: x86_64
mnem: XABORT
description:
XABORT - Transactional Abort
 Opcode/Instruction               Op/        64/32bit    CPUID     Description
                                  En         Mode        Feature
                                             Support     Flag
 C6 F8 ib                         A          V/V         RTM       Causes an RTM abort if in RTM execution
 XABORT imm8



                                                    Instruction Operand Encoding
  Op/En              Operand 1                          Operand2                   Operand3                    Operand4
     A                 imm8                               NA                          NA                          NA


Description
XABORT forces an RTM abort. Following an RTM abort, the logical processor resumes execution at the fallback
address computed through the outermost XBEGIN instruction. The EAX register is updated to reflect an XABORT
instruction caused the abort, and the imm8 argument will be provided in bits 31:24 of EAX.

Operation
XABORT
IF RTM_ACTIVE = 0
    THEN
        Treat as NOP;
    ELSE
        GOTO RTM_ABORT_PROCESSING;
FI;

(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
    Restore architectural register state;
    Discard memory updates performed in transaction;
    Update EAX with status and XABORT argument;
    RTM_NEST_COUNT <- 0;
    RTM_ACTIVE <- 0;
    IF 64-bit Mode
         THEN
              RIP <- fallbackRIP;
         ELSE
              EIP <- fallbackEIP;
    FI;
END

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
XABORT:       void _xabort( unsigned int);

SIMD Floating-Point Exceptions
None





Other Exceptions
#UD                 CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
                    If LOCK prefix is used.






platform: x86_64
mnem: XADD
description:
XADD-Exchange and Add
 Opcode                   Instruction                   Op/   64-Bit       Compat/ Description
                                                        En    Mode         Leg Mode
 0F C0 /r                 XADD r/m8, r8                 MR    Valid        Valid        Exchange r8 and r/m8; load sum into r/m8.
 REX + 0F C0 /r           XADD r/m8*, r8*               MR    Valid        N.E.         Exchange r8 and r/m8; load sum into r/m8.
 0F C1 /r                 XADD r/m16, r16               MR    Valid        Valid        Exchange r16 and r/m16; load sum into r/m16.
 0F C1 /r                 XADD r/m32, r32               MR    Valid        Valid        Exchange r32 and r/m32; load sum into r/m32.
 REX.W + 0F C1 /r         XADD r/m64, r64               MR    Valid        N.E.         Exchange r64 and r/m64; load sum into r/m64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En             Operand 1                    Operand 2                        Operand 3                     Operand 4
    MR            ModRM:r/m (r, w)             ModRM:reg (r, w)                       NA                             NA


Description
Exchanges the first operand (destination operand) with the second operand (source operand), then loads the sum
of the two values into the destination operand. The destination operand can be a register or a memory location; the
source operand is a register.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.

IA-32 Architecture Compatibility
IA-32 processors earlier than the Intel486 processor do not recognize this instruction. If this instruction is used,
you should provide an equivalent code sequence that runs on earlier processors.

Operation
TEMP <- SRC + DEST;
SRC <- DEST;
DEST <- TEMP;

Flags Affected
The CF, PF, AF, SF, ZF, and OF flags are set according to the result of the addition, which is stored in the destination
operand.

Protected Mode Exceptions
#GP(0)                  If the destination is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.




Real-Address Mode Exceptions
#GP                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                 If a memory operand effective address is outside the SS segment limit.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: XBEGIN
description:
XBEGIN - Transactional Begin
 Opcode/Instruction                Op/    64/32bit     CPUID         Description
                                   En     Mode         Feature
                                          Support      Flag
 C7 F8                             A      V/V          RTM           Specifies the start of an RTM region. Provides a 16-bit relative
 XBEGIN rel16                                                        offset to compute the address of the fallback instruction address at
                                                                     which execution resumes following an RTM abort.
 C7 F8                             A      V/V          RTM           Specifies the start of an RTM region. Provides a 32-bit relative
 XBEGIN rel32                                                        offset to compute the address of the fallback instruction address at
                                                                     which execution resumes following an RTM abort.



                                                  Instruction Operand Encoding
   Op/En             Operand 1                     Operand2                         Operand3                        Operand4
     A                 Offset                         NA                                NA                              NA


Description
The XBEGIN instruction specifies the start of an RTM code region. If the logical processor was not already in trans-
actional execution, then the XBEGIN instruction causes the logical processor to transition into transactional execu-
tion. The XBEGIN instruction that transitions the logical processor into transactional execution is referred to as the
outermost XBEGIN instruction. The instruction also specifies a relative offset to compute the address of the fallback
code path following a transactional abort.
On an RTM abort, the logical processor discards all architectural register and memory updates performed during
the RTM execution and restores architectural state to that corresponding to the outermost XBEGIN instruction. The
fallback address following an abort is computed from the outermost XBEGIN instruction.

Operation
XBEGIN
IF RTM_NEST_COUNT < MAX_RTM_NEST_COUNT
    THEN
       RTM_NEST_COUNT++
       IF RTM_NEST_COUNT = 1 THEN
            IF 64-bit Mode
                 THEN
                          fallbackRIP <- RIP + SignExtend64(IMM)
                                        (* RIP is instruction following XBEGIN instruction *)
                      ELSE
                          fallbackEIP <- EIP + SignExtend32(IMM)
                                        (* EIP is instruction following XBEGIN instruction *)
            FI;

             IF (64-bit mode)
                  THEN IF (fallbackRIP is not canonical)
                       THEN #GP(0)
                  FI;
                  ELSE IF (fallbackEIP outside code segment limit)
                       THEN #GP(0)
                  FI;
             FI;

               RTM_ACTIVE <- 1
               Enter RTM Execution (* record register state, start tracking memory state*)
         FI; (* RTM_NEST_COUNT = 1 *)



      ELSE (* RTM_NEST_COUNT = MAX_RTM_NEST_COUNT *)
          GOTO RTM_ABORT_PROCESSING
FI;

(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
    Restore architectural register state
    Discard memory updates performed in transaction
    Update EAX with status
    RTM_NEST_COUNT <- 0
    RTM_ACTIVE <- 0
    IF 64-bit mode
         THEN
              RIP <- fallbackRIP
         ELSE
              EIP <- fallbackEIP
    FI;
END

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
XBEGIN:      unsigned int _xbegin( void );

SIMD Floating-Point Exceptions
None

Protected Mode Exceptions
#UD                      CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
                         If LOCK prefix is used.
#GP(0)                   If the fallback address is outside the CS segment.

Real-Address Mode Exceptions
#GP(0)                   If the fallback address is outside the address space 0000H and FFFFH.
#UD                      CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
                         If LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   If the fallback address is outside the address space 0000H and FFFFH.
#UD                      CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11]=0.
                         If LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-bit Mode Exceptions
#UD                      CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
                         If LOCK prefix is used.
#GP(0)                   If the fallback address is non-canonical.






platform: x86_64
mnem: XCHG
description:
XCHG - Exchange Register/Memory with Register
 Opcode                    Instruction                  Op/    64-Bit       Compat/ Description
                                                        En     Mode         Leg Mode
 90+rw                     XCHG AX, r16                 O      Valid        Valid       Exchange r16 with AX.
 90+rw                     XCHG r16, AX                 O      Valid        Valid       Exchange AX with r16.
 90+rd                     XCHG EAX, r32                O      Valid        Valid       Exchange r32 with EAX.
 REX.W + 90+rd             XCHG RAX, r64                O      Valid        N.E.        Exchange r64 with RAX.
 90+rd                     XCHG r32, EAX                O      Valid        Valid       Exchange EAX with r32.
 REX.W + 90+rd             XCHG r64, RAX                O      Valid        N.E.        Exchange RAX with r64.
 86 /r                     XCHG r/m8, r8                MR     Valid        Valid       Exchange r8 (byte register) with byte from
                                                                                        r/m8.
 REX + 86 /r               XCHG r/m8*, r8*              MR     Valid        N.E.        Exchange r8 (byte register) with byte from
                                                                                        r/m8.
 86 /r                     XCHG r8, r/m8                RM     Valid        Valid       Exchange byte from r/m8 with r8 (byte
                                                                                        register).
 REX + 86 /r               XCHG r8*, r/m8*              RM     Valid        N.E.        Exchange byte from r/m8 with r8 (byte
                                                                                        register).
 87 /r                     XCHG r/m16, r16              MR     Valid        Valid       Exchange r16 with word from r/m16.
 87 /r                     XCHG r16, r/m16              RM     Valid        Valid       Exchange word from r/m16 with r16.
 87 /r                     XCHG r/m32, r32              MR     Valid        Valid       Exchange r32 with doubleword from r/m32.
 REX.W + 87 /r             XCHG r/m64, r64              MR     Valid        N.E.        Exchange r64 with quadword from r/m64.
 87 /r                     XCHG r32, r/m32              RM     Valid        Valid       Exchange doubleword from r/m32 with r32.
 REX.W + 87 /r             XCHG r64, r/m64              RM     Valid        N.E.        Exchange quadword from r/m64 with r64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                     Operand 2                      Operand 3                     Operand 4
     O            AX/EAX/RAX (r, w)               opcode + rd (r, w)                   NA                             NA
     O             opcode + rd (r, w)            AX/EAX/RAX (r, w)                     NA                             NA
     MR            ModRM:r/m (r, w)                 ModRM:reg (r)                      NA                             NA
     RM             ModRM:reg (w)                   ModRM:r/m (r)                      NA                             NA


Description
Exchanges the contents of the destination (first) and source (second) operands. The operands can be two general-
purpose registers or a register and a memory location. If a memory operand is referenced, the processor's locking
protocol is automatically implemented for the duration of the exchange operation, regardless of the presence or
absence of the LOCK prefix or of the value of the IOPL. (See the LOCK prefix description in this chapter for more
information on the locking protocol.)
This instruction is useful for implementing semaphores or similar data structures for process synchronization. (See
"Bus Locking" in Chapter 8 of the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, for
more information on bus locking.)
The XCHG instruction can also be used instead of the BSWAP instruction for 16-bit operands.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.



                                                        NOTE
         XCHG (E)AX, (E)AX (encoded instruction byte is 90H) is an alias for NOP regardless of data size
         prefixes, including REX.W.

Operation
TEMP <- DEST;
DEST <- SRC;
SRC <- TEMP;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                 If either operand is in a non-writable segment.
                       If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                    If a memory operand effective address is outside the SS segment limit.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                 If the memory address is in a non-canonical form.
#PF(fault-code)        If a page fault occurs.
#AC(0)                 If alignment checking is enabled and an unaligned memory reference is made while the
                       current privilege level is 3.
#UD                    If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: XEND
description:
XEND - Transactional End
 Opcode/Instruction              Op/    64/32bit      CPUID     Description
                                 En     Mode          Feature
                                        Support       Flag
 0F 01 D5                        A      V/V           RTM       Specifies the end of an RTM code region.
 XEND



                                                Instruction Operand Encoding
  Op/En              Operand 1                       Operand2                   Operand3                     Operand4
     A                  NA                             NA                           NA                           NA


Description
The instruction marks the end of an RTM code region. If this corresponds to the outermost scope (that is, including
this XEND instruction, the number of XBEGIN instructions is the same as number of XEND instructions), the logical
processor will attempt to commit the logical processor state atomically. If the commit fails, the logical processor will
rollback all architectural register and memory updates performed during the RTM execution. The logical processor
will resume execution at the fallback address computed from the outermost XBEGIN instruction. The EAX register
is updated to reflect RTM abort information.
XEND executed outside a transactional region will cause a #GP (General Protection Fault).

Operation
XEND
IF (RTM_ACTIVE = 0) THEN
    SIGNAL #GP
ELSE
    RTM_NEST_COUNT--
    IF (RTM_NEST_COUNT = 0) THEN
         Try to commit transaction
         IF fail to commit transactional execution
               THEN
                     GOTO RTM_ABORT_PROCESSING;
               ELSE (* commit success *)
                     RTM_ACTIVE <- 0
         FI;
    FI;
FI;

(* For any RTM abort condition encountered during RTM execution *)
RTM_ABORT_PROCESSING:
    Restore architectural register state
    Discard memory updates performed in transaction
    Update EAX with status
    RTM_NEST_COUNT <- 0
    RTM_ACTIVE <- 0
    IF 64-bit Mode
         THEN
              RIP <- fallbackRIP
         ELSE
              EIP <- fallbackEIP
    FI;
END




Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
XEND:         void _xend( void );

SIMD Floating-Point Exceptions
None

Other Exceptions
#UD                        CPUID.(EAX=7, ECX=0):EBX.RTM[bit 11] = 0.
                           If LOCK or 66H or F2H or F3H prefix is used.
#GP(0)                     If RTM_ACTIVE = 0.






platform: x86_64
mnem: XGETBV
description:
XGETBV-Get Value of Extended Control Register
 Opcode                     Instruction                    Op/   64-Bit   Compat/ Description
                                                           En    Mode     Leg Mode
 0F 01 D0                   XGETBV                         NP    Valid    Valid      Reads an XCR specified by ECX into EDX:EAX.



                                                   Instruction Operand Encoding
   Op/En                 Operand 1                    Operand 2                   Operand 3                      Operand 4
      NP                     NA                            NA                        NA                              NA


Description
Reads the contents of the extended control register (XCR) specified in the ECX register into registers EDX:EAX. (On
processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register is
loaded with the high-order 32 bits of the XCR and the EAX register is loaded with the low-order 32 bits. (On proces-
sors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If fewer
than 64 bits are implemented in the XCR being read, the values returned to EDX:EAX in unimplemented bit loca-
tions are undefined.
XCR0 is supported on any processor that supports the XGETBV instruction. If
CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 1, executing XGETBV with ECX = 1 returns in EDX:EAX the logical-
AND of XCR0 and the current value of the XINUSE state-component bitmap. This allows software to discover the
state of the init optimization used by XSAVEOPT and XSAVES. See Chapter 13, "Managing State Using the XSAVE
Feature Set," in Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1.
Use of any other value for ECX results in a general-protection (#GP) exception.

Operation
EDX:EAX <- XCR[ECX];

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
XGETBV:         unsigned __int64 _xgetbv( unsigned int);

Protected Mode Exceptions
#GP(0)                    If an invalid XCR is specified in ECX (includes ECX = 1 if
                          CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).
#UD                       If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                          If CR4.OSXSAVE[bit 18] = 0.
                          If the LOCK prefix is used.
                          If 66H, F3H or F2H prefix is used.

Real-Address Mode Exceptions
#GP(0)                    If an invalid XCR is specified in ECX (includes ECX = 1 if
                          CPUID.(EAX=0DH,ECX=1):EAX.XG1[bit 2] = 0).
#UD                       If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                          If CR4.OSXSAVE[bit 18] = 0.
                          If the LOCK prefix is used.
                          If 66H, F3H or F2H prefix is used.




Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: XLAT
description:
XLAT/XLATB-Table Look-up Translation
 Opcode                  Instruction                 Op/     64-Bit   Compat/ Description
                                                     En      Mode     Leg Mode
 D7                      XLAT m8                     NP      Valid    Valid        Set AL to memory byte DS:[(E)BX + unsigned
                                                                                   AL].
 D7                      XLATB                       NP      Valid    Valid       Set AL to memory byte DS:[(E)BX + unsigned
                                                                                  AL].
 REX.W + D7              XLATB                       NP      Valid    N.E.         Set AL to memory byte [RBX + unsigned AL].



                                              Instruction Operand Encoding
   Op/En             Operand 1                   Operand 2                    Operand 3                    Operand 4
      NP                NA                          NA                           NA                           NA


Description
Locates a byte entry in a table in memory, using the contents of the AL register as a table index, then copies the
contents of the table entry back into the AL register. The index in the AL register is treated as an unsigned integer.
The XLAT and XLATB instructions get the base address of the table in memory from either the DS:EBX or the DS:BX
registers (depending on the address-size attribute of the instruction, 32 or 16, respectively). (The DS segment may
be overridden with a segment override prefix.)
At the assembly-code level, two forms of this instruction are allowed: the "explicit-operand" form and the "no-
operand" form. The explicit-operand form (specified with the XLAT mnemonic) allows the base address of the table
to be specified explicitly with a symbol. This explicit-operands form is provided to allow documentation; however,
note that the documentation provided by this form can be misleading. That is, the symbol does not have to specify
the correct base address. The base address is always specified by the DS:(E)BX registers, which must be loaded
correctly before the XLAT instruction is executed.
The no-operands form (XLATB) provides a "short form" of the XLAT instructions. Here also the processor assumes
that the DS:(E)BX registers contain the base address of the table.
In 64-bit mode, operation is similar to that in legacy or compatibility mode. AL is used to specify the table index
(the operand size is fixed at 8 bits). RBX, however, is used to specify the table's base address. See the summary
chart at the beginning of this section for encoding data and limits.

Operation
IF AddressSize = 16
    THEN
        AL <- (DS:BX + ZeroExtend(AL));
    ELSE IF (AddressSize = 32)
        AL <- (DS:EBX + ZeroExtend(AL)); FI;
    ELSE (AddressSize = 64)
        AL <- (RBX + ZeroExtend(AL));
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.



#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                  If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                  If the memory address is in a non-canonical form.
#PF(fault-code)         If a page fault occurs.
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: XOR
description:
XOR-Logical Exclusive OR
 Opcode                     Instruction                 Op/    64-Bit      Compat/ Description
                                                        En     Mode        Leg Mode
 34 ib                     XOR AL, imm8                 I      Valid       Valid        AL XOR imm8.
 35 iw                     XOR AX, imm16                I      Valid       Valid        AX XOR imm16.
 35 id                     XOR EAX, imm32               I      Valid       Valid        EAX XOR imm32.
 REX.W + 35 id             XOR RAX, imm32               I      Valid       N.E.         RAX XOR imm32 (sign-extended).
 80 /6 ib                  XOR r/m8, imm8               MI     Valid       Valid        r/m8 XOR imm8.
 REX + 80 /6 ib            XOR r/m8*, imm8              MI     Valid       N.E.         r/m8 XOR imm8.
 81 /6 iw                  XOR r/m16, imm16             MI     Valid       Valid        r/m16 XOR imm16.
 81 /6 id                  XOR r/m32, imm32             MI     Valid       Valid        r/m32 XOR imm32.
 REX.W + 81 /6 id          XOR r/m64, imm32             MI     Valid       N.E.         r/m64 XOR imm32 (sign-extended).
 83 /6 ib                  XOR r/m16, imm8              MI     Valid       Valid        r/m16 XOR imm8 (sign-extended).
 83 /6 ib                  XOR r/m32, imm8              MI     Valid       Valid        r/m32 XOR imm8 (sign-extended).
 REX.W + 83 /6 ib          XOR r/m64, imm8              MI     Valid       N.E.         r/m64 XOR imm8 (sign-extended).
 30 /r                     XOR r/m8, r8                 MR     Valid       Valid        r/m8 XOR r8.
 REX + 30 /r               XOR r/m8*, r8*               MR     Valid       N.E.         r/m8 XOR r8.
 31 /r                     XOR r/m16, r16               MR     Valid       Valid        r/m16 XOR r16.
 31 /r                     XOR r/m32, r32               MR     Valid       Valid        r/m32 XOR r32.
 REX.W + 31 /r             XOR r/m64, r64               MR     Valid       N.E.         r/m64 XOR r64.
 32 /r                     XOR r8, r/m8                 RM     Valid       Valid        r8 XOR r/m8.
 REX + 32 /r               XOR r8*, r/m8*               RM     Valid       N.E.         r8 XOR r/m8.
 33 /r                     XOR r16, r/m16               RM     Valid       Valid        r16 XOR r/m16.
 33 /r                     XOR r32, r/m32               RM     Valid       Valid        r32 XOR r/m32.
 REX.W + 33 /r             XOR r64, r/m64               RM     Valid       N.E.         r64 XOR r/m64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                   Operand 2                       Operand 3                     Operand 4
         I          AL/AX/EAX/RAX                 imm8/16/32                          NA                             NA
     MI             ModRM:r/m (r, w)              imm8/16/32                          NA                             NA
    MR              ModRM:r/m (r, w)             ModRM:reg (r)                        NA                             NA
    RM              ModRM:reg (r, w)             ModRM:r/m (r)                        NA                             NA


Description
Performs a bitwise exclusive OR (XOR) operation on the destination (first) and source (second) operands and
stores the result in the destination operand location. The source operand can be an immediate, a register, or a
memory location; the destination operand can be a register or a memory location. (However, two memory oper-
ands cannot be used in one instruction.) Each bit of the result is 1 if the corresponding bits of the operands are
different; each bit is 0 if the corresponding bits are the same.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.





In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Using a
REX prefix in the form of REX.W promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.

Operation
DEST <- DEST XOR SRC;

Flags Affected
The OF and CF flags are cleared; the SF, ZF, and PF flags are set according to the result. The state of the AF flag is
undefined.

Protected Mode Exceptions
#GP(0)                     If the destination operand points to a non-writable segment.
                           If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                           If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                     If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made while the
                           current privilege level is 3.
#UD                        If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                        If a memory operand effective address is outside the SS segment limit.
#UD                        If the LOCK prefix is used but the destination is not a memory operand.

Virtual-8086 Mode Exceptions
#GP(0)                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                     If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made.
#UD                        If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                     If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                     If the memory address is in a non-canonical form.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If alignment checking is enabled and an unaligned memory reference is made while the
                           current privilege level is 3.
#UD                        If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: XORPD
description:
XORPD-Bitwise Logical XOR of Packed Double Precision Floating-Point Values
 Opcode/                                  Op /      64/32       CPUID          Description
 Instruction                              En        bit Mode    Feature
                                                    Support     Flag
 66 0F 57/r                                         V/V         SSE2           Return the bitwise logical XOR of packed double-
                                          RM
 XORPD xmm1, xmm2/m128                                                         precision floating-point values in xmm1 and xmm2/mem.
 VEX.NDS.128.66.0F.WIG 57 /r                        V/V         AVX            Return the bitwise logical XOR of packed double-
 VXORPD xmm1,xmm2,                        RVM                                  precision floating-point values in xmm2 and xmm3/mem.
 xmm3/m128
 VEX.NDS.256.66.0F.WIG 57 /r              RVM       V/V         AVX            Return the bitwise logical XOR of packed double-
 VXORPD ymm1, ymm2,                                                            precision floating-point values in ymm2 and ymm3/mem.
 ymm3/m256
 EVEX.NDS.128.66.0F.W1 57 /r              FV        V/V         AVX512VL       Return the bitwise logical XOR of packed double-
 VXORPD xmm1 {k1}{z}, xmm2,                                     AVX512DQ       precision floating-point values in xmm2 and
 xmm3/m128/m64bcst                                                             xmm3/m128/m64bcst subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 57 /r              FV        V/V         AVX512VL       Return the bitwise logical XOR of packed double-
 VXORPD ymm1 {k1}{z}, ymm2,                                     AVX512DQ       precision floating-point values in ymm2 and
 ymm3/m256/m64bcst                                                             ymm3/m256/m64bcst subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 57 /r              FV        V/V         AVX512DQ       Return the bitwise logical XOR of packed double-
 VXORPD zmm1 {k1}{z}, zmm2,                                                    precision floating-point values in zmm2 and
 zmm3/m512/m64bcst                                                             zmm3/m512/m64bcst subject to writemask k1.



                                                     Instruction Operand Encoding
          Op/En                     Operand 1                   Operand 2                  Operand 3                    Operand 4
            RM                   ModRM:reg (r, w)              ModRM:r/m (r)                  NA                            NA
          RVM                     ModRM:reg (w)                VEX.vvvv (r)              ModRM:r/m (r)                      NA
            FV                    ModRM:reg (w)                EVEX.vvvv (r)             ModRM:r/m (r)                      NA

Description
Performs a bitwise logical XOR of the two, four or eight packed double-precision floating-point values from the first
source operand and the second source operand, and stores the result in the destination operand
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM
register or a vector memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination
are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination
are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.

Operation
VXORPD (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN



             IF (EVEX.b == 1) AND (SRC2 *is memory*)
                  THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[63:0];
                  ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[i+63:i];
             FI;
         ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                      DEST[i+63:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VXORPD (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[191:128] <- SRC1[191:128] BITWISE XOR SRC2[191:128]
DEST[255:192] <- SRC1[255:192] BITWISE XOR SRC2[255:192]
DEST[MAX_VL-1:256] <- 0

VXORPD (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0] BITWISE XOR SRC2[63:0]
DEST[127:64] <- SRC1[127:64] BITWISE XOR SRC2[127:64]
DEST[MAX_VL-1:128] <- 0

XORPD (128-bit Legacy SSE version)
DEST[63:0] <- DEST[63:0] BITWISE XOR SRC[63:0]
DEST[127:64] <- DEST[127:64] BITWISE XOR SRC[127:64]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VXORPD __m512d _mm512_xor_pd (__m512d a, __m512d b);
VXORPD __m512d _mm512_mask_xor_pd (__m512d a, __mmask8 m, __m512d b);
VXORPD __m512d _mm512_maskz_xor_pd (__mmask8 m, __m512d a);
VXORPD __m256d _mm256_xor_pd (__m256d a, __m256d b);
VXORPD __m256d _mm256_mask_xor_pd (__m256d a, __mmask8 m, __m256d b);
VXORPD __m256d _mm256_maskz_xor_pd (__mmask8 m, __m256d a);
XORPD __m128d _mm_xor_pd (__m128d a, __m128d b);
VXORPD __m128d _mm_mask_xor_pd (__m128d a, __mmask8 m, __m128d b);
VXORPD __m128d _mm_maskz_xor_pd (__mmask8 m, __m128d a);

SIMD Floating-Point Exceptions
None





Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4.






platform: x86_64
mnem: XORPS
description:
XORPS-Bitwise Logical XOR of Packed Single Precision Floating-Point Values
 Opcode/                                       Op /    64/32         CPUID      Description
 Instruction                                   En      bit Mode      Feature
                                                       Support       Flag
 0F 57 /r                                      RM      V/V           SSE        Return the bitwise logical XOR of packed single-
 XORPS xmm1, xmm2/m128                                                          precision floating-point values in xmm1 and
                                                                                xmm2/mem.
 VEX.NDS.128.0F.WIG 57 /r                      RVM     V/V           AVX        Return the bitwise logical XOR of packed single-
 VXORPS xmm1,xmm2, xmm3/m128                                                    precision floating-point values in xmm2 and
                                                                                xmm3/mem.
 VEX.NDS.256.0F.WIG 57 /r                      RVM     V/V           AVX        Return the bitwise logical XOR of packed single-
 VXORPS ymm1, ymm2, ymm3/m256                                                   precision floating-point values in ymm2 and
                                                                                ymm3/mem.
 EVEX.NDS.128.0F.W0 57 /r                      FV      V/V           AVX512VL   Return the bitwise logical XOR of packed single-
 VXORPS xmm1 {k1}{z}, xmm2,                                          AVX512DQ   precision floating-point values in xmm2 and
 xmm3/m128/m32bcst                                                              xmm3/m128/m32bcst subject to writemask k1.
 EVEX.NDS.256.0F.W0 57 /r                      FV      V/V           AVX512VL   Return the bitwise logical XOR of packed single-
 VXORPS ymm1 {k1}{z}, ymm2,                                          AVX512DQ   precision floating-point values in ymm2 and
 ymm3/m256/m32bcst                                                              ymm3/m256/m32bcst subject to writemask k1.
 EVEX.NDS.512.0F.W0 57 /r                      FV      V/V           AVX512DQ   Return the bitwise logical XOR of packed single-
 VXORPS zmm1 {k1}{z}, zmm2,                                                     precision floating-point values in zmm2 and
 zmm3/m512/m32bcst                                                              zmm3/m512/m32bcst subject to writemask k1.



                                                      Instruction Operand Encoding
           Op/En                     Operand 1                    Operand 2             Operand 3                   Operand 4
            RM                    ModRM:reg (r, w)              ModRM:r/m (r)                 NA                       NA
           RVM                     ModRM:reg (w)                   VEX.vvvv           ModRM:r/m (r)                    NA
            FV                     ModRM:reg (w)                  EVEX.vvvv           ModRM:r/m (r)                    NA

Description
Performs a bitwise logical XOR of the four, eight or sixteen packed single-precision floating-point values from the
first source operand and the second source operand, and stores the result in the destination operand
EVEX.512 encoded version: The first source operand is a ZMM register. The second source operand can be a ZMM
register or a vector memory location. The destination operand is a ZMM register conditionally updated with
writemask k1.
VEX.256 and EVEX.256 encoded versions: The first source operand is a YMM register. The second source operand
is a YMM register or a 256-bit memory location. The destination operand is a YMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:256) of the corresponding ZMM register destination
are zeroed.
VEX.128 and EVEX.128 encoded versions: The first source operand is an XMM register. The second source operand
is an XMM register or 128-bit memory location. The destination operand is an XMM register (conditionally updated
with writemask k1 in case of EVEX). The upper bits (MAX_VL-1:128) of the corresponding ZMM register destination
are zeroed.
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (MAX_VL-1:128) of the corresponding
register destination are unmodified.





Operation
VXORPS (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b == 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[31:0];
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[i+31:i];
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] = 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VXORPS (VEX.256 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[159:128] <- SRC1[159:128] BITWISE XOR SRC2[159:128]
DEST[191:160] <- SRC1[191:160] BITWISE XOR SRC2[191:160]
DEST[223:192] <- SRC1[223:192] BITWISE XOR SRC2[223:192]
DEST[255:224] <- SRC1[255:224] BITWISE XOR SRC2[255:224].
DEST[MAX_VL-1:256] <- 0

VXORPS (VEX.128 encoded version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[MAX_VL-1:128] <- 0

XORPS (128-bit Legacy SSE version)
DEST[31:0] <- SRC1[31:0] BITWISE XOR SRC2[31:0]
DEST[63:32] <- SRC1[63:32] BITWISE XOR SRC2[63:32]
DEST[95:64] <- SRC1[95:64] BITWISE XOR SRC2[95:64]
DEST[127:96] <- SRC1[127:96] BITWISE XOR SRC2[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VXORPS __m512 _mm512_xor_ps (__m512 a, __m512 b);
VXORPS __m512 _mm512_mask_xor_ps (__m512 a, __mmask16 m, __m512 b);
VXORPS __m512 _mm512_maskz_xor_ps (__mmask16 m, __m512 a);
VXORPS __m256 _mm256_xor_ps (__m256 a, __m256 b);
VXORPS __m256 _mm256_mask_xor_ps (__m256 a, __mmask8 m, __m256 b);
VXORPS __m256 _mm256_maskz_xor_ps (__mmask8 m, __m256 a);
XORPS __m128 _mm_xor_ps (__m128 a, __m128 b);
VXORPS __m128 _mm_mask_xor_ps (__m128 a, __mmask8 m, __m128 b);


VXORPS __m128 _mm_maskz_xor_ps (__mmask8 m, __m128 a);

SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instructions, see Exceptions Type 4.
EVEX-encoded instructions, see Exceptions Type E4.






platform: x86_64
mnem: XRSTOR
description:
XRSTOR-Restore Processor Extended States
 Opcode                   Instruction                 Op/   64-Bit      Compat/ Description
                                                      En    Mode        Leg Mode
 0F AE /5                 XRSTOR mem                  M     Valid       Valid       Restore state components specified by
                                                                                    EDX:EAX from mem.
 REX.W+ 0F AE /5          XRSTOR64 mem                M     Valid       N.E.        Restore state components specified by
                                                                                    EDX:EAX from mem.



                                                Instruction Operand Encoding
    Op/En            Operand 1                     Operand 2                    Operand 3                      Operand 4
     M              ModRM:r/m (r)                     NA                           NA                              NA


Description
Performs a full or partial restore of processor state components from the XSAVE area located at the memory
address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, "XSAVE Area," of Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1.
Section 13.8, "Operation of XRSTOR," of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume
1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a high-
level outline:
.   Execution of XRSTOR may take one of two forms: standard and compacted. Bit 63 of the XCOMP_BV field in the
    XSAVE header determines which form is used: value 0 specifies the standard form, while value 1 specifies the
    compacted form.
.   If RFBM[i] = 0, XRSTOR does not update state component i.1
.   If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTOR initializes state
    component i.
.   If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTOR loads state component i from the XSAVE area.
.   The standard form of XRSTOR treats MXCSR (which is part of state component 1 - SSE) differently from the
    XMM registers. If either form attempts to load MXCSR with an illegal value, a general-protection exception
    (#GP) occurs.
.   XRSTOR loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of
    XSAVEOPT or XSAVES.
.   Immediately following an execution of XRSTOR, the processor tracks as in-use (not in initial configuration) any
    state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component
    i for which RFBM[i] = 0.
Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protec-
tion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.

Operation

RFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */
COMPMASK <- XCOMP_BV field from XSAVE header;
RSTORMASK <- XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
     THEN VMXNR <- 1;

1. There is an exception if RFBM[1] = 0 and RFBM[2] = 1. In this case, the standard form of XRSTOR will load MXCSR from memory,
   even though MXCSR is part of state component 1 - SSE. The compacted form of XRSTOR does not make this exception.



    ELSE VMXNR <- 0;
FI;
LAXA <- linear address of XSAVE area;

IF COMPMASK[63] = 0
    THEN
        /* Standard form of XRSTOR */
        If RFBM[0] = 1
             THEN
                  IF RSTORMASK[0] = 1
                       THEN load x87 state from legacy region of XSAVE area;
                       ELSE initialize x87 state;
                  FI;
        FI;
        If RFBM[1] = 1
             THEN
                  IF RSTORMASK[1] = 1
                       THEN load XMM registers from legacy region of XSAVE area;
                       ELSE set all XMM registers to 0;
                  FI;
        FI;
        If RFBM[2] = 1
             THEN
                  IF RSTORMASK[2] = 1
                       THEN load AVX state from extended region (standard format) of XSAVE area;
                       ELSE initialize AVX state;
                  FI;
        FI;
        If RFBM[1] = 1 or RFBM[2] = 1
             THEN load MXCSR from legacy region of XSAVE area;
        FI;
FI;
    ELSE
        /* Compacted form of XRSTOR */
        IF CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0
             THEN      /* compacted form not supported */
                  #GP(0);
        FI;
        If RFBM[0] = 1
             THEN
                  IF RSTORMASK[0] = 1
                       THEN load x87 state from legacy region of XSAVE area;
                       ELSE initialize x87 state;
                  FI;
        FI;
        If RFBM[1] = 1
             THEN
                  IF RSTORMASK[1] = 1
                       THEN load SSE state from legacy region of XSAVE area;
                       ELSE initialize SSE state;
                  FI;
        FI;
        If RFBM[2] = 1
             THEN



                    IF RSTORMASK[2] = 1
                         THEN load AVX state from extended region (compacted format) of XSAVE area;
                         ELSE initialize AVX state;
                    FI;
      FI;
FI;
XRSTOR_INFO <- (CPL,VMXNR,LAXA,COMPMASK);

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
XRSTOR:         void _xrstor( void * , unsigned __int64);
XRSTOR:         void _xrstor64( void * , unsigned __int64);

Protected Mode Exceptions
#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                          If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
                          CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
                          If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                          XSTATE_BV field of the XSAVE header is 1.
                          If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
                          If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                          XCOMP_BV field of the XSAVE header is 1.
                          If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
                          and the corresponding bit in the XSTATE_BV field is 1.
                          If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
                          If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#NM                       If CR0.TS[bit 3] = 1.
#UD                       If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                          If CR4.OSXSAVE[bit 18] = 0.
                          If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                       If this exception is disabled a general protection exception (#GP) is signaled if the memory
                          operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                          exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                          vary with implementation, as follows. In all implementations where #AC is not signaled, a
                          general protection exception is signaled in its place. In addition, the width of the alignment
                          check may also vary with implementation. For instance, for a given implementation, an align-
                          ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                          tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                          misalignments).

Real-Address Mode Exceptions
#GP                       If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                          If any part of the operand lies outside the effective address space from 0 to FFFFH.
                          If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
                          CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.




                       If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                       XSTATE_BV field of the XSAVE header is 1.
                       If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
                       If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                       XCOMP_BV field of the XSAVE header is 1.
                       If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
                       and the corresponding bit in the XSTATE_BV field is 1.
                       If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
                       If attempting to write any reserved bits of the MXCSR register with 1.
#NM                    If CR0.TS[bit 3] = 1.
#UD                    If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                       If CR4.OSXSAVE[bit 18] = 0.
                       If any of the LOCK, 66H, F3H or F2H prefixes is used.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                 If a memory address is in a non-canonical form.
                       If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                       If bit 63 of the XCOMP_BV field of the XSAVE header is 1 and
                       CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
                       If the standard form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                       XSTATE_BV field of the XSAVE header is 1.
                       If the standard form is executed and bytes 23:8 of the XSAVE header are not all zero.
                       If the compacted form is executed and a bit in XCR0 is 0 and the corresponding bit in the
                       XCOMP_BV field of the XSAVE header is 1.
                       If the compacted form is executed and a bit in the XCOMP_BV field in the XSAVE header is 0
                       and the corresponding bit in the XSTATE_BV field is 1.
                       If the compacted form is executed and bytes 63:16 of the XSAVE header are not all zero.
                       If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)                 If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)        If a page fault occurs.
#NM                    If CR0.TS[bit 3] = 1.
#UD                    If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                       If CR4.OSXSAVE[bit 18] = 0.
                       If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                    If this exception is disabled a general protection exception (#GP) is signaled if the memory
                       operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                       exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                       vary with implementation, as follows. In all implementations where #AC is not signaled, a
                       general protection exception is signaled in its place. In addition, the width of the alignment
                       check may also vary with implementation. For instance, for a given implementation, an align-
                       ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                       tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                       misalignments).






platform: x86_64
mnem: XRSTORS
description:
XRSTORS-Restore Processor Extended States Supervisor
 Opcode                 Instruction               Op/   64-Bit      Compat/ Description
                                                  En    Mode        Leg Mode
 0F C7 /3               XRSTORS mem               M     Valid       Valid         Restore state components specified by
                                                                                  EDX:EAX from mem.
 REX.W+ 0F C7 /3        XRSTORS64 mem             M     Valid       N.E.          Restore state components specified by
                                                                                  EDX:EAX from mem.



                                             Instruction Operand Encoding
    Op/En           Operand 1                  Operand 2                    Operand 3                      Operand 4
     M             ModRM:r/m (r)                   NA                           NA                            NA


Description
Performs a full or partial restore of processor state components from the XSAVE area located at the memory
address specified by the source operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components restored correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and the logical-OR of XCR0 with the IA32_XSS MSR. XRSTORS may be executed only if
CPL = 0.
The format of the XSAVE area is detailed in Section 13.4, "XSAVE Area," of Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1.
Section 13.12, "Operation of XRSTORS," of Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 1 provides a detailed description of the operation of the XRSTOR instruction. The following items provide a
high-level outline:
.   Execution of XRSTORS is similar to that of the compacted form of XRSTOR; XRSTORS cannot restore from an
    XSAVE area in which the extended region is in the standard format (see Section 13.4.3, "Extended Region of an
    XSAVE Area").
.   XRSTORS differs from XRSTOR in that it can restore state components corresponding to bits set in the
    IA32_XSS MSR.
.   If RFBM[i] = 0, XRSTORS does not update state component i.
.   If RFBM[i] = 1 and bit i is clear in the XSTATE_BV field in the XSAVE header, XRSTORS initializes state
    component i.
.   If RFBM[i] = 1 and XSTATE_BV[i] = 1, XRSTORS loads state component i from the XSAVE area.
.   If XRSTORS attempts to load MXCSR with an illegal value, a general-protection exception (#GP) occurs.
.   XRSTORS loads the internal value XRSTOR_INFO, which may be used to optimize a subsequent execution of
    XSAVEOPT or XSAVES.
.   Immediately following an execution of XRSTORS, the processor tracks as in-use (not in initial configuration)
    any state component i for which RFBM[i] = 1 and XSTATE_BV[i] = 1; it tracks as modified any state component
    i for which RFBM[i] = 0.
Use of a source operand not aligned to 64-byte boundary (for 64-bit and 32-bit modes) results in a general-protec-
tion (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.

Operation

RFBM <- (XCR0 OR IA32_XSS) AND EDX:EAX;         /* bitwise logical OR and AND */
COMPMASK <- XCOMP_BV field from XSAVE header;
RSTORMASK <- XSTATE_BV field from XSAVE header;
IF in VMX non-root operation
     THEN VMXNR <- 1;
     ELSE VMXNR <- 0;
FI;


LAXA <- linear address of XSAVE area;

If RFBM[0] = 1
    THEN
        IF RSTORMASK[0] = 1
             THEN load x87 state from legacy region of XSAVE area;
             ELSE initialize x87 state;
        FI;
FI;
If RFBM[1] = 1
    THEN
        IF RSTORMASK[1] = 1
             THEN load SSE state from legacy region of XSAVE area;
             ELSE initialize SSE state;
        FI;
FI;
If RFBM[2] = 1
    THEN
        IF RSTORMASK[2] = 1
             THEN load AVX state from extended region (compacted format) of XSAVE area;
             ELSE initialize AVX state;
        FI;
FI;
XRSTOR_INFO <- (CPL,VMXNR,LAXA,COMPMASK);

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
XRSTORS:      void _xrstors( void * , unsigned __int64);
XRSTORS64: void _xrstors64( void * , unsigned __int64);

Protected Mode Exceptions
#GP(0)                  If CPL > 0.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                        If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
                        If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
                        If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
                        XSTATE_BV field is 1.
                        If bytes 63:16 of the XSAVE header are not all zero.
                        If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#NM                     If CR0.TS[bit 3] = 1.
#UD                     If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
                        If CR4.OSXSAVE[bit 18] = 0.
                        If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                     If this exception is disabled a general protection exception (#GP) is signaled if the memory
                        operand is not aligned on a 16-byte boundary, as described above. If the alignment check



                    exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                    vary with implementation, as follows. In all implementations where #AC is not signaled, a #GP
                    is signaled in its place. In addition, the width of the alignment check may also vary with imple-
                    mentation. For instance, for a given implementation, an alignment check exception might be
                    signaled for a 2-byte misalignment, whereas a #GP might be signaled for all other misalign-
                    ments (4-, 8-, or 16-byte misalignments).

Real-Address Mode Exceptions
#GP                 If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                    If any part of the operand lies outside the effective address space from 0 to FFFFH.
                    If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
                    If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
                    If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
                    XSTATE_BV field is 1.
                    If bytes 63:16 of the XSAVE header are not all zero.
                    If attempting to write any reserved bits of the MXCSR register with 1.
#NM                 If CR0.TS[bit 3] = 1.
#UD                 If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
                    If CR4.OSXSAVE[bit 18] = 0.
                    If any of the LOCK, 66H, F3H or F2H prefixes is used.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)              If CPL > 0.
                    If a memory address is in a non-canonical form.
                    If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                    If bit 63 of the XCOMP_BV field of the XSAVE header is 0.
                    If a bit in XCR0 is 0 and the corresponding bit in the XCOMP_BV field of the XSAVE header is 1.
                    If a bit in the XCOMP_BV field in the XSAVE header is 0 and the corresponding bit in the
                    XSTATE_BV field is 1.
                    If bytes 63:16 of the XSAVE header are not all zero.
                    If attempting to write any reserved bits of the MXCSR register with 1.
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#NM                 If CR0.TS[bit 3] = 1.
#UD                 If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSS[bit 3] = 0.
                    If CR4.OSXSAVE[bit 18] = 0.
                    If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                 If this exception is disabled a general protection exception (#GP) is signaled if the memory
                    operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                    exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                    vary with implementation, as follows. In all implementations where #AC is not signaled, a
                    general protection exception is signaled in its place. In addition, the width of the alignment
                    check may also vary with implementation. For instance, for a given implementation, an align-
                    ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-



                        tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                        misalignments).






platform: x86_64
mnem: XSAVE
description:
XSAVE-Save Processor Extended States
 Opcode                  Instruction                  Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 0F AE /4                XSAVE mem                    M     Valid    Valid      Save state components specified by EDX:EAX
                                                                                to mem.
 REX.W+ 0F AE /4         XSAVE64 mem                  M     Valid    N.E.       Save state components specified by EDX:EAX
                                                                                to mem.



                                                Instruction Operand Encoding
    Op/En             Operand 1                     Operand 2                Operand 3                  Operand 4
     M              ModRM:r/m (w)                      NA                       NA                          NA


Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, "XSAVE Area," of Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1.
Section 13.7, "Operation of XSAVE," of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1
provides a detailed description of the operation of the XSAVE instruction. The following items provide a high-level
outline:
.   XSAVE saves state component i if and only if RFBM[i] = 1.1
.   XSAVE does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, "Legacy
    Region of an XSAVE Area").
.   XSAVE reads the XSTATE_BV field of the XSAVE header (see Section 13.4.2, "XSAVE Header") and writes a
    modified value back to memory as follows. If RFBM[i] = 1, XSAVE writes XSTATE_BV[i] with the value of
    XINUSE[i]. (XINUSE is a bitmap by which the processor tracks the status of various state components. See
    Section 13.6, "Processor Tracking of XSAVE-Managed State.") If RFBM[i] = 0, XSAVE writes XSTATE_BV[i] with
    the value that it read from memory (it does not modify the bit). XSAVE does not write to any part of the XSAVE
    header other than the XSTATE_BV field.
.   XSAVE always uses the standard format of the extended region of the XSAVE area (see Section 13.4.3,
    "Extended Region of an XSAVE Area").
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.

Operation

RFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */
OLD_BV <- XSTATE_BV field from XSAVE header;

IF RFBM[0] = 1
    THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1
    THEN store XMM registers into legacy region of XSAVE area;
FI;


1. An exception is made for MXCSR and MXCSR_MASK, which belong to state component 1 - SSE. XSAVE saves these values to mem-
   ory if either RFBM[1] or RFBM[2] is 1.



IF RFBM[2] = 1
    THEN store AVX state into extended region of XSAVE area;
FI;
IF RFBM[1] = 1 or RFBM[2] = 1
    THEN store MXCSR and MXCSR_MASK into legacy region of XSAVE area;
FI;

XSTATE_BV field in XSAVE header <- (OLD_BV AND ~RFBM) OR (XINUSE AND RFBM);

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
XSAVE:       void _xsave( void * , unsigned __int64);
XSAVE:       void _xsave64( void * , unsigned __int64);

Protected Mode Exceptions
#GP(0)                 If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                       If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)                 If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)        If a page fault occurs.
#NM                    If CR0.TS[bit 3] = 1.
#UD                    If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                       If CR4.OSXSAVE[bit 18] = 0.
                       If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                    If this exception is disabled a general protection exception (#GP) is signaled if the memory
                       operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                       exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                       vary with implementation, as follows. In all implementations where #AC is not signaled, a
                       general protection exception is signaled in its place. In addition, the width of the alignment
                       check may also vary with implementation. For instance, for a given implementation, an align-
                       ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                       tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                       misalignments).

Real-Address Mode Exceptions
#GP                    If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                       If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM                    If CR0.TS[bit 3] = 1.
#UD                    If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                       If CR4.OSXSAVE[bit 18] = 0.
                       If any of the LOCK, 66H, F3H or F2H prefixes is used.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
                    If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#NM                 If CR0.TS[bit 3] = 1.
#UD                 If CPUID.01H:ECX.XSAVE[bit 26] = 0.
                    If CR4.OSXSAVE[bit 18] = 0.
                    If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                 If this exception is disabled a general protection exception (#GP) is signaled if the memory
                    operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                    exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                    vary with implementation, as follows. In all implementations where #AC is not signaled, a
                    general protection exception is signaled in its place. In addition, the width of the alignment
                    check may also vary with implementation. For instance, for a given implementation, an align-
                    ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                    tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                    misalignments).






platform: x86_64
mnem: XSAVEC
description:
XSAVEC-Save Processor Extended States with Compaction
 Opcode                   Instruction                    Op/    64-Bit   Compat/ Description
                                                         En     Mode     Leg Mode
 0F C7 /4                 XSAVEC mem                     M      Valid    Valid      Save state components specified by EDX:EAX
                                                                                    to mem with compaction.
 REX.W+ 0F C7 /4          XSAVEC64 mem                   M      Valid    N.E.       Save state components specified by EDX:EAX
                                                                                    to mem with compaction.



                                                 Instruction Operand Encoding
    Op/En              Operand 1                        Operand 2                Operand 3                    Operand 4
      M              ModRM:r/m (w)                         NA                       NA                            NA


Description
Performs a full or partial save of processor state components to the XSAVE area located at the memory address
specified by the destination operand. The implicit EDX:EAX register pair specifies a 64-bit instruction mask. The
specific state components saved correspond to the bits set in the requested-feature bitmap (RFBM), which is the
logical-AND of EDX:EAX and XCR0.
The format of the XSAVE area is detailed in Section 13.4, "XSAVE Area," of Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1.
Section 13.10, "Operation of XSAVEC," of Intel 64 and IA-32 Architectures Software Developer's Manual, Volume
1 provides a detailed description of the operation of the XSAVEC instruction. The following items provide a high-
level outline:
.   Execution of XSAVEC is similar to that of XSAVE. XSAVEC differs from XSAVE in that it uses compaction and that
    it may use the init optimization.
.   XSAVEC saves state component i if and only if RFBM[i] = 1 and XINUSE[i] = 1.1 (XINUSE is a bitmap by which
    the processor tracks the status of various state components. See Section 13.6, "Processor Tracking of XSAVE-
    Managed State.")
.   XSAVEC does not modify bytes 511:464 of the legacy region of the XSAVE area (see Section 13.4.1, "Legacy
    Region of an XSAVE Area").
.   XSAVEC writes the logical AND of RFBM and XINUSE to the XSTATE_BV field of the XSAVE header.2,3 (See
    Section 13.4.2, "XSAVE Header.") XSAVEC sets bit 63 of the XCOMP_BV field and sets bits 62:0 of that field to
    RFBM[62:0]. XSAVEC does not write to any parts of the XSAVE header other than the XSTATE_BV and
    XCOMP_BV fields.
.   XSAVEC always uses the compacted format of the extended region of the XSAVE area (see Section 13.4.3,
    "Extended Region of an XSAVE Area").
Use of a destination operand not aligned to 64-byte boundary (in either 64-bit or 32-bit modes) results in a
general-protection (#GP) exception. In 64-bit mode, the upper 32 bits of RDX and RAX are ignored.

Operation

RFBM <- XCR0 AND EDX:EAX; /* bitwise logical AND */
COMPMASK <- RFBM OR 80000000_00000000H;

IF RFBM[0] = 1 and XINUSE[0] = 1

1. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
   have its initial value of 1F80H. In this case, XSAVEC saves SSE state as long as RFBM[1] = 1.
2. Unlike XSAVE and XSAVEOPT, XSAVEC clears bits in the XSTATE_BV field that correspond to bits that are clear in RFBM.
3. There is an exception for state component 1 (SSE). MXCSR is part of SSE state, but XINUSE[1] may be 0 even if MXCSR does not
   have its initial value of 1F80H. In this case, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1.



    THEN store x87 state into legacy region of XSAVE area;
FI;
IF RFBM[1] = 1 and (XINUSE[1] = 1 or MXCSR != 1F80H)
    THEN store SSE state into legacy region of XSAVE area;
FI;
IF RFBM[2] = 1 AND XINUSE[2] = 1
    THEN store AVX state into extended region of XSAVE area;
FI;

XSTATE_BV field in XSAVE header <- XINUSE AND RFBM;1
XCOMP_BV field in XSAVE header <- COMPMASK;

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
XSAVEC:         void _xsavec( void * , unsigned __int64);
XSAVEC64:       void _xsavec64( void * , unsigned __int64);

Protected Mode Exceptions
#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                          If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)           If a page fault occurs.
#NM                       If CR0.TS[bit 3] = 1.
#UD                       If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
                          If CR4.OSXSAVE[bit 18] = 0.
                          If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                       If this exception is disabled a general protection exception (#GP) is signaled if the memory
                          operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                          exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                          vary with implementation, as follows. In all implementations where #AC is not signaled, a
                          general protection exception is signaled in its place. In addition, the width of the alignment
                          check may also vary with implementation. For instance, for a given implementation, an align-
                          ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                          tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                          misalignments).

Real-Address Mode Exceptions
#GP                       If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
                          If any part of the operand lies outside the effective address space from 0 to FFFFH.
#NM                       If CR0.TS[bit 3] = 1.
#UD                       If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
                          If CR4.OSXSAVE[bit 18] = 0.
                          If any of the LOCK, 66H, F3H or F2H prefixes is used.




1. If MXCSR does not have its initial value of 1F80H, XSAVEC sets XSTATE_BV[1] to 1 as long as RFBM[1] = 1, regardless of the value
   of XINUSE[1].



Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                  If the memory address is in a non-canonical form.
                        If a memory operand is not aligned on a 64-byte boundary, regardless of segment.
#SS(0)                  If a memory address referencing the SS segment is in a non-canonical form.
#PF(fault-code)         If a page fault occurs.
#NM                     If CR0.TS[bit 3] = 1.
#UD                     If CPUID.01H:ECX.XSAVE[bit 26] = 0 or CPUID.(EAX=0DH,ECX=1):EAX.XSAVEC[bit 1] = 0.
                        If CR4.OSXSAVE[bit 18] = 0.
                        If any of the LOCK, 66H, F3H or F2H prefixes is used.
#AC                     If this exception is disabled a general protection exception (#GP) is signaled if the memory
                        operand is not aligned on a 16-byte boundary, as described above. If the alignment check
                        exception (#AC) is enabled (and the CPL is 3), signaling of #AC is not guaranteed and may
                        vary with implementation, as follows. In all implementations where #AC is not signaled, a
                        general protection exception is signaled in its place. In addition, the width of the alignment
                        check may also vary with implementation. For instance, for a given implementation, an align-
                        ment check exception might be signaled for a 2-byte misalignment, whereas a general protec-
                        tion exception might be signaled for all other misalignments (4-, 8-, or 16-byte
                        misalignments).






