# instructions

platform: x86_64
mnem: PSRLDQ
description:
PSRLDQ-Shift Double Quadword Right Logical
Opcode/                                       Op/     64/32 bit   CPUID       Description
Instruction                                   En      Mode        Feature
                                                      Support     Flag
66 0F 73 /3 ib                                MI      V/V         SSE2        Shift xmm1 right by imm8 while shifting in 0s.
PSRLDQ xmm1, imm8
VEX.NDD.128.66.0F.WIG 73 /3 ib                VMI     V/V         AVX         Shift xmm2 right by imm8 bytes while shifting in
VPSRLDQ xmm1, xmm2, imm8                                                      0s.

VEX.NDD.256.66.0F.WIG 73 /3 ib                VMI     V/V         AVX2        Shift ymm1 right by imm8 bytes while shifting in
VPSRLDQ ymm1, ymm2, imm8                                                      0s.

EVEX.NDD.128.66.0F.WIG 73 /3 ib               FVM     V/V         AVX512VL Shift xmm2/m128 right by imm8 bytes while
VPSRLDQ xmm1, xmm2/m128, imm8                                     AVX512BW shifting in 0s and store result in xmm1.
EVEX.NDD.256.66.0F.WIG 73 /3 ib               FVM     V/V         AVX512VL Shift ymm2/m256 right by imm8 bytes while
VPSRLDQ ymm1, ymm2/m256, imm8                                     AVX512BW shifting in 0s and store result in ymm1.
EVEX.NDD.512.66.0F.WIG 73 /3 ib               FVM     V/V         AVX512BW Shift zmm2/m512 right by imm8 bytes while
VPSRLDQ zmm1, zmm2/m512, imm8                                              shifting in 0s and store result in zmm1.



                                             Instruction Operand Encoding
  Op/En               Operand 1                Operand 2                    Operand 3                     Operand 4
    MI             ModRM:r/m (r, w)                 imm8                       NA                            NA
    VMI              VEX.vvvv (w)            ModRM:r/m (r)                    imm8                           NA
   FVM              EVEX.vvvv (w)            ModRM:r/m (R)                    Imm8                           NA


Description
Shifts the destination operand (first operand) to the right by the number of bytes specified in the count operand
(second operand). The empty high-order bytes are cleared (set to all 0s). If the value specified by the count
operand is greater than 15, the destination operand is set to all 0s. The count operand is an 8-bit immediate.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
128-bit Legacy SSE version: The source and destination operands are the same. Bits (VLMAX-1:128) of the corre-
sponding YMM destination register remain unchanged.
VEX.128 encoded version: The source and destination operands are XMM registers. Bits (VLMAX-1:128) of the
destination YMM register are zeroed.
VEX.256 encoded version: The source operand is a YMM register. The destination operand is a YMM register. The
count operand applies to both the low and high 128-bit lanes.
VEX.256 encoded version: The source operand is YMM register. The destination operand is an YMM register. Bits
(MAX_VL-1:256) of the corresponding ZMM register are zeroed. The count operand applies to both the low and
high 128-bit lanes.
EVEX encoded versions: The source operand is a ZMM/YMM/XMM register or a 512/256/128-bit memory location.
The destination operand is a ZMM/YMM/XMM register. The count operand applies to each 128-bit lanes.
Note: VEX.vvvv/EVEX.vvvv encodes the destination register.





Operation
VPSRLDQ (EVEX.512 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST[127:0] <- SRC[127:0] >> (TEMP * 8)
DEST[255:128] <- SRC[255:128] >> (TEMP * 8)
DEST[383:256] <- SRC[383:256] >> (TEMP * 8)
DEST[511:384] <- SRC[511:384] >> (TEMP * 8)
DEST[MAX_VL-1:512] <- 0;

VPSRLDQ (VEX.256 and EVEX.256 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST[127:0] <- SRC[127:0] >> (TEMP * 8)
DEST[255:128] <- SRC[255:128] >> (TEMP * 8)
DEST[MAX_VL-1:256] <- 0;

VPSRLDQ (VEX.128 and EVEX.128 encoded version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- SRC >> (TEMP * 8)
DEST[MAX_VL-1:128] <- 0;

PSRLDQ(128-bit Legacy SSE version)
TEMP <- COUNT
IF (TEMP > 15) THEN TEMP <- 16; FI
DEST <- DEST >> (TEMP * 8)
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents
(V)PSRLDQ __m128i _mm_srli_si128 ( __m128i a, int imm)
VPSRLDQ __m256i _mm256_bsrli_epi128 ( __m256i, const int)
VPSRLDQ __m512i _mm512_bsrli_epi128 ( __m512i, int)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 7.
EVEX-encoded instruction, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PSRLW
description:
PSRLW/PSRLD/PSRLQ-Shift Packed Data Right Logical
Opcode/                                             Op/   64/32 bit   CPUID     Description
Instruction                                         En    Mode        Feature
                                                          Support     Flag
0F D1 /r1                                           RM    V/V         MMX       Shift words in mm right by amount specified in
PSRLW mm, mm/m64                                                                mm/m64 while shifting in 0s.

66 0F D1 /r                                         RM    V/V         SSE2      Shift words in xmm1 right by amount
PSRLW xmm1, xmm2/m128                                                           specified in xmm2/m128 while shifting in 0s.

0F 71 /2 ib1                                        MI    V/V         MMX       Shift words in mm right by imm8 while shifting
PSRLW mm, imm8                                                                  in 0s.

66 0F 71 /2 ib                                      MI    V/V         SSE2      Shift words in xmm1 right by imm8 while
PSRLW xmm1, imm8                                                                shifting in 0s.

0F D2 /r1                                           RM    V/V         MMX       Shift doublewords in mm right by amount
PSRLD mm, mm/m64                                                                specified in mm/m64 while shifting in 0s.

66 0F D2 /r                                         RM    V/V         SSE2      Shift doublewords in xmm1 right by amount
PSRLD xmm1, xmm2/m128                                                           specified in xmm2 /m128 while shifting in 0s.

0F 72 /2 ib1                                        MI    V/V         MMX       Shift doublewords in mm right by imm8 while
PSRLD mm, imm8                                                                  shifting in 0s.

66 0F 72 /2 ib                                      MI    V/V         SSE2      Shift doublewords in xmm1 right by imm8
PSRLD xmm1, imm8                                                                while shifting in 0s.

0F D3 /r1                                           RM    V/V         MMX       Shift mm right by amount specified in
PSRLQ mm, mm/m64                                                                mm/m64 while shifting in 0s.

66 0F D3 /r                                         RM    V/V         SSE2      Shift quadwords in xmm1 right by amount
PSRLQ xmm1, xmm2/m128                                                           specified in xmm2/m128 while shifting in 0s.

0F 73 /2 ib1                                        MI    V/V         MMX       Shift mm right by imm8 while shifting in 0s.
PSRLQ mm, imm8
66 0F 73 /2 ib                                      MI    V/V         SSE2      Shift quadwords in xmm1 right by imm8 while
PSRLQ xmm1, imm8                                                                shifting in 0s.

VEX.NDS.128.66.0F.WIG D1 /r                         RVM   V/V         AVX       Shift words in xmm2 right by amount
VPSRLW xmm1, xmm2, xmm3/m128                                                    specified in xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 71 /2 ib                      VMI   V/V         AVX       Shift words in xmm2 right by imm8 while
VPSRLW xmm1, xmm2, imm8                                                         shifting in 0s.

VEX.NDS.128.66.0F.WIG D2 /r                         RVM   V/V         AVX       Shift doublewords in xmm2 right by amount
VPSRLD xmm1, xmm2, xmm3/m128                                                    specified in xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 72 /2 ib                      VMI   V/V         AVX       Shift doublewords in xmm2 right by imm8
VPSRLD xmm1, xmm2, imm8                                                         while shifting in 0s.

VEX.NDS.128.66.0F.WIG D3 /r                         RVM   V/V         AVX       Shift quadwords in xmm2 right by amount
VPSRLQ xmm1, xmm2, xmm3/m128                                                    specified in xmm3/m128 while shifting in 0s.

VEX.NDD.128.66.0F.WIG 73 /2 ib                      VMI   V/V         AVX       Shift quadwords in xmm2 right by imm8 while
VPSRLQ xmm1, xmm2, imm8                                                         shifting in 0s.

VEX.NDS.256.66.0F.WIG D1 /r                         RVM   V/V         AVX2      Shift words in ymm2 right by amount specified
VPSRLW ymm1, ymm2, xmm3/m128                                                    in xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 71 /2 ib                      VMI   V/V         AVX2      Shift words in ymm2 right by imm8 while
VPSRLW ymm1, ymm2, imm8                                                         shifting in 0s.





VEX.NDS.256.66.0F.WIG D2 /r               RVM   V/V   AVX2         Shift doublewords in ymm2 right by amount
VPSRLD ymm1, ymm2, xmm3/m128                                       specified in xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 72 /2 ib            VMI   V/V   AVX2         Shift doublewords in ymm2 right by imm8
VPSRLD ymm1, ymm2, imm8                                            while shifting in 0s.

VEX.NDS.256.66.0F.WIG D3 /r               RVM   V/V   AVX2         Shift quadwords in ymm2 right by amount
VPSRLQ ymm1, ymm2, xmm3/m128                                       specified in xmm3/m128 while shifting in 0s.

VEX.NDD.256.66.0F.WIG 73 /2 ib            VMI   V/V   AVX2         Shift quadwords in ymm2 right by imm8 while
VPSRLQ ymm1, ymm2, imm8                                            shifting in 0s.

EVEX.NDS.128.66.0F.WIG D1 /r              M128 V/V    AVX512VL     Shift words in xmm2 right by amount specified
VPSRLW xmm1 {k1}{z}, xmm2, xmm3/m128                  AVX512BW     in xmm3/m128 while shifting in 0s using
                                                                   writemask k1.
EVEX.NDS.256.66.0F.WIG D1 /r              M128 V/V    AVX512VL     Shift words in ymm2 right by amount specified
VPSRLW ymm1 {k1}{z}, ymm2, xmm3/m128                  AVX512BW     in xmm3/m128 while shifting in 0s using
                                                                   writemask k1.
EVEX.NDS.512.66.0F.WIG D1 /r              M128 V/V    AVX512BW     Shift words in zmm2 right by amount specified
VPSRLW zmm1 {k1}{z}, zmm2, xmm3/m128                               in xmm3/m128 while shifting in 0s using
                                                                   writemask k1.
EVEX.NDD.128.66.0F.WIG 71 /2 ib           FVM   V/V   AVX512VL     Shift words in xmm2/m128 right by imm8
VPSRLW xmm1 {k1}{z}, xmm2/m128, imm8                  AVX512BW     while shifting in 0s using writemask k1.
EVEX.NDD.256.66.0F.WIG 71 /2 ib           FVM   V/V   AVX512VL     Shift words in ymm2/m256 right by imm8
VPSRLW ymm1 {k1}{z}, ymm2/m256, imm8                  AVX512BW     while shifting in 0s using writemask k1.
EVEX.NDD.512.66.0F.WIG 71 /2 ib           FVM   V/V   AVX512BW     Shift words in zmm2/m512 right by imm8
VPSRLW zmm1 {k1}{z}, zmm2/m512, imm8                               while shifting in 0s using writemask k1.
EVEX.NDS.128.66.0F.W0 D2 /r               M128 V/V    AVX512VL     Shift doublewords in xmm2 right by amount
VPSRLD xmm1 {k1}{z}, xmm2, xmm3/m128                  AVX512F      specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.256.66.0F.W0 D2 /r               M128 V/V    AVX512VL     Shift doublewords in ymm2 right by amount
VPSRLD ymm1 {k1}{z}, ymm2, xmm3/m128                  AVX512F      specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.512.66.0F.W0 D2 /r               M128 V/V    AVX512F      Shift doublewords in zmm2 right by amount
VPSRLD zmm1 {k1}{z}, zmm2, xmm3/m128                               specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDD.128.66.0F.W0 72 /2 ib            FV    V/V   AVX512VL     Shift doublewords in xmm2/m128/m32bcst
VPSRLD xmm1 {k1}{z}, xmm2/m128/m32bcst,               AVX512F      right by imm8 while shifting in 0s using
imm8                                                               writemask k1.
EVEX.NDD.256.66.0F.W0 72 /2 ib            FV    V/V   AVX512VL     Shift doublewords in ymm2/m256/m32bcst
VPSRLD ymm1 {k1}{z}, ymm2/m256/m32bcst,               AVX512F      right by imm8 while shifting in 0s using
imm8                                                               writemask k1.
EVEX.NDD.512.66.0F.W0 72 /2 ib            FVI   V/V   AVX512F      Shift doublewords in zmm2/m512/m32bcst
VPSRLD zmm1 {k1}{z}, zmm2/m512/m32bcst,                            right by imm8 while shifting in 0s using
imm8                                                               writemask k1.
EVEX.NDS.128.66.0F.W1 D3 /r               M128 V/V    AVX512VL     Shift quadwords in xmm2 right by amount
VPSRLQ xmm1 {k1}{z}, xmm2, xmm3/m128                  AVX512F      specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.256.66.0F.W1 D3 /r               M128 V/V    AVX512VL     Shift quadwords in ymm2 right by amount
VPSRLQ ymm1 {k1}{z}, ymm2, xmm3/m128                  AVX512F      specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.
EVEX.NDS.512.66.0F.W1 D3 /r               M128 V/V    AVX512F      Shift quadwords in zmm2 right by amount
VPSRLQ zmm1 {k1}{z}, zmm2, xmm3/m128                               specified in xmm3/m128 while shifting in 0s
                                                                   using writemask k1.




EVEX.NDD.128.66.0F.W1 73 /2 ib                        FV        V/V       AVX512VL      Shift quadwords in xmm2/m128/m64bcst
VPSRLQ xmm1 {k1}{z}, xmm2/m128/m64bcst,                                   AVX512F       right by imm8 while shifting in 0s using
imm8                                                                                    writemask k1.
EVEX.NDD.256.66.0F.W1 73 /2 ib                        FV        V/V       AVX512VL      Shift quadwords in ymm2/m256/m64bcst
VPSRLQ ymm1 {k1}{z}, ymm2/m256/m64bcst,                                   AVX512F       right by imm8 while shifting in 0s using
imm8                                                                                    writemask k1.
EVEX.NDD.512.66.0F.W1 73 /2 ib                        FVI       V/V       AVX512F       Shift quadwords in zmm2/m512/m64bcst
VPSRLQ zmm1 {k1}{z}, zmm2/m512/m64bcst,                                                 right by imm8 while shifting in 0s using
imm8                                                                                    writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                    Instruction Operand Encoding
  Op/En              Operand 1                        Operand 2                     Operand 3                    Operand 4
    RM            ModRM:reg (r, w)                  ModRM:r/m (r)                      NA                           NA
    MI            ModRM:r/m (r, w)                       imm8                          NA                           NA
   RVM             ModRM:reg (w)                     VEX.vvvv (r)                 ModRM:r/m (r)                     NA
    VMI             VEX.vvvv (w)                    ModRM:r/m (r)                     imm8                          NA
   FVM             EVEX.vvvv (w)                    ModRM:r/m (R)                     Imm8                          NA
    FVI            EVEX.vvvv (w)                    ModRM:r/m (R)                     Imm8                          NA
   M128            ModRM:reg (w)                     VEX.vvvv (r)                 ModRM:r/m (r)                     NA


Description
Shifts the bits in the individual data elements (words, doublewords, or quadword) in the destination operand (first
operand) to the right by the number of bits specified in the count operand (second operand). As the bits in the data
elements are shifted right, the empty high-order bits are cleared (set to 0). If the value specified by the count
operand is greater than 15 (for words), 31 (for doublewords), or 63 (for a quadword), then the destination operand
is set to all 0s. Figure 4-19 gives an example of shifting words in a 64-bit operand.
Note that only the low 64-bits of a 128-bit count operand are checked to compute the count.


                              Pre-Shift
                                               X3                X2          X1                 X0
                                 DEST
                             Shift Right
                              with Zero
                              Extension

                            Post-Shift
                               DEST        X3 >> COUNT      X2 >> COUNT   X1 >> COUNT X0 >> COUNT

                  Figure 4-19. PSRLW, PSRLD, and PSRLQ Instruction Operation Using 64-bit Operand

The (V)PSRLW instruction shifts each of the words in the destination operand to the right by the number of bits
specified in the count operand; the (V)PSRLD instruction shifts each of the doublewords in the destination operand;
and the PSRLQ instruction shifts the quadword (or quadwords) in the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instruction 64-bit operand: The destination operand is an MMX technology register; the count operand
can be either an MMX technology register or an 64-bit memory location.



128-bit Legacy SSE version: The destination operand is an XMM register; the count operand can be either an XMM
register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits
are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the corresponding YMM destination register
remain unchanged.
VEX.128 encoded version: The destination operand is an XMM register; the count operand can be either an XMM
register or a 128-bit memory location, or an 8-bit immediate. If the count operand is a memory address, 128 bits
are loaded but the upper 64 bits are ignored. Bits (VLMAX-1:128) of the destination YMM register are zeroed.
VEX.256 encoded version: The destination operand is a YMM register. The source operand is a YMM register or a
memory location. The count operand can come either from an XMM register or a memory location or an 8-bit imme-
diate. Bits (MAX_VL-1:256) of the corresponding ZMM register are zeroed.
EVEX encoded versions: The destination operand is a ZMM register updated according to the writemask. The count
operand is either an 8-bit immediate (the immediate count version) or an 8-bit value from an XMM register or a
memory location (the variable count version). For the immediate count version, the source operand (the second
operand) can be a ZMM register, a 512-bit memory location or a 512-bit vector broadcasted from a 32/64-bit
memory location. For the variable count version, the first source operand (the second operand) is a ZMM register,
the second source operand (the third operand, 8-bit variable count) can be an XMM register or a memory location.
Note: In VEX/EVEX encoded versions of shifts with an immediate count, vvvv of VEX/EVEX encode the destination
register, and VEX.B/EVEX.B + ModRM.r/m encodes the source register.
Note: For shifts with an immediate count (VEX.128.66.0F 71-73 /2, or EVEX.128.66.0F 71-73 /2),
VEX.vvvv/EVEX.vvvv encodes the destination register.

Operation

PSRLW (with 64-bit operand)
   IF (COUNT > 15)
   THEN
        DEST[64:0] <- 0000000000000000H
   ELSE
        DEST[15:0] <- ZeroExtend(DEST[15:0] >> COUNT);
        (* Repeat shift operation for 2nd and 3rd words *)
        DEST[63:48] <- ZeroExtend(DEST[63:48] >> COUNT);
   FI;

PSRLD (with 64-bit operand)
   IF (COUNT > 31)
   THEN
        DEST[64:0] <- 0000000000000000H
   ELSE
        DEST[31:0] <- ZeroExtend(DEST[31:0] >> COUNT);
        DEST[63:32] <- ZeroExtend(DEST[63:32] >> COUNT);
   FI;

PSRLQ (with 64-bit operand)
    IF (COUNT > 63)
    THEN
         DEST[64:0] <- 0000000000000000H
    ELSE
         DEST <- ZeroExtend(DEST >> COUNT);
    FI;
LOGICAL_RIGHT_SHIFT_DWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[31:0] <- 0
ELSE



      DEST[31:0] <- ZeroExtend(SRC[31:0] >> COUNT);
FI;

LOGICAL_RIGHT_SHIFT_QWORDS1(SRC, COUNT_SRC)
COUNT <- COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[63:0] <- 0
ELSE
    DEST[63:0] <- ZeroExtend(SRC[63:0] >> COUNT);
FI;
LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
    DEST[255:0] <-0
ELSE
    DEST[15:0] <-ZeroExtend(SRC[15:0] >> COUNT);
    (* Repeat shift operation for 2nd through 15th words *)
    DEST[255:240] <-ZeroExtend(SRC[255:240] >> COUNT);
FI;

LOGICAL_RIGHT_SHIFT_WORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 15)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[15:0] <-ZeroExtend(SRC[15:0] >> COUNT);
    (* Repeat shift operation for 2nd through 7th words *)
    DEST[127:112] <-ZeroExtend(SRC[127:112] >> COUNT);
FI;

LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[255:0] <-0
ELSE
    DEST[31:0] <-ZeroExtend(SRC[31:0] >> COUNT);
    (* Repeat shift operation for 2nd through 3rd words *)
    DEST[255:224] <-ZeroExtend(SRC[255:224] >> COUNT);
FI;

LOGICAL_RIGHT_SHIFT_DWORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 31)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[31:0] <-ZeroExtend(SRC[31:0] >> COUNT);
    (* Repeat shift operation for 2nd through 3rd words *)
    DEST[127:96] <-ZeroExtend(SRC[127:96] >> COUNT);
FI;



LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[255:0] <-0
ELSE
    DEST[63:0] <-ZeroExtend(SRC[63:0] >> COUNT);
    DEST[127:64] <-ZeroExtend(SRC[127:64] >> COUNT);
    DEST[191:128] <-ZeroExtend(SRC[191:128] >> COUNT);
    DEST[255:192] <-ZeroExtend(SRC[255:192] >> COUNT);
FI;

LOGICAL_RIGHT_SHIFT_QWORDS(SRC, COUNT_SRC)
COUNT <-COUNT_SRC[63:0];
IF (COUNT > 63)
THEN
    DEST[127:0] <-00000000000000000000000000000000H
ELSE
    DEST[63:0] <-ZeroExtend(SRC[63:0] >> COUNT);
    DEST[127:64] <-ZeroExtend(SRC[127:64] >> COUNT);
FI;





VPSRLW (EVEX versions, xmm/m128)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], SRC2)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRLW (EVEX versions, imm8)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_WORDS_128b(SRC1[127:0], imm8)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[255:0], imm8)
    TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1[511:256], imm8)
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+15:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+15:i] = 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0




VPSRLW (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSRLW (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_WORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;

VPSRLW (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSRLW (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSRLW (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSRLW (xmm, imm8)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_WORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

VPSRLD (EVEX versions, xmm/m128)
(KL, VL) = (4, 128), (8, 256), (16, 512)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1[511:256], SRC2)
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0





VPSRLD (EVEX versions, imm8)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+31:i] <- LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[31:0], imm8)
                    ELSE DEST[i+31:i] <- LOGICAL_RIGHT_SHIFT_DWORDS1(SRC1[i+31:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRLD (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSRLD (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_DWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;

VPSRLD (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSRLD (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSRLD (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSRLD (xmm, imm8)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_DWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)





VPSRLQ (EVEX versions, xmm/m128)
(KL, VL) = (2, 128), (4, 256), (8, 512)
TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
IF VL = 128
    TMP_DEST[127:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_128b(SRC1[127:0], SRC2)
FI;
IF VL = 256
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
FI;
IF VL = 512
    TMP_DEST[255:0] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[255:0], SRC2)
    TMP_DEST[511:256] <- LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1[511:256], SRC2)
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRLQ (EVEX versions, imm8)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC1 *is memory*)
                    THEN DEST[i+63:i] <- LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[63:0], imm8)
                    ELSE DEST[i+63:i] <- LOGICAL_RIGHT_SHIFT_QWORDS1(SRC1[i+63:i], imm8)
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VPSRLQ (ymm, ymm, xmm/m128) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0;

VPSRLQ (ymm, imm8) - VEX.256 encoding
DEST[255:0] <-LOGICAL_RIGHT_SHIFT_QWORDS_256b(SRC1, imm8)
DEST[MAX_VL-1:256] <-0;



VPSRLQ (xmm, xmm, xmm/m128) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPSRLQ (xmm, imm8) - VEX.128 encoding
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(SRC1, imm8)
DEST[MAX_VL-1:128] <-0

PSRLQ (xmm, xmm, xmm/m128)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

PSRLQ (xmm, imm8)
DEST[127:0] <-LOGICAL_RIGHT_SHIFT_QWORDS(DEST, imm8)
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents
VPSRLD __m512i _mm512_srli_epi32(__m512i a, unsigned int imm);
VPSRLD __m512i _mm512_mask_srli_epi32(__m512i s, __mmask16 k, __m512i a, unsigned int imm);
VPSRLD __m512i _mm512_maskz_srli_epi32( __mmask16 k, __m512i a, unsigned int imm);
VPSRLD __m256i _mm256_mask_srli_epi32(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRLD __m256i _mm256_maskz_srli_epi32( __mmask8 k, __m256i a, unsigned int imm);
VPSRLD __m128i _mm_mask_srli_epi32(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLD __m128i _mm_maskz_srli_epi32( __mmask8 k, __m128i a, unsigned int imm);
VPSRLD __m512i _mm512_srl_epi32(__m512i a, __m128i cnt);
VPSRLD __m512i _mm512_mask_srl_epi32(__m512i s, __mmask16 k, __m512i a, __m128i cnt);
VPSRLD __m512i _mm512_maskz_srl_epi32( __mmask16 k, __m512i a, __m128i cnt);
VPSRLD __m256i _mm256_mask_srl_epi32(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m256i _mm256_maskz_srl_epi32( __mmask8 k, __m256i a, __m128i cnt);
VPSRLD __m128i _mm_mask_srl_epi32(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLD __m128i _mm_maskz_srl_epi32( __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m512i _mm512_srli_epi64(__m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64(__m512i s, __mmask8 k, __m512i a, unsigned int imm);
VPSRLQ __m512i _mm512_mask_srli_epi64( __mmask8 k, __m512i a, unsigned int imm);
VPSRLQ __m256i _mm256_mask_srli_epi64(__m256i s, __mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m256i _mm256_maskz_srli_epi64( __mmask8 k, __m256i a, unsigned int imm);
VPSRLQ __m128i _mm_mask_srli_epi64(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLQ __m128i _mm_maskz_srli_epi64( __mmask8 k, __m128i a, unsigned int imm);
VPSRLQ __m512i _mm512_srl_epi64(__m512i a, __m128i cnt);
VPSRLQ __m512i _mm512_mask_srl_epi64(__m512i s, __mmask8 k, __m512i a, __m128i cnt);
VPSRLQ __m512i _mm512_mask_srl_epi64( __mmask8 k, __m512i a, __m128i cnt);
VPSRLQ __m256i _mm256_mask_srl_epi64(__m256i s, __mmask8 k, __m256i a, __m128i cnt);
VPSRLQ __m256i _mm256_maskz_srl_epi64( __mmask8 k, __m256i a, __m128i cnt);
VPSRLQ __m128i _mm_mask_srl_epi64(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLQ __m128i _mm_maskz_srl_epi64( __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m512i _mm512_srli_epi16(__m512i a, unsigned int imm);
VPSRLW __m512i _mm512_mask_srli_epi16(__m512i s, __mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m512i _mm512_maskz_srli_epi16( __mmask32 k, __m512i a, unsigned int imm);
VPSRLW __m256i _mm256_mask_srlii_epi16(__m256i s, __mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m256i _mm256_maskz_srli_epi16( __mmask16 k, __m256i a, unsigned int imm);
VPSRLW __m128i _mm_mask_srli_epi16(__m128i s, __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m128i _mm_maskz_srli_epi16( __mmask8 k, __m128i a, unsigned int imm);
VPSRLW __m512i _mm512_srl_epi16(__m512i a, __m128i cnt);
VPSRLW __m512i _mm512_mask_srl_epi16(__m512i s, __mmask32 k, __m512i a, __m128i cnt);



VPSRLW __m512i _mm512_maskz_srl_epi16( __mmask32 k, __m512i a, __m128i cnt);
VPSRLW __m256i _mm256_mask_srl_epi16(__m256i s, __mmask16 k, __m256i a, __m128i cnt);
VPSRLW __m256i _mm256_maskz_srl_epi16( __mmask8 k, __mmask16 a, __m128i cnt);
VPSRLW __m128i _mm_mask_srl_epi16(__m128i s, __mmask8 k, __m128i a, __m128i cnt);
VPSRLW __m128i _mm_maskz_srl_epi16( __mmask8 k, __m128i a, __m128i cnt);
PSRLW:__m64 _mm_srli_pi16(__m64 m, int count)
PSRLW:__m64 _mm_srl_pi16 (__m64 m, __m64 count)
(V)PSRLW:__m128i _mm_srli_epi16 (__m128i m, int count)
(V)PSRLW:__m128i _mm_srl_epi16 (__m128i m, __m128i count)
VPSRLW:__m256i _mm256_srli_epi16 (__m256i m, int count)
VPSRLW:__m256i _mm256_srl_epi16 (__m256i m, __m128i count)
PSRLD:__m64 _mm_srli_pi32 (__m64 m, int count)
PSRLD:__m64 _mm_srl_pi32 (__m64 m, __m64 count)
(V)PSRLD:__m128i _mm_srli_epi32 (__m128i m, int count)
(V)PSRLD:__m128i _mm_srl_epi32 (__m128i m, __m128i count)
VPSRLD:__m256i _mm256_srli_epi32 (__m256i m, int count)
VPSRLD:__m256i _mm256_srl_epi32 (__m256i m, __m128i count)
PSRLQ:__m64 _mm_srli_si64 (__m64 m, int count)
PSRLQ:__m64 _mm_srl_si64 (__m64 m, __m64 count)
(V)PSRLQ:__m128i _mm_srli_epi64 (__m128i m, int count)
(V)PSRLQ:__m128i _mm_srl_epi64 (__m128i m, __m128i count)
VPSRLQ:__m256i _mm256_srli_epi64 (__m256i m, int count)
VPSRLQ:__m256i _mm256_srl_epi64 (__m256i m, __m128i count)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
VEX-encoded instructions:
                     Syntax with RM/RVM operand encoding, see Exceptions Type 4.
                     Syntax with MI/VMI operand encoding, see Exceptions Type 7.


EVEX-encoded VPSRLW, see Exceptions Type E4NF.nb.


EVEX-encoded VPSRLD/Q:
                     Syntax with M128 operand encoding, see Exceptions Type E4NF.nb.
                     Syntax with FVI operand encoding, see Exceptions Type E4.






platform: x86_64
mnem: PSUBB
description:
PSUBB/PSUBW/PSUBD-Subtract Packed Integers
Opcode/                                      Op/   64/32 bit   CPUID      Description
Instruction                                  En    Mode        Feature
                                                   Support     Flag
0F F8 /r1                                    RM    V/V         MMX        Subtract packed byte integers in mm/m64
PSUBB mm, mm/m64                                                          from packed byte integers in mm.

66 0F F8 /r                                  RM    V/V         SSE2       Subtract packed byte integers in xmm2/m128
PSUBB xmm1, xmm2/m128                                                     from packed byte integers in xmm1.

0F F9 /r1                                    RM    V/V         MMX        Subtract packed word integers in mm/m64
PSUBW mm, mm/m64                                                          from packed word integers in mm.

66 0F F9 /r                                  RM    V/V         SSE2       Subtract packed word integers in
PSUBW xmm1, xmm2/m128                                                     xmm2/m128 from packed word integers in
                                                                          xmm1.
0F FA /r1                                    RM    V/V         MMX        Subtract packed doubleword integers in
PSUBD mm, mm/m64                                                          mm/m64 from packed doubleword integers in
                                                                          mm.
66 0F FA /r                                  RM    V/V         SSE2       Subtract packed doubleword integers in
PSUBD xmm1, xmm2/m128                                                     xmm2/mem128 from packed doubleword
                                                                          integers in xmm1.
VEX.NDS.128.66.0F.WIG F8 /r                  RVM V/V           AVX        Subtract packed byte integers in xmm3/m128
VPSUBB xmm1, xmm2, xmm3/m128                                              from xmm2.
VEX.NDS.128.66.0F.WIG F9 /r                  RVM V/V           AVX        Subtract packed word integers in
VPSUBW xmm1, xmm2, xmm3/m128                                              xmm3/m128 from xmm2.

VEX.NDS.128.66.0F.WIG FA /r                  RVM V/V           AVX        Subtract packed doubleword integers in
VPSUBD xmm1, xmm2, xmm3/m128                                              xmm3/m128 from xmm2.
VEX.NDS.256.66.0F.WIG F8 /r                  RVM V/V           AVX2       Subtract packed byte integers in ymm3/m256
VPSUBB ymm1, ymm2, ymm3/m256                                              from ymm2.
VEX.NDS.256.66.0F.WIG F9 /r                  RVM V/V           AVX2       Subtract packed word integers in
VPSUBW ymm1, ymm2, ymm3/m256                                              ymm3/m256 from ymm2.
VEX.NDS.256.66.0F.WIG FA /r                  RVM V/V           AVX2       Subtract packed doubleword integers in
VPSUBD ymm1, ymm2, ymm3/m256                                              ymm3/m256 from ymm2.
EVEX.NDS.128.66.0F.WIG F8 /r                 FVM V/V           AVX512VL Subtract packed byte integers in xmm3/m128
VPSUBB xmm1 {k1}{z}, xmm2, xmm3/m128                           AVX512BW from xmm2 and store in xmm1 using
                                                                        writemask k1.
EVEX.NDS.256.66.0F.WIG F8 /r                 FVM V/V           AVX512VL Subtract packed byte integers in ymm3/m256
VPSUBB ymm1 {k1}{z}, ymm2, ymm3/m256                           AVX512BW from ymm2 and store in ymm1 using
                                                                        writemask k1.
EVEX.NDS.512.66.0F.WIG F8 /r                 FVM V/V           AVX512BW Subtract packed byte integers in zmm3/m512
VPSUBB zmm1 {k1}{z}, zmm2, zmm3/m512                                    from zmm2 and store in zmm1 using
                                                                        writemask k1.
EVEX.NDS.128.66.0F.WIG F9 /r                 FVM V/V           AVX512VL Subtract packed word integers in
VPSUBW xmm1 {k1}{z}, xmm2, xmm3/m128                           AVX512BW xmm3/m128 from xmm2 and store in xmm1
                                                                        using writemask k1.
EVEX.NDS.256.66.0F.WIG F9 /r                 FVM V/V           AVX512VL Subtract packed word integers in
VPSUBW ymm1 {k1}{z}, ymm2, ymm3/m256                           AVX512BW ymm3/m256 from ymm2 and store in ymm1
                                                                        using writemask k1.
EVEX.NDS.512.66.0F.WIG F9 /r                 FVM V/V           AVX512BW Subtract packed word integers in
VPSUBW zmm1 {k1}{z}, zmm2, zmm3/m512                                    zmm3/m512 from zmm2 and store in zmm1
                                                                        using writemask k1.





EVEX.NDS.128.66.0F.W0 FA /r                  FV                V/V       AVX512VL       Subtract packed doubleword integers in
VPSUBD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst                             AVX512F        xmm3/m128/m32bcst from xmm2 and store
                                                                                        in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W0 FA /r                  FV                V/V       AVX512VL       Subtract packed doubleword integers in
VPSUBD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst                             AVX512F        ymm3/m256/m32bcst from ymm2 and store
                                                                                        in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W0 FA /r                           FV       V/V       AVX512F        Subtract packed doubleword integers in
VPSUBD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst                                            zmm3/m512/m32bcst from zmm2 and store
                                                                                        in zmm1 using writemask k1
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers" in
the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                                Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                     Operand 3                      Operand 4
    RM          ModRM:reg (r, w)               ModRM:r/m (r)                       NA                            NA
   RVM           ModRM:reg (w)                  VEX.vvvv (r)                 ModRM:r/m (r)                       NA
   FVM           ModRM:reg (w)                  EVEX.vvvv (r)                ModRM:r/m (r)                       NA
    FV           ModRM:reg (w)                  EVEX.vvvv (r)                ModRM:r/m (r)                       NA


Description
Performs a SIMD subtract of the packed integers of the source operand (second operand) from the packed integers
of the destination operand (first operand), and stores the packed integer results in the destination operand. See
Figure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of
a SIMD operation. Overflow is handled with wraparound, as described in the following paragraphs.
The (V)PSUBB instruction subtracts packed byte integers. When an individual result is too large or too small to be
represented in a byte, the result is wrapped around and the low 8 bits are written to the destination element.
The (V)PSUBW instruction subtracts packed word integers. When an individual result is too large or too small to be
represented in a word, the result is wrapped around and the low 16 bits are written to the destination element.
The (V)PSUBD instruction subtracts packed doubleword integers. When an individual result is too large or too small
to be represented in a doubleword, the result is wrapped around and the low 32 bits are written to the destination
element.
Note that the (V)PSUBB, (V)PSUBW, and (V)PSUBD instructions can operate on either unsigned or signed (two's
complement notation) packed integers; however, it does not set bits in the EFLAGS register to indicate overflow
and/or a carry. To prevent undetected overflow conditions, software must control the ranges of values upon which
it operates.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-
nation register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.





VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded VPSUBD: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and
destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.
EVEX encoded VPSUBB/W: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-
tionally updated with writemask k1.

Operation
PSUBB (with 64-bit operands)
  DEST[7:0] <- DEST[7:0] - SRC[7:0];
  (* Repeat subtract operation for 2nd through 7th byte *)
  DEST[63:56] <- DEST[63:56] - SRC[63:56];

PSUBW (with 64-bit operands)
  DEST[15:0] <- DEST[15:0] - SRC[15:0];
  (* Repeat subtract operation for 2nd and 3rd word *)
  DEST[63:48] <- DEST[63:48] - SRC[63:48];

PSUBD (with 64-bit operands)
  DEST[31:0] <- DEST[31:0] - SRC[31:0];
  DEST[63:32] <- DEST[63:32] - SRC[63:32];

PSUBD (with 128-bit operands)
  DEST[31:0] <- DEST[31:0] - SRC[31:0];
  (* Repeat subtract operation for 2nd and 3rd doubleword *)
  DEST[127:96] <- DEST[127:96] - SRC[127:96];

VPSUBB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i<-j*8
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SRC1[i+7:i] - SRC2[i+7:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+7:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+7:i] = 0
              FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPSUBW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SRC1[i+15:i] - SRC2[i+15:i]
         ELSE
               IF *merging-masking*              ; merging-masking




                 THEN *DEST[i+15:i] remains unchanged*
                 ELSE *zeroing-masking*             ; zeroing-masking
                     DEST[i+15:i] = 0
          FI
   FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPSUBD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] - SRC2[31:0]
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] - SRC2[i+31:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+31:i] remains unchanged*
                    ELSE *zeroing-masking*               ; zeroing-masking
                         DEST[i+31:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPSUBB (VEX.256 encoded version)
DEST[7:0] <-SRC1[7:0]-SRC2[7:0]
DEST[15:8] <-SRC1[15:8]-SRC2[15:8]
DEST[23:16] <-SRC1[23:16]-SRC2[23:16]
DEST[31:24] <-SRC1[31:24]-SRC2[31:24]
DEST[39:32] <-SRC1[39:32]-SRC2[39:32]
DEST[47:40] <-SRC1[47:40]-SRC2[47:40]
DEST[55:48] <-SRC1[55:48]-SRC2[55:48]
DEST[63:56] <-SRC1[63:56]-SRC2[63:56]
DEST[71:64] <-SRC1[71:64]-SRC2[71:64]
DEST[79:72] <-SRC1[79:72]-SRC2[79:72]
DEST[87:80] <-SRC1[87:80]-SRC2[87:80]
DEST[95:88] <-SRC1[95:88]-SRC2[95:88]
DEST[103:96] <-SRC1[103:96]-SRC2[103:96]
DEST[111:104] <-SRC1[111:104]-SRC2[111:104]
DEST[119:112] <-SRC1[119:112]-SRC2[119:112]
DEST[127:120] <-SRC1[127:120]-SRC2[127:120]
DEST[135:128] <-SRC1[135:128]-SRC2[135:128]
DEST[143:136] <-SRC1[143:136]-SRC2[143:136]
DEST[151:144] <-SRC1[151:144]-SRC2[151:144]
DEST[159:152] <-SRC1[159:152]-SRC2[159:152]
DEST[167:160] <-SRC1[167:160]-SRC2[167:160]
DEST[175:168] <-SRC1[175:168]-SRC2[175:168]
DEST[183:176] <-SRC1[183:176]-SRC2[183:176]
DEST[191:184] <-SRC1[191:184]-SRC2[191:184]
DEST[199:192] <-SRC1[199:192]-SRC2[199:192]
DEST[207:200] <-SRC1[207:200]-SRC2[207:200]



DEST[215:208] <-SRC1[215:208]-SRC2[215:208]
DEST[223:216] <-SRC1[223:216]-SRC2[223:216]
DEST[231:224] <-SRC1[231:224]-SRC2[231:224]
DEST[239:232] <-SRC1[239:232]-SRC2[239:232]
DEST[247:240] <-SRC1[247:240]-SRC2[247:240]
DEST[255:248] <-SRC1[255:248]-SRC2[255:248]
DEST[MAX_VL-1:256] <-0

VPSUBB (VEX.128 encoded version)
DEST[7:0] <-SRC1[7:0]-SRC2[7:0]
DEST[15:8] <-SRC1[15:8]-SRC2[15:8]
DEST[23:16] <-SRC1[23:16]-SRC2[23:16]
DEST[31:24] <-SRC1[31:24]-SRC2[31:24]
DEST[39:32] <-SRC1[39:32]-SRC2[39:32]
DEST[47:40] <-SRC1[47:40]-SRC2[47:40]
DEST[55:48] <-SRC1[55:48]-SRC2[55:48]
DEST[63:56] <-SRC1[63:56]-SRC2[63:56]
DEST[71:64] <-SRC1[71:64]-SRC2[71:64]
DEST[79:72] <-SRC1[79:72]-SRC2[79:72]
DEST[87:80] <-SRC1[87:80]-SRC2[87:80]
DEST[95:88] <-SRC1[95:88]-SRC2[95:88]
DEST[103:96] <-SRC1[103:96]-SRC2[103:96]
DEST[111:104] <-SRC1[111:104]-SRC2[111:104]
DEST[119:112] <-SRC1[119:112]-SRC2[119:112]
DEST[127:120] <-SRC1[127:120]-SRC2[127:120]
DEST[MAX_VL-1:128] <-0

PSUBB (128-bit Legacy SSE version)
DEST[7:0] <-DEST[7:0]-SRC[7:0]
DEST[15:8] <-DEST[15:8]-SRC[15:8]
DEST[23:16] <-DEST[23:16]-SRC[23:16]
DEST[31:24] <-DEST[31:24]-SRC[31:24]
DEST[39:32] <-DEST[39:32]-SRC[39:32]
DEST[47:40] <-DEST[47:40]-SRC[47:40]
DEST[55:48] <-DEST[55:48]-SRC[55:48]
DEST[63:56] <-DEST[63:56]-SRC[63:56]
DEST[71:64] <-DEST[71:64]-SRC[71:64]
DEST[79:72] <-DEST[79:72]-SRC[79:72]
DEST[87:80] <-DEST[87:80]-SRC[87:80]
DEST[95:88] <-DEST[95:88]-SRC[95:88]
DEST[103:96] <-DEST[103:96]-SRC[103:96]
DEST[111:104] <-DEST[111:104]-SRC[111:104]
DEST[119:112] <-DEST[119:112]-SRC[119:112]
DEST[127:120] <-DEST[127:120]-SRC[127:120]
DEST[MAX_VL-1:128] (Unmodified)

VPSUBW (VEX.256 encoded version)
DEST[15:0] <-SRC1[15:0]-SRC2[15:0]
DEST[31:16] <-SRC1[31:16]-SRC2[31:16]
DEST[47:32] <-SRC1[47:32]-SRC2[47:32]
DEST[63:48] <-SRC1[63:48]-SRC2[63:48]
DEST[79:64] <-SRC1[79:64]-SRC2[79:64]
DEST[95:80] <-SRC1[95:80]-SRC2[95:80]
DEST[111:96] <-SRC1[111:96]-SRC2[111:96]



DEST[127:112] <-SRC1[127:112]-SRC2[127:112]
DEST[143:128] <-SRC1[143:128]-SRC2[143:128]
DEST[159:144] <-SRC1[159:144]-SRC2[159:144]
DEST[175:160] <-SRC1[175:160]-SRC2[175:160]
DEST[191:176] <-SRC1[191:176]-SRC2[191:176]
DEST[207:192] <-SRC1207:192]-SRC2[207:192]
DEST[223:208] <-SRC1[223:208]-SRC2[223:208]
DEST[239:224] <-SRC1[239:224]-SRC2[239:224]
DEST[255:240] <-SRC1[255:240]-SRC2[255:240]
DEST[MAX_VL-1:256] <-0

VPSUBW (VEX.128 encoded version)
DEST[15:0] <-SRC1[15:0]-SRC2[15:0]
DEST[31:16] <-SRC1[31:16]-SRC2[31:16]
DEST[47:32] <-SRC1[47:32]-SRC2[47:32]
DEST[63:48] <-SRC1[63:48]-SRC2[63:48]
DEST[79:64] <-SRC1[79:64]-SRC2[79:64]
DEST[95:80] <-SRC1[95:80]-SRC2[95:80]
DEST[111:96] <-SRC1[111:96]-SRC2[111:96]
DEST[127:112] <-SRC1[127:112]-SRC2[127:112]
DEST[MAX_VL-1:128] <-0

PSUBW (128-bit Legacy SSE version)
DEST[15:0] <-DEST[15:0]-SRC[15:0]
DEST[31:16] <-DEST[31:16]-SRC[31:16]
DEST[47:32] <-DEST[47:32]-SRC[47:32]
DEST[63:48] <-DEST[63:48]-SRC[63:48]
DEST[79:64] <-DEST[79:64]-SRC[79:64]
DEST[95:80] <-DEST[95:80]-SRC[95:80]
DEST[111:96] <-DEST[111:96]-SRC[111:96]
DEST[127:112] <-DEST[127:112]-SRC[127:112]
DEST[MAX_VL-1:128] (Unmodified)

VPSUBD (VEX.256 encoded version)
DEST[31:0] <-SRC1[31:0]-SRC2[31:0]
DEST[63:32] <-SRC1[63:32]-SRC2[63:32]
DEST[95:64] <-SRC1[95:64]-SRC2[95:64]
DEST[127:96] <-SRC1[127:96]-SRC2[127:96]
DEST[159:128] <-SRC1[159:128]-SRC2[159:128]
DEST[191:160] <-SRC1[191:160]-SRC2[191:160]
DEST[223:192] <-SRC1[223:192]-SRC2[223:192]
DEST[255:224] <-SRC1[255:224]-SRC2[255:224]
DEST[MAX_VL-1:256] <-0

VPSUBD (VEX.128 encoded version)
DEST[31:0] <-SRC1[31:0]-SRC2[31:0]
DEST[63:32] <-SRC1[63:32]-SRC2[63:32]
DEST[95:64] <-SRC1[95:64]-SRC2[95:64]
DEST[127:96] <-SRC1[127:96]-SRC2[127:96]
DEST[MAX_VL-1:128] <-0

PSUBD (128-bit Legacy SSE version)
DEST[31:0] <-DEST[31:0]-SRC[31:0]
DEST[63:32] <-DEST[63:32]-SRC[63:32]



DEST[95:64] <-DEST[95:64]-SRC[95:64]
DEST[127:96] <-DEST[127:96]-SRC[127:96]
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents
VPSUBB __m512i _mm512_sub_epi8(__m512i a, __m512i b);
VPSUBB __m512i _mm512_mask_sub_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBB __m512i _mm512_maskz_sub_epi8( __mmask64 k, __m512i a, __m512i b);
VPSUBB __m256i _mm256_mask_sub_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBB __m256i _mm256_maskz_sub_epi8( __mmask32 k, __m256i a, __m256i b);
VPSUBB __m128i _mm_mask_sub_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBB __m128i _mm_maskz_sub_epi8( __mmask16 k, __m128i a, __m128i b);
VPSUBW __m512i _mm512_sub_epi16(__m512i a, __m512i b);
VPSUBW __m512i _mm512_mask_sub_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBW __m512i _mm512_maskz_sub_epi16( __mmask32 k, __m512i a, __m512i b);
VPSUBW __m256i _mm256_mask_sub_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBW __m256i _mm256_maskz_sub_epi16( __mmask16 k, __m256i a, __m256i b);
VPSUBW __m128i _mm_mask_sub_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBW __m128i _mm_maskz_sub_epi16( __mmask8 k, __m128i a, __m128i b);
VPSUBD __m512i _mm512_sub_epi32(__m512i a, __m512i b);
VPSUBD __m512i _mm512_mask_sub_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPSUBD __m512i _mm512_maskz_sub_epi32( __mmask16 k, __m512i a, __m512i b);
VPSUBD __m256i _mm256_mask_sub_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPSUBD __m256i _mm256_maskz_sub_epi32( __mmask8 k, __m256i a, __m256i b);
VPSUBD __m128i _mm_mask_sub_epi32(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBD __m128i _mm_maskz_sub_epi32( __mmask8 k, __m128i a, __m128i b);
PSUBB:__m64 _mm_sub_pi8(__m64 m1, __m64 m2)
(V)PSUBB:__m128i _mm_sub_epi8 ( __m128i a, __m128i b)
VPSUBB:__m256i _mm256_sub_epi8 ( __m256i a, __m256i b)
PSUBW:__m64 _mm_sub_pi16(__m64 m1, __m64 m2)
(V)PSUBW:__m128i _mm_sub_epi16 ( __m128i a, __m128i b)
VPSUBW:__m256i _mm256_sub_epi16 ( __m256i a, __m256i b)
PSUBD:__m64 _mm_sub_pi32(__m64 m1, __m64 m2)
(V)PSUBD:__m128i _mm_sub_epi32 ( __m128i a, __m128i b)
VPSUBD:__m256i _mm256_sub_epi32 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPSUBD, see Exceptions Type E4.
EVEX-encoded VPSUBB/W, see Exceptions Type E4.nb.






platform: x86_64
mnem: PSUBQ
description:
PSUBQ-Subtract Packed Quadword Integers
Opcode/                                              Op/   64/32 bit   CPUID        Description
Instruction                                          En    Mode        Feature
                                                           Support     Flag
0F FB /r1                                            RM    V/V         SSE2         Subtract quadword integer in mm1 from mm2
PSUBQ mm1, mm2/m64                                                                  /m64.

66 0F FB /r                                          RM    V/V         SSE2         Subtract packed quadword integers in xmm1
PSUBQ xmm1, xmm2/m128                                                               from xmm2 /m128.

VEX.NDS.128.66.0F.WIG FB/r                           RVM V/V           AVX          Subtract packed quadword integers in
VPSUBQ xmm1, xmm2, xmm3/m128                                                        xmm3/m128 from xmm2.

VEX.NDS.256.66.0F.WIG FB /r                          RVM V/V           AVX2         Subtract packed quadword integers in
VPSUBQ ymm1, ymm2, ymm3/m256                                                        ymm3/m256 from ymm2.

EVEX.NDS.128.66.0F.W1 FB /r                  FV            V/V         AVX512VL Subtract packed quadword integers in
VPSUBQ xmm1 {k1}{z}, xmm2, xmm3/m128/m64bcst                           AVX512F  xmm3/m128/m64bcst from xmm2 and store
                                                                                in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.W1 FB /r                  FV            V/V         AVX512VL Subtract packed quadword integers in
VPSUBQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst                           AVX512F  ymm3/m256/m64bcst from ymm2 and store
                                                                                in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.W1 FB/r                   FV            V/V         AVX512F      Subtract packed quadword integers in
VPSUBQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst                                        zmm3/m512/m64bcst from zmm2 and store
                                                                                    in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En             Operand 1                   Operand 2                     Operand 3                     Operand 4
    RM            ModRM:reg (r, w)             ModRM:r/m (r)                       NA                            NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                      NA
    FV            ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                      NA


Description
Subtracts the second operand (source operand) from the first operand (destination operand) and stores the result
in the destination operand. When packed quadword operands are used, a SIMD subtract is performed. When a
quadword result is too large to be represented in 64 bits (overflow), the result is wrapped around and the low 64
bits are written to the destination element (that is, the carry is ignored).
Note that the (V)PSUBQ instruction can operate on either unsigned or signed (two's complement notation) inte-
gers; however, it does not set bits in the EFLAGS register to indicate overflow and/or a carry. To prevent undetected
overflow conditions, software must control the ranges of the values upon which it operates.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The source operand can be a quadword integer stored in an MMX technology
register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-
nation register remain unchanged.





VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded VPSUBQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit memory loca-
tion or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source operand and
destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with writemask k1.

Operation
PSUBQ (with 64-Bit operands)
  DEST[63:0] <- DEST[63:0] - SRC[63:0];

PSUBQ (with 128-Bit operands)
  DEST[63:0] <- DEST[63:0] - SRC[63:0];
  DEST[127:64] <- DEST[127:64] - SRC[127:64];

VPSUBQ (VEX.128 encoded version)
DEST[63:0] <- SRC1[63:0]-SRC2[63:0]
DEST[127:64] <- SRC1[127:64]-SRC2[127:64]
DEST[VLMAX-1:128] <- 0

VPSUBQ (VEX.256 encoded version)
DEST[63:0] <- SRC1[63:0]-SRC2[63:0]
DEST[127:64] <- SRC1[127:64]-SRC2[127:64]
DEST[191:128] <- SRC1[191:128]-SRC2[191:128]
DEST[255:192] <- SRC1[255:192]-SRC2[255:192]
DEST[VLMAX-1:256] <- 0

VPSUBQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- SRC1[i+63:i] - SRC2[63:0]
                    ELSE DEST[i+63:i] <- SRC1[i+63:i] - SRC2[i+63:i]
               FI;
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+63:i] remains unchanged*
                    ELSE *zeroing-masking*               ; zeroing-masking
                         DEST[i+63:i] <- 0
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPSUBQ __m512i _mm512_sub_epi64(__m512i a, __m512i b);
VPSUBQ __m512i _mm512_mask_sub_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPSUBQ __m512i _mm512_maskz_sub_epi64( __mmask8 k, __m512i a, __m512i b);
VPSUBQ __m256i _mm256_mask_sub_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);



VPSUBQ __m256i _mm256_maskz_sub_epi64( __mmask8 k, __m256i a, __m256i b);
VPSUBQ __m128i _mm_mask_sub_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBQ __m128i _mm_maskz_sub_epi64( __mmask8 k, __m128i a, __m128i b);
PSUBQ:__m64 _mm_sub_si64(__m64 m1, __m64 m2)
(V)PSUBQ:__m128i _mm_sub_epi64(__m128i m1, __m128i m2)
VPSUBQ:__m256i _mm256_sub_epi64(__m256i m1, __m256i m2)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPSUBQ, see Exceptions Type E4.






platform: x86_64
mnem: PSUBSB
description:
PSUBSB/PSUBSW-Subtract Packed Signed Integers with Signed Saturation
 Opcode/                                              Op/   64/32 bit   CPUID       Description
 Instruction                                          En    Mode        Feature
                                                            Support     Flag
 0F E8 /r1                                            RM    V/V         MMX         Subtract signed packed bytes in mm/m64 from
 PSUBSB mm, mm/m64                                                                  signed packed bytes in mm and saturate results.

 66 0F E8 /r                                          RM    V/V         SSE2        Subtract packed signed byte integers in
 PSUBSB xmm1, xmm2/m128                                                             xmm2/m128 from packed signed byte integers
                                                                                    in xmm1 and saturate results.
 0F E9 /r1                                            RM    V/V         MMX         Subtract signed packed words in mm/m64 from
 PSUBSW mm, mm/m64                                                                  signed packed words in mm and saturate
                                                                                    results.
 66 0F E9 /r                                          RM    V/V         SSE2        Subtract packed signed word integers in
 PSUBSW xmm1, xmm2/m128                                                             xmm2/m128 from packed signed word integers
                                                                                    in xmm1 and saturate results.
 VEX.NDS.128.66.0F.WIG E8 /r                          RVM V/V           AVX         Subtract packed signed byte integers in
 VPSUBSB xmm1, xmm2, xmm3/m128                                                      xmm3/m128 from packed signed byte integers
                                                                                    in xmm2 and saturate results.
 VEX.NDS.128.66.0F.WIG E9 /r                          RVM V/V           AVX         Subtract packed signed word integers in
 VPSUBSW xmm1, xmm2, xmm3/m128                                                      xmm3/m128 from packed signed word integers
                                                                                    in xmm2 and saturate results.
 VEX.NDS.256.66.0F.WIG E8 /r                          RVM V/V           AVX2        Subtract packed signed byte integers in
 VPSUBSB ymm1, ymm2, ymm3/m256                                                      ymm3/m256 from packed signed byte integers
                                                                                    in ymm2 and saturate results.
 VEX.NDS.256.66.0F.WIG E9 /r                          RVM V/V           AVX2        Subtract packed signed word integers in
 VPSUBSW ymm1, ymm2, ymm3/m256                                                      ymm3/m256 from packed signed word integers
                                                                                    in ymm2 and saturate results.
 EVEX.NDS.128.66.0F.WIG E8 /r                         FVM V/V           AVX512VL Subtract packed signed byte integers in
 VPSUBSB xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW xmm3/m128 from packed signed byte integers
                                                                                 in xmm2 and saturate results and store in
                                                                                 xmm1 using writemask k1.
 EVEX.NDS.256.66.0F.WIG E8 /r                         FVM V/V           AVX512VL Subtract packed signed byte integers in
 VPSUBSB ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW ymm3/m256 from packed signed byte integers
                                                                                 in ymm2 and saturate results and store in
                                                                                 ymm1 using writemask k1.
 EVEX.NDS.512.66.0F.WIG E8 /r                         FVM V/V           AVX512BW Subtract packed signed byte integers in
 VPSUBSB zmm1 {k1}{z}, zmm2, zmm3/m512                                           zmm3/m512 from packed signed byte integers
                                                                                 in zmm2 and saturate results and store in zmm1
                                                                                 using writemask k1.
 EVEX.NDS.128.66.0F.WIG E9 /r                         FVM V/V           AVX512VL Subtract packed signed word integers in
 VPSUBSW xmm1 {k1}{z}, xmm2, xmm3/m128                                  AVX512BW xmm3/m128 from packed signed word integers
                                                                                 in xmm2 and saturate results and store in
                                                                                 xmm1 using writemask k1.
 EVEX.NDS.256.66.0F.WIG E9 /r                         FVM V/V           AVX512VL Subtract packed signed word integers in
 VPSUBSW ymm1 {k1}{z}, ymm2, ymm3/m256                                  AVX512BW ymm3/m256 from packed signed word integers
                                                                                 in ymm2 and saturate results and store in
                                                                                 ymm1 using writemask k1.





EVEX.NDS.512.66.0F.WIG E9 /r                      FVM V/V            AVX512BW Subtract packed signed word integers in
VPSUBSW zmm1 {k1}{z}, zmm2, zmm3/m512                                         zmm3/m512 from packed signed word integers
                                                                              in zmm2 and saturate results and store in zmm1
                                                                              using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                     Operand 2                    Operand 3                      Operand 4
    RM           ModRM:reg (r, w)               ModRM:r/m (r)                      NA                             NA
   RVM            ModRM:reg (w)                  VEX.vvvv (r)                ModRM:r/m (r)                        NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                        NA


Description
Performs a SIMD subtract of the packed signed integers of the source operand (second operand) from the packed
signed integers of the destination operand (first operand), and stores the packed integer results in the destination
operand. See Figure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, for an
illustration of a SIMD operation. Overflow is handled with signed saturation, as described in the following para-
graphs.
The (V)PSUBSB instruction subtracts packed signed byte integers. When an individual byte result is beyond the
range of a signed byte integer (that is, greater than 7FH or less than 80H), the saturated value of 7FH or 80H,
respectively, is written to the destination operand.
The (V)PSUBSW instruction subtracts packed signed word integers. When an individual word result is beyond the
range of a signed word integer (that is, greater than 7FFFH or less than 8000H), the saturated value of 7FFFH or
8000H, respectively, is written to the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-
nation register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-
tionally updated with writemask k1.

Operation
PSUBSB (with 64-bit operands)
  DEST[7:0] <- SaturateToSignedByte (DEST[7:0] - SRC (7:0]);
  (* Repeat subtract operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToSignedByte (DEST[63:56] - SRC[63:56] );




PSUBSW (with 64-bit operands)
  DEST[15:0] <- SaturateToSignedWord (DEST[15:0] - SRC[15:0] );
  (* Repeat subtract operation for 2nd and 7th words *)
  DEST[63:48] <- SaturateToSignedWord (DEST[63:48] - SRC[63:48] );

VPSUBSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i <- j * 8;
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SaturateToSignedByte (SRC1[i+7:i] - SRC2[i+7:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+7:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+7:i] <- 0;
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

VPSUBSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SaturateToSignedWord (SRC1[i+15:i] - SRC2[i+15:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0;
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;

VPSUBSB (VEX.256 encoded version)
DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31th bytes *)
DEST[255:248] <- SaturateToSignedByte (SRC1[255:248] - SRC2[255:248]);
DEST[MAX_VL-1:256] <-0;

VPSUBSB (VEX.128 encoded version)
DEST[7:0] <- SaturateToSignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToSignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[MAX_VL-1:128] <- 0;

PSUBSB (128-bit Legacy SSE Version)
DEST[7:0] <- SaturateToSignedByte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToSignedByte (DEST[127:120] - SRC[127:120]);
DEST[MAX_VL-1:128] (Unmodified);



VPSUBSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] <- SaturateToSignedWord (SRC1[255:240] - SRC2[255:240]);
DEST[MAX_VL-1:256] <- 0;

VPSUBSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToSignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToSignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[MAX_VL-1:128] <- 0;

PSUBSW (128-bit Legacy SSE Version)
DEST[15:0] <- SaturateToSignedWord (DEST[15:0] - SRC[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToSignedWord (DEST[127:112] - SRC[127:112]);
DEST[MAX_VL-1:128] (Unmodified);

Intel C/C++ Compiler Intrinsic Equivalents
VPSUBSB __m512i _mm512_subs_epi8(__m512i a, __m512i b);
VPSUBSB __m512i _mm512_mask_subs_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m512i _mm512_maskz_subs_epi8( __mmask64 k, __m512i a, __m512i b);
VPSUBSB __m256i _mm256_mask_subs_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m256i _mm256_maskz_subs_epi8( __mmask32 k, __m256i a, __m256i b);
VPSUBSB __m128i _mm_mask_subs_epi8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBSB __m128i _mm_maskz_subs_epi8( __mmask16 k, __m128i a, __m128i b);
VPSUBSW __m512i _mm512_subs_epi16(__m512i a, __m512i b);
VPSUBSW __m512i _mm512_mask_subs_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m512i _mm512_maskz_subs_epi16( __mmask32 k, __m512i a, __m512i b);
VPSUBSW __m256i _mm256_mask_subs_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m256i _mm256_maskz_subs_epi16( __mmask16 k, __m256i a, __m256i b);
VPSUBSW __m128i _mm_mask_subs_epi16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBSW __m128i _mm_maskz_subs_epi16( __mmask8 k, __m128i a, __m128i b);
PSUBSB:__m64 _mm_subs_pi8(__m64 m1, __m64 m2)
(V)PSUBSB:__m128i _mm_subs_epi8(__m128i m1, __m128i m2)
VPSUBSB:__m256i _mm256_subs_epi8(__m256i m1, __m256i m2)
PSUBSW:__m64 _mm_subs_pi16(__m64 m1, __m64 m2)
(V)PSUBSW:__m128i _mm_subs_epi16(__m128i m1, __m128i m2)
VPSUBSW:__m256i _mm256_subs_epi16(__m256i m1, __m256i m2)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.nb.






platform: x86_64
mnem: PSUBUSB
description:
PSUBUSB/PSUBUSW-Subtract Packed Unsigned Integers with Unsigned Saturation
Opcode/                                                Op/   64/32 bit       CPUID       Description
Instruction                                            En    Mode            Feature
                                                             Support         Flag
0F D8 /r1                                              RM    V/V             MMX         Subtract unsigned packed bytes in mm/m64
PSUBUSB mm, mm/m64                                                                       from unsigned packed bytes in mm and
                                                                                         saturate result.
66 0F D8 /r                                            RM    V/V             SSE2        Subtract packed unsigned byte integers in
PSUBUSB xmm1, xmm2/m128                                                                  xmm2/m128 from packed unsigned byte
                                                                                         integers in xmm1 and saturate result.
0F D9 /r1                                              RM    V/V             MMX         Subtract unsigned packed words in mm/m64
PSUBUSW mm, mm/m64                                                                       from unsigned packed words in mm and
                                                                                         saturate result.
66 0F D9 /r                                            RM    V/V             SSE2        Subtract packed unsigned word integers in
PSUBUSW xmm1, xmm2/m128                                                                  xmm2/m128 from packed unsigned word
                                                                                         integers in xmm1 and saturate result.
VEX.NDS.128.66.0F.WIG D8 /r                            RVM V/V               AVX         Subtract packed unsigned byte integers in
VPSUBUSB xmm1, xmm2, xmm3/m128                                                           xmm3/m128 from packed unsigned byte
                                                                                         integers in xmm2 and saturate result.
VEX.NDS.128.66.0F.WIG D9 /r                            RVM V/V               AVX         Subtract packed unsigned word integers in
VPSUBUSW xmm1, xmm2, xmm3/m128                                                           xmm3/m128 from packed unsigned word
                                                                                         integers in xmm2 and saturate result.
VEX.NDS.256.66.0F.WIG D8 /r                            RVM V/V               AVX2        Subtract packed unsigned byte integers in
VPSUBUSB ymm1, ymm2, ymm3/m256                                                           ymm3/m256 from packed unsigned byte
                                                                                         integers in ymm2 and saturate result.
VEX.NDS.256.66.0F.WIG D9 /r                            RVM V/V               AVX2        Subtract packed unsigned word integers in
VPSUBUSW ymm1, ymm2, ymm3/m256                                                           ymm3/m256 from packed unsigned word
                                                                                         integers in ymm2 and saturate result.
EVEX.NDS.128.66.0F.WIG D8 /r                           FVM V/V               AVX512VL Subtract packed unsigned byte integers in
VPSUBUSB xmm1 {k1}{z}, xmm2, xmm3/m128                                       AVX512BW xmm3/m128 from packed unsigned byte
                                                                                      integers in xmm2, saturate results and store
                                                                                      in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG D8 /r                           FVM V/V               AVX512VL Subtract packed unsigned byte integers in
VPSUBUSB ymm1 {k1}{z}, ymm2, ymm3/m256                                       AVX512BW ymm3/m256 from packed unsigned byte
                                                                                      integers in ymm2, saturate results and store
                                                                                      in ymm1 using writemask k1.
EVEX.NDS.512.66.0F.WIG D8 /r                           FVM V/V               AVX512BW Subtract packed unsigned byte integers in
VPSUBUSB zmm1 {k1}{z}, zmm2, zmm3/m512                                                zmm3/m512 from packed unsigned byte
                                                                                      integers in zmm2, saturate results and store
                                                                                      in zmm1 using writemask k1.
EVEX.NDS.128.66.0F.WIG D9 /r                           FVM V/V               AVX512VL Subtract packed unsigned word integers in
VPSUBUSW xmm1 {k1}{z}, xmm2, xmm3/m128                                       AVX512BW xmm3/m128 from packed unsigned word
                                                                                      integers in xmm2 and saturate results and
                                                                                      store in xmm1 using writemask k1.
EVEX.NDS.256.66.0F.WIG D9 /r                           FVM V/V               AVX512VL Subtract packed unsigned word integers in
VPSUBUSW ymm1 {k1}{z}, ymm2, ymm3/m256                                       AVX512BW ymm3/m256 from packed unsigned word
                                                                                      integers in ymm2, saturate results and store
                                                                                      in ymm1 using writemask k1.





EVEX.NDS.512.66.0F.WIG D9 /r                        FVM V/V            AVX512BW Subtract packed unsigned word integers in
VPSUBUSW zmm1 {k1}{z}, zmm2, zmm3/m512                                          zmm3/m512 from packed unsigned word
                                                                                integers in zmm2, saturate results and store
                                                                                in zmm1 using writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En            Operand 1                     Operand 2                    Operand 3                      Operand 4
    RM          ModRM:reg (r, w)               ModRM:r/m (r)                     NA                              NA
   RVM           ModRM:reg (w)                  VEX.vvvv (r)                ModRM:r/m (r)                       NA
   FVM           ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                        NA


Description
Performs a SIMD subtract of the packed unsigned integers of the source operand (second operand) from the
packed unsigned integers of the destination operand (first operand), and stores the packed unsigned integer
results in the destination operand. See Figure 9-4 in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for an illustration of a SIMD operation. Overflow is handled with unsigned saturation, as
described in the following paragraphs.
These instructions can operate on either 64-bit or 128-bit operands.
The (V)PSUBUSB instruction subtracts packed unsigned byte integers. When an individual byte result is less than
zero, the saturated value of 00H is written to the destination operand.
The (V)PSUBUSW instruction subtracts packed unsigned word integers. When an individual word result is less than
zero, the saturated value of 0000H is written to the destination operand.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE version 64-bit operand: The destination operand must be an MMX technology register and the source
operand can be either an MMX technology register or a 64-bit memory location.
128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-
nation register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded versions: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.
EVEX encoded version: The second source operand is an ZMM/YMM/XMM register or an 512/256/128-bit memory
location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination is condi-
tionally updated with writemask k1.

Operation
PSUBUSB (with 64-bit operands)
  DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] - SRC (7:0] );
  (* Repeat add operation for 2nd through 7th bytes *)
  DEST[63:56] <- SaturateToUnsignedByte (DEST[63:56] - SRC[63:56];




PSUBUSW (with 64-bit operands)
  DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] - SRC[15:0] );
  (* Repeat add operation for 2nd and 3rd words *)
  DEST[63:48] <- SaturateToUnsignedWord (DEST[63:48] - SRC[63:48] );

VPSUBUSB (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
FOR j <- 0 TO KL-1
    i <- j * 8;
    IF k1[j] OR *no writemask*
         THEN DEST[i+7:i] <- SaturateToUnsignedByte (SRC1[i+7:i] - SRC2[i+7:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+7:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+7:i] <- 0;
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;

VPSUBUSW (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
FOR j <- 0 TO KL-1
    i <- j * 16;
    IF k1[j] OR *no writemask*
         THEN DEST[i+15:i] <- SaturateToUnsignedWord (SRC1[i+15:i] - SRC2[i+15:i])
         ELSE
               IF *merging-masking*                ; merging-masking
                    THEN *DEST[i+15:i] remains unchanged*
                    ELSE *zeroing-masking*              ; zeroing-masking
                        DEST[i+15:i] <- 0;
               FI
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0;

VPSUBUSB (VEX.256 encoded version)
DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 31st bytes *)
DEST[255:148] <- SaturateToUnsignedByte (SRC1[255:248] - SRC2[255:248]);
DEST[MAX_VL-1:256] <- 0;

VPSUBUSB (VEX.128 encoded version)
DEST[7:0] <- SaturateToUnsignedByte (SRC1[7:0] - SRC2[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToUnsignedByte (SRC1[127:120] - SRC2[127:120]);
DEST[MAX_VL-1:128] <- 0

PSUBUSB (128-bit Legacy SSE Version)
DEST[7:0] <- SaturateToUnsignedByte (DEST[7:0] - SRC[7:0]);
(* Repeat subtract operation for 2nd through 14th bytes *)
DEST[127:120] <- SaturateToUnsignedByte (DEST[127:120] - SRC[127:120]);
DEST[MAX_VL-1:128] (Unmodified)



VPSUBUSW (VEX.256 encoded version)
DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 15th words *)
DEST[255:240] <- SaturateToUnsignedWord (SRC1[255:240] - SRC2[255:240]);
DEST[MAX_VL-1:256] <- 0;

VPSUBUSW (VEX.128 encoded version)
DEST[15:0] <- SaturateToUnsignedWord (SRC1[15:0] - SRC2[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToUnsignedWord (SRC1[127:112] - SRC2[127:112]);
DEST[MAX_VL-1:128] <- 0

PSUBUSW (128-bit Legacy SSE Version)
DEST[15:0] <- SaturateToUnsignedWord (DEST[15:0] - SRC[15:0]);
(* Repeat subtract operation for 2nd through 7th words *)
DEST[127:112] <- SaturateToUnsignedWord (DEST[127:112] - SRC[127:112]);
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalents
VPSUBUSB __m512i _mm512_subs_epu8(__m512i a, __m512i b);
VPSUBUSB __m512i _mm512_mask_subs_epu8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPSUBUSB __m512i _mm512_maskz_subs_epu8( __mmask64 k, __m512i a, __m512i b);
VPSUBUSB __m256i _mm256_mask_subs_epu8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPSUBUSB __m256i _mm256_maskz_subs_epu8( __mmask32 k, __m256i a, __m256i b);
VPSUBUSB __m128i _mm_mask_subs_epu8(__m128i s, __mmask16 k, __m128i a, __m128i b);
VPSUBUSB __m128i _mm_maskz_subs_epu8( __mmask16 k, __m128i a, __m128i b);
VPSUBUSW __m512i _mm512_subs_epu16(__m512i a, __m512i b);
VPSUBUSW __m512i _mm512_mask_subs_epu16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m512i _mm512_maskz_subs_epu16( __mmask32 k, __m512i a, __m512i b);
VPSUBUSW __m256i _mm256_mask_subs_epu16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m256i _mm256_maskz_subs_epu16( __mmask16 k, __m256i a, __m256i b);
VPSUBUSW __m128i _mm_mask_subs_epu16(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPSUBUSW __m128i _mm_maskz_subs_epu16( __mmask8 k, __m128i a, __m128i b);
PSUBUSB:__m64 _mm_subs_pu8(__m64 m1, __m64 m2)
(V)PSUBUSB:__m128i _mm_subs_epu8(__m128i m1, __m128i m2)
VPSUBUSB:__m256i _mm256_subs_epu8(__m256i m1, __m256i m2)
PSUBUSW:__m64 _mm_subs_pu16(__m64 m1, __m64 m2)
(V)PSUBUSW:__m128i _mm_subs_epu16(__m128i m1, __m128i m2)
VPSUBUSW:__m256i _mm256_subs_epu16(__m256i m1, __m256i m2)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: PTEST
description:
PTEST- Logical Compare
 Opcode/                                             Op/   64/32 bit   CPUID     Description
 Instruction                                         En    Mode        Feature
                                                           Support     Flag
 66 0F 38 17 /r                                      RM    V/V         SSE4_1    Set ZF if xmm2/m128 AND xmm1 result is all
 PTEST xmm1, xmm2/m128                                                           0s. Set CF if xmm2/m128 AND NOT xmm1
                                                                                 result is all 0s.
 VEX.128.66.0F38.WIG 17 /r                           RM    V/V         AVX       Set ZF and CF depending on bitwise AND and
 VPTEST xmm1, xmm2/m128                                                          ANDN of sources.
 VEX.256.66.0F38.WIG 17 /r                           RM    V/V         AVX       Set ZF and CF depending on bitwise AND and
 VPTEST ymm1, ymm2/m256                                                          ANDN of sources.



                                             Instruction Operand Encoding
   Op/En                 Operand 1                Operand 2                  Operand 3                   Operand 4
     RM              ModRM:reg (r)            ModRM:r/m (r)                      NA                         NA


Description
PTEST and VPTEST set the ZF flag if all bits in the result are 0 of the bitwise AND of the first source operand (first
operand) and the second source operand (second operand). VPTEST sets the CF flag if all bits in the result are 0 of
the bitwise AND of the second source operand (second operand) and the logical NOT of the destination operand.
The first source register is specified by the ModR/M reg field.
128-bit versions: The first source register is an XMM register. The second source register can be an XMM register
or a 128-bit memory location. The destination register is not modified.
VEX.256 encoded version: The first source register is a YMM register. The second source register can be a YMM
register or a 256-bit memory location. The destination register is not modified.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.

Operation
(V)PTEST (128-bit version)
IF (SRC[127:0] BITWISE AND DEST[127:0] = 0)
    THEN ZF <- 1;
    ELSE ZF <- 0;
IF (SRC[127:0] BITWISE AND NOT DEST[127:0] = 0)
    THEN CF <- 1;
    ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;

VPTEST (VEX.256 encoded version)
IF (SRC[255:0] BITWISE AND DEST[255:0] = 0) THEN ZF <- 1;
    ELSE ZF <- 0;
IF (SRC[255:0] BITWISE AND NOT DEST[255:0] = 0) THEN CF <- 1;
    ELSE CF <- 0;
DEST (unmodified)
AF <- OF <- PF <- SF <- 0;





Intel C/C++ Compiler Intrinsic Equivalent

PTEST
int _mm_testz_si128 (__m128i s1, __m128i s2);
int _mm_testc_si128 (__m128i s1, __m128i s2);
int _mm_testnzc_si128 (__m128i s1, __m128i s2);


VPTEST
int _mm256_testz_si256 (__m256i s1, __m256i s2);
int _mm256_testc_si256 (__m256i s1, __m256i s2);
int _mm256_testnzc_si256 (__m256i s1, __m256i s2);
int _mm_testz_si128 (__m128i s1, __m128i s2);
int _mm_testc_si128 (__m128i s1, __m128i s2);
int _mm_testnzc_si128 (__m128i s1, __m128i s2);

Flags Affected
The 0F, AF, PF, SF flags are cleared and the ZF, CF flags are set according to the operation.

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                   If VEX.vvvv != 1111B.






platform: x86_64
mnem: PTWRITE
description:
PTWRITE - Write Data to a Processor Trace Packet
 Opcode/                                               Op/   64/32 bit   CPUID     Description
 Instruction                                           En    Mode        Feature
                                                             Support     Flag
 F3 REX.W 0F AE /4                                     RM    V/N.E                 Reads the data from r64/m64 to encod into a
 PTWRITE r64/m64                                                                   PTW packet if dependencies are met (see
                                                                                   details below).
 F3 0F AE /4                                           RM    V/V                   Reads the data from r32/m32 to encode into a
 PTWRITE r32/m32                                                                   PTW packet if dependencies are met (see
                                                                                   details below).



                                                   Instruction Operand Encoding
   Op/En               Operand 1                    Operand 2                  Operand 3                   Operand 4
     RM               ModRM:rm (r)                     NA                          NA                          NA


Description
This instruction reads data in the source operand and sends it to the Intel Processor Trace hardware to be encoded
in a PTW packet if TriggerEn, ContextEn, FilterEn, and PTWEn are all set to 1. For more details on these values, see
Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3C, Section 36.2.3, "Power Event
Tracing". The size of data is 64-bit if using REX.W in 64-bit mode, otherwise 32-bits of data are copied from the
source operand.
Note: The instruction will #UD if prefix 66H is used.

Operation
IF (IA32_RTIT_STATUS.TriggerEn & IA32_RTIT_STATUS.ContextEn & IA32_RTIT_STATUS.FilterEn & IA32_RTIT_CTL.PTWEn) = 1
     PTW.PayloadBytes <- Encoded payload size;
     PTW.IP <- IA32_RTIT_CTL.FUPonPTW
     IF IA32_RTIT_CTL.FUPonPTW = 1
          Insert FUP packet with IP of PTWRITE;
     FI;
FI;

Flags Affected
None.

Other Exceptions
#GP(0)                    If a memory operand effective address is outside the CS, DS, ES, FS or GS segments.
#SS(0)                    If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)          For a page fault.
#AC(0)                    If an unaligned memory reference is made while the current privilege level is 3 and alignment
                          checking is enabled.
#UD                       If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
                          If LOCK prefix is used.
                          If 66H prefix is used.





Real-Address Mode Exceptions
#GP(0)              If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#UD                 If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
                    If LOCK prefix is used.
                    If 66H prefix is used.

Virtual 8086 Mode Exceptions
#GP(0)              If any part of the operand lies outside of the effective address space from 0 to 0FFFFH.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF (fault-code)    For a page fault.
#AC(0)              If an unaligned memory reference is made while alignment checking is enabled.
#UD                 If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
                    If LOCK prefix is used.
                    If 66H prefix is used.

Compatibility Mode Exceptions
Same exceptions as in Protected Mode.

64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#PF (fault-code)    For a page fault.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If CPUID.(EAX=14H, ECX=0):EBX.PTWRITE [Bit 4] = 0.
                    If LOCK prefix is used.
                    If 66H prefix is used.






platform: x86_64
mnem: PUNPCKHBW
description:
PUNPCKHBW/PUNPCKHWD/PUNPCKHDQ/PUNPCKHQDQ- Unpack High Data
Opcode/                                        Op/   64/32 bit   CPUID      Description
Instruction                                    En    Mode        Feature
                                                     Support     Flag
0F 68 /r1                                      RM    V/V         MMX        Unpack and interleave high-order bytes from
PUNPCKHBW mm, mm/m64                                                        mm and mm/m64 into mm.

66 0F 68 /r                                    RM    V/V         SSE2       Unpack and interleave high-order bytes from
PUNPCKHBW xmm1, xmm2/m128                                                   xmm1 and xmm2/m128 into xmm1.

0F 69 /r1                                      RM    V/V         MMX        Unpack and interleave high-order words from
PUNPCKHWD mm, mm/m64                                                        mm and mm/m64 into mm.

66 0F 69 /r                                    RM    V/V         SSE2       Unpack and interleave high-order words from
PUNPCKHWD xmm1, xmm2/m128                                                   xmm1 and xmm2/m128 into xmm1.

0F 6A /r1                                      RM    V/V         MMX        Unpack and interleave high-order
PUNPCKHDQ mm, mm/m64                                                        doublewords from mm and mm/m64 into mm.

66 0F 6A /r                                    RM    V/V         SSE2       Unpack and interleave high-order
PUNPCKHDQ xmm1, xmm2/m128                                                   doublewords from xmm1 and xmm2/m128
                                                                            into xmm1.
66 0F 6D /r                                    RM    V/V         SSE2       Unpack and interleave high-order quadwords
PUNPCKHQDQ xmm1, xmm2/m128                                                  from xmm1 and xmm2/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 68/r                     RVM V/V           AVX        Interleave high-order bytes from xmm2 and
VPUNPCKHBW xmm1,xmm2, xmm3/m128                                             xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 69/r                     RVM V/V           AVX        Interleave high-order words from xmm2 and
VPUNPCKHWD xmm1,xmm2, xmm3/m128                                             xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 6A/r                     RVM V/V           AVX        Interleave high-order doublewords from
VPUNPCKHDQ xmm1, xmm2, xmm3/m128                                            xmm2 and xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 6D/r                     RVM V/V           AVX        Interleave high-order quadword from xmm2
VPUNPCKHQDQ xmm1, xmm2, xmm3/m128                                           and xmm3/m128 into xmm1 register.
VEX.NDS.256.66.0F.WIG 68 /r                    RVM V/V           AVX2       Interleave high-order bytes from ymm2 and
VPUNPCKHBW ymm1, ymm2, ymm3/m256                                            ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 69 /r                    RVM V/V           AVX2       Interleave high-order words from ymm2 and
VPUNPCKHWD ymm1, ymm2, ymm3/m256                                            ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 6A /r                    RVM V/V           AVX2       Interleave high-order doublewords from
VPUNPCKHDQ ymm1, ymm2, ymm3/m256                                            ymm2 and ymm3/m256 into ymm1 register.
VEX.NDS.256.66.0F.WIG 6D /r                    RVM V/V           AVX2       Interleave high-order quadword from ymm2
VPUNPCKHQDQ ymm1, ymm2, ymm3/m256                                           and ymm3/m256 into ymm1 register.
EVEX.NDS.128.66.0F.WIG 68 /r                   FVM V/V           AVX512VL Interleave high-order bytes from xmm2 and
VPUNPCKHBW xmm1 {k1}{z}, xmm2, xmm3/m128                         AVX512BW xmm3/m128 into xmm1 register using k1
                                                                          write mask.

EVEX.NDS.128.66.0F.WIG 69 /r                   FVM V/V           AVX512VL Interleave high-order words from xmm2 and
VPUNPCKHWD xmm1 {k1}{z}, xmm2, xmm3/m128                         AVX512BW xmm3/m128 into xmm1 register using k1
                                                                          write mask.
EVEX.NDS.128.66.0F.W0 6A /r                    FV    V/V         AVX512VL   Interleave high-order doublewords from
VPUNPCKHDQ xmm1 {k1}{z}, xmm2,                                   AVX512F    xmm2 and xmm3/m128/m32bcst into xmm1
xmm3/m128/m32bcst                                                           register using k1 write mask.
EVEX.NDS.128.66.0F.W1 6D /r                    FV    V/V         AVX512VL   Interleave high-order quadword from xmm2
VPUNPCKHQDQ xmm1 {k1}{z}, xmm2,                                  AVX512F    and xmm3/m128/m64bcst into xmm1
xmm3/m128/m64bcst                                                           register using k1 write mask.





EVEX.NDS.256.66.0F.WIG 68 /r                        FVM V/V           AVX512VL Interleave high-order bytes from ymm2 and
VPUNPCKHBW ymm1 {k1}{z}, ymm2, ymm3/m256                              AVX512BW ymm3/m256 into ymm1 register using k1
                                                                               write mask.
EVEX.NDS.256.66.0F.WIG 69 /r                        FVM V/V           AVX512VL Interleave high-order words from ymm2 and
VPUNPCKHWD ymm1 {k1}{z}, ymm2, ymm3/m256                              AVX512BW ymm3/m256 into ymm1 register using k1
                                                                               write mask.
EVEX.NDS.256.66.0F.W0 6A /r                         FV    V/V         AVX512VL     Interleave high-order doublewords from
VPUNPCKHDQ ymm1 {k1}{z}, ymm2,                                        AVX512F      ymm2 and ymm3/m256/m32bcst into ymm1
ymm3/m256/m32bcst                                                                  register using k1 write mask.

EVEX.NDS.256.66.0F.W1 6D /r                         FV    V/V         AVX512VL     Interleave high-order quadword from ymm2
VPUNPCKHQDQ ymm1 {k1}{z}, ymm2,                                       AVX512F      and ymm3/m256/m64bcst into ymm1
ymm3/m256/m64bcst                                                                  register using k1 write mask.

EVEX.NDS.512.66.0F.WIG 68/r                         FVM V/V           AVX512BW Interleave high-order bytes from zmm2 and
VPUNPCKHBW zmm1 {k1}{z}, zmm2, zmm3/m512                                       zmm3/m512 into zmm1 register.

EVEX.NDS.512.66.0F.WIG 69/r                         FVM V/V           AVX512BW Interleave high-order words from zmm2 and
VPUNPCKHWD zmm1 {k1}{z}, zmm2, zmm3/m512                                       zmm3/m512 into zmm1 register.

EVEX.NDS.512.66.0F.W0 6A /r                         FV    V/V         AVX512F      Interleave high-order doublewords from
VPUNPCKHDQ zmm1 {k1}{z}, zmm2,                                                     zmm2 and zmm3/m512/m32bcst into zmm1
zmm3/m512/m32bcst                                                                  register using k1 write mask.
EVEX.NDS.512.66.0F.W1 6D /r                         FV    V/V         AVX512F      Interleave high-order quadword from zmm2
VPUNPCKHQDQ zmm1 {k1}{z}, zmm2,                                                    and zmm3/m512/m64bcst into zmm1 register
zmm3/m512/m64bcst                                                                  using k1 write mask.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                     Operand 3                    Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                      NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA
    FV            ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA


Description
Unpacks and interleaves the high-order data elements (bytes, words, doublewords, or quadwords) of the destina-
tion operand (first operand) and source operand (second operand) into the destination operand. Figure 4-20 shows
the unpack operation for bytes in 64-bit operands. The low-order data elements are ignored.





                  SRC Y7 Y6    Y5 Y4    Y3 Y2   Y1 Y0              X7 X6   X5 X4   X3 X2     X1 X0 DEST




                     DEST Y7 X7 Y6      X6 Y5   X5 Y4        X4


                     Figure 4-20. PUNPCKHBW Instruction Operation Using 64-bit Operands




                      255                          31    0        255                            31 0

                  SRC Y7 Y6     Y5 Y4   Y3 Y2   Y1 Y0              X7 X6   X5 X4   X3 X2     X1 X0




                                                   255                                       0

                                                DEST Y7 X7 Y6           X6 Y3   X3 Y2   X2


                            Figure 4-21. 256-bit VPUNPCKHDQ Instruction Operation

When the source data comes from a 64-bit memory operand, the full 64-bit operand is accessed from memory, but
the instruction uses only the high-order 32 bits. When the source data comes from a 128-bit memory operand, an
implementation may fetch only the appropriate 64 bits; however, alignment to a 16-byte boundary and normal
segment checking will still be enforced.
The (V)PUNPCKHBW instruction interleaves the high-order bytes of the source and destination operands, the
(V)PUNPCKHWD instruction interleaves the high-order words of the source and destination operands, the
(V)PUNPCKHDQ instruction interleaves the high-order doubleword (or doublewords) of the source and destination
operands, and the (V)PUNPCKHQDQ instruction interleaves the high-order quadwords of the source and destina-
tion operands.
These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and
quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand
contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data
elements from the original value in the destination operand. For example, with the (V)PUNPCKHBW instruction the
high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKHWD
instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 64-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers.




EVEX encoded VPUNPCKHDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source
operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with
writemask k1.
EVEX encoded VPUNPCKHWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination
is conditionally updated with writemask k1.

Operation
PUNPCKHBW instruction with 64-bit operands:
  DEST[7:0] <- DEST[39:32];
  DEST[15:8] <- SRC[39:32];
  DEST[23:16] <- DEST[47:40];
  DEST[31:24] <- SRC[47:40];
  DEST[39:32] <- DEST[55:48];
  DEST[47:40] <- SRC[55:48];
  DEST[55:48] <- DEST[63:56];
  DEST[63:56] <- SRC[63:56];

PUNPCKHW instruction with 64-bit operands:
  DEST[15:0] <- DEST[47:32];
  DEST[31:16] <- SRC[47:32];
  DEST[47:32] <- DEST[63:48];
  DEST[63:48] <- SRC[63:48];

PUNPCKHDQ instruction with 64-bit operands:
  DEST[31:0] <- DEST[63:32];
  DEST[63:32] <- SRC[63:32];

INTERLEAVE_HIGH_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_HIGH_BYTES_256b (SRC1, SRC2)
DEST[7:0] <- SRC1[71:64]
DEST[15:8] <- SRC2[71:64]
DEST[23:16] <- SRC1[79:72]
DEST[31:24] <- SRC2[79:72]
DEST[39:32] <- SRC1[87:80]
DEST[47:40] <- SRC2[87:80]
DEST[55:48] <- SRC1[95:88]
DEST[63:56] <- SRC2[95:88]
DEST[71:64] <- SRC1[103:96]
DEST[79:72] <- SRC2[103:96]
DEST[87:80] <- SRC1[111:104]
DEST[95:88] <- SRC2[111:104]
DEST[103:96] <- SRC1[119:112]
DEST[111:104] <- SRC2[119:112]
DEST[119:112] <- SRC1[127:120]
DEST[127:120] <- SRC2[127:120]
DEST[135:128] <- SRC1[199:192]
DEST[143:136] <- SRC2[199:192]
DEST[151:144] <- SRC1[207:200]
DEST[159:152] <- SRC2[207:200]



DEST[167:160] <- SRC1[215:208]
DEST[175:168] <- SRC2[215:208]
DEST[183:176] <- SRC1[223:216]
DEST[191:184] <- SRC2[223:216]
DEST[199:192] <- SRC1[231:224]
DEST[207:200] <- SRC2[231:224]
DEST[215:208] <- SRC1[239:232]
DEST[223:216] <- SRC2[239:232]
DEST[231:224] <- SRC1[247:240]
DEST[239:232] <- SRC2[247:240]
DEST[247:240] <- SRC1[255:248]
DEST[255:248] <- SRC2[255:248]

INTERLEAVE_HIGH_BYTES (SRC1, SRC2)
DEST[7:0] <- SRC1[71:64]
DEST[15:8] <- SRC2[71:64]
DEST[23:16] <- SRC1[79:72]
DEST[31:24] <- SRC2[79:72]
DEST[39:32] <- SRC1[87:80]
DEST[47:40] <- SRC2[87:80]
DEST[55:48] <- SRC1[95:88]
DEST[63:56] <- SRC2[95:88]
DEST[71:64] <- SRC1[103:96]
DEST[79:72] <- SRC2[103:96]
DEST[87:80] <- SRC1[111:104]
DEST[95:88] <- SRC2[111:104]
DEST[103:96] <- SRC1[119:112]
DEST[111:104] <- SRC2[119:112]
DEST[119:112] <- SRC1[127:120]
DEST[127:120] <- SRC2[127:120]

INTERLEAVE_HIGH_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
DEST[15:0] <- SRC1[79:64]
DEST[31:16] <- SRC2[79:64]
DEST[47:32] <- SRC1[95:80]
DEST[63:48] <- SRC2[95:80]
DEST[79:64] <- SRC1[111:96]
DEST[95:80] <- SRC2[111:96]
DEST[111:96] <- SRC1[127:112]
DEST[127:112] <- SRC2[127:112]
DEST[143:128] <- SRC1[207:192]
DEST[159:144] <- SRC2[207:192]
DEST[175:160] <- SRC1[223:208]
DEST[191:176] <- SRC2[223:208]
DEST[207:192] <- SRC1[239:224]
DEST[223:208] <- SRC2[239:224]
DEST[239:224] <- SRC1[255:240]
DEST[255:240] <- SRC2[255:240]

INTERLEAVE_HIGH_WORDS (SRC1, SRC2)



DEST[15:0] <- SRC1[79:64]
DEST[31:16] <- SRC2[79:64]
DEST[47:32] <- SRC1[95:80]
DEST[63:48] <- SRC2[95:80]
DEST[79:64] <- SRC1[111:96]
DEST[95:80] <- SRC2[111:96]
DEST[111:96] <- SRC1[127:112]
DEST[127:112] <- SRC2[127:112]

INTERLEAVE_HIGH_DWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]
DEST[159:128] <- SRC1[223:192]
DEST[191:160] <- SRC2[223:192]
DEST[223:192] <- SRC1[255:224]
DEST[255:224] <- SRC2[255:224]

INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[31:0] <- SRC1[95:64]
DEST[63:32] <- SRC2[95:64]
DEST[95:64] <- SRC1[127:96]
DEST[127:96] <- SRC2[127:96]

INTERLEAVE_HIGH_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]
DEST[191:128] <- SRC1[255:192]
DEST[255:192] <- SRC2[255:192]

INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[63:0] <- SRC1[127:64]
DEST[127:64] <- SRC2[127:64]

PUNPCKHBW (128-bit Legacy SSE Version)
DEST[127:0] <-INTERLEAVE_HIGH_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)
VPUNPCKHBW (VEX.128 encoded version)
DEST[127:0] <-INTERLEAVE_HIGH_BYTES(SRC1, SRC2)
DEST[511:127] <-0

VPUNPCKHBW (VEX.256 encoded version)
DEST[255:0] <-INTERLEAVE_HIGH_BYTES_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0




VPUNPCKHBW (EVEX encoded versions)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- TMP_DEST[i+7:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

PUNPCKHWD (128-bit Legacy SSE Version)
DEST[127:0] <-INTERLEAVE_HIGH_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)

VPUNPCKHWD (VEX.128 encoded version)
DEST[127:0] <-INTERLEAVE_HIGH_WORDS(SRC1, SRC2)
DEST[511:127] <-0

VPUNPCKHWD (VEX.256 encoded version)
DEST[255:0] <-INTERLEAVE_HIGH_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKHWD (EVEX encoded versions)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*
        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]



        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+15:i] remains unchanged*
                 ELSE *zeroing-masking*              ; zeroing-masking
                     DEST[i+15:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

PUNPCKHDQ (128-bit Legacy SSE Version)
DEST[127:0] <-INTERLEAVE_HIGH_DWORDS(DEST, SRC)
DEST[255:127] (Unmodified)

VPUNPCKHDQ (VEX.128 encoded version)
DEST[127:0] <-INTERLEAVE_HIGH_DWORDS(SRC1, SRC2)
DEST[511:127] <-0

VPUNPCKHDQ (VEX.256 encoded version)
DEST[255:0] <-INTERLEAVE_HIGH_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKHDQ (EVEX.512 encoded version)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0



PUNPCKHQDQ (128-bit Legacy SSE Version)
DEST[127:0] <-INTERLEAVE_HIGH_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

VPUNPCKHQDQ (VEX.128 encoded version)
DEST[127:0] <-INTERLEAVE_HIGH_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPUNPCKHQDQ (VEX.256 encoded version)
DEST[255:0] <-INTERLEAVE_HIGH_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKHQDQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_HIGH_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPUNPCKHBW __m512i _mm512_unpackhi_epi8(__m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_mask_unpackhi_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m512i _mm512_maskz_unpackhi_epi8( __mmask64 k, __m512i a, __m512i b);
VPUNPCKHBW __m256i _mm256_mask_unpackhi_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);
VPUNPCKHBW __m256i _mm256_maskz_unpackhi_epi8( __mmask32 k, __m256i a, __m256i b);
VPUNPCKHBW __m128i _mm_mask_unpackhi_epi8(v s, __mmask16 k, __m128i a, __m128i b);
VPUNPCKHBW __m128i _mm_maskz_unpackhi_epi8( __mmask16 k, __m128i a, __m128i b);



VPUNPCKHWD __m512i _mm512_unpackhi_epi16(__m512i a, __m512i b);
VPUNPCKHWD __m512i _mm512_mask_unpackhi_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPUNPCKHWD __m512i _mm512_maskz_unpackhi_epi16( __mmask32 k, __m512i a, __m512i b);
VPUNPCKHWD __m256i _mm256_mask_unpackhi_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPUNPCKHWD __m256i _mm256_maskz_unpackhi_epi16( __mmask16 k, __m256i a, __m256i b);
VPUNPCKHWD __m128i _mm_mask_unpackhi_epi16(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKHWD __m128i _mm_maskz_unpackhi_epi16( __mmask8 k, __m128i a, __m128i b);
VPUNPCKHDQ __m512i _mm512_unpackhi_epi32(__m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_mask_unpackhi_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKHDQ __m512i _mm512_maskz_unpackhi_epi32( __mmask16 k, __m512i a, __m512i b);
VPUNPCKHDQ __m256i _mm256_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m256i _mm256_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_mask_unpackhi_epi32(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHDQ __m128i _mm_maskz_unpackhi_epi32( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_unpackhi_epi64(__m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m512i _mm512_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m256i _mm256_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m256i _mm256_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m128i _mm_mask_unpackhi_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKHQDQ __m128i _mm_maskz_unpackhi_epi64( __mmask8 k, __m512i a, __m512i b);
PUNPCKHBW:__m64 _mm_unpackhi_pi8(__m64 m1, __m64 m2)
(V)PUNPCKHBW:__m128i _mm_unpackhi_epi8(__m128i m1, __m128i m2)
VPUNPCKHBW:__m256i _mm256_unpackhi_epi8(__m256i m1, __m256i m2)
PUNPCKHWD:__m64 _mm_unpackhi_pi16(__m64 m1,__m64 m2)
(V)PUNPCKHWD:__m128i _mm_unpackhi_epi16(__m128i m1,__m128i m2)
VPUNPCKHWD:__m256i _mm256_unpackhi_epi16(__m256i m1,__m256i m2)
PUNPCKHDQ:__m64 _mm_unpackhi_pi32(__m64 m1, __m64 m2)
(V)PUNPCKHDQ:__m128i _mm_unpackhi_epi32(__m128i m1, __m128i m2)
VPUNPCKHDQ:__m256i _mm256_unpackhi_epi32(__m256i m1, __m256i m2)
(V)PUNPCKHQDQ:__m128i _mm_unpackhi_epi64 ( __m128i a, __m128i b)
VPUNPCKHQDQ:__m256i _mm256_unpackhi_epi64 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPUNPCKHQDQ/QDQ, see Exceptions Type E4NF.
EVEX-encoded VPUNPCKHBW/WD, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PUNPCKLBW
description:
PUNPCKLBW/PUNPCKLWD/PUNPCKLDQ/PUNPCKLQDQ-Unpack Low Data
Opcode/                                        Op/   64/32 bit   CPUID      Description
Instruction                                    En    Mode        Feature
                                                     Support     Flag
0F 60 /r1                                      RM    V/V         MMX        Interleave low-order bytes from mm and
PUNPCKLBW mm, mm/m32                                                        mm/m32 into mm.

66 0F 60 /r                                    RM    V/V         SSE2       Interleave low-order bytes from xmm1 and
PUNPCKLBW xmm1, xmm2/m128                                                   xmm2/m128 into xmm1.

0F 61 /r1                                      RM    V/V         MMX        Interleave low-order words from mm and
PUNPCKLWD mm, mm/m32                                                        mm/m32 into mm.

66 0F 61 /r                                    RM    V/V         SSE2       Interleave low-order words from xmm1 and
PUNPCKLWD xmm1, xmm2/m128                                                   xmm2/m128 into xmm1.

0F 62 /r1                                      RM    V/V         MMX        Interleave low-order doublewords from mm
PUNPCKLDQ mm, mm/m32                                                        and mm/m32 into mm.

66 0F 62 /r                                    RM    V/V         SSE2       Interleave low-order doublewords from xmm1
PUNPCKLDQ xmm1, xmm2/m128                                                   and xmm2/m128 into xmm1.

66 0F 6C /r                                    RM    V/V         SSE2       Interleave low-order quadword from xmm1
PUNPCKLQDQ xmm1, xmm2/m128                                                  and xmm2/m128 into xmm1 register.

VEX.NDS.128.66.0F.WIG 60/r                     RVM V/V           AVX        Interleave low-order bytes from xmm2 and
VPUNPCKLBW xmm1,xmm2, xmm3/m128                                             xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 61/r                     RVM V/V           AVX        Interleave low-order words from xmm2 and
VPUNPCKLWD xmm1,xmm2, xmm3/m128                                             xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 62/r                     RVM V/V           AVX        Interleave low-order doublewords from xmm2
VPUNPCKLDQ xmm1, xmm2, xmm3/m128                                            and xmm3/m128 into xmm1.

VEX.NDS.128.66.0F.WIG 6C/r                     RVM V/V           AVX        Interleave low-order quadword from xmm2
VPUNPCKLQDQ xmm1, xmm2, xmm3/m128                                           and xmm3/m128 into xmm1 register.
VEX.NDS.256.66.0F.WIG 60 /r                    RVM V/V           AVX2       Interleave low-order bytes from ymm2 and
VPUNPCKLBW ymm1, ymm2, ymm3/m256                                            ymm3/m256 into ymm1 register.

VEX.NDS.256.66.0F.WIG 61 /r                    RVM V/V           AVX2       Interleave low-order words from ymm2 and
VPUNPCKLWD ymm1, ymm2, ymm3/m256                                            ymm3/m256 into ymm1 register.

VEX.NDS.256.66.0F.WIG 62 /r                    RVM V/V           AVX2       Interleave low-order doublewords from ymm2
VPUNPCKLDQ ymm1, ymm2, ymm3/m256                                            and ymm3/m256 into ymm1 register.

VEX.NDS.256.66.0F.WIG 6C /r                    RVM V/V           AVX2       Interleave low-order quadword from ymm2
VPUNPCKLQDQ ymm1, ymm2, ymm3/m256                                           and ymm3/m256 into ymm1 register.

EVEX.NDS.128.66.0F.WIG 60 /r                   FVM V/V           AVX512VL Interleave low-order bytes from xmm2 and
VPUNPCKLBW xmm1 {k1}{z}, xmm2, xmm3/m128                         AVX512BW xmm3/m128 into xmm1 register subject to
                                                                          write mask k1.
EVEX.NDS.128.66.0F.WIG 61 /r                   FVM V/V           AVX512VL Interleave low-order words from xmm2 and
VPUNPCKLWD xmm1 {k1}{z}, xmm2, xmm3/m128                         AVX512BW xmm3/m128 into xmm1 register subject to
                                                                          write mask k1.
EVEX.NDS.128.66.0F.W0 62 /r                    FV    V/V         AVX512VL Interleave low-order doublewords from xmm2
VPUNPCKLDQ xmm1 {k1}{z}, xmm2,                                   AVX512F  and xmm3/m128/m32bcst into xmm1
xmm3/m128/m32bcst                                                         register subject to write mask k1.
EVEX.NDS.128.66.0F.W1 6C /r                    FV    V/V         AVX512VL Interleave low-order quadword from zmm2
VPUNPCKLQDQ xmm1 {k1}{z}, xmm2,                                  AVX512F  and zmm3/m512/m64bcst into zmm1
xmm3/m128/m64bcst                                                         register subject to write mask k1.





EVEX.NDS.256.66.0F.WIG 60 /r                        FVM V/V            AVX512VL Interleave low-order bytes from ymm2 and
VPUNPCKLBW ymm1 {k1}{z}, ymm2, ymm3/m256                               AVX512BW ymm3/m256 into ymm1 register subject to
                                                                                write mask k1.
EVEX.NDS.256.66.0F.WIG 61 /r                        FVM V/V            AVX512VL Interleave low-order words from ymm2 and
VPUNPCKLWD ymm1 {k1}{z}, ymm2, ymm3/m256                               AVX512BW ymm3/m256 into ymm1 register subject to
                                                                                write mask k1.
EVEX.NDS.256.66.0F.W0 62 /r                         FV    V/V          AVX512VL Interleave low-order doublewords from ymm2
VPUNPCKLDQ ymm1 {k1}{z}, ymm2,                                         AVX512F  and ymm3/m256/m32bcst into ymm1
ymm3/m256/m32bcst                                                               register subject to write mask k1.
EVEX.NDS.256.66.0F.W1 6C /r                         FV    V/V          AVX512VL Interleave low-order quadword from ymm2
VPUNPCKLQDQ ymm1 {k1}{z}, ymm2,                                        AVX512F  and ymm3/m256/m64bcst into ymm1
ymm3/m256/m64bcst                                                               register subject to write mask k1.
EVEX.NDS.512.66.0F.WIG 60/r                         FVM V/V            AVX512BW Interleave low-order bytes from zmm2 and
VPUNPCKLBW zmm1 {k1}{z}, zmm2, zmm3/m512                                        zmm3/m512 into zmm1 register subject to
                                                                                write mask k1.
EVEX.NDS.512.66.0F.WIG 61/r                         FVM V/V            AVX512BW Interleave low-order words from zmm2 and
VPUNPCKLWD zmm1 {k1}{z}, zmm2, zmm3/m512                                        zmm3/m512 into zmm1 register subject to
                                                                                write mask k1.
EVEX.NDS.512.66.0F.W0 62 /r                         FV    V/V          AVX512F      Interleave low-order doublewords from zmm2
VPUNPCKLDQ zmm1 {k1}{z}, zmm2,                                                      and zmm3/m512/m32bcst into zmm1
zmm3/m512/m32bcst                                                                   register subject to write mask k1.
EVEX.NDS.512.66.0F.W1 6C /r                         FV    V/V          AVX512F      Interleave low-order quadword from zmm2
VPUNPCKLQDQ zmm1 {k1}{z}, zmm2,                                                     and zmm3/m512/m64bcst into zmm1
zmm3/m512/m64bcst                                                                   register subject to write mask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                    Operand 3                     Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                      NA                            NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                 ModRM:r/m (r)                      NA
   FVM            ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA
    FV            ModRM:reg (w)                 EVEX.vvvv (r)                ModRM:r/m (r)                      NA


Description
Unpacks and interleaves the low-order data elements (bytes, words, doublewords, and quadwords) of the destina-
tion operand (first operand) and source operand (second operand) into the destination operand. (Figure 4-22
shows the unpack operation for bytes in 64-bit operands.). The high-order data elements are ignored.





                  SRC Y7 Y6     Y5 Y4   Y3 Y2   Y1 Y0         X7 X6   X5 X4   X3 X2     X1 X0 DEST




                                                DEST Y3 X3 Y2      X2 Y1   X1 Y0   X0


                     Figure 4-22. PUNPCKLBW Instruction Operation Using 64-bit Operands




                      255                          31    0   255                            31 0

                  SRC Y7 Y6     Y5 Y4   Y3 Y2   Y1 Y0         X7 X6   X5 X4   X3 X2     X1 X0




                                                   255                                  0

                                                DEST Y5 X5 Y4      X4 Y1   X1 Y0   X0


                            Figure 4-23. 256-bit VPUNPCKLDQ Instruction Operation



When the source data comes from a 128-bit memory operand, an implementation may fetch only the appropriate
64 bits; however, alignment to a 16-byte boundary and normal segment checking will still be enforced.
The (V)PUNPCKLBW instruction interleaves the low-order bytes of the source and destination operands, the
(V)PUNPCKLWD instruction interleaves the low-order words of the source and destination operands, the
(V)PUNPCKLDQ instruction interleaves the low-order doubleword (or doublewords) of the source and destination
operands, and the (V)PUNPCKLQDQ instruction interleaves the low-order quadwords of the source and destination
operands.
These instructions can be used to convert bytes to words, words to doublewords, doublewords to quadwords, and
quadwords to double quadwords, respectively, by placing all 0s in the source operand. Here, if the source operand
contains all 0s, the result (stored in the destination operand) contains zero extensions of the high-order data
elements from the original value in the destination operand. For example, with the (V)PUNPCKLBW instruction the
high-order bytes are zero extended (that is, unpacked into unsigned word integers), and with the (V)PUNPCKLWD
instruction, the high-order words are zero extended (unpacked into unsigned doubleword integers).
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE versions 64-bit operand: The source operand can be an MMX technology register or a 32-bit memory
location. The destination operand is an MMX technology register.
128-bit Legacy SSE versions: The second source operand is an XMM register or a 128-bit memory location. The
first source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM
destination register remain unchanged.
VEX.128 encoded versions: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The second source operand is an YMM register or an 256-bit memory location. The first
source operand and destination operands are YMM registers. Bits (MAX_VL-1:256) of the corresponding ZMM
register are zeroed.





EVEX encoded VPUNPCKLDQ/QDQ: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location or a 512/256/128-bit vector broadcasted from a 32/64-bit memory location. The first source
operand and destination operands are ZMM/YMM/XMM registers. The destination is conditionally updated with
writemask k1.
EVEX encoded VPUNPCKLWD/BW: The second source operand is a ZMM/YMM/XMM register, a 512/256/128-bit
memory location. The first source operand and destination operands are ZMM/YMM/XMM registers. The destination
is conditionally updated with writemask k1.

Operation
PUNPCKLBW instruction with 64-bit operands:
  DEST[63:56] <- SRC[31:24];
  DEST[55:48] <- DEST[31:24];
  DEST[47:40] <- SRC[23:16];
  DEST[39:32] <- DEST[23:16];
  DEST[31:24] <- SRC[15:8];
  DEST[23:16] <- DEST[15:8];
  DEST[15:8] <- SRC[7:0];
  DEST[7:0] <- DEST[7:0];

PUNPCKLWD instruction with 64-bit operands:
  DEST[63:48] <- SRC[31:16];
  DEST[47:32] <- DEST[31:16];
  DEST[31:16] <- SRC[15:0];
  DEST[15:0] <- DEST[15:0];

PUNPCKLDQ instruction with 64-bit operands:
   DEST[63:32] <- SRC[31:0];
   DEST[31:0] <- DEST[31:0];
INTERLEAVE_BYTES_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_BYTES_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] <- INTERLEAVE_BYTES_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_BYTES_256b (SRC1, SRC2)
DEST[7:0] <- SRC1[7:0]
DEST[15:8] <- SRC2[7:0]
DEST[23:16] <- SRC1[15:8]
DEST[31:24] <- SRC2[15:8]
DEST[39:32] <- SRC1[23:16]
DEST[47:40] <- SRC2[23:16]
DEST[55:48] <- SRC1[31:24]
DEST[63:56] <- SRC2[31:24]
DEST[71:64] <- SRC1[39:32]
DEST[79:72] <- SRC2[39:32]
DEST[87:80] <- SRC1[47:40]
DEST[95:88] <- SRC2[47:40]
DEST[103:96] <- SRC1[55:48]
DEST[111:104] <- SRC2[55:48]
DEST[119:112] <- SRC1[63:56]
DEST[127:120] <- SRC2[63:56]
DEST[135:128] <- SRC1[135:128]
DEST[143:136] <- SRC2[135:128]
DEST[151:144] <- SRC1[143:136]
DEST[159:152] <- SRC2[143:136]
DEST[167:160] <- SRC1[151:144]



DEST[175:168] <- SRC2[151:144]
DEST[183:176] <- SRC1[159:152]
DEST[191:184] <- SRC2[159:152]
DEST[199:192] <- SRC1[167:160]
DEST[207:200] <- SRC2[167:160]
DEST[215:208] <- SRC1[175:168]
DEST[223:216] <- SRC2[175:168]
DEST[231:224] <- SRC1[183:176]
DEST[239:232] <- SRC2[183:176]
DEST[247:240] <- SRC1[191:184]
DEST[255:248] <- SRC2[191:184]

INTERLEAVE_BYTES (SRC1, SRC2)
DEST[7:0] <- SRC1[7:0]
DEST[15:8] <- SRC2[7:0]
DEST[23:16] <- SRC2[15:8]
DEST[31:24] <- SRC2[15:8]
DEST[39:32] <- SRC1[23:16]
DEST[47:40] <- SRC2[23:16]
DEST[55:48] <- SRC1[31:24]
DEST[63:56] <- SRC2[31:24]
DEST[71:64] <- SRC1[39:32]
DEST[79:72] <- SRC2[39:32]
DEST[87:80] <- SRC1[47:40]
DEST[95:88] <- SRC2[47:40]
DEST[103:96] <- SRC1[55:48]
DEST[111:104] <- SRC2[55:48]
DEST[119:112] <- SRC1[63:56]
DEST[127:120] <- SRC2[63:56]

INTERLEAVE_WORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_WORDS_256b(SRC1[255:0], SRC[255:0])
TMP_DEST[511:256] <- INTERLEAVE_WORDS_256b(SRC1[511:256], SRC[511:256])

INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[15:0] <- SRC1[15:0]
DEST[31:16] <- SRC2[15:0]
DEST[47:32] <- SRC1[31:16]
DEST[63:48] <- SRC2[31:16]
DEST[79:64] <- SRC1[47:32]
DEST[95:80] <- SRC2[47:32]
DEST[111:96] <- SRC1[63:48]
DEST[127:112] <- SRC2[63:48]
DEST[143:128] <- SRC1[143:128]
DEST[159:144] <- SRC2[143:128]
DEST[175:160] <- SRC1[159:144]
DEST[191:176] <- SRC2[159:144]
DEST[207:192] <- SRC1[175:160]
DEST[223:208] <- SRC2[175:160]
DEST[239:224] <- SRC1[191:176]
DEST[255:240] <- SRC2[191:176]

INTERLEAVE_WORDS (SRC1, SRC2)
DEST[15:0] <- SRC1[15:0]



DEST[31:16] <- SRC2[15:0]
DEST[47:32] <- SRC1[31:16]
DEST[63:48] <- SRC2[31:16]
DEST[79:64] <- SRC1[47:32]
DEST[95:80] <- SRC2[47:32]
DEST[111:96] <- SRC1[63:48]
DEST[127:112] <- SRC2[63:48]

INTERLEAVE_DWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_DWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] <- INTERLEAVE_DWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
DEST[159:128] <- SRC1[159:128]
DEST[191:160] <- SRC2[159:128]
DEST[223:192] <- SRC1[191:160]
DEST[255:224] <- SRC2[191:160]

INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[31:0] <- SRC1[31:0]
DEST[63:32] <- SRC2[31:0]
DEST[95:64] <- SRC1[63:32]
DEST[127:96] <- SRC2[63:32]
INTERLEAVE_QWORDS_512b (SRC1, SRC2)
TMP_DEST[255:0] <- INTERLEAVE_QWORDS_256b(SRC1[255:0], SRC2[255:0])
TMP_DEST[511:256] <- INTERLEAVE_QWORDS_256b(SRC1[511:256], SRC2[511:256])

INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]
DEST[191:128] <- SRC1[191:128]
DEST[255:192] <- SRC2[191:128]

INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[63:0] <- SRC1[63:0]
DEST[127:64] <- SRC2[63:0]

PUNPCKLBW
DEST[127:0] <-INTERLEAVE_BYTES(DEST, SRC)
DEST[255:127] (Unmodified)

VPUNPCKLBW (VEX.128 encoded instruction)
DEST[127:0] <-INTERLEAVE_BYTES(SRC1, SRC2)
DEST[511:127] <-0

VPUNPCKLBW (VEX.256 encoded instruction)
DEST[255:0] <-INTERLEAVE_BYTES_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0





VPUNPCKLBW (EVEX.512 encoded instruction)
(KL, VL) = (16, 128), (32, 256), (64, 512)
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_BYTES_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i<-j*8
   IF k1[j] OR *no writemask*
        THEN DEST[i+7:i] <- TMP_DEST[i+7:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+7:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+7:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0
DEST[511:0] <- INTERLEAVE_BYTES_512b(SRC1, SRC2)

PUNPCKLWD
DEST[127:0] <-INTERLEAVE_WORDS(DEST, SRC)
DEST[255:127] (Unmodified)

VPUNPCKLWD (VEX.128 encoded instruction)
DEST[127:0] <-INTERLEAVE_WORDS(SRC1, SRC2)
DEST[511:127] <-0

VPUNPCKLWD (VEX.256 encoded instruction)
DEST[255:0] <-INTERLEAVE_WORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKLWD (EVEX.512 encoded instruction)
(KL, VL) = (8, 128), (16, 256), (32, 512)
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS_256b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_WORDS_512b(SRC1[VL-1:0], SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 16
   IF k1[j] OR *no writemask*



        THEN DEST[i+15:i] <- TMP_DEST[i+15:i]
        ELSE
            IF *merging-masking*                ; merging-masking
                 THEN *DEST[i+15:i] remains unchanged*
                 ELSE *zeroing-masking*              ; zeroing-masking
                     DEST[i+15:i] <- 0
            FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0
DEST[511:0] <- INTERLEAVE_WORDS_512b(SRC1, SRC2)

PUNPCKLDQ
DEST[127:0] <-INTERLEAVE_DWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

VPUNPCKLDQ (VEX.128 encoded instruction)
DEST[127:0] <-INTERLEAVE_DWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPUNPCKLDQ (VEX.256 encoded instruction)
DEST[255:0] <-INTERLEAVE_DWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKLDQ (EVEX encoded instructions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+31:i] <- SRC2[31:0]
         ELSE TMP_SRC2[i+31:i] <- SRC2[i+31:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_DWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 32
   IF k1[j] OR *no writemask*
        THEN DEST[i+31:i] <- TMP_DEST[i+31:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+31:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+31:i] <- 0
             FI
   FI;



ENDFOR
DEST511:0] <-INTERLEAVE_DWORDS_512b(SRC1, SRC2)
DEST[MAX_VL-1:VL] <- 0

PUNPCKLQDQ
DEST[127:0] <-INTERLEAVE_QWORDS(DEST, SRC)
DEST[MAX_VL-1:128] (Unmodified)

VPUNPCKLQDQ (VEX.128 encoded instruction)
DEST[127:0] <-INTERLEAVE_QWORDS(SRC1, SRC2)
DEST[MAX_VL-1:128] <-0

VPUNPCKLQDQ (VEX.256 encoded instruction)
DEST[255:0] <-INTERLEAVE_QWORDS_256b(SRC1, SRC2)
DEST[MAX_VL-1:256] <-0

VPUNPCKLQDQ (EVEX encoded instructions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1) AND (SRC2 *is memory*)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF VL = 128
    TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 256
    TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS_256b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;
IF VL = 512
    TMP_DEST[VL-1:0] <- INTERLEAVE_QWORDS_512b(SRC1[VL-1:0], TMP_SRC2[VL-1:0])
FI;

FOR j <- 0 TO KL-1
   i <- j * 64
   IF k1[j] OR *no writemask*
        THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
        ELSE
             IF *merging-masking*                ; merging-masking
                  THEN *DEST[i+63:i] remains unchanged*
                  ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
             FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalents
VPUNPCKLBW __m512i _mm512_unpacklo_epi8(__m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_mask_unpacklo_epi8(__m512i s, __mmask64 k, __m512i a, __m512i b);
VPUNPCKLBW __m512i _mm512_maskz_unpacklo_epi8( __mmask64 k, __m512i a, __m512i b);
VPUNPCKLBW __m256i _mm256_mask_unpacklo_epi8(__m256i s, __mmask32 k, __m256i a, __m256i b);



VPUNPCKLBW __m256i _mm256_maskz_unpacklo_epi8( __mmask32 k, __m256i a, __m256i b);
VPUNPCKLBW __m128i _mm_mask_unpacklo_epi8(v s, __mmask16 k, __m128i a, __m128i b);
VPUNPCKLBW __m128i _mm_maskz_unpacklo_epi8( __mmask16 k, __m128i a, __m128i b);
VPUNPCKLWD __m512i _mm512_unpacklo_epi16(__m512i a, __m512i b);
VPUNPCKLWD __m512i _mm512_mask_unpacklo_epi16(__m512i s, __mmask32 k, __m512i a, __m512i b);
VPUNPCKLWD __m512i _mm512_maskz_unpacklo_epi16( __mmask32 k, __m512i a, __m512i b);
VPUNPCKLWD __m256i _mm256_mask_unpacklo_epi16(__m256i s, __mmask16 k, __m256i a, __m256i b);
VPUNPCKLWD __m256i _mm256_maskz_unpacklo_epi16( __mmask16 k, __m256i a, __m256i b);
VPUNPCKLWD __m128i _mm_mask_unpacklo_epi16(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLWD __m128i _mm_maskz_unpacklo_epi16( __mmask8 k, __m128i a, __m128i b);
VPUNPCKLDQ __m512i _mm512_unpacklo_epi32(__m512i a, __m512i b);
VPUNPCKLDQ __m512i _mm512_mask_unpacklo_epi32(__m512i s, __mmask16 k, __m512i a, __m512i b);
VPUNPCKLDQ __m512i _mm512_maskz_unpacklo_epi32( __mmask16 k, __m512i a, __m512i b);
VPUNPCKLDQ __m256i _mm256_mask_unpacklo_epi32(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLDQ __m256i _mm256_maskz_unpacklo_epi32( __mmask8 k, __m256i a, __m256i b);
VPUNPCKLDQ __m128i _mm_mask_unpacklo_epi32(v s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLDQ __m128i _mm_maskz_unpacklo_epi32( __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m512i _mm512_unpacklo_epi64(__m512i a, __m512i b);
VPUNPCKLQDQ __m512i _mm512_mask_unpacklo_epi64(__m512i s, __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m512i _mm512_maskz_unpacklo_epi64( __mmask8 k, __m512i a, __m512i b);
VPUNPCKLQDQ __m256i _mm256_mask_unpacklo_epi64(__m256i s, __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m256i _mm256_maskz_unpacklo_epi64( __mmask8 k, __m256i a, __m256i b);
VPUNPCKLQDQ __m128i _mm_mask_unpacklo_epi64(__m128i s, __mmask8 k, __m128i a, __m128i b);
VPUNPCKLQDQ __m128i _mm_maskz_unpacklo_epi64( __mmask8 k, __m128i a, __m128i b);
PUNPCKLBW:__m64 _mm_unpacklo_pi8 (__m64 m1, __m64 m2)
(V)PUNPCKLBW:__m128i _mm_unpacklo_epi8 (__m128i m1, __m128i m2)
VPUNPCKLBW:__m256i _mm256_unpacklo_epi8 (__m256i m1, __m256i m2)
PUNPCKLWD:__m64 _mm_unpacklo_pi16 (__m64 m1, __m64 m2)
(V)PUNPCKLWD:__m128i _mm_unpacklo_epi16 (__m128i m1, __m128i m2)
VPUNPCKLWD:__m256i _mm256_unpacklo_epi16 (__m256i m1, __m256i m2)
PUNPCKLDQ:__m64 _mm_unpacklo_pi32 (__m64 m1, __m64 m2)
(V)PUNPCKLDQ:__m128i _mm_unpacklo_epi32 (__m128i m1, __m128i m2)
VPUNPCKLDQ:__m256i _mm256_unpacklo_epi32 (__m256i m1, __m256i m2)
(V)PUNPCKLQDQ:__m128i _mm_unpacklo_epi64 (__m128i m1, __m128i m2)
VPUNPCKLQDQ:__m256i _mm256_unpacklo_epi64 (__m256i m1, __m256i m2)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded VPUNPCKLDQ/QDQ, see Exceptions Type E4NF.
EVEX-encoded VPUNPCKLBW/WD, see Exceptions Type E4NF.nb.






platform: x86_64
mnem: PUSH
description:
PUSH-Push Word, Doubleword or Quadword Onto the Stack
 Opcode*                  Instruction                    Op/   64-Bit    Compat/ Description
                                                         En    Mode      Leg Mode
 FF /6                    PUSH r/m16                     M     Valid     Valid        Push r/m16.
 FF /6                    PUSH r/m32                     M     N.E.      Valid        Push r/m32.
 FF /6                    PUSH r/m64                     M     Valid     N.E.         Push r/m64.
 50+rw                    PUSH r16                       O     Valid     Valid        Push r16.
 50+rd                    PUSH r32                       O     N.E.      Valid        Push r32.
 50+rd                    PUSH r64                       O     Valid     N.E.         Push r64.
 6A ib                    PUSH imm8                      I     Valid     Valid        Push imm8.
 68 iw                    PUSH imm16                     I     Valid     Valid        Push imm16.
 68 id                    PUSH imm32                     I     Valid     Valid        Push imm32.
 0E                       PUSH CS                        NP    Invalid   Valid        Push CS.
 16                       PUSH SS                        NP    Invalid   Valid        Push SS.
 1E                       PUSH DS                        NP    Invalid   Valid        Push DS.
 06                       PUSH ES                        NP    Invalid   Valid        Push ES.
 0F A0                    PUSH FS                        NP    Valid     Valid        Push FS.
 0F A8                    PUSH GS                        NP    Valid     Valid        Push GS.
 NOTES:
 * See IA-32 Architecture Compatibility section below.



                                                 Instruction Operand Encoding
    Op/En           Operand 1                     Operand 2                      Operand 3                    Operand 4
      M           ModRM:r/m (r)                          NA                         NA                           NA
      O           opcode + rd (r)                        NA                         NA                           NA
      I            imm8/16/32                            NA                         NA                           NA
      NP                NA                               NA                         NA                           NA


Description
Decrements the stack pointer and then stores the source operand on the top of the stack. Address and operand
sizes are determined and used as follows:
.     Address size. The D flag in the current code-segment descriptor determines the default address size; it may be
      overridden by an instruction prefix (67H).
      The address size is used only when referencing a source operand in memory.
.     Operand size. The D flag in the current code-segment descriptor determines the default operand size; it may
      be overridden by instruction prefixes (66H or REX.W).
      The operand size (16, 32, or 64 bits) determines the amount by which the stack pointer is decremented (2, 4
      or 8).
      If the source operand is an immediate of size less than the operand size, a sign-extended value is pushed on
      the stack. If the source operand is a segment register (16 bits) and the operand size is 64-bits, a zero-
      extended value is pushed on the stack; if the operand size is 32-bits, either a zero-extended value is pushed
      on the stack or the segment selector is written on the stack using a 16-bit move. For the last case, all recent
      Core and Atom processors perform a 16-bit move, leaving the upper portion of the stack location unmodified.
.     Stack-address size. Outside of 64-bit mode, the B flag in the current stack-segment descriptor determines the
      size of the stack pointer (16 or 32 bits); in 64-bit mode, the size of the stack pointer is always 64 bits.



    The stack-address size determines the width of the stack pointer when writing to the stack in memory and
    when decrementing the stack pointer. (As stated above, the amount by which the stack pointer is
    decremented is determined by the operand size.)
    If the operand size is less than the stack-address size, the PUSH instruction may result in a misaligned stack
    pointer (a stack pointer that is not aligned on a doubleword or quadword boundary).
The PUSH ESP instruction pushes the value of the ESP register as it existed before the instruction was executed. If
a PUSH instruction uses a memory operand in which the ESP register is used for computing the operand address,
the address of the operand is computed before the ESP register is decremented.
If the ESP or SP register is 1 when the PUSH instruction is executed in real-address mode, a stack-fault exception
(#SS) is generated (because the limit of the stack segment is violated). Its delivery encounters a second stack-
fault exception (for the same reason), causing generation of a double-fault exception (#DF). Delivery of the
double-fault exception encounters a third stack-fault exception, and the logical processor enters shutdown mode.
See the discussion of the double-fault exception in Chapter 6 of the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 3A.

IA-32 Architecture Compatibility
For IA-32 processors from the Intel 286 on, the PUSH ESP instruction pushes the value of the ESP register as it
existed before the instruction was executed. (This is also true for Intel 64 architecture, real-address and virtual-
8086 modes of IA-32 architecture.) For the Intel 8086 processor, the PUSH SP instruction pushes the new value
of the SP register (that is the value after it has been decremented by 2).

Operation
(* See Description section for possible sign-extension or zero-extension of source operand and for *)
(* a case in which the size of the memory store may be smaller than the instruction's operand size *)
IF StackAddrSize = 64
    THEN
         IF OperandSize = 64
              THEN
                   RSP <- RSP - 8;
                   Memory[SS:RSP] <- SRC;                 (* push quadword *)
         ELSE IF OperandSize = 32
              THEN
                   RSP <- RSP - 4;
                   Memory[SS:RSP] <- SRC;                 (* push dword *)
              ELSE (* OperandSize = 16 *)
                   RSP <- RSP - 2;
                   Memory[SS:RSP] <- SRC;                 (* push word *)
         FI;
ELSE IF StackAddrSize = 32
   THEN
        IF OperandSize = 64
             THEN
                 ESP <- ESP - 8;
                 Memory[SS:ESP] <- SRC;                 (* push quadword *)
        ELSE IF OperandSize = 32
             THEN
                 ESP <- ESP - 4;
                 Memory[SS:ESP] <- SRC;                 (* push dword *)
             ELSE (* OperandSize = 16 *)
                 ESP <- ESP - 2;
                 Memory[SS:ESP] <- SRC;                 (* push word *)
        FI;
   ELSE (* StackAddrSize = 16 *)



        IF OperandSize = 32
             THEN
                 SP <- SP - 4;
                 Memory[SS:SP] <- SRC;                   (* push dword *)
             ELSE (* OperandSize = 16 *)
                 SP <- SP - 2;
                 Memory[SS:SP] <- SRC;                   (* push word *)
        FI;
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                        selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
                        If the new value of the SP or ESP register is outside the stack segment limit.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                  If the memory address is in a non-canonical form.
#SS(0)                  If the stack address is in a non-canonical form.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.
                        If the PUSH is of CS, SS, DS, or ES.






platform: x86_64
mnem: PUSHA
description:
PUSHA/PUSHAD-Push All General-Purpose Registers
 Opcode                   Instruction                  Op/   64-Bit    Compat/ Description
                                                       En    Mode      Leg Mode
 60                       PUSHA                        NP    Invalid   Valid     Push AX, CX, DX, BX, original SP, BP, SI, and DI.
 60                       PUSHAD                       NP    Invalid   Valid     Push EAX, ECX, EDX, EBX, original ESP, EBP,
                                                                                 ESI, and EDI.



                                                Instruction Operand Encoding
      Op/En           Operand 1                      Operand 2                 Operand 3                      Operand 4
       NP                NA                             NA                        NA                              NA


Description
Pushes the contents of the general-purpose registers onto the stack. The registers are stored on the stack in the
following order: EAX, ECX, EDX, EBX, ESP (original value), EBP, ESI, and EDI (if the current operand-size attribute
is 32) and AX, CX, DX, BX, SP (original value), BP, SI, and DI (if the operand-size attribute is 16). These instruc-
tions perform the reverse operation of the POPA/POPAD instructions. The value pushed for the ESP or SP register
is its value before prior to pushing the first register (see the "Operation" section below).
The PUSHA (push all) and PUSHAD (push all double) mnemonics reference the same opcode. The PUSHA instruc-
tion is intended for use when the operand-size attribute is 16 and the PUSHAD instruction for when the operand-
size attribute is 32. Some assemblers may force the operand size to 16 when PUSHA is used and to 32 when
PUSHAD is used. Others may treat these mnemonics as synonyms (PUSHA/PUSHAD) and use the current setting
of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the
mnemonic used.
In the real-address mode, if the ESP or SP register is 1, 3, or 5 when PUSHA/PUSHAD executes: an #SS exception
is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates a
#DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.
This instruction executes as described in compatibility mode and legacy mode. It is not valid in 64-bit mode.

Operation
IF 64-bit Mode

      THEN #UD

FI;

IF OperandSize = 32 (* PUSHAD instruction *)
    THEN
        Temp <- (ESP);
        Push(EAX);
        Push(ECX);
        Push(EDX);
        Push(EBX);
        Push(Temp);
        Push(EBP);
        Push(ESI);
        Push(EDI);
    ELSE (* OperandSize = 16, PUSHA instruction *)
        Temp <- (SP);
        Push(AX);
        Push(CX);
        Push(DX);


        Push(BX);
        Push(Temp);
        Push(BP);
        Push(SI);
        Push(DI);
FI;

Flags Affected
None.

Protected Mode Exceptions
#SS(0)                  If the starting or ending stack address is outside the stack segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while the current privilege level is 3 and alignment
                        checking is enabled.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If the ESP or SP register contains 7, 9, 11, 13, or 15.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If the ESP or SP register contains 7, 9, 11, 13, or 15.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory reference is made while alignment checking is enabled.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#UD                     If in 64-bit mode.






platform: x86_64
mnem: PUSHF
description:
PUSHF/PUSHFD-Push EFLAGS Register onto the Stack
 Opcode*                   Instruction                  Op/     64-Bit      Compat/ Description
                                                        En      Mode        Leg Mode
 9C                        PUSHF                        NP      Valid       Valid         Push lower 16 bits of EFLAGS.
 9C                        PUSHFD                       NP      N.E.        Valid         Push EFLAGS.
 9C                        PUSHFQ                       NP      Valid       N.E.          Push RFLAGS.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                     Operand 2                       Operand 3                       Operand 4
      NP                  NA                            NA                               NA                               NA


Description
Decrements the stack pointer by 4 (if the current operand-size attribute is 32) and pushes the entire contents of
the EFLAGS register onto the stack, or decrements the stack pointer by 2 (if the operand-size attribute is 16) and
pushes the lower 16 bits of the EFLAGS register (that is, the FLAGS register) onto the stack. These instructions
reverse the operation of the POPF/POPFD instructions.
When copying the entire EFLAGS register to the stack, the VM and RF flags (bits 16 and 17) are not copied; instead,
the values for these flags are cleared in the EFLAGS image stored on the stack. See Chapter 3 of the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for more information about the EFLAGS register.
The PUSHF (push flags) and PUSHFD (push flags double) mnemonics reference the same opcode. The PUSHF
instruction is intended for use when the operand-size attribute is 16 and the PUSHFD instruction for when the
operand-size attribute is 32. Some assemblers may force the operand size to 16 when PUSHF is used and to 32
when PUSHFD is used. Others may treat these mnemonics as synonyms (PUSHF/PUSHFD) and use the current
setting of the operand-size attribute to determine the size of values to be pushed from the stack, regardless of the
mnemonic used.
In 64-bit mode, the instruction's default operation is to decrement the stack pointer (RSP) by 8 and pushes RFLAGS
on the stack. 16-bit operation is supported using the operand size override prefix 66H. 32-bit operand size cannot
be encoded in this mode. When copying RFLAGS to the stack, the VM and RF flags (bits 16 and 17) are not copied;
instead, values for these flags are cleared in the RFLAGS image stored on the stack.
When in virtual-8086 mode and the I/O privilege level (IOPL) is less than 3, the PUSHF/PUSHFD instruction causes
a general protection exception (#GP).
In the real-address mode, if the ESP or SP register is 1 when PUSHF/PUSHFD instruction executes: an #SS excep-
tion is generated but not delivered (the stack error reported prevents #SS delivery). Next, the processor generates
a #DF exception and enters a shutdown state as described in the #DF discussion in Chapter 6 of the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 3A.

Operation
IF (PE = 0) or (PE = 1 and ((VM = 0) or (VM = 1 and IOPL = 3)))
(* Real-Address Mode, Protected mode, or Virtual-8086 mode with IOPL equal to 3 *)
    THEN
         IF OperandSize = 32
              THEN
                   push (EFLAGS AND 00FCFFFFH);
                   (* VM and RF EFLAG bits are cleared in image stored on the stack *)
              ELSE
                   push (EFLAGS); (* Lower 16 bits only *)
         FI;

   ELSE IF 64-bit MODE (* In 64-bit Mode *)
       IF OperandSize = 64



                THEN
                    push (RFLAGS AND 00000000_00FCFFFFH);
                    (* VM and RF RFLAG bits are cleared in image stored on the stack; *)
                ELSE
                    push (EFLAGS); (* Lower 16 bits only *)
          FI;

      ELSE (* In Virtual-8086 Mode with IOPL less than 3 *)
          #GP(0); (* Trap to virtual-8086 monitor *)
FI;

Flags Affected
None.

Protected Mode Exceptions
#SS(0)                     If the new value of the ESP register is outside the stack segment boundary.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If an unaligned memory reference is made while the current privilege level is 3 and alignment
                           checking is enabled.
#UD                        If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                        If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                     If the I/O privilege level is less than 3.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If an unaligned memory reference is made while alignment checking is enabled.
#UD                        If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                     If the memory address is in a non-canonical form.
#SS(0)                     If the stack address is in a non-canonical form.
#PF(fault-code)            If a page fault occurs.
#AC(0)                     If an unaligned memory reference is made while the current privilege level is 3 and alignment
                           checking is enabled.
#UD                        If the LOCK prefix is used.






platform: x86_64
mnem: PXOR
description:
PXOR-Logical Exclusive OR
Opcode*/                                             Op/   64/32 bit   CPUID        Description
Instruction                                          En    Mode        Feature
                                                           Support     Flag
0F EF /r1                                            RM    V/V         MMX          Bitwise XOR of mm/m64 and mm.
PXOR mm, mm/m64
66 0F EF /r                                          RM    V/V         SSE2         Bitwise XOR of xmm2/m128 and xmm1.
PXOR xmm1, xmm2/m128
VEX.NDS.128.66.0F.WIG EF /r                          RVM V/V           AVX          Bitwise XOR of xmm3/m128 and xmm2.
VPXOR xmm1, xmm2, xmm3/m128
VEX.NDS.256.66.0F.WIG EF /r                          RVM V/V           AVX2         Bitwise XOR of ymm3/m256 and ymm2.
VPXOR ymm1, ymm2, ymm3/m256
EVEX.NDS.128.66.0F.W0 EF /r                  FV            V/V         AVX512VL Bitwise XOR of packed doubleword integers in
VPXORD xmm1 {k1}{z}, xmm2, xmm3/m128/m32bcst                           AVX512F xmm2 and xmm3/m128 using writemask k1.
EVEX.NDS.256.66.0F.W0 EF /r                  FV            V/V         AVX512VL Bitwise XOR of packed doubleword integers in
VPXORD ymm1 {k1}{z}, ymm2, ymm3/m256/m32bcst                           AVX512F ymm2 and ymm3/m256 using writemask k1.
EVEX.NDS.512.66.0F.W0 EF /r                  FV            V/V         AVX512F      Bitwise XOR of packed doubleword integers in
VPXORD zmm1 {k1}{z}, zmm2, zmm3/m512/m32bcst                                        zmm2 and zmm3/m512/m32bcst using
                                                                                    writemask k1.
EVEX.NDS.128.66.0F.W1 EF /r                          FV    V/V         AVX512VL Bitwise XOR of packed quadword integers in
VPXORQ xmm1 {k1}{z}, xmm2,                                             AVX512F xmm2 and xmm3/m128 using writemask k1.
xmm3/m128/m64bcst
EVEX.NDS.256.66.0F.W1 EF /r                  FV            V/V         AVX512VL Bitwise XOR of packed quadword integers in
VPXORQ ymm1 {k1}{z}, ymm2, ymm3/m256/m64bcst                           AVX512F ymm2 and ymm3/m256 using writemask k1.
EVEX.NDS.512.66.0F.W1 EF /r                  FV            V/V         AVX512F      Bitwise XOR of packed quadword integers in
VPXORQ zmm1 {k1}{z}, zmm2, zmm3/m512/m64bcst                                        zmm2 and zmm3/m512/m64bcst using
                                                                                    writemask k1.
NOTES:
1. See note in Section 2.4, "AVX and SSE Instruction Exception Specification" in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 2A and Section 22.25.3, "Exception Conditions of Legacy SIMD Instructions Operating on MMX Registers"
in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A.



                                               Instruction Operand Encoding
   Op/En            Operand 1                    Operand 2                     Operand 3                    Operand 4
    RM           ModRM:reg (r, w)              ModRM:r/m (r)                       NA                           NA
   RVM            ModRM:reg (w)                 VEX.vvvv (r)                  ModRM:r/m (r)                     NA
    FV            ModRM:reg (w)                 EVEX.vvvv (r)                 ModRM:r/m (r)                     NA


Description
Performs a bitwise logical exclusive-OR (XOR) operation on the source operand (second operand) and the destina-
tion operand (first operand) and stores the result in the destination operand. Each bit of the result is 1 if the corre-
sponding bits of the two operands are different; each bit is 0 if the corresponding bits of the operands are the same.
In 64-bit mode and not encoded with VEX/EVEX, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Legacy SSE instructions 64-bit operand: The source operand can be an MMX technology register or a 64-bit
memory location. The destination operand is an MMX technology register.





128-bit Legacy SSE version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the corresponding YMM desti-
nation register remain unchanged.
VEX.128 encoded version: The second source operand is an XMM register or a 128-bit memory location. The first
source operand and destination operands are XMM registers. Bits (VLMAX-1:128) of the destination YMM register
are zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand is a YMM register
or a 256-bit memory location. The destination operand is a YMM register. The upper bits (MAX_VL-1:256) of the
corresponding register destination are zeroed.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
32/64-bit memory location. The destination operand is a ZMM/YMM/XMM register conditionally updated with
writemask k1.

Operation
PXOR (64-bit operand)
DEST <- DEST XOR SRC
PXOR (128-bit Legacy SSE version)
DEST <- DEST XOR SRC
DEST[VLMAX-1:128] (Unmodified)

VPXOR (VEX.128 encoded version)
DEST <- SRC1 XOR SRC2
DEST[VLMAX-1:128] <- 0

VPXOR (VEX.256 encoded version)
DEST <- SRC1 XOR SRC2
DEST[VLMAX-1:256] <- 0

VPXORD (EVEX encoded versions)
(KL, VL) = (4, 128), (8, 256), (16, 512)
FOR j <- 0 TO KL-1
    i <- j * 32
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[31:0]
                    ELSE DEST[i+31:i] <- SRC1[i+31:i] BITWISE XOR SRC2[i+31:i]
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[31:0] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[31:0] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0





VPXORQ (EVEX encoded versions)
(KL, VL) = (2, 128), (4, 256), (8, 512)
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask* THEN
               IF (EVEX.b = 1) AND (SRC2 *is memory*)
                    THEN DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[63:0]
                    ELSE DEST[i+63:i] <- SRC1[i+63:i] BITWISE XOR SRC2[i+63:i]
               FI;
    ELSE
         IF *merging-masking*                  ; merging-masking
               THEN *DEST[63:0] remains unchanged*
               ELSE                            ; zeroing-masking
                    DEST[63:0] <- 0
         FI;
    FI;
ENDFOR;
DEST[MAX_VL-1:VL] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
VPXORD __m512i _mm512_xor_epi32(__m512i a, __m512i b)
VPXORD __m512i _mm512_mask_xor_epi32(__m512i s, __mmask16 m, __m512i a, __m512i b)
VPXORD __m512i _mm512_maskz_xor_epi32( __mmask16 m, __m512i a, __m512i b)
VPXORD __m256i _mm256_xor_epi32(__m256i a, __m256i b)
VPXORD __m256i _mm256_mask_xor_epi32(__m256i s, __mmask8 m, __m256i a, __m256i b)
VPXORD __m256i _mm256_maskz_xor_epi32( __mmask8 m, __m256i a, __m256i b)
VPXORD __m128i _mm_xor_epi32(__m128i a, __m128i b)
VPXORD __m128i _mm_mask_xor_epi32(__m128i s, __mmask8 m, __m128i a, __m128i b)
VPXORD __m128i _mm_maskz_xor_epi32( __mmask16 m, __m128i a, __m128i b)
VPXORQ __m512i _mm512_xor_epi64( __m512i a, __m512i b);
VPXORQ __m512i _mm512_mask_xor_epi64(__m512i s, __mmask8 m, __m512i a, __m512i b);
VPXORQ __m512i _mm512_maskz_xor_epi64(__mmask8 m, __m512i a, __m512i b);
VPXORQ __m256i _mm256_xor_epi64( __m256i a, __m256i b);
VPXORQ __m256i _mm256_mask_xor_epi64(__m256i s, __mmask8 m, __m256i a, __m256i b);
VPXORQ __m256i _mm256_maskz_xor_epi64(__mmask8 m, __m256i a, __m256i b);
VPXORQ __m128i _mm_xor_epi64( __m128i a, __m128i b);
VPXORQ __m128i _mm_mask_xor_epi64(__m128i s, __mmask8 m, __m128i a, __m128i b);
VPXORQ __m128i _mm_maskz_xor_epi64(__mmask8 m, __m128i a, __m128i b);
PXOR:__m64 _mm_xor_si64 (__m64 m1, __m64 m2)
(V)PXOR:__m128i _mm_xor_si128 ( __m128i a, __m128i b)
VPXOR:__m256i _mm256_xor_si256 ( __m256i a, __m256i b)

Flags Affected
None.

Numeric Exceptions
None.

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4.






platform: x86_64
mnem: RCL
description:
RCL/RCR/ROL/ROR-Rotate
 Opcode**                Instruction       Op/   64-Bit   Compat/ Description
                                           En    Mode     Leg Mode
 D0 /2                   RCL r/m8, 1       M1    Valid    Valid    Rotate 9 bits (CF, r/m8) left once.
 REX + D0 /2             RCL r/m8*, 1      M1    Valid    N.E.     Rotate 9 bits (CF, r/m8) left once.
 D2 /2                   RCL r/m8, CL      MC    Valid    Valid    Rotate 9 bits (CF, r/m8) left CL times.
 REX + D2 /2             RCL r/m8*, CL     MC    Valid    N.E.     Rotate 9 bits (CF, r/m8) left CL times.
 C0 /2 ib                RCL r/m8, imm8    MI    Valid    Valid    Rotate 9 bits (CF, r/m8) left imm8 times.
 REX + C0 /2 ib          RCL r/m8*, imm8   MI    Valid    N.E.     Rotate 9 bits (CF, r/m8) left imm8 times.
 D1 /2                   RCL r/m16, 1      M1    Valid    Valid    Rotate 17 bits (CF, r/m16) left once.
 D3 /2                   RCL r/m16, CL     MC    Valid    Valid    Rotate 17 bits (CF, r/m16) left CL times.
 C1 /2 ib                RCL r/m16, imm8   MI    Valid    Valid    Rotate 17 bits (CF, r/m16) left imm8 times.
 D1 /2                   RCL r/m32, 1      M1    Valid    Valid    Rotate 33 bits (CF, r/m32) left once.
 REX.W + D1 /2           RCL r/m64, 1      M1    Valid    N.E.     Rotate 65 bits (CF, r/m64) left once. Uses a 6
                                                                   bit count.
 D3 /2                   RCL r/m32, CL     MC    Valid    Valid    Rotate 33 bits (CF, r/m32) left CL times.
 REX.W + D3 /2           RCL r/m64, CL     MC    Valid    N.E.     Rotate 65 bits (CF, r/m64) left CL times. Uses a
                                                                   6 bit count.
 C1 /2 ib                RCL r/m32, imm8   MI    Valid    Valid    Rotate 33 bits (CF, r/m32) left imm8 times.
 REX.W + C1 /2 ib        RCL r/m64, imm8   MI    Valid    N.E.     Rotate 65 bits (CF, r/m64) left imm8 times.
                                                                   Uses a 6 bit count.
 D0 /3                   RCR r/m8, 1       M1    Valid    Valid    Rotate 9 bits (CF, r/m8) right once.
 REX + D0 /3             RCR r/m8*, 1      M1    Valid    N.E.     Rotate 9 bits (CF, r/m8) right once.
 D2 /3                   RCR r/m8, CL      MC    Valid    Valid    Rotate 9 bits (CF, r/m8) right CL times.
 REX + D2 /3             RCR r/m8*, CL     MC    Valid    N.E.     Rotate 9 bits (CF, r/m8) right CL times.
 C0 /3 ib                RCR r/m8, imm8    MI    Valid    Valid    Rotate 9 bits (CF, r/m8) right imm8 times.
 REX + C0 /3 ib          RCR r/m8*, imm8   MI    Valid    N.E.     Rotate 9 bits (CF, r/m8) right imm8 times.
 D1 /3                   RCR r/m16, 1      M1    Valid    Valid    Rotate 17 bits (CF, r/m16) right once.
 D3 /3                   RCR r/m16, CL     MC    Valid    Valid    Rotate 17 bits (CF, r/m16) right CL times.
 C1 /3 ib                RCR r/m16, imm8   MI    Valid    Valid    Rotate 17 bits (CF, r/m16) right imm8 times.
 D1 /3                   RCR r/m32, 1      M1    Valid    Valid    Rotate 33 bits (CF, r/m32) right once. Uses a 6
                                                                   bit count.
 REX.W + D1 /3           RCR r/m64, 1      M1    Valid    N.E.     Rotate 65 bits (CF, r/m64) right once. Uses a 6
                                                                   bit count.
 D3 /3                   RCR r/m32, CL     MC    Valid    Valid    Rotate 33 bits (CF, r/m32) right CL times.
 REX.W + D3 /3           RCR r/m64, CL     MC    Valid    N.E.     Rotate 65 bits (CF, r/m64) right CL times. Uses
                                                                   a 6 bit count.
 C1 /3 ib                RCR r/m32, imm8   MI    Valid    Valid    Rotate 33 bits (CF, r/m32) right imm8 times.
 REX.W + C1 /3 ib        RCR r/m64, imm8   MI    Valid    N.E.     Rotate 65 bits (CF, r/m64) right imm8 times.
                                                                   Uses a 6 bit count.
 D0 /0                   ROL r/m8, 1       M1    Valid    Valid    Rotate 8 bits r/m8 left once.
 REX + D0 /0             ROL r/m8*, 1      M1    Valid    N.E.     Rotate 8 bits r/m8 left once
 D2 /0                   ROL r/m8, CL      MC    Valid    Valid    Rotate 8 bits r/m8 left CL times.
 REX + D2 /0             ROL r/m8*, CL     MC    Valid    N.E.     Rotate 8 bits r/m8 left CL times.
 C0 /0 ib                ROL r/m8, imm8    MI    Valid    Valid    Rotate 8 bits r/m8 left imm8 times.


 Opcode**                 Instruction                  Op/    64-Bit       Compat/ Description
                                                       En     Mode         Leg Mode
 REX + C0 /0 ib           ROL r/m8*, imm8              MI     Valid        N.E.        Rotate 8 bits r/m8 left imm8 times.
 D1 /0                    ROL r/m16, 1                 M1     Valid        Valid       Rotate 16 bits r/m16 left once.
 D3 /0                    ROL r/m16, CL                MC     Valid        Valid       Rotate 16 bits r/m16 left CL times.
 C1 /0 ib                 ROL r/m16, imm8              MI     Valid        Valid       Rotate 16 bits r/m16 left imm8 times.
 D1 /0                    ROL r/m32, 1                 M1     Valid        Valid       Rotate 32 bits r/m32 left once.



 REX.W + D1 /0            ROL r/m64, 1                 M1     Valid        N.E.        Rotate 64 bits r/m64 left once. Uses a 6 bit
                                                                                       count.
 D3 /0                    ROL r/m32, CL                MC     Valid        Valid       Rotate 32 bits r/m32 left CL times.
 REX.W + D3 /0            ROL r/m64, CL                MC     Valid        N.E.        Rotate 64 bits r/m64 left CL times. Uses a 6
                                                                                       bit count.
 C1 /0 ib                 ROL r/m32, imm8              MI     Valid        Valid       Rotate 32 bits r/m32 left imm8 times.
 REX.W + C1 /0 ib         ROL r/m64, imm8              MI     Valid        N.E.        Rotate 64 bits r/m64 left imm8 times. Uses a
                                                                                       6 bit count.
 D0 /1                    ROR r/m8, 1                  M1     Valid        Valid       Rotate 8 bits r/m8 right once.
 REX + D0 /1              ROR r/m8*, 1                 M1     Valid        N.E.        Rotate 8 bits r/m8 right once.
 D2 /1                    ROR r/m8, CL                 MC     Valid        Valid       Rotate 8 bits r/m8 right CL times.
 REX + D2 /1              ROR r/m8*, CL                MC     Valid        N.E.        Rotate 8 bits r/m8 right CL times.
 C0 /1 ib                 ROR r/m8, imm8               MI     Valid        Valid       Rotate 8 bits r/m16 right imm8 times.
 REX + C0 /1 ib           ROR r/m8*, imm8              MI     Valid        N.E.        Rotate 8 bits r/m16 right imm8 times.
 D1 /1                    ROR r/m16, 1                 M1     Valid        Valid       Rotate 16 bits r/m16 right once.
 D3 /1                    ROR r/m16, CL                MC     Valid        Valid       Rotate 16 bits r/m16 right CL times.
 C1 /1 ib                 ROR r/m16, imm8              MI     Valid        Valid       Rotate 16 bits r/m16 right imm8 times.
 D1 /1                    ROR r/m32, 1                 M1     Valid        Valid       Rotate 32 bits r/m32 right once.
 REX.W + D1 /1            ROR r/m64, 1                 M1     Valid        N.E.        Rotate 64 bits r/m64 right once. Uses a 6 bit
                                                                                       count.
 D3 /1                    ROR r/m32, CL                MC     Valid        Valid       Rotate 32 bits r/m32 right CL times.
 REX.W + D3 /1            ROR r/m64, CL                MC     Valid        N.E.        Rotate 64 bits r/m64 right CL times. Uses a 6
                                                                                       bit count.
 C1 /1 ib                 ROR r/m32, imm8              MI     Valid        Valid       Rotate 32 bits r/m32 right imm8 times.
 REX.W + C1 /1 ib         ROR r/m64, imm8              MI     Valid        N.E.        Rotate 64 bits r/m64 right imm8 times. Uses a
                                                                                       6 bit count.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
 ** See IA-32 Architecture Compatibility section below.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                     Operand 2                      Operand 3                      Operand 4
    M1              ModRM:r/m (w)                        1                            NA                                NA
    MC              ModRM:r/m (w)                       CL                            NA                                NA
     MI             ModRM:r/m (w)                      imm8                           NA                                NA





Description
Shifts (rotates) the bits of the first operand (destination operand) the number of bit positions specified in the
second operand (count operand) and stores the result in the destination operand. The destination operand can be
a register or a memory location; the count operand is an unsigned integer that can be an immediate or a value in
the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W = 1).
The rotate left (ROL) and rotate through carry left (RCL) instructions shift all the bits toward more-significant bit
positions, except for the most-significant bit, which is rotated to the least-significant bit location. The rotate right
(ROR) and rotate through carry right (RCR) instructions shift all the bits toward less significant bit positions, except
for the least-significant bit, which is rotated to the most-significant bit location.
The RCL and RCR instructions include the CF flag in the rotation. The RCL instruction shifts the CF flag into the
least-significant bit and shifts the most-significant bit into the CF flag. The RCR instruction shifts the CF flag into
the most-significant bit and shifts the least-significant bit into the CF flag. For the ROL and ROR instructions, the
original value of the CF flag is not a part of the result, but the CF flag receives a copy of the bit that was shifted from
one end to the other.
The OF flag is defined only for the 1-bit rotates; it is undefined in all other cases (except RCL and RCR instructions
only: a zero-bit rotate does nothing, that is affects no flags). For left rotates, the OF flag is set to the exclusive OR
of the CF bit (after the rotate) and the most-significant bit of the result. For right rotates, the OF flag is set to the
exclusive OR of the two most-significant bits of the result.
In 64-bit mode, using a REX prefix in the form of REX.R permits access to additional registers (R8-R15). Use of
REX.W promotes the first operand to 64 bits and causes the count operand to become a 6-bit counter.

IA-32 Architecture Compatibility
The 8086 does not mask the rotation count. However, all other IA-32 processors (starting with the Intel 286
processor) do mask the rotation count to 5 bits, resulting in a maximum count of 31. This masking is done in all
operating modes (including the virtual-8086 mode) to reduce the maximum execution time of the instructions.

Operation
(* RCL and RCR instructions *)
SIZE <- OperandSize;
CASE (determine count) OF
    SIZE <- 8:    tempCOUNT <- (COUNT AND 1FH) MOD 9;
    SIZE <- 16: tempCOUNT <- (COUNT AND 1FH) MOD 17;
    SIZE <- 32: tempCOUNT <- COUNT AND 1FH;
    SIZE <- 64: tempCOUNT <- COUNT AND 3FH;
ESAC;

(* RCL instruction operation *)
WHILE (tempCOUNT != 0)
    DO
         tempCF <- MSB(DEST);
         DEST <- (DEST * 2) + CF;
         CF <- tempCF;
         tempCOUNT <- tempCOUNT - 1;
    OD;
ELIHW;
IF (COUNT & COUNTMASK) = 1
    THEN OF <- MSB(DEST) XOR CF;
    ELSE OF is undefined;
FI;





(* RCR instruction operation *)
IF (COUNT & COUNTMASK) = 1
    THEN OF <- MSB(DEST) XOR CF;
    ELSE OF is undefined;
FI;
WHILE (tempCOUNT != 0)
    DO
         tempCF <- LSB(SRC);
         DEST <- (DEST / 2) + (CF * 2SIZE);
         CF <- tempCF;
         tempCOUNT <- tempCOUNT - 1;
    OD;

(* ROL and ROR instructions *)
IF OperandSize = 64
    THEN COUNTMASK = 3FH;
    ELSE COUNTMASK = 1FH;
FI;

(* ROL instruction operation *)
tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE

WHILE (tempCOUNT != 0)
    DO
        tempCF <- MSB(DEST);
        DEST <- (DEST * 2) + tempCF;
        tempCOUNT <- tempCOUNT - 1;
    OD;
ELIHW;
IF (COUNT & COUNTMASK) != 0
    THEN CF <- LSB(DEST);
FI;
IF (COUNT & COUNTMASK) = 1
    THEN OF <- MSB(DEST) XOR CF;
    ELSE OF is undefined;
FI;

(* ROR instruction operation *)
tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE
WHILE (tempCOUNT != 0)
    DO
        tempCF <- LSB(SRC);
        DEST <- (DEST / 2) + (tempCF * 2SIZE);
        tempCOUNT <- tempCOUNT - 1;
    OD;
ELIHW;
IF (COUNT & COUNTMASK) != 0
    THEN CF <- MSB(DEST);
FI;
IF (COUNT & COUNTMASK) = 1
    THEN OF <- MSB(DEST) XOR MSB - 1(DEST);
    ELSE OF is undefined;
FI;




Flags Affected
If the masked count is 0, the flags are not affected. If the masked count is 1, then the OF flag is affected, otherwise
(masked count is greater than 1) the OF flag is undefined. The CF flag is affected when the masked count is non-
zero. The SF, ZF, AF, and PF flags are always unaffected.

Protected Mode Exceptions
#GP(0)               If the source operand is located in a non-writable segment.
                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                  If a memory operand effective address is outside the SS segment limit.
#UD                  If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made.
#UD                  If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the source operand is located in a nonwritable segment.
                     If the memory address is in a non-canonical form.
#PF(fault-code)      If a page fault occurs.
#AC(0)               If alignment checking is enabled and an unaligned memory reference is made while the
                     current privilege level is 3.
#UD                  If the LOCK prefix is used.






platform: x86_64
mnem: RCPPS
description:
RCPPS-Compute Reciprocals of Packed Single-Precision Floating-Point Values
 Opcode*/                                          Op/   64/32 bit     CPUID        Description
 Instruction                                       En    Mode          Feature
                                                         Support       Flag
 0F 53 /r                                          RM    V/V           SSE          Computes the approximate reciprocals of the
 RCPPS xmm1, xmm2/m128                                                              packed single-precision floating-point values
                                                                                    in xmm2/m128 and stores the results in
                                                                                    xmm1.
 VEX.128.0F.WIG 53 /r                              RM    V/V           AVX          Computes the approximate reciprocals of
 VRCPPS xmm1, xmm2/m128                                                             packed single-precision values in xmm2/mem
                                                                                    and stores the results in xmm1.
 VEX.256.0F.WIG 53 /r                              RM    V/V           AVX          Computes the approximate reciprocals of
 VRCPPS ymm1, ymm2/m256                                                             packed single-precision values in ymm2/mem
                                                                                    and stores the results in ymm1.



                                           Instruction Operand Encoding
   Op/En                Operand 1                Operand 2                       Operand 3                      Operand 4
     RM              ModRM:reg (w)              ModRM:r/m (r)                       NA                              NA


Description
Performs a SIMD computation of the approximate reciprocals of the four packed single-precision floating-point
values in the source operand (second operand) stores the packed single-precision floating-point results in the
destination operand. The source operand can be an XMM register or a 128-bit memory location. The destination
operand is an XMM register. See Figure 10-5 in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.
The relative error for this approximation is:

   |Relative Error| <= 1.5 * 2-12
The RCPPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a
0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results (see Section 4.9.1.5, "Numeric Underflow Exception (#U)" in Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater
than or equal to |1.11111111110100000000000B*2125| are guaranteed to not produce tiny results; input values
less than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in
turn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the
implementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN
is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





Operation
RCPPS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] (Unmodified)

VRCPPS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[VLMAX-1:128] <- 0

VRCPPS (VEX.256 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[63:32] <- APPROXIMATE(1/SRC[63:32])
DEST[95:64] <- APPROXIMATE(1/SRC[95:64])
DEST[127:96] <- APPROXIMATE(1/SRC[127:96])
DEST[159:128] <- APPROXIMATE(1/SRC[159:128])
DEST[191:160] <- APPROXIMATE(1/SRC[191:160])
DEST[223:192] <- APPROXIMATE(1/SRC[223:192])
DEST[255:224] <- APPROXIMATE(1/SRC[255:224])

Intel C/C++ Compiler Intrinsic Equivalent
RCCPS:           __m128 _mm_rcp_ps(__m128 a)
RCPPS:            __m256 _mm256_rcp_ps (__m256 a);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                       If VEX.vvvv != 1111B.






platform: x86_64
mnem: RCPSS
description:
RCPSS-Compute Reciprocal of Scalar Single-Precision Floating-Point Values
Opcode*/                                           Op/      64/32 bit     CPUID        Description
Instruction                                        En       Mode          Feature
                                                            Support       Flag
F3 0F 53 /r                                        RM       V/V           SSE          Computes the approximate reciprocal of the
RCPSS xmm1, xmm2/m32                                                                   scalar single-precision floating-point value in
                                                                                       xmm2/m32 and stores the result in xmm1.
VEX.NDS.LIG.F3.0F.WIG 53 /r                        RVM V/V                AVX          Computes the approximate reciprocal of the
VRCPSS xmm1, xmm2, xmm3/m32                                                            scalar single-precision floating-point value in
                                                                                       xmm3/m32 and stores the result in xmm1.
                                                                                       Also, upper single precision floating-point
                                                                                       values (bits[127:32]) from xmm2 are copied to
                                                                                       xmm1[127:32].



                                           Instruction Operand Encoding
  Op/En              Operand 1                  Operand 2                         Operand 3                        Operand 4
    RM            ModRM:reg (w)            ModRM:r/m (r)                              NA                               NA
   RVM            ModRM:reg (w)             VEX.vvvv (r)                        ModRM:r/m (r)                          NA


Description
Computes of an approximate reciprocal of the low single-precision floating-point value in the source operand
(second operand) and stores the single-precision floating-point result in the destination operand. The source
operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The
three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel 64 and
IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a scalar single-precision floating-
point operation.
The relative error for this approximation is:

   |Relative Error| <= 1.5 * 2-12
The RCPSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a
0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign).
Tiny results (see Section 4.9.1.5, "Numeric Underflow Exception (#U)" in Intel 64 and IA-32 Architectures Soft-
ware Developer's Manual, Volume 1) are always flushed to 0.0, with the sign of the operand. (Input values greater
than or equal to |1.11111111110100000000000B*2125| are guaranteed to not produce tiny results; input values
less than or equal to |1.00000000000110000000001B*2126| are guaranteed to produce tiny results, which are in
turn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the
implementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN
is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation
RCPSS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SRC[31:0])
DEST[VLMAX-1:32] (Unmodified)





VRCPSS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SRC2[31:0])
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
RCPSS:           __m128 _mm_rcp_ss(__m128 a)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 5.






platform: x86_64
mnem: RDFSBASE
description:
RDFSBASE/RDGSBASE-Read FS/GS Segment Base
Opcode/                                        Op/        64/32-   CPUID Fea-   Description
Instruction                                    En         bit      ture Flag
                                                          Mode
F3 0F AE /0                                    M          V/I      FSGSBASE     Load the 32-bit destination register with the FS
RDFSBASE r32                                                                    base address.
F3 REX.W 0F AE /0                              M          V/I      FSGSBASE     Load the 64-bit destination register with the FS
RDFSBASE r64                                                                    base address.
F3 0F AE /1                                    M          V/I      FSGSBASE     Load the 32-bit destination register with the GS
RDGSBASE r32                                                                    base address.
F3 REX.W 0F AE /1                              M          V/I      FSGSBASE     Load the 64-bit destination register with the GS
RDGSBASE r64                                                                    base address.



                                              Instruction Operand Encoding
  Op/En             Operand 1                  Operand 2                        Operand 3                      Operand 4
    M            ModRM:r/m (w)                       NA                            NA                             NA


Description
Loads the general-purpose register indicated by the modR/M:r/m field with the FS or GS segment base address.
The destination operand may be either a 32-bit or a 64-bit general-purpose register. The REX.W prefix indicates the
operand size is 64 bits. If no REX.W prefix is used, the operand size is 32 bits; the upper 32 bits of the source base
address (for FS or GS) are ignored and upper 32 bits of the destination register are cleared.
This instruction is supported only in 64-bit mode.

Operation
DEST <- FS/GS segment base address;

Flags Affected
None

C/C++ Compiler Intrinsic Equivalent
RDFSBASE:        unsigned int _readfsbase_u32(void );
RDFSBASE:        unsigned __int64 _readfsbase_u64(void );
RDGSBASE:        unsigned int _readgsbase_u32(void );
RDGSBASE:        unsigned __int64 _readgsbase_u64(void );

Protected Mode Exceptions
#UD                   The RDFSBASE and RDGSBASE instructions are not recognized in protected mode.

Real-Address Mode Exceptions
#UD                   The RDFSBASE and RDGSBASE instructions are not recognized in real-address mode.

Virtual-8086 Mode Exceptions
#UD                   The RDFSBASE and RDGSBASE instructions are not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
#UD                   The RDFSBASE and RDGSBASE instructions are not recognized in compatibility mode.



64-Bit Mode Exceptions
#UD                   If the LOCK prefix is used.
                      If CR4.FSGSBASE[bit 16] = 0.
                      If CPUID.07H.0H:EBX.FSGSBASE[bit 0] = 0.






platform: x86_64
mnem: RDMSR
description:
RDMSR-Read from Model Specific Register
Opcode*                  Instruction                    Op/   64-Bit   Compat/ Description
                                                        En    Mode     Leg Mode
0F 32                    RDMSR                          NP    Valid    Valid       Read MSR specified by ECX into EDX:EAX.
NOTES:
* See IA-32 Architecture Compatibility section below.



                                                Instruction Operand Encoding
  Op/En             Operand 1                    Operand 2                     Operand 3                    Operand 4
    NP                  NA                              NA                        NA                            NA


Description
Reads the contents of a 64-bit model specific register (MSR) specified in the ECX register into registers EDX:EAX.
(On processors that support the Intel 64 architecture, the high-order 32 bits of RCX are ignored.) The EDX register
is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits. (On
processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.) If
fewer than 64 bits are implemented in the MSR being read, the values returned to EDX:EAX in unimplemented bit
locations are undefined.
This instruction must be executed at privilege level 0 or in real-address mode; otherwise, a general protection
exception #GP(0) will be generated. Specifying a reserved or unimplemented MSR address in ECX will also cause a
general protection exception.
The MSRs control functions for testability, execution tracing, performance-monitoring, and machine check errors.
Chapter 35, "Model-Specific Registers (MSRs)," in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3C, lists all the MSRs that can be read with this instruction and their addresses. Note that each
processor family has its own set of MSRs.
The CPUID instruction should be used to determine whether MSRs are supported (CPUID.01H:EDX[5] = 1) before
using this instruction.

IA-32 Architecture Compatibility
The MSRs and the ability to read them with the RDMSR instruction were introduced into the IA-32 Architecture with
the Pentium processor. Execution of this instruction by an IA-32 processor earlier than the Pentium processor
results in an invalid opcode exception #UD.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
EDX:EAX <- MSR[ECX];

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                If the current privilege level is not 0.
                      If the value in ECX specifies a reserved or unimplemented MSR address.
#UD                   If the LOCK prefix is used.





Real-Address Mode Exceptions
#GP                     If the value in ECX specifies a reserved or unimplemented MSR address.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   The RDMSR instruction is not recognized in virtual-8086 mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RDPID
description:
RDPID-Read Processor ID
Opcode/                                     Op/    64/32-   CPUID        Description
Instruction                                 En     bit      Feature Flag
                                                   Mode
F3 0F C7 /7                                 M      N.E./V   RDPID        Read IA32_TSC_AUX into r32.
RDPID r32
F3 0F C7 /7                                 M      V/N.E.   RDPID        Read IA32_TSC_AUX into r64.
RDPID r64



                                            Instruction Operand Encoding
  Op/En            Operand 1                 Operand 2                  Operand 3                      Operand 4
    M            ModRM:r/m (w)                    NA                       NA                             NA


Description
Reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the destination register. The value of CS.D
and operand-size prefixes (66H and REX.W) do not affect the behavior of the RDPID instruction.

Operation

DEST <- IA32_TSC_AUX

Flags Affected
None.

Protected Mode Exceptions
#UD                  If the LOCK prefix is used.
                     If the F2 prefix is used.
                     If CPUID.7H.0:ECX.RDPID[bit 22] = 0.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RDPKRU
description:
RDPKRU-Read Protection Key Rights for User Pages
Opcode*                 Instruction                Op/   64/32bit   CPUID     Description
                                                   En    Mode       Feature
                                                         Support    Flag
0F 01 EE                RDPKRU                     NP    V/V        OSPKE     Reads PKRU into EAX.



                                                   Instruction Operand Encoding
  Op/En              Operand 1                      Operand 2                  Operand 3                  Operand 4
    NP                  NA                               NA                       NA                          NA


Description
Reads the value of PKRU into EAX and clears EDX. ECX must be 0 when RDPKRU is executed; otherwise, a general-
protection exception (#GP) occurs.
RDPKRU can be executed only if CR4.PKE = 1; otherwise, an invalid-opcode exception (#UD) occurs. Software can
discover the value of CR4.PKE by examining CPUID.(EAX=07H,ECX=0H):ECX.OSPKE [bit 4].
On processors that support the Intel 64 Architecture, the high-order 32-bits of RCX are ignored and the high-order
32-bits of RDX and RAX are cleared.

Operation

IF (ECX = 0)
    THEN
        EAX <- PKRU;
        EDX <- 0;
    ELSE #GP(0);
FI;

Flags Affected
None.

C/C++ Compiler Intrinsic Equivalent
RDPKRU:             uint32_t _rdpkru_u32(void);

Protected Mode Exceptions
#GP(0)                  If ECX   !=0
#UD                     If the LOCK prefix is used.
                        If CR4.PKE = 0.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RDPMC
description:
RDPMC-Read Performance-Monitoring Counters
Opcode*                  Instruction               Op/     64-Bit   Compat/ Description
                                                   En      Mode     Leg Mode
0F 33                    RDPMC                     NP      Valid    Valid        Read performance-monitoring counter
                                                                                 specified by ECX into EDX:EAX.



                                              Instruction Operand Encoding
    Op/En           Operand 1                  Operand 2                    Operand 3                   Operand 4
      NP                NA                        NA                           NA                            NA


Description
The EAX register is loaded with the low-order 32 bits. The EDX register is loaded with the supported high-order bits
of the counter. The number of high-order bits loaded into EDX is implementation specific on processors that do no
support architectural performance monitoring. The width of fixed-function and general-purpose performance coun-
ters on processors supporting architectural performance monitoring are reported by CPUID 0AH leaf. See below for
the treatment of the EDX register for "fast" reads.
The ECX register specifies the counter type (if the processor supports architectural performance monitoring) and
counter index. Counter type is specified in ECX[30] to select one of two type of performance counters. If the
processor does not support architectural performance monitoring, ECX[30:0] specifies the counter index; other-
wise ECX[29:0] specifies the index relative to the base of each counter type. ECX[31] selects "fast" read mode if
supported. The two counter types are:
.     General-purpose or special-purpose performance counters are specified with ECX[30] = 0: The number of
      general-purpose performance counters on processor supporting architectural performance monitoring are
      reported by CPUID 0AH leaf. The number of general-purpose counters is model specific if the processor does
      not support architectural performance monitoring, see Chapter 18, "Performance Monitoring" of Intel 64 and
      IA-32 Architectures Software Developer's Manual, Volume 3B. Special-purpose counters are available only in
      selected processor members, see Table 4-16.
.     Fixed-function performance counter are specified with ECX[30] = 1. The number fixed-function performance
      counters is enumerated by CPUID 0AH leaf. See Chapter 30 of Intel 64 and IA-32 Architectures Software
      Developer's Manual, Volume 3B. This counter type is selected if ECX[30] is set.
The width of fixed-function performance counters and general-purpose performance counters on processor
supporting architectural performance monitoring are reported by CPUID 0AH leaf. The width of general-purpose
performance counters are 40-bits for processors that do not support architectural performance monitoring coun-
ters. The width of special-purpose performance counters are implementation specific.
Table 4-16 lists valid indices of the general-purpose and special-purpose performance counters according to the
DisplayFamily_DisplayModel values of CPUID encoding for each processor family (see CPUID instruction in Chapter
3, "Instruction Set Reference, A-L" in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume
2A).


            Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC
 Processor Family                            DisplayFamily_DisplayModel/      Valid PMC Index         General-purpose
                                             Other Signatures                 Range                   Counters
 P6                                          06H_01H, 06H_03H, 06H_05H,       0, 1                    0, 1
                                             06H_06H, 06H_07H, 06H_08H,
                                             06H_0AH, 06H_0BH
 Processors Based on Intel NetBurst          0FH_00H, 0FH_01H, 0FH_02H,       >= 0 and <= 17            >= 0 and <= 17
 microarchitecture (No L3)                   0FH_03H, 0FH_04H, 0FH_06H
 Pentium M processors                        06H_09H, 06H_0DH                 0, 1                    0, 1
 Processors Based on Intel NetBurst          0FH_03H, 0FH_04H) and (L3 is     >= 0 and <= 25            >= 0 and <= 17
 microarchitecture (No L3)                   present)




       Table 4-16. Valid General and Special Purpose Performance Counter Index Range for RDPMC (Contd.)
 Processor Family                               DisplayFamily_DisplayModel/   Valid PMC Index          General-purpose
                                                Other Signatures              Range                    Counters
 Intel Core Solo and Intel Core Duo         06H_0EH                       0, 1                     0, 1
 processors, Dual-core Intel Xeon
 processor LV
 Intel Core2 Duo processor, Intel Xeon        06H_0FH                       0, 1                     0, 1
 processor 3000, 5100, 5300, 7300 Series -
 general-purpose PMC
 Intel Core2 Duo processor family, Intel      06H_17H                       0, 1                     0, 1
 Xeon processor 3100, 3300, 5200, 5400
 series - general-purpose PMC
 Intel Xeon processors 7400 series              (06H_1DH)                     >= 0 and <= 9              0, 1
                         
 45 nm and 32 nm Intel       Atom processors   06H_1CH, 06_26H, 06_27H,      0, 1                     0, 1
                                                06_35H, 06_36H
 Intel Atom processors based on               06H_37H, 06_4AH, 06_4DH,      0, 1                     0, 1
 Silvermont or Airmont microarchitectures       06_5AH, 06_5DH, 06_4CH
 Next Generation Intel Atom processors        06H_5CH, 06_5FH               0-3                      0-3
 based on Goldmont microarchitecture
 Intel processors based on the Nehalem,        06H_1AH, 06H_1EH, 06H_1FH,    0-3                      0-3
 Westmere microarchitectures                    06_25H, 06_2CH, 06H_2EH,
                                                06_2FH
 Intel processors based on the Sandy           06H_2AH, 06H_2DH, 06H_3AH,    0-3 (0-7 if              0-3 (0-7 if
 Bridge, Ivy Bridge microarchitecture           06H_3EH                       HyperThreading is off)   HyperThreading is off)
 Intel processors based on the Haswell,        06H_3CH, 06H_45H, 06H_46H,    0-3 (0-7 if              0-3 (0-7 if
 Broadwell, SkyLake microarchitectures          06H_3FH, 06_3DH, 06_47H,      HyperThreading is off)   HyperThreading is off)
                                                4FH, 06_56H, 06_4EH, 06_5EH

Processors based on Intel NetBurst microarchitecture support "fast" (32-bit) and "slow" (40-bit) reads on the first
18 performance counters. Selected this option using ECX[31]. If bit 31 is set, RDPMC reads only the low 32 bits of
the selected performance counter. If bit 31 is clear, all 40 bits are read. A 32-bit result is returned in EAX and EDX
is set to 0. A 32-bit read executes faster on these processors than a full 40-bit read.
On processors based on Intel NetBurst microarchitecture with L3, performance counters with indices 18-25 are 32-
bit counters. EDX is cleared after executing RDPMC for these counters.
In Intel Core 2 processor family, Intel Xeon processor 3000, 5100, 5300 and 7400 series, the fixed-function perfor-
mance counters are 40-bits wide; they can be accessed by RDMPC with ECX between from 4000_0000H and
4000_0002H.
On Intel Xeon processor 7400 series, there are eight 32-bit special-purpose counters addressable with indices 2-9,
ECX[30]=0.
When in protected or virtual 8086 mode, the performance-monitoring counters enabled (PCE) flag in register CR4
restricts the use of the RDPMC instruction as follows. When the PCE flag is set, the RDPMC instruction can be
executed at any privilege level; when the flag is clear, the instruction can only be executed at privilege level 0.
(When in real-address mode, the RDPMC instruction is always enabled.)
The performance-monitoring counters can also be read with the RDMSR instruction, when executing at privilege
level 0.
The performance-monitoring counters are event counters that can be programmed to count events such as the
number of instructions decoded, number of interrupts received, or number of cache loads. Chapter 19, "Perfor-
mance Monitoring Events," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3B, lists
the events that can be counted for various processors in the Intel 64 and IA-32 architecture families.
The RDPMC instruction is not a serializing instruction; that is, it does not imply that all the events caused by the
preceding instructions have been completed or that events caused by subsequent instructions have not begun. If




an exact event count is desired, software must insert a serializing instruction (such as the CPUID instruction)
before and/or after the RDPMC instruction.
Performing back-to-back fast reads are not guaranteed to be monotonic. To guarantee monotonicity on back-to-
back reads, a serializing instruction must be placed between the two RDPMC instructions.
The RDPMC instruction can execute in 16-bit addressing mode or virtual-8086 mode; however, the full contents of
the ECX register are used to select the counter, and the event count is stored in the full EAX and EDX registers. The
RDPMC instruction was introduced into the IA-32 Architecture in the Pentium Pro processor and the Pentium
processor with MMX technology. The earlier Pentium processors have performance-monitoring counters, but they
must be read with the RDMSR instruction.

Operation
(* Intel processors that support architectural performance monitoring *)

Most significant counter bit (MSCB) = 47

IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
     THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
         EAX <- IA32_FIXED_CTR(ECX)[30:0];
         EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];
     ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
         EAX <- PMC(ECX[30:0])[31:0];
         EDX <- PMC(ECX[30:0])[MSCB:32];
     ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
         #GP(0);
FI;

(* Intel Core 2 Duo processor family and Intel Xeon processor 3000, 5100, 5300, 7400 series*)

Most significant counter bit (MSCB) = 39

IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
     THEN IF (ECX[30] = 1 and ECX[29:0] in valid fixed-counter range)
         EAX <- IA32_FIXED_CTR(ECX)[30:0];
         EDX <- IA32_FIXED_CTR(ECX)[MSCB:32];
     ELSE IF (ECX[30] = 0 and ECX[29:0] in valid general-purpose counter range)
         EAX <- PMC(ECX[30:0])[31:0];
         EDX <- PMC(ECX[30:0])[MSCB:32];
     ELSE IF (ECX[30] = 0 and ECX[29:0] in valid special-purpose counter range)
         EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
     ELSE (* ECX is not valid or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
         #GP(0);
FI;

(* P6 family processors and Pentium processor with MMX technology *)

IF (ECX = 0 or 1) and ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
     THEN
         EAX <- PMC(ECX)[31:0];
         EDX <- PMC(ECX)[39:32];
     ELSE (* ECX is not 0 or 1 or CR4.PCE is 0 and CPL is 1, 2, or 3 and CR0.PE is 1 *)
         #GP(0);
FI;
(* Processors based on Intel NetBurst microarchitecture *)
IF ((CR4.PCE = 1) or (CPL = 0) or (CR0.PE = 0))
     THEN IF (ECX[30:0] = 0:17)
         THEN IF ECX[31] = 0



              THEN
                   EAX <- PMC(ECX[30:0])[31:0]; (* 40-bit read *)
                   EDX <- PMC(ECX[30:0])[39:32];
        ELSE (* ECX[31] = 1*)
              THEN
                   EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
                   EDX <- 0;
        FI;
    ELSE IF (*64-bit Intel processor based on Intel NetBurst microarchitecture with L3 *)
        THEN IF (ECX[30:0] = 18:25 )
              EAX <- PMC(ECX[30:0])[31:0]; (* 32-bit read *)
              EDX <- 0;
        FI;
    ELSE (* Invalid PMC index in ECX[30:0], see Table 4-19. *)
        GP(0);
    FI;
ELSE (* CR4.PCE = 0 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
    #GP(0);
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.
                        If an invalid performance counter index is specified (see Table 4-16).
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If an invalid performance counter index is specified (see Table 4-16).
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If the PCE flag in the CR4 register is clear.
                        If an invalid performance counter index is specified (see Table 4-16).
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#GP(0)                  If the current privilege level is not 0 and the PCE flag in the CR4 register is clear.
                        If an invalid performance counter index is specified (see Table 4-16).
#UD                     If the LOCK prefix is used.






platform: x86_64
mnem: RDRAND
description:
RDRAND-Read Random Number
Opcode*/                                            Op/    64/32 bit   CPUID      Description
Instruction                                         En     Mode        Feature
                                                           Support     Flag
0F C7 /6                                            M      V/V         RDRAND     Read a 16-bit random number and store in the
RDRAND r16                                                                        destination register.

0F C7 /6                                            M      V/V         RDRAND     Read a 32-bit random number and store in the
RDRAND r32                                                                        destination register.

REX.W + 0F C7 /6                                    M      V/I         RDRAND     Read a 64-bit random number and store in the
RDRAND r64                                                                        destination register.



                                              Instruction Operand Encoding
  Op/En              Operand 1                 Operand 2                    Operand 3                      Operand 4
    M              ModRM:r/m (w)                   NA                            NA                           NA


Description
Loads a hardware generated random value and store it in the destination register. The size of the random value is
determined by the destination register size and operating mode. The Carry Flag indicates whether a random value
is available at the time the instruction is executed. CF=1 indicates that the data in the destination is valid. Other-
wise CF=0 and the data in the destination operand will be returned as zeros for the specified width. All other flags
are forced to 0 in either situation. Software must check the state of CF=1 for determining if a valid random value
has been returned, otherwise it is expected to loop and retry execution of RDRAND (see Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 1, Section 7.3.17, "Random Number Generator Instructions").
This instruction is available at all privilege levels.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-
ands. See the summary chart at the beginning of this section for encoding data and limits.

Operation
IF HW_RND_GEN.ready = 1
    THEN
         CASE of
             osize is 64: DEST[63:0] <- HW_RND_GEN.data;
             osize is 32: DEST[31:0] <- HW_RND_GEN.data;
             osize is 16: DEST[15:0] <- HW_RND_GEN.data;
         ESAC
         CF <- 1;
    ELSE
         CASE of
             osize is 64: DEST[63:0] <- 0;
             osize is 32: DEST[31:0] <- 0;
             osize is 16: DEST[15:0] <- 0;
         ESAC
         CF <- 0;
FI
OF, SF, ZF, AF, PF <- 0;

Flags Affected
The CF flag is set according to the result (see the "Operation" section above). The OF, SF, ZF, AF, and PF flags are
set to 0.



Intel C/C++ Compiler Intrinsic Equivalent
RDRAND:         int _rdrand16_step( unsigned short * );
RDRAND:         int _rdrand32_step( unsigned int * );
RDRAND:         int _rdrand64_step( unsigned __int64 *);

Protected Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.01H:ECX.RDRAND[bit 30] = 0.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RDSEED
description:
RDSEED-Read Random SEED
 Opcode/                         Op/      64/32      CPUID         Description
 Instruction                     En       bit Mode   Feature
                                          Support    Flag
 0F C7 /7                        M        V/V        RDSEED        Read a 16-bit NIST SP800-90B & C compliant random value and
 RDSEED r16                                                        store in the destination register.

 0F C7 /7                        M        V/V        RDSEED        Read a 32-bit NIST SP800-90B & C compliant random value and
 RDSEED r32                                                        store in the destination register.

 REX.W + 0F C7 /7                M        V/I        RDSEED        Read a 64-bit NIST SP800-90B & C compliant random value and
 RDSEED r64                                                        store in the destination register.


                                                 Instruction Operand Encoding
      Op/En                 Operand 1                  Operand 2                 Operand 3                   Operand 4
        M                 ModRM:r/m (w)                   NA                         NA                         NA

Description
Loads a hardware generated random value and store it in the destination register. The random value is generated
from an Enhanced NRBG (Non Deterministic Random Bit Generator) that is compliant to NIST SP800-90B and NIST
SP800-90C in the XOR construction mode. The size of the random value is determined by the destination register
size and operating mode. The Carry Flag indicates whether a random value is available at the time the instruction
is executed. CF=1 indicates that the data in the destination is valid. Otherwise CF=0 and the data in the destination
operand will be returned as zeros for the specified width. All other flags are forced to 0 in either situation. Software
must check the state of CF=1 for determining if a valid random seed value has been returned, otherwise it is
expected to loop and retry execution of RDSEED (see Section 1.2).
The RDSEED instruction is available at all privilege levels. The RDSEED instruction executes normally either inside
or outside a transaction region.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.B permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bit oper-
ands. See the summary chart at the beginning of this section for encoding data and limits.

Operation
IF HW_NRND_GEN.ready = 1
    THEN
        CASE of
            osize is 64: DEST[63:0] <- HW_NRND_GEN.data;
            osize is 32: DEST[31:0] <- HW_NRND_GEN.data;
            osize is 16: DEST[15:0] <- HW_NRND_GEN.data;
        ESAC;
        CF <- 1;
    ELSE
        CASE of
            osize is 64: DEST[63:0] <- 0;
            osize is 32: DEST[31:0] <- 0;
            osize is 16: DEST[15:0] <- 0;
        ESAC;
        CF <- 0;
FI;

OF, SF, ZF, AF, PF <- 0;




Flags Affected

The CF flag is set according to the result (see the "Operation" section above). The OF, SF, ZF, AF, and PF flags
are set to 0.

C/C++ Compiler Intrinsic Equivalent
RDSEED int _rdseed16_step( unsigned short * );
RDSEED int _rdseed32_step( unsigned int * );
RDSEED int _rdseed64_step( unsigned __int64 *);

Protected Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.

Real-Address Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.

Virtual-8086 Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.

Compatibility Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.

64-Bit Mode Exceptions
#UD                    If the LOCK prefix is used.
                       If the F2H or F3H prefix is used.
                       If CPUID.(EAX=07H, ECX=0H):EBX.RDSEED[bit 18] = 0.






platform: x86_64
mnem: RDTSC
description:
RDTSC-Read Time-Stamp Counter
 Opcode*                  Instruction                   Op/   64-Bit   Compat/ Description
                                                        En    Mode     Leg Mode
 0F 31                    RDTSC                         NP    Valid    Valid      Read time-stamp counter into EDX:EAX.



                                                  Instruction Operand Encoding
   Op/En               Operand 1                     Operand 2                 Operand 3                  Operand 4
     NP                    NA                            NA                       NA                          NA


Description
Reads the current value of the processor's time-stamp counter (a 64-bit MSR) into the EDX:EAX registers. The EDX
register is loaded with the high-order 32 bits of the MSR and the EAX register is loaded with the low-order 32 bits.
(On processors that support the Intel 64 architecture, the high-order 32 bits of each of RAX and RDX are cleared.)
The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever
the processor is reset. See "Time Stamp Counter" in Chapter 17 of the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 3B, for specific details of the time stamp counter behavior.
The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSC instruction as follows. When the
flag is clear, the RDTSC instruction can be executed at any privilege level; when the flag is set, the instruction can
only be executed at privilege level 0.
The time-stamp counter can also be read with the RDMSR instruction, when executing at privilege level 0.
The RDTSC instruction is not a serializing instruction. It does not necessarily wait until all previous instructions
have been executed before reading the counter. Similarly, subsequent instructions may begin execution before the
read operation is performed. If software requires RDTSC to be executed only after all previous instructions have
completed locally, it can either use RDTSCP (if the processor supports that instruction) or execute the sequence
LFENCE;RDTSC.
This instruction was introduced by the Pentium processor.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
    THEN EDX:EAX <- TimeStampCounter;
    ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
         #GP(0);
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the TSD flag in register CR4 is set and the CPL is greater than 0.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#UD                     If the LOCK prefix is used.





Virtual-8086 Mode Exceptions
#GP(0)              If the TSD flag in register CR4 is set.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RDTSCP
description:
RDTSCP-Read Time-Stamp Counter and Processor ID
Opcode*                   Instruction                   Op/    64-Bit   Compat/ Description
                                                        En     Mode     Leg Mode
0F 01 F9                  RDTSCP                        NP     Valid    Valid       Read 64-bit time-stamp counter and
                                                                                    IA32_TSC_AUX value into EDX:EAX and ECX.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                  Operand 3                  Operand 4
    NP                    NA                            NA                         NA                         NA


Description
Reads the current value of the processor's time-stamp counter (a 64-bit MSR) into the EDX:EAX registers and also
reads the value of the IA32_TSC_AUX MSR (address C0000103H) into the ECX register. The EDX register is loaded
with the high-order 32 bits of the IA32_TSC MSR; the EAX register is loaded with the low-order 32 bits of the
IA32_TSC MSR; and the ECX register is loaded with the low-order 32-bits of IA32_TSC_AUX MSR. On processors
that support the Intel 64 architecture, the high-order 32 bits of each of RAX, RDX, and RCX are cleared.
The processor monotonically increments the time-stamp counter MSR every clock cycle and resets it to 0 whenever
the processor is reset. See "Time Stamp Counter" in Chapter 17 of the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 3B, for specific details of the time stamp counter behavior.
The time stamp disable (TSD) flag in register CR4 restricts the use of the RDTSCP instruction as follows. When the
flag is clear, the RDTSCP instruction can be executed at any privilege level; when the flag is set, the instruction can
only be executed at privilege level 0.
The RDTSCP instruction waits until all previous instructions have been executed before reading the counter.
However, subsequent instructions may begin execution before the read operation is performed.
See "Changes to Instruction Behavior in VMX Non-Root Operation" in Chapter 25 of the Intel 64 and IA-32 Archi-
tectures Software Developer's Manual, Volume 3C, for more information about the behavior of this instruction in
VMX non-root operation.

Operation
IF (CR4.TSD = 0) or (CPL = 0) or (CR0.PE = 0)
    THEN
         EDX:EAX <- TimeStampCounter;
         ECX <- IA32_TSC_AUX[31:0];
    ELSE (* CR4.TSD = 1 and (CPL = 1, 2, or 3) and CR0.PE = 1 *)
         #GP(0);
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the TSD flag in register CR4 is set and the CPL is greater than 0.
#UD                     If the LOCK prefix is used.
                        If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.

Real-Address Mode Exceptions
#UD                     If the LOCK prefix is used.
                        If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.




Virtual-8086 Mode Exceptions
#GP(0)              If the TSD flag in register CR4 is set.
#UD                 If the LOCK prefix is used.
                    If CPUID.80000001H:EDX.RDTSCP[bit 27] = 0.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: REP
description:
REP/REPE/REPZ/REPNE/REPNZ-Repeat String Operation Prefix
 Opcode                   Instruction                  Op/   64-Bit   Compat/ Description
                                                       En    Mode     Leg Mode
 F3 6C                    REP INS m8, DX               NP    Valid    Valid    Input (E)CX bytes from port DX into ES:[(E)DI].
 F3 6C                    REP INS m8, DX               NP    Valid    N.E.     Input RCX bytes from port DX into [RDI].
 F3 6D                    REP INS m16, DX              NP    Valid    Valid    Input (E)CX words from port DX into ES:[(E)DI.]
 F3 6D                    REP INS m32, DX              NP    Valid    Valid    Input (E)CX doublewords from port DX into
                                                                               ES:[(E)DI].
 F3 6D                    REP INS r/m32, DX            NP    Valid    N.E.     Input RCX default size from port DX into [RDI].
 F3 A4                    REP MOVS m8, m8              NP    Valid    Valid    Move (E)CX bytes from DS:[(E)SI] to ES:[(E)DI].
 F3 REX.W A4              REP MOVS m8, m8              NP    Valid    N.E.     Move RCX bytes from [RSI] to [RDI].
 F3 A5                    REP MOVS m16, m16            NP    Valid    Valid    Move (E)CX words from DS:[(E)SI] to ES:[(E)DI].
 F3 A5                    REP MOVS m32, m32            NP    Valid    Valid    Move (E)CX doublewords from DS:[(E)SI] to
                                                                               ES:[(E)DI].
 F3 REX.W A5              REP MOVS m64, m64            NP    Valid    N.E.     Move RCX quadwords from [RSI] to [RDI].
 F3 6E                    REP OUTS DX, r/m8            NP    Valid    Valid    Output (E)CX bytes from DS:[(E)SI] to port DX.
 F3 REX.W 6E              REP OUTS DX, r/m8*           NP    Valid    N.E.     Output RCX bytes from [RSI] to port DX.
 F3 6F                    REP OUTS DX, r/m16           NP    Valid    Valid    Output (E)CX words from DS:[(E)SI] to port DX.
 F3 6F                    REP OUTS DX, r/m32           NP    Valid    Valid    Output (E)CX doublewords from DS:[(E)SI] to
                                                                               port DX.
 F3 REX.W 6F              REP OUTS DX, r/m32           NP    Valid    N.E.     Output RCX default size from [RSI] to port DX.
 F3 AC                    REP LODS AL                  NP    Valid    Valid    Load (E)CX bytes from DS:[(E)SI] to AL.
 F3 REX.W AC              REP LODS AL                  NP    Valid    N.E.     Load RCX bytes from [RSI] to AL.
 F3 AD                    REP LODS AX                  NP    Valid    Valid    Load (E)CX words from DS:[(E)SI] to AX.
 F3 AD                    REP LODS EAX                 NP    Valid    Valid    Load (E)CX doublewords from DS:[(E)SI] to
                                                                               EAX.
 F3 REX.W AD              REP LODS RAX                 NP    Valid    N.E.     Load RCX quadwords from [RSI] to RAX.
 F3 AA                    REP STOS m8                  NP    Valid    Valid    Fill (E)CX bytes at ES:[(E)DI] with AL.
 F3 REX.W AA              REP STOS m8                  NP    Valid    N.E.     Fill RCX bytes at [RDI] with AL.
 F3 AB                    REP STOS m16                 NP    Valid    Valid    Fill (E)CX words at ES:[(E)DI] with AX.
 F3 AB                    REP STOS m32                 NP    Valid    Valid    Fill (E)CX doublewords at ES:[(E)DI] with EAX.
 F3 REX.W AB              REP STOS m64                 NP    Valid    N.E.     Fill RCX quadwords at [RDI] with RAX.
 F3 A6                    REPE CMPS m8, m8             NP    Valid    Valid    Find nonmatching bytes in ES:[(E)DI] and
                                                                               DS:[(E)SI].
 F3 REX.W A6              REPE CMPS m8, m8             NP    Valid    N.E.     Find non-matching bytes in [RDI] and [RSI].
 F3 A7                    REPE CMPS m16, m16           NP    Valid    Valid    Find nonmatching words in ES:[(E)DI] and
                                                                               DS:[(E)SI].
 F3 A7                    REPE CMPS m32, m32           NP    Valid    Valid    Find nonmatching doublewords in ES:[(E)DI]
                                                                               and DS:[(E)SI].
 F3 REX.W A7              REPE CMPS m64, m64           NP    Valid    N.E.     Find non-matching quadwords in [RDI] and
                                                                               [RSI].
 F3 AE                    REPE SCAS m8                 NP    Valid    Valid    Find non-AL byte starting at ES:[(E)DI].
 F3 REX.W AE              REPE SCAS m8                 NP    Valid    N.E.     Find non-AL byte starting at [RDI].
 F3 AF                    REPE SCAS m16                NP    Valid    Valid    Find non-AX word starting at ES:[(E)DI].
 F3 AF                    REPE SCAS m32                NP    Valid    Valid    Find non-EAX doubleword starting at
                                                                               ES:[(E)DI].


 Opcode                    Instruction                   Op/    64-Bit     Compat/ Description
                                                         En     Mode       Leg Mode
 F3 REX.W AF               REPE SCAS m64                 NP     Valid      N.E.         Find non-RAX quadword starting at [RDI].
 F2 A6                     REPNE CMPS m8, m8             NP     Valid      Valid        Find matching bytes in ES:[(E)DI] and DS:[(E)SI].
 F2 REX.W A6               REPNE CMPS m8, m8             NP     Valid      N.E.         Find matching bytes in [RDI] and [RSI].
 F2 A7                     REPNE CMPS m16, m16           NP     Valid      Valid        Find matching words in ES:[(E)DI] and
                                                                                        DS:[(E)SI].
 F2 A7                     REPNE CMPS m32, m32           NP     Valid      Valid        Find matching doublewords in ES:[(E)DI] and
                                                                                        DS:[(E)SI].
 F2 REX.W A7               REPNE CMPS m64, m64           NP     Valid      N.E.         Find matching doublewords in [RDI] and [RSI].
 F2 AE                     REPNE SCAS m8                 NP     Valid      Valid        Find AL, starting at ES:[(E)DI].
 F2 REX.W AE               REPNE SCAS m8                 NP     Valid      N.E.         Find AL, starting at [RDI].
 F2 AF                     REPNE SCAS m16                NP     Valid      Valid        Find AX, starting at ES:[(E)DI].
 F2 AF                     REPNE SCAS m32                NP     Valid      Valid        Find EAX, starting at ES:[(E)DI].
 F2 REX.W AF               REPNE SCAS m64                NP     Valid      N.E.         Find RAX, starting at [RDI].
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                    Instruction Operand Encoding
  Op/En              Operand 1                      Operand 2                      Operand 3                          Operand 4
   NP                   NA                             NA                             NA                                 NA


Description
Repeats a string instruction the number of times specified in the count register or until the indicated condition of
the ZF flag is no longer met. The REP (repeat), REPE (repeat while equal), REPNE (repeat while not equal), REPZ
(repeat while zero), and REPNZ (repeat while not zero) mnemonics are prefixes that can be added to one of the
string instructions. The REP prefix can be added to the INS, OUTS, MOVS, LODS, and STOS instructions, and the
REPE, REPNE, REPZ, and REPNZ prefixes can be added to the CMPS and SCAS instructions. (The REPZ and REPNZ
prefixes are synonymous forms of the REPE and REPNE prefixes, respectively.) The F3H prefix is defined for the
following instructions and undefined for the rest:
          .     F3H as REP/REPE/REPZ for string and input/output instruction.
          .     F3H is a mandatory prefix for POPCNT, LZCNT, and ADOX.
The REP prefixes apply only to one string instruction at a time. To repeat a block of instructions, use the LOOP
instruction or another looping construct. All of these repeat prefixes cause the associated instruction to be repeated
until the count in register is decremented to 0. See Table 4-17.


                                                    Table 4-17. Repeat Prefixes
 Repeat Prefix                   Termination Condition 1*                     Termination Condition 2
 REP                             RCX or (E)CX = 0                             None
 REPE/REPZ                       RCX or (E)CX = 0                             ZF = 0
 REPNE/REPNZ                     RCX or (E)CX = 0                             ZF = 1
 NOTES:
 * Count register is CX, ECX or RCX by default, depending on attributes of the operating modes.





The REPE, REPNE, REPZ, and REPNZ prefixes also check the state of the ZF flag after each iteration and terminate
the repeat loop if the ZF flag is not in the specified state. When both termination conditions are tested, the cause
of a repeat termination can be determined either by testing the count register with a JECXZ instruction or by
testing the ZF flag (with a JZ, JNZ, or JNE instruction).
When the REPE/REPZ and REPNE/REPNZ prefixes are used, the ZF flag does not require initialization because both
the CMPS and SCAS instructions affect the ZF flag according to the results of the comparisons they make.
A repeating string operation can be suspended by an exception or interrupt. When this happens, the state of the
registers is preserved to allow the string operation to be resumed upon a return from the exception or interrupt
handler. The source and destination registers point to the next string elements to be operated on, the EIP register
points to the string instruction, and the ECX register has the value it held following the last successful iteration of
the instruction. This mechanism allows long string operations to proceed without affecting the interrupt response
time of the system.
When a fault occurs during the execution of a CMPS or SCAS instruction that is prefixed with REPE or REPNE, the
EFLAGS value is restored to the state prior to the execution of the instruction. Since the SCAS and CMPS instruc-
tions do not use EFLAGS as an input, the processor can resume the instruction after the page fault handler.
Use the REP INS and REP OUTS instructions with caution. Not all I/O ports can handle the rate at which these
instructions execute. Note that a REP STOS instruction is the fastest way to initialize a large block of memory.
In 64-bit mode, the operand size of the count register is associated with the address size attribute. Thus the default
count register is RCX; REX.W has no effect on the address size and the count register. In 64-bit mode, if 67H is
used to override address size attribute, the count register is ECX and any implicit source/destination operand will
use the corresponding 32-bit index register. See the summary chart at the beginning of this section for encoding
data and limits.
REP INS may read from the I/O port without writing to the memory location if an exception or VM exit occurs due
to the write (e.g. #PF). If this would be problematic, for example because the I/O port read has side-effects, soft-
ware should ensure the write to the memory location does not cause an exception or VM exit.

Operation
IF AddressSize = 16
    THEN
      Use CX for CountReg;
      Implicit Source/Dest operand for memory use of SI/DI;
    ELSE IF AddressSize = 64
      THEN Use RCX for CountReg;
      Implicit Source/Dest operand for memory use of RSI/RDI;
    ELSE
      Use ECX for CountReg;
      Implicit Source/Dest operand for memory use of ESI/EDI;
FI;
WHILE CountReg != 0
     DO
          Service pending interrupts (if any);
          Execute associated string instruction;
          CountReg <- (CountReg - 1);
          IF CountReg = 0
                THEN exit WHILE loop; FI;
          IF (Repeat prefix is REPZ or REPE) and (ZF = 0)
          or (Repeat prefix is REPNZ or REPNE) and (ZF = 1)
                THEN exit WHILE loop; FI;
     OD;

Flags Affected
None; however, the CMPS and SCAS instructions do set the status flags in the EFLAGS register.




Exceptions (All Operating Modes)
Exceptions may be generated by an instruction associated with the prefix.

64-Bit Mode Exceptions
#GP(0)              If the memory address is in a non-canonical form.






platform: x86_64
mnem: RET
description:
RET/RETN/RETF-Return from Procedure
 Opcode*                    Instruction           Op/     64-Bit   Compat/ Description
                                                  En      Mode     Leg Mode
 C3                         RET                   NP      Valid    Valid       Near return to calling procedure.
 CB                         RET                   NP      Valid    Valid       Far return to calling procedure.
 C2 iw                      RET imm16             I       Valid    Valid       Near return to calling procedure and pop
                                                                               imm16 bytes from stack.
 CA iw                      RET imm16             I       Valid    Valid       Far return to calling procedure and pop imm16
                                                                               bytes from stack.



                                             Instruction Operand Encoding
    Op/En            Operand 1                Operand 2                    Operand 3                      Operand 4
      NP                NA                       NA                           NA                              NA
       I              imm16                      NA                           NA                              NA


Description
Transfers program control to a return address located on the top of the stack. The address is usually placed on the
stack by a CALL instruction, and the return is made to the instruction that follows the CALL instruction.
The optional source operand specifies the number of stack bytes to be released after the return address is popped;
the default is none. This operand can be used to release parameters from the stack that were passed to the called
procedure and are no longer needed. It must be used when the CALL instruction used to switch to a new procedure
uses a call gate with a non-zero word count to access the new procedure. Here, the source operand for the RET
instruction must specify the same number of bytes as is specified in the word count field of the call gate.
The RET instruction can be used to execute three different types of returns:
.     Near return - A return to a calling procedure within the current code segment (the segment currently pointed
      to by the CS register), sometimes referred to as an intrasegment return.
.     Far return - A return to a calling procedure located in a different segment than the current code segment,
      sometimes referred to as an intersegment return.
.     Inter-privilege-level far return - A far return to a different privilege level than that of the currently
      executing program or procedure.
The inter-privilege-level return type can only be executed in protected mode. See the section titled "Calling Proce-
dures Using Call and RET" in Chapter 6 of the Intel 64 and IA-32 Architectures Software Developer's Manual,
Volume 1, for detailed information on near, far, and inter-privilege-level returns.
When executing a near return, the processor pops the return instruction pointer (offset) from the top of the stack
into the EIP register and begins program execution at the new instruction pointer. The CS register is unchanged.
When executing a far return, the processor pops the return instruction pointer from the top of the stack into the EIP
register, then pops the segment selector from the top of the stack into the CS register. The processor then begins
program execution in the new code segment at the new instruction pointer.
The mechanics of an inter-privilege-level far return are similar to an intersegment return, except that the
processor examines the privilege levels and access rights of the code and stack segments being returned to deter-
mine if the control transfer is allowed to be made. The DS, ES, FS, and GS segment registers are cleared by the RET
instruction during an inter-privilege-level return if they refer to segments that are not allowed to be accessed at the
new privilege level. Since a stack switch also occurs on an inter-privilege level return, the ESP and SS registers are
loaded from the stack.
If parameters are passed to the called procedure during an inter-privilege level call, the optional source operand
must be used with the RET instruction to release the parameters on the return. Here, the parameters are released
both from the called procedure's stack and the calling procedure's stack (that is, the stack being returned to).
In 64-bit mode, the default operation size of this instruction is the stack-address size, i.e. 64 bits. This applies to
near returns, not far returns; the default operation size of far returns is 32 bits.



Operation
(* Near return *)
IF instruction = near return
     THEN;
         IF OperandSize = 32
              THEN
                   IF top 4 bytes of stack not within stack limits
                        THEN #SS(0); FI;
                   EIP <- Pop();
              ELSE
                   IF OperandSize = 64
                        THEN
                             IF top 8 bytes of stack not within stack limits
                                  THEN #SS(0); FI;
                             RIP <- Pop();
                        ELSE (* OperandSize = 16 *)
                             IF top 2 bytes of stack not within stack limits
                                  THEN #SS(0); FI;
                             tempEIP <- Pop();
                             tempEIP <- tempEIP AND 0000FFFFH;
                             IF tempEIP not within code segment limits
                                  THEN #GP(0); FI;
                             EIP <- tempEIP;
                   FI;
         FI;

      IF instruction has immediate operand
            THEN (* Release parameters from stack *)
                IF StackAddressSize = 32
                     THEN
                          ESP <- ESP + SRC;
                     ELSE
                          IF StackAddressSize = 64
                               THEN
                                   RSP <- RSP + SRC;
                               ELSE (* StackAddressSize = 16 *)
                                   SP <- SP + SRC;
                          FI;
                FI;
      FI;
FI;

(* Real-address mode or virtual-8086 mode *)
IF ((PE = 0) or (PE = 1 AND VM = 1)) and instruction = far return
     THEN
         IF OperandSize = 32
              THEN
                   IF top 8 bytes of stack not within stack limits
                        THEN #SS(0); FI;
                   EIP <- Pop();
                   CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
              ELSE (* OperandSize = 16 *)
                   IF top 4 bytes of stack not within stack limits
                        THEN #SS(0); FI;



                   tempEIP <- Pop();
                   tempEIP <- tempEIP AND 0000FFFFH;
                   IF tempEIP not within code segment limits
                        THEN #GP(0); FI;
                   EIP <- tempEIP;
                   CS <- Pop(); (* 16-bit pop *)
            FI;
      IF instruction has immediate operand
            THEN (* Release parameters from stack *)
                SP <- SP + (SRC AND FFFFH);
      FI;
FI;

(* Protected mode, not virtual-8086 mode *)
IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 0) and instruction = far return
    THEN
         IF OperandSize = 32
              THEN
                  IF second doubleword on stack is not within stack limits
                       THEN #SS(0); FI;
              ELSE (* OperandSize = 16 *)
                  IF second word on stack is not within stack limits
                       THEN #SS(0); FI;
         FI;
    IF return code segment selector is NULL
         THEN #GP(0); FI;
    IF return code segment selector addresses descriptor beyond descriptor table limit
         THEN #GP(selector); FI;
    Obtain descriptor to which return code segment selector points from descriptor table;
    IF return code segment descriptor is not a code segment
         THEN #GP(selector); FI;
    IF return code segment selector RPL < CPL
         THEN #GP(selector); FI;
    IF return code segment descriptor is conforming
    and return code segment DPL > return code segment selector RPL
         THEN #GP(selector); FI;
    IF return code segment descriptor is non-conforming and return code
    segment DPL != return code segment selector RPL
         THEN #GP(selector); FI;
    IF return code segment descriptor is not present
         THEN #NP(selector); FI:
    IF return code segment selector RPL > CPL
         THEN GOTO RETURN-TO-OUTER-PRIVILEGE-LEVEL;
         ELSE GOTO RETURN-TO-SAME-PRIVILEGE-LEVEL;
    FI;
FI;

RETURN-SAME-PRIVILEGE-LEVEL:
   IF the return instruction pointer is not within the return code segment limit
        THEN #GP(0); FI;
   IF OperandSize = 32
        THEN
             EIP <- Pop();
             CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)



        ELSE (* OperandSize = 16 *)
            EIP <- Pop();
            EIP <- EIP AND 0000FFFFH;
            CS <- Pop(); (* 16-bit pop *)
   FI;
   IF instruction has immediate operand
         THEN (* Release parameters from stack *)
             IF StackAddressSize = 32
                  THEN
                       ESP <- ESP + SRC;
                  ELSE (* StackAddressSize = 16 *)
                       SP <- SP + SRC;
             FI;
   FI;

RETURN-TO-OUTER-PRIVILEGE-LEVEL:
   IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
   or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
             THEN #SS(0); FI;
   Read return segment selector;
   IF stack segment selector is NULL
        THEN #GP(0); FI;
   IF return stack segment selector index is not within its descriptor table limits
        THEN #GP(selector); FI;
   Read segment descriptor pointed to by return segment selector;
   IF stack segment selector RPL != RPL of the return code segment selector
   or stack segment is not a writable data segment
   or stack segment descriptor DPL != RPL of the return code segment selector
             THEN #GP(selector); FI;
   IF stack segment not present
        THEN #SS(StackSegmentSelector); FI;
   IF the return instruction pointer is not within the return code segment limit
        THEN #GP(0); FI;
   CPL <- ReturnCodeSegmentSelector(RPL);
   IF OperandSize = 32
        THEN
             EIP <- Pop();
             CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; segment descriptor loaded *)
             CS(RPL) <- CPL;
             IF instruction has immediate operand
                   THEN (* Release parameters from called procedure's stack *)
                       IF StackAddressSize = 32
                            THEN
                                 ESP <- ESP + SRC;
                            ELSE (* StackAddressSize = 16 *)
                                 SP <- SP + SRC;
                       FI;
             FI;
             tempESP <- Pop();
             tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded; seg. descriptor loaded *)
             ESP <- tempESP;
             SS <- tempSS;
        ELSE (* OperandSize = 16 *)
             EIP <- Pop();



             EIP <- EIP AND 0000FFFFH;
             CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
             CS(RPL) <- CPL;
             IF instruction has immediate operand
                   THEN (* Release parameters from called procedure's stack *)
                       IF StackAddressSize = 32
                            THEN
                                 ESP <- ESP + SRC;
                            ELSE (* StackAddressSize = 16 *)
                                 SP <- SP + SRC;
                       FI;
             FI;
             tempESP <- Pop();
             tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
             ESP <- tempESP;
             SS <- tempSS;
   FI;

   FOR each of segment register (ES, FS, GS, and DS)
       DO
           IF segment register points to data or non-conforming code segment
           and CPL > segment descriptor DPL (* DPL in hidden part of segment register *)
                THEN SegmentSelector <- 0; (* Segment selector invalid *)
           FI;
       OD;

   IF instruction has immediate operand
         THEN (* Release parameters from calling procedure's stack *)
             IF StackAddressSize = 32
                  THEN
                       ESP <- ESP + SRC;
                  ELSE (* StackAddressSize = 16 *)
                       SP <- SP + SRC;
             FI;
   FI;

(* IA-32e Mode *)
    IF (PE = 1 and VM = 0 and IA32_EFER.LMA = 1) and instruction = far return
         THEN
              IF OperandSize = 32
                   THEN
                       IF second doubleword on stack is not within stack limits
                             THEN #SS(0); FI;
                       IF first or second doubleword on stack is not in canonical space
                             THEN #SS(0); FI;
                   ELSE
                       IF OperandSize = 16
                             THEN
                                  IF second word on stack is not within stack limits
                                        THEN #SS(0); FI;
                                  IF first or second word on stack is not in canonical space
                                        THEN #SS(0); FI;
                             ELSE (* OperandSize = 64 *)
                                  IF first or second quadword on stack is not in canonical space



                                     THEN #SS(0); FI;
                       FI
              FI;
         IF return code segment selector is NULL
              THEN GP(0); FI;
         IF return code segment selector addresses descriptor beyond descriptor table limit
              THEN GP(selector); FI;
         IF return code segment selector addresses descriptor in non-canonical space
              THEN GP(selector); FI;
         Obtain descriptor to which return code segment selector points from descriptor table;
         IF return code segment descriptor is not a code segment
              THEN #GP(selector); FI;
         IF return code segment descriptor has L-bit = 1 and D-bit = 1
              THEN #GP(selector); FI;
         IF return code segment selector RPL < CPL
              THEN #GP(selector); FI;
         IF return code segment descriptor is conforming
         and return code segment DPL > return code segment selector RPL
              THEN #GP(selector); FI;
         IF return code segment descriptor is non-conforming
         and return code segment DPL != return code segment selector RPL
              THEN #GP(selector); FI;
         IF return code segment descriptor is not present
              THEN #NP(selector); FI:
         IF return code segment selector RPL > CPL
              THEN GOTO IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL;
              ELSE GOTO IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL;
         FI;
   FI;

IA-32E-MODE-RETURN-SAME-PRIVILEGE-LEVEL:
IF the return instruction pointer is not within the return code segment limit
     THEN #GP(0); FI;
IF the return instruction pointer is not within canonical address space
     THEN #GP(0); FI;
IF OperandSize = 32
     THEN
         EIP <- Pop();
         CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded *)
     ELSE
         IF OperandSize = 16
              THEN
                   EIP <- Pop();
                   EIP <- EIP AND 0000FFFFH;
                   CS <- Pop(); (* 16-bit pop *)
              ELSE (* OperandSize = 64 *)
                   RIP <- Pop();
                   CS <- Pop(); (* 64-bit pop, high-order 48 bits discarded *)
         FI;
FI;
IF instruction has immediate operand
     THEN (* Release parameters from stack *)
         IF StackAddressSize = 32
              THEN



                  ESP <- ESP + SRC;
              ELSE
                  IF StackAddressSize = 16
                       THEN
                           SP <- SP + SRC;
                       ELSE (* StackAddressSize = 64 *)
                           RSP <- RSP + SRC;
                  FI;
        FI;
FI;

IA-32E-MODE-RETURN-TO-OUTER-PRIVILEGE-LEVEL:
IF top (16 + SRC) bytes of stack are not within stack limits (OperandSize = 32)
or top (8 + SRC) bytes of stack are not within stack limits (OperandSize = 16)
    THEN #SS(0); FI;
IF top (16 + SRC) bytes of stack are not in canonical address space (OperandSize = 32)
or top (8 + SRC) bytes of stack are not in canonical address space (OperandSize = 16)
or top (32 + SRC) bytes of stack are not in canonical address space (OperandSize = 64)
    THEN #SS(0); FI;
Read return stack segment selector;
IF stack segment selector is NULL
    THEN
         IF new CS descriptor L-bit = 0
               THEN #GP(selector);
         IF stack segment selector RPL = 3
               THEN #GP(selector);
FI;
IF return stack segment descriptor is not within descriptor table limits
         THEN #GP(selector); FI;
IF return stack segment descriptor is in non-canonical address space
         THEN #GP(selector); FI;
Read segment descriptor pointed to by return segment selector;
IF stack segment selector RPL != RPL of the return code segment selector
or stack segment is not a writable data segment
or stack segment descriptor DPL != RPL of the return code segment selector
    THEN #GP(selector); FI;
IF stack segment not present
    THEN #SS(StackSegmentSelector); FI;
IF the return instruction pointer is not within the return code segment limit
    THEN #GP(0); FI:
IF the return instruction pointer is not within canonical address space
    THEN #GP(0); FI;
CPL <- ReturnCodeSegmentSelector(RPL);
IF OperandSize = 32
    THEN
         EIP <- Pop();
         CS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
         CS(RPL) <- CPL;
         IF instruction has immediate operand
               THEN (* Release parameters from called procedure's stack *)
                   IF StackAddressSize = 32
                        THEN
                             ESP <- ESP + SRC;
                        ELSE



                             IF StackAddressSize = 16
                                  THEN
                                      SP <- SP + SRC;
                                  ELSE (* StackAddressSize = 64 *)
                                      RSP <- RSP + SRC;
                             FI;
                   FI;
          FI;
          tempESP <- Pop();
          tempSS <- Pop(); (* 32-bit pop, high-order 16 bits discarded, segment descriptor loaded *)
          ESP <- tempESP;
          SS <- tempSS;
      ELSE
          IF OperandSize = 16
               THEN
                   EIP <- Pop();
                   EIP <- EIP AND 0000FFFFH;
                   CS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
                   CS(RPL) <- CPL;
                   IF instruction has immediate operand
                         THEN (* Release parameters from called procedure's stack *)
                             IF StackAddressSize = 32
                                  THEN
                                       ESP <- ESP + SRC;
                                  ELSE
                                       IF StackAddressSize = 16
                                            THEN
                                                SP <- SP + SRC;
                                            ELSE (* StackAddressSize = 64 *)
                                                RSP <- RSP + SRC;
                                       FI;
                             FI;
                   FI;
                   tempESP <- Pop();
                   tempSS <- Pop(); (* 16-bit pop; segment descriptor loaded *)
                   ESP <- tempESP;
                   SS <- tempSS;
               ELSE (* OperandSize = 64 *)
                   RIP <- Pop();
                   CS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. descriptor loaded *)
                   CS(RPL) <- CPL;
                   IF instruction has immediate operand
                         THEN (* Release parameters from called procedure's stack *)
                             RSP <- RSP + SRC;
                   FI;
                   tempESP <- Pop();
                   tempSS <- Pop(); (* 64-bit pop; high-order 48 bits discarded; seg. desc. loaded *)
                   ESP <- tempESP;
                   SS <- tempSS;
          FI;
FI;

FOR each of segment register (ES, FS, GS, and DS)
   DO



         IF segment register points to data or non-conforming code segment
         and CPL > segment descriptor DPL; (* DPL in hidden part of segment register *)
              THEN SegmentSelector <- 0; (* SegmentSelector invalid *)
         FI;
   OD;

IF instruction has immediate operand
     THEN (* Release parameters from calling procedure's stack *)
         IF StackAddressSize = 32
              THEN
                   ESP <- ESP + SRC;
              ELSE
                   IF StackAddressSize = 16
                        THEN
                            SP <- SP + SRC;
                        ELSE (* StackAddressSize = 64 *)
                            RSP <- RSP + SRC;
                   FI;
         FI;
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)                  If the return code or stack segment selector NULL.
                        If the return instruction pointer is not within the return code segment limit
#GP(selector)           If the RPL of the return code segment selector is less then the CPL.
                        If the return code or stack segment selector index is not within its descriptor table limits.
                        If the return code segment descriptor does not indicate a code segment.
                        If the return code segment is non-conforming and the segment selector's DPL is not equal to
                        the RPL of the code segment's segment selector
                        If the return code segment is conforming and the segment selector's DPL greater than the RPL
                        of the code segment's segment selector
                        If the stack segment is not a writable data segment.
                        If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
                        If the stack segment descriptor DPL is not equal to the RPL of the return code segment
                        selector.
#SS(0)                  If the top bytes of stack are not within stack limits.
                        If the return stack segment is not present.
#NP(selector)           If the return code segment is not present.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If an unaligned memory access occurs when the CPL is 3 and alignment checking is enabled.

Real-Address Mode Exceptions
#GP                     If the return instruction pointer is not within the return code segment limit
#SS                     If the top bytes of stack are not within stack limits.

Virtual-8086 Mode Exceptions
#GP(0)                  If the return instruction pointer is not within the return code segment limit



#SS(0)              If the top bytes of stack are not within stack limits.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If an unaligned memory access occurs when alignment checking is enabled.

Compatibility Mode Exceptions
Same as 64-bit mode exceptions.

64-Bit Mode Exceptions
#GP(0)              If the return instruction pointer is non-canonical.
                    If the return instruction pointer is not within the return code segment limit.
                    If the stack segment selector is NULL going back to compatibility mode.
                    If the stack segment selector is NULL going back to CPL3 64-bit mode.
                    If a NULL stack segment selector RPL is not equal to CPL going back to non-CPL3 64-bit mode.
                    If the return code segment selector is NULL.
#GP(selector)       If the proposed segment descriptor for a code segment does not indicate it is a code segment.
                    If the proposed new code segment descriptor has both the D-bit and L-bit set.
                    If the DPL for a nonconforming-code segment is not equal to the RPL of the code segment
                    selector.
                    If CPL is greater than the RPL of the code segment selector.
                    If the DPL of a conforming-code segment is greater than the return code segment selector
                    RPL.
                    If a segment selector index is outside its descriptor table limits.
                    If a segment descriptor memory address is non-canonical.
                    If the stack segment is not a writable data segment.
                    If the stack segment descriptor DPL is not equal to the RPL of the return code segment
                    selector.
                    If the stack segment selector RPL is not equal to the RPL of the return code segment selector.
#SS(0)              If an attempt to pop a value off the stack violates the SS limit.
                    If an attempt to pop a value off the stack causes a non-canonical address to be referenced.
#NP(selector)       If the return code or stack segment is not present.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.






platform: x86_64
mnem: RORX
description:
RORX - Rotate Right Logical Without Affecting Flags
 Opcode/                               Op/     64/32       CPUID        Description
 Instruction                           En      -bit        Feature
                                               Mode        Flag
 VEX.LZ.F2.0F3A.W0 F0 /r ib            RMI     V/V         BMI2         Rotate 32-bit r/m32 right imm8 times without affecting arithmetic
 RORX r32, r/m32, imm8                                                  flags.
 VEX.LZ.F2.0F3A.W1 F0 /r ib            RMI     V/N.E.      BMI2         Rotate 64-bit r/m64 right imm8 times without affecting arithmetic
 RORX r64, r/m64, imm8                                                  flags.



                                                        Instruction Operand Encoding
   Op/En              Operand 1                          Operand 2                      Operand 3                      Operand 4
    RMI             ModRM:reg (w)                       ModRM:r/m (r)                      Imm8                           NA


Description
Rotates the bits of second operand right by the count value specified in imm8 without affecting arithmetic flags.
The RORX instruction does not read or write the arithmetic flags.
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.

Operation
IF (OperandSize = 32)
    y <- imm8 AND 1FH;
    DEST <- (SRC >> y) | (SRC << (32-y));
ELSEIF (OperandSize = 64 )
    y <- imm8 AND 3FH;
    DEST <- (SRC >> y) | (SRC << (64-y));
ENDIF

Flags Affected
None

Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.

SIMD Floating-Point Exceptions
None

Other Exceptions
See Section 2.5.1, "Exception Conditions for VEX-Encoded GPR Instructions", Table 2-29; additionally
#UD                       If VEX.W = 1.






platform: x86_64
mnem: ROUNDPD
description:
ROUNDPD - Round Packed Double Precision Floating-Point Values
 Opcode*/                                       Op/     64/32 bit   CPUID       Description
 Instruction                                    En      Mode        Feature
                                                        Support     Flag
 66 0F 3A 09 /r ib                              RMI     V/V         SSE4_1      Round packed double precision floating-point
 ROUNDPD xmm1, xmm2/m128, imm8                                                  values in xmm2/m128 and place the result in
                                                                                xmm1. The rounding mode is determined by
                                                                                imm8.
 VEX.128.66.0F3A.WIG 09 /r ib                   RMI     V/V         AVX         Round packed double-precision floating-point
 VROUNDPD xmm1, xmm2/m128, imm8                                                 values in xmm2/m128 and place the result in
                                                                                xmm1. The rounding mode is determined by
                                                                                imm8.
 VEX.256.66.0F3A.WIG 09 /r ib                   RMI     V/V         AVX         Round packed double-precision floating-point
 VROUNDPD ymm1, ymm2/m256, imm8                                                 values in ymm2/m256 and place the result in
                                                                                ymm1. The rounding mode is determined by
                                                                                imm8.



                                           Instruction Operand Encoding
   Op/En          Operand 1                 Operand 2                      Operand 3                       Operand 4
    RMI         ModRM:reg (w)             ModRM:r/m (r)                       imm8                             NA


Description
Round the 2 double-precision floating-point values in the source operand (second operand) using the rounding
mode specified in the immediate operand (third operand) and place the results in the destination operand (first
operand). The rounding process rounds each input floating-point value to an integer value and returns the integer
result as a double-precision floating-point value.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-
tion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM
register destination are unmodified.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-
tion operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





                                 8                                                                 3 2 1 0

                                                             Reserved



                                     P - Precision Mask; 0: normal, 1: inexact
                                     RS - Rounding select; 1: MXCSR.RC, 0: Imm8.RC
                                     RC - Rounding mode


                         Figure 4-24. Bit Control Fields of Immediate Byte for ROUNDxx Instruction


                         Table 4-18. Rounding Modes and Encoding of Rounding Control (RC) Field
 Rounding          RC Field   Description
 Mode              Setting
 Round to          00B        Rounded result is the closest to the infinitely precise result. If two values are equally close, the result is
 nearest (even)               the even value (i.e., the integer value with the least-significant bit of zero).
 Round down        01B        Rounded result is closest to but no greater than the infinitely precise result.
 (toward -inf)
 Round up          10B        Rounded result is closest to but no less than the infinitely precise result.
 (toward +inf)
 Round toward 11B             Rounded result is closest to but no greater in absolute value than the infinitely precise result.
 zero (Truncate)

Operation
IF (imm[2] = '1)
     THEN     // rounding mode is determined by MXCSR.RC
         DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);
         DEST[127:64] <- ConvertDPFPToInteger_M(SRC[127:64]);
     ELSE     // rounding mode is determined by IMM8.RC
         DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);
         DEST[127:64] <- ConvertDPFPToInteger_Imm(SRC[127:64]);
FI

ROUNDPD (128-bit Legacy SSE version)
DEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)

VROUNDPD (VEX.128 encoded version)
DEST[63:0] <- RoundToInteger(SRC[63:0]], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[VLMAX-1:128] <- 0

VROUNDPD (VEX.256 encoded version)
DEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[127:64] <- RoundToInteger(SRC[127:64]], ROUND_CONTROL)
DEST[191:128] <- RoundToInteger(SRC[191:128]], ROUND_CONTROL)
DEST[255:192] <- RoundToInteger(SRC[255:192] ], ROUND_CONTROL)





Intel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_pd(__m128d s1, int iRoundMode);
__m128 _mm_floor_pd(__m128d s1);
__m128 _mm_ceil_pd(__m128d s1)
__m256 _mm256_round_pd(__m256d s1, int iRoundMode);
__m256 _mm256_floor_pd(__m256d s1);
__m256 _mm256_ceil_pd(__m256d s1)

SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-
sion exception is not signaled.)
Note that Denormal is not signaled by ROUNDPD.

Other Exceptions
See Exceptions Type 2; additionally
#UD                 If VEX.vvvv != 1111B.






platform: x86_64
mnem: ROUNDPS
description:
ROUNDPS - Round Packed Single Precision Floating-Point Values
Opcode*/                                                   Op/    64/32 bit   CPUID       Description
Instruction                                                En     Mode        Feature
                                                                  Support     Flag
66 0F 3A 08                                                RMI    V/V         SSE4_1      Round packed single precision floating-point
/r ib                                                                                     values in xmm2/m128 and place the result in
ROUNDPS xmm1, xmm2/m128, imm8                                                             xmm1. The rounding mode is determined by
                                                                                          imm8.
VEX.128.66.0F3A.WIG 08 /r ib                               RMI    V/V         AVX         Round packed single-precision floating-point
VROUNDPS xmm1, xmm2/m128, imm8                                                            values in xmm2/m128 and place the result in
                                                                                          xmm1. The rounding mode is determined by
                                                                                          imm8.
VEX.256.66.0F3A.WIG 08 /r ib                               RMI    V/V         AVX         Round packed single-precision floating-point
VROUNDPS ymm1, ymm2/m256, imm8                                                            values in ymm2/m256 and place the result in
                                                                                          ymm1. The rounding mode is determined by
                                                                                          imm8.



                                                    Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                     Operand 3                     Operand 4
    RMI             ModRM:reg (w)                   ModRM:r/m (r)                       imm8                          NA


Description
Round the 4 single-precision floating-point values in the source operand (second operand) using the rounding
mode specified in the immediate operand (third operand) and place the results in the destination operand (first
operand). The rounding process rounds each input floating-point value to an integer value and returns the integer
result as a single-precision floating-point value.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The second source can be an XMM register or 128-bit memory location. The destina-
tion is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM
register destination are unmodified.
VEX.128 encoded version: the source operand second source operand or a 128-bit memory location. The destina-
tion operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The source operand is a YMM register or a 256-bit memory location. The destination
operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.





Operation
IF (imm[2] = '1)
     THEN     // rounding mode is determined by MXCSR.RC
         DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);
         DEST[63:32] <- ConvertSPFPToInteger_M(SRC[63:32]);
         DEST[95:64] <- ConvertSPFPToInteger_M(SRC[95:64]);
         DEST[127:96] <- ConvertSPFPToInteger_M(SRC[127:96]);
     ELSE     // rounding mode is determined by IMM8.RC
         DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);
         DEST[63:32] <- ConvertSPFPToInteger_Imm(SRC[63:32]);
         DEST[95:64] <- ConvertSPFPToInteger_Imm(SRC[95:64]);
         DEST[127:96] <- ConvertSPFPToInteger_Imm(SRC[127:96]);
FI;

ROUNDPS(128-bit Legacy SSE version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] (Unmodified)

VROUNDPS (VEX.128 encoded version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[VLMAX-1:128] <- 0

VROUNDPS (VEX.256 encoded version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[63:32] <- RoundToInteger(SRC[63:32], ROUND_CONTROL)
DEST[95:64] <- RoundToInteger(SRC[95:64]], ROUND_CONTROL)
DEST[127:96] <- RoundToInteger(SRC[127:96]], ROUND_CONTROL)
DEST[159:128] <- RoundToInteger(SRC[159:128]], ROUND_CONTROL)
DEST[191:160] <- RoundToInteger(SRC[191:160]], ROUND_CONTROL)
DEST[223:192] <- RoundToInteger(SRC[223:192] ], ROUND_CONTROL)
DEST[255:224] <- RoundToInteger(SRC[255:224] ], ROUND_CONTROL)

Intel C/C++ Compiler Intrinsic Equivalent
__m128 _mm_round_ps(__m128 s1, int iRoundMode);
__m128 _mm_floor_ps(__m128 s1);
__m128 _mm_ceil_ps(__m128 s1)
__m256 _mm256_round_ps(__m256 s1, int iRoundMode);
__m256 _mm256_floor_ps(__m256 s1);
__m256 _mm256_ceil_ps(__m256 s1)





SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-
sion exception is not signaled.)
Note that Denormal is not signaled by ROUNDPS.

Other Exceptions
See Exceptions Type 2; additionally
#UD                      If VEX.vvvv != 1111B.






platform: x86_64
mnem: ROUNDSD
description:
ROUNDSD - Round Scalar Double Precision Floating-Point Values
 Opcode*/                                         Op/    64/32 bit   CPUID        Description
 Instruction                                      En     Mode        Feature
                                                         Support     Flag
 66 0F 3A 0B /r ib                                RMI    V/V         SSE4_1       Round the low packed double precision
 ROUNDSD xmm1, xmm2/m64, imm8                                                     floating-point value in xmm2/m64 and place
                                                                                  the result in xmm1. The rounding mode is
                                                                                  determined by imm8.
 VEX.NDS.LIG.66.0F3A.WIG 0B /r ib                 RVMI V/V           AVX          Round the low packed double precision
 VROUNDSD xmm1, xmm2, xmm3/m64, imm8                                              floating-point value in xmm3/m64 and place
                                                                                  the result in xmm1. The rounding mode is
                                                                                  determined by imm8. Upper packed double
                                                                                  precision floating-point value (bits[127:64])
                                                                                  from xmm2 is copied to xmm1[127:64].



                                             Instruction Operand Encoding
   Op/En            Operand 1                  Operand 2                       Operand 3                     Operand 4
    RMI           ModRM:reg (w)               ModRM:r/m (r)                      imm8                            NA
    RVMI          ModRM:reg (w)                VEX.vvvv (r)                ModRM:r/m (r)                       imm8


Description
Round the DP FP value in the lower qword of the source operand (second operand) using the rounding mode spec-
ified in the immediate operand (third operand) and place the result in the destination operand (first operand). The
rounding process rounds a double-precision floating-point input to an integer value and returns the integer result
as a double precision floating-point value in the lowest position. The upper double precision floating-point value in
the destination is retained.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-
1:64) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation
IF (imm[2] = '1)
     THEN     // rounding mode is determined by MXCSR.RC
         DEST[63:0] <- ConvertDPFPToInteger_M(SRC[63:0]);
     ELSE     // rounding mode is determined by IMM8.RC
         DEST[63:0] <- ConvertDPFPToInteger_Imm(SRC[63:0]);
FI;
DEST[127:63] remains unchanged ;

ROUNDSD (128-bit Legacy SSE version)
DEST[63:0] <- RoundToInteger(SRC[63:0], ROUND_CONTROL)
DEST[VLMAX-1:64] (Unmodified)





VROUNDSD (VEX.128 encoded version)
DEST[63:0] <- RoundToInteger(SRC2[63:0], ROUND_CONTROL)
DEST[127:64] <- SRC1[127:64]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
ROUNDSD:         __m128d mm_round_sd(__m128d dst, __m128d s1, int iRoundMode);
                 __m128d mm_floor_sd(__m128d dst, __m128d s1);
                 __m128d mm_ceil_sd(__m128d dst, __m128d s1);

SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-
sion exception is not signaled.)
Note that Denormal is not signaled by ROUNDSD.

Other Exceptions
See Exceptions Type 3.






platform: x86_64
mnem: ROUNDSS
description:
ROUNDSS - Round Scalar Single Precision Floating-Point Values
 Opcode*/                                         Op/       64/32 bit   CPUID       Description
 Instruction                                      En        Mode        Feature
                                                            Support     Flag
 66 0F 3A 0A /r ib                                RMI       V/V         SSE4_1      Round the low packed single precision
 ROUNDSS xmm1, xmm2/m32, imm8                                                       floating-point value in xmm2/m32 and place
                                                                                    the result in xmm1. The rounding mode is
                                                                                    determined by imm8.
 VEX.NDS.LIG.66.0F3A.WIG 0A /r ib                 RVMI V/V              AVX         Round the low packed single precision
 VROUNDSS xmm1, xmm2, xmm3/m32, imm8                                                floating-point value in xmm3/m32 and place
                                                                                    the result in xmm1. The rounding mode is
                                                                                    determined by imm8. Also, upper packed
                                                                                    single precision floating-point values
                                                                                    (bits[127:32]) from xmm2 are copied to
                                                                                    xmm1[127:32].



                                             Instruction Operand Encoding
  Op/En            Operand 1                  Operand 2                       Operand 3                        Operand 4
   RMI           ModRM:reg (w)              ModRM:r/m (r)                         imm8                             NA
   RVMI          ModRM:reg (w)               VEX.vvvv (r)                  ModRM:r/m (r)                          imm8


Description
Round the single-precision floating-point value in the lowest dword of the source operand (second operand) using
the rounding mode specified in the immediate operand (third operand) and place the result in the destination
operand (first operand). The rounding process rounds a single-precision floating-point input to an integer value and
returns the result as a single-precision floating-point value in the lowest position. The upper three single-precision
floating-point values in the destination are retained.
The immediate operand specifies control fields for the rounding operation, three bit fields are defined and shown in
Figure 4-24. Bit 3 of the immediate byte controls processor behavior for a precision exception, bit 2 selects the
source of rounding mode control. Bits 1:0 specify a non-sticky rounding-mode value (Table 4-18 lists the encoded
values for rounding-mode field).
The Precision Floating-Point Exception is signaled according to the immediate operand. If any source operand is an
SNaN then it will be converted to a QNaN. If DAZ is set to '1 then denormals will be converted to zero before
rounding.
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation
IF (imm[2] = '1)
     THEN     // rounding mode is determined by MXCSR.RC
         DEST[31:0] <- ConvertSPFPToInteger_M(SRC[31:0]);
     ELSE     // rounding mode is determined by IMM8.RC
         DEST[31:0] <- ConvertSPFPToInteger_Imm(SRC[31:0]);
FI;
DEST[127:32] remains unchanged ;

ROUNDSS (128-bit Legacy SSE version)
DEST[31:0] <- RoundToInteger(SRC[31:0], ROUND_CONTROL)
DEST[VLMAX-1:32] (Unmodified)




VROUNDSS (VEX.128 encoded version)
DEST[31:0] <- RoundToInteger(SRC2[31:0], ROUND_CONTROL)
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0

Intel C/C++ Compiler Intrinsic Equivalent
ROUNDSS:         __m128 mm_round_ss(__m128 dst, __m128 s1, int iRoundMode);
                 __m128 mm_floor_ss(__m128 dst, __m128 s1);
                 __m128 mm_ceil_ss(__m128 dst, __m128 s1);

SIMD Floating-Point Exceptions
Invalid (signaled only if SRC = SNaN)
Precision (signaled only if imm[3] = '0; if imm[3] = '1, then the Precision Mask in the MXSCSR is ignored and preci-
sion exception is not signaled.)
Note that Denormal is not signaled by ROUNDSS.

Other Exceptions
See Exceptions Type 3.






platform: x86_64
mnem: RSM
description:
RSM-Resume from System Management Mode
 Opcode*                  Instruction                 Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 0F AA                    RSM                         NP    Valid    Valid      Resume operation of interrupted program.



                                              Instruction Operand Encoding
    Op/En             Operand 1                 Operand 2                    Operand 3                  Operand 4
       NP                NA                           NA                        NA                          NA


Description
Returns program control from system management mode (SMM) to the application program or operating-system
procedure that was interrupted when the processor received an SMM interrupt. The processor's state is restored
from the dump created upon entering SMM. If the processor detects invalid state information during state restora-
tion, it enters the shutdown state. The following invalid information can cause a shutdown:
.      Any reserved bit of CR4 is set to 1.
.      Any illegal combination of bits in CR0, such as (PG=1 and PE=0) or (NW=1 and CD=0).
.      (Intel Pentium and Intel486 processors only.) The value stored in the state dump base field is not a 32-KByte
       aligned address.
The contents of the model-specific registers are not affected by a return from SMM.
The SMM state map used by RSM supports resuming processor context for non-64-bit modes and 64-bit mode.
See Chapter 34, "System Management Mode," in the Intel 64 and IA-32 Architectures Software Developer's
Manual, Volume 3C, for more information about SMM and the behavior of the RSM instruction.

Operation
ReturnFromSMM;
IF (IA-32e mode supported) or (CPUID DisplayFamily_DisplayModel = 06H_0CH )
     THEN
          ProcessorState <- Restore(SMMDump(IA-32e SMM STATE MAP));
     Else
          ProcessorState <- Restore(SMMDump(Non-32-Bit-Mode SMM STATE MAP));
FI

Flags Affected
All.

Protected Mode Exceptions
#UD                     If an attempt is made to execute this instruction when the processor is not in SMM.
                        If the LOCK prefix is used.

Real-Address Mode Exceptions
Same exceptions as in protected mode.

Virtual-8086 Mode Exceptions
Same exceptions as in protected mode.

Compatibility Mode Exceptions
Same exceptions as in protected mode.




64-Bit Mode Exceptions
Same exceptions as in protected mode.






platform: x86_64
mnem: RSQRTPS
description:
RSQRTPS-Compute Reciprocals of Square Roots of Packed Single-Precision Floating-Point
Values
Opcode*/                                          Op/    64/32 bit    CPUID        Description
Instruction                                       En     Mode         Feature
                                                         Support      Flag
0F 52 /r                                          RM     V/V          SSE          Computes the approximate reciprocals of the
RSQRTPS xmm1, xmm2/m128                                                            square roots of the packed single-precision
                                                                                   floating-point values in xmm2/m128 and
                                                                                   stores the results in xmm1.
VEX.128.0F.WIG 52 /r                              RM     V/V          AVX          Computes the approximate reciprocals of the
VRSQRTPS xmm1, xmm2/m128                                                           square roots of packed single-precision values
                                                                                   in xmm2/mem and stores the results in xmm1.
VEX.256.0F.WIG 52 /r                              RM     V/V          AVX          Computes the approximate reciprocals of the
VRSQRTPS ymm1, ymm2/m256                                                           square roots of packed single-precision values
                                                                                   in ymm2/mem and stores the results in ymm1.



                                            Instruction Operand Encoding
   Op/En               Operand 1                Operand 2                      Operand 3                       Operand 4
    RM              ModRM:reg (w)            ModRM:r/m (r)                         NA                              NA


Description
Performs a SIMD computation of the approximate reciprocals of the square roots of the four packed single-preci-
sion floating-point values in the source operand (second operand) and stores the packed single-precision floating-
point results in the destination operand. The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Figure 10-5 in the Intel 64 and IA-32 Architectures Software
Developer's Manual, Volume 1, for an illustration of a SIMD single-precision floating-point operation.
The relative error for this approximation is:

   |Relative Error| <= 1.5 * 2-12
The RSQRTPS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is
a 0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than -0.0), a floating-point indefinite is returned. When a
source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding
YMM register destination are unmodified.
VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination
operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are
zeroed.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register.
Note: In VEX-encoded versions, VEX.vvvv is reserved and must be 1111b, otherwise instructions will #UD.





Operation
RSQRTPS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] (Unmodified)

VRSQRTPS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[VLMAX-1:128] <- 0

VRSQRTPS (VEX.256 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC[31:0]))
DEST[63:32] <- APPROXIMATE(1/SQRT(SRC1[63:32]))
DEST[95:64] <- APPROXIMATE(1/SQRT(SRC1[95:64]))
DEST[127:96] <- APPROXIMATE(1/SQRT(SRC2[127:96]))
DEST[159:128] <- APPROXIMATE(1/SQRT(SRC2[159:128]))
DEST[191:160] <- APPROXIMATE(1/SQRT(SRC2[191:160]))
DEST[223:192] <- APPROXIMATE(1/SQRT(SRC2[223:192]))
DEST[255:224] <- APPROXIMATE(1/SQRT(SRC2[255:224]))

Intel C/C++ Compiler Intrinsic Equivalent
RSQRTPS:        __m128 _mm_rsqrt_ps(__m128 a)
RSQRTPS:        __m256 _mm256_rsqrt_ps (__m256 a);

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 4; additionally
#UD                      If VEX.vvvv != 1111B.






platform: x86_64
mnem: RSQRTSS
description:
RSQRTSS-Compute Reciprocal of Square Root of Scalar Single-Precision Floating-Point Value
 Opcode*/                                           Op/     64/32 bit    CPUID        Description
 Instruction                                        En      Mode         Feature
                                                            Support      Flag
 F3 0F 52 /r                                        RM      V/V          SSE          Computes the approximate reciprocal of the
 RSQRTSS xmm1, xmm2/m32                                                               square root of the low single-precision
                                                                                      floating-point value in xmm2/m32 and stores
                                                                                      the results in xmm1.
 VEX.NDS.LIG.F3.0F.WIG 52 /r                        RVM V/V              AVX          Computes the approximate reciprocal of the
 VRSQRTSS xmm1, xmm2, xmm3/m32                                                        square root of the low single precision
                                                                                      floating-point value in xmm3/m32 and stores
                                                                                      the results in xmm1. Also, upper single
                                                                                      precision floating-point values (bits[127:32])
                                                                                      from xmm2 are copied to xmm1[127:32].



                                           Instruction Operand Encoding
   Op/En               Operand 1                Operand 2                       Operand 3                         Operand 4
     RM             ModRM:reg (w)           ModRM:r/m (r)                           NA                                NA
    RVM             ModRM:reg (w)           VEX.vvvv (r)                       ModRM:r/m (r)                          NA


Description
Computes an approximate reciprocal of the square root of the low single-precision floating-point value in the
source operand (second operand) stores the single-precision floating-point result in the destination operand. The
source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register.
The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the Intel 64
and IA-32 Architectures Software Developer's Manual, Volume 1, for an illustration of a scalar single-precision
floating-point operation.
The relative error for this approximation is:

   |Relative Error| <= 1.5 * 2-12
The RSQRTSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is
a 0.0, an inf of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same
sign). When a source value is a negative value (other than -0.0), a floating-point indefinite is returned. When a
source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers
(XMM8-XMM15).
128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-
1:32) of the corresponding YMM destination register remain unchanged.
VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.

Operation
RSQRTSS (128-bit Legacy SSE version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[VLMAX-1:32] (Unmodified)

VRSQRTSS (VEX.128 encoded version)
DEST[31:0] <- APPROXIMATE(1/SQRT(SRC2[31:0]))
DEST[127:32] <- SRC1[127:32]
DEST[VLMAX-1:128] <- 0





Intel C/C++ Compiler Intrinsic Equivalent
RSQRTSS:        __m128 _mm_rsqrt_ss(__m128 a)

SIMD Floating-Point Exceptions
None.

Other Exceptions
See Exceptions Type 5.






platform: x86_64
mnem: SAHF
description:
SAHF-Store AH into Flags
 Opcode*                    Instruction                    Op/    64-Bit     Compat/ Description
                                                           En     Mode       Leg Mode
 9E                         SAHF                           NP     Invalid*   Valid       Loads SF, ZF, AF, PF, and CF from AH into
                                                                                         EFLAGS register.
 NOTES:
 * Valid in specific steppings. See Description section.



                                                    Instruction Operand Encoding
   Op/En              Operand 1                       Operand 2                      Operand 3                     Operand 4
      NP                  NA                               NA                           NA                             NA


Description
Loads the SF, ZF, AF, PF, and CF flags of the EFLAGS register with values from the corresponding bits in the AH
register (bits 7, 6, 4, 2, and 0, respectively). Bits 1, 3, and 5 of register AH are ignored; the corresponding reserved
bits (1, 3, and 5) in the EFLAGS register remain as shown in the "Operation" section below.
This instruction executes as described above in compatibility mode and legacy mode. It is valid in 64-bit mode only
if CPUID.80000001H:ECX.LAHF-SAHF[bit 0] = 1.

Operation
IF IA-64 Mode
    THEN
         IF CPUID.80000001H.ECX[0] = 1;
              THEN
                  RFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;
              ELSE
                  #UD;
         FI
    ELSE
         EFLAGS(SF:ZF:0:AF:0:PF:1:CF) <- AH;
FI;

Flags Affected
The SF, ZF, AF, PF, and CF flags are loaded with values from the AH register. Bits 1, 3, and 5 of the EFLAGS register
are unaffected, with the values remaining 1, 0, and 0, respectively.

Protected Mode Exceptions
None.

Real-Address Mode Exceptions
None.

Virtual-8086 Mode Exceptions
None.

Compatibility Mode Exceptions
None.





64-Bit Mode Exceptions
#UD                        If CPUID.80000001H.ECX[0] = 0.
                           If the LOCK prefix is used.






platform: x86_64
mnem: SAL
description:
SAL/SAR/SHL/SHR-Shift
 Opcode***            Instruction        Op/   64-Bit   Compat/ Description
                                         En    Mode     Leg Mode
 D0 /4                SAL r/m8, 1        M1    Valid    Valid    Multiply r/m8 by 2, once.
 REX + D0 /4          SAL r/m8**, 1      M1    Valid    N.E.     Multiply r/m8 by 2, once.
 D2 /4                SAL r/m8, CL       MC    Valid    Valid    Multiply r/m8 by 2, CL times.
 REX + D2 /4          SAL r/m8**, CL     MC    Valid    N.E.     Multiply r/m8 by 2, CL times.
 C0 /4 ib             SAL r/m8, imm8     MI    Valid    Valid    Multiply r/m8 by 2, imm8 times.
 REX + C0 /4 ib       SAL r/m8**, imm8   MI    Valid    N.E.     Multiply r/m8 by 2, imm8 times.
 D1 /4                SAL r/m16, 1       M1    Valid    Valid    Multiply r/m16 by 2, once.
 D3 /4                SAL r/m16, CL      MC    Valid    Valid    Multiply r/m16 by 2, CL times.
 C1 /4 ib             SAL r/m16, imm8    MI    Valid    Valid    Multiply r/m16 by 2, imm8 times.
 D1 /4                SAL r/m32, 1       M1    Valid    Valid    Multiply r/m32 by 2, once.
 REX.W + D1 /4        SAL r/m64, 1       M1    Valid    N.E.     Multiply r/m64 by 2, once.
 D3 /4                SAL r/m32, CL      MC    Valid    Valid    Multiply r/m32 by 2, CL times.
 REX.W + D3 /4        SAL r/m64, CL      MC    Valid    N.E.     Multiply r/m64 by 2, CL times.
 C1 /4 ib             SAL r/m32, imm8    MI    Valid    Valid    Multiply r/m32 by 2, imm8 times.
 REX.W + C1 /4 ib     SAL r/m64, imm8    MI    Valid    N.E.     Multiply r/m64 by 2, imm8 times.
 D0 /7                SAR r/m8, 1        M1    Valid    Valid    Signed divide* r/m8 by 2, once.
 REX + D0 /7          SAR r/m8**, 1      M1    Valid    N.E.     Signed divide* r/m8 by 2, once.
 D2 /7                SAR r/m8, CL       MC    Valid    Valid    Signed divide* r/m8 by 2, CL times.
 REX + D2 /7          SAR r/m8**, CL     MC    Valid    N.E.     Signed divide* r/m8 by 2, CL times.
 C0 /7 ib             SAR r/m8, imm8     MI    Valid    Valid    Signed divide* r/m8 by 2, imm8 time.
 REX + C0 /7 ib       SAR r/m8**, imm8   MI    Valid    N.E.     Signed divide* r/m8 by 2, imm8 times.
 D1 /7                SAR r/m16,1        M1    Valid    Valid    Signed divide* r/m16 by 2, once.
 D3 /7                SAR r/m16, CL      MC    Valid    Valid    Signed divide* r/m16 by 2, CL times.
 C1 /7 ib             SAR r/m16, imm8    MI    Valid    Valid    Signed divide* r/m16 by 2, imm8 times.
 D1 /7                SAR r/m32, 1       M1    Valid    Valid    Signed divide* r/m32 by 2, once.
 REX.W + D1 /7        SAR r/m64, 1       M1    Valid    N.E.     Signed divide* r/m64 by 2, once.
 D3 /7                SAR r/m32, CL      MC    Valid    Valid    Signed divide* r/m32 by 2, CL times.
 REX.W + D3 /7        SAR r/m64, CL      MC    Valid    N.E.     Signed divide* r/m64 by 2, CL times.
 C1 /7 ib             SAR r/m32, imm8    MI    Valid    Valid    Signed divide* r/m32 by 2, imm8 times.
 REX.W + C1 /7 ib     SAR r/m64, imm8    MI    Valid    N.E.     Signed divide* r/m64 by 2, imm8 times
 D0 /4                SHL r/m8, 1        M1    Valid    Valid    Multiply r/m8 by 2, once.
 REX + D0 /4          SHL r/m8**, 1      M1    Valid    N.E.     Multiply r/m8 by 2, once.
 D2 /4                SHL r/m8, CL       MC    Valid    Valid    Multiply r/m8 by 2, CL times.
 REX + D2 /4          SHL r/m8**, CL     MC    Valid    N.E.     Multiply r/m8 by 2, CL times.
 C0 /4 ib             SHL r/m8, imm8     MI    Valid    Valid    Multiply r/m8 by 2, imm8 times.
 REX + C0 /4 ib       SHL r/m8**, imm8   MI    Valid    N.E.     Multiply r/m8 by 2, imm8 times.
 D1 /4                SHL r/m16,1        M1    Valid    Valid    Multiply r/m16 by 2, once.
 D3 /4                SHL r/m16, CL      MC    Valid    Valid    Multiply r/m16 by 2, CL times.
 C1 /4 ib             SHL r/m16, imm8    MI    Valid    Valid    Multiply r/m16 by 2, imm8 times.
 D1 /4                SHL r/m32,1        M1    Valid    Valid    Multiply r/m32 by 2, once.



 Opcode                    Instruction                  Op/    64-Bit       Compat/ Description
                                                        En     Mode         Leg Mode
 REX.W + D1 /4             SHL r/m64,1                  M1     Valid        N.E.        Multiply r/m64 by 2, once.
 D3 /4                     SHL r/m32, CL                MC     Valid        Valid       Multiply r/m32 by 2, CL times.
 REX.W + D3 /4             SHL r/m64, CL                MC     Valid        N.E.        Multiply r/m64 by 2, CL times.
 C1 /4 ib                  SHL r/m32, imm8              MI     Valid        Valid       Multiply r/m32 by 2, imm8 times.
 REX.W + C1 /4 ib          SHL r/m64, imm8              MI     Valid        N.E.        Multiply r/m64 by 2, imm8 times.
 D0 /5                     SHR r/m8,1                   M1     Valid        Valid       Unsigned divide r/m8 by 2, once.
 REX + D0 /5               SHR r/m8**, 1                M1     Valid        N.E.        Unsigned divide r/m8 by 2, once.
 D2 /5                     SHR r/m8, CL                 MC     Valid        Valid       Unsigned divide r/m8 by 2, CL times.
 REX + D2 /5               SHR r/m8**, CL               MC     Valid        N.E.        Unsigned divide r/m8 by 2, CL times.
 C0 /5 ib                  SHR r/m8, imm8               MI     Valid        Valid       Unsigned divide r/m8 by 2, imm8 times.
 REX + C0 /5 ib            SHR r/m8**, imm8             MI     Valid        N.E.        Unsigned divide r/m8 by 2, imm8 times.
 D1 /5                     SHR r/m16, 1                 M1     Valid        Valid       Unsigned divide r/m16 by 2, once.
 D3 /5                     SHR r/m16, CL                MC     Valid        Valid       Unsigned divide r/m16 by 2, CL times
 C1 /5 ib                  SHR r/m16, imm8              MI     Valid        Valid       Unsigned divide r/m16 by 2, imm8 times.
 D1 /5                     SHR r/m32, 1                 M1     Valid        Valid       Unsigned divide r/m32 by 2, once.
 REX.W + D1 /5             SHR r/m64, 1                 M1     Valid        N.E.        Unsigned divide r/m64 by 2, once.
 D3 /5                     SHR r/m32, CL                MC     Valid        Valid       Unsigned divide r/m32 by 2, CL times.
 REX.W + D3 /5             SHR r/m64, CL                MC     Valid        N.E.        Unsigned divide r/m64 by 2, CL times.
 C1 /5 ib                  SHR r/m32, imm8              MI     Valid        Valid       Unsigned divide r/m32 by 2, imm8 times.
 REX.W + C1 /5 ib          SHR r/m64, imm8              MI     Valid        N.E.        Unsigned divide r/m64 by 2, imm8 times.
 NOTES:
 * Not the same form of division as IDIV; rounding is toward negative infinity.
 ** In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.
 ***See IA-32 Architecture Compatibility section below.



                                                  Instruction Operand Encoding
  Op/En              Operand 1                     Operand 2                        Operand 3                     Operand 4
    M1            ModRM:r/m (r, w)                      1                              NA                             NA
    MC            ModRM:r/m (r, w)                     CL                              NA                             NA
    MI            ModRM:r/m (r, w)                    imm8                             NA                             NA


Description
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the
second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF
flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination
operand.
The destination operand can be a register or a memory location. The count operand can be an immediate value or
the CL register. The count is masked to 5 bits (or 6 bits if in 64-bit mode and REX.W is used). The count range is
limited to 0 to 31 (or 63 if 64-bit mode and REX.W is used). A special opcode encoding is provided for a count of 1.
The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the
bits in the destination operand to the left (toward more significant bit locations). For each shift count, the most
significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see
Figure 7-7 in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1).




The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to
the right (toward less significant bit locations). For each shift count, the least significant bit of the destination
operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction
type. The SHR instruction clears the most significant bit (see Figure 7-8 in the Intel 64 and IA-32 Architectures
Software Developer's Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond
to the sign (most significant bit) of the original value in the destination operand. In effect, the SAR instruction fills
the empty bit position's shifted value with the sign of the unshifted value (see Figure 7-9 in the Intel 64 and IA-32
Architectures Software Developer's Manual, Volume 1).
The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination
operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides
the value by 2.
Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction.
The quotient from the IDIV instruction is rounded toward zero, whereas the "quotient" of the SAR instruction is
rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the
IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to
shift -9 right by two bits, the result is -3 and the "remainder" is +3; however, the SAR instruction stores only the
most significant bit of the remainder (in the CF flag).
The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is set to 0 if the most-significant bit of the
result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is
set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set
to the most-significant bit of the original operand.
In 64-bit mode, the instruction's default operation size is 32 bits and the mask width for CL is 5 bits. Using a REX
prefix in the form of REX.R permits access to additional registers (R8-R15). Using a REX prefix in the form of REX.W
promotes operation to 64-bits and sets the mask width for CL to 6 bits. See the summary chart at the beginning of
this section for encoding data and limits.

IA-32 Architecture Compatibility
The 8086 does not mask the shift count. However, all other IA-32 processors (starting with the Intel 286 processor)
do mask the shift count to 5 bits, resulting in a maximum count of 31. This masking is done in all operating modes
(including the virtual-8086 mode) to reduce the maximum execution time of the instructions.

Operation
IF 64-Bit Mode and using REX.W
    THEN
         countMASK <- 3FH;
    ELSE
         countMASK <- 1FH;
FI

tempCOUNT <- (COUNT AND countMASK);
tempDEST <- DEST;
WHILE (tempCOUNT != 0)
DO
   IF instruction is SAL or SHL
         THEN
             CF <- MSB(DEST);
         ELSE (* Instruction is SAR or SHR *)
             CF <- LSB(DEST);
   FI;
   IF instruction is SAL or SHL
         THEN
             DEST <- DEST * 2;
         ELSE
             IF instruction is SAR



                  THEN
                      DEST <- DEST / 2; (* Signed divide, rounding toward negative infinity *)
                  ELSE (* Instruction is SHR *)
                      DEST <- DEST / 2 ; (* Unsigned divide *)
             FI;
      FI;
      tempCOUNT <- tempCOUNT - 1;
OD;

(* Determine overflow for the various instructions *)
IF (COUNT and countMASK) = 1
    THEN
        IF instruction is SAL or SHL
              THEN
                    OF <- MSB(DEST) XOR CF;
              ELSE
                    IF instruction is SAR
                          THEN
                              OF <- 0;
                          ELSE (* Instruction is SHR *)
                              OF <- MSB(tempDEST);
                    FI;
        FI;
    ELSE IF (COUNT AND countMASK) = 0
        THEN
              All flags unchanged;
        ELSE (* COUNT not 1 or 0 *)
              OF <- undefined;
    FI;
FI;

Flags Affected
The CF flag contains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR
instructions where the count is greater than or equal to the size (in bits) of the destination operand. The OF flag is
affected only for 1-bit shifts (see "Description" above); otherwise, it is undefined. The SF, ZF, and PF flags are set
according to the result. If the count is 0, the flags are not affected. For a non-zero count, the AF flag is undefined.

Protected Mode Exceptions
#GP(0)                   If the destination is located in a non-writable segment.
                         If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                         If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                      If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                      If a memory operand effective address is outside the SS segment limit.
#UD                      If the LOCK prefix is used.




Virtual-8086 Mode Exceptions
#GP(0)              If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)              If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made.
#UD                 If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: SARX
description:
SARX/SHLX/SHRX - Shift Without Affecting Flags
 Opcode/                             Op/         64/32      CPUID      Description
 Instruction                         En          -bit       Feature
                                                 Mode       Flag
 VEX.NDS.LZ.F3.0F38.W0 F7 /r         RMV         V/V        BMI2       Shift r/m32 arithmetically right with count specified in r32b.
 SARX r32a, r/m32, r32b
 VEX.NDS.LZ.66.0F38.W0 F7 /r         RMV         V/V        BMI2       Shift r/m32 logically left with count specified in r32b.
 SHLX r32a, r/m32, r32b
 VEX.NDS.LZ.F2.0F38.W0 F7 /r         RMV         V/V        BMI2       Shift r/m32 logically right with count specified in r32b.
 SHRX r32a, r/m32, r32b
 VEX.NDS.LZ.F3.0F38.W1 F7 /r         RMV         V/N.E.     BMI2       Shift r/m64 arithmetically right with count specified in r64b.
 SARX r64a, r/m64, r64b
 VEX.NDS.LZ.66.0F38.W1 F7 /r         RMV         V/N.E.     BMI2       Shift r/m64 logically left with count specified in r64b.
 SHLX r64a, r/m64, r64b
 VEX.NDS.LZ.F2.0F38.W1 F7 /r         RMV         V/N.E.     BMI2       Shift r/m64 logically right with count specified in r64b.
 SHRX r64a, r/m64, r64b



                                                       Instruction Operand Encoding
   Op/En              Operand 1                           Operand 2                    Operand 3                        Operand 4
   RMV             ModRM:reg (w)                       ModRM:r/m (r)                  VEX.vvvv (r)                          NA


Description
Shifts the bits of the first source operand (the second operand) to the left or right by a COUNT value specified in
the second source operand (the third operand). The result is written to the destination operand (the first operand).
The shift arithmetic right (SARX) and shift logical right (SHRX) instructions shift the bits of the destination operand
to the right (toward less significant bit locations), SARX keeps and propagates the most significant bit (sign bit)
while shifting.
The logical shift left (SHLX) shifts the bits of the destination operand to the left (toward more significant bit loca-
tions).
This instruction is not supported in real mode and virtual-8086 mode. The operand size is always 32 bits if not in
64-bit mode. In 64-bit mode operand size 64 requires VEX.W1. VEX.W1 is ignored in non-64-bit modes. An
attempt to execute this instruction with VEX.L not equal to 0 will cause #UD.
If the value specified in the first source operand exceeds OperandSize -1, the COUNT value is masked.
SARX,SHRX, and SHLX instructions do not update flags.

Operation
TEMP <- SRC1;
IF VEX.W1 and CS.L = 1
THEN
    countMASK <-3FH;
ELSE
    countMASK <-1FH;
FI
COUNT <- (SRC2 AND countMASK)

DEST[OperandSize -1] = TEMP[OperandSize -1];
DO WHILE (COUNT != 0)
   IF instruction is SHLX
         THEN
             DEST[] <- DEST *2;




        ELSE IF instruction is SHRX
            THEN
                  DEST[] <- DEST /2; //unsigned divide
        ELSE          // SARX
                  DEST[] <- DEST /2; // signed divide, round toward negative infinity
     FI;
     COUNT <- COUNT - 1;
OD

Flags Affected
None.

Intel C/C++ Compiler Intrinsic Equivalent
Auto-generated from high-level language.

SIMD Floating-Point Exceptions
None

Other Exceptions
See Section 2.5.1, "Exception Conditions for VEX-Encoded GPR Instructions", Table 2-29; additionally
#UD                    If VEX.W = 1.






platform: x86_64
mnem: SBB
description:
SBB-Integer Subtraction with Borrow
 Opcode                    Instruction                  Op/   64-Bit       Compat/ Description
                                                        En    Mode         Leg Mode
 1C ib                     SBB AL, imm8                 I     Valid        Valid        Subtract with borrow imm8 from AL.
 1D iw                     SBB AX, imm16                I     Valid        Valid        Subtract with borrow imm16 from AX.
 1D id                     SBB EAX, imm32               I     Valid        Valid        Subtract with borrow imm32 from EAX.
 REX.W + 1D id             SBB RAX, imm32               I     Valid        N.E.         Subtract with borrow sign-extended imm.32
                                                                                        to 64-bits from RAX.
 80 /3 ib                  SBB r/m8, imm8               MI    Valid        Valid        Subtract with borrow imm8 from r/m8.
 REX + 80 /3 ib            SBB r/m8*, imm8              MI    Valid        N.E.         Subtract with borrow imm8 from r/m8.
 81 /3 iw                  SBB r/m16, imm16             MI    Valid        Valid        Subtract with borrow imm16 from r/m16.
 81 /3 id                  SBB r/m32, imm32             MI    Valid        Valid        Subtract with borrow imm32 from r/m32.
 REX.W + 81 /3 id          SBB r/m64, imm32             MI    Valid        N.E.         Subtract with borrow sign-extended imm32 to
                                                                                        64-bits from r/m64.
 83 /3 ib                  SBB r/m16, imm8              MI    Valid        Valid        Subtract with borrow sign-extended imm8
                                                                                        from r/m16.
 83 /3 ib                  SBB r/m32, imm8              MI    Valid        Valid        Subtract with borrow sign-extended imm8
                                                                                        from r/m32.
 REX.W + 83 /3 ib          SBB r/m64, imm8              MI    Valid        N.E.         Subtract with borrow sign-extended imm8
                                                                                        from r/m64.
 18 /r                     SBB r/m8, r8                 MR    Valid        Valid        Subtract with borrow r8 from r/m8.
 REX + 18 /r               SBB r/m8*, r8                MR    Valid        N.E.         Subtract with borrow r8 from r/m8.
 19 /r                     SBB r/m16, r16               MR    Valid        Valid        Subtract with borrow r16 from r/m16.
 19 /r                     SBB r/m32, r32               MR    Valid        Valid        Subtract with borrow r32 from r/m32.
 REX.W + 19 /r             SBB r/m64, r64               MR    Valid        N.E.         Subtract with borrow r64 from r/m64.
 1A /r                     SBB r8, r/m8                 RM    Valid        Valid        Subtract with borrow r/m8 from r8.
 REX + 1A /r               SBB r8*, r/m8*               RM    Valid        N.E.         Subtract with borrow r/m8 from r8.
 1B /r                     SBB r16, r/m16               RM    Valid        Valid        Subtract with borrow r/m16 from r16.


 1B /r                     SBB r32, r/m32               RM    Valid        Valid        Subtract with borrow r/m32 from r32.
 REX.W + 1B /r             SBB r64, r/m64               RM    Valid        N.E.         Subtract with borrow r/m64 from r64.
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                     Operand 2                      Operand 3                      Operand 4
      I             AL/AX/EAX/RAX                  imm8/16/32                          NA                             NA
     MI             ModRM:r/m (w)                  imm8/16/32                          NA                             NA
    MR              ModRM:r/m (w)                  ModRM:reg (r)                       NA                             NA
    RM              ModRM:reg (w)                 ModRM:r/m (r)                        NA                             NA





Description
Adds the source operand (second operand) and the carry (CF) flag, and subtracts the result from the destination
operand (first operand). The result of the subtraction is stored in the destination operand. The destination operand
can be a register or a memory location; the source operand can be an immediate, a register, or a memory location.
(However, two memory operands cannot be used in one instruction.) The state of the CF flag represents a borrow
from a previous subtraction.
When an immediate value is used as an operand, it is sign-extended to the length of the destination operand
format.
The SBB instruction does not distinguish between signed or unsigned operands. Instead, the processor evaluates
the result for both data types and sets the OF and CF flags to indicate a borrow in the signed or unsigned result,
respectively. The SF flag indicates the sign of the signed result.
The SBB instruction is usually executed as part of a multibyte or multiword subtraction in which a SUB instruction
is followed by a SBB instruction.
This instruction can be used with a LOCK prefix to allow the instruction to be executed atomically.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits. See
the summary chart at the beginning of this section for encoding data and limits.

Operation
DEST <- (DEST - (SRC + CF));

Intel C/C++ Compiler Intrinsic Equivalent
SBB:       extern unsigned char _subborrow_u8(unsigned char c_in, unsigned char src1, unsigned char src2, unsigned char *diff_out);
SBB:        extern unsigned char _subborrow_u16(unsigned char c_in, unsigned short src1, unsigned short src2, unsigned short
*diff_out);
SBB:        extern unsigned char _subborrow_u32(unsigned char c_in, unsigned int src1, unsigned char int, unsigned int *diff_out);
SBB:        extern unsigned char _subborrow_u64(unsigned char c_in, unsigned __int64 src1, unsigned __int64 src2, unsigned
__int64 *diff_out);

Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the result.

Protected Mode Exceptions
#GP(0)                  If the destination is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used but the destination is not a memory operand.





Virtual-8086 Mode Exceptions
#GP(0)                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made.
#UD                      If the LOCK prefix is used but the destination is not a memory operand.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                   If the memory address is in a non-canonical form.
#PF(fault-code)          If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                      If the LOCK prefix is used but the destination is not a memory operand.






platform: x86_64
mnem: SCAS
description:
SCAS/SCASB/SCASW/SCASD-Scan String
 Opcode                    Instruction                   Op/    64-Bit       Compat/ Description
                                                         En     Mode         Leg Mode
 AE                        SCAS m8                       NP     Valid        Valid       Compare AL with byte at ES:(E)DI or RDI, then
                                                                                         set status flags.*
 AF                        SCAS m16                      NP     Valid        Valid       Compare AX with word at ES:(E)DI or RDI, then
                                                                                         set status flags.*
 AF                        SCAS m32                      NP     Valid        Valid       Compare EAX with doubleword at ES(E)DI or
                                                                                         RDI then set status flags.*
 REX.W + AF                SCAS m64                      NP     Valid        N.E.        Compare RAX with quadword at RDI or EDI
                                                                                         then set status flags.
 AE                        SCASB                         NP     Valid        Valid       Compare AL with byte at ES:(E)DI or RDI then
                                                                                         set status flags.*
 AF                        SCASW                         NP     Valid        Valid       Compare AX with word at ES:(E)DI or RDI then
                                                                                         set status flags.*
 AF                        SCASD                         NP     Valid        Valid       Compare EAX with doubleword at ES:(E)DI or
                                                                                         RDI then set status flags.*
 REX.W + AF                SCASQ                         NP     Valid        N.E.        Compare RAX with quadword at RDI or EDI
                                                                                         then set status flags.
 NOTES:
 * In 64-bit mode, only 64-bit (RDI) and 32-bit (EDI) address sizes are supported. In non-64-bit mode, only 32-bit (EDI) and 16-bit (DI)
   address sizes are supported.



                                                   Instruction Operand Encoding
  Op/En               Operand 1                      Operand 2                       Operand 3                      Operand 4
      NP                  NA                             NA                              NA                             NA


Description
In non-64-bit modes and in default 64-bit mode: this instruction compares a byte, word, doubleword or quadword
specified using a memory operand with the value in AL, AX, or EAX. It then sets status flags in EFLAGS recording
the results. The memory operand address is read from ES:(E)DI register (depending on the address-size attribute
of the instruction and the current operational mode). Note that ES cannot be overridden with a segment override
prefix.
At the assembly-code level, two forms of this instruction are allowed. The explicit-operand form and the no-oper-
ands form. The explicit-operand form (specified using the SCAS mnemonic) allows a memory operand to be speci-
fied explicitly. The memory operand must be a symbol that indicates the size and location of the operand value. The
register operand is then automatically selected to match the size of the memory operand (AL register for byte
comparisons, AX for word comparisons, EAX for doubleword comparisons). The explicit-operand form is provided
to allow documentation. Note that the documentation provided by this form can be misleading. That is, the
memory operand symbol must specify the correct type (size) of the operand (byte, word, or doubleword) but it
does not have to specify the correct location. The location is always specified by ES:(E)DI.
The no-operands form of the instruction uses a short form of SCAS. Again, ES:(E)DI is assumed to be the memory
operand and AL, AX, or EAX is assumed to be the register operand. The size of operands is selected by the
mnemonic: SCASB (byte comparison), SCASW (word comparison), or SCASD (doubleword comparison).
After the comparison, the (E)DI register is incremented or decremented automatically according to the setting of
the DF flag in the EFLAGS register. If the DF flag is 0, the (E)DI register is incremented; if the DF flag is 1, the (E)DI
register is decremented. The register is incremented or decremented by 1 for byte operations, by 2 for word oper-
ations, and by 4 for doubleword operations.
SCAS, SCASB, SCASW, SCASD, and SCASQ can be preceded by the REP prefix for block comparisons of ECX bytes,
words, doublewords, or quadwords. Often, however, these instructions will be used in a LOOP construct that takes



some action based on the setting of status flags. See "REP/REPE/REPZ /REPNE/REPNZ-Repeat String Operation
Prefix" in this chapter for a description of the REP prefix.
In 64-bit mode, the instruction's default address size is 64-bits, 32-bit address size is supported using the prefix
67H. Using a REX prefix in the form of REX.W promotes operation on doubleword operand to 64 bits. The 64-bit no-
operand mnemonic is SCASQ. Address of the memory operand is specified in either RDI or EDI, and
AL/AX/EAX/RAX may be used as the register operand. After a comparison, the destination register is incremented
or decremented by the current operand size (depending on the value of the DF flag). See the summary chart at the
beginning of this section for encoding data and limits.

Operation
Non-64-bit Mode:

IF (Byte comparison)
    THEN
         temp <- AL - SRC;
         SetStatusFlags(temp);
              THEN IF DF = 0
                   THEN (E)DI <- (E)DI + 1;
                   ELSE (E)DI <- (E)DI - 1; FI;
    ELSE IF (Word comparison)
         THEN
              temp <- AX - SRC;
              SetStatusFlags(temp);
              IF DF = 0
                   THEN (E)DI <- (E)DI + 2;
                   ELSE (E)DI <- (E)DI - 2; FI;
         FI;
    ELSE IF (Doubleword comparison)
         THEN
              temp <- EAX - SRC;
              SetStatusFlags(temp);
              IF DF = 0
                   THEN (E)DI <- (E)DI + 4;
                   ELSE (E)DI <- (E)DI - 4; FI;
         FI;
FI;

64-bit Mode:

IF (Byte cmparison)
    THEN
         temp <- AL - SRC;
         SetStatusFlags(temp);
             THEN IF DF = 0
                  THEN (R|E)DI <- (R|E)DI + 1;
                  ELSE (R|E)DI <- (R|E)DI - 1; FI;
    ELSE IF (Word comparison)
         THEN
             temp <- AX - SRC;
             SetStatusFlags(temp);
             IF DF = 0
                  THEN (R|E)DI <- (R|E)DI + 2;
                  ELSE (R|E)DI <- (R|E)DI - 2; FI;
         FI;



    ELSE IF (Doubleword comparison)
        THEN
              temp <- EAX - SRC;
              SetStatusFlags(temp);
              IF DF = 0
                   THEN (R|E)DI <- (R|E)DI + 4;
                   ELSE (R|E)DI <- (R|E)DI - 4; FI;
        FI;
    ELSE IF (Quadword comparison using REX.W )
        THEN
              temp <- RAX - SRC;
              SetStatusFlags(temp);
              IF DF = 0
                   THEN (R|E)DI <- (R|E)DI + 8;
                   ELSE (R|E)DI <- (R|E)DI - 8;
              FI;
    FI;
F

Flags Affected
The OF, SF, ZF, AF, PF, and CF flags are set according to the temporary result of the comparison.

Protected Mode Exceptions
#GP(0)                   If a memory operand effective address is outside the limit of the ES segment.
                         If the ES register contains a NULL segment selector.
                         If an illegal memory operand effective address in the ES segment is given.
#PF(fault-code)          If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                      If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                      If a memory operand effective address is outside the SS segment limit.
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made.
#UD                      If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#GP(0)                If the memory address is in a non-canonical form.
#PF(fault-code)       If a page fault occurs.
#AC(0)                If alignment checking is enabled and an unaligned memory reference is made while the
                      current privilege level is 3.
#UD                   If the LOCK prefix is used.






platform: x86_64
mnem: SETcc
description:
SETcc-Set Byte on Condition
 Opcode               Instruction    Op/   64-Bit   Compat/ Description
                                     En    Mode     Leg Mode
 0F 97                SETA r/m8      M     Valid    Valid    Set byte if above (CF=0 and ZF=0).
 REX + 0F 97          SETA r/m8*     M     Valid    N.E.     Set byte if above (CF=0 and ZF=0).
 0F 93                SETAE r/m8     M     Valid    Valid    Set byte if above or equal (CF=0).
 REX + 0F 93          SETAE r/m8*    M     Valid    N.E.     Set byte if above or equal (CF=0).
 0F 92                SETB r/m8      M     Valid    Valid    Set byte if below (CF=1).
 REX + 0F 92          SETB r/m8*     M     Valid    N.E.     Set byte if below (CF=1).
 0F 96                SETBE r/m8     M     Valid    Valid    Set byte if below or equal (CF=1 or ZF=1).
 REX + 0F 96          SETBE r/m8*    M     Valid    N.E.     Set byte if below or equal (CF=1 or ZF=1).
 0F 92                SETC r/m8      M     Valid    Valid    Set byte if carry (CF=1).
 REX + 0F 92          SETC r/m8*     M     Valid    N.E.     Set byte if carry (CF=1).
 0F 94                SETE r/m8      M     Valid    Valid    Set byte if equal (ZF=1).
 REX + 0F 94          SETE r/m8*     M     Valid    N.E.     Set byte if equal (ZF=1).
 0F 9F                SETG r/m8      M     Valid    Valid    Set byte if greater (ZF=0 and SF=OF).
 REX + 0F 9F          SETG r/m8*     M     Valid    N.E.     Set byte if greater (ZF=0 and SF=OF).
 0F 9D                SETGE r/m8     M     Valid    Valid    Set byte if greater or equal (SF=OF).
 REX + 0F 9D          SETGE r/m8*    M     Valid    N.E.     Set byte if greater or equal (SF=OF).
 0F 9C                SETL r/m8      M     Valid    Valid    Set byte if less (SF!= OF).
 REX + 0F 9C          SETL r/m8*     M     Valid    N.E.     Set byte if less (SF!= OF).
 0F 9E                SETLE r/m8     M     Valid    Valid    Set byte if less or equal (ZF=1 or SF!= OF).
 REX + 0F 9E          SETLE r/m8*    M     Valid    N.E.     Set byte if less or equal (ZF=1 or SF!= OF).
 0F 96                SETNA r/m8     M     Valid    Valid    Set byte if not above (CF=1 or ZF=1).
 REX + 0F 96          SETNA r/m8*    M     Valid    N.E.     Set byte if not above (CF=1 or ZF=1).
 0F 92                SETNAE r/m8    M     Valid    Valid    Set byte if not above or equal (CF=1).
 REX + 0F 92          SETNAE r/m8*   M     Valid    N.E.     Set byte if not above or equal (CF=1).
 0F 93                SETNB r/m8     M     Valid    Valid    Set byte if not below (CF=0).
 REX + 0F 93          SETNB r/m8*    M     Valid    N.E.     Set byte if not below (CF=0).
 0F 97                SETNBE r/m8    M     Valid    Valid    Set byte if not below or equal (CF=0 and
                                                             ZF=0).
 REX + 0F 97          SETNBE r/m8*   M     Valid    N.E.     Set byte if not below or equal (CF=0 and
                                                             ZF=0).
 0F 93                SETNC r/m8     M     Valid    Valid    Set byte if not carry (CF=0).
 REX + 0F 93          SETNC r/m8*    M     Valid    N.E.     Set byte if not carry (CF=0).
 0F 95                SETNE r/m8     M     Valid    Valid    Set byte if not equal (ZF=0).
 REX + 0F 95          SETNE r/m8*    M     Valid    N.E.     Set byte if not equal (ZF=0).
 0F 9E                SETNG r/m8     M     Valid    Valid    Set byte if not greater (ZF=1 or SF!= OF)
 REX + 0F 9E          SETNG r/m8*    M     Valid    N.E.     Set byte if not greater (ZF=1 or SF!= OF).
 0F 9C                SETNGE r/m8    M     Valid    Valid    Set byte if not greater or equal (SF!= OF).
 REX + 0F 9C          SETNGE r/m8*   M     Valid    N.E.     Set byte if not greater or equal (SF!= OF).
 0F 9D                SETNL r/m8     M     Valid    Valid    Set byte if not less (SF=OF).
 REX + 0F 9D          SETNL r/m8*    M     Valid    N.E.     Set byte if not less (SF=OF).
 0F 9F                SETNLE r/m8    M     Valid    Valid    Set byte if not less or equal (ZF=0 and SF=OF).


 Opcode                       Instruction              Op/     64-Bit      Compat/ Description
                                                       En      Mode        Leg Mode
 REX + 0F 9F                  SETNLE r/m8*              M      Valid       N.E.        Set byte if not less or equal (ZF=0 and SF=OF).
 0F 91                        SETNO r/m8                M      Valid       Valid       Set byte if not overflow (OF=0).
 REX + 0F 91                  SETNO r/m8*               M      Valid       N.E.        Set byte if not overflow (OF=0).
 0F 9B                        SETNP r/m8                M      Valid       Valid        Set byte if not parity (PF=0).


 REX + 0F 9B                  SETNP r/m8*               M      Valid       N.E.         Set byte if not parity (PF=0).
 0F 99                        SETNS r/m8                M      Valid       Valid       Set byte if not sign (SF=0).
 REX + 0F 99                  SETNS r/m8*               M      Valid       N.E.        Set byte if not sign (SF=0).
 0F 95                        SETNZ r/m8                M      Valid       Valid       Set byte if not zero (ZF=0).
 REX + 0F 95                  SETNZ r/m8*               M      Valid       N.E.        Set byte if not zero (ZF=0).
 0F 90                        SETO r/m8                 M      Valid       Valid       Set byte if overflow (OF=1)
 REX + 0F 90                  SETO r/m8*                M      Valid       N.E.         Set byte if overflow (OF=1).
 0F 9A                        SETP r/m8                 M      Valid       Valid        Set byte if parity (PF=1).
 REX + 0F 9A                  SETP r/m8*                M      Valid       N.E.         Set byte if parity (PF=1).
 0F 9A                        SETPE r/m8                M      Valid       Valid        Set byte if parity even (PF=1).
 REX + 0F 9A                  SETPE r/m8*               M      Valid       N.E.         Set byte if parity even (PF=1).
 0F 9B                        SETPO r/m8                M      Valid       Valid        Set byte if parity odd (PF=0).
 REX + 0F 9B                  SETPO r/m8*               M      Valid       N.E.         Set byte if parity odd (PF=0).
 0F 98                        SETS r/m8                 M      Valid       Valid        Set byte if sign (SF=1).
 REX + 0F 98                  SETS r/m8*                M      Valid       N.E.         Set byte if sign (SF=1).
 0F 94                        SETZ r/m8                 M      Valid       Valid       Set byte if zero (ZF=1).
 REX + 0F 94                  SETZ r/m8*                M      Valid       N.E.        Set byte if zero (ZF=1).
 NOTES:
 * In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is used: AH, BH, CH, DH.



                                                  Instruction Operand Encoding
   Op/En              Operand 1                    Operand 2                       Operand 3                         Operand 4
     M              ModRM:r/m (r)                      NA                             NA                                 NA


Description
Sets the destination operand to 0 or 1 depending on the settings of the status flags (CF, SF, OF, ZF, and PF) in the
EFLAGS register. The destination operand points to a byte register or a byte in memory. The condition code suffix
(cc) indicates the condition being tested for.
The terms "above" and "below" are associated with the CF flag and refer to the relationship between two unsigned
integer values. The terms "greater" and "less" are associated with the SF and OF flags and refer to the relationship
between two signed integer values.
Many of the SETcc instruction opcodes have alternate mnemonics. For example, SETG (set byte if greater) and
SETNLE (set if not less or equal) have the same opcode and test for the same condition: ZF equals 0 and SF equals
OF. These alternate mnemonics are provided to make code more intelligible. Appendix B, "EFLAGS Condition
Codes," in the Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1, shows the alternate
mnemonics for various test conditions.
Some languages represent a logical one as an integer with all bits set. This representation can be obtained by
choosing the logically opposite condition for the SETcc instruction, then decrementing the result. For example, to
test for overflow, use the SETNO instruction, then decrement the result.



In IA-64 mode, the operand size is fixed at 8 bits. Use of REX prefix enable uniform addressing to additional byte
registers. Otherwise, this instruction's operation is the same as in legacy mode and compatibility mode.

Operation
IF condition
    THEN DEST <- 1;
    ELSE DEST <- 0;
FI;

Flags Affected
None.

Protected Mode Exceptions
#GP(0)               If the destination is located in a non-writable segment.
                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                     If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#UD                  If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                  If a memory operand effective address is outside the SS segment limit.
#UD                  If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)               If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)               If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)      If a page fault occurs.
#UD                  If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)               If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)               If the memory address is in a non-canonical form.
#PF(fault-code)      If a page fault occurs.
#UD                  If the LOCK prefix is used.






platform: x86_64
mnem: SFENCE
description:
SFENCE-Store Fence
 Opcode*                  Instruction                 Op/   64-Bit   Compat/ Description
                                                      En    Mode     Leg Mode
 0F AE F8                 SFENCE                      NP    Valid    Valid      Serializes store operations.



                                                Instruction Operand Encoding
  Op/En              Operand 1                     Operand 2                 Operand 3                     Operand 4
    NP                   NA                            NA                       NA                             NA


Description
Performs a serializing operation on all store-to-memory instructions that were issued prior the SFENCE instruction.
This serializing operation guarantees that every store instruction that precedes the SFENCE instruction in program
order becomes globally visible before any store instruction that follows the SFENCE instruction. The SFENCE
instruction is ordered with respect to store instructions, other SFENCE instructions, any LFENCE and MFENCE
instructions, and any serializing instructions (such as the CPUID instruction). It is not ordered with respect to load
instructions.
Weakly ordered memory types can be used to achieve higher processor performance through such techniques as
out-of-order issue, write-combining, and write-collapsing. The degree to which a consumer of data recognizes or
knows that the data is weakly ordered varies among applications and may be unknown to the producer of this data.
The SFENCE instruction provides a performance-efficient way of ensuring store ordering between routines that
produce weakly-ordered results and routines that consume this data.
This instruction's operation is the same in non-64-bit modes and 64-bit mode.
Specification of the instruction's opcode above indicates a ModR/M byte of F8. For this instruction, the processor
ignores the r/m field of the ModR/M byte. Thus, SFENCE is encoded by any opcode of the form 0F AE Fx, where x
is in the range 8-F.

Operation
Wait_On_Following_Stores_Until(preceding_stores_globally_visible);

Intel C/C++ Compiler Intrinsic Equivalent
void _mm_sfence(void)

Exceptions (All Operating Modes)
#UD                     If CPUID.01H:EDX.SSE[bit 25] = 0.
                        If the LOCK prefix is used.






platform: x86_64
mnem: SGDT
description:
SGDT-Store Global Descriptor Table Register
 Opcode*                  Instruction                    Op/   64-Bit     Compat/ Description
                                                         En    Mode       Leg Mode
 0F 01 /0                 SGDT m                         M     Valid      Valid         Store GDTR to m.
 NOTES:
 * See IA-32 Architecture Compatibility section below.



                                                 Instruction Operand Encoding
   Op/En              Operand 1                      Operand 2                       Operand 3                     Operand 4
     M              ModRM:r/m (w)                        NA                             NA                             NA


Description
Stores the content of the global descriptor table register (GDTR) in the destination operand. The destination
operand specifies a memory location.
In legacy or compatibility mode, the destination operand is a 6-byte memory location. If the operand-size attribute
is 16 bits, the limit is stored in the low 2 bytes and the 24-bit base address is stored in bytes 3-5, and byte 6 is zero-
filled. If the operand-size attribute is 32 bits, the 16-bit limit field of the register is stored in the low 2 bytes of the
memory location and the 32-bit base address is stored in the high 4 bytes.
In IA-32e mode, the operand size is fixed at 8+2 bytes. The instruction stores an 8-byte base and a 2-byte limit.
SGDT is useful only by operating-system software. However, it can be used in application programs without causing
an exception to be generated if CR4.UMIP = 0. See "LGDT/LIDT-Load Global/Interrupt Descriptor Table Register"
in Chapter 3, Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, for information on
loading the GDTR and IDTR.

IA-32 Architecture Compatibility
The 16-bit form of the SGDT is compatible with the Intel 286 processor if the upper 8 bits are not referenced. The
Intel 286 processor fills these bits with 1s; processor generations later than the Intel 286 processor fill these bits
with 0s.

Operation
IF instruction is SGDT
         IF OperandSize = 16
              THEN
                   DEST[0:15] <- GDTR(Limit);
                   DEST[16:39] <- GDTR(Base); (* 24 bits of base address stored *)
                   DEST[40:47] <- 0;
              ELSE IF (32-bit Operand Size)
                   DEST[0:15] <- GDTR(Limit);
                   DEST[16:47] <- GDTR(Base); (* Full 32-bit base address stored *)
                   FI;
              ELSE (* 64-bit Operand Size *)
                   DEST[0:15] <- GDTR(Limit);
                   DEST[16:79] <- GDTR(Base); (* Full 64-bit base address stored *)
         FI;
FI;

Flags Affected
None.




Protected Mode Exceptions
#UD                      If the destination operand is a register.
                         If the LOCK prefix is used.
#GP(0)                   If the destination is located in a non-writable segment.
                         If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                         If the DS, ES, FS, or GS register is used to access memory and it contains a NULL segment
                         selector.
                         If CR4.UMIP = 1 and CPL > 0.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.

Real-Address Mode Exceptions
#UD                      If the destination operand is a register.
                         If the LOCK prefix is used.
#GP                      If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                      If a memory operand effective address is outside the SS segment limit.

Virtual-8086 Mode Exceptions
#UD                      If the destination operand is a register.
                         If the LOCK prefix is used.
#GP(0)                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                         If CR4.UMIP = 1.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made.

Compatibility Mode Exceptions
Same exceptions as in protected mode.

64-Bit Mode Exceptions
#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.
#UD                      If the destination operand is a register.
                         If the LOCK prefix is used.
#GP(0)                   If the memory address is in a non-canonical form.
                         If CR4.UMIP = 1 and CPL > 0.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while CPL = 3.






platform: x86_64
mnem: SHA1RNDS4
description:
SHA1RNDS4-Perform Four Rounds of SHA1 Operation
 Opcode/                            Op/En      64/32         CPUID     Description
 Instruction                                   bit Mode      Feature
                                               Support       Flag
 0F 3A CC /r ib                     RMI        V/V           SHA       Performs four rounds of SHA1 operation operating on SHA1 state
 SHA1RNDS4 xmm1,                                                       (A,B,C,D) from xmm1, with a pre-computed sum of the next 4
 xmm2/m128, imm8                                                       round message dwords and state variable E from xmm2/m128.
                                                                       The immediate byte controls logic functions and round constants.



                                                    Instruction Operand Encoding
      Op/En                        Operand 1                              Operand 2                             Operand 3
       RMI                      ModRM:reg (r, w)                        ModRM:r/m (r)                              Imm8

Description
The SHA1RNDS4 instruction performs four rounds of SHA1 operation using an initial SHA1 state (A,B,C,D) from the
first operand (which is a source operand and the destination operand) and some pre-computed sum of the next 4
round message dwords, and state variable E from the second operand (a source operand). The updated SHA1 state
(A,B,C,D) after four rounds of processing is stored in the destination operand.

Operation
SHA1RNDS4
The function f() and Constant K are dependent on the value of the immediate.

IF ( imm8[1:0] = 0 )
     THEN f() <- f0(), K <- K0;
ELSE IF ( imm8[1:0] = 1 )
     THEN f() <- f1(), K <- K1;
ELSE IF ( imm8[1:0] = 2 )
     THEN f() <- f2(), K <- K2;
ELSE IF ( imm8[1:0] = 3 )
     THEN f() <- f3(), K <- K3;
FI;

A <- SRC1[127:96];
B <- SRC1[95:64];
C <- SRC1[63:32];
D <- SRC1[31:0];
W0E <- SRC2[127:96];
W1 <- SRC2[95:64];
W2 <- SRC2[63:32];
W3 <- SRC2[31:0];

Round i = 0 operation:
A_1 <- f (B, C, D) + (A ROL 5) +W0E +K;
B_1 <- A;
C_1 <- B ROL 30;
D_1 <- C;
E_1 <- D;

FOR i = 1 to 3
   A_(i +1) <- f (B_i, C_i, D_i) + (A_i ROL 5) +Wi+ E_i +K;
   B_(i +1) <- A_i;



   C_(i +1) <- B_i ROL 30;
   D_(i +1) <- C_i;
   E_(i +1) <- D_i;
ENDFOR

DEST[127:96] <- A_4;
DEST[95:64] <- B_4;
DEST[63:32] <- C_4;
DEST[31:0] <- D_4;

Intel C/C++ Compiler Intrinsic Equivalent
SHA1RNDS4: __m128i _mm_sha1rnds4_epu32(__m128i, __m128i, const int);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA1NEXTE
description:
SHA1NEXTE-Calculate SHA1 State Variable E after Four Rounds
 Opcode/                         Op/En      64/32      CPUID     Description
 Instruction                                bit Mode   Feature
                                            Support    Flag
 0F 38 C8 /r                     RM         V/V        SHA       Calculates SHA1 state variable E after four rounds of operation
 SHA1NEXTE xmm1,                                                 from the current SHA1 state variable A in xmm1. The calculated
 xmm2/m128                                                       value of the SHA1 state variable E is added to the scheduled
                                                                 dwords in xmm2/m128, and stored with some of the scheduled
                                                                 dwords in xmm1.



                                                 Instruction Operand Encoding
     Op/En                   Operand 1                            Operand 2                               Operand 3
       RM                 ModRM:reg (r, w)                       ModRM:r/m (r)                                NA

Description
The SHA1NEXTE calculates the SHA1 state variable E after four rounds of operation from the current SHA1 state
variable A in the destination operand. The calculated value of the SHA1 state variable E is added to the source
operand, which contains the scheduled dwords.

Operation
SHA1NEXTE

TMP <- (SRC1[127:96] ROL 30);

DEST[127:96] <- SRC2[127:96] + TMP;
DEST[95:64] <- SRC2[95:64];
DEST[63:32] <- SRC2[63:32];
DEST[31:0] <- SRC2[31:0];

Intel C/C++ Compiler Intrinsic Equivalent
SHA1NEXTE: __m128i _mm_sha1nexte_epu32(__m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA1MSG1
description:
SHA1MSG1-Perform an Intermediate Calculation for the Next Four SHA1 Message Dwords
 Opcode/                          Op/En     64/32        CPUID       Description
 Instruction                                bit Mode     Feature
                                            Support      Flag
 0F 38 C9 /r                      RM        V/V          SHA         Performs an intermediate calculation for the next four SHA1
 SHA1MSG1 xmm1,                                                      message dwords using previous message dwords from xmm1 and
 xmm2/m128                                                           xmm2/m128, storing the result in xmm1.



                                                  Instruction Operand Encoding
     Op/En                     Operand 1                             Operand 2                           Operand 3
       RM                   ModRM:reg (r, w)                       ModRM:r/m (r)                             NA

Description
The SHA1MSG1 instruction is one of two SHA1 message scheduling instructions. The instruction performs an inter-
mediate calculation for the next four SHA1 message dwords.

Operation
SHA1MSG1

W0 <- SRC1[127:96] ;
W1 <- SRC1[95:64] ;
W2 <- SRC1[63: 32] ;
W3 <- SRC1[31: 0] ;
W4 <- SRC2[127:96] ;
W5 <- SRC2[95:64] ;

DEST[127:96] <- W2 XOR W0;
DEST[95:64] <- W3 XOR W1;
DEST[63:32] <- W4 XOR W2;
DEST[31:0] <- W5 XOR W3;

Intel C/C++ Compiler Intrinsic Equivalent
SHA1MSG1: __m128i _mm_sha1msg1_epu32(__m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA1MSG2
description:
SHA1MSG2-Perform a Final Calculation for the Next Four SHA1 Message Dwords
 Opcode/                         Op/En      64/32      CPUID     Description
 Instruction                                bit Mode   Feature
                                            Support    Flag
 0F 38 CA /r                     RM         V/V        SHA       Performs the final calculation for the next four SHA1 message
 SHA1MSG2 xmm1,                                                  dwords using intermediate results from xmm1 and the previous
 xmm2/m128                                                       message dwords from xmm2/m128, storing the result in xmm1.



                                                 Instruction Operand Encoding
       Op/En                  Operand 1                            Operand 2                               Operand 3
        RM                 ModRM:reg (r, w)                      ModRM:r/m (r)                                NA

Description
The SHA1MSG2 instruction is one of two SHA1 message scheduling instructions. The instruction performs the final
calculation to derive the next four SHA1 message dwords.

Operation
SHA1MSG2

W13 <- SRC2[95:64] ;
W14 <- SRC2[63: 32] ;
W15 <- SRC2[31: 0] ;
W16 <- (SRC1[127:96] XOR W13 ) ROL 1;
W17 <- (SRC1[95:64] XOR W14) ROL 1;
W18 <- (SRC1[63: 32] XOR W15) ROL 1;
W19 <- (SRC1[31: 0] XOR W16) ROL 1;

DEST[127:96] <- W16;
DEST[95:64] <- W17;
DEST[63:32] <- W18;
DEST[31:0] <- W19;

Intel C/C++ Compiler Intrinsic Equivalent

SHA1MSG2: __m128i _mm_sha1msg2_epu32(__m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA256RNDS2
description:
SHA256RNDS2-Perform Two Rounds of SHA256 Operation
 Opcode/                           Op/En     64/32        CPUID       Description
 Instruction                                 bit Mode     Feature
                                             Support      Flag
 0F 38 CB /r                       RM0       V/V          SHA         Perform 2 rounds of SHA256 operation using an initial SHA256
 SHA256RNDS2 xmm1,                                                    state (C,D,G,H) from xmm1, an initial SHA256 state (A,B,E,F) from
 xmm2/m128, <XMM0>                                                    xmm2/m128, and a pre-computed sum of the next 2 round mes-
                                                                      sage dwords and the corresponding round constants from the
                                                                      implicit operand XMM0, storing the updated SHA256 state
                                                                      (A,B,E,F) result in xmm1.



                                                   Instruction Operand Encoding
     Op/En                     Operand 1                                Operand 2                              Operand 3
       RMI                  ModRM:reg (r, w)                          ModRM:r/m (r)                         Implicit XMM0 (r)

Description
The SHA256RNDS2 instruction performs 2 rounds of SHA256 operation using an initial SHA256 state (C,D,G,H)
from the first operand, an initial SHA256 state (A,B,E,F) from the second operand, and a pre-computed sum of the
next 2 round message dwords and the corresponding round constants from the implicit operand xmm0. Note that
only the two lower dwords of XMM0 are used by the instruction.
The updated SHA256 state (A,B,E,F) is written to the first operand, and the second operand can be used as the
updated state (C,D,G,H) in later rounds.

Operation
SHA256RNDS2

A_0 <- SRC2[127:96];
B_0 <- SRC2[95:64];
C_0 <- SRC1[127:96];
D_0 <- SRC1[95:64];
E_0 <- SRC2[63:32];
F_0 <- SRC2[31:0];
G_0 <- SRC1[63:32];
H_0 <- SRC1[31:0];
WK0 <- XMM0[31: 0];
WK1 <- XMM0[63: 32];

FOR i = 0 to 1
   A_(i +1) <- Ch (E_i, F_i, G_i) +o1( E_i) +WKi+ H_i + Maj(A_i , B_i, C_i) +o0( A_i);
   B_(i +1) <- A_i;
   C_(i +1) <- B_i ;
   D_(i +1) <- C_i;
   E_(i +1) <- Ch (E_i, F_i, G_i) +o1( E_i) +WKi+ H_i + D_i;
   F_(i +1) <- E_i ;
   G_(i +1) <- F_i;
   H_(i +1) <- G_i;
ENDFOR

DEST[127:96] <- A_2;
DEST[95:64] <- B_2;
DEST[63:32] <- E_2;
DEST[31:0] <- F_2;



Intel C/C++ Compiler Intrinsic Equivalent
SHA256RNDS2: __m128i _mm_sha256rnds2_epu32(__m128i, __m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA256MSG1
description:
SHA256MSG1-Perform an Intermediate Calculation for the Next Four SHA256 Message
Dwords
 Opcode/                          Op/En     64/32       CPUID       Description
 Instruction                                bit Mode    Feature
                                            Support     Flag
 0F 38 CC /r                      RM        V/V         SHA         Performs an intermediate calculation for the next four SHA256
 SHA256MSG1 xmm1,                                                   message dwords using previous message dwords from xmm1 and
 xmm2/m128                                                          xmm2/m128, storing the result in xmm1.



                                                 Instruction Operand Encoding
     Op/En                    Operand 1                              Operand 2                            Operand 3
       RM                  ModRM:reg (r, w)                        ModRM:r/m (r)                              NA

Description
The SHA256MSG1 instruction is one of two SHA256 message scheduling instructions. The instruction performs an
intermediate calculation for the next four SHA256 message dwords.

Operation
SHA256MSG1

W4 <- SRC2[31: 0] ;
W3 <- SRC1[127:96] ;
W2 <- SRC1[95:64] ;
W1 <- SRC1[63: 32] ;
W0 <- SRC1[31: 0] ;

DEST[127:96] <- W3 + o0( W4);
DEST[95:64] <- W2 + o0( W3);
DEST[63:32] <- W1 + o0( W2);
DEST[31:0] <- W0 + o0( W1);

Intel C/C++ Compiler Intrinsic Equivalent
SHA256MSG1: __m128i _mm_sha256msg1_epu32(__m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHA256MSG2
description:
SHA256MSG2-Perform a Final Calculation for the Next Four SHA256 Message Dwords
 Opcode/                         Op/En      64/32      CPUID      Description
 Instruction                                bit Mode   Feature
                                            Support    Flag
 0F 38 CD /r                     RM         V/V        SHA        Performs the final calculation for the next four SHA256 message
 SHA256MSG2 xmm1,                                                 dwords using previous message dwords from xmm1 and
 xmm2/m128                                                        xmm2/m128, storing the result in xmm1.



                                                 Instruction Operand Encoding
     Op/En                    Operand 1                             Operand 2                              Operand 3
       RM                  ModRM:reg (r, w)                       ModRM:r/m (r)                                NA

Description
The SHA256MSG2 instruction is one of two SHA2 message scheduling instructions. The instruction performs the
final calculation for the next four SHA256 message dwords.

Operation
SHA256MSG2

W14 <- SRC2[95:64] ;
W15 <- SRC2[127:96] ;
W16 <- SRC1[31: 0] + o1( W14) ;
W17 <- SRC1[63: 32] + o1( W15) ;
W18 <- SRC1[95: 64] + o1( W16) ;
W19 <- SRC1[127: 96] + o1( W17) ;

DEST[127:96] <- W19 ;
DEST[95:64] <- W18 ;
DEST[63:32] <- W17 ;
DEST[31:0] <- W16;

Intel C/C++ Compiler Intrinsic Equivalent
SHA256MSG2 : __m128i _mm_sha256msg2_epu32(__m128i, __m128i);

Flags Affected
None

SIMD Floating-Point Exceptions

None

Other Exceptions
See Exceptions Type 4.






platform: x86_64
mnem: SHLD
description:
SHLD-Double Precision Shift Left
 Opcode*                    Instruction                  Op/   64-Bit   Compat/ Description
                                                         En    Mode     Leg Mode
 0F A4 /r ib                SHLD r/m16, r16, imm8        MRI   Valid    Valid       Shift r/m16 to left imm8 places while shifting
                                                                                    bits from r16 in from the right.
 0F A5 /r                   SHLD r/m16, r16, CL          MRC Valid      Valid       Shift r/m16 to left CL places while shifting bits
                                                                                    from r16 in from the right.
 0F A4 /r ib                SHLD r/m32, r32, imm8        MRI   Valid    Valid       Shift r/m32 to left imm8 places while shifting
                                                                                    bits from r32 in from the right.
 REX.W + 0F A4 /r ib        SHLD r/m64, r64, imm8        MRI   Valid    N.E.        Shift r/m64 to left imm8 places while shifting
                                                                                    bits from r64 in from the right.
 0F A5 /r                   SHLD r/m32, r32, CL          MRC Valid      Valid       Shift r/m32 to left CL places while shifting bits
                                                                                    from r32 in from the right.
 REX.W + 0F A5 /r           SHLD r/m64, r64, CL          MRC Valid      N.E.        Shift r/m64 to left CL places while shifting
                                                                                    bits from r64 in from the right.



                                                  Instruction Operand Encoding
    Op/En               Operand 1                    Operand 2                  Operand 3                      Operand 4
     MRI             ModRM:r/m (w)                  ModRM:reg (r)                 imm8                             NA
    MRC              ModRM:r/m (w)                  ModRM:reg (r)                  CL                              NA


Description
The SHLD instruction is used for multi-precision shifts of 64 bits or more.
The instruction shifts the first operand (destination operand) to the left the number of bits specified by the third
operand (count operand). The second operand (source operand) provides bits to shift in from the right (starting
with bit 0 of the destination operand).
The destination operand can be a register or a memory location; the source operand is a register. The count
operand is an unsigned integer that can be stored in an immediate byte or in the CL register. If the count operand
is CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode; only
bits 0 through 4 of the count are used. This masks the count to a value between 0 and 31. If a count is greater than
the operand size, the result is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit
shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not
affected.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits
(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and
limits.

Operation
IF (In 64-Bit Mode and REX.W = 1)
     THEN COUNT <- COUNT MOD 64;
     ELSE COUNT <- COUNT MOD 32;
FI
SIZE <- OperandSize;
IF COUNT = 0
     THEN
         No operation;
     ELSE



        IF COUNT > SIZE
             THEN (* Bad parameters *)
                 DEST is undefined;
                 CF, OF, SF, ZF, AF, PF are undefined;
             ELSE (* Perform the shift *)
                 CF <- BIT[DEST, SIZE - COUNT];
                 (* Last bit shifted out on exit *)
                 FOR i <- SIZE - 1 DOWN TO COUNT
                      DO
                            Bit(DEST, i) <- Bit(DEST, i - COUNT);
                      OD;
                 FOR i <- COUNT - 1 DOWN TO 0
                      DO
                            BIT[DEST, i] <- BIT[SRC, i - COUNT + SIZE];
                      OD;
        FI;
FI;

Flags Affected
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF, ZF,
and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change occurred;
otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag is unde-
fined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the flags
are undefined.

Protected Mode Exceptions
#GP(0)                  If the destination is located in a non-writable segment.
                        If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                        If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made while the
                        current privilege level is 3.
#UD                     If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                     If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                     If a memory operand effective address is outside the SS segment limit.
#UD                     If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                  If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                  If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)         If a page fault occurs.
#AC(0)                  If alignment checking is enabled and an unaligned memory reference is made.
#UD                     If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#SS(0)                   If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)                   If the memory address is in a non-canonical form.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.
#UD                      If the LOCK prefix is used.






platform: x86_64
mnem: SHRD
description:
SHRD-Double Precision Shift Right
 Opcode*                   Instruction                Op/      64-Bit   Compat/ Description
                                                      En       Mode     Leg Mode
 0F AC /r ib               SHRD r/m16, r16, imm8      MRI      Valid    Valid       Shift r/m16 to right imm8 places while
                                                                                    shifting bits from r16 in from the left.
 0F AD /r                  SHRD r/m16, r16, CL        MRC Valid         Valid       Shift r/m16 to right CL places while shifting
                                                                                    bits from r16 in from the left.
 0F AC /r ib               SHRD r/m32, r32, imm8      MRI      Valid    Valid       Shift r/m32 to right imm8 places while
                                                                                    shifting bits from r32 in from the left.
 REX.W + 0F AC /r ib       SHRD r/m64, r64, imm8      MRI      Valid    N.E.        Shift r/m64 to right imm8 places while
                                                                                    shifting bits from r64 in from the left.
 0F AD /r                  SHRD r/m32, r32, CL        MRC Valid         Valid       Shift r/m32 to right CL places while shifting
                                                                                    bits from r32 in from the left.
 REX.W + 0F AD /r          SHRD r/m64, r64, CL        MRC Valid         N.E.        Shift r/m64 to right CL places while shifting
                                                                                    bits from r64 in from the left.



                                                 Instruction Operand Encoding
   Op/En               Operand 1                   Operand 2                    Operand 3                     Operand 4
    MRI             ModRM:r/m (w)                ModRM:reg (r)                    imm8                            NA
    MRC             ModRM:r/m (w)                ModRM:reg (r)                     CL                             NA


Description
The SHRD instruction is useful for multi-precision shifts of 64 bits or more.
The instruction shifts the first operand (destination operand) to the right the number of bits specified by the third
operand (count operand). The second operand (source operand) provides bits to shift in from the left (starting with
the most significant bit of the destination operand).
The destination operand can be a register or a memory location; the source operand is a register. The count
operand is an unsigned integer that can be stored in an immediate byte or the CL register. If the count operand is
CL, the shift count is the logical AND of CL and a count mask. In non-64-bit modes and default 64-bit mode, the
width of the count mask is 5 bits. Only bits 0 through 4 of the count register are used (masking the count to a value
between 0 and 31). If the count is greater than the operand size, the result is undefined.
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand. For a 1-bit
shift, the OF flag is set if a sign change occurred; otherwise, it is cleared. If the count operand is 0, flags are not
affected.
In 64-bit mode, the instruction's default operation size is 32 bits. Using a REX prefix in the form of REX.R permits
access to additional registers (R8-R15). Using a REX prefix in the form of REX.W promotes operation to 64 bits
(upgrading the count mask to 6 bits). See the summary chart at the beginning of this section for encoding data and
limits.

Operation
IF (In 64-Bit Mode and REX.W = 1)
     THEN COUNT <- COUNT MOD 64;
     ELSE COUNT <- COUNT MOD 32;
FI
SIZE <- OperandSize;
IF COUNT = 0
     THEN
         No operation;
     ELSE



        IF COUNT > SIZE
             THEN (* Bad parameters *)
                 DEST is undefined;
                 CF, OF, SF, ZF, AF, PF are undefined;
             ELSE (* Perform the shift *)
                 CF <- BIT[DEST, COUNT - 1]; (* Last bit shifted out on exit *)
                 FOR i <- 0 TO SIZE - 1 - COUNT
                      DO
                           BIT[DEST, i] <- BIT[DEST, i + COUNT];
                      OD;
                 FOR i <- SIZE - COUNT TO SIZE - 1
                      DO
                           BIT[DEST,i] <- BIT[SRC, i + COUNT - SIZE];
                      OD;
        FI;
FI;

Flags Affected
If the count is 1 or greater, the CF flag is filled with the last bit shifted out of the destination operand and the SF,
ZF, and PF flags are set according to the value of the result. For a 1-bit shift, the OF flag is set if a sign change
occurred; otherwise, it is cleared. For shifts greater than 1 bit, the OF flag is undefined. If a shift occurs, the AF flag
is undefined. If the count operand is 0, the flags are not affected. If the count is greater than the operand size, the
flags are undefined.

Protected Mode Exceptions
#GP(0)                   If the destination is located in a non-writable segment.
                         If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
                         If the DS, ES, FS, or GS register contains a NULL segment selector.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made while the
                         current privilege level is 3.
#UD                      If the LOCK prefix is used.

Real-Address Mode Exceptions
#GP                      If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS                      If a memory operand effective address is outside the SS segment limit.
#UD                      If the LOCK prefix is used.

Virtual-8086 Mode Exceptions
#GP(0)                   If a memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.
#SS(0)                   If a memory operand effective address is outside the SS segment limit.
#PF(fault-code)          If a page fault occurs.
#AC(0)                   If alignment checking is enabled and an unaligned memory reference is made.
#UD                      If the LOCK prefix is used.

Compatibility Mode Exceptions
Same exceptions as in protected mode.





64-Bit Mode Exceptions
#SS(0)              If a memory address referencing the SS segment is in a non-canonical form.
#GP(0)              If the memory address is in a non-canonical form.
#PF(fault-code)     If a page fault occurs.
#AC(0)              If alignment checking is enabled and an unaligned memory reference is made while the
                    current privilege level is 3.
#UD                 If the LOCK prefix is used.






platform: x86_64
mnem: SHUFPD
description:
SHUFPD-Packed Interleave Shuffle of Pairs of Double-Precision Floating-Point Values
 Opcode/                                        Op /     64/32         CPUID          Description
 Instruction                                    En       bit Mode      Feature
                                                         Support       Flag
 66 0F C6 /r ib                                 RMI      V/V           SSE2           Shuffle two pairs of double-precision floating-point
 SHUFPD xmm1, xmm2/m128, imm8                                                         values from xmm1 and xmm2/m128 using imm8 to
                                                                                      select from each pair, interleaved result is stored in
                                                                                      xmm1.
 VEX.NDS.128.66.0F.WIG C6 /r ib                 RVMI     V/V           AVX            Shuffle two pairs of double-precision floating-point
 VSHUFPD xmm1, xmm2, xmm3/m128,                                                       values from xmm2 and xmm3/m128 using imm8 to
 imm8                                                                                 select from each pair, interleaved result is stored in
                                                                                      xmm1.
 VEX.NDS.256.66.0F.WIG C6 /r ib                 RVMI     V/V           AVX            Shuffle four pairs of double-precision floating-point
 VSHUFPD ymm1, ymm2, ymm3/m256,                                                       values from ymm2 and ymm3/m256 using imm8 to
 imm8                                                                                 select from each pair, interleaved result is stored in
                                                                                      xmm1.
 EVEX.NDS.128.66.0F.W1 C6 /r ib                 FV       V/V           AVX512VL       Shuffle two paris of double-precision floating-point
 VSHUFPD xmm1{k1}{z}, xmm2,                                            AVX512F        values from xmm2 and xmm3/m128/m64bcst using
 xmm3/m128/m64bcst, imm8                                                              imm8 to select from each pair. store interleaved
                                                                                      results in xmm1 subject to writemask k1.
 EVEX.NDS.256.66.0F.W1 C6 /r ib                 FV       V/V           AVX512VL       Shuffle four paris of double-precision floating-point
 VSHUFPD ymm1{k1}{z}, ymm2,                                            AVX512F        values from ymm2 and ymm3/m256/m64bcst using
 ymm3/m256/m64bcst, imm8                                                              imm8 to select from each pair. store interleaved
                                                                                      results in ymm1 subject to writemask k1.
 EVEX.NDS.512.66.0F.W1 C6 /r ib                 FV       V/V           AVX512F        Shuffle eight paris of double-precision floating-point
 VSHUFPD zmm1{k1}{z}, zmm2,                                                           values from zmm2 and zmm3/m512/m64bcst using
 zmm3/m512/m64bcst, imm8                                                              imm8 to select from each pair. store interleaved
                                                                                      results in zmm1 subject to writemask k1.



                                                       Instruction Operand Encoding
        Op/En                    Operand 1                      Operand 2                    Operand 3                    Operand 4
          RMI                ModRM:reg (r, w)                ModRM:r/m (r)                     Imm8                           NA
         RVMI                 ModRM:reg (w)                    VEX.vvvv (r)                ModRM:r/m (r)                     Imm8
          FV                  ModRM:reg (w)                    EVEX.vvvv (r)               ModRM:r/m (r)                     Imm8

Description
Selects a double-precision floating-point value of an input pair using a bit control and move to a designated
element of the destination operand. The low-to-high order of double-precision element of the destination operand
is interleaved between the first source operand and the second source operand at the granularity of input pair of
128 bits. Each bit in the imm8 byte, starting from bit 0, is the select control of the corresponding element of the
destination to received the shuffled result of an input pair.
EVEX encoded versions: The first source operand is a ZMM/YMM/XMM register. The second source operand can be
a ZMM/YMM/XMM register, a 512/256/128-bit memory location or a 512/256/128-bit vector broadcasted from a
64-bit memory location The destination operand is a ZMM/YMM/XMM register updated according to the writemask.
The select controls are the lower 8/4/2 bits of the imm8 byte.
VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM
register or a 256-bit memory location. The destination operand is a YMM register. The select controls are the bit 3:0
of the imm8 byte, imm8[7:4) are ignored.
VEX.128 encoded version: The first source operand is a XMM register. The second source operand can be a XMM
register or a 128-bit memory location. The destination operand is a XMM register. The upper bits (MAX_VL-1:128)
of the corresponding ZMM register destination are zeroed. The select controls are the bit 1:0 of the imm8 byte,
imm8[7:2) are ignored.




128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-
nation operand and the first source operand is the same and is an XMM register. The upper bits (MAX_VL-1:128) of
the corresponding ZMM register destination are unmodified. The select controls are the bit 1:0 of the imm8 byte,
imm8[7:2) are ignored.




                    SRC1         X3               X2                   X1                   X0



                    SRC2         Y3               Y2                   Y1                   Y0



                    DEST      Y2 or Y3         X2 or X3             Y0 or Y1             X0 or X1



                      Figure 4-25. 256-bit VSHUFPD Operation of Four Pairs of DP FP Values


Operation
VSHUFPD (EVEX encoded versions when SRC2 is a vector register)
(KL, VL) = (2, 128), (4, 256), (8, 512)
IF IMM0[0] = 0
    THEN TMP_DEST[63:0] <- SRC1[63:0]
    ELSE TMP_DEST[63:0] <- SRC1[127:64] FI;
IF IMM0[1] = 0
    THEN TMP_DEST[127:64] <- SRC2[63:0]
    ELSE TMP_DEST[127:64] <- SRC2[127:64] FI;
IF VL >= 256
    IF IMM0[2] = 0
         THEN TMP_DEST[191:128] <- SRC1[191:128]
         ELSE TMP_DEST[191:128] <- SRC1[255:192] FI;
    IF IMM0[3] = 0
         THEN TMP_DEST[255:192] <- SRC2[191:128]
         ELSE TMP_DEST[255:192] <- SRC2[255:192] FI;
FI;
IF VL >= 512
    IF IMM0[4] = 0
         THEN TMP_DEST[319:256] <- SRC1[319:256]
         ELSE TMP_DEST[319:256] <- SRC1[383:320] FI;
    IF IMM0[5] = 0
         THEN TMP_DEST[383:320] <- SRC2[319:256]
         ELSE TMP_DEST[383:320] <- SRC2[383:320] FI;
    IF IMM0[6] = 0
         THEN TMP_DEST[447:384] <- SRC1[447:384]
         ELSE TMP_DEST[447:384] <- SRC1[511:448] FI;
    IF IMM0[7] = 0
         THEN TMP_DEST[511:448] <- SRC2[447:384]
         ELSE TMP_DEST[511:448] <- SRC2[511:448] FI;
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE



              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*
                   ELSE *zeroing-masking*              ; zeroing-masking
                       DEST[i+63:i] <- 0
              FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSHUFPD (EVEX encoded versions when SRC2 is memory)
(KL, VL) = (2, 128), (4, 256), (8, 512)

FOR j <- 0 TO KL-1
    i <- j * 64
    IF (EVEX.b = 1)
         THEN TMP_SRC2[i+63:i] <- SRC2[63:0]
         ELSE TMP_SRC2[i+63:i] <- SRC2[i+63:i]
    FI;
ENDFOR;
IF IMM0[0] = 0
    THEN TMP_DEST[63:0] <- SRC1[63:0]
    ELSE TMP_DEST[63:0] <- SRC1[127:64] FI;
IF IMM0[1] = 0
    THEN TMP_DEST[127:64] <- TMP_SRC2[63:0]
    ELSE TMP_DEST[127:64] <- TMP_SRC2[127:64] FI;
IF VL >= 256
    IF IMM0[2] = 0
         THEN TMP_DEST[191:128] <- SRC1[191:128]
         ELSE TMP_DEST[191:128] <- SRC1[255:192] FI;
    IF IMM0[3] = 0
         THEN TMP_DEST[255:192] <- TMP_SRC2[191:128]
         ELSE TMP_DEST[255:192] <- TMP_SRC2[255:192] FI;
FI;
IF VL >= 512
    IF IMM0[4] = 0
         THEN TMP_DEST[319:256] <- SRC1[319:256]
         ELSE TMP_DEST[319:256] <- SRC1[383:320] FI;
    IF IMM0[5] = 0
         THEN TMP_DEST[383:320] <- TMP_SRC2[319:256]
         ELSE TMP_DEST[383:320] <- TMP_SRC2[383:320] FI;
    IF IMM0[6] = 0
         THEN TMP_DEST[447:384] <- SRC1[447:384]
         ELSE TMP_DEST[447:384] <- SRC1[511:448] FI;
    IF IMM0[7] = 0
         THEN TMP_DEST[511:448] <- TMP_SRC2[447:384]
         ELSE TMP_DEST[511:448] <- TMP_SRC2[511:448] FI;
FI;
FOR j <- 0 TO KL-1
    i <- j * 64
    IF k1[j] OR *no writemask*
         THEN DEST[i+63:i] <- TMP_DEST[i+63:i]
         ELSE
              IF *merging-masking*                ; merging-masking
                   THEN *DEST[i+63:i] remains unchanged*



                 ELSE *zeroing-masking*         ; zeroing-masking
                     DEST[i+63:i] <- 0
          FI
   FI;
ENDFOR
DEST[MAX_VL-1:VL] <- 0

VSHUFPD (VEX.256 encoded version)
IF IMM0[0] = 0
    THEN DEST[63:0] <-SRC1[63:0]
    ELSE DEST[63:0] <-SRC1[127:64] FI;
IF IMM0[1] = 0
    THEN DEST[127:64] <-SRC2[63:0]
    ELSE DEST[127:64] <-SRC2[127:64] FI;
IF IMM0[2] = 0
    THEN DEST[191:128] <-SRC1[191:128]
    ELSE DEST[191:128] <-SRC1[255:192] FI;
IF IMM0[3] = 0
    THEN DEST[255:192] <-SRC2[191:128]
    ELSE DEST[255:192] <-SRC2[255:192] FI;
DEST[MAX_VL-1:256] (Unmodified)

VSHUFPD (VEX.128 encoded version)
IF IMM0[0] = 0
    THEN DEST[63:0] <-SRC1[63:0]
    ELSE DEST[63:0] <-SRC1[127:64] FI;
IF IMM0[1] = 0
    THEN DEST[127:64] <-SRC2[63:0]
    ELSE DEST[127:64] <-SRC2[127:64] FI;
DEST[MAX_VL-1:128] <-0

VSHUFPD (128-bit Legacy SSE version)
IF IMM0[0] = 0
    THEN DEST[63:0] <-SRC1[63:0]
    ELSE DEST[63:0] <-SRC1[127:64] FI;
IF IMM0[1] = 0
    THEN DEST[127:64] <-SRC2[63:0]
    ELSE DEST[127:64] <-SRC2[127:64] FI;
DEST[MAX_VL-1:128] (Unmodified)

Intel C/C++ Compiler Intrinsic Equivalent
VSHUFPD __m512d _mm512_shuffle_pd(__m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_mask_shuffle_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFPD __m512d _mm512_maskz_shuffle_pd( __mmask8 k, __m512d a, __m512d b, int imm);
VSHUFPD __m256d _mm256_shuffle_pd (__m256d a, __m256d b, const int select);
VSHUFPD __m256d _mm256_mask_shuffle_pd(__m256d s, __mmask8 k, __m256d a, __m256d b, int imm);
VSHUFPD __m256d _mm256_maskz_shuffle_pd( __mmask8 k, __m256d a, __m256d b, int imm);
SHUFPD __m128d _mm_shuffle_pd (__m128d a, __m128d b, const int select);
VSHUFPD __m128d _mm_mask_shuffle_pd(__m128d s, __mmask8 k, __m128d a, __m128d b, int imm);
VSHUFPD __m128d _mm_maskz_shuffle_pd( __mmask8 k, __m128d a, __m128d b, int imm);





SIMD Floating-Point Exceptions
None

Other Exceptions
Non-EVEX-encoded instruction, see Exceptions Type 4.
EVEX-encoded instruction, see Exceptions Type E4NF.






