The Memory component implements a simple Memory Bank. Memory is an array of bytes. The A (address) input selects a memory location that is output on the R output. The component can be configured for 8-, 16-, or 32-bit memory.

In the 16-bit configuration, all accesses are considered to be multiples of two and retrieve two bytes. Addresses with the lower bit set are considered erroneous.

In the 32-bit configuration, all accesses are considered to be multiples of four and retrieve four bytes. Addresses with any of the lower two bits set are considered erroneous.

Memory is retrieved in little-endian mode (first byte is the least significant byte). Erroneous addresses are indicated by an X next to the A input on the component.

A rising edge on the clock input writes the memory component with the value on the W (write) input.

Memory can be specified in the component dialog box as a sequence of Hexadecimal byte values:

12 34 a8 93 b7 00 12 9a

Spaces and new-lines are ignored. Addresses can optionally be included at the beginning of lines:

0000: 12 34 a8 93 b7 00 12 9a
0008: 18 b7

The clock input will always write memory on the clock leading edge. The memory component does not have a write enable input. However, it is easy to make one by using an AND gate: