type DiscriminatedUnion<K extends PropertyKey, T extends object> = {
    [P in keyof T]: {
        [Q in K]: P;
    } & T[P] extends infer U ? {
        [Q in keyof U]: U[Q];
    } : never;
}[keyof T];
export type Operation = "ANDITOCCR" | "ANDITOSR" | "EORITOCCR" | "EORITOSR" | "ORITOCCR" | "ORITOSR" | "MOVEP" | "BTST" | "BCHG" | "BCLR" | "BSET" | "RTM" | "CALLM" | "ADDI" | "SUBI" | "ANDI" | "ORI" | "CMP2" | "CHK2" | "EORI" | "CMPI" | "MOVES" | "MOVE" | "MOVEA" | "BGND" | "ILLEGAL" | "NOP" | "RESET" | "RTD" | "RTE" | "RTR" | "RTS" | "STOP" | "TRAPV" | "MOVEC" | "SWAP" | "BKPT" | "EXTW" | "EXTL" | "EXTBL" | "LEA" | "LINK" | "UNLK" | "TRAP" | "DIVSL" | "DIVSLL" | "DIVUL" | "DIVULL" | "JMP" | "JSR" | "MULS" | "MULU" | "NBCD" | "MOVEFROMSR" | "MOVETOSR" | "MOVETOUSP" | "MOVEFROMUSP" | "MOVEFROMCCR" | "MOVETOCCR" | "PEA" | "TAS" | "MOVEM" | "CLR" | "NEG" | "NEGX" | "NOT" | "TST" | "CHK" | "DBCC" | "ADDQ" | "SUBQ" | "TRAPCC" | "SCC" | "BRA" | "BSR" | "BCC" | "MOVEQ" | "PACK" | "UNPK" | "SBCD" | "DIVS" | "DIVU" | "OR" | "SUBX" | "SUB" | "SUBA" | "CMPA" | "CMPM" | "CMP" | "EOR" | "ABCD" | "EXG" | "AND" | "ADDX" | "ADD" | "ADDA" | "BFCHG" | "BFCLR" | "BFEXTS" | "BFEXTU" | "BFFFO" | "BFINS" | "BFSET" | "BFTST" | "ASL" | "ASR" | "LSL" | "LSR" | "ROXL" | "ROXR" | "ROL" | "ROR" | "FMOVECR" | "FABS" | "FSABS" | "FDABS" | "FACOS" | "FADD" | "FSADD" | "FDADD" | "FASIN" | "FATAN" | "FATANH" | "FNOP" | "FBCC" | "FCMP" | "FCOS" | "FCOSH" | "FDBCC" | "FDIV" | "FSDIV" | "FDDIV" | "FETOX" | "FETOXM1" | "FGETEXP" | "FGETMAN" | "FINT" | "FINTRZ" | "FLOG10" | "FLOG2" | "FLOGN" | "FLOGNP1" | "FMOD" | "FMOVE" | "FSMOVE" | "FDMOVE" | "FMOVEM" | "FMUL" | "FSMUL" | "FDMUL" | "FNEG" | "FSNEG" | "FDNEG" | "FREM" | "FSCALE" | "FTRAPCC" | "FSCC" | "FSGLDIV" | "FSGLMUL" | "FSIN" | "FSINCOS" | "FSINH" | "FSQRT" | "FSSQRT" | "FDSQRT" | "FSUB" | "FSSUB" | "FDSUB" | "FTAN" | "FTANH" | "FTENTOX" | "FTST" | "FTWOTOX";
export type MemoryIndirection = "Indirect" | "IndirectPreIndexed" | "IndirectPostIndexed";
export type Indexer = DiscriminatedUnion<"kind", {
    DR: {
        reg: number;
        scale: number;
    };
    AR: {
        reg: number;
        scale: number;
    };
}>;
export declare const DRIndexer: (reg: number, scale: number) => Indexer;
export declare const ARIndexer: (reg: number, scale: number) => Indexer;
export interface Displacement {
    baseDisplacement: number;
    outerDisplacement: number;
    indexer: Indexer | null;
    indirection: MemoryIndirection | null;
}
export type Operand = DiscriminatedUnion<"kind", {
    Implied: {};
    IMM8: {
        value: number;
    };
    IMM16: {
        value: number;
    };
    IMM32: {
        value: number;
    };
    ABS16: {
        value: number;
    };
    ABS32: {
        value: number;
    };
    DR: {
        reg: number;
    };
    AR: {
        reg: number;
    };
    FR: {
        reg: number;
    };
    ARIND: {
        reg: number;
    };
    ARINC: {
        reg: number;
    };
    ARDEC: {
        reg: number;
    };
    ARDISP: {
        reg: number;
        disp: Displacement;
    };
    PCDISP: {
        offset: number;
        disp: Displacement;
    };
    DISP: {
        disp: Displacement;
    };
    DPAIR: {
        reg1: number;
        reg2: number;
    };
    FPAIR: {
        reg1: number;
        reg2: number;
    };
    REGLIST: {
        bitmask: number;
    };
    CONTROLREG: {
        reg: number;
    };
}>;
export declare const Implied: () => Operand;
export declare const IMM8: (value: number) => Operand;
export declare const IMM16: (value: number) => Operand;
export declare const IMM32: (value: number) => Operand;
export declare const ABS16: (value: number) => Operand;
export declare const ABS32: (value: number) => Operand;
export declare const DR: (reg: number) => Operand;
export declare const AR: (reg: number) => Operand;
export declare const FR: (reg: number) => Operand;
export declare const ARIND: (reg: number) => Operand;
export declare const ARINC: (reg: number) => Operand;
export declare const ARDEC: (reg: number) => Operand;
export declare const ARDISP: (reg: number, disp: Displacement) => Operand;
export declare const PCDISP: (offset: number, disp: Displacement) => Operand;
export declare const DISP: (disp: Displacement) => Operand;
export declare const DPAIR: (reg1: number, reg2: number) => Operand;
export declare const FPAIR: (reg1: number, reg2: number) => Operand;
export declare const REGLIST: (bitmask: number) => Operand;
export declare const CONTROLREG: (reg: number) => Operand;
export type BitfieldData = DiscriminatedUnion<"kind", {
    STATIC: {
        value: number;
    };
    DYNAMIC: {
        reg: number;
    };
}>;
export declare const STATIC: (value: number) => BitfieldData;
export declare const DYNAMIC: (reg: number) => BitfieldData;
export declare enum ConditionCode {
    CC_T = 0,
    CC_F = 1,
    CC_HI = 2,
    CC_LS = 3,
    CC_CC = 4,
    CC_CS = 5,
    CC_NE = 6,
    CC_EQ = 7,
    CC_VC = 8,
    CC_VS = 9,
    CC_PL = 10,
    CC_MI = 11,
    CC_GE = 12,
    CC_LT = 13,
    CC_GT = 14,
    CC_LE = 15
}
export declare enum FPConditionCode {
    FPCC_F = 0,
    FPCC_EQ = 1,
    FPCC_OGT = 2,
    FPCC_OGE = 3,
    FPCC_OLT = 4,
    FPCC_OLE = 5,
    FPCC_OGL = 6,
    FPCC_OR = 7,
    FPCC_UN = 8,
    FPCC_UEQ = 9,
    FPCC_UGT = 10,
    FPCC_UGE = 11,
    FPCC_ULT = 12,
    FPCC_ULE = 13,
    FPCC_NE = 14,
    FPCC_T = 15,
    FPCC_SF = 16,
    FPCC_SEQ = 17,
    FPCC_GT = 18,
    FPCC_GE = 19,
    FPCC_LT = 20,
    FPCC_LE = 21,
    FPCC_GL = 22,
    FPCC_GLE = 23,
    FPCC_NGLE = 24,
    FPCC_NGL = 25,
    FPCC_NLE = 26,
    FPCC_NLT = 27,
    FPCC_NGE = 28,
    FPCC_NGT = 29,
    FPCC_SNE = 30,
    FPCC_ST = 31
}
export type FPFormat = DiscriminatedUnion<"kind", {
    FPF_LONG_INT: {};
    FPF_SINGLE: {};
    FPF_EXTENDED_REAL: {};
    FPF_PACKED_DECIMAL_REAL_STATIC: {
        fmove: number;
    };
    FPF_PACKED_DECIMAL_REAL_DYNAMIC: {
        fmove: number;
    };
    FPF_WORD_INT: {};
    FPF_DOUBLE: {};
    FPF_BYTE_INT: {};
}>;
export declare const FPF_LONG_INT: () => FPFormat;
export declare const FPF_SINGLE: () => FPFormat;
export declare const FPF_EXTENDED_REAL: () => FPFormat;
export declare const FPF_PACKED_DECIMAL_REAL_STATIC: (fmove: number) => FPFormat;
export declare const FPF_PACKED_DECIMAL_REAL_DYNAMIC: (fmove: number) => FPFormat;
export declare const FPF_WORD_INT: () => FPFormat;
export declare const FPF_DOUBLE: () => FPFormat;
export declare const FPF_BYTE_INT: () => FPFormat;
export type InstructionExtra = DiscriminatedUnion<"kind", {
    Bitfield: {
        offset: BitfieldData;
        width: BitfieldData;
    };
    Condition: {
        code: ConditionCode;
    };
    FPCondition: {
        code: FPConditionCode;
    };
    PackAdjustment: {
        value: number;
    };
    FloatFormat: {
        format: FPFormat;
    };
}>;
export declare const Bitfield: (offset: BitfieldData, width: BitfieldData) => InstructionExtra;
export declare const Condition: (code: ConditionCode) => InstructionExtra;
export declare const FPCondition: (code: FPConditionCode) => InstructionExtra;
export declare const PackAdjustment: (value: number) => InstructionExtra;
export declare const FloatFormat: (format: FPFormat) => InstructionExtra;
export interface Instruction {
    size: number;
    operation: Operation;
    operands: [Operand | null, Operand | null];
    extra: InstructionExtra | null;
}
export interface DecodedInstruction {
    bytesUsed: number;
    instruction: Instruction;
}
export type DecodingError = "NotImplemented" | "OutOfSpace" | "BadRegister" | "BadSize" | "Reserved";
export {};