//
// Copyright (c) Microsoft Corporation. All rights reserved.
//
// Definitions specific to Intel Galileo board
//
#ifndef _INTEL_GALILEO_H_
#define _INTEL_GALILEO_H_

#define I2C_CONTROLLER_INDEX 0
#define SPI_CONTROLLER_INDEX 1
#define ADC_CONTROLLER_INDEX 0

#define ADC_NUM_CHANNELS 8
#define ADC_MAX_VALUE 0xfff

#define PWM_MAX_DUTYCYCLE 0xffff

typedef enum _GALILEO_GPIO_PIN {
	
    // Quark Legacy bridge GPIO pins (Core well)

	QRK_LEGACY_CORE_GPIO8 = 0,
	QRK_LEGACY_CORE_GPIO9,

	// Quark legacy bridge GPIO pins (Resume well)

	QRK_LEGACY_RESUME_SUS0,
	QRK_LEGACY_RESUME_SUS1,
	QRK_LEGACY_RESUME_SUS2,
	QRK_LEGACY_RESUME_SUS3,
	QRK_LEGACY_RESUME_SUS4,
	QRK_LEGACY_RESUME_SUS5,

	// Quark GPIO controller (IOFABRIC)

	QRK_IOFABRIC_GPIO_0,
	QRK_IOFABRIC_GPIO_1,
	QRK_IOFABRIC_GPIO_2,
	QRK_IOFABRIC_GPIO_3,
	QRK_IOFABRIC_GPIO_4,
	QRK_IOFABRIC_GPIO_5,
	QRK_IOFABRIC_GPIO_6,
	QRK_IOFABRIC_GPIO_7,

	// Cypruss CY8C95X0A I/O expander GPIO pins

    GPORT0_BIT0_PWM7,
	GPORT0_BIT1_PWM5,
	GPORT0_BIT2_PWM3,
	GPORT0_BIT3_PWM1,
	GPORT0_BIT4,
	GPORT0_BIT5,
	GPORT0_BIT6,
	GPORT0_BIT7,
	GPORT1_BIT0_PWM6,
	GPORT1_BIT1_PWM4,
	GPORT1_BIT2_PWM2,
	GPORT1_BIT3_PWM0,
	GPORT1_BIT4,
	GPORT1_BIT5,
	GPORT1_BIT6,
	GPORT1_BIT7,
	GPORT2_BIT0,
	GPORT2_BIT1,
	GPORT2_BIT2,
	GPORT2_BIT3,
	GPORT3_BIT0,
	GPORT3_BIT1,
	GPORT3_BIT2,
	GPORT3_BIT3,
	GPORT3_BIT4,
	GPORT3_BIT5,
	GPORT3_BIT6,
	GPORT3_BIT7,
	GPORT4_BIT0,
	GPORT4_BIT1,
	GPORT4_BIT2,
	GPORT4_BIT3,
	GPORT4_BIT4,
	GPORT4_BIT5,
	GPORT4_BIT6,
	GPORT4_BIT7,
	GPORT5_BIT0,
	GPORT5_BIT1,
	GPORT5_BIT2,
	GPORT5_BIT3,
	GALILEO_GPIO_PIN_COUNT
} GALILEO_GPIO_PIN;

const GALILEO_GPIO_PIN GALILEO_PWM_PINS[] =
{
    GPORT1_BIT3_PWM0,
    GPORT0_BIT3_PWM1,    
    GPORT1_BIT2_PWM2,
    GPORT0_BIT2_PWM3,
    GPORT1_BIT1_PWM4,
    GPORT0_BIT1_PWM5,
    GPORT1_BIT0_PWM6,
    GPORT0_BIT0_PWM7
};

#endif // _INTEL_GALILEO_H_