{
  "entity": {
    "name": "video_core",
        "description": "\n\n \n\n \n\n\n \n \n\n\n \n\n \n"
  },
  "generics": [],
  "ports": [
    {
      "name": "clk",
      "type": "std_logic",
      "line": 27,
      "direction": "in",
      "default_value": "",
      "description": " core clock, 100 Mhz",
      "group": ""
    },
    {
      "name": "reset_n",
      "type": "std_logic",
      "line": 29,
      "direction": "in",
      "default_value": "",
      "description": " asynchronous active low reset",
      "group": ""
    },
    {
      "name": "mem_addr",
      "type": "std_logic_vector(LUT_ADDR_SIZE-1  downto 0)",
      "line": 82,
      "direction": "out",
      "default_value": "",
      "description": " memory address to enable read ",
      "group": ""
    },
    {
      "name": "axi_lite_config",
      "type": "virtual_bus",
      "line": -1,
      "direction": "in",
      "default_value": "",
      "description": " an AXI4-Lite interface to write core registers",
      "group": ""
    },
    {
      "name": "video_in_axi_stream",
      "type": "virtual_bus",
      "line": -1,
      "direction": "in",
      "default_value": "",
      "description": " a slave axi stream interface for video in",
      "group": ""
    },
    {
      "name": "video_out_axi_stream",
      "type": "virtual_bus",
      "line": -1,
      "direction": "out",
      "default_value": "",
      "description": "a master axi stream interface for video out",
      "group": ""
    }
  ],
  "body": { "processes": [], "instantiations": [] },
  "declarations": { "types": [], "signals": [], "constants": [], "functions": [] },
  "info": {
    "title": "Video Core",
    "file": "example_11.vhd",
    "date": "2020-07-10",
    "copyright": " Copyright (c) 2021 by TerosHDL\n              GNU Public License\n  This program is free software: you can redistribute it and/or modify\n  it under the terms of the GNU General Public License as published by\n  the Free Software Foundation, either version 3 of the License, or\n  (at your option) any later version.\n  This program is distributed in the hope that it will be useful,\n  but WITHOUT ANY WARRANTY; without even the implied warranty of\n  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n  GNU General Public License for more details.\n  You should have received a copy of the GNU General Public License\n  along with this program.  If not, see <https://www.gnu.org/licenses/>",
    "author": "el3ctrician (elbadriahmad@gmail.com)",
    "version": "0.1",
    "brief": "Some description can be added here\n also in multi-lines",
    "details": "Another description can be added here\n And more core description can be added here\n"
},
  "virtual_buses": [
    {
      "name": "axi_lite_config",
      "description": " an AXI4-Lite interface to write core registers",
      "direction": "in",
      "keep_ports": false,
      "ports": [
        {
          "name": "s_axi_awaddr",
          "type": "std_logic_vector(AXI_LITE_ADDR_WIDTH - 1 downto 0)",
          "line": 31,
          "direction": "in",
          "default_value": "",
          "description": "\n",
          "group": ""
        },
        {
          "name": "s_axi_awprot",
          "type": "std_logic_vector(2 downto 0)",
          "line": 32,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_awvalid",
          "type": "std_logic",
          "line": 33,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_awready",
          "type": "std_logic",
          "line": 34,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_wdata",
          "type": "std_logic_vector(AXI_LITE_DATA_WIDTH - 1 downto 0)",
          "line": 35,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_wstrb",
          "type": "std_logic_vector((AXI_LITE_DATA_WIDTH/8) - 1 downto 0)",
          "line": 36,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_wvalid",
          "type": "std_logic",
          "line": 37,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_wready",
          "type": "std_logic",
          "line": 38,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_bresp",
          "type": "std_logic_vector(1 downto 0)",
          "line": 39,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_bvalid",
          "type": "std_logic",
          "line": 40,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_bready",
          "type": "std_logic",
          "line": 41,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_araddr",
          "type": "std_logic_vector(AXI_LITE_ADDR_WIDTH - 1 downto 0)",
          "line": 42,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_arprot",
          "type": "std_logic_vector(2 downto 0)",
          "line": 43,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_arvalid",
          "type": "std_logic",
          "line": 44,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_arready",
          "type": "std_logic",
          "line": 45,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_rdata",
          "type": "std_logic_vector(AXI_LITE_DATA_WIDTH - 1 downto 0)",
          "line": 46,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_rresp",
          "type": "std_logic_vector(1 downto 0)",
          "line": 47,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_rvalid",
          "type": "std_logic",
          "line": 48,
          "direction": "out",
          "default_value": "",
          "description": "",
          "group": ""
        },
        {
          "name": "s_axi_rready",
          "type": "std_logic",
          "line": 49,
          "direction": "in",
          "default_value": "",
          "description": "",
          "group": ""
        }
      ]
    },
    {
      "name": "video_in_axi_stream",
      "description": " a slave axi stream interface for video in",
      "direction": "in",
      "keep_ports": false,
      "ports": [
        {
          "name": "video_in_tdata",
          "type": "std_logic_vector(23 downto 0)",
          "line": 55,
          "direction": "in",
          "default_value": "",
          "description": "@virtualbus video_in_axi_stream @dir in a slave axi stream interface for video in axis data bus, transfers two pixels per clock with pixel width of 12 bits in mono color\n",
          "group": ""
        },
        {
          "name": "video_in_tlast",
          "type": "std_logic",
          "line": 57,
          "direction": "in",
          "default_value": "",
          "description": " axis last, used to indicate the end of packet which in video context refer to line\n",
          "group": ""
        },
        {
          "name": "video_in_tuser",
          "type": "std_logic_vector(0 downto 0)",
          "line": 59,
          "direction": "in",
          "default_value": "",
          "description": " axis user, usually is user defined but in video context it marks the start of a frame\n",
          "group": ""
        },
        {
          "name": "video_in_tvalid",
          "type": "std_logic",
          "line": 61,
          "direction": "in",
          "default_value": "",
          "description": " axis valid handshake signal\n",
          "group": ""
        },
        {
          "name": "video_in_tready",
          "type": "std_logic",
          "line": 63,
          "direction": "out",
          "default_value": "",
          "description": " axis ready handshake signal\n",
          "group": ""
        }
      ]
    },
    {
      "name": "video_out_axi_stream",
      "description": "a master axi stream interface for video out",
      "direction": "out",
      "keep_ports": true,
      "ports": [
        {
          "name": "video_out_tdata",
          "type": "std_logic_vector(23 downto 0)",
          "line": 68,
          "direction": "out",
          "default_value": "",
          "description": " axis data bus, transfers two pixels per clock with pixel width of 10 bits in mono color\n",
          "group": ""
        },
        {
          "name": "video_out_tlast",
          "type": "std_logic",
          "line": 70,
          "direction": "out",
          "default_value": "",
          "description": " axis last, used to indicate the end of packet which in video context refer to line\n",
          "group": ""
        },
        {
          "name": "video_out_tuser",
          "type": "std_logic_vector(0 downto 0)",
          "line": 72,
          "direction": "out",
          "default_value": "",
          "description": " axis user, usually is user defined but in video context it marks the start of a frame\n",
          "group": ""
        },
        {
          "name": "video_out_tvalid",
          "type": "std_logic",
          "line": 74,
          "direction": "out",
          "default_value": "",
          "description": " axis valid handshake signal\n",
          "group": ""
        },
        {
          "name": "video_out_tready",
          "type": "std_logic",
          "line": 76,
          "direction": "in",
          "default_value": "",
          "description": " axis ready handshake signal\n",
          "group": ""
        },
        {
          "name": "mem_dout",
          "type": "std_logic_vector(LUT_WORD_SIZE-1 downto 0)",
          "line": 80,
          "direction": "in",
          "default_value": "",
          "description": " @end\n data out signal, read data from memory\n",
          "group": ""
        }
      ]
    }
  ]
}